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Differential D145707

[LiveInterval] Fix live range overlap check
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Authored by chill on Mar 9 2023, 10:38 AM.

Details

Reviewers
MatzeB
Commits
rG4ac6f99ae0f5: [LiveInterval] Fix live range overlap check

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Event Timeline

chill created this revision.Mar 9 2023, 10:38 AM
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chill requested review of this revision.Mar 9 2023, 10:38 AM
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chill added a parent revision: D145706: [MachineSink] Sink instruction copies when they can replace copy into hard register.Mar 9 2023, 10:39 AM
MatzeB added a comment.Mar 9 2023, 11:36 AM

Nice catch, I would not have expected a bug in those basic datastructures!

Could you add a test to unittests/MI/LiveIntervalTest.cpp?

Harbormaster completed remote builds in B218445: Diff 503844.Mar 9 2023, 12:45 PM
chill updated this revision to Diff 509262.Mar 29 2023, 2:11 AM
chill removed a parent revision: D145706: [MachineSink] Sink instruction copies when they can replace copy into hard register.
In D145707#4182348, @MatzeB wrote:

Could you add a test to unittests/MI/LiveIntervalTest.cpp?

Done.

Harbormaster completed remote builds in B222447: Diff 509262.Mar 29 2023, 7:40 AM
chill added a child revision: D143895: [AArch64] Fix incorrect `isLegalAddressingMode`.Mar 30 2023, 6:39 AM
chill added a comment.Apr 6 2023, 7:10 AM

Ping?

MatzeB accepted this revision.Apr 6 2023, 11:20 AM

LGTM, thanks

This revision is now accepted and ready to land.Apr 6 2023, 11:20 AM
This revision was landed with ongoing or failed builds.Apr 11 2023, 3:12 AM
Closed by commit rG4ac6f99ae0f5: [LiveInterval] Fix live range overlap check (authored by chill). · Explain Why
This revision was automatically updated to reflect the committed changes.
chill added a commit: rG4ac6f99ae0f5: [LiveInterval] Fix live range overlap check.
MaskRay mentioned this in rGda5bea948df0: [bazel] Disable layering_check for llvm/unittests:mi_tests after D145707.Apr 11 2023, 2:45 PM

Revision Contents

PathSize
llvm/
lib/
CodeGen/
6 lines
test/
CodeGen/
ARM/
10 lines
BPF/
2 lines
X86/
10 lines
10 lines
88 lines
unittests/
MI/
59 lines

Diff 512383

llvm/lib/CodeGen/LiveInterval.cpp

Show First 20 Lines • Show All 439 Lines • ▼ Show 20 Lines if (I == IE)
return false; return false;
const_iterator J = Other.find(I->start); const_iterator J = Other.find(I->start);
const_iterator JE = Other.end(); const_iterator JE = Other.end();
if (J == JE) if (J == JE)
return false; return false;
while (true) { while (true) {
// J has just been advanced to satisfy: // J has just been advanced to satisfy:
assert(J->end >= I->start); assert(J->end > I->start);
// Check for an overlap. // Check for an overlap.
if (J->start < I->end) { if (J->start < I->end) {
// I and J are overlapping. Find the later start. // I and J are overlapping. Find the later start.
SlotIndex Def = std::max(I->start, J->start); SlotIndex Def = std::max(I->start, J->start);
// Allow the overlap if Def is a coalescable copy. // Allow the overlap if Def is a coalescable copy.
if (Def.isBlock() || if (Def.isBlock() ||
!CP.isCoalescable(Indexes.getInstructionFromIndex(Def))) !CP.isCoalescable(Indexes.getInstructionFromIndex(Def)))
return true; return true;
} }
// Advance the iterator that ends first to check for more overlaps. // Advance the iterator that ends first to check for more overlaps.
if (J->end > I->end) { if (J->end > I->end) {
std::swap(I, J); std::swap(I, J);
std::swap(IE, JE); std::swap(IE, JE);
} }
// Advance J until J->end >= I->start. // Advance J until J->end > I->start.
do do
if (++J == JE) if (++J == JE)
return false; return false;
while (J->end < I->start); while (J->end <= I->start);
} }
} }
/// overlaps - Return true if the live range overlaps an interval specified /// overlaps - Return true if the live range overlaps an interval specified
/// by [Start, End). /// by [Start, End).
bool LiveRange::overlaps(SlotIndex Start, SlotIndex End) const { bool LiveRange::overlaps(SlotIndex Start, SlotIndex End) const {
assert(Start < End && "Invalid range"); assert(Start < End && "Invalid range");
const_iterator I = lower_bound(*this, End); const_iterator I = lower_bound(*this, End);
▲ Show 20 Lines • Show All 934 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/neon-copy.ll

Show First 20 Lines • Show All 606 Lines • ▼ Show 20 Lines
; CHECK-NEXT: .byte 0 @ 0x0 ; CHECK-NEXT: .byte 0 @ 0x0
%vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0> %vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0>
ret <8 x i8> %vset_lane ret <8 x i8> %vset_lane
} }
define <16 x i8> @test_vcopyq_laneq_swap_s8(<16 x i8> %v1, <16 x i8> %v2) { define <16 x i8> @test_vcopyq_laneq_swap_s8(<16 x i8> %v1, <16 x i8> %v2) {
; CHECK-LABEL: test_vcopyq_laneq_swap_s8: ; CHECK-LABEL: test_vcopyq_laneq_swap_s8:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: vorr q9, q1, q1 ; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
; CHECK-NEXT: vldr d20, .LCPI53_0 ; CHECK-NEXT: vldr d16, .LCPI53_0
; CHECK-NEXT: vorr q8, q0, q0 ; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
; CHECK-NEXT: vtbl.8 d18, {d17, d18}, d20 ; CHECK-NEXT: vtbl.8 d2, {d1, d2}, d16
; CHECK-NEXT: vorr q0, q9, q9 ; CHECK-NEXT: vorr q0, q1, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .p2align 3
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI53_0: ; CHECK-NEXT: .LCPI53_0:
; CHECK-NEXT: .byte 7 @ 0x7 ; CHECK-NEXT: .byte 7 @ 0x7
; CHECK-NEXT: .byte 9 @ 0x9 ; CHECK-NEXT: .byte 9 @ 0x9
; CHECK-NEXT: .byte 10 @ 0xa ; CHECK-NEXT: .byte 10 @ 0xa
; CHECK-NEXT: .byte 11 @ 0xb ; CHECK-NEXT: .byte 11 @ 0xb
▲ Show 20 Lines • Show All 1,316 Lines • Show Last 20 Lines

llvm/test/CodeGen/BPF/sockex2.ll

Show First 20 Lines • Show All 305 Lines • ▼ Show 20 Lines; <label>:199 ; preds = %187
%201 = call i32 inttoptr (i64 2 to i32 (i8*, i8*, i8*, i64)*)(i8* bitcast (%struct.bpf_map_def* @hash_map to i8*), i8* %193, i8* %200, i64 0) #2 %201 = call i32 inttoptr (i64 2 to i32 (i8*, i8*, i8*, i64)*)(i8* bitcast (%struct.bpf_map_def* @hash_map to i8*), i8* %193, i8* %200, i64 0) #2
br label %flow_dissector.exit.thread br label %flow_dissector.exit.thread
flow_dissector.exit.thread: ; preds = %86, %12, %196, %199 flow_dissector.exit.thread: ; preds = %86, %12, %196, %199
ret i32 0 ret i32 0
; CHECK-LABEL: bpf_prog2: ; CHECK-LABEL: bpf_prog2:
; CHECK: r0 = *(u16 *)skb[12] # encoding: [0x28,0x00,0x00,0x00,0x0c,0x00,0x00,0x00] ; CHECK: r0 = *(u16 *)skb[12] # encoding: [0x28,0x00,0x00,0x00,0x0c,0x00,0x00,0x00]
; CHECK: r0 = *(u16 *)skb[16] # encoding: [0x28,0x00,0x00,0x00,0x10,0x00,0x00,0x00] ; CHECK: r0 = *(u16 *)skb[16] # encoding: [0x28,0x00,0x00,0x00,0x10,0x00,0x00,0x00]
; CHECK: implicit-def: $r1 ; CHECK: implicit-def: $r8
; CHECK: r1 = ; CHECK: r1 =
; CHECK: call 1 # encoding: [0x85,0x00,0x00,0x00,0x01,0x00,0x00,0x00] ; CHECK: call 1 # encoding: [0x85,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
; CHECK: call 2 # encoding: [0x85,0x00,0x00,0x00,0x02,0x00,0x00,0x00] ; CHECK: call 2 # encoding: [0x85,0x00,0x00,0x00,0x02,0x00,0x00,0x00]
} }
declare i64 @llvm.bpf.load.half(i8*, i64) #1 declare i64 @llvm.bpf.load.half(i8*, i64) #1
declare i64 @llvm.bpf.load.word(i8*, i64) #1 declare i64 @llvm.bpf.load.word(i8*, i64) #1
declare i64 @llvm.bpf.load.byte(i8*, i64) #1 declare i64 @llvm.bpf.load.byte(i8*, i64) #1

llvm/test/CodeGen/X86/muloti.ll

Show All 9 Lines
; CHECK-NEXT: pushq %r14 ; CHECK-NEXT: pushq %r14
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 24 ; CHECK-NEXT: .cfi_def_cfa_offset 24
; CHECK-NEXT: .cfi_offset %rbx, -24 ; CHECK-NEXT: .cfi_offset %rbx, -24
; CHECK-NEXT: .cfi_offset %r14, -16 ; CHECK-NEXT: .cfi_offset %r14, -16
; CHECK-NEXT: movq %rdx, %r11 ; CHECK-NEXT: movq %rdx, %r11
; CHECK-NEXT: movq %rdi, %r10 ; CHECK-NEXT: movq %rdi, %r10
; CHECK-NEXT: movq %rsi, %rdi ; CHECK-NEXT: movq %rsi, %rdx
; CHECK-NEXT: sarq $63, %rdi ; CHECK-NEXT: sarq $63, %rdx
; CHECK-NEXT: movq %rcx, %r8 ; CHECK-NEXT: movq %rcx, %r8
; CHECK-NEXT: imulq %rdi, %r8 ; CHECK-NEXT: imulq %rdx, %r8
; CHECK-NEXT: movq %rdx, %rax ; CHECK-NEXT: movq %r11, %rax
; CHECK-NEXT: mulq %rdi ; CHECK-NEXT: mulq %rdx
; CHECK-NEXT: movq %rdx, %rdi ; CHECK-NEXT: movq %rdx, %rdi
; CHECK-NEXT: movq %rax, %rbx ; CHECK-NEXT: movq %rax, %rbx
; CHECK-NEXT: addq %rax, %rdi ; CHECK-NEXT: addq %rax, %rdi
; CHECK-NEXT: addq %r8, %rdi ; CHECK-NEXT: addq %r8, %rdi
; CHECK-NEXT: movq %rcx, %rax ; CHECK-NEXT: movq %rcx, %rax
; CHECK-NEXT: sarq $63, %rax ; CHECK-NEXT: sarq $63, %rax
; CHECK-NEXT: movq %rax, %r14 ; CHECK-NEXT: movq %rax, %r14
; CHECK-NEXT: imulq %rsi, %r14 ; CHECK-NEXT: imulq %rsi, %r14
▲ Show 20 Lines • Show All 75 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/smulo-128-legalisation-lowering.ll

Show All 10 Lines
; X64-NEXT: .cfi_def_cfa_offset 24 ; X64-NEXT: .cfi_def_cfa_offset 24
; X64-NEXT: pushq %rbx ; X64-NEXT: pushq %rbx
; X64-NEXT: .cfi_def_cfa_offset 32 ; X64-NEXT: .cfi_def_cfa_offset 32
; X64-NEXT: .cfi_offset %rbx, -32 ; X64-NEXT: .cfi_offset %rbx, -32
; X64-NEXT: .cfi_offset %r14, -24 ; X64-NEXT: .cfi_offset %r14, -24
; X64-NEXT: .cfi_offset %r15, -16 ; X64-NEXT: .cfi_offset %r15, -16
; X64-NEXT: movq %rdx, %rbx ; X64-NEXT: movq %rdx, %rbx
; X64-NEXT: movq %rdi, %r11 ; X64-NEXT: movq %rdi, %r11
; X64-NEXT: movq %rsi, %rdi ; X64-NEXT: movq %rsi, %rdx
; X64-NEXT: sarq $63, %rdi ; X64-NEXT: sarq $63, %rdx
; X64-NEXT: movq %rcx, %r9 ; X64-NEXT: movq %rcx, %r9
; X64-NEXT: imulq %rdi, %r9 ; X64-NEXT: imulq %rdx, %r9
; X64-NEXT: movq %rdx, %rax ; X64-NEXT: movq %rbx, %rax
; X64-NEXT: mulq %rdi ; X64-NEXT: mulq %rdx
; X64-NEXT: movq %rdx, %rdi ; X64-NEXT: movq %rdx, %rdi
; X64-NEXT: movq %rax, %r14 ; X64-NEXT: movq %rax, %r14
; X64-NEXT: addq %rax, %rdi ; X64-NEXT: addq %rax, %rdi
; X64-NEXT: addq %r9, %rdi ; X64-NEXT: addq %r9, %rdi
; X64-NEXT: movq %rcx, %rax ; X64-NEXT: movq %rcx, %rax
; X64-NEXT: sarq $63, %rax ; X64-NEXT: sarq $63, %rax
; X64-NEXT: movq %rax, %r15 ; X64-NEXT: movq %rax, %r15
; X64-NEXT: imulq %rsi, %r15 ; X64-NEXT: imulq %rsi, %r15
▲ Show 20 Lines • Show All 1,465 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vec_smulo.ll

Show First 20 Lines • Show All 3,304 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pushq %r12 ; SSE2-NEXT: pushq %r12
; SSE2-NEXT: pushq %rbx ; SSE2-NEXT: pushq %rbx
; SSE2-NEXT: movq %r8, %r15 ; SSE2-NEXT: movq %r8, %r15
; SSE2-NEXT: movq %rdx, %r8 ; SSE2-NEXT: movq %rdx, %r8
; SSE2-NEXT: movq %rsi, %r11 ; SSE2-NEXT: movq %rsi, %r11
; SSE2-NEXT: movq %rdi, %r10 ; SSE2-NEXT: movq %rdi, %r10
; SSE2-NEXT: movq {{[0-9]+}}(%rsp), %rsi ; SSE2-NEXT: movq {{[0-9]+}}(%rsp), %rsi
; SSE2-NEXT: movq {{[0-9]+}}(%rsp), %rbp ; SSE2-NEXT: movq {{[0-9]+}}(%rsp), %rbp
; SSE2-NEXT: movq %r11, %rdi ; SSE2-NEXT: movq %r11, %rdx
; SSE2-NEXT: sarq $63, %rdi ; SSE2-NEXT: sarq $63, %rdx
; SSE2-NEXT: movq %r9, %rbx ; SSE2-NEXT: movq %r9, %rbx
; SSE2-NEXT: imulq %rdi, %rbx ; SSE2-NEXT: imulq %rdx, %rbx
; SSE2-NEXT: movq %r15, %rax ; SSE2-NEXT: movq %r15, %rax
; SSE2-NEXT: mulq %rdi ; SSE2-NEXT: mulq %rdx
; SSE2-NEXT: movq %rdx, %rdi ; SSE2-NEXT: movq %rdx, %rdi
; SSE2-NEXT: movq %rax, %r12 ; SSE2-NEXT: movq %rax, %r12
; SSE2-NEXT: addq %rax, %rdi ; SSE2-NEXT: addq %rax, %rdi
; SSE2-NEXT: addq %rbx, %rdi ; SSE2-NEXT: addq %rbx, %rdi
; SSE2-NEXT: movq %r9, %rax ; SSE2-NEXT: movq %r9, %rax
; SSE2-NEXT: sarq $63, %rax ; SSE2-NEXT: sarq $63, %rax
; SSE2-NEXT: movq %rax, %r13 ; SSE2-NEXT: movq %rax, %r13
; SSE2-NEXT: imulq %r11, %r13 ; SSE2-NEXT: imulq %r11, %r13
Show All 31 Lines
; SSE2-NEXT: movq {{[0-9]+}}(%rsp), %r12 ; SSE2-NEXT: movq {{[0-9]+}}(%rsp), %r12
; SSE2-NEXT: movq %r10, 8(%r12) ; SSE2-NEXT: movq %r10, 8(%r12)
; SSE2-NEXT: sarq $63, %r10 ; SSE2-NEXT: sarq $63, %r10
; SSE2-NEXT: xorq %r10, %rdx ; SSE2-NEXT: xorq %r10, %rdx
; SSE2-NEXT: xorq %rax, %r10 ; SSE2-NEXT: xorq %rax, %r10
; SSE2-NEXT: xorl %r15d, %r15d ; SSE2-NEXT: xorl %r15d, %r15d
; SSE2-NEXT: orq %rdx, %r10 ; SSE2-NEXT: orq %rdx, %r10
; SSE2-NEXT: setne %r15b ; SSE2-NEXT: setne %r15b
; SSE2-NEXT: movq %rcx, %r9 ; SSE2-NEXT: movq %rcx, %rdx
; SSE2-NEXT: sarq $63, %r9 ; SSE2-NEXT: sarq $63, %rdx
; SSE2-NEXT: movq %rbp, %r11 ; SSE2-NEXT: movq %rbp, %r11
; SSE2-NEXT: imulq %r9, %r11 ; SSE2-NEXT: imulq %rdx, %r11
; SSE2-NEXT: movq %rsi, %rax ; SSE2-NEXT: movq %rsi, %rax
; SSE2-NEXT: mulq %r9 ; SSE2-NEXT: mulq %rdx
; SSE2-NEXT: movq %rdx, %r9 ; SSE2-NEXT: movq %rdx, %r9
; SSE2-NEXT: movq %rax, %r10 ; SSE2-NEXT: movq %rax, %r10
; SSE2-NEXT: addq %rax, %r9 ; SSE2-NEXT: addq %rax, %r9
; SSE2-NEXT: addq %r11, %r9 ; SSE2-NEXT: addq %r11, %r9
; SSE2-NEXT: movq %rbp, %rax ; SSE2-NEXT: movq %rbp, %rax
; SSE2-NEXT: sarq $63, %rax ; SSE2-NEXT: sarq $63, %rax
; SSE2-NEXT: movq %rax, %r14 ; SSE2-NEXT: movq %rax, %r14
; SSE2-NEXT: imulq %rcx, %r14 ; SSE2-NEXT: imulq %rcx, %r14
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; SSSE3-NEXT: pushq %r12 ; SSSE3-NEXT: pushq %r12
; SSSE3-NEXT: pushq %rbx ; SSSE3-NEXT: pushq %rbx
; SSSE3-NEXT: movq %r8, %r15 ; SSSE3-NEXT: movq %r8, %r15
; SSSE3-NEXT: movq %rdx, %r8 ; SSSE3-NEXT: movq %rdx, %r8
; SSSE3-NEXT: movq %rsi, %r11 ; SSSE3-NEXT: movq %rsi, %r11
; SSSE3-NEXT: movq %rdi, %r10 ; SSSE3-NEXT: movq %rdi, %r10
; SSSE3-NEXT: movq {{[0-9]+}}(%rsp), %rsi ; SSSE3-NEXT: movq {{[0-9]+}}(%rsp), %rsi
; SSSE3-NEXT: movq {{[0-9]+}}(%rsp), %rbp ; SSSE3-NEXT: movq {{[0-9]+}}(%rsp), %rbp
; SSSE3-NEXT: movq %r11, %rdi ; SSSE3-NEXT: movq %r11, %rdx
; SSSE3-NEXT: sarq $63, %rdi ; SSSE3-NEXT: sarq $63, %rdx
; SSSE3-NEXT: movq %r9, %rbx ; SSSE3-NEXT: movq %r9, %rbx
; SSSE3-NEXT: imulq %rdi, %rbx ; SSSE3-NEXT: imulq %rdx, %rbx
; SSSE3-NEXT: movq %r15, %rax ; SSSE3-NEXT: movq %r15, %rax
; SSSE3-NEXT: mulq %rdi ; SSSE3-NEXT: mulq %rdx
; SSSE3-NEXT: movq %rdx, %rdi ; SSSE3-NEXT: movq %rdx, %rdi
; SSSE3-NEXT: movq %rax, %r12 ; SSSE3-NEXT: movq %rax, %r12
; SSSE3-NEXT: addq %rax, %rdi ; SSSE3-NEXT: addq %rax, %rdi
; SSSE3-NEXT: addq %rbx, %rdi ; SSSE3-NEXT: addq %rbx, %rdi
; SSSE3-NEXT: movq %r9, %rax ; SSSE3-NEXT: movq %r9, %rax
; SSSE3-NEXT: sarq $63, %rax ; SSSE3-NEXT: sarq $63, %rax
; SSSE3-NEXT: movq %rax, %r13 ; SSSE3-NEXT: movq %rax, %r13
; SSSE3-NEXT: imulq %r11, %r13 ; SSSE3-NEXT: imulq %r11, %r13
Show All 31 Lines
; SSSE3-NEXT: movq {{[0-9]+}}(%rsp), %r12 ; SSSE3-NEXT: movq {{[0-9]+}}(%rsp), %r12
; SSSE3-NEXT: movq %r10, 8(%r12) ; SSSE3-NEXT: movq %r10, 8(%r12)
; SSSE3-NEXT: sarq $63, %r10 ; SSSE3-NEXT: sarq $63, %r10
; SSSE3-NEXT: xorq %r10, %rdx ; SSSE3-NEXT: xorq %r10, %rdx
; SSSE3-NEXT: xorq %rax, %r10 ; SSSE3-NEXT: xorq %rax, %r10
; SSSE3-NEXT: xorl %r15d, %r15d ; SSSE3-NEXT: xorl %r15d, %r15d
; SSSE3-NEXT: orq %rdx, %r10 ; SSSE3-NEXT: orq %rdx, %r10
; SSSE3-NEXT: setne %r15b ; SSSE3-NEXT: setne %r15b
; SSSE3-NEXT: movq %rcx, %r9 ; SSSE3-NEXT: movq %rcx, %rdx
; SSSE3-NEXT: sarq $63, %r9 ; SSSE3-NEXT: sarq $63, %rdx
; SSSE3-NEXT: movq %rbp, %r11 ; SSSE3-NEXT: movq %rbp, %r11
; SSSE3-NEXT: imulq %r9, %r11 ; SSSE3-NEXT: imulq %rdx, %r11
; SSSE3-NEXT: movq %rsi, %rax ; SSSE3-NEXT: movq %rsi, %rax
; SSSE3-NEXT: mulq %r9 ; SSSE3-NEXT: mulq %rdx
; SSSE3-NEXT: movq %rdx, %r9 ; SSSE3-NEXT: movq %rdx, %r9
; SSSE3-NEXT: movq %rax, %r10 ; SSSE3-NEXT: movq %rax, %r10
; SSSE3-NEXT: addq %rax, %r9 ; SSSE3-NEXT: addq %rax, %r9
; SSSE3-NEXT: addq %r11, %r9 ; SSSE3-NEXT: addq %r11, %r9
; SSSE3-NEXT: movq %rbp, %rax ; SSSE3-NEXT: movq %rbp, %rax
; SSSE3-NEXT: sarq $63, %rax ; SSSE3-NEXT: sarq $63, %rax
; SSSE3-NEXT: movq %rax, %r14 ; SSSE3-NEXT: movq %rax, %r14
; SSSE3-NEXT: imulq %rcx, %r14 ; SSSE3-NEXT: imulq %rcx, %r14
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; SSE41-NEXT: pushq %r12 ; SSE41-NEXT: pushq %r12
; SSE41-NEXT: pushq %rbx ; SSE41-NEXT: pushq %rbx
; SSE41-NEXT: movq %r8, %r15 ; SSE41-NEXT: movq %r8, %r15
; SSE41-NEXT: movq %rdx, %r8 ; SSE41-NEXT: movq %rdx, %r8
; SSE41-NEXT: movq %rsi, %r11 ; SSE41-NEXT: movq %rsi, %r11
; SSE41-NEXT: movq %rdi, %r10 ; SSE41-NEXT: movq %rdi, %r10
; SSE41-NEXT: movq {{[0-9]+}}(%rsp), %rsi ; SSE41-NEXT: movq {{[0-9]+}}(%rsp), %rsi
; SSE41-NEXT: movq {{[0-9]+}}(%rsp), %rbp ; SSE41-NEXT: movq {{[0-9]+}}(%rsp), %rbp
; SSE41-NEXT: movq %r11, %rdi ; SSE41-NEXT: movq %r11, %rdx
; SSE41-NEXT: sarq $63, %rdi ; SSE41-NEXT: sarq $63, %rdx
; SSE41-NEXT: movq %r9, %rbx ; SSE41-NEXT: movq %r9, %rbx
; SSE41-NEXT: imulq %rdi, %rbx ; SSE41-NEXT: imulq %rdx, %rbx
; SSE41-NEXT: movq %r15, %rax ; SSE41-NEXT: movq %r15, %rax
; SSE41-NEXT: mulq %rdi ; SSE41-NEXT: mulq %rdx
; SSE41-NEXT: movq %rdx, %rdi ; SSE41-NEXT: movq %rdx, %rdi
; SSE41-NEXT: movq %rax, %r12 ; SSE41-NEXT: movq %rax, %r12
; SSE41-NEXT: addq %rax, %rdi ; SSE41-NEXT: addq %rax, %rdi
; SSE41-NEXT: addq %rbx, %rdi ; SSE41-NEXT: addq %rbx, %rdi
; SSE41-NEXT: movq %r9, %rax ; SSE41-NEXT: movq %r9, %rax
; SSE41-NEXT: sarq $63, %rax ; SSE41-NEXT: sarq $63, %rax
; SSE41-NEXT: movq %rax, %r13 ; SSE41-NEXT: movq %rax, %r13
; SSE41-NEXT: imulq %r11, %r13 ; SSE41-NEXT: imulq %r11, %r13
Show All 31 Lines
; SSE41-NEXT: movq {{[0-9]+}}(%rsp), %r12 ; SSE41-NEXT: movq {{[0-9]+}}(%rsp), %r12
; SSE41-NEXT: movq %r10, 8(%r12) ; SSE41-NEXT: movq %r10, 8(%r12)
; SSE41-NEXT: sarq $63, %r10 ; SSE41-NEXT: sarq $63, %r10
; SSE41-NEXT: xorq %r10, %rdx ; SSE41-NEXT: xorq %r10, %rdx
; SSE41-NEXT: xorq %rax, %r10 ; SSE41-NEXT: xorq %rax, %r10
; SSE41-NEXT: xorl %r15d, %r15d ; SSE41-NEXT: xorl %r15d, %r15d
; SSE41-NEXT: orq %rdx, %r10 ; SSE41-NEXT: orq %rdx, %r10
; SSE41-NEXT: setne %r15b ; SSE41-NEXT: setne %r15b
; SSE41-NEXT: movq %rcx, %r9 ; SSE41-NEXT: movq %rcx, %rdx
; SSE41-NEXT: sarq $63, %r9 ; SSE41-NEXT: sarq $63, %rdx
; SSE41-NEXT: movq %rbp, %r11 ; SSE41-NEXT: movq %rbp, %r11
; SSE41-NEXT: imulq %r9, %r11 ; SSE41-NEXT: imulq %rdx, %r11
; SSE41-NEXT: movq %rsi, %rax ; SSE41-NEXT: movq %rsi, %rax
; SSE41-NEXT: mulq %r9 ; SSE41-NEXT: mulq %rdx
; SSE41-NEXT: movq %rdx, %r9 ; SSE41-NEXT: movq %rdx, %r9
; SSE41-NEXT: movq %rax, %r10 ; SSE41-NEXT: movq %rax, %r10
; SSE41-NEXT: addq %rax, %r9 ; SSE41-NEXT: addq %rax, %r9
; SSE41-NEXT: addq %r11, %r9 ; SSE41-NEXT: addq %r11, %r9
; SSE41-NEXT: movq %rbp, %rax ; SSE41-NEXT: movq %rbp, %rax
; SSE41-NEXT: sarq $63, %rax ; SSE41-NEXT: sarq $63, %rax
; SSE41-NEXT: movq %rax, %r14 ; SSE41-NEXT: movq %rax, %r14
; SSE41-NEXT: imulq %rcx, %r14 ; SSE41-NEXT: imulq %rcx, %r14
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; AVX-NEXT: pushq %r12 ; AVX-NEXT: pushq %r12
; AVX-NEXT: pushq %rbx ; AVX-NEXT: pushq %rbx
; AVX-NEXT: movq %r8, %r15 ; AVX-NEXT: movq %r8, %r15
; AVX-NEXT: movq %rdx, %r8 ; AVX-NEXT: movq %rdx, %r8
; AVX-NEXT: movq %rsi, %r11 ; AVX-NEXT: movq %rsi, %r11
; AVX-NEXT: movq %rdi, %r10 ; AVX-NEXT: movq %rdi, %r10
; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rsi ; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rsi
; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rbp ; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rbp
; AVX-NEXT: movq %r11, %rdi ; AVX-NEXT: movq %r11, %rdx
; AVX-NEXT: sarq $63, %rdi ; AVX-NEXT: sarq $63, %rdx
; AVX-NEXT: movq %r9, %rbx ; AVX-NEXT: movq %r9, %rbx
; AVX-NEXT: imulq %rdi, %rbx ; AVX-NEXT: imulq %rdx, %rbx
; AVX-NEXT: movq %r15, %rax ; AVX-NEXT: movq %r15, %rax
; AVX-NEXT: mulq %rdi ; AVX-NEXT: mulq %rdx
; AVX-NEXT: movq %rdx, %rdi ; AVX-NEXT: movq %rdx, %rdi
; AVX-NEXT: movq %rax, %r12 ; AVX-NEXT: movq %rax, %r12
; AVX-NEXT: addq %rax, %rdi ; AVX-NEXT: addq %rax, %rdi
; AVX-NEXT: addq %rbx, %rdi ; AVX-NEXT: addq %rbx, %rdi
; AVX-NEXT: movq %r9, %rax ; AVX-NEXT: movq %r9, %rax
; AVX-NEXT: sarq $63, %rax ; AVX-NEXT: sarq $63, %rax
; AVX-NEXT: movq %rax, %r13 ; AVX-NEXT: movq %rax, %r13
; AVX-NEXT: imulq %r11, %r13 ; AVX-NEXT: imulq %r11, %r13
Show All 31 Lines
; AVX-NEXT: movq {{[0-9]+}}(%rsp), %r12 ; AVX-NEXT: movq {{[0-9]+}}(%rsp), %r12
; AVX-NEXT: movq %r10, 8(%r12) ; AVX-NEXT: movq %r10, 8(%r12)
; AVX-NEXT: sarq $63, %r10 ; AVX-NEXT: sarq $63, %r10
; AVX-NEXT: xorq %r10, %rdx ; AVX-NEXT: xorq %r10, %rdx
; AVX-NEXT: xorq %rax, %r10 ; AVX-NEXT: xorq %rax, %r10
; AVX-NEXT: xorl %r15d, %r15d ; AVX-NEXT: xorl %r15d, %r15d
; AVX-NEXT: orq %rdx, %r10 ; AVX-NEXT: orq %rdx, %r10
; AVX-NEXT: setne %r15b ; AVX-NEXT: setne %r15b
; AVX-NEXT: movq %rcx, %r9 ; AVX-NEXT: movq %rcx, %rdx
; AVX-NEXT: sarq $63, %r9 ; AVX-NEXT: sarq $63, %rdx
; AVX-NEXT: movq %rbp, %r11 ; AVX-NEXT: movq %rbp, %r11
; AVX-NEXT: imulq %r9, %r11 ; AVX-NEXT: imulq %rdx, %r11
; AVX-NEXT: movq %rsi, %rax ; AVX-NEXT: movq %rsi, %rax
; AVX-NEXT: mulq %r9 ; AVX-NEXT: mulq %rdx
; AVX-NEXT: movq %rdx, %r9 ; AVX-NEXT: movq %rdx, %r9
; AVX-NEXT: movq %rax, %r10 ; AVX-NEXT: movq %rax, %r10
; AVX-NEXT: addq %rax, %r9 ; AVX-NEXT: addq %rax, %r9
; AVX-NEXT: addq %r11, %r9 ; AVX-NEXT: addq %r11, %r9
; AVX-NEXT: movq %rbp, %rax ; AVX-NEXT: movq %rbp, %rax
; AVX-NEXT: sarq $63, %rax ; AVX-NEXT: sarq $63, %rax
; AVX-NEXT: movq %rax, %r14 ; AVX-NEXT: movq %rax, %r14
; AVX-NEXT: imulq %rcx, %r14 ; AVX-NEXT: imulq %rcx, %r14
▲ Show 20 Lines • Show All 110 Lines • ▼ Show 20 Lines
; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %r12 ; AVX512F-NEXT: movq {{[0-9]+}}(%rsp), %r12
; AVX512F-NEXT: movq %r10, 24(%r12) ; AVX512F-NEXT: movq %r10, 24(%r12)
; AVX512F-NEXT: sarq $63, %r10 ; AVX512F-NEXT: sarq $63, %r10
; AVX512F-NEXT: xorq %r10, %rdx ; AVX512F-NEXT: xorq %r10, %rdx
; AVX512F-NEXT: xorq %rax, %r10 ; AVX512F-NEXT: xorq %rax, %r10
; AVX512F-NEXT: orq %rdx, %r10 ; AVX512F-NEXT: orq %rdx, %r10
; AVX512F-NEXT: setne %al ; AVX512F-NEXT: setne %al
; AVX512F-NEXT: kmovw %eax, %k0 ; AVX512F-NEXT: kmovw %eax, %k0
; AVX512F-NEXT: movq %r9, %rsi ; AVX512F-NEXT: movq %r9, %rdx
; AVX512F-NEXT: sarq $63, %rsi ; AVX512F-NEXT: sarq $63, %rdx
; AVX512F-NEXT: movq %rbp, %rbx ; AVX512F-NEXT: movq %rbp, %rsi
; AVX512F-NEXT: imulq %rsi, %rbx ; AVX512F-NEXT: imulq %rdx, %rsi
; AVX512F-NEXT: movq %r8, %rax ; AVX512F-NEXT: movq %r8, %rax
; AVX512F-NEXT: mulq %rsi ; AVX512F-NEXT: mulq %rdx
; AVX512F-NEXT: movq %rdx, %r10 ; AVX512F-NEXT: movq %rdx, %r10
; AVX512F-NEXT: movq %rax, %r11 ; AVX512F-NEXT: movq %rax, %r11
; AVX512F-NEXT: addq %rax, %r10 ; AVX512F-NEXT: addq %rax, %r10
; AVX512F-NEXT: addq %rbx, %r10 ; AVX512F-NEXT: addq %rsi, %r10
; AVX512F-NEXT: movq %rbp, %rax ; AVX512F-NEXT: movq %rbp, %rax
; AVX512F-NEXT: sarq $63, %rax ; AVX512F-NEXT: sarq $63, %rax
; AVX512F-NEXT: movq %rax, %rsi ; AVX512F-NEXT: movq %rax, %rsi
; AVX512F-NEXT: imulq %r9, %rsi ; AVX512F-NEXT: imulq %r9, %rsi
; AVX512F-NEXT: mulq %rdi ; AVX512F-NEXT: mulq %rdi
; AVX512F-NEXT: movq %rax, %rbx ; AVX512F-NEXT: movq %rax, %rbx
; AVX512F-NEXT: movq %rdx, %r14 ; AVX512F-NEXT: movq %rdx, %r14
; AVX512F-NEXT: addq %rsi, %r14 ; AVX512F-NEXT: addq %rsi, %r14
▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
; AVX512BW-NEXT: movq {{[0-9]+}}(%rsp), %r12 ; AVX512BW-NEXT: movq {{[0-9]+}}(%rsp), %r12
; AVX512BW-NEXT: movq %r10, 24(%r12) ; AVX512BW-NEXT: movq %r10, 24(%r12)
; AVX512BW-NEXT: sarq $63, %r10 ; AVX512BW-NEXT: sarq $63, %r10
; AVX512BW-NEXT: xorq %r10, %rdx ; AVX512BW-NEXT: xorq %r10, %rdx
; AVX512BW-NEXT: xorq %rax, %r10 ; AVX512BW-NEXT: xorq %rax, %r10
; AVX512BW-NEXT: orq %rdx, %r10 ; AVX512BW-NEXT: orq %rdx, %r10
; AVX512BW-NEXT: setne %al ; AVX512BW-NEXT: setne %al
; AVX512BW-NEXT: kmovd %eax, %k0 ; AVX512BW-NEXT: kmovd %eax, %k0
; AVX512BW-NEXT: movq %r9, %rsi ; AVX512BW-NEXT: movq %r9, %rdx
; AVX512BW-NEXT: sarq $63, %rsi ; AVX512BW-NEXT: sarq $63, %rdx
; AVX512BW-NEXT: movq %rbp, %rbx ; AVX512BW-NEXT: movq %rbp, %rsi
; AVX512BW-NEXT: imulq %rsi, %rbx ; AVX512BW-NEXT: imulq %rdx, %rsi
; AVX512BW-NEXT: movq %r8, %rax ; AVX512BW-NEXT: movq %r8, %rax
; AVX512BW-NEXT: mulq %rsi ; AVX512BW-NEXT: mulq %rdx
; AVX512BW-NEXT: movq %rdx, %r10 ; AVX512BW-NEXT: movq %rdx, %r10
; AVX512BW-NEXT: movq %rax, %r11 ; AVX512BW-NEXT: movq %rax, %r11
; AVX512BW-NEXT: addq %rax, %r10 ; AVX512BW-NEXT: addq %rax, %r10
; AVX512BW-NEXT: addq %rbx, %r10 ; AVX512BW-NEXT: addq %rsi, %r10
; AVX512BW-NEXT: movq %rbp, %rax ; AVX512BW-NEXT: movq %rbp, %rax
; AVX512BW-NEXT: sarq $63, %rax ; AVX512BW-NEXT: sarq $63, %rax
; AVX512BW-NEXT: movq %rax, %rsi ; AVX512BW-NEXT: movq %rax, %rsi
; AVX512BW-NEXT: imulq %r9, %rsi ; AVX512BW-NEXT: imulq %r9, %rsi
; AVX512BW-NEXT: mulq %rdi ; AVX512BW-NEXT: mulq %rdi
; AVX512BW-NEXT: movq %rax, %rbx ; AVX512BW-NEXT: movq %rax, %rbx
; AVX512BW-NEXT: movq %rdx, %r14 ; AVX512BW-NEXT: movq %rdx, %r14
; AVX512BW-NEXT: addq %rsi, %r14 ; AVX512BW-NEXT: addq %rsi, %r14
▲ Show 20 Lines • Show All 55 Lines • Show Last 20 Lines

llvm/unittests/MI/LiveIntervalTest.cpp

#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/LiveIntervals.h" #include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/MIRParser/MIRParser.h" #include "llvm/CodeGen/MIRParser/MIRParser.h"
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/LegacyPassManager.h" #include "llvm/IR/LegacyPassManager.h"
#include "llvm/InitializePasses.h" #include "llvm/InitializePasses.h"
#include "llvm/MC/TargetRegistry.h" #include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/MemoryBuffer.h"
#include "llvm/Support/SourceMgr.h" #include "llvm/Support/SourceMgr.h"
#include "llvm/Support/TargetSelect.h" #include "llvm/Support/TargetSelect.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetOptions.h"
#include "gtest/gtest.h" #include "gtest/gtest.h"
#include "../lib/CodeGen/RegisterCoalescer.h"
using namespace llvm; using namespace llvm;
namespace llvm { namespace llvm {
void initializeTestPassPass(PassRegistry &); void initializeTestPassPass(PassRegistry &);
} }
namespace { namespace {
▲ Show 20 Lines • Show All 132 Lines • ▼ Show 20 Linesstatic void testSplitAt(MachineFunction &MF, LiveIntervals &LIS,
unsigned SplitAt, unsigned BlockNum) { unsigned SplitAt, unsigned BlockNum) {
MachineInstr &SplitInstr = getMI(MF, SplitAt, BlockNum); MachineInstr &SplitInstr = getMI(MF, SplitAt, BlockNum);
MachineBasicBlock &MBB = *SplitInstr.getParent(); MachineBasicBlock &MBB = *SplitInstr.getParent();
// Split block and update live intervals // Split block and update live intervals
MBB.splitAt(SplitInstr, false, &LIS); MBB.splitAt(SplitInstr, false, &LIS);
} }
/**
* Helper function to test for interference between a hard register and a
* virtual register live ranges.
*/
static bool checkRegUnitInterference(LiveIntervals &LIS,
const TargetRegisterInfo &TRI,
const LiveInterval &VirtReg,
MCRegister PhysReg) {
if (VirtReg.empty())
return false;
CoalescerPair CP(VirtReg.reg(), PhysReg, TRI);
for (MCRegUnitIterator Units(PhysReg, &TRI); Units.isValid(); ++Units) {
const LiveRange &UnitRange = LIS.getRegUnit(*Units);
if (VirtReg.overlaps(UnitRange, CP, *LIS.getSlotIndexes()))
return true;
}
return false;
}
static void liveIntervalTest(StringRef MIRFunc, LiveIntervalTest T) { static void liveIntervalTest(StringRef MIRFunc, LiveIntervalTest T) {
LLVMContext Context; LLVMContext Context;
std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine(); std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine();
// This test is designed for the X86 backend; stop if it is not available. // This test is designed for the X86 backend; stop if it is not available.
if (!TM) if (!TM)
return; return;
legacy::PassManager PM; legacy::PassManager PM;
▲ Show 20 Lines • Show All 505 Lines • ▼ Show 20 Lines SmallVector<Register> OrigRegs{
Instr1.getOperand(0).getReg(), Instr1.getOperand(0).getReg(),
Instr2.getOperand(0).getReg(), Instr2.getOperand(0).getReg(),
Instr2.getOperand(1).getReg(), Instr2.getOperand(1).getReg(),
}; };
LIS.repairIntervalsInRange(MBB, Instr2, Instr3, OrigRegs); LIS.repairIntervalsInRange(MBB, Instr2, Instr3, OrigRegs);
}); });
} }
TEST(LiveIntervalTest, AdjacentIntervals) {
liveIntervalTest(
R"MIR(
successors: %bb.1, %bb.2
$vgpr1 = IMPLICIT_DEF
S_NOP 0, implicit $vgpr1
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF
S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc
S_BRANCH %bb.1
bb.1:
$vgpr0, dead renamable $vcc = V_ADD_CO_U32_e64 %1, %2, 0, implicit $exec
S_NOP 0, implicit $vgpr0
S_BRANCH %bb.3
bb.2:
$vgpr0 = IMPLICIT_DEF
$vgpr1, dead renamable $vcc = V_ADD_CO_U32_e64 %1, %2, 0, implicit $exec
S_NOP 0, implicit $vgpr0, implicit $vgpr1
S_BRANCH %bb.3
bb.3:
)MIR",
[](MachineFunction &MF, LiveIntervals &LIS) {
const auto &R1 =
LIS.getInterval(getMI(MF, 2, 0).getOperand(0).getReg());
const auto &R2 =
LIS.getInterval(getMI(MF, 3, 0).getOperand(0).getReg());
MCRegister V1 = getMI(MF, 1, 2).getOperand(0).getReg().asMCReg();
ASSERT_FALSE(checkRegUnitInterference(
LIS, *MF.getSubtarget().getRegisterInfo(), R1, V1));
ASSERT_FALSE(checkRegUnitInterference(
LIS, *MF.getSubtarget().getRegisterInfo(), R2, V1));
});
}
int main(int argc, char **argv) { int main(int argc, char **argv) {
::testing::InitGoogleTest(&argc, argv); ::testing::InitGoogleTest(&argc, argv);
initLLVM(); initLLVM();
return RUN_ALL_TESTS(); return RUN_ALL_TESTS();
} }