[CodeGen] Define and use MachineOperand::getOperandNo

[foad]

Summary

This is a helper function to very slightly simplify many calls to
MachineInstruction::getOperandNo.

[asb]

Seems like a useful helper to me.

llvm/include/llvm/CodeGen/MachineOperand.h

public:
   /// The MachineOperand copy constructor also copies ParentMI, expecting the
   /// original to be deleted. If a MachineOperand is ever stored outside a
   /// MachineInstr, the parent pointer must be cleared.
   ///
   /// Never call clearParent() on an operand in a MachineInstr.
   ///
   void clearParent() { ParentMI = nullptr; }
 
+  /// Returns the index of this operand in the instruction that it belongs to.
+  unsigned getOperandNo() const;
+
   /// Print a subreg index operand.
   /// MO_Immediate operands can also be subreg idices. If it's the case, the
   /// subreg index name will be printed. MachineInstr::isOperandSubregIdx can be
   /// called to check this.
   static void printSubRegIdx(raw_ostream &OS, uint64_t Index,
                              const TargetRegisterInfo *TRI);
 
   /// Print operand target flags.

llvm/lib/CodeGen/CalcSpillWeights.cpp

 }
 
 bool VirtRegAuxInfo::isLiveAtStatepointVarArg(LiveInterval &LI) {
   return any_of(VRM.getRegInfo().reg_operands(LI.reg()),
                 [](MachineOperand &MO) {
     MachineInstr *MI = MO.getParent();
     if (MI->getOpcode() != TargetOpcode::STATEPOINT)
       return false;
-    return StatepointOpers(MI).getVarIdx() <= MI->getOperandNo(&MO);
+    return StatepointOpers(MI).getVarIdx() <= MO.getOperandNo();
   });
 }
 
 void VirtRegAuxInfo::calculateSpillWeightAndHint(LiveInterval &LI) {
   float Weight = weightCalcHelper(LI);
   // Check if unspillable.
   if (Weight < 0)
     return;

llvm/lib/CodeGen/DetectDeadLanes.cpp

if (DstRC == SrcRC)
     return false;
 
   unsigned SrcSubIdx = MO.getSubReg();
 
   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
   unsigned DstSubIdx = 0;
   switch (MI.getOpcode()) {
   case TargetOpcode::INSERT_SUBREG:
-    if (MI.getOperandNo(&MO) == 2)
+    if (MO.getOperandNo() == 2)
       DstSubIdx = MI.getOperand(3).getImm();
     break;
   case TargetOpcode::REG_SEQUENCE: {
-    unsigned OpNum = MI.getOperandNo(&MO);
+    unsigned OpNum = MO.getOperandNo();
     DstSubIdx = MI.getOperand(OpNum+1).getImm();
     break;
   }
   case TargetOpcode::EXTRACT_SUBREG: {
     unsigned SubReg = MI.getOperand(2).getImm();
     SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx);
   }
   }
for (const MachineOperand &MO : MI.uses()) {
     addUsedLanesOnOperand(MO, UsedOnMO);
   }
 }
 
 LaneBitmask
 DeadLaneDetector::transferUsedLanes(const MachineInstr &MI,
                                     LaneBitmask UsedLanes,
                                     const MachineOperand &MO) const {
-  unsigned OpNum = MI.getOperandNo(&MO);
+  unsigned OpNum = MO.getOperandNo();
   assert(lowersToCopies(MI) &&
          DefinedByCopy[Register::virtReg2Index(MI.getOperand(0).getReg())]);
 
   switch (MI.getOpcode()) {
   case TargetOpcode::COPY:
   case TargetOpcode::PHI:
     return UsedLanes;
   case TargetOpcode::REG_SEQUENCE: {
void DeadLaneDetector::transferDefinedLanesStep(const MachineOperand &Use,
   const MachineOperand &Def = *MI.defs().begin();
   Register DefReg = Def.getReg();
   if (!DefReg.isVirtual())
     return;
   unsigned DefRegIdx = Register::virtReg2Index(DefReg);
   if (!DefinedByCopy.test(DefRegIdx))
     return;
 
-  unsigned OpNum = MI.getOperandNo(&Use);
+  unsigned OpNum = Use.getOperandNo();
   DefinedLanes =
       TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes);
   DefinedLanes = transferDefinedLanes(Def, OpNum, DefinedLanes);
 
   VRegInfo &RegInfo = VRegInfos[DefRegIdx];
   LaneBitmask PrevDefinedLanes = RegInfo.DefinedLanes;
   // Any change at all?
   if ((DefinedLanes & ~PrevDefinedLanes).none())
for (const MachineOperand &MO : DefMI.uses()) {
             continue;
         }
         unsigned MOSubReg = MO.getSubReg();
         MODefinedLanes = MRI->getMaxLaneMaskForVReg(MOReg);
         MODefinedLanes = TRI->reverseComposeSubRegIndexLaneMask(
             MOSubReg, MODefinedLanes);
       }
 
-      unsigned OpNum = DefMI.getOperandNo(&MO);
+      unsigned OpNum = MO.getOperandNo();
       DefinedLanes |= transferDefinedLanes(Def, OpNum, MODefinedLanes);
     }
     return DefinedLanes;
   }
   if (DefMI.isImplicitDef() || Def.isDead())
     return LaneBitmask::getNone();
 
   assert(Def.getSubReg() == 0 &&

llvm/lib/CodeGen/GlobalISel/Localizer.cpp

void Localizer::getAnalysisUsage(AnalysisUsage &AU) const {
   MachineFunctionPass::getAnalysisUsage(AU);
 }
 
 bool Localizer::isLocalUse(MachineOperand &MOUse, const MachineInstr &Def,
                            MachineBasicBlock *&InsertMBB) {
   MachineInstr &MIUse = *MOUse.getParent();
   InsertMBB = MIUse.getParent();
   if (MIUse.isPHI())
-    InsertMBB = MIUse.getOperand(MIUse.getOperandNo(&MOUse) + 1).getMBB();
+    InsertMBB = MIUse.getOperand(MOUse.getOperandNo() + 1).getMBB();
   return InsertMBB == Def.getParent();
 }
 
 bool Localizer::isNonUniquePhiValue(MachineOperand &Op) const {
   MachineInstr *MI = Op.getParent();
   if (!MI->isPHI())
     return false;
 
for (MachineInstr &MI : llvm::reverse(MBB)) {
     // We are going to invalidation the list of use operands, so we
     // can't use range iterator.
     for (MachineOperand &MOUse :
          llvm::make_early_inc_range(MRI->use_operands(Reg))) {
       // Check if the use is already local.
       MachineBasicBlock *InsertMBB;
       LLVM_DEBUG(MachineInstr &MIUse = *MOUse.getParent();
                  dbgs() << "Checking use: " << MIUse
-                        << " #Opd: " << MIUse.getOperandNo(&MOUse) << '\n');
+                        << " #Opd: " << MOUse.getOperandNo() << '\n');
       if (isLocalUse(MOUse, MI, InsertMBB)) {
         // Even if we're in the same block, if the block is very large we could
         // still have many long live ranges. Try to do intra-block localization
         // too.
         LocalizedInstrs.insert(&MI);
         continue;
       }
 

llvm/lib/CodeGen/LiveVariables.cpp

void LiveVariables::recomputeForSingleDefVirtReg(Register Reg) {
   for (auto &UseMO : MRI->use_nodbg_operands(Reg)) {
     UseMO.setIsKill(false);
     MachineInstr &UseMI = *UseMO.getParent();
     MachineBasicBlock &UseBB = *UseMI.getParent();
     UseBlocks.set(UseBB.getNumber());
     if (UseMI.isPHI()) {
       // If Reg is used in a phi then it is live-to-end of the corresponding
       // predecessor.
-      unsigned Idx = UseMI.getOperandNo(&UseMO);
+      unsigned Idx = UseMO.getOperandNo();
       LiveToEndBlocks.push_back(UseMI.getOperand(Idx + 1).getMBB());
     } else if (&UseBB == &DefBB) {
       // A non-phi use in the same BB as the single def must come after the def.
     } else {
       // Otherwise Reg must be live-to-end of all predecessors.
       LiveToEndBlocks.append(UseBB.pred_begin(), UseBB.pred_end());
     }
   }

llvm/lib/CodeGen/MachineFunction.cpp

auto MachineFunction::salvageCopySSAImpl(MachineInstr &MI)
   // If we managed to find the defining instruction after COPYs, return an
   // instruction / operand pair after adding subregister qualifiers.
   if (State.first.isVirtual()) {
     // Virtual register def -- we can just look up where this happens.
     MachineInstr *Inst = MRI.def_begin(State.first)->getParent();
     for (auto &MO : Inst->operands()) {
       if (!MO.isReg() || !MO.isDef() || MO.getReg() != State.first)
         continue;
-      return ApplySubregisters(
-          {Inst->getDebugInstrNum(), Inst->getOperandNo(&MO)});
+      return ApplySubregisters({Inst->getDebugInstrNum(), MO.getOperandNo()});
     }
 
     llvm_unreachable("Vreg def with no corresponding operand?");
   }
 
   // Our search ended in a copy from a physreg: walk back up the function
   // looking for whatever defines the physreg.
   assert(CurInst->isCopyLike() || TII.isCopyInstr(*CurInst));
   State = GetRegAndSubreg(*CurInst);
   Register RegToSeek = State.first;
 
   auto RMII = CurInst->getReverseIterator();
   auto PrevInstrs = make_range(RMII, CurInst->getParent()->instr_rend());
   for (auto &ToExamine : PrevInstrs) {
     for (auto &MO : ToExamine.operands()) {
       // Test for operand that defines something aliasing RegToSeek.
       if (!MO.isReg() || !MO.isDef() ||
           !TRI.regsOverlap(RegToSeek, MO.getReg()))
         continue;
 
       return ApplySubregisters(
-          {ToExamine.getDebugInstrNum(), ToExamine.getOperandNo(&MO)});
+          {ToExamine.getDebugInstrNum(), MO.getOperandNo()});
     }
   }
 
   MachineBasicBlock &InsertBB = *CurInst->getParent();
 
   // We reached the start of the block before finding a defining instruction.
   // There are numerous scenarios where this can happen:
   // * Constant physical registers,

llvm/lib/CodeGen/MachineOperand.cpp

static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
   return nullptr;
 }
 
 static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
   return const_cast<MachineFunction *>(
       getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
 }
 
+unsigned MachineOperand::getOperandNo() const {
+  assert(getParent() && "Operand does not belong to any instruction!");
+  return getParent()->getOperandNo(this);
+}
+
 void MachineOperand::setReg(Register Reg) {
   if (getReg() == Reg)
     return; // No change.
 
   // Clear the IsRenamable bit to keep it conservatively correct.
   IsRenamable = false;
 
   // Otherwise, we have to change the register.  If this operand is embedded

llvm/lib/CodeGen/MachinePipeliner.cpp

void SwingSchedulerDAG::updatePhiDependences() {
   // Iterate over each DAG node.
   for (SUnit &I : SUnits) {
     RemoveDeps.clear();
     // Set to true if the instruction has an operand defined by a Phi.
     unsigned HasPhiUse = 0;
     unsigned HasPhiDef = 0;
     MachineInstr *MI = I.getInstr();
     // Iterate over each operand, and we process the definitions.
-    for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
-                                    MOE = MI->operands_end();
-         MOI != MOE; ++MOI) {
-      if (!MOI->isReg())
+    for (const MachineOperand &MO : MI->operands()) {
+      if (!MO.isReg())
         continue;
-      Register Reg = MOI->getReg();
-      if (MOI->isDef()) {
+      Register Reg = MO.getReg();
+      if (MO.isDef()) {
         // If the register is used by a Phi, then create an anti dependence.
         for (MachineRegisterInfo::use_instr_iterator
                  UI = MRI.use_instr_begin(Reg),
                  UE = MRI.use_instr_end();
              UI != UE; ++UI) {
           MachineInstr *UseMI = &*UI;
           SUnit *SU = getSUnit(UseMI);
           if (SU != nullptr && UseMI->isPHI()) {
             if (!MI->isPHI()) {
               SDep Dep(SU, SDep::Anti, Reg);
               Dep.setLatency(1);
               I.addPred(Dep);
             } else {
               HasPhiDef = Reg;
               // Add a chain edge to a dependent Phi that isn't an existing
               // predecessor.
               if (SU->NodeNum < I.NodeNum && !I.isPred(SU))
                 I.addPred(SDep(SU, SDep::Barrier));
             }
           }
         }
-      } else if (MOI->isUse()) {
+      } else if (MO.isUse()) {
         // If the register is defined by a Phi, then create a true dependence.
         MachineInstr *DefMI = MRI.getUniqueVRegDef(Reg);
         if (DefMI == nullptr)
           continue;
         SUnit *SU = getSUnit(DefMI);
         if (SU != nullptr && DefMI->isPHI()) {
           if (!MI->isPHI()) {
             SDep Dep(SU, SDep::Data, Reg);
             Dep.setLatency(0);
-            ST.adjustSchedDependency(SU, 0, &I, MI->getOperandNo(MOI), Dep);
+            ST.adjustSchedDependency(SU, 0, &I, MO.getOperandNo(), Dep);
             I.addPred(Dep);
           } else {
             HasPhiUse = Reg;
             // Add a chain edge to a dependent Phi that isn't an existing
             // predecessor.
             if (SU->NodeNum < I.NodeNum && !I.isPred(SU))
               I.addPred(SDep(SU, SDep::Barrier));
           }

llvm/lib/CodeGen/MachineSink.cpp

bool MachineSinking::AllUsesDominatedByBlock(Register Reg,
   //     ...
   //     JE_4 <%bb.37>, implicit %eflags
   //   Successors according to CFG: %bb.37 %bb.2
   //
   // %bb.2:
   //     %p = PHI %y, %bb.0, %def, %bb.1
   if (all_of(MRI->use_nodbg_operands(Reg), [&](MachineOperand &MO) {
         MachineInstr *UseInst = MO.getParent();
-        unsigned OpNo = UseInst->getOperandNo(&MO);
+        unsigned OpNo = MO.getOperandNo();
         MachineBasicBlock *UseBlock = UseInst->getParent();
         return UseBlock == MBB && UseInst->isPHI() &&
                UseInst->getOperand(OpNo + 1).getMBB() == DefMBB;
       })) {
     BreakPHIEdge = true;
     return true;
   }
 

llvm/lib/CodeGen/MachineTraceMetrics.cpp

 static bool getDataDeps(const MachineInstr &UseMI,
                         SmallVectorImpl<DataDep> &Deps,
                         const MachineRegisterInfo *MRI) {
   // Debug values should not be included in any calculations.
   if (UseMI.isDebugInstr())
     return false;
 
   bool HasPhysRegs = false;
-  for (MachineInstr::const_mop_iterator I = UseMI.operands_begin(),
-       E = UseMI.operands_end(); I != E; ++I) {
-    const MachineOperand &MO = *I;
+  for (const MachineOperand &MO : UseMI.operands()) {
     if (!MO.isReg())
       continue;
     Register Reg = MO.getReg();
     if (!Reg)
       continue;
     if (Reg.isPhysical()) {
       HasPhysRegs = true;
       continue;
     }
     // Collect virtual register reads.
     if (MO.readsReg())
-      Deps.push_back(DataDep(MRI, Reg, UseMI.getOperandNo(I)));
+      Deps.push_back(DataDep(MRI, Reg, MO.getOperandNo()));
   }
   return HasPhysRegs;
 }
 
 // Get the input data dependencies of a PHI instruction, using Pred as the
 // preferred predecessor.
 // This will add at most one dependency to Deps.
 static void getPHIDeps(const MachineInstr &UseMI,

 // tracking set when scanning instructions downwards.
 static void updatePhysDepsDownwards(const MachineInstr *UseMI,
                                     SmallVectorImpl<DataDep> &Deps,
                                     SparseSet<LiveRegUnit> &RegUnits,
                                     const TargetRegisterInfo *TRI) {
   SmallVector<MCRegister, 8> Kills;
   SmallVector<unsigned, 8> LiveDefOps;
 
-  for (MachineInstr::const_mop_iterator MI = UseMI->operands_begin(),
-       ME = UseMI->operands_end(); MI != ME; ++MI) {
-    const MachineOperand &MO = *MI;
+  for (const MachineOperand &MO : UseMI->operands()) {
     if (!MO.isReg() || !MO.getReg().isPhysical())
       continue;
     MCRegister Reg = MO.getReg().asMCReg();
     // Track live defs and kills for updating RegUnits.
     if (MO.isDef()) {
       if (MO.isDead())
         Kills.push_back(Reg);
       else
-        LiveDefOps.push_back(UseMI->getOperandNo(MI));
+        LiveDefOps.push_back(MO.getOperandNo());
     } else if (MO.isKill())
       Kills.push_back(Reg);
     // Identify dependencies.
     if (!MO.readsReg())
       continue;
     for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
       SparseSet<LiveRegUnit>::iterator I = RegUnits.find(*Units);
       if (I == RegUnits.end())
         continue;
-      Deps.push_back(DataDep(I->MI, I->Op, UseMI->getOperandNo(MI)));
+      Deps.push_back(DataDep(I->MI, I->Op, MO.getOperandNo()));
       break;
     }
   }
 
   // Update RegUnits to reflect live registers after UseMI.
   // First kills.
   for (MCRegister Kill : Kills)
     for (MCRegUnitIterator Units(Kill, TRI); Units.isValid(); ++Units)

 // Height is the issue height computed from virtual register dependencies alone.
 static unsigned updatePhysDepsUpwards(const MachineInstr &MI, unsigned Height,
                                       SparseSet<LiveRegUnit> &RegUnits,
                                       const TargetSchedModel &SchedModel,
                                       const TargetInstrInfo *TII,
                                       const TargetRegisterInfo *TRI) {
   SmallVector<unsigned, 8> ReadOps;
 
-  for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(),
-                                        MOE = MI.operands_end();
-       MOI != MOE; ++MOI) {
-    const MachineOperand &MO = *MOI;
+  for (const MachineOperand &MO : MI.operands()) {
     if (!MO.isReg())
       continue;
     Register Reg = MO.getReg();
     if (!Reg.isPhysical())
       continue;
     if (MO.readsReg())
-      ReadOps.push_back(MI.getOperandNo(MOI));
+      ReadOps.push_back(MO.getOperandNo());
     if (!MO.isDef())
       continue;
     // This is a def of Reg. Remove corresponding entries from RegUnits, and
     // update MI Height to consider the physreg dependencies.
     for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
          ++Units) {
       SparseSet<LiveRegUnit>::iterator I = RegUnits.find(*Units);
       if (I == RegUnits.end())
         continue;
       unsigned DepHeight = I->Cycle;
       if (!MI.isTransient()) {
         // We may not know the UseMI of this dependency, if it came from the
         // live-in list. SchedModel can handle a NULL UseMI.
-        DepHeight += SchedModel.computeOperandLatency(&MI, MI.getOperandNo(MOI),
+        DepHeight += SchedModel.computeOperandLatency(&MI, MO.getOperandNo(),
                                                       I->MI, I->Op);
       }
       Height = std::max(Height, DepHeight);
       // This regunit is dead above MI.
       RegUnits.erase(I);
     }
   }
 

llvm/lib/CodeGen/RenameIndependentSubregs.cpp

for (MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(Reg),
 
     unsigned VReg = Intervals[ID]->reg();
     MO.setReg(VReg);
 
     if (MO.isTied() && Reg != VReg) {
       /// Undef use operands are not tracked in the equivalence class,
       /// but need to be updated if they are tied; take care to only
       /// update the tied operand.
-      unsigned OperandNo = MI->getOperandNo(&MO);
+      unsigned OperandNo = MO.getOperandNo();
       unsigned TiedIdx = MI->findTiedOperandIdx(OperandNo);
       MI->getOperand(TiedIdx).setReg(VReg);
 
       // above substitution breaks the iterator, so restart.
       I = MRI->reg_nodbg_begin(Reg);
     }
   }
   // TODO: We could attempt to recompute new register classes while visiting

llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

void ScheduleDAGInstrs::addSchedBarrierDeps() {
   // Add dependencies on the defs and uses of the instruction.
   if (ExitMI) {
     for (const MachineOperand &MO : ExitMI->operands()) {
       if (!MO.isReg() || MO.isDef()) continue;
       Register Reg = MO.getReg();
       if (Reg.isPhysical()) {
         Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
       } else if (Reg.isVirtual() && MO.readsReg()) {
-        addVRegUseDeps(&ExitSU, ExitMI->getOperandNo(&MO));
+        addVRegUseDeps(&ExitSU, MO.getOperandNo());
       }
     }
   }
   if (!ExitMI || (!ExitMI->isCall() && !ExitMI->isBarrier())) {
     // For others, e.g. fallthrough, conditional branch, assume the exit
     // uses all the registers that are livein to the successor blocks.
     for (const MachineBasicBlock *Succ : BB->successors()) {
       for (const auto &LI : Succ->liveins()) {

llvm/lib/CodeGen/SplitKit.cpp

if (MO.isDef()) {
         //  0  %0 = ...
         // 16  early-clobber %0 = Op %0 (tied-def 0), ...
         // 32  ... = Op %0
         // Before extend:
         //   %0 = [0r, 0d) [16e, 32d)
         // The point we want to extend is 0d to 16e not 16r in this case, but if
         // we use 16r here we will extend nothing because that already contained
         // in [16e, 32d).
-        unsigned OpIdx = MI->getOperandNo(&MO);
+        unsigned OpIdx = MO.getOperandNo();
         unsigned DefOpIdx = MI->findTiedOperandIdx(OpIdx);
         const MachineOperand &DefOp = MI->getOperand(DefOpIdx);
         IsEarlyClobber = DefOp.isEarlyClobber();
       }
 
       Idx = Idx.getRegSlot(IsEarlyClobber);
     }
 

llvm/lib/CodeGen/StackMaps.cpp

unsigned StatepointOpers::getGCPointerMap(
   }
 
   return GCMapSize;
 }
 
 bool StatepointOpers::isFoldableReg(Register Reg) const {
   unsigned FoldableAreaStart = getVarIdx();
   for (const MachineOperand &MO : MI->uses()) {
-    if (MI->getOperandNo(&MO) >= FoldableAreaStart)
+    if (MO.getOperandNo() >= FoldableAreaStart)
       break;
     if (MO.isReg() && MO.getReg() == Reg)
       return false;
   }
   return true;
 }
 
 bool StatepointOpers::isFoldableReg(const MachineInstr *MI, Register Reg) {

llvm/lib/CodeGen/TwoAddressInstructionPass.cpp

findOnlyInterestingUse(Register Reg, MachineBasicBlock *MBB,
   }
   IsDstPhys = false;
   if (isTwoAddrUse(UseMI, Reg, DstReg)) {
     IsDstPhys = DstReg.isPhysical();
     return &UseMI;
   }
   if (UseMI.isCommutable()) {
     unsigned Src1 = TargetInstrInfo::CommuteAnyOperandIndex;
-    unsigned Src2 = UseMI.getOperandNo(UseOp);
+    unsigned Src2 = UseOp->getOperandNo();
     if (TII->findCommutedOpIndices(UseMI, Src1, Src2)) {
       MachineOperand &MO = UseMI.getOperand(Src1);
       if (MO.isReg() && MO.isUse() &&
           isTwoAddrUse(UseMI, MO.getReg(), DstReg)) {
         IsDstPhys = DstReg.isPhysical();
         return &UseMI;
       }
     }
bool TwoAddressInstructionPass::convertInstTo3Addr(
   LLVM_DEBUG(dbgs() << "2addr:         TO 3-ADDR: " << *NewMI);
 
   // If the old instruction is debug value tracked, an update is required.
   if (auto OldInstrNum = mi->peekDebugInstrNum()) {
     assert(mi->getNumExplicitDefs() == 1);
     assert(NewMI->getNumExplicitDefs() == 1);
 
     // Find the old and new def location.
-    auto OldIt = mi->defs().begin();
-    auto NewIt = NewMI->defs().begin();
-    unsigned OldIdx = mi->getOperandNo(OldIt);
-    unsigned NewIdx = NewMI->getOperandNo(NewIt);
+    unsigned OldIdx = mi->defs().begin()->getOperandNo();
+    unsigned NewIdx = NewMI->defs().begin()->getOperandNo();
 
     // Record that one def has been replaced by the other.
     unsigned NewInstrNum = NewMI->getDebugInstrNum();
     MF->makeDebugValueSubstitution(std::make_pair(OldInstrNum, OldIdx),
                                    std::make_pair(NewInstrNum, NewIdx));
   }
 
   MBB->erase(mi); // Nuke the old inst.