DAG: Remove hasBitPreservingFPLogic

[arsenm]

Summary

This doesn't make sense as an option. fneg and fabs are bit
preserving by definition. If a target has some fneg or fabs
instruction that are not bitpreserving it's incorrect to lower
fneg/fabs to use it.

[efriedma]

I think hasBitPreservingFPLogic() is an artifact of the old days when FNEG/FABS would sometimes get expanded using FSUB etc. If we don't do that anymore, then sure, let's kill the hook off. LGTM.

llvm/lib/Target/SystemZ/SystemZISelLowering.h

1

Accidental whitespace?

[spatel]

For reference, I added this hook with:
https://reviews.llvm.org/D19391
...which was responding to:
https://lists.llvm.org/pipermail/llvm-dev/2016-April/098098.html
and:
https://bugs.llvm.org/show_bug.cgi?id=24886#c4

So there were problems before we had fneg/fabs in IR/SDAG, but it seems there were also problems with denorms and other edge cases.
I'm not opposed to this patch, but I think we should notify a wider audience about the change (since the hook defaulted to "off"). Out-of-tree targets may need to make adjustments. Post a message on discourse?

[arsenm]

In D142567#4080807, @spatel wrote:

For reference, I added this hook with:
https://reviews.llvm.org/D19391
...which was responding to:
https://lists.llvm.org/pipermail/llvm-dev/2016-April/098098.html
and:
https://bugs.llvm.org/show_bug.cgi?id=24886#c4

So there were problems before we had fneg/fabs in IR/SDAG, but it seems there were also problems with denorms and other edge cases.
I'm not opposed to this patch, but I think we should notify a wider audience about the change (since the hook defaulted to "off"). Out-of-tree targets may need to make adjustments. Post a message on discourse?

I don't think anyone notices those kinds of notices, but I posted https://discourse.llvm.org/t/notice-to-out-of-tree-targets-targetlowering-hasbitpreservingfplogic-is-being-removed/67975

[asb]

In D142567#4082260, @arsenm wrote:

In D142567#4080807, @spatel wrote:

For reference, I added this hook with:
https://reviews.llvm.org/D19391
...which was responding to:
https://lists.llvm.org/pipermail/llvm-dev/2016-April/098098.html
and:
https://bugs.llvm.org/show_bug.cgi?id=24886#c4

So there were problems before we had fneg/fabs in IR/SDAG, but it seems there were also problems with denorms and other edge cases.
I'm not opposed to this patch, but I think we should notify a wider audience about the change (since the hook defaulted to "off"). Out-of-tree targets may need to make adjustments. Post a message on discourse?

I don't think anyone notices those kinds of notices, but I posted https://discourse.llvm.org/t/notice-to-out-of-tree-targets-targetlowering-hasbitpreservingfplogic-is-being-removed/67975

I included it in today's LLVM Weekly, so it hopefully gets an audience (not sure what the bar should be for posting such notices though - there are plenty of things that may break out-of-tree targets and maintainers are presumably used to looking up the commit that removed whatever hook they had been calling to find out why it was removed/changed).

[arsenm]

09dd4d870e192da73594b713bb201859e5a09efb

llvm/include/llvm/CodeGen/TargetLowering.h

public:
   /// Return true if instruction generated for equality comparison is folded
   /// with instruction generated for signed comparison.
   virtual bool isEqualityCmpFoldedWithSignedCmp() const { return true; }
 
   /// Return true if the heuristic to prefer icmp eq zero should be used in code
   /// gen prepare.
   virtual bool preferZeroCompareBranch() const { return false; }
 
-  /// Return true if it is safe to transform an integer-domain bitwise operation
-  /// into the equivalent floating-point operation. This should be set to true
-  /// if the target has IEEE-754-compliant fabs/fneg operations for the input
-  /// type.
-  virtual bool hasBitPreservingFPLogic(EVT VT) const {
-    return false;
-  }
-
   /// Return true if it is cheaper to split the store of a merged int val
   /// from a pair of smaller values into multiple stores.
   virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
     return false;
   }
 
   /// Return if the target supports combining a
   /// chain like:

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

private:
 
     bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
                            SDValue &CC, bool MatchStrict = false) const;
     bool isOneUseSetCC(SDValue N) const;
 
     SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
                                          unsigned HiOp);
     SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
+    SDValue foldBitcastedFPLogic(SDNode *N, SelectionDAG &DAG,
+                                 const TargetLowering &TLI);
+
     SDValue CombineExtLoad(SDNode *N);
     SDValue CombineZExtLogicopShiftLoad(SDNode *N);
     SDValue combineRepeatedFPDivisors(SDNode *N);
     SDValue mergeInsertEltWithShuffle(SDNode *N, unsigned InsIndex);
     SDValue combineInsertEltToShuffle(SDNode *N, unsigned InsIndex);
     SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
     SDValue BuildSDIV(SDNode *N);
     SDValue BuildSDIVPow2(SDNode *N);

 }
 
 static unsigned getPPCf128HiElementSelector(const SelectionDAG &DAG) {
   // On little-endian machines, bitcasting from ppcf128 to i128 does swap the Hi
   // and Lo parts; on big-endian machines it doesn't.
   return DAG.getDataLayout().isBigEndian() ? 1 : 0;
 }
 
-static SDValue foldBitcastedFPLogic(SDNode *N, SelectionDAG &DAG,
+SDValue DAGCombiner::foldBitcastedFPLogic(SDNode *N, SelectionDAG &DAG,
                                           const TargetLowering &TLI) {
   // If this is not a bitcast to an FP type or if the target doesn't have
   // IEEE754-compliant FP logic, we're done.
   EVT VT = N->getValueType(0);
-  if (!VT.isFloatingPoint() || !TLI.hasBitPreservingFPLogic(VT))
+  SDValue N0 = N->getOperand(0);
+  EVT SourceVT = N0.getValueType();
+
+  if (!VT.isFloatingPoint())
     return SDValue();
 
   // TODO: Handle cases where the integer constant is a different scalar
   // bitwidth to the FP.
-  SDValue N0 = N->getOperand(0);
-  EVT SourceVT = N0.getValueType();
   if (VT.getScalarSizeInBits() != SourceVT.getScalarSizeInBits())
     return SDValue();
 
   unsigned FPOpcode;
   APInt SignMask;
   switch (N0.getOpcode()) {
   case ISD::AND:
     FPOpcode = ISD::FABS;
     SignMask = ~APInt::getSignMask(SourceVT.getScalarSizeInBits());
     break;
   case ISD::XOR:
     FPOpcode = ISD::FNEG;
     SignMask = APInt::getSignMask(SourceVT.getScalarSizeInBits());
     break;
   case ISD::OR:
     FPOpcode = ISD::FABS;
     SignMask = APInt::getSignMask(SourceVT.getScalarSizeInBits());
     break;
   default:
     return SDValue();
   }
 
+  if (LegalOperations && !TLI.isOperationLegal(FPOpcode, VT))
+    return SDValue();
+
   // This needs to be the inverse of logic in foldSignChangeInBitcast.
   // FIXME: I don't think looking for bitcast intrinsically makes sense, but
   // removing this would require more changes.
   auto IsBitCastOrFree = [&TLI, FPOpcode](SDValue Op, EVT VT) {
     if (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).getValueType() == VT)
       return true;
 
     return FPOpcode == ISD::FABS ? TLI.isFAbsFree(VT) : TLI.isFNegFree(VT);

llvm/lib/Target/AArch64/AArch64ISelLowering.h

public:
   bool isComplexDeinterleavingOperationSupported(
       ComplexDeinterleavingOperation Operation, Type *Ty) const override;
 
   Value *createComplexDeinterleavingIR(
       Instruction *I, ComplexDeinterleavingOperation OperationType,
       ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB,
       Value *Accumulator = nullptr) const override;
 
-  bool hasBitPreservingFPLogic(EVT VT) const override {
-    // FIXME: Is this always true? It should be true for vectors at least.
-    return VT == MVT::f32 || VT == MVT::f64;
-  }
-
   bool supportSplitCSR(MachineFunction *MF) const override {
     return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
            MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
   }
   void initializeSplitCSR(MachineBasicBlock *Entry) const override;
   void insertCopiesSplitCSR(
       MachineBasicBlock *Entry,
       const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;

llvm/lib/Target/AMDGPU/SIISelLowering.h

public:
   void bundleInstWithWaitcnt(MachineInstr &MI) const;
   MachineBasicBlock *emitGWSMemViolTestLoop(MachineInstr &MI,
                                             MachineBasicBlock *BB) const;
 
   MachineBasicBlock *
   EmitInstrWithCustomInserter(MachineInstr &MI,
                               MachineBasicBlock *BB) const override;
 
-  bool hasBitPreservingFPLogic(EVT VT) const override;
   bool hasAtomicFaddRtnForTy(SDValue &Op) const;
   bool enableAggressiveFMAFusion(EVT VT) const override;
   bool enableAggressiveFMAFusion(LLT Ty) const override;
   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
                          EVT VT) const override;
   MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
   LLT getPreferredShiftAmountTy(LLT Ty) const override;
 

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

case AMDGPU::S_SETREG_B32: {
 
     return BB;
   }
   default:
     return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
   }
 }
 
-bool SITargetLowering::hasBitPreservingFPLogic(EVT VT) const {
-  return isTypeLegal(VT.getScalarType());
-}
-
 bool SITargetLowering::hasAtomicFaddRtnForTy(SDValue &Op) const {
   switch (Op.getValue(0).getSimpleValueType().SimpleTy) {
   case MVT::f32:
     return Subtarget->hasAtomicFaddRtnInsts();
   case MVT::v2f16:
   case MVT::f64:
     return Subtarget->hasGFX90AInsts();
   default:

llvm/lib/Target/PowerPC/PPCISelLowering.h

private:
     /// lowerToXXSPLTI32DX - Return the SDValue if this VECTOR_SHUFFLE can be
     /// handled by the XXSPLTI32DX instruction introduced in ISA 3.1.
     SDValue lowerToXXSPLTI32DX(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
 
     // Return whether the call instruction can potentially be optimized to a
     // tail call. This will cause the optimizers to attempt to move, or
     // duplicate return instructions to help enable tail call optimizations.
     bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
-    bool hasBitPreservingFPLogic(EVT VT) const override;
     bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
 
     /// getAddrModeForFlags - Based on the set of address flags, select the most
     /// optimal instruction format to match by.
     PPC::AddrMode getAddrModeForFlags(unsigned Flags) const;
 
     /// computeMOFlags - Given a node N and it's Parent (a MemSDNode), compute
     /// the address flags of the load/store instruction that is to be matched.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

bool PPCTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
   if (!areCallingConvEligibleForTCO_64SVR4(Caller->getCallingConv(),
                                            CI->getCallingConv()))
       return false;
 
   // If the function is local then we have a good chance at tail-calling it
   return getTargetMachine().shouldAssumeDSOLocal(*Caller->getParent(), Callee);
 }
 
-bool PPCTargetLowering::hasBitPreservingFPLogic(EVT VT) const {
-  if (!Subtarget.hasVSX())
-    return false;
-  if (Subtarget.hasP9Vector() && VT == MVT::f128)
-    return true;
-  return VT == MVT::f32 || VT == MVT::f64 ||
-    VT == MVT::v4f32 || VT == MVT::v2f64;
-}
-
 bool PPCTargetLowering::
 isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
   const Value *Mask = AndI.getOperand(1);
   // If the mask is suitable for andi. or andis. we should sink the and.
   if (const ConstantInt *CI = dyn_cast<ConstantInt>(Mask)) {
     // Can't handle constants wider than 64-bits.
     if (CI->getBitWidth() > 64)
       return false;

llvm/lib/Target/RISCV/RISCVISelLowering.h

public:
 
   bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode,
                                             EVT VT) const override;
 
   /// Return true if the given shuffle mask can be codegen'd directly, or if it
   /// should be stack expanded.
   bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
 
-  bool hasBitPreservingFPLogic(EVT VT) const override;
   bool
   shouldExpandBuildVectorWithShuffles(EVT VT,
                                       unsigned DefinedValues) const override;
 
   // Provide custom lowering hooks for some operations.
   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
   void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
                           SelectionDAG &DAG) const override;

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

bool RISCVTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
   if (Index >= 32)
     return false;
 
   // TODO: We can do arbitrary slidedowns, but for now only support extracting
   // the upper half of a vector until we have more test coverage.
   return Index == 0 || Index == ResElts;
 }
 
-bool RISCVTargetLowering::hasBitPreservingFPLogic(EVT VT) const {
-  return (VT == MVT::f16 && Subtarget.hasStdExtZfhOrZfhmin()) ||
-         (VT == MVT::f32 && Subtarget.hasStdExtF()) ||
-         (VT == MVT::f64 && Subtarget.hasStdExtD());
-}
-
 MVT RISCVTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
                                                       CallingConv::ID CC,
                                                       EVT VT) const {
   // Use f32 to pass f16 if it is legal and Zfh/Zfhmin is not enabled.
   // We might still end up using a GPR but that will be decided based on ABI.
   if (VT == MVT::f16 && Subtarget.hasStdExtF() &&
       !Subtarget.hasStdExtZfhOrZfhmin())
     return MVT::f32;

llvm/lib/Target/SystemZ/SystemZISelLowering.h

+
 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
getNumRegisters(LLVMContext &Context, EVT VT,
                   std::optional<MVT> RegisterVT) const override {
     // i128 inline assembly operand.
     if (VT == MVT::i128 && RegisterVT && *RegisterVT == MVT::Untyped)
       return 1;
     return TargetLowering::getNumRegisters(Context, VT);
   }
   bool isCheapToSpeculateCtlz(Type *) const override { return true; }
   bool preferZeroCompareBranch() const override { return true; }
-  bool hasBitPreservingFPLogic(EVT VT) const override {
-    EVT ScVT = VT.getScalarType();
-    return ScVT == MVT::f32 || ScVT == MVT::f64 || ScVT == MVT::f128;
-  }
   bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override {
     ConstantInt* Mask = dyn_cast<ConstantInt>(AndI.getOperand(1));
     return Mask && Mask->getValue().isIntN(16);
   }
   bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
     return VT.isScalarInteger();
   }
   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,

llvm/lib/Target/X86/X86ISelLowering.h

bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
                           const MachineFunction &MF) const override;
 
     bool isCheapToSpeculateCttz(Type *Ty) const override;
 
     bool isCheapToSpeculateCtlz(Type *Ty) const override;
 
     bool isCtlzFast() const override;
 
-    bool hasBitPreservingFPLogic(EVT VT) const override;
-
     bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
       // If the pair to store is a mixture of float and int values, we will
       // save two bitwise instructions and one float-to-int instruction and
       // increase one store instruction. There is potentially a more
       // significant benefit because it avoids the float->int domain switch
       // for input value. So It is more likely a win.
       if ((LTy.isFloatingPoint() && HTy.isInteger()) ||
           (LTy.isInteger() && HTy.isFloatingPoint()))

llvm/lib/Target/X86/X86ISelLowering.cpp

return Subtarget.hasBMI() ||
          (!Ty->isVectorTy() && Ty->getScalarSizeInBits() < 32);
 }
 
 bool X86TargetLowering::isCheapToSpeculateCtlz(Type *Ty) const {
   // Speculate ctlz only if we can directly use LZCNT.
   return Subtarget.hasLZCNT();
 }
 
-bool X86TargetLowering::hasBitPreservingFPLogic(EVT VT) const {
-  return VT == MVT::f32 || VT == MVT::f64 || VT.isVector();
-}
-
 bool X86TargetLowering::ShouldShrinkFPConstant(EVT VT) const {
   // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
   // expensive than a straight movsd. On the other hand, it's important to
   // shrink long double fp constant since fldt is very slow.
   return !Subtarget.hasSSE2() || VT == MVT::f80;
 }
 
 bool X86TargetLowering::isScalarFPTypeInSSEReg(EVT VT) const {

llvm/test/CodeGen/AMDGPU/fneg.ll

 ; GCN-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
 ; GCN-NEXT: s_setpc_b64
 define i16 @v_fneg_i16(i16 %in) {
   %fneg = xor i16 %in, -32768
   ret i16 %fneg
 }
 
 ; FUNC-LABEL: {{^}}s_fneg_i16_fp_use:
-; SI: v_cvt_f32_f16_e64 [[CVT0:v[0-9]+]], -s{{[0-9]+}}
-; SI: v_add_f32_e32 [[ADD:v[0-9]+]], 2.0, [[CVT0]]
+; SI: v_cvt_f32_f16_e32 [[CVT0:v[0-9]+]], s{{[0-9]+}}
+; SI: v_sub_f32_e32 [[ADD:v[0-9]+]], 2.0, [[CVT0]]
 ; SI: v_cvt_f16_f32_e32 [[CVT1:v[0-9]+]], [[ADD]]
 
 ; VI: s_load_dword [[IN:s[0-9]+]]
 ; VI: v_sub_f16_e64 v{{[0-9]+}}, 2.0, [[IN]]
 define amdgpu_kernel void @s_fneg_i16_fp_use(ptr addrspace(1) %out, i16 %in) {
   %fneg = xor i16 %in, -32768
   %bitcast = bitcast i16 %fneg to half
   %fadd = fadd half %bitcast, 2.0
   store half %fadd, ptr addrspace(1) %out
   ret void
 }
 
 ; FUNC-LABEL: {{^}}v_fneg_i16_fp_use:
 ; SI: s_waitcnt
-; SI-NEXT: v_cvt_f32_f16_e64 v0, -v0
-; SI-NEXT: v_add_f32_e32 v0, 2.0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_sub_f32_e32 v0, 2.0, v0
 ; SI-NEXT: s_setpc_b64
 
 ; VI: s_waitcnt
 ; VI-NEXT: v_sub_f16_e32 v0, 2.0, v0
 ; VI-NEXT: s_setpc_b64
 define half @v_fneg_i16_fp_use(i16 %in) {
   %fneg = xor i16 %in, -32768
   %bitcast = bitcast i16 %fneg to half

 ; VI-NEXT: s_setpc_b64
 define <2 x i16> @v_fneg_v2i16(<2 x i16> %in) {
   %fneg = xor <2 x i16> %in, <i16 -32768, i16 -32768>
   ret <2 x i16> %fneg
 }
 
 ; FUNC-LABEL: {{^}}s_fneg_v2i16_fp_use:
 ; SI: s_lshr_b32 s3, s2, 16
-; SI: v_cvt_f32_f16_e64 v0, -s3
-; SI: v_cvt_f32_f16_e64 v1, -s2
+; SI: v_cvt_f32_f16_e32 v0, s3
+; SI: v_cvt_f32_f16_e32 v1, s2
+; SI: v_sub_f32_e32 v0, 2.0, v0
+; SI: v_sub_f32_e32 v1, 2.0, v1
 
 ; VI: s_lshr_b32 s5, s4, 16
 ; VI: s_xor_b32 s5, s5, 0x8000
 ; VI: s_xor_b32 s4, s4, 0x8000
 ; VI: v_mov_b32_e32 v0, s5
 ; VI: v_add_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 ; VI: v_add_f16_e64 v1, s4, 2.0
 ; VI: v_or_b32_e32 v0, v1, v0
 define amdgpu_kernel void @s_fneg_v2i16_fp_use(ptr addrspace(1) %out, i32 %arg) {
   %in = bitcast i32 %arg to <2 x i16>
   %fneg = xor <2 x i16> %in, <i16 -32768, i16 -32768>
   %bitcast = bitcast <2 x i16> %fneg to <2 x half>
   %fadd = fadd <2 x half> %bitcast, <half 2.0, half 2.0>
   store <2 x half> %fadd, ptr addrspace(1) %out
   ret void
 }
 
 ; FUNC-LABEL: {{^}}v_fneg_v2i16_fp_use:
 ; SI: v_lshrrev_b32_e32 v1, 16, v0
-; SI: v_cvt_f32_f16_e64 v0, -v0
-; SI: v_cvt_f32_f16_e64 v1, -v1
-; SI: v_add_f32_e32 v0, 2.0, v0
-; SI: v_add_f32_e32 v1, 2.0, v1
+; SI: v_cvt_f32_f16_e32 v0, v0
+; SI: v_cvt_f32_f16_e32 v1, v1
+; SI: v_sub_f32_e32 v0, 2.0, v0
+; SI: v_sub_f32_e32 v1, 2.0, v1
 
 ; VI: s_waitcnt
 ; VI: v_mov_b32_e32 v1, 0x4000
 ; VI: v_sub_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; VI: v_sub_f16_e32 v0, 2.0, v0
 ; VI: v_or_b32_e32 v0, v0, v1
 ; VI: s_setpc_b64
 define <2 x half> @v_fneg_v2i16_fp_use(i32 %arg) {
   %in = bitcast i32 %arg to <2 x i16>
   %fneg = xor <2 x i16> %in, <i16 -32768, i16 -32768>
   %bitcast = bitcast <2 x i16> %fneg to <2 x half>
   %fadd = fadd <2 x half> %bitcast, <half 2.0, half 2.0>
   ret <2 x half> %fadd
 }

llvm/test/CodeGen/PowerPC/fabs.ll

 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names < %s -mattr=-vsx -mtriple=powerpc-unknown-linux-gnu | FileCheck %s
 
 define double @fabs(double %f) {
 ; CHECK-LABEL: fabs:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fabs f1, f1
 ; CHECK-NEXT:    blr
 ;
   %t = tail call double @fabs( double %f ) readnone
   ret double %t
 }
 
 define float @bitcast_fabs(float %x) {
 ; CHECK-LABEL: bitcast_fabs:
 ; CHECK:       # %bb.0:
-; CHECK:         stfs f1, 8(r1)
-; CHECK:         lwz r3, 8(r1)
-; CHECK-NEXT:    clrlwi r3, r3, 1
-; CHECK-NEXT:    stw r3, 12(r1)
-; CHECK-NEXT:    lfs f1, 12(r1)
-; CHECK-NEXT:    addi r1, r1, 16
+; CHECK-NEXT: fabs f1, f1
 ; CHECK-NEXT:    blr
 ;
   %bc1 = bitcast float %x to i32
   %and = and i32 %bc1, 2147483647
   %bc2 = bitcast i32 %and to float
   ret float %bc2
 }
 

llvm/test/CodeGen/X86/avx512fp16-fp-logic.ll

; CHECK-NEXT:    retq
   %and = and i16 %bc1, 32768
   %bc2 = bitcast i16 %and to half
   ret half %bc2
 }
 
 define half @bitcast_fabs(half %x) {
 ; CHECK-LABEL: bitcast_fabs:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmovsh {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
-; CHECK-NEXT:    vandps %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vpbroadcastw {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
+; CHECK-NEXT:    vpand %xmm1, %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %bc1 = bitcast half %x to i16
   %and = and i16 %bc1, 32767
   %bc2 = bitcast i16 %and to half
   ret half %bc2
 }
 
 define half @bitcast_fneg(half %x) {
 ; CHECK-LABEL: bitcast_fneg:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmovsh {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
-; CHECK-NEXT:    vxorps %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vpbroadcastw {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; CHECK-NEXT:    vpxor %xmm1, %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %bc1 = bitcast half %x to i16
   %xor = xor i16 %bc1, 32768
   %bc2 = bitcast i16 %xor to half
   ret half %bc2
 }
 
 define <8 x half> @bitcast_fabs_vec(<8 x half> %x) {
; CHECK-NEXT:    retq
   %bc2 = bitcast i16 %xor to half
   %fsub = fsub half %x, %bc2
   ret half %fsub
 }
 
 define half @nabs(half %a) {
 ; CHECK-LABEL: nabs:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmovsh {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
-; CHECK-NEXT:    vorps %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vpbroadcastw {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; CHECK-NEXT:    vpor %xmm1, %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %conv = bitcast half %a to i16
   %and = or i16 %conv, -32768
   %conv1 = bitcast i16 %and to half
   ret half %conv1
 }
 
 define <8 x half> @nabsv8f16(<8 x half> %a) {

llvm/test/CodeGen/X86/fp128-i128.ll

 ;  union IEEEl2bits z;
 ;  z.e = x;
 ;  z.bits.sign = 0;
 ;  return (z.e < 0.1L) ? 1.0L : 2.0L;
 ; }
 define fp128 @TestI128_1(fp128 %x) #0 {
 ; SSE-LABEL: TestI128_1:
 ; SSE:       # %bb.0: # %entry
-; SSE-NEXT:    subq $40, %rsp
-; SSE-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; SSE-NEXT:    movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
-; SSE-NEXT:    andq {{[0-9]+}}(%rsp), %rax
-; SSE-NEXT:    movq {{[0-9]+}}(%rsp), %rcx
-; SSE-NEXT:    movq %rax, {{[0-9]+}}(%rsp)
-; SSE-NEXT:    movq %rcx, (%rsp)
-; SSE-NEXT:    movaps (%rsp), %xmm0
+; SSE-NEXT:    pushq %rax
+; SSE-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; SSE-NEXT:    movaps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
 ; SSE-NEXT:    callq __lttf2@PLT
 ; SSE-NEXT:    xorl %ecx, %ecx
 ; SSE-NEXT:    testl %eax, %eax
 ; SSE-NEXT:    sets %cl
 ; SSE-NEXT:    shlq $4, %rcx
 ; SSE-NEXT:    movaps {{\.?LCPI[0-9]+_[0-9]+}}(%rcx), %xmm0
-; SSE-NEXT:    addq $40, %rsp
+; SSE-NEXT:    popq %rax
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: TestI128_1:
 ; AVX:       # %bb.0: # %entry
-; AVX-NEXT:    subq $40, %rsp
-; AVX-NEXT:    vmovaps %xmm0, {{[0-9]+}}(%rsp)
-; AVX-NEXT:    movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
-; AVX-NEXT:    andq {{[0-9]+}}(%rsp), %rax
-; AVX-NEXT:    movq {{[0-9]+}}(%rsp), %rcx
-; AVX-NEXT:    movq %rax, {{[0-9]+}}(%rsp)
-; AVX-NEXT:    movq %rcx, (%rsp)
-; AVX-NEXT:    vmovaps (%rsp), %xmm0
+; AVX-NEXT:    pushq %rax
+; AVX-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
 ; AVX-NEXT:    vmovaps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
 ; AVX-NEXT:    callq __lttf2@PLT
 ; AVX-NEXT:    xorl %ecx, %ecx
 ; AVX-NEXT:    testl %eax, %eax
 ; AVX-NEXT:    sets %cl
 ; AVX-NEXT:    shlq $4, %rcx
 ; AVX-NEXT:    vmovaps {{\.?LCPI[0-9]+_[0-9]+}}(%rcx), %xmm0
-; AVX-NEXT:    addq $40, %rsp
+; AVX-NEXT:    popq %rax
 ; AVX-NEXT:    retq
 entry:
   %0 = bitcast fp128 %x to i128
   %bf.clear = and i128 %0, 170141183460469231731687303715884105727
   %1 = bitcast i128 %bf.clear to fp128
   %cmp = fcmp olt fp128 %1, 0xL999999999999999A3FFB999999999999
   %cond = select i1 %cmp, fp128 0xL00000000000000003FFF000000000000, fp128 0xL00000000000000004000000000000000
   ret fp128 %cond