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Differential D142021

AMDGPU/GlobalISel: Add stub custom regbankselect pass
ClosedPublic

Authored by arsenm on Jan 18 2023, 7:21 AM.

Details

Reviewers
sameerds
Petar.Avramovic
Pierre-vh
foad
nhaehnle
qcolombet
paquette
aemerson
rovka
Group Reviewers
Restricted Project
Summary

Uniformity analysis needs to be the fundamental basis for
regbank decisions. The considerations of the default pass
are secondary, but potentially useful for some edge cases (e.g.
selecting AGPRs when arbitrary loads and stores can directly use
them). This needs to be a separate pass since it requires new
analysis dependencies.




Boilerplate to subclass the existing pass which does nothing

different.
Diff Detail
Event Timeline
arsenm created this revision.Jan 18 2023, 7:21 AM
Herald added a project: Restricted Project.  ·  View Herald TranscriptJan 18 2023, 7:21 AM
Herald added subscribers: kosarev, StephenFan, kerbowa and 7 others.  ·  View Herald Transcript
arsenm requested review of this revision.Jan 18 2023, 7:21 AM
Herald added a project: Restricted Project.  ·  View Herald TranscriptJan 18 2023, 7:21 AM
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arsenm added parent revisions: D142020: AMDGPU: Partially fix machine uniformity for inline asm, D142009: GlobalISel: Split main function of RegBankSelect up.Jan 18 2023, 7:21 AM
Harbormaster completed remote builds in B208487: Diff 490150.Jan 18 2023, 7:22 AM
rovka added a subscriber: rovka.Jan 19 2023, 1:36 AM
Why do we need a new pass? Could we achieve the same goals with a new RegBankSelect mode instead? (Sorry if this was discussed somewhere else and I missed it, in any case I think the commit message should either explain the rationale or point to wherever it's been discussed)
llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp


71–72
Where is PassID used?


llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp


15
Nit: This diverges from AMDGPUInstructionSelector and Legalizer, which both define the DEBUG_TYPE as "amdgpu-blah" directly.


llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.h


11
Update this comment for RegBankSelect instead of InstructionSelector (ditto for the header guard)
Pierre-vh mentioned this in D142020: AMDGPU: Partially fix machine uniformity for inline asm.Jan 19 2023, 1:47 AM
Pierre-vh added a comment.Jan 19 2023, 1:56 AM
I agree that the commit message should have a rationale for this change



Also, now that we need to pass amdgpu-regbankselect, what happens if someone just passes regbankselect? 💥 ?
llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.h


11
It would be nice to explain why this custom pass is actually needed. If it's a stub then just say it's a stub but it's been added because it makes X or Y possible later for instance;

Otherwise it's difficult to understand why it's needed and someone might try to remove it later
arsenm added a comment.Jan 19 2023, 11:07 AM


In D142021#4064779, @rovka wrote:


Why do we need a new pass? Could we achieve the same goals with a new RegBankSelect mode instead? (Sorry if this was discussed somewhere else and I missed it, in any case I think the commit message should either explain the rationale or point to wherever it's been discussed)





I believe the mode is an orthogonal choice, which is part of why I am trying to subclass the existing pass. We could have the same use and def analysis like other targets with the different modes, but the uniformity driven decisions are more fundamental. Additionally this needs to be a separate pass because it introduces new required analysis passes
arsenm added a comment.Jan 19 2023, 11:11 AM


In D142021#4064815, @Pierre-vh wrote:


I agree that the commit message should have a rationale for this change



Also, now that we need to pass amdgpu-regbankselect, what happens if someone just passes regbankselect? 💥 ?





It will just be broken in the same way it’s broken today. Running arbitrary MIR passes isn’t supposed to be a production ready, end user exposed feature in the same way as an IR pass so I’m not too worried about diagnosing this
arsenm marked an inline comment as done.Jan 20 2023, 6:26 AM
arsenm added inline comments.
llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp


15
Those should probably use the generic name. Different debug types for the same pass are counterproductive


llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.h


11
I'll just drop it because these style comments are useless
arsenm updated this revision to Diff 490836.Jan 20 2023, 7:16 AM
More comments, fix -stop-after tests
Herald added a subscriber: wenlei.  ·  View Herald TranscriptJan 20 2023, 7:16 AM
arsenm edited the summary of this revision. (Show Details)Jan 20 2023, 7:16 AM
Harbormaster completed remote builds in B208984: Diff 490836.Jan 20 2023, 7:17 AM
Petar.Avramovic accepted this revision as: Petar.Avramovic.Jan 24 2023, 5:23 AM
This revision is now accepted and ready to land.Jan 24 2023, 5:23 AM
rovka accepted this revision as: rovka.Jan 24 2023, 6:12 AM
Thanks for the updates, LGTM with nits.
llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp


11
Nit: I like the first sentence, but the second one is a bit difficult to parse. Maybe you can rephrase it a bit?


15
Be that as it may, I'd prefer using the same string for -stop-before/after and -debug-only. As it is now we'd have to use "amdgpu-regbankselect" to run the pass and just "regbankselect" to get the debug logs.
arsenm closed this revision.Jan 30 2023, 12:18 PM
arsenm marked an inline comment as done.
e9c49901a43f5b16c3df416460b7e4dbdd24ce03
llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp


15
If I change this to amdgpu-regbankselect, -debug-only=amdgpu-regbankselect will print a fraction of the debugging information. The real debug information is in the base classes and you can't stack -debug-onlys
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Diff 490836
llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
Show First 20 Lines • Show All 611 Lines • ▼ Show 20 Linesprotected:

  /// applied.
  /// applied.

  /// \return True if the mapping was applied sucessfully, false otherwise.
  /// \return True if the mapping was applied sucessfully, false otherwise.

  bool applyMapping(MachineInstr &MI,
  bool applyMapping(MachineInstr &MI,

                    const RegisterBankInfo::InstructionMapping &InstrMapping,
                    const RegisterBankInfo::InstructionMapping &InstrMapping,

                    SmallVectorImpl<RepairingPlacement> &RepairPts);
                    SmallVectorImpl<RepairingPlacement> &RepairPts);




public:
public:

  /// Create a RegBankSelect pass with the specified \p RunningMode.
  /// Create a RegBankSelect pass with the specified \p RunningMode.

  RegBankSelect(Mode RunningMode = Fast);
  RegBankSelect(char &PassID = ID, Mode RunningMode = Fast);




  StringRef getPassName() const override { return "RegBankSelect"; }
  StringRef getPassName() const override { return "RegBankSelect"; }




  void getAnalysisUsage(AnalysisUsage &AU) const override;
  void getAnalysisUsage(AnalysisUsage &AU) const override;




  MachineFunctionProperties getRequiredProperties() const override {
  MachineFunctionProperties getRequiredProperties() const override {

    return MachineFunctionProperties()
    return MachineFunctionProperties()

        .set(MachineFunctionProperties::Property::IsSSA)
        .set(MachineFunctionProperties::Property::IsSSA)

▲ Show 20 Lines • Show All 50 Lines • Show Last 20 Lines
llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
Show First 20 Lines • Show All 62 Lines • ▼ Show 20 LinesINITIALIZE_PASS_BEGIN(RegBankSelect, DEBUG_TYPE,

                      "Assign register bank of generic virtual registers",
                      "Assign register bank of generic virtual registers",

                      false, false);
                      false, false);

INITIALIZE_PASS_DEPENDENCY(MachineBlockFrequencyInfo)
INITIALIZE_PASS_DEPENDENCY(MachineBlockFrequencyInfo)

INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)

INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)

INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,

                    "Assign register bank of generic virtual registers", false,
                    "Assign register bank of generic virtual registers", false,

                    false)
                    false)




RegBankSelect::RegBankSelect(Mode RunningMode)
RegBankSelect::RegBankSelect(char &PassID, Mode RunningMode)

rovkaUnsubmitted
Not Done
ReplyInline Actions
Where is PassID used?
rovka: Where is PassID used?
    : MachineFunctionPass(ID), OptMode(RunningMode) {
    : MachineFunctionPass(PassID), OptMode(RunningMode) {

  if (RegBankSelectMode.getNumOccurrences() != 0) {
  if (RegBankSelectMode.getNumOccurrences() != 0) {

    OptMode = RegBankSelectMode;
    OptMode = RegBankSelectMode;

    if (RegBankSelectMode != RunningMode)
    if (RegBankSelectMode != RunningMode)

      LLVM_DEBUG(dbgs() << "RegBankSelect mode overrided by command line\n");
      LLVM_DEBUG(dbgs() << "RegBankSelect mode overrided by command line\n");

  }
  }

}
}




void RegBankSelect::init(MachineFunction &MF) {
void RegBankSelect::init(MachineFunction &MF) {

▲ Show 20 Lines • Show All 1,026 Lines • Show Last 20 Lines
llvm/lib/Target/AMDGPU/AMDGPU.h
Show All 20 Lines
// GlobalISel passes
// GlobalISel passes

void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &);
void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &);

FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone);
FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone);

void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &);
void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &);

FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone);
FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone);

FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone);
FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone);

void initializeAMDGPURegBankCombinerPass(PassRegistry &);
void initializeAMDGPURegBankCombinerPass(PassRegistry &);




void initializeAMDGPURegBankSelectPass(PassRegistry &);



// SI Passes
// SI Passes

FunctionPass *createGCNDPPCombinePass();
FunctionPass *createGCNDPPCombinePass();

FunctionPass *createSIAnnotateControlFlowPass();
FunctionPass *createSIAnnotateControlFlowPass();

FunctionPass *createSIFoldOperandsPass();
FunctionPass *createSIFoldOperandsPass();

FunctionPass *createSIPeepholeSDWAPass();
FunctionPass *createSIPeepholeSDWAPass();

FunctionPass *createSILowerI1CopiesPass();
FunctionPass *createSILowerI1CopiesPass();

FunctionPass *createSIShrinkInstructionsPass();
FunctionPass *createSIShrinkInstructionsPass();

FunctionPass *createSILoadStoreOptimizerPass();
FunctionPass *createSILoadStoreOptimizerPass();

▲ Show 20 Lines • Show All 392 Lines • Show Last 20 Lines
llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.h
  • This file was added.
//===- AMDGPURegBankSelect.h -------------------------------------*- C++ -*-==//

//

// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

// See https://llvm.org/LICENSE.txt for license information.

// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

//

//===----------------------------------------------------------------------===//



#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGBANKSELECT_H

#define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGBANKSELECT_H



rovkaUnsubmitted
Done
ReplyInline Actions
Update this comment for RegBankSelect instead of InstructionSelector (ditto for the header guard)
rovka: Update this comment for RegBankSelect instead of InstructionSelector (ditto for the header…
Pierre-vhUnsubmitted
Not Done
ReplyInline Actions
It would be nice to explain why this custom pass is actually needed. If it's a stub then just say it's a stub but it's been added because it makes X or Y possible later for instance;

Otherwise it's difficult to understand why it's needed and someone might try to remove it later
Pierre-vh: It would be nice to explain why this custom pass is actually needed. If it's a stub then just…
arsenmAuthorUnsubmitted
Done
ReplyInline Actions
I'll just drop it because these style comments are useless
arsenm: I'll just drop it because these style comments are useless
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"



namespace llvm {



class AMDGPURegBankSelect final : public RegBankSelect {

public:

  static char ID;



  AMDGPURegBankSelect(Mode RunningMode = Fast);



  StringRef getPassName() const override;



  void getAnalysisUsage(AnalysisUsage &AU) const override;

  bool runOnMachineFunction(MachineFunction &MF) override;

};



} // namespace llvm

#endif

llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
  • This file was added.
//===- AMDGPURegBankSelect.cpp -----------------------------------*- C++ -*-==//

//

// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

// See https://llvm.org/LICENSE.txt for license information.

// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

//

//===----------------------------------------------------------------------===//

//

// Use MachineUniformityAnalysis as the primary basis for making SGPR vs. VGPR

// register bank selection. The use/def analyses the default RegBankSelect are a

// secondary consideration.

rovkaUnsubmitted
Done
ReplyInline Actions
Nit: I like the first sentence, but the second one is a bit difficult to parse. Maybe you can rephrase it a bit?
rovka: Nit: I like the first sentence, but the second one is a bit difficult to parse. Maybe you can…
//

//===----------------------------------------------------------------------===//



#include "AMDGPURegBankSelect.h"

rovkaUnsubmitted
Not Done
ReplyInline Actions
Nit: This diverges from AMDGPUInstructionSelector and Legalizer, which both define the DEBUG_TYPE as "amdgpu-blah" directly.
rovka: Nit: This diverges from AMDGPUInstructionSelector and Legalizer, which both define the…
arsenmAuthorUnsubmitted
Done
ReplyInline Actions
Those should probably use the generic name. Different debug types for the same pass are counterproductive
arsenm: Those should probably use the generic name. Different debug types for the same pass are…
rovkaUnsubmitted
Not Done
ReplyInline Actions
Be that as it may, I'd prefer using the same string for -stop-before/after and -debug-only. As it is now we'd have to use "amdgpu-regbankselect" to run the pass and just "regbankselect" to get the debug logs.
rovka: Be that as it may, I'd prefer using the same string for -stop-before/after and -debug-only. As…
arsenmAuthorUnsubmitted
Done
ReplyInline Actions
If I change this to amdgpu-regbankselect, -debug-only=amdgpu-regbankselect will print a fraction of the debugging information. The real debug information is in the base classes and you can't stack -debug-onlys
arsenm: If I change this to amdgpu-regbankselect, -debug-only=amdgpu-regbankselect will print a…
#include "AMDGPU.h"

#include "llvm/CodeGen/MachineUniformityAnalysis.h"

#include "llvm/InitializePasses.h"



#define DEBUG_TYPE "regbankselect"



using namespace llvm;



AMDGPURegBankSelect::AMDGPURegBankSelect(Mode RunningMode)

    : RegBankSelect(AMDGPURegBankSelect::ID, RunningMode) {}



char AMDGPURegBankSelect::ID = 0;



StringRef AMDGPURegBankSelect::getPassName() const {

  return "AMDGPURegBankSelect";

}



void AMDGPURegBankSelect::getAnalysisUsage(AnalysisUsage &AU) const {

  AU.addRequired<MachineCycleInfoWrapperPass>();

  AU.addRequired<MachineDominatorTree>();

  // TODO: Preserve DomTree

  RegBankSelect::getAnalysisUsage(AU);

}



INITIALIZE_PASS_BEGIN(AMDGPURegBankSelect, "amdgpu-" DEBUG_TYPE,

                      "AMDGPU Register Bank Select", false, false)

INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass)

INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)

INITIALIZE_PASS_END(AMDGPURegBankSelect, "amdgpu-" DEBUG_TYPE,

                    "AMDGPU Register Bank Select", false, false)



bool AMDGPURegBankSelect::runOnMachineFunction(MachineFunction &MF) {

  // If the ISel pipeline failed, do not bother running that pass.

  if (MF.getProperties().hasProperty(

          MachineFunctionProperties::Property::FailedISel))

    return false;



  LLVM_DEBUG(dbgs() << "Assign register banks for: " << MF.getName() << '\n');

  const Function &F = MF.getFunction();

  Mode SaveOptMode = OptMode;

  if (F.hasOptNone())

    OptMode = Mode::Fast;

  init(MF);



  assert(!checkFunctionIsLegal(MF));



  MachineCycleInfo &CycleInfo =

      getAnalysis<MachineCycleInfoWrapperPass>().getCycleInfo();

  MachineDominatorTree &DomTree = getAnalysis<MachineDominatorTree>();



  MachineUniformityInfo Uniformity =

      computeMachineUniformityInfo(MF, CycleInfo, DomTree.getBase());

  (void)Uniformity; // TODO: Use this



  assignRegisterBanks(MF);



  OptMode = SaveOptMode;

  return false;

}

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
Show All 13 Lines



#include "AMDGPUTargetMachine.h"
#include "AMDGPUTargetMachine.h"

#include "AMDGPU.h"
#include "AMDGPU.h"

#include "AMDGPUAliasAnalysis.h"
#include "AMDGPUAliasAnalysis.h"

#include "AMDGPUCtorDtorLowering.h"
#include "AMDGPUCtorDtorLowering.h"

#include "AMDGPUExportClustering.h"
#include "AMDGPUExportClustering.h"

#include "AMDGPUIGroupLP.h"
#include "AMDGPUIGroupLP.h"

#include "AMDGPUMacroFusion.h"
#include "AMDGPUMacroFusion.h"

#include "AMDGPURegBankSelect.h"

#include "AMDGPUTargetObjectFile.h"
#include "AMDGPUTargetObjectFile.h"

#include "AMDGPUTargetTransformInfo.h"
#include "AMDGPUTargetTransformInfo.h"

#include "GCNIterativeScheduler.h"
#include "GCNIterativeScheduler.h"

#include "GCNSchedStrategy.h"
#include "GCNSchedStrategy.h"

#include "GCNVOPDUtils.h"
#include "GCNVOPDUtils.h"

#include "R600.h"
#include "R600.h"

#include "R600MachineFunctionInfo.h"
#include "R600MachineFunctionInfo.h"

#include "R600TargetMachine.h"
#include "R600TargetMachine.h"

▲ Show 20 Lines • Show All 338 Lines • ▼ Show 20 Linesextern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {

  initializeAMDGPULowerKernelArgumentsPass(*PR);
  initializeAMDGPULowerKernelArgumentsPass(*PR);

  initializeAMDGPUPromoteKernelArgumentsPass(*PR);
  initializeAMDGPUPromoteKernelArgumentsPass(*PR);

  initializeAMDGPULowerKernelAttributesPass(*PR);
  initializeAMDGPULowerKernelAttributesPass(*PR);

  initializeAMDGPULowerIntrinsicsPass(*PR);
  initializeAMDGPULowerIntrinsicsPass(*PR);

  initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
  initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);

  initializeAMDGPUPostLegalizerCombinerPass(*PR);
  initializeAMDGPUPostLegalizerCombinerPass(*PR);

  initializeAMDGPUPreLegalizerCombinerPass(*PR);
  initializeAMDGPUPreLegalizerCombinerPass(*PR);

  initializeAMDGPURegBankCombinerPass(*PR);
  initializeAMDGPURegBankCombinerPass(*PR);

  initializeAMDGPURegBankSelectPass(*PR);

  initializeAMDGPUPromoteAllocaPass(*PR);
  initializeAMDGPUPromoteAllocaPass(*PR);

  initializeAMDGPUPromoteAllocaToVectorPass(*PR);
  initializeAMDGPUPromoteAllocaToVectorPass(*PR);

  initializeAMDGPUCodeGenPreparePass(*PR);
  initializeAMDGPUCodeGenPreparePass(*PR);

  initializeAMDGPULateCodeGenPreparePass(*PR);
  initializeAMDGPULateCodeGenPreparePass(*PR);

  initializeAMDGPUPropagateAttributesEarlyPass(*PR);
  initializeAMDGPUPropagateAttributesEarlyPass(*PR);

  initializeAMDGPUPropagateAttributesLatePass(*PR);
  initializeAMDGPUPropagateAttributesLatePass(*PR);

  initializeAMDGPUReplaceLDSUseWithPointerPass(*PR);
  initializeAMDGPUReplaceLDSUseWithPointerPass(*PR);

  initializeAMDGPULowerModuleLDSPass(*PR);
  initializeAMDGPULowerModuleLDSPass(*PR);

▲ Show 20 Lines • Show All 822 Lines • ▼ Show 20 Lines
}
}




void GCNPassConfig::addPreRegBankSelect() {
void GCNPassConfig::addPreRegBankSelect() {

  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
  bool IsOptNone = getOptLevel() == CodeGenOpt::None;

  addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
  addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));

}
}




bool GCNPassConfig::addRegBankSelect() {
bool GCNPassConfig::addRegBankSelect() {

  addPass(new RegBankSelect());
  addPass(new AMDGPURegBankSelect());

  return false;
  return false;

}
}




void GCNPassConfig::addPreGlobalInstructionSelect() {
void GCNPassConfig::addPreGlobalInstructionSelect() {

  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
  bool IsOptNone = getOptLevel() == CodeGenOpt::None;

  addPass(createAMDGPURegBankCombiner(IsOptNone));
  addPass(createAMDGPURegBankCombiner(IsOptNone));

}
}




▲ Show 20 Lines • Show All 389 Lines • Show Last 20 Lines
llvm/lib/Target/AMDGPU/CMakeLists.txt
Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Linesadd_llvm_target(AMDGPUCodeGen

  AMDGPUPerfHintAnalysis.cpp
  AMDGPUPerfHintAnalysis.cpp

  AMDGPUPostLegalizerCombiner.cpp
  AMDGPUPostLegalizerCombiner.cpp

  AMDGPUPreLegalizerCombiner.cpp
  AMDGPUPreLegalizerCombiner.cpp

  AMDGPUPrintfRuntimeBinding.cpp
  AMDGPUPrintfRuntimeBinding.cpp

  AMDGPUPromoteAlloca.cpp
  AMDGPUPromoteAlloca.cpp

  AMDGPUPropagateAttributes.cpp
  AMDGPUPropagateAttributes.cpp

  AMDGPUPromoteKernelArguments.cpp
  AMDGPUPromoteKernelArguments.cpp

  AMDGPURegBankCombiner.cpp
  AMDGPURegBankCombiner.cpp

  AMDGPURegBankSelect.cpp

  AMDGPURegisterBankInfo.cpp
  AMDGPURegisterBankInfo.cpp

  AMDGPUReleaseVGPRs.cpp
  AMDGPUReleaseVGPRs.cpp

  AMDGPUReplaceLDSUseWithPointer.cpp
  AMDGPUReplaceLDSUseWithPointer.cpp

  AMDGPUResourceUsageAnalysis.cpp
  AMDGPUResourceUsageAnalysis.cpp

  AMDGPURewriteOutArguments.cpp
  AMDGPURewriteOutArguments.cpp

  AMDGPURewriteUndefForPHI.cpp
  AMDGPURewriteUndefForPHI.cpp

  AMDGPUSetWavePriority.cpp
  AMDGPUSetWavePriority.cpp

  AMDGPUSubtarget.cpp
  AMDGPUSubtarget.cpp

▲ Show 20 Lines • Show All 99 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s

---
---

name: add_s16_ss
name: add_s16_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

    ; CHECK-LABEL: name: add_s16_ss
    ; CHECK-LABEL: name: add_s16_ss

▲ Show 20 Lines • Show All 92 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s




---
---

name: add_s32_ss
name: add_s32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 66 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: add_v2s16_ss
name: add_v2s16_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 80 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: exp_compr_v2f16_s
name: exp_compr_v2f16_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3

Show All 29 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




--- |
--- |

  define void @exp_s() {
  define void @exp_s() {

    call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float 1.0, float 1.0, float 1.0, float 1.0, i1 0, i1 0)
    call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float 1.0, float 1.0, float 1.0, float 1.0, i1 0, i1 0)

    ret void
    ret void

  }
  }

  define void @exp_v() {
  define void @exp_v() {

    call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float 1.0, float 1.0, float 1.0, float 1.0, i1 0, i1 0)
    call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float 1.0, float 1.0, float 1.0, float 1.0, i1 0, i1 0)

▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: buffer_load_ss
name: buffer_load_ss

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4

▲ Show 20 Lines • Show All 147 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o -  %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o -  %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o -  %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o -  %s | FileCheck %s




---
---

name:            ballot_sgpr_src
name:            ballot_sgpr_src

legalized:       true
legalized:       true

tracksRegLiveness: true
tracksRegLiveness: true

body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

▲ Show 20 Lines • Show All 56 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: class_ss
name: class_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1, $sgpr2
    liveins: $sgpr0_sgpr1, $sgpr2

▲ Show 20 Lines • Show All 69 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: cvt_pkrtz_ss
name: cvt_pkrtz_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 65 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -verify-machineinstrs -regbankselect-fast -o - %s  | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -verify-machineinstrs -regbankselect-fast -o - %s  | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s | FileCheck %s




---
---

name: div_fmas_sss_scc
name: div_fmas_sss_scc

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3

▲ Show 20 Lines • Show All 109 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: div_scale_ss
name: div_scale_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 68 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast  -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast  -verify-machineinstrs %s -o - | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy  -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy  -verify-machineinstrs %s -o - | FileCheck %s




---
---

name: ds_append_s
name: ds_append_s

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 27 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast  -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast  -verify-machineinstrs %s -o - | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy  -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy  -verify-machineinstrs %s -o - | FileCheck %s




---
---

name: ds_bpermute_ss
name: ds_bpermute_ss

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

Show All 14 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast  -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast  -verify-machineinstrs %s -o - | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy  -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy  -verify-machineinstrs %s -o - | FileCheck %s




---
---

name: ds_consume_s
name: ds_consume_s

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 27 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: ds_gws_init_s_s
name: ds_gws_init_s_s

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

▲ Show 20 Lines • Show All 72 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: ds_gws_init_s
name: ds_gws_init_s

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

Show All 28 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: ds_ordered_add_ss
name: ds_ordered_add_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 68 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: ds_ordered_swap_ss
name: ds_ordered_swap_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 68 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast  -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast  -verify-machineinstrs %s -o - | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy  -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy  -verify-machineinstrs %s -o - | FileCheck %s




---
---

name: ds_permute_ss
name: ds_permute_ss

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

Show All 14 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast  -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast  -verify-machineinstrs %s -o - | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy  -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy  -verify-machineinstrs %s -o - | FileCheck %s




---
---

name: ds_swizzle_s
name: ds_swizzle_s

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 11 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: else
name: else

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 9 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s

---
---

name: else
name: else

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1
    liveins: $sgpr0_sgpr1

    ; CHECK-LABEL: name: else
    ; CHECK-LABEL: name: else

    ; CHECK: liveins: $sgpr0_sgpr1
    ; CHECK: liveins: $sgpr0_sgpr1

    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: {{  $}}

    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1

    ; CHECK-NEXT: [[INT:%[0-9]+]]:vcc(s1), [[INT1:%[0-9]+]]:sgpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.else), [[COPY]](s64)
    ; CHECK-NEXT: [[INT:%[0-9]+]]:vcc(s1), [[INT1:%[0-9]+]]:sgpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.else), [[COPY]](s64)

    %0:_(s64) = COPY $sgpr0_sgpr1
    %0:_(s64) = COPY $sgpr0_sgpr1

    %1:_(s1), %2:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.else), %0
    %1:_(s1), %2:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.else), %0




...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy  -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy  -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: fcmp_ss
name: fcmp_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 68 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: fmul_legacy_ss
name: fmul_legacy_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 65 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o -  %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o -  %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o -  %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o -  %s | FileCheck %s




---
---

name: groupstaticsize
name: groupstaticsize

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    ; CHECK-LABEL: name: groupstaticsize
    ; CHECK-LABEL: name: groupstaticsize

    ; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.groupstaticsize)
    ; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.groupstaticsize)

    %0:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.groupstaticsize)
    %0:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.groupstaticsize)

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: icmp_ss
name: icmp_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 68 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=regbankselect -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=amdgpu-regbankselect -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=regbankselect -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=amdgpu-regbankselect -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s




; Natural mapping
; Natural mapping

define amdgpu_ps void @load_1d_vgpr_vaddr__sgpr_srsrc(<8 x i32> inreg %rsrc, i32 %s) {
define amdgpu_ps void @load_1d_vgpr_vaddr__sgpr_srsrc(<8 x i32> inreg %rsrc, i32 %s) {

  ; FAST-LABEL: name: load_1d_vgpr_vaddr__sgpr_srsrc
  ; FAST-LABEL: name: load_1d_vgpr_vaddr__sgpr_srsrc

  ; FAST: bb.1 (%ir-block.0):
  ; FAST: bb.1 (%ir-block.0):

  ; FAST-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0
  ; FAST-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0

  ; FAST-NEXT: {{  $}}
  ; FAST-NEXT: {{  $}}

  ; FAST-NEXT:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; FAST-NEXT:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

▲ Show 20 Lines • Show All 348 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=amdgpu-regbankselect -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=amdgpu-regbankselect -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s




; Natural mapping
; Natural mapping

define amdgpu_ps void @sample_1d_vgpr_vaddr__sgpr_rsrc__sgpr_samp(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {
define amdgpu_ps void @sample_1d_vgpr_vaddr__sgpr_rsrc__sgpr_samp(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {

  ; FAST-LABEL: name: sample_1d_vgpr_vaddr__sgpr_rsrc__sgpr_samp
  ; FAST-LABEL: name: sample_1d_vgpr_vaddr__sgpr_rsrc__sgpr_samp

  ; FAST: bb.1 (%ir-block.0):
  ; FAST: bb.1 (%ir-block.0):

  ; FAST-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0
  ; FAST-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0

  ; FAST-NEXT: {{  $}}
  ; FAST-NEXT: {{  $}}

  ; FAST-NEXT:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; FAST-NEXT:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

▲ Show 20 Lines • Show All 523 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: interp_mov_ss
name: interp_mov_ss

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

Show All 30 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: interp_p1_f16_ss
name: interp_p1_f16_ss

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

Show All 34 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: interp_p1_ss
name: interp_p1_ss

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

▲ Show 20 Lines • Show All 72 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: interp_p2_f16_sss
name: interp_p2_f16_sss

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

Show All 40 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: interp_p2_sss
name: interp_p2_sss

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

Show All 39 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kernarg.segment.ptr.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: kernarg_segment_ptr
name: kernarg_segment_ptr

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    ; CHECK-LABEL: name: kernarg_segment_ptr
    ; CHECK-LABEL: name: kernarg_segment_ptr

    ; CHECK: [[INT:%[0-9]+]]:sgpr(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
    ; CHECK: [[INT:%[0-9]+]]:sgpr(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)

    %2:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
    %2:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o -  %s| FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o -  %s| FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o -  %s| FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o -  %s| FileCheck %s




---
---

name: kill_scc
name: kill_scc

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: lds_direct_load_s
name: lds_direct_load_s

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

Show All 27 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: lds_param_load_s
name: lds_param_load_s

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

Show All 27 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: live_mask
name: live_mask

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    ; CHECK-LABEL: name: live_mask
    ; CHECK-LABEL: name: live_mask

    ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.live.mask)
    ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.live.mask)

    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INT]](s1)
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INT]](s1)

    %0:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.live.mask)
    %0:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.live.mask)

    S_ENDPGM 0, implicit %0
    S_ENDPGM 0, implicit %0

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx90a -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=FAST
# RUN: llc -march=amdgcn -mcpu=gfx90a -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=FAST

# RUN: llc -march=amdgcn -mcpu=gfx90a -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GREEDY
# RUN: llc -march=amdgcn -mcpu=gfx90a -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GREEDY




---
---

name: mfma_f32_32x32x4bf16_1k_vva
name: mfma_f32_32x32x4bf16_1k_vva

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true

body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31

▲ Show 20 Lines • Show All 209 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx940.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx940 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=FAST
# RUN: llc -march=amdgcn -mcpu=gfx940 -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=FAST

# RUN: llc -march=amdgcn -mcpu=gfx940 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GREEDY
# RUN: llc -march=amdgcn -mcpu=gfx940 -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GREEDY




---
---

name: mfma_i32_16x16x32_i8_vva
name: mfma_i32_16x16x32_i8_vva

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true

body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr1_vgpr2, $vgpr2_vgpr3, $agpr0_agpr1_agpr2_agpr3
    liveins: $vgpr1_vgpr2, $vgpr2_vgpr3, $agpr0_agpr1_agpr2_agpr3

▲ Show 20 Lines • Show All 320 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck %s




---
---

name: mfma_f32_32x32x1f32_vva
name: mfma_f32_32x32x1f32_vva

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true

body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31
    liveins: $vgpr0, $vgpr1, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31

▲ Show 20 Lines • Show All 972 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: ps_live
name: ps_live

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    ; CHECK-LABEL: name: ps_live
    ; CHECK-LABEL: name: ps_live

    ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.ps.live)
    ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.ps.live)

    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INT]](s1)
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[INT]](s1)

    %0:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.ps.live)
    %0:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.ps.live)

    S_ENDPGM 0, implicit %0
    S_ENDPGM 0, implicit %0

...
...




llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-fast -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=amdgpu-regbankselect -regbankselect-fast -o - %s | FileCheck %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-greedy -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=amdgpu-regbankselect -regbankselect-greedy -o - %s | FileCheck %s




; Natural mapping
; Natural mapping

define amdgpu_ps float @raw_buffer_load__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @raw_buffer_load__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: raw_buffer_load__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: raw_buffer_load__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
  ; CHECK-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0

  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: {{  $}}

  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

▲ Show 20 Lines • Show All 201 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: readfirstlane_s
name: readfirstlane_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 25 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: readlane_ss
name: readlane_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 151 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -simplify-mir -stop-after=regbankselect -regbankselect-fast -o - %s | FileCheck %s
; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -simplify-mir -stop-after=amdgpu-regbankselect -regbankselect-fast -o - %s | FileCheck %s

; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -simplify-mir -stop-after=regbankselect -regbankselect-greedy -o - %s | FileCheck %s --check-prefix=GREEDY
; RUN: llc -amdgpu-global-isel-new-legality -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -simplify-mir -stop-after=amdgpu-regbankselect -regbankselect-greedy -o - %s | FileCheck %s --check-prefix=GREEDY




; Natural mapping
; Natural mapping

define amdgpu_ps i32 @s_buffer_load_i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {
define amdgpu_ps i32 @s_buffer_load_i32(<4 x i32> inreg %rsrc, i32 inreg %soffset) {

  ; CHECK-LABEL: name: s_buffer_load_i32
  ; CHECK-LABEL: name: s_buffer_load_i32

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6
  ; CHECK-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6

  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: {{  $}}

  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

▲ Show 20 Lines • Show All 3,154 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=regbankselect -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-regbankselect -regbankselect-fast -o - %s | FileCheck -check-prefix=FAST %s

# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=regbankselect -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-regbankselect -regbankselect-greedy -o - %s | FileCheck -check-prefix=GREEDY %s




# We see the offset is a VGPR, but this is due to a constant for some
# We see the offset is a VGPR, but this is due to a constant for some

# reason ending up in a VGPR. This shouldn't really ever happen, but
# reason ending up in a VGPR. This shouldn't really ever happen, but

# make sure this doesn't break when looking through copies for the add
# make sure this doesn't break when looking through copies for the add

# operands.
# operands.




---
---

name:            s_buffer_load_f32_vgpr_offset_cross_bank_copy_add_offset
name:            s_buffer_load_f32_vgpr_offset_cross_bank_copy_add_offset

▲ Show 20 Lines • Show All 80 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o -  %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o -  %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o -  %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o -  %s | FileCheck %s




---
---

name: s_get_waveid_in_workgroup
name: s_get_waveid_in_workgroup

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    ; CHECK-LABEL: name: s_get_waveid_in_workgroup
    ; CHECK-LABEL: name: s_get_waveid_in_workgroup

    ; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.get.waveid.in.workgroup)
    ; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.get.waveid.in.workgroup)

    %0:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.get.waveid.in.workgroup)
    %0:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.get.waveid.in.workgroup)

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o -  %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o -  %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o -  %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o -  %s | FileCheck %s




---
---

name: getpc
name: getpc

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    ; CHECK-LABEL: name: getpc
    ; CHECK-LABEL: name: getpc

    ; CHECK: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.getpc)
    ; CHECK: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.getpc)

    %0:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.getpc)
    %0:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.getpc)

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o -  %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o -  %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o -  %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o -  %s | FileCheck %s




---
---

name: getreg
name: getreg

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    ; CHECK-LABEL: name: getreg
    ; CHECK-LABEL: name: getreg

    ; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
    ; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0

    %0:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
    %0:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o -  %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o -  %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o -  %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o -  %s | FileCheck %s




---
---

name: memrealtime
name: memrealtime

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    ; CHECK-LABEL: name: memrealtime
    ; CHECK-LABEL: name: memrealtime

    ; CHECK: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.memrealtime)
    ; CHECK: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.memrealtime)

    %0:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.memrealtime)
    %0:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.memrealtime)

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o -  %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o -  %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o -  %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o -  %s | FileCheck %s




---
---

name: memtime
name: memtime

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    ; CHECK-LABEL: name: memtime
    ; CHECK-LABEL: name: memtime

    ; CHECK: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.memtime)
    ; CHECK: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.memtime)

    %0:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.memtime)
    %0:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.memtime)

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: sendmsg_s
name: sendmsg_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 25 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: sendmsghalt_s
name: sendmsghalt_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 25 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-fast -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=amdgpu-regbankselect -regbankselect-fast -o - %s | FileCheck %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-greedy -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=amdgpu-regbankselect -regbankselect-greedy -o - %s | FileCheck %s




; Natural mapping
; Natural mapping

define amdgpu_ps float @struct_buffer_load__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps float @struct_buffer_load__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_load__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_load__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
  ; CHECK-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1

  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: {{  $}}

  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

▲ Show 20 Lines • Show All 197 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-fast -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=amdgpu-regbankselect -regbankselect-fast -o - %s | FileCheck %s

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=regbankselect -regbankselect-greedy -o - %s | FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -stop-after=amdgpu-regbankselect -regbankselect-greedy -o - %s | FileCheck %s




; Natural mapping
; Natural mapping

define amdgpu_ps void @struct_buffer_store__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, float %val, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
define amdgpu_ps void @struct_buffer_store__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, float %val, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

  ; CHECK-LABEL: name: struct_buffer_store__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset
  ; CHECK-LABEL: name: struct_buffer_store__sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset

  ; CHECK: bb.1 (%ir-block.0):
  ; CHECK: bb.1 (%ir-block.0):

  ; CHECK-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
  ; CHECK-NEXT:   liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2

  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: {{  $}}

  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2

▲ Show 20 Lines • Show All 198 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s




---
---

name: update_dpp_ss
name: update_dpp_ss

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 76 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o -  %s| FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o -  %s| FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o -  %s| FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o -  %s| FileCheck %s




---
---

name: wqm_demote_scc
name: wqm_demote_scc

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: wqm_s
name: wqm_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 25 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: wqm_vote_scc
name: wqm_vote_scc

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 53 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: writelane_sss
name: writelane_sss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr2
    liveins: $sgpr0, $sgpr1, $sgpr2

▲ Show 20 Lines • Show All 97 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: strict_wwm_s
name: strict_wwm_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 25 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: ffbh_u32_s
name: ffbh_u32_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 25 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: ffbl_b32_s
name: ffbl_b32_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 25 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -o - %s | FileCheck %s




# TODO: We could use scalar
# TODO: We could use scalar

---
---

name: amdgpu_wave_address
name: amdgpu_wave_address

legalized: true
legalized: true

body: |
body: |

  bb.0:
  bb.0:

    ; CHECK-LABEL: name: amdgpu_wave_address
    ; CHECK-LABEL: name: amdgpu_wave_address

Show All 21 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: and_s1_sgpr_sgpr
name: and_s1_sgpr_sgpr

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 311 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: and_s32_ss
name: and_s32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 643 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: anyext_s32_to_s64_s
name: anyext_s32_to_s64_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

▲ Show 20 Lines • Show All 268 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=regbankselect -regbankselect-fast -o -  %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=amdgpu-regbankselect -regbankselect-fast -o -  %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=regbankselect -regbankselect-greedy -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=amdgpu-regbankselect -regbankselect-greedy -o - %s | FileCheck %s




---
---

name: ashr_s32_ss
name: ashr_s32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 273 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx90a -run-pass=regbankselect %s -verify-machineinstrs -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx90a -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - | FileCheck %s




---
---

name:            assert_align_vgpr
name:            assert_align_vgpr

alignment:       4
alignment:       4

legalized:       true
legalized:       true

tracksRegLiveness: true
tracksRegLiveness: true

body:             |
body:             |

  bb.0:
  bb.0:

▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx90a -run-pass=regbankselect %s -verify-machineinstrs -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx90a -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - | FileCheck %s




---
---

name:            assert_zext_vgpr
name:            assert_zext_vgpr

alignment:       4
alignment:       4

legalized:       true
legalized:       true

tracksRegLiveness: true
tracksRegLiveness: true

body:             |
body:             |

  bb.0:
  bb.0:

▲ Show 20 Lines • Show All 92 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: atomic_cmpxchg_global_i32_sss
name: atomic_cmpxchg_global_i32_sss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
    liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3

▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: atomicrmw_add_global_i32_ss
name: atomicrmw_add_global_i32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1, $sgpr2
    liveins: $sgpr0_sgpr1, $sgpr2

▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: atomicrmw_and_global_i32_ss
name: atomicrmw_and_global_i32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1, $sgpr2
    liveins: $sgpr0_sgpr1, $sgpr2

▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: atomicrmw_fadd_local_i32_ss
name: atomicrmw_fadd_local_i32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

Show All 12 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: atomicrmw_max_global_i32_ss
name: atomicrmw_max_global_i32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1, $sgpr2
    liveins: $sgpr0_sgpr1, $sgpr2

▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: atomicrmw_min_global_i32_ss
name: atomicrmw_min_global_i32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1, $sgpr2
    liveins: $sgpr0_sgpr1, $sgpr2

▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: atomicrmw_or_global_i32_ss
name: atomicrmw_or_global_i32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1, $sgpr2
    liveins: $sgpr0_sgpr1, $sgpr2

▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: atomicrmw_sub_global_i32_ss
name: atomicrmw_sub_global_i32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1, $sgpr2
    liveins: $sgpr0_sgpr1, $sgpr2

▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: atomicrmw_umax_global_i32_ss
name: atomicrmw_umax_global_i32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1, $sgpr2
    liveins: $sgpr0_sgpr1, $sgpr2

▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: atomicrmw_umin_global_i32_ss
name: atomicrmw_umin_global_i32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1, $sgpr2
    liveins: $sgpr0_sgpr1, $sgpr2

▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: atomicrmw_xchg_global_i32_ss
name: atomicrmw_xchg_global_i32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1, $sgpr2
    liveins: $sgpr0_sgpr1, $sgpr2

▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: atomicrmw_xor_global_i32_ss
name: atomicrmw_xor_global_i32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1, $sgpr2
    liveins: $sgpr0_sgpr1, $sgpr2

▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: bitcast_s
name: bitcast_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 24 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: bitreverse_i32_s
name: bitreverse_i32_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

▲ Show 20 Lines • Show All 59 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -O0 -march amdgcn -mcpu=fiji -run-pass=regbankselect %s -o - | FileCheck %s
# RUN: llc -O0 -march amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -o - | FileCheck %s




--- |
--- |




  @addr = global ptr null
  @addr = global ptr null




  define void @test_blockaddress() {
  define void @test_blockaddress() {

    store ptr blockaddress(@test_blockaddress, %block), ptr @addr
    store ptr blockaddress(@test_blockaddress, %block), ptr @addr

    indirectbr ptr blockaddress(@test_blockaddress, %block), [label %block]
    indirectbr ptr blockaddress(@test_blockaddress, %block), [label %block]

Show All 19 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: brcond_vcc_cond
name: brcond_vcc_cond

legalized: true
legalized: true

body:             |
body:             |

  ; CHECK-LABEL: name: brcond_vcc_cond
  ; CHECK-LABEL: name: brcond_vcc_cond

  ; CHECK: bb.0.entry:
  ; CHECK: bb.0.entry:

  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)

▲ Show 20 Lines • Show All 198 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: bswap_i32_s
name: bswap_i32_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 25 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: build_vector_v2s32_ss
name: build_vector_v2s32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 316 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: concat_vectors_v4s16_ss
name: concat_vectors_v4s16_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

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llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: test_constant_s32_vgpr_use
name: test_constant_s32_vgpr_use

legalized:       true
legalized:       true

body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: test_constant_s32_vgpr_use
    ; CHECK-LABEL: name: test_constant_s32_vgpr_use

Show All 24 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck %s




---
---

name: copy_s32_vgpr_to_vgpr
name: copy_s32_vgpr_to_vgpr

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0

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llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-undef.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: ctlz_zero_undef_s32_s
name: ctlz_zero_undef_s32_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

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llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: ctpop_s32_s
name: ctpop_s32_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

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llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: cttz_zero_undef_s32_s
name: cttz_zero_undef_s32_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

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llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -O0 -march amdgcn -mcpu=fiji -run-pass=regbankselect %s -o - | FileCheck %s
# RUN: llc -O0 -march amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -o - | FileCheck %s




# Check the default mappings for various instructions.
# Check the default mappings for various instructions.




---
---

name:            test_fconstant_f32_1
name:            test_fconstant_f32_1

legalized:       true
legalized:       true

body: |
body: |

  bb.0:
  bb.0:

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llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=WAVE64 %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=WAVE64 %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=WAVE64 %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=WAVE64 %s

# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=WAVE32 %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=WAVE32 %s

# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=WAVE32 %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=WAVE32 %s







---
---

name: test_dyn_stackalloc_sgpr_align1
name: test_dyn_stackalloc_sgpr_align1

legalized:       true
legalized:       true

frameInfo:
frameInfo:

  maxAlignment: 2
  maxAlignment: 2

stack:
stack:

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llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=WAVE64 %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=WAVE64 %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=WAVE64 %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=WAVE64 %s

# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=WAVE32 %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=WAVE32 %s

# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=WAVE32 %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=WAVE32 %s







---
---

name: extract_vector_elt_v16s32_ss
name: extract_vector_elt_v16s32_ss

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

▲ Show 20 Lines • Show All 1,259 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: extract_lo32_i64_s
name: extract_lo32_i64_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1
    liveins: $sgpr0_sgpr1

▲ Show 20 Lines • Show All 74 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: fabs_s
name: fabs_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1
    liveins: $sgpr0_sgpr1

Show All 28 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: fadd_ss
name: fadd_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 68 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: fcanonicalize_s
name: fcanonicalize_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1
    liveins: $sgpr0_sgpr1

Show All 29 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: fceil_s
name: fceil_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 25 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: fcmp_ss
name: fcmp_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 68 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: fexp2_s
name: fexp2_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 25 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: flog2_s
name: flog2_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 25 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: fma_sss
name: fma_sss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr2
    liveins: $sgpr0, $sgpr1, $sgpr2

▲ Show 20 Lines • Show All 157 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: fmul_ss
name: fmul_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 68 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: fneg_s
name: fneg_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1
    liveins: $sgpr0_sgpr1

Show All 28 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: fpext_s
name: fpext_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 25 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: fptosi_s
name: fptosi_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 25 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: fptoui_s
name: fptoui_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 25 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: fptrunc_s
name: fptrunc_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1
    liveins: $sgpr0_sgpr1

Show All 25 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




--- |
--- |

  target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
  target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"

  define void @test_frame_index_p5() {
  define void @test_frame_index_p5() {

      %ptr0 = alloca i32, addrspace(5)
      %ptr0 = alloca i32, addrspace(5)

     ret void
     ret void

    }
    }

...
...

Show All 12 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=regbankselect %s -o - | FileCheck %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-regbankselect %s -o - | FileCheck %s

# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=regbankselect %s -o - | FileCheck %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=amdgpu-regbankselect %s -o - | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=regbankselect %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-regbankselect %s -o - | FileCheck %s




---
---

name: test_freeze_s1_vgpr_to_vgpr
name: test_freeze_s1_vgpr_to_vgpr

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0

▲ Show 20 Lines • Show All 636 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frint.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: frint_s
name: frint_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 25 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: fshr_sss
name: fshr_sss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr2
    liveins: $sgpr0, $sgpr1, $sgpr2

▲ Show 20 Lines • Show All 157 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: fsqrt_s
name: fsqrt_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1
    liveins: $sgpr0_sgpr1

Show All 29 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: fsub_ss
name: fsub_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 68 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s

# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s




---
---

name: icmp_eq_s32_ss
name: icmp_eq_s32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 471 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect  -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect  -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy  -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8  %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy  -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8  %s




---
---

name: icmp_eq_s16_ss
name: icmp_eq_s16_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 84 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
# RUN: not --crash llc -march=amdgcn -run-pass=regbankselect  -regbankselect-fast  %s -o /dev/null 2>&1 | FileCheck %s
# RUN: not --crash llc -march=amdgcn -run-pass=amdgpu-regbankselect  -regbankselect-fast  %s -o /dev/null 2>&1 | FileCheck %s

# RUN: not --crash llc -march=amdgcn -run-pass=regbankselect  -regbankselect-greedy  %s -o /dev/null 2>&1 | FileCheck %s
# RUN: not --crash llc -march=amdgcn -run-pass=amdgpu-regbankselect  -regbankselect-greedy  %s -o /dev/null 2>&1 | FileCheck %s




# Check behavior for illegal copies.
# Check behavior for illegal copies.




# CHECK: LLVM ERROR: unable to map instruction: $sgpr0 = COPY %0:vgpr(s32) (in function: illegal_copy_s32_v_to_s)
# CHECK: LLVM ERROR: unable to map instruction: $sgpr0 = COPY %0:vgpr(s32) (in function: illegal_copy_s32_v_to_s)




---
---

name: illegal_copy_s32_v_to_s
name: illegal_copy_s32_v_to_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    %0:_(s32) = COPY $vgpr0
    %0:_(s32) = COPY $vgpr0

    $sgpr0 = COPY %0
    $sgpr0 = COPY %0

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefixes=CHECK,FAST %s
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefixes=CHECK,FAST %s

# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefixes=CHECK,GREEDY %s
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefixes=CHECK,GREEDY %s




---
---

name: test_implicit_def_s32_vgpr_use
name: test_implicit_def_s32_vgpr_use

legalized:       true
legalized:       true

body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1
    liveins: $vgpr0_vgpr1




▲ Show 20 Lines • Show All 209 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: insert_vector_elt_v4i32_s_s_s
name: insert_vector_elt_v4i32_s_s_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, $sgpr5
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, $sgpr5

▲ Show 20 Lines • Show All 800 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: insert_lo32_i64_ss
name: insert_lo32_i64_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1, $sgpr2
    liveins: $sgpr0_sgpr1, $sgpr2

▲ Show 20 Lines • Show All 176 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: intrinsic_trunc_s
name: intrinsic_trunc_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 25 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: inttoptr_s
name: inttoptr_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1
    liveins: $sgpr0_sgpr1

Show All 24 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




--- |
--- |

  define amdgpu_kernel void @load_global_v8i32_non_uniform(ptr addrspace(1) %in) {
  define amdgpu_kernel void @load_global_v8i32_non_uniform(ptr addrspace(1) %in) {

    %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0
    %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0

    %global.not.uniform.v8i32 = getelementptr <8 x i32>, ptr addrspace(1) %in, i32 %tmp0
    %global.not.uniform.v8i32 = getelementptr <8 x i32>, ptr addrspace(1) %in, i32 %tmp0

    %tmp2 = load <8 x i32>, ptr addrspace(1) %global.not.uniform.v8i32
    %tmp2 = load <8 x i32>, ptr addrspace(1) %global.not.uniform.v8i32

    ret void
    ret void

  }
  }

▲ Show 20 Lines • Show All 914 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=regbankselect -regbankselect-fast -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=amdgpu-regbankselect -regbankselect-fast -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=regbankselect -regbankselect-greedy -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=amdgpu-regbankselect -regbankselect-greedy -o - %s | FileCheck %s




---
---

name: lshr_s32_ss
name: lshr_s32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 275 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX8 %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX8 %s

# RUN: llc -march=amdgcn -mcpu=gfx90a -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX9MI %s
# RUN: llc -march=amdgcn -mcpu=gfx90a -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX9MI %s

# RUN: llc -march=amdgcn -mcpu=gfx1030 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX10 %s
# RUN: llc -march=amdgcn -mcpu=gfx1030 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck --check-prefixes=CHECK,GFX10 %s




---
---

name: mad_u64_u32_sss
name: mad_u64_u32_sss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3

▲ Show 20 Lines • Show All 590 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: merge_s64_s32_s32_ss
name: merge_s64_s32_s32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

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llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s




---
---

name: mul_s32_ss
name: mul_s32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 66 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: or_s32_ss
name: or_s32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 809 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=FAST %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=FAST %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GREEDY %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GREEDY %s




---
---

name: phi_s1_scc_scc_sbranch
name: phi_s1_scc_scc_sbranch

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  ; FAST-LABEL: name: phi_s1_scc_scc_sbranch
  ; FAST-LABEL: name: phi_s1_scc_scc_sbranch

▲ Show 20 Lines • Show All 1,746 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=FAST %s
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=FAST %s

# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GREEDY %s
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GREEDY %s




---
---

name: phi_s32_ss_sbranch
name: phi_s32_ss_sbranch

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  ; FAST-LABEL: name: phi_s32_ss_sbranch
  ; FAST-LABEL: name: phi_s32_ss_sbranch

▲ Show 20 Lines • Show All 3,009 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: gep_p1_s_k
name: gep_p1_s_k

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1
    liveins: $sgpr0_sgpr1

▲ Show 20 Lines • Show All 89 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: ptrmask_p1_s_k
name: ptrmask_p1_s_k

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1
    liveins: $sgpr0_sgpr1

▲ Show 20 Lines • Show All 89 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: ptrtoint_s
name: ptrtoint_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1
    liveins: $sgpr0_sgpr1

Show All 24 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: reg_sequence_ss_vreg
name: reg_sequence_ss_vreg

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

▲ Show 20 Lines • Show All 137 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s




---
---

name: sadde_s32_sss
name: sadde_s32_sss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr2
    liveins: $sgpr0, $sgpr1, $sgpr2

▲ Show 20 Lines • Show All 171 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




...
...




# Generate the 3 operand vector bitfield extract instructions for 32-bit
# Generate the 3 operand vector bitfield extract instructions for 32-bit

# operations only.
# operations only.

---
---

name:            test_sbfx_s32_vvv
name:            test_sbfx_s32_vvv

legalized: true
legalized: true

▲ Show 20 Lines • Show All 357 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s




---
---

name: select_s32_scc_ss
name: select_s32_scc_ss

legalized: true
legalized: true

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3

    ; FAST-LABEL: name: select_s32_scc_ss
    ; FAST-LABEL: name: select_s32_scc_ss

▲ Show 20 Lines • Show All 1,865 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: sext_inreg_s_s32_1
name: sext_inreg_s_s32_1

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

▲ Show 20 Lines • Show All 255 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: sext_s32_to_s64_s
name: sext_s32_to_s64_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

▲ Show 20 Lines • Show All 309 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect  -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect  -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect  -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect  -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: sextload_constant_i8_to_i32_uniform
name: sextload_constant_i8_to_i32_uniform

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1
    liveins: $sgpr0_sgpr1

▲ Show 20 Lines • Show All 98 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=regbankselect -regbankselect-fast -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=amdgpu-regbankselect -regbankselect-fast -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=regbankselect -regbankselect-greedy -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=amdgpu-regbankselect -regbankselect-greedy -o - %s | FileCheck %s




---
---

name: shl_s32_ss
name: shl_s32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 271 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: sitofp_s
name: sitofp_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 25 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-fast -o - %s  | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=amdgpu-regbankselect -verify-machineinstrs -regbankselect-fast -o - %s  | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s  | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=amdgpu-regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s  | FileCheck %s




---
---

name: smax_s32_ss
name: smax_s32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 255 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-fast -o - %s  | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=amdgpu-regbankselect -verify-machineinstrs -regbankselect-fast -o - %s  | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s  | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=amdgpu-regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s  | FileCheck %s




---
---

name: smin_s32_ss
name: smin_s32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 258 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s

# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s




# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s




---
---

name: smulh_s32_ss
name: smulh_s32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 98 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -run-pass=regbankselect %s -o - | FileCheck -check-prefix=SI %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -run-pass=amdgpu-regbankselect %s -o - | FileCheck -check-prefix=SI %s




--- |
--- |




  define amdgpu_ps i96 @split_smrd_load_range(ptr addrspace(4) %ptr) {
  define amdgpu_ps i96 @split_smrd_load_range(ptr addrspace(4) %ptr) {

    %load = load i96, ptr addrspace(4) %ptr, !range !0
    %load = load i96, ptr addrspace(4) %ptr, !range !0

    ret i96 %load
    ret i96 %load

  }
  }




▲ Show 20 Lines • Show All 60 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s




---
---

name: ssube_s32_sss
name: ssube_s32_sss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr2
    liveins: $sgpr0, $sgpr1, $sgpr2

▲ Show 20 Lines • Show All 171 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s




---
---

name: sub_s32_ss
name: sub_s32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

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llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: trunc_i64_to_i32_s
name: trunc_i64_to_i32_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1
    liveins: $sgpr0_sgpr1

▲ Show 20 Lines • Show All 87 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s

---
---

name: uadde_s32_sss
name: uadde_s32_sss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr2
    liveins: $sgpr0, $sgpr1, $sgpr2

    ; FAST-LABEL: name: uadde_s32_sss
    ; FAST-LABEL: name: uadde_s32_sss

▲ Show 20 Lines • Show All 170 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: uaddo_s32_ss
name: uaddo_s32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 67 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




...
...




# Generate the 3 operand vector bitfield extract instructions for 32-bit
# Generate the 3 operand vector bitfield extract instructions for 32-bit

# operations only.
# operations only.

---
---

name:            test_ubfx_s32_vvv
name:            test_ubfx_s32_vvv

legalized: true
legalized: true

▲ Show 20 Lines • Show All 357 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: uitofp_s
name: uitofp_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

Show All 25 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-fast -o - %s  | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=amdgpu-regbankselect -verify-machineinstrs -regbankselect-fast -o - %s  | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s  | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=amdgpu-regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s  | FileCheck %s




---
---

name: umax_s32_ss
name: umax_s32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 260 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-fast -o - %s  | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=amdgpu-regbankselect -verify-machineinstrs -regbankselect-fast -o - %s  | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s  | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=amdgpu-regbankselect -verify-machineinstrs -regbankselect-greedy -o - %s  | FileCheck %s




---
---

name: umin_s32_ss
name: umin_s32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 264 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s

# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s




# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=amdgpu-regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=amdgpu-regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s




---
---

name: umulh_s32_ss
name: umulh_s32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 98 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=kaveri -run-pass=regbankselect -mattr=+unaligned-access-mode %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX7 %s
# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=kaveri -run-pass=amdgpu-regbankselect -mattr=+unaligned-access-mode %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX7 %s

# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -run-pass=regbankselect -mattr=+unaligned-access-mode %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX1010 %s
# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -run-pass=amdgpu-regbankselect -mattr=+unaligned-access-mode %s -verify-machineinstrs -o - | FileCheck -check-prefixes=GFX1010 %s




---
---

name: test_uniform_load_without_noclobber
name: test_uniform_load_without_noclobber

legalized: true
legalized: true

tracksRegLiveness: true
tracksRegLiveness: true

body: |
body: |

  bb.1.entry:
  bb.1.entry:

    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3

▲ Show 20 Lines • Show All 132 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=amdgpu-regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s




---
---

name: test_unmerge_s64_s32_s
name: test_unmerge_s64_s32_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

   liveins: $sgpr0_sgpr1
   liveins: $sgpr0_sgpr1

▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s




---
---

name: usube_s32_sss
name: usube_s32_sss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr2
    liveins: $sgpr0, $sgpr1, $sgpr2

▲ Show 20 Lines • Show All 171 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: usubo_s32_ss
name: usubo_s32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

▲ Show 20 Lines • Show All 67 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -run-pass=regbankselect -o - %s | FileCheck %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -run-pass=amdgpu-regbankselect -o - %s | FileCheck %s




# Make sure that an arbitrary AGPR is treated as a divergent value
# Make sure that an arbitrary AGPR is treated as a divergent value

# that needs to be copied to VGPR, and then waterfalled
# that needs to be copied to VGPR, and then waterfalled




# 32-bit case
# 32-bit case

---
---

name:            raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__agpr_soffset
name:            raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__agpr_soffset

legalized:       true
legalized:       true

▲ Show 20 Lines • Show All 115 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -global-isel -march=amdgcn -mcpu=fiji -run-pass=regbankselect -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
# RUN: llc -global-isel -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s

# RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
# RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -run-pass=amdgpu-regbankselect -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s

# RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -run-pass=regbankselect -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
# RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-regbankselect -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s

---
---

name: constant_load_i8_align8
name: constant_load_i8_align8

legalized: true
legalized: true




body: |
body: |

 bb.0:
 bb.0:

   liveins: $sgpr0_sgpr1
   liveins: $sgpr0_sgpr1

    ; GFX8-LABEL: name: constant_load_i8_align8
    ; GFX8-LABEL: name: constant_load_i8_align8

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llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: xor_s32_ss
name: xor_s32_ss

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

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llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s




---
---

name: zext_s32_to_s64_s
name: zext_s32_to_s64_s

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0

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llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect  -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect  -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect  -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-regbankselect  -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: zextload_constant_i8_to_i32_uniform
name: zextload_constant_i8_to_i32_uniform

legalized: true
legalized: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1
    liveins: $sgpr0_sgpr1

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llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=hawaii -mattr=+flat-for-global -run-pass=regbankselect %s -verify-machineinstrs -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=hawaii -mattr=+flat-for-global -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - | FileCheck %s




--- |
--- |

  define amdgpu_kernel void @load_constant(ptr addrspace(4) %ptr0) {
  define amdgpu_kernel void @load_constant(ptr addrspace(4) %ptr0) {

    ret void
    ret void

  }
  }




  define amdgpu_kernel void @load_constant_volatile(ptr addrspace(4) %ptr0) {
  define amdgpu_kernel void @load_constant_volatile(ptr addrspace(4) %ptr0) {

    ret void
    ret void

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