[TypePromotion] NewPM support.

[samparker]

Summary

Addressing https://github.com/llvm/llvm-project/issues/59385

First time that I've added a pass to the NPM, so may have missed something.

[lebedev.ri]

Thank you!

llvm/tools/opt/opt.cpp

469–470

Please drop this, remove "type-promotion" from shouldPinPassToLegacyPM(),
and adjust the run lines in newly-failing tests.

[samparker]

Updated opt and the test runs.

[samparker]

Fixed typo.

[lebedev.ri]

Assuming that *all* tests that used to call this pass now pass, LG.
Thank you! (other "codegen" IR->IR passes need similar treatment)

llvm/tools/opt/opt.cpp

366

Please precommit this clang-format

[samparker]

Thanks for the quick review! I will be porting hardware-loops and mve-tail-predication as well.

[ronlieb]

hi . bbot failure related to this patch https://lab.llvm.org/buildbot/#/builders/193/builds/24271

[jdoerfert]

In D140893#4023208, @ronlieb wrote:

hi . bbot failure related to this patch https://lab.llvm.org/buildbot/#/builders/193/builds/24271

Should be as simple as renaming the inititialize, or even dropping it in our code. Someone is verifying that now and we'll patch OpenMP.

[ronlieb]

it does look simple :-) i pushed in a fix a while ago, (hour or so)

[arsenm]

In D140893#4023630, @ronlieb wrote:

it does look simple :-) i pushed in a fix a while ago, (hour or so)

The bot is failing since it also included a printf change, should revert

[ronlieb]

sorry about that, reverted.
will push a different fix now.

llvm/include/llvm/CodeGen/Passes.h

namespace llvm {
 
   /// Create Hardware Loop pass. \see HardwareLoops.cpp
   FunctionPass *createHardwareLoopsPass();
 
   /// This pass inserts pseudo probe annotation for callsite profiling.
   FunctionPass *createPseudoProbeInserter();
 
   /// Create IR Type Promotion pass. \see TypePromotion.cpp
-  FunctionPass *createTypePromotionPass();
+  FunctionPass *createTypePromotionLegacyPass();
 
   /// Add Flow Sensitive Discriminators. PassNum specifies the
   /// sequence number of this pass (starting from 1).
   FunctionPass *
   createMIRAddFSDiscriminatorsPass(sampleprof::FSDiscriminatorPass P);
 
   /// Read Flow Sensitive Profile.
   FunctionPass *createMIRProfileLoaderPass(std::string File,

llvm/include/llvm/CodeGen/TypePromotion.h

+//===- TypePromotion.h ------------------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+///
+/// Defines an IR pass for type promotion.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_TYPEPROMOTION_H
+#define LLVM_CODEGEN_TYPEPROMOTION_H
+
+#include "llvm/IR/PassManager.h"
+
+namespace llvm {
+
+class Function;
+class TargetMachine;
+
+class TypePromotionPass : public PassInfoMixin<TypePromotionPass> {
+private:
+  const TargetMachine *TM;
+
+public:
+  TypePromotionPass(const TargetMachine *TM): TM(TM) { }
+  PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
+};
+
+} // end namespace llvm
+
+#endif // LLVM_CODEGEN_TYPEPROMOTION_H

llvm/include/llvm/InitializePasses.h

 void initializeTailCallElimPass(PassRegistry&);
 void initializeTailDuplicatePass(PassRegistry&);
 void initializeTargetLibraryInfoWrapperPassPass(PassRegistry&);
 void initializeTargetPassConfigPass(PassRegistry&);
 void initializeTargetTransformInfoWrapperPassPass(PassRegistry&);
 void initializeTLSVariableHoistLegacyPassPass(PassRegistry &);
 void initializeTwoAddressInstructionPassPass(PassRegistry&);
 void initializeTypeBasedAAWrapperPassPass(PassRegistry&);
-void initializeTypePromotionPass(PassRegistry&);
+void initializeTypePromotionLegacyPass(PassRegistry&);
 void initializeUniformityInfoWrapperPassPass(PassRegistry &);
 void initializeUnifyFunctionExitNodesLegacyPassPass(PassRegistry &);
 void initializeUnifyLoopExitsLegacyPassPass(PassRegistry &);
 void initializeUnpackMachineBundlesPass(PassRegistry&);
 void initializeUnreachableBlockElimLegacyPassPass(PassRegistry&);
 void initializeUnreachableMachineBlockElimPass(PassRegistry&);
 void initializeVectorCombineLegacyPassPass(PassRegistry&);
 void initializeVerifierLegacyPassPass(PassRegistry&);

llvm/lib/CodeGen/CMakeLists.txt

add_llvm_component_library(LLVMCodeGen
   TargetInstrInfo.cpp
   TargetLoweringBase.cpp
   TargetLoweringObjectFileImpl.cpp
   TargetOptionsImpl.cpp
   TargetPassConfig.cpp
   TargetRegisterInfo.cpp
   TargetSchedule.cpp
   TargetSubtargetInfo.cpp
-  TypePromotion.cpp
   TwoAddressInstructionPass.cpp
+  TypePromotion.cpp
   UnreachableBlockElim.cpp
   ValueTypes.cpp
   VLIWMachineScheduler.cpp
   VirtRegMap.cpp
   WasmEHPrepare.cpp
   WinEHPrepare.cpp
   XRayInstrumentation.cpp
   ${GeneratedMLSources}

llvm/lib/CodeGen/CodeGen.cpp

void llvm::initializeCodeGen(PassRegistry &Registry) {
   initializeStackColoringPass(Registry);
   initializeStackMapLivenessPass(Registry);
   initializeStackProtectorPass(Registry);
   initializeStackSlotColoringPass(Registry);
   initializeStripDebugMachineModulePass(Registry);
   initializeTailDuplicatePass(Registry);
   initializeTargetPassConfigPass(Registry);
   initializeTwoAddressInstructionPassPass(Registry);
-  initializeTypePromotionPass(Registry);
+  initializeTypePromotionLegacyPass(Registry);
   initializeUnpackMachineBundlesPass(Registry);
   initializeUnreachableBlockElimLegacyPassPass(Registry);
   initializeUnreachableMachineBlockElimPass(Registry);
   initializeVirtRegMapPass(Registry);
   initializeVirtRegRewriterPass(Registry);
   initializeWasmEHPreparePass(Registry);
   initializeWinEHPreparePass(Registry);
   initializeXRayInstrumentationPass(Registry);
 }
 
 void LLVMInitializeCodeGen(LLVMPassRegistryRef R) {
   initializeCodeGen(*unwrap(R));
 }

llvm/lib/CodeGen/TypePromotion.cpp

 /// This is an opcode based type promotion pass for small types that would
 /// otherwise be promoted during legalisation. This works around the limitations
 /// of selection dag for cyclic regions. The search begins from icmp
 /// instructions operands where a tree, consisting of non-wrapping or safe
 /// wrapping instructions, is built, checked and promoted if possible.
 ///
 //===----------------------------------------------------------------------===//
 
+#include "llvm/CodeGen/TypePromotion.h"
 #include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Analysis/LoopInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetLowering.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
IRPromoter(LLVMContext &C, unsigned Width, SetVector<Value *> &visited,
       : Ctx(C), PromotedWidth(Width), Visited(visited), Sources(sources),
         Sinks(sinks), SafeWrap(wrap), InstsToRemove(instsToRemove) {
     ExtTy = IntegerType::get(Ctx, PromotedWidth);
   }
 
   void Mutate();
 };
 
-class TypePromotion : public FunctionPass {
+class TypePromotionImpl {
   unsigned TypeSize = 0;
   LLVMContext *Ctx = nullptr;
   unsigned RegisterBitWidth = 0;
   SmallPtrSet<Value *, 16> AllVisited;
   SmallPtrSet<Instruction *, 8> SafeToPromote;
   SmallPtrSet<Instruction *, 4> SafeWrap;
   SmallPtrSet<Instruction *, 4> InstsToRemove;
 
class TypePromotionImpl {
   // handle, such as constants and basic blocks.
   bool isSupportedValue(Value *V);
   // Is V an instruction thats result can trivially promoted, or has safe
   // wrapping.
   bool isLegalToPromote(Value *V);
   bool TryToPromote(Value *V, unsigned PromotedWidth, const LoopInfo &LI);
 
 public:
+  bool run(Function &F, const TargetMachine *TM,
+           const TargetTransformInfo &TTI, const LoopInfo &LI);
+};
+
+class TypePromotionLegacy : public FunctionPass {
+public:
   static char ID;
 
-  TypePromotion() : FunctionPass(ID) {}
+  TypePromotionLegacy() : FunctionPass(ID) {}
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addRequired<LoopInfoWrapperPass>();
     AU.addRequired<TargetTransformInfoWrapperPass>();
     AU.addRequired<TargetPassConfig>();
     AU.setPreservesCFG();
     AU.addPreserved<LoopInfoWrapperPass>();
   }
 
   StringRef getPassName() const override { return PASS_NAME; }
 
   bool runOnFunction(Function &F) override;
 };
 
 } // namespace
 
 static bool GenerateSignBits(Instruction *I) {
   unsigned Opc = I->getOpcode();
   return Opc == Instruction::AShr || Opc == Instruction::SDiv ||
          Opc == Instruction::SRem || Opc == Instruction::SExt;
 }
 
-bool TypePromotion::EqualTypeSize(Value *V) {
+bool TypePromotionImpl::EqualTypeSize(Value *V) {
   return V->getType()->getScalarSizeInBits() == TypeSize;
 }
 
-bool TypePromotion::LessOrEqualTypeSize(Value *V) {
+bool TypePromotionImpl::LessOrEqualTypeSize(Value *V) {
   return V->getType()->getScalarSizeInBits() <= TypeSize;
 }
 
-bool TypePromotion::GreaterThanTypeSize(Value *V) {
+bool TypePromotionImpl::GreaterThanTypeSize(Value *V) {
   return V->getType()->getScalarSizeInBits() > TypeSize;
 }
 
-bool TypePromotion::LessThanTypeSize(Value *V) {
+bool TypePromotionImpl::LessThanTypeSize(Value *V) {
   return V->getType()->getScalarSizeInBits() < TypeSize;
 }
 
 /// Return true if the given value is a source in the use-def chain, producing
 /// a narrow 'TypeSize' value. These values will be zext to start the promotion
 /// of the tree to i32. We guarantee that these won't populate the upper bits
 /// of the register. ZExt on the loads will be free, and the same for call
 /// return values because we only accept ones that guarantee a zeroext ret val.
 /// Many arguments will have the zeroext attribute too, so those would be free
 /// too.
-bool TypePromotion::isSource(Value *V) {
+bool TypePromotionImpl::isSource(Value *V) {
   if (!isa<IntegerType>(V->getType()))
     return false;
 
   // TODO Allow zext to be sources.
   if (isa<Argument>(V))
     return true;
   else if (isa<LoadInst>(V))
     return true;
   else if (isa<BitCastInst>(V))
     return true;
   else if (auto *Call = dyn_cast<CallInst>(V))
     return Call->hasRetAttr(Attribute::AttrKind::ZExt);
   else if (auto *Trunc = dyn_cast<TruncInst>(V))
     return EqualTypeSize(Trunc);
   return false;
 }
 
 /// Return true if V will require any promoted values to be truncated for the
 /// the IR to remain valid. We can't mutate the value type of these
 /// instructions.
-bool TypePromotion::isSink(Value *V) {
+bool TypePromotionImpl::isSink(Value *V) {
   // TODO The truncate also isn't actually necessary because we would already
   // proved that the data value is kept within the range of the original data
   // type. We currently remove any truncs inserted for handling zext sinks.
 
   // Sinks are:
   // - points where the value in the register is being observed, such as an
   //   icmp, switch or store.
   // - points where value types have to match, such as calls and returns.
if (auto *Switch = dyn_cast<SwitchInst>(V))
     return LessThanTypeSize(Switch->getCondition());
   if (auto *ICmp = dyn_cast<ICmpInst>(V))
     return ICmp->isSigned() || LessThanTypeSize(ICmp->getOperand(0));
 
   return isa<CallInst>(V);
 }
 
 /// Return whether this instruction can safely wrap.
-bool TypePromotion::isSafeWrap(Instruction *I) {
+bool TypePromotionImpl::isSafeWrap(Instruction *I) {
   // We can support a potentially wrapping instruction (I) if:
   // - It is only used by an unsigned icmp.
   // - The icmp uses a constant.
   // - The wrapping value (I) is decreasing, i.e would underflow - wrapping
   //   around zero to become a larger number than before.
   // - The wrapping instruction (I) also uses a constant.
   //
   // We can then use the two constants to calculate whether the result would
LLVM_DEBUG(dbgs() << "IR Promotion: Allowing safe overflow for sext "
                       << "const of " << *I << " and " << *CI << "\n");
     SafeWrap.insert(I);
     SafeWrap.insert(CI);
     return true;
   }
   return false;
 }
 
-bool TypePromotion::shouldPromote(Value *V) {
+bool TypePromotionImpl::shouldPromote(Value *V) {
   if (!isa<IntegerType>(V->getType()) || isSink(V))
     return false;
 
   if (isSource(V))
     return true;
 
   auto *I = dyn_cast<Instruction>(V);
   if (!I)
void IRPromoter::Mutate() {
   Cleanup();
 
   LLVM_DEBUG(dbgs() << "IR Promotion: Mutation complete\n");
 }
 
 /// We disallow booleans to make life easier when dealing with icmps but allow
 /// any other integer that fits in a scalar register. Void types are accepted
 /// so we can handle switches.
-bool TypePromotion::isSupportedType(Value *V) {
+bool TypePromotionImpl::isSupportedType(Value *V) {
   Type *Ty = V->getType();
 
   // Allow voids and pointers, these won't be promoted.
   if (Ty->isVoidTy() || Ty->isPointerTy())
     return true;
 
   if (!isa<IntegerType>(Ty) || cast<IntegerType>(Ty)->getBitWidth() == 1 ||
       cast<IntegerType>(Ty)->getBitWidth() > RegisterBitWidth)
     return false;
 
   return LessOrEqualTypeSize(V);
 }
 
 /// We accept most instructions, as well as Arguments and ConstantInsts. We
 /// Disallow casts other than zext and truncs and only allow calls if their
 /// return value is zeroext. We don't allow opcodes that can introduce sign
 /// bits.
-bool TypePromotion::isSupportedValue(Value *V) {
+bool TypePromotionImpl::isSupportedValue(Value *V) {
   if (auto *I = dyn_cast<Instruction>(V)) {
     switch (I->getOpcode()) {
     default:
       return isa<BinaryOperator>(I) && isSupportedType(I) &&
              !GenerateSignBits(I);
     case Instruction::GetElementPtr:
     case Instruction::Store:
     case Instruction::Br:
if (auto *I = dyn_cast<Instruction>(V)) {
     return isSupportedType(V);
 
   return isa<BasicBlock>(V);
 }
 
 /// Check that the type of V would be promoted and that the original type is
 /// smaller than the targeted promoted type. Check that we're not trying to
 /// promote something larger than our base 'TypeSize' type.
-bool TypePromotion::isLegalToPromote(Value *V) {
+bool TypePromotionImpl::isLegalToPromote(Value *V) {
   auto *I = dyn_cast<Instruction>(V);
   if (!I)
     return true;
 
   if (SafeToPromote.count(I))
     return true;
 
   if (isPromotedResultSafe(I) || isSafeWrap(I)) {
     SafeToPromote.insert(I);
     return true;
   }
   return false;
 }
 
-bool TypePromotion::TryToPromote(Value *V, unsigned PromotedWidth,
+bool TypePromotionImpl::TryToPromote(Value *V, unsigned PromotedWidth,
                                  const LoopInfo &LI) {
   Type *OrigTy = V->getType();
   TypeSize = OrigTy->getPrimitiveSizeInBits().getFixedSize();
   SafeToPromote.clear();
   SafeWrap.clear();
 
   if (!isSupportedValue(V) || !shouldPromote(V) || !isLegalToPromote(V))
     return false;
if (!isa<PHINode>(V) && !(LoopSinks && NonLoopSources) &&
     return false;
 
   IRPromoter Promoter(*Ctx, PromotedWidth, CurrentVisited, Sources, Sinks,
                       SafeWrap, InstsToRemove);
   Promoter.Mutate();
   return true;
 }
 
-bool TypePromotion::runOnFunction(Function &F) {
-  if (skipFunction(F) || DisablePromotion)
+bool TypePromotionImpl::run(Function &F, const TargetMachine *TM,
+                            const TargetTransformInfo &TTI,
+                            const LoopInfo &LI) {
+  if (DisablePromotion)
     return false;
 
   LLVM_DEBUG(dbgs() << "IR Promotion: Running on " << F.getName() << "\n");
 
-  auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
-  if (!TPC)
-    return false;
-
   AllVisited.clear();
   SafeToPromote.clear();
   SafeWrap.clear();
   bool MadeChange = false;
   const DataLayout &DL = F.getParent()->getDataLayout();
-  const TargetMachine &TM = TPC->getTM<TargetMachine>();
-  const TargetSubtargetInfo *SubtargetInfo = TM.getSubtargetImpl(F);
+  const TargetSubtargetInfo *SubtargetInfo = TM->getSubtargetImpl(F);
   const TargetLowering *TLI = SubtargetInfo->getTargetLowering();
-  const TargetTransformInfo &TII =
-      getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
-  const LoopInfo &LI = getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
   RegisterBitWidth =
-      TII.getRegisterBitWidth(TargetTransformInfo::RGK_Scalar).getFixedSize();
+      TTI.getRegisterBitWidth(TargetTransformInfo::RGK_Scalar).getFixedSize();
   Ctx = &F.getParent()->getContext();
 
   // Return the preferred integer width of the instruction, or zero if we
   // shouldn't try.
   auto GetPromoteWidth = [&](Instruction *I) -> uint32_t {
     if (!isa<IntegerType>(I->getType()))
       return 0;
 
bool TypePromotionImpl::run(Function &F, const TargetMachine *TM,
 
   AllVisited.clear();
   SafeToPromote.clear();
   SafeWrap.clear();
 
   return MadeChange;
 }
 
-INITIALIZE_PASS_BEGIN(TypePromotion, DEBUG_TYPE, PASS_NAME, false, false)
-INITIALIZE_PASS_END(TypePromotion, DEBUG_TYPE, PASS_NAME, false, false)
+INITIALIZE_PASS_BEGIN(TypePromotionLegacy, DEBUG_TYPE, PASS_NAME, false, false)
+INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
+INITIALIZE_PASS_DEPENDENCY(TargetTransformInfoWrapperPass)
+INITIALIZE_PASS_END(TypePromotionLegacy, DEBUG_TYPE, PASS_NAME, false, false)
+
+char TypePromotionLegacy::ID = 0;
+
+bool TypePromotionLegacy::runOnFunction(Function &F) {
+  if (skipFunction(F))
+    return false;
+
+  auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
+  if (!TPC)
+    return false;
+
+  auto *TM = &TPC->getTM<TargetMachine>();
+  auto &TTI = getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
+  auto &LI = getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
+
+  TypePromotionImpl TP;
+  return TP.run(F, TM, TTI, LI);
+}
+
+FunctionPass *llvm::createTypePromotionLegacyPass() {
+  return new TypePromotionLegacy();
+}
 
-char TypePromotion::ID = 0;
+PreservedAnalyses TypePromotionPass::run(Function &F,
+                                         FunctionAnalysisManager &AM) {
+  auto &TTI = AM.getResult<TargetIRAnalysis>(F);
+  auto &LI = AM.getResult<LoopAnalysis>(F);
+  TypePromotionImpl TP;
 
-FunctionPass *llvm::createTypePromotionPass() { return new TypePromotion(); }
+  bool Changed = TP.run(F, TM, TTI, LI);
+  if (!Changed)
+    return PreservedAnalyses::all();
+
+  PreservedAnalyses PA;
+  PA.preserveSet<CFGAnalyses>();
+  PA.preserve<LoopAnalysis>();
+  return PA;
+}

llvm/lib/Passes/CMakeLists.txt

add_llvm_component_library(LLVMPasses
   ${LLVM_MAIN_INCLUDE_DIR}/llvm/Passes
 
   DEPENDS
   intrinsics_gen
 
   LINK_COMPONENTS
   AggressiveInstCombine
   Analysis
+  CodeGen
   Core
   Coroutines
   IPO
   InstCombine
   IRPrinter
   ObjCARC
   Scalar
   Support
   Target
   TransformUtils
   Vectorize
   Instrumentation
   )

llvm/lib/Passes/PassBuilder.cpp

 #include "llvm/Analysis/ScalarEvolutionAliasAnalysis.h"
 #include "llvm/Analysis/ScopedNoAliasAA.h"
 #include "llvm/Analysis/StackLifetime.h"
 #include "llvm/Analysis/StackSafetyAnalysis.h"
 #include "llvm/Analysis/TargetLibraryInfo.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/Analysis/TypeBasedAliasAnalysis.h"
 #include "llvm/Analysis/UniformityAnalysis.h"
+#include "llvm/CodeGen/TypePromotion.h"
 #include "llvm/IR/DebugInfo.h"
 #include "llvm/IR/Dominators.h"
 #include "llvm/IR/PassManager.h"
 #include "llvm/IR/PrintPasses.h"
 #include "llvm/IR/SafepointIRVerifier.h"
 #include "llvm/IR/Verifier.h"
 #include "llvm/IRPrinter/IRPrintingPasses.h"
 #include "llvm/Support/CommandLine.h"

llvm/lib/Passes/PassRegistry.def

 FUNCTION_PASS("sccp", SCCPPass())
 FUNCTION_PASS("sink", SinkingPass())
 FUNCTION_PASS("slp-vectorizer", SLPVectorizerPass())
 FUNCTION_PASS("slsr", StraightLineStrengthReducePass())
 FUNCTION_PASS("speculative-execution", SpeculativeExecutionPass())
 FUNCTION_PASS("strip-gc-relocates", StripGCRelocates())
 FUNCTION_PASS("structurizecfg", StructurizeCFGPass())
 FUNCTION_PASS("tailcallelim", TailCallElimPass())
+FUNCTION_PASS("typepromotion", TypePromotionPass(TM))
 FUNCTION_PASS("unify-loop-exits", UnifyLoopExitsPass())
 FUNCTION_PASS("vector-combine", VectorCombinePass())
 FUNCTION_PASS("verify", VerifierPass())
 FUNCTION_PASS("verify<domtree>", DominatorTreeVerifierPass())
 FUNCTION_PASS("verify<loops>", LoopVerifierPass())
 FUNCTION_PASS("verify<memoryssa>", MemorySSAVerifierPass())
 FUNCTION_PASS("verify<regions>", RegionInfoVerifierPass())
 FUNCTION_PASS("verify<safepoint-ir>", SafepointIRVerifierPass())

llvm/lib/Target/AArch64/AArch64TargetMachine.cpp

addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,
                                   MergeExternalByDefault));
   }
 
   return false;
 }
 
 void AArch64PassConfig::addCodeGenPrepare() {
   if (getOptLevel() != CodeGenOpt::None)
-    addPass(createTypePromotionPass());
+    addPass(createTypePromotionLegacyPass());
   TargetPassConfig::addCodeGenPrepare();
 }
 
 bool AArch64PassConfig::addInstSelector() {
   addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
 
   // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
   // references to _TLS_MODULE_BASE_ as possible.

llvm/lib/Target/ARM/ARMTargetMachine.cpp

if (TM->getTargetTriple().isOSWindows())
     addPass(createCFGuardCheckPass());
 
   if (TM->Options.JMCInstrument)
     addPass(createJMCInstrumenterPass());
 }
 
 void ARMPassConfig::addCodeGenPrepare() {
   if (getOptLevel() != CodeGenOpt::None)
-    addPass(createTypePromotionPass());
+    addPass(createTypePromotionLegacyPass());
   TargetPassConfig::addCodeGenPrepare();
 }
 
 bool ARMPassConfig::addPreISel() {
   if ((TM->getOptLevel() != CodeGenOpt::None &&
        EnableGlobalMerge == cl::BOU_UNSET) ||
       EnableGlobalMerge == cl::BOU_TRUE) {
     // FIXME: This is using the thumb1 only constant value for

llvm/test/CodeGen/AArch64/bfis-in-loop.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: opt -mtriple=aarch64-linux-gnu -type-promotion < %s | llc -mtriple=aarch64-linux-gnu -o - | FileCheck %s
+; RUN: opt -mtriple=aarch64-linux-gnu -passes=typepromotion < %s | llc -mtriple=aarch64-linux-gnu -o - | FileCheck %s
 
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 
 %struct.bar = type { %struct.foo }
 %struct.foo = type { ptr }
 %struct.wobble = type { ptr }
 %struct.zot = type <{ %struct.wobble, ptr, ptr, i8, [7 x i8] }>
 

llvm/test/Transforms/TypePromotion/AArch64/convert-utf.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=aarch64 -type-promotion -verify -dce -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=aarch64 -passes=typepromotion,verify,dce -S %s -o - | FileCheck %s
 
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 
 @_ZN4llvmL20trailingBytesForUTF8E = internal unnamed_addr constant [256 x i8] c"\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\03\03\03\03\03\03\03\03\04\04\04\04\05\05\05\05", align 1
 @_ZN4llvmL15offsetsFromUTF8E = internal unnamed_addr constant [6 x i32] [i32 0, i32 12416, i32 925824, i32 63447168, i32 -100130688, i32 -2113396608], align 4
 
 define dso_local noundef i32 @_ZN4llvm18ConvertUTF8toUTF16EPPKhS1_PPtS3_NS_15ConversionFlagsE(i8** nocapture noundef %sourceStart, i8* noundef %sourceEnd, i16** nocapture noundef %targetStart, i16* noundef readnone %targetEnd, i32 noundef %flags) local_unnamed_addr {
 ; CHECK-LABEL: @_ZN4llvm18ConvertUTF8toUTF16EPPKhS1_PPtS3_NS_15ConversionFlagsE(

llvm/test/Transforms/TypePromotion/AArch64/loops.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=aarch64 -type-promotion -verify -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=aarch64 -passes=typepromotion,verify -S %s -o - | FileCheck %s
 
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 
 define dso_local i32 @ic_strcmp(i8* nocapture readonly %arg, i8* nocapture readonly %arg1) {
 ; CHECK-LABEL: @ic_strcmp(
 ; CHECK-NEXT:  bb:
 ; CHECK-NEXT:    [[I:%.*]] = load i8, i8* [[ARG:%.*]], align 1
 ; CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[I]] to i32

llvm/test/Transforms/TypePromotion/AArch64/phi-zext-gep.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=aarch64 -type-promotion -verify -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=aarch64 -passes=typepromotion,verify -S %s -o - | FileCheck %s
 
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 
 define dso_local i32 @avoid_trunc_gep(i8* nocapture readonly %ip) {
 ; CHECK-LABEL: @avoid_trunc_gep(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TAG_0_IN8:%.*]] = load i8, i8* [[IP:%.*]], align 1
 ; CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[TAG_0_IN8]] to i32

llvm/test/Transforms/TypePromotion/AArch64/phi-zext-gep2.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=aarch64 -type-promotion -verify -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=aarch64 -passes=typepromotion,verify -S %s -o - | FileCheck %s
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 
 ; Function Attrs: mustprogress nofree nosync nounwind uwtable
 define dso_local void @foo(ptr noundef %ptr0, ptr nocapture noundef readonly %ptr1, ptr nocapture noundef %dest) local_unnamed_addr {
 ; CHECK-LABEL: @foo(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i8, ptr [[PTR0:%.*]], align 1
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[TMP0]] to i64

llvm/test/Transforms/TypePromotion/AArch64/search-loop.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -type-promotion -mtriple=aarch64 %s -o - | FileCheck %s
+; RUN: opt -S -passes=typepromotion -mtriple=aarch64 %s -o - | FileCheck %s
 
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64"
 
 define dso_local noundef i1 @_Z10find_shortPssj(ptr nocapture noundef readonly %0, i16 noundef %1, i32 noundef %2) {
 ; CHECK-LABEL: @_Z10find_shortPssj(
 ; CHECK-NEXT:    [[TMP4:%.*]] = zext i16 [[TMP1:%.*]] to i32
 ; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[TMP2:%.*]], 0

llvm/test/Transforms/TypePromotion/AArch64/trunc-zext-chain.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=aarch64-linux-gnu -type-promotion -verify -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=aarch64-linux-gnu -passes=typepromotion,verify -S %s -o - | FileCheck %s
 
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 
 %struct.bar = type { %struct.foo }
 %struct.foo = type { %struct.wobble* }
 %struct.wobble = type { %struct.zot* }
 %struct.zot = type <{ %struct.wobble, %struct.zot*, %struct.wobble*, i8, [7 x i8] }>
 

llvm/test/Transforms/TypePromotion/AArch64/vla-zext.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=aarch64 -type-promotion -verify -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=aarch64 -passes=typepromotion,verify -S %s -o - | FileCheck %s
 
 define dso_local void @foo(ptr nocapture noundef readonly %a, ptr nocapture noundef readonly %b, ptr nocapture noundef writeonly %c, i64 noundef %n) local_unnamed_addr {
 ; CHECK-LABEL: @foo(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[B:%.*]], i64 0
 ; CHECK-NEXT:    [[TMP1:%.*]] = load <vscale x 4 x i8>, ptr [[TMP0]], align 1
 ; CHECK-NEXT:    [[TMP2:%.*]] = tail call i64 @llvm.vscale.i64()
 ; CHECK-NEXT:    [[TMP3:%.*]] = shl nuw nsw i64 [[TMP2]], 3

llvm/test/Transforms/TypePromotion/ARM/calls.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify  -S %s -o - | FileCheck %s
 
 define i8 @call_with_imms(i8* %arg) {
 ; CHECK-LABEL: @call_with_imms(
 ; CHECK-NEXT:    [[CALL:%.*]] = tail call arm_aapcs_vfpcc zeroext i8 @dummy2(i8* nonnull [[ARG:%.*]], i8 zeroext 0, i8 zeroext 0)
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i8 [[CALL]], 0
 ; CHECK-NEXT:    [[RES:%.*]] = select i1 [[CMP]], i8 [[CALL]], i8 1
 ; CHECK-NEXT:    ret i8 [[RES]]
 ;

llvm/test/Transforms/TypePromotion/ARM/casts.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify  -S %s -o - | FileCheck %s
 
 define i16 @dsp_trunc(i32 %arg0, i32 %arg1, i16* %gep0, i16* %gep1) {
 ; CHECK-LABEL: @dsp_trunc(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[ADD0:%.*]] = add i32 [[ARG0:%.*]], [[ARG1:%.*]]
 ; CHECK-NEXT:    [[CONV0:%.*]] = trunc i32 [[ADD0]] to i16
 ; CHECK-NEXT:    [[SUB0:%.*]] = sub i16 0, [[CONV0]]
 ; CHECK-NEXT:    [[LOAD0:%.*]] = load i16, i16* [[GEP0:%.*]], align 2

llvm/test/Transforms/TypePromotion/ARM/clear-structures.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify  -S %s -o - | FileCheck %s
 
 define i32 @clear_structures(i8* nocapture readonly %fmt, [1 x i32] %ap.coerce, i8* %out, void (i32, i8*)* nocapture %write) {
 ; CHECK-LABEL: @clear_structures(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[WHILE_COND_OUTER:%.*]]
 ; CHECK:       while.cond.outer:
 ; CHECK-NEXT:    [[FMT_ADDR_0_PH:%.*]] = phi i8* [ [[FMT:%.*]], [[ENTRY:%.*]] ], [ [[FMT_ADDR_3:%.*]], [[WHILE_COND_OUTER_BACKEDGE:%.*]] ]
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i8, i8* [[FMT_ADDR_0_PH]], align 1

llvm/test/Transforms/TypePromotion/ARM/icmps.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify  -S %s -o - | FileCheck %s
 
 define i32 @test_ult_254_inc_imm(i8 zeroext %x) {
 ; CHECK-LABEL: @test_ult_254_inc_imm(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[ADD:%.*]] = add i8 [[X:%.*]], 1
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i8 [[ADD]], -2
 ; CHECK-NEXT:    [[RES:%.*]] = select i1 [[CMP]], i32 35, i32 47
 ; CHECK-NEXT:    ret i32 [[RES]]

llvm/test/Transforms/TypePromotion/ARM/large-int.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=thumbv7 -type-promotion -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=thumbv7 -passes=typepromotion  -S %s -o - | FileCheck %s
 
 define hidden void @dont_promote_large_int(i8* %in, i64* %out) {
 ; CHECK-LABEL: @dont_promote_large_int(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[CAST:%.*]] = bitcast i8* [[IN:%.*]] to i144*
 ; CHECK-NEXT:    [[LOAD:%.*]] = load i144, i144* [[CAST]], align 4
 ; CHECK-NEXT:    [[TRUNC:%.*]] = trunc i144 [[LOAD]] to i98
 ; CHECK-NEXT:    [[AND:%.*]] = and i98 [[TRUNC]], -79228162514264337593543950336

llvm/test/Transforms/TypePromotion/ARM/phi-zext-gep.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify -S %s -o - | FileCheck %s
 
 ; Function Attrs: mustprogress nofree nosync nounwind uwtable
 define dso_local void @foo(ptr noundef %ptr0, ptr nocapture noundef readonly %ptr1, ptr nocapture noundef %dest) local_unnamed_addr {
 ; CHECK-LABEL: @foo(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i8, ptr [[PTR0:%.*]], align 1
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[TMP0]] to i32
 ; CHECK-NEXT:    br label [[DO_BODY:%.*]]

llvm/test/Transforms/TypePromotion/ARM/phi-zext-gep2.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify -S %s -o - | FileCheck %s
 
 ; Function Attrs: mustprogress nofree nosync nounwind uwtable
 define dso_local void @foo(ptr noundef %ptr0, ptr nocapture noundef readonly %ptr1, ptr nocapture noundef %dest) local_unnamed_addr {
 ; CHECK-LABEL: @foo(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[PTR0:%.*]], align 1
 ; CHECK-NEXT:    br label [[DO_BODY:%.*]]
 ; CHECK:       do.body:

llvm/test/Transforms/TypePromotion/ARM/phis-ret.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify  -S %s -o - | FileCheck %s
 
 ; Check that the arguments are extended but then nothing else is.
 ; This also ensures that the pass can handle loops.
 define void @phi_feeding_phi_args(i8 %a, i8 %b) {
 ; CHECK-LABEL: @phi_feeding_phi_args(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[A:%.*]] to i32
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[B:%.*]] to i32

llvm/test/Transforms/TypePromotion/ARM/pointers.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify  -S %s -o - | FileCheck %s
 
 define void @phi_pointers(i16* %a, i16* %b, i8 zeroext %M, i8 zeroext %N) {
 ; CHECK-LABEL: @phi_pointers(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[M:%.*]] to i32
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[N:%.*]] to i32
 ; CHECK-NEXT:    [[ADD:%.*]] = add nuw i32 [[TMP0]], 1
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ADD]], 1

llvm/test/Transforms/TypePromotion/ARM/signed-icmps.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify  -S %s -o - | FileCheck %s
 
 define i8 @eq_sgt(i8* %x, i8 *%y, i8 zeroext %z) {
 ; CHECK-LABEL: @eq_sgt(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[LOAD0:%.*]] = load i8, i8* [[X:%.*]], align 1
 ; CHECK-NEXT:    [[LOAD1:%.*]] = load i8, i8* [[Y:%.*]], align 1
 ; CHECK-NEXT:    [[ADD:%.*]] = add i8 [[LOAD0]], [[Z:%.*]]
 ; CHECK-NEXT:    [[SUB:%.*]] = sub i8 [[LOAD1]], 1

llvm/test/Transforms/TypePromotion/ARM/signed.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify  -S %s -o - | FileCheck %s
 
 ; Test to check that ARMCodeGenPrepare doesn't optimised away sign extends.
 define i16 @test_signed_load(i16* %ptr) {
 ; CHECK-LABEL: @test_signed_load(
 ; CHECK-NEXT:    [[LOAD:%.*]] = load i16, i16* [[PTR:%.*]], align 2
 ; CHECK-NEXT:    [[CONV0:%.*]] = zext i16 [[LOAD]] to i32
 ; CHECK-NEXT:    [[CONV1:%.*]] = sext i16 [[LOAD]] to i32
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[CONV0]], [[CONV1]]

llvm/test/Transforms/TypePromotion/ARM/switch.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify  -S %s -o - | FileCheck %s
 
 define void @truncate_source_phi_switch(i8* %memblock, i8* %store, i16 %arg) {
 ; CHECK-LABEL: @truncate_source_phi_switch(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[PRE:%.*]] = load i8, i8* [[MEMBLOCK:%.*]], align 1
 ; CHECK-NEXT:    [[TMP0:%.*]] = zext i8 [[PRE]] to i32
 ; CHECK-NEXT:    [[CONV:%.*]] = trunc i16 [[ARG:%.*]] to i8
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[CONV]] to i32

llvm/test/Transforms/TypePromotion/ARM/wrapping.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify  -S %s -o - | FileCheck %s
 
 define zeroext i16 @overflow_add(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: @overflow_add(
 ; CHECK-NEXT:    [[ADD:%.*]] = add i16 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    [[OR:%.*]] = or i16 [[ADD]], 1
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i16 [[OR]], 1024
 ; CHECK-NEXT:    [[RES:%.*]] = select i1 [[CMP]], i16 2, i16 5
 ; CHECK-NEXT:    ret i16 [[RES]]

llvm/tools/opt/opt.cpp

if (llvm::is_contained(PassNameExactToIgnore, Pass))
     return false;
 
   std::vector<StringRef> PassNamePrefix = {
       "x86-",    "xcore-", "wasm-",  "systemz-", "ppc-",    "nvvm-",
       "nvptx-",  "mips-",  "lanai-", "hexagon-", "bpf-",    "avr-",
       "thumb2-", "arm-",   "si-",    "gcn-",     "amdgpu-", "aarch64-",
       "amdgcn-", "polly-", "riscv-", "dxil-"};
   std::vector<StringRef> PassNameContain = {"ehprepare"};
   std::vector<StringRef> PassNameExact = {
       "safe-stack",
       "cost-model",
       "codegenprepare",
       "interleaved-load-combine",
       "unreachableblockelim",
       "verify-safepoint-ir",
       "atomic-expand",
       "expandvp",
       "hardware-loops",
-      "type-promotion",
       "mve-tail-predication",
       "interleaved-access",
       "global-merge",
       "pre-isel-intrinsic-lowering",
       "expand-reductions",
       "indirectbr-expand",
       "generic-to-nvvm",
       "expandmemcmp",
int main(int argc, char **argv) {
   initializeIndirectBrExpandPassPass(Registry);
   initializeInterleavedLoadCombinePass(Registry);
   initializeInterleavedAccessPass(Registry);
   initializeUnreachableBlockElimLegacyPassPass(Registry);
   initializeExpandReductionsPass(Registry);
   initializeExpandVectorPredicationPass(Registry);
   initializeWasmEHPreparePass(Registry);
   initializeWriteBitcodePassPass(Registry);
   initializeHardwareLoopsPass(Registry);
-  initializeTypePromotionPass(Registry);
   initializeReplaceWithVeclibLegacyPass(Registry);
   initializeJMCInstrumenterPass(Registry);
 
 #ifdef BUILD_EXAMPLES
   initializeExampleIRTransforms(Registry);
 #endif
 
   SmallVector<PassPlugin, 1> PluginList;
   PassPlugins.setCallback([&](const std::string &PluginPath) {