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avieira (Andre Vieira)
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User Since
Jan 19 2017, 12:49 AM (349 w, 2 d)

Recent Activity

Oct 12 2022

avieira committed rGbc71aa4fbc77: [libc] Update benchmarks/README.md (authored by avieira).
[libc] Update benchmarks/README.md
Oct 12 2022, 8:14 AM · Restricted Project, Restricted Project
avieira closed D135582: [libc] Update benchmarks/README.md.
Oct 12 2022, 8:14 AM · Restricted Project, Restricted Project

Oct 10 2022

avieira requested review of D135582: [libc] Update benchmarks/README.md.
Oct 10 2022, 7:31 AM · Restricted Project, Restricted Project

Aug 19 2022

avieira added inline comments to D132121: [NFC][libc] rearrange aarch64 memset code to better match new implementation.
Aug 19 2022, 7:17 AM · Restricted Project, Restricted Project

Aug 17 2022

avieira committed rG49223e0a2df3: [TypePromotion] Don't promote PHI + ZExt if wider than RegisterBitWidth (authored by avieira).
[TypePromotion] Don't promote PHI + ZExt if wider than RegisterBitWidth
Aug 17 2022, 1:55 AM · Restricted Project, Restricted Project
avieira closed D131966: [TypePromotion] Don't promote PHI + ZExt if wider than RegisterBitWidth.
Aug 17 2022, 1:55 AM · Restricted Project, Restricted Project

Aug 16 2022

avieira requested review of D131966: [TypePromotion] Don't promote PHI + ZExt if wider than RegisterBitWidth.
Aug 16 2022, 7:36 AM · Restricted Project, Restricted Project
avieira committed rGc6b5a13b7ae5: [TypePromotion] Only search for PHI + ZExt promotion of Integers (authored by avieira).
[TypePromotion] Only search for PHI + ZExt promotion of Integers
Aug 16 2022, 2:17 AM · Restricted Project, Restricted Project
avieira closed D131948: [TypePromotion] Only search for PHI + ZExt promotion of Integers.
Aug 16 2022, 2:16 AM · Restricted Project, Restricted Project
avieira added a comment to D131948: [TypePromotion] Only search for PHI + ZExt promotion of Integers.

Hehe, I don't see why not but that feels like another potential improvement rather than a fix ;) I'll go ahead and commit this to unblock @paulwalker-arm if that's OK?

Aug 16 2022, 2:11 AM · Restricted Project, Restricted Project
avieira added a comment to D111237: [TypePromotion] Search from ZExt + PHI.

Fix posted in https://reviews.llvm.org/D131948

Aug 16 2022, 1:48 AM · Restricted Project, Restricted Project
avieira added reviewers for D131948: [TypePromotion] Only search for PHI + ZExt promotion of Integers: samparker, paulwalker-arm.
Aug 16 2022, 1:48 AM · Restricted Project, Restricted Project
avieira requested review of D131948: [TypePromotion] Only search for PHI + ZExt promotion of Integers.
Aug 16 2022, 1:47 AM · Restricted Project, Restricted Project

Aug 15 2022

avieira added a comment to D111237: [TypePromotion] Search from ZExt + PHI.

@avieira This patch looks to be breaking the AArch64/SVE buildbots. It's a compile time failure where getFixedSizeInBits() is being called on a scalable vector. Can you please take a look and perhaps revert the patch if it's not a quick fix?

See https://lab.llvm.org/buildbot/#/builders/197/builds/2467. Note 2466 also has failures but I've narrowed down the MultiSource/Applications/sgefa & SingleSource/UnitTests/Vectorizer ones to this patch.

Aug 15 2022, 10:17 AM · Restricted Project, Restricted Project

Aug 11 2022

avieira added a comment to D111237: [TypePromotion] Search from ZExt + PHI.

Fixed it in a NFC.

Aug 11 2022, 5:36 AM · Restricted Project, Restricted Project
avieira committed rGf9563967cadf: [TypePromotion] Update comment in testcase. RFC (authored by avieira).
[TypePromotion] Update comment in testcase. RFC
Aug 11 2022, 5:35 AM · Restricted Project, Restricted Project
avieira committed rG164067918725: [TypePromotion] Search from ZExt + PHI (authored by avieira).
[TypePromotion] Search from ZExt + PHI
Aug 11 2022, 1:51 AM · Restricted Project, Restricted Project
avieira committed rG05fc5037cd6c: [TypePromotion] Hoist out Promote Width calculation (authored by avieira).
[TypePromotion] Hoist out Promote Width calculation
Aug 11 2022, 1:51 AM · Restricted Project, Restricted Project
avieira committed rGe524d61f35a3: [TypePromotion] Don't delete Insns when iterating (authored by avieira).
[TypePromotion] Don't delete Insns when iterating
Aug 11 2022, 1:50 AM · Restricted Project, Restricted Project
avieira committed rG57de4e059ddc: [TypePromotion] Don't insert Truncate for a no-op ZExt (authored by avieira).
[TypePromotion] Don't insert Truncate for a no-op ZExt
Aug 11 2022, 1:50 AM · Restricted Project, Restricted Project
avieira closed D111237: [TypePromotion] Search from ZExt + PHI.
Aug 11 2022, 1:50 AM · Restricted Project, Restricted Project
avieira closed D131489: [TypePromotion] Hoist out Promote Width calculation.
Aug 11 2022, 1:50 AM · Restricted Project, Restricted Project
avieira closed D131488: [TypePromotion] Don't delete Insns when iterating.
Aug 11 2022, 1:50 AM · Restricted Project, Restricted Project
avieira closed D131487: [TypePromotion] Don't insert Truncate for a no-op ZExt.
Aug 11 2022, 1:50 AM · Restricted Project, Restricted Project

Aug 10 2022

avieira updated the diff for D111237: [TypePromotion] Search from ZExt + PHI.

Had not run this for ARM and there is a testcase there that also benefits from this change moving the zext up to the loads outside of the loop.

Aug 10 2022, 8:58 AM · Restricted Project, Restricted Project
avieira updated the diff for D131487: [TypePromotion] Don't insert Truncate for a no-op ZExt.

Is that somewhat clearer? I suspect the reason we never see a failure is because we 'replace' the input, rather than create a new ZExt. But like I said in the comment, it get's deleted. And as it is the trunc would just stay there dangling and get in the way of things.

Aug 10 2022, 8:55 AM · Restricted Project, Restricted Project
avieira updated the diff for D131487: [TypePromotion] Don't insert Truncate for a no-op ZExt.

I had forgotten to build for ARM too, which had similar testisms as AArch64 where this patch removes unnecessary Truncates. Updated tests.

Aug 10 2022, 6:21 AM · Restricted Project, Restricted Project
avieira added a comment to D131487: [TypePromotion] Don't insert Truncate for a no-op ZExt.

I'm just gonna rebase this to see if I also get the failure on TypePromotion/ARM/calls.ll that the bot is reporting.

Aug 10 2022, 3:06 AM · Restricted Project, Restricted Project

Aug 9 2022

avieira updated the diff for D111237: [TypePromotion] Search from ZExt + PHI.

Addressed comments by @samparker. This patch depends on D131487, D131488 and D131489.

Aug 9 2022, 5:53 AM · Restricted Project, Restricted Project
avieira requested review of D131489: [TypePromotion] Hoist out Promote Width calculation.
Aug 9 2022, 5:50 AM · Restricted Project, Restricted Project
avieira requested review of D131488: [TypePromotion] Don't delete Insns when iterating.
Aug 9 2022, 5:46 AM · Restricted Project, Restricted Project
avieira requested review of D131487: [TypePromotion] Don't insert Truncate for a no-op ZExt.
Aug 9 2022, 4:55 AM · Restricted Project, Restricted Project

Aug 8 2022

avieira updated the diff for D111237: [TypePromotion] Search from ZExt + PHI.

Hi all,

Aug 8 2022, 1:54 AM · Restricted Project, Restricted Project

May 23 2022

avieira committed rG572fc7d2fd14: [AArch64] Order STP Q's by ascending address (authored by avieira).
[AArch64] Order STP Q's by ascending address
May 23 2022, 1:51 AM · Restricted Project, Restricted Project
avieira closed D125377: [AArch64] Order STP Q's by ascending address.
May 23 2022, 1:51 AM · Restricted Project, Restricted Project
avieira added a comment to D125377: [AArch64] Order STP Q's by ascending address.

I believe that 'scheduling doesn't matter for Out of Order cores' is a long-standing myth that we've seen not to be correct. Yes, scheduling is definitely different for out of order cores, the problem shifts towards thinking about a sliding window of instructions that go into specific pipelines and dispatch queues and the likes. And you now find yourself trying to optimize the utilisation of pipelines, avoiding bubbles, rather than looking for the 'perfect sequence'. Out of order execution has some other limits and in some cases it helps if the compiler can lend the core a hand. In this case the Neoverse N1 prefers ascending STP Q's and an updated Neoverse N1 Software Optimization Guide will be reflecting this.

May 23 2022, 1:41 AM · Restricted Project, Restricted Project

May 17 2022

avieira added inline comments to D125377: [AArch64] Order STP Q's by ascending address.
May 17 2022, 3:36 AM · Restricted Project, Restricted Project
avieira updated the diff for D125377: [AArch64] Order STP Q's by ascending address.
May 17 2022, 3:35 AM · Restricted Project, Restricted Project

May 12 2022

avieira added inline comments to D125377: [AArch64] Order STP Q's by ascending address.
May 12 2022, 1:37 AM · Restricted Project, Restricted Project

May 11 2022

avieira added reviewers for D125377: [AArch64] Order STP Q's by ascending address: dmgreen, SjoerdMeijer.
May 11 2022, 5:13 AM · Restricted Project, Restricted Project
avieira requested review of D125377: [AArch64] Order STP Q's by ascending address.
May 11 2022, 5:12 AM · Restricted Project, Restricted Project

Feb 7 2022

avieira added a comment to D114637: [libc] Optimized version of memmove.

Hi @gchatelet,

I'm working on an aarch64 optimised version and I came across something that might be of use to you too. I found that the Repeated implementation of Move was yielding sub-optimal code in the large loop, it would load a _64 element in reverse (last 32-bytes first), I believe this was a side-effect of how it was stacking the loads and stores in opposite order like:
Load (src)
Load (src + 8)
Load (src + 16)
Load (src + 32)
Store (src + 32)
Store (src + 16)
...

Do you have an idea of why this is yielding suboptimal results?
In the code I generated for x86-64, using this pyramid shape offset pattern reduced the number of instructions (the compiler could outline the last store across different functions).
I'm not sure this translated into better performance though, only slightly smaller function size.

I found that changing the implementation of the Repeated Move to a for-loop of loads followed by a for-loop of stores from 0 to ElementCount solved it and gave me a speed up on larger memmoves.

Could you share the resulting asm?

Feb 7 2022, 8:58 AM · Restricted Project
avieira added a comment to D114637: [libc] Optimized version of memmove.

@avieira Shall I transform

static void move(char *dst, const char *src) {
  const auto value = Element::load(src);
  Repeated<Element, ElementCount - 1>::move(dst + Element::SIZE, src + Element::SIZE);
  Element::store(dst, value);
}

into

static void move(char *dst, const char *src) {
  const auto value = load(src);
  store(dst, value);
}

before submitting?
As discussed offline, this seems to help on aarch64 but doesn't seem to affect x86.

Feb 7 2022, 8:54 AM · Restricted Project

Dec 17 2021

avieira added a comment to D114637: [libc] Optimized version of memmove.

I'm working on an aarch64 optimised version and I came across something that might be of use to you too. I found that the Repeated implementation of Move was yielding sub-optimal code in the large loop, it would load a _64 element in reverse (last 32-bytes first), I believe this was a side-effect of how it was stacking the loads and stores in opposite order like:
Load (src)
Load (src + 8)
Load (src + 16)
Load (src + 32)
Store (src + 32)
Store (src + 16)
...

Dec 17 2021, 2:26 AM · Restricted Project

Dec 6 2021

avieira added a comment to D111237: [TypePromotion] Search from ZExt + PHI.

I could alternatively try to avoid generating the trunc

Yes, there's a TODO about avoiding the insertion in TypePromotion::isSink

Dec 6 2021, 9:36 AM · Restricted Project, Restricted Project
avieira added a comment to D111237: [TypePromotion] Search from ZExt + PHI.

Thanks for the suggestion @samparker . I hadn't look too much into it after I found that the ICmp promotion leaves the code in a somewhat 'dirty' state.
For instance if you take the motivating example from Snappy, the BB before the one with the PHI + ZEXT has an icmp that feeds into the relevant PHI node and it ends up yielding:

%tag.0.in10 = phi i32 [ %2, %for.body ], [ %0, %for.body.preheader ]
%1 = trunc i32 %tag.0.in10 to i8
%tag.0 = zext i8 %1 to i64
Dec 6 2021, 8:41 AM · Restricted Project, Restricted Project

Nov 30 2021

avieira added a comment to D111237: [TypePromotion] Search from ZExt + PHI.

I forgot to mention this address https://bugs.llvm.org/show_bug.cgi?id=51317 which is a suboptimal codegen issue encountered in snappy. Currently Snappy uses an inline asm workaround to make sure it doesn't end up with an extra 'and', this patch removes the need for that workaround.

Nov 30 2021, 3:30 AM · Restricted Project, Restricted Project

Nov 18 2021

avieira retitled D111237: [TypePromotion] Search from ZExt + PHI from [TypePromotion] Promote PHI-nodes to [TypePromotion] Promote PHI + [SZ]Ext.
Nov 18 2021, 3:45 AM · Restricted Project, Restricted Project
avieira updated the diff for D111237: [TypePromotion] Search from ZExt + PHI.

Coming back to this as I abandoned the approach in D112300, since that was deemed too early to be consulting target information.

Nov 18 2021, 3:45 AM · Restricted Project, Restricted Project
avieira abandoned D112300: [InstCombine] Don't split up Loads and free Exts.

Abandoning this in favour of reworking D111237.

Nov 18 2021, 2:36 AM · Restricted Project

Nov 1 2021

avieira added a comment to D112300: [InstCombine] Don't split up Loads and free Exts.

@spatel Yeah that's where I first made the change, but as I was working on it I noticed the original transformation was being done in InstCombine and as a practice I prefer to prevent transformations rather than undo them. I am guessing we are not in agreement on that. I've started reworking the original approach to do it in TypePromotion.

I actually agree that code sinking shouldn't be in instcombine, or it should be limited in some way (and there is a debug flag to disable it).

Check: by sinking, are you talking about just moving instructions into other blocks closer to their users?
Because the change here is not about that, but about [not] folding phi-of-loads to load-of-phi, i believe.

Ah, I didn't actually look at the details here. I thought it was about general sinking across blocks from the comments. Disregard if that was irrelevant.

Nov 1 2021, 2:21 PM · Restricted Project

Oct 25 2021

avieira added a comment to D112300: [InstCombine] Don't split up Loads and free Exts.

Fair enough, out of curiosity, where would you think this type of sinking should live in the optimization pipeline?

Oct 25 2021, 6:59 AM · Restricted Project
avieira added a comment to D112300: [InstCombine] Don't split up Loads and free Exts.

@spatel Yeah that's where I first made the change, but as I was working on it I noticed the original transformation was being done in InstCombine and as a practice I prefer to prevent transformations rather than undo them. I am guessing we are not in agreement on that. I've started reworking the original approach to do it in TypePromotion.

Oct 25 2021, 6:12 AM · Restricted Project
avieira added a comment to D112300: [InstCombine] Don't split up Loads and free Exts.

@lebedev.ri what do you suggest I do? I am not entirely sure I agree that sinking instructions like this is canonicalization, but that aside, separating these Loads and Exts is making codegen worse for targets that support widening loads. Targets that don't would probably be better off with the sinking transformation. This is why I'd like to use TTI here.

Oct 25 2021, 1:55 AM · Restricted Project

Oct 22 2021

avieira abandoned D111237: [TypePromotion] Search from ZExt + PHI.

Abandoning this in favor of D112300, I think that it would be better to try to avoid the sinking of the Exts rather than trying to undo them this late.

Oct 22 2021, 2:28 AM · Restricted Project, Restricted Project
avieira requested review of D112300: [InstCombine] Don't split up Loads and free Exts.
Oct 22 2021, 2:27 AM · Restricted Project

Oct 21 2021

avieira closed D112014: [libc] Add bcmp implementation for AArch64.

Has been applied but I forgot to include the Differential Revision.

Oct 21 2021, 6:07 AM
avieira accepted D112014: [libc] Add bcmp implementation for AArch64.

Ah ... and I forgot to add the Differential Review to the commit... So I'll close this manually.

Oct 21 2021, 6:06 AM
avieira updated the diff for D112014: [libc] Add bcmp implementation for AArch64.
Oct 21 2021, 6:06 AM
avieira added inline comments to D112014: [libc] Add bcmp implementation for AArch64.
Oct 21 2021, 3:36 AM

Oct 20 2021

avieira added a comment to D112014: [libc] Add bcmp implementation for AArch64.

Took me three attempts, will apply after the pre-merge checks and build are done.

Oct 20 2021, 8:29 AM
avieira updated the diff for D112014: [libc] Add bcmp implementation for AArch64.
Oct 20 2021, 8:28 AM
avieira updated the diff for D112014: [libc] Add bcmp implementation for AArch64.
Oct 20 2021, 8:22 AM

Oct 19 2021

avieira added a reviewer for D111237: [TypePromotion] Search from ZExt + PHI: adriantong1024.
Oct 19 2021, 1:41 AM · Restricted Project, Restricted Project

Oct 18 2021

avieira requested review of D112014: [libc] Add bcmp implementation for AArch64.
Oct 18 2021, 9:28 AM

Oct 11 2021

avieira added a comment to D111237: [TypePromotion] Search from ZExt + PHI.

I found that other than the motivation example I showed above coming up with C-level examples, especially for cases where I don't think transforming is a good idea is difficult. I'll see if I have better luck with IR tests.

Oct 11 2021, 3:48 AM · Restricted Project, Restricted Project

Oct 6 2021

avieira requested review of D111237: [TypePromotion] Search from ZExt + PHI.
Oct 6 2021, 9:06 AM · Restricted Project, Restricted Project

Sep 23 2021

avieira committed rG8b87c3d57367: [libc] Add optimized memset for AArch64 (authored by avieira).
[libc] Add optimized memset for AArch64
Sep 23 2021, 1:22 AM
avieira closed D107848: [libc] Add optimized memset for AArch64.
Sep 23 2021, 1:22 AM · Restricted Project

Sep 17 2021

avieira added a comment to D107848: [libc] Add optimized memset for AArch64.

Are dc zva and mrs broadly available on aarch64 or should they be guarded by some #define?
They are available for any AArch64 ISA, so no define required since this is for AArch64 only.

Sep 17 2021, 8:25 AM · Restricted Project
avieira updated the diff for D107848: [libc] Add optimized memset for AArch64.
Sep 17 2021, 8:23 AM · Restricted Project

Aug 12 2021

avieira added a comment to D107848: [libc] Add optimized memset for AArch64.

Yeah no problem!

Aug 12 2021, 7:15 AM · Restricted Project

Aug 10 2021

avieira requested review of D107848: [libc] Add optimized memset for AArch64.
Aug 10 2021, 10:56 AM · Restricted Project

Aug 4 2021

avieira committed rG2f002817fb46: [libc] Fix Memory Benchmarks code after rename (authored by avieira).
[libc] Fix Memory Benchmarks code after rename
Aug 4 2021, 1:18 AM
avieira closed D107376: [libc] Fix Memory Benchmarks code after rename.
Aug 4 2021, 1:18 AM · Restricted Project

Aug 3 2021

avieira requested review of D107376: [libc] Fix Memory Benchmarks code after rename.
Aug 3 2021, 10:19 AM · Restricted Project

Jul 29 2021

avieira added a comment to D106641: [libc] rewrite aarch64 memcmp implementation.

LGTM

Jul 29 2021, 4:09 AM · Restricted Project

Jul 23 2021

avieira added inline comments to D106641: [libc] rewrite aarch64 memcmp implementation.
Jul 23 2021, 3:39 AM · Restricted Project

Jul 7 2021

avieira abandoned D105440: [RFC] Implement support for __builtin_memcmp_inline.
Jul 7 2021, 8:00 AM · Restricted Project
avieira committed rG366805ea175e: [LIBC] Add an optimized memcmp implementation for AArch64 (authored by avieira).
[LIBC] Add an optimized memcmp implementation for AArch64
Jul 7 2021, 7:59 AM
avieira closed D105441: [LIBC] Add an optimized memcmp implementation for AArch64.
Jul 7 2021, 7:59 AM · Restricted Project
avieira added inline comments to D105441: [LIBC] Add an optimized memcmp implementation for AArch64.
Jul 7 2021, 6:36 AM · Restricted Project
avieira updated the diff for D105441: [LIBC] Add an optimized memcmp implementation for AArch64.
Jul 7 2021, 6:35 AM · Restricted Project
avieira added inline comments to D105441: [LIBC] Add an optimized memcmp implementation for AArch64.
Jul 7 2021, 5:44 AM · Restricted Project
avieira updated the diff for D105441: [LIBC] Add an optimized memcmp implementation for AArch64.
Jul 7 2021, 5:44 AM · Restricted Project
avieira updated the diff for D105441: [LIBC] Add an optimized memcmp implementation for AArch64.

I think I've addressed all the comments and style issues.

Jul 7 2021, 3:37 AM · Restricted Project
avieira added a comment to D105440: [RFC] Implement support for __builtin_memcmp_inline.

The motivation here seems weaker than it was for memcpy. memcmp is much less fundamental to LLVM optimizations. It looks like the primary motivation here is to avoid duplicating the logic in llvm/lib/CodeGen/ExpandMemCmp.cpp ? But really, it isn't very much target-independent logic, and the only target-specific bit is the heuristic for load widths.

I'd rather not duplicate logic in llvm/lib/CodeGen/ExpandMemCmp.cpp they may get out of sync.

The problem, from my perspective, is that you'll have to duplicate the logic to some extent anyway.

I see, we'll probably have to extract the shared logic in one or more libraries then.

Jul 7 2021, 1:58 AM · Restricted Project

Jul 5 2021

avieira requested review of D105441: [LIBC] Add an optimized memcmp implementation for AArch64.
Jul 5 2021, 10:31 AM · Restricted Project
avieira requested review of D105440: [RFC] Implement support for __builtin_memcmp_inline.
Jul 5 2021, 10:27 AM · Restricted Project

May 6 2021

avieira added inline comments to D101895: [libc] Simplifies multi implementations.
May 6 2021, 6:33 AM · Restricted Project

May 5 2021

avieira added a comment to D101895: [libc] Simplifies multi implementations.

LGTM otherwise.

May 5 2021, 9:18 AM · Restricted Project

Apr 28 2021

avieira added inline comments to D100646: [libc] Add a set of elementary operations.
Apr 28 2021, 9:13 AM · Restricted Project

Apr 23 2021

avieira added a comment to D100646: [libc] Add a set of elementary operations.

Alright I'll give it a wait, I was currently trying to figure out why I can't build the libc_string_unittests, getting a build error around elements_test.cpp saying there's an issue with the 'cstring' header file 'no member named 'strcmp' in the global namespace' which is an odd one ... What libc++ library do you use to build this normally?

Apr 23 2021, 7:48 AM · Restricted Project
avieira added a comment to D100646: [libc] Add a set of elementary operations.

I'm going to try to rewrite my memcmp implementation using these now and report findings as I go through it :).

Apr 23 2021, 7:29 AM · Restricted Project

Apr 22 2021

avieira added inline comments to D100646: [libc] Add a set of elementary operations.
Apr 22 2021, 5:08 AM · Restricted Project

Feb 4 2021

avieira added a comment to D92235: [ARM] Turn pred_cast(xor(x, -1)) into xor(pred_cast(x), -1).

Accidentally linked my commit of https://reviews.llvm.org/D92236 to this revision. Apologies.

Feb 4 2021, 4:18 AM · Restricted Project
avieira closed D92236: [LIBC] Add optimized memcpy routine for AArch64.

I've committed the patch in https://reviews.llvm.org/rG369f7de3135a517a69c45084d4b175f7b0d5e6f5 but it seems when copying the revision link I may have hit ctrl + x in vim and linked it to D92235 :(

Feb 4 2021, 4:17 AM · Restricted Project

Feb 3 2021

avieira committed rG369f7de3135a: [LIBC] Add optimized memcpy routine for AArch64 (authored by avieira).
[LIBC] Add optimized memcpy routine for AArch64
Feb 3 2021, 1:32 AM

Jan 24 2021

avieira committed rG8fbc1437c605: [AArch64] Merge [US]MULL with half adds and subs into [US]ML[AS]L (authored by avieira).
[AArch64] Merge [US]MULL with half adds and subs into [US]ML[AS]L
Jan 24 2021, 11:59 PM
avieira closed D95218: [AArch64] Merge [US]MULL with half adds and subs into [US]ML[AS]L.
Jan 24 2021, 11:58 PM · Restricted Project