[SelectionDAG][PowerPC] Memset reuse vector element for tail store

[tingwang]

Summary

On PPC there are instructions to store element from vector(e.g. stxsdx/stxsiwx), and these instructions can be leveraged to avoid tail constant in memset and constant splat array initialization.

This patch tries to explore these opportunities.

[nemanjai]

I think this is useful, but we should ensure we can get rid of the swap that this introduces (in a separate patch).

llvm/include/llvm/CodeGen/TargetLowering.h

672 ↗

(On Diff #478424)

Do we need this? Can canCombineStoreAndExtract() suffice for this purpose?

llvm/test/CodeGen/PowerPC/memset-tail.ll

195

Why do we now get the redundant swap for the vector store that we didn't get before? Was it eliminated by the swap elimination before and now it is not because we have a use of the partial vector?

[nemanjai]

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

7310

Can we reduce the nesting here by converting this to else if?

[tingwang]

Update according to comments:
(1) Use existing canCombineStoreAndExtract() instead of creating new.
(2) Nest the else statement properly.
(3) Saw two cases changed due to (1).

[tingwang]

llvm/include/llvm/CodeGen/TargetLowering.h

672 ↗

(On Diff #478424)

Thank you! I did a try and updated patch. Saw two cases changed. I will look into the detail tomorrow.

llvm/test/CodeGen/PowerPC/memset-tail.ll

195

Debug-only ppc-vsx-swaps shows "Web 0 rejected for physreg, partial reg, or not swap[pable]". I will look into it and probably post another patch to fix the issue. Thank you!

[tingwang]

Realized I need to use PPCTTIImpl::getVectorInstrCost() API to determine the cost of instructions. I'm working on it now.

[tingwang]

Changes in this update:
(1) I was trying to use TTI.getVectorInstrCost() to query instruction cost in PPCTargetLowering::canCombineStoreAndExtract(). However not able to reach TTI, and didn't find any reference to do that in SDAG. Given that the original implementation of canCombineStoreAndExtract() on ARM implemented its own logic to calculate Cost, followed the approach and implemented logic by referring to PPCTTIImpl::getVectorInstrCost().

(2) Refactored logic inside getMemsetStores(). For PPC CombineStoreAndExtract is beneficial on some specific element index according to endianness and instruction (StoreAndExtract elements on other indexes requires vector permutation, which makes the whole idea less attractive). Since this is platform independent logic, I'm querying the cost for indexes, and pick the least cost to do the combine.

[tingwang]

llvm/test/CodeGen/PowerPC/p10-fi-elim.ll

31–36

Instruction sequence change in PowerPC/p10-fi-elim.ll is result of CodeGenPrepare::optimizeExtractElementInst() now can generate combined pattern since we enabled canCombineStoreAndExtract(). Seems we can avoid two mfvsrd instructions.

[tingwang]

llvm/test/CodeGen/ARM/memset-align.ll

21

Hello @dmgreen @asavonic. This patch tries to reuse vector element for the tail store in memset by implementing canCombineStoreAndExtract() on PPC. This changed introduced test case change on ARM in llvm/test/CodeGen/ARM/memset-align.ll. Could you please help me check if the change looks good or not? Thank you!

Looked into the scenario on ARM, if the i8 fill value of memset is zero, it creates vector for the initial 16B, and constant tail for the remaining bytes, which exactly hit this patch's scenario. For other values, it creates i32 for memset and will not be impacted by this patch.

[tingwang]

Add memset-tail.ll changes.

[lkail]

I would expect not only memset, some consecutive stores could also reuse the result of vector split, see https://godbolt.org/z/77aMvncb4.
For

void foo(long a[3]) {
    a[0] = 12;
    a[1] = 12;
    a[2] = 12;
}

foo(long*):                               # @foo(long*)
        .quad   .Lfunc_begin0
        .quad   .TOC.@tocbase
        .quad   0
.Lfunc_begin0:
        xxlxor 0, 0, 0
        li 4, 12
        xxsplti32dx 0, 1, 12
        std 4, 16(3)
        stxv 0, 0(3)
        blr
        .long   0
        .quad   0

We don't reuse the result of xxsplti32dx.

[tingwang]

In D138883#3962255, @lkail wrote:

I would expect not only memset, some consecutive stores could also reuse the result of vector split, see https://godbolt.org/z/77aMvncb4.
For

void foo(long a[3]) {
    a[0] = 12;
    a[1] = 12;
    a[2] = 12;
}

foo(long*):                               # @foo(long*)
        .quad   .Lfunc_begin0
        .quad   .TOC.@tocbase
        .quad   0
.Lfunc_begin0:
        xxlxor 0, 0, 0
        li 4, 12
        xxsplti32dx 0, 1, 12
        std 4, 16(3)
        stxv 0, 0(3)
        blr
        .long   0
        .quad   0

We don't reuse the result of xxsplti32dx.

Sure. The posted IR could be handled by DAGCombiner::mergeConsecutiveStores(), and I agree similar combine can be applied there. But for this case, memset stores are volatile, and DAGCombiner::getStoreMergeCandidates() does not accept volatile store currently.

[asavonic]

llvm/test/CodeGen/ARM/memset-align.ll

21

This looks fine to me. VST1 and scalar STR seem equivalent in this case, if I'm reading the docs right.

[tingwang]

llvm/test/CodeGen/ARM/memset-align.ll

21

This looks fine to me. VST1 and scalar STR seem equivalent in this case, if I'm reading the docs right.

Thank you for the confirm!

[tingwang]

Test case update.

[tingwang]

In D138883#3955904, @nemanjai wrote:

I think this is useful, but we should ensure we can get rid of the swap that this introduces (in a separate patch).

According to my test case, there are two kinds of swap in LE: (1) swap after vector splat immediate; (2) swap after load from constant-pool. Submitted two patches D139193 and D139491 to address them separately.

[tingwang]

Gentle ping.

[tingwang]

Update patch as following test case pattern changed:
llvm/test/CodeGen/ARM/memset-align.ll

[tingwang]

Gentle ping.

[tingwang]

Gentle ping.

[tingwang]

Rebase && Gentle ping.

[nemanjai]

While I am not principally against this approach, it doesn't really give me a great feeling going in this direction. The issue is more widespread than just memset/memcpy/memmove as Kai's example illustrates.
I wonder if it would be a more complete solution to add a DAG combine that looks up the chain from the store to see if a store of a splat of the same value exists. That should certainly cover both examples.

[tingwang]

I will try to get similar results by DAG combine. Thanks to Nemanja and Kai's insight!

[tingwang]

Redo the implementation, and now both memset and constant splat array initialization get changed.

[tingwang]

Plan to continue improve the patch...

[tingwang]

(1) Format code to follow coding style guidance.
(2) Fix SplatValue check.
(3) Remaining redundant instructions like mtfprd will be fixed in separate patches.

[tingwang]

(1) Update element type ElemTy which now matches the type expected by both STFIWX and STXSIX PPCISD nodes.
(2) Add missing match pattern for PPCstxsix.

[tingwang]

Update StoreSizeInBits check to skip on PowerOf2 bit size less than 8.

[tingwang]

Attempt to push the logic into DAGCombiner::mergeConsecutiveStores()...

[nemanjai]

Sorry, I had unsubmitted comments. Not sure if they still apply.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

14854

Nit: you don't need the name of the function here.

14868

What if dyn_cast returns null (i.e. if operand 1 is not a constant)?

14877–14879

We don't need to construct an APInt just to check whether it is a power of 2. You can just use isPowerOf2_64() from MathExtras.h.

[tingwang]

In D138883#4181453, @nemanjai wrote:

Sorry, I had unsubmitted comments. Not sure if they still apply.

Hi Nemanja,

Appreciate your help! I planned to change due to the reason that DAGCombiner::getStoreMergeCandidates() already walks through chain of stores, and I realized that it could be a better place to find candidate for this opportunity. By the way, maybe the criteria of splat of constant could be relieved to just match the subsection that is extracted by the target store, and I would like to have a try.

I hope next version will be final for review. Thank you again for taking time looking into this!

[tingwang]

Since canCombineStoreAndExtract() target hook looks not good on PPC, reconsider use this approach to do the combine.

Change in this version:
(1) Address comments from previous review.
(2) Add check to make sure do not combine on truncated stores or those stores that return value.

[tingwang]

Gentle ping. Since the alternative path (D146602/D146610) looks not good, shall we take this approach forward? Any comments are welcome. Thank you!

[tingwang]

Minor update:
(1) Add bitwidth is multiple of check for isSplat() call.
(2) Reduce MaxSearchNodes from 4 to 3, this is the minimum setting to allow target patterns in test cases.

And ping...

[tingwang]

Rebase and added some comments.

Hi @nemanjai, I accepted and addressed your previous comments. Do you have any more concerns on the approach that is implemented here? Thank you!

[nemanjai]

In D138883#4479380, @tingwang wrote:

Rebase and added some comments.

Hi @nemanjai, I accepted and addressed your previous comments. Do you have any more concerns on the approach that is implemented here? Thank you!

I am really sorry about the delay...
While I am not completely opposed to this, it seems like a fair bit of machinery to add for something that we could solve more simply with unaligned stores (i.e. the same way we would codegen a memset where the tail is *not* a power of 2).

I don't think that

xxspltib 0, 165
li 4, 16
stxsibx 0, 3, 4
stxv 0, 0(3)

is any better than

xxspltib 0, 165
li 4, 1
stxvx 0, 3, 4
stxv 0, 0(3)

Is it possible to do something like that without walking the chain and with existing capabilities?

[tingwang]

Hi @nemanjai, appreciate your time looking into this patch. Thank you!

I agree with you, and I think walking the chain is burning CPU cycles without achieving anything. I realized it is difficult for me to take both targets (the original memset case, and the one @lkail mentioned) in this patch, so I would like to drop the second target, in order to focus on the first one.

I like the idea to use unaligned store, and quickly tested that to see if any potential issue. Created memset.c with multiple memset(p, 0xXY, 24); lines to stress the performance. According to my numbers from Power10, use extract-and-store (https://reviews.llvm.org/D138883?id=493461) got 17% faster than baseline, whereas unaligned store got about 30% slower than baseline.

From performance perspective, I think I should pursuit the original approach. However since canCombineStoreAndExtract target hook has been proved not beneficial (https://reviews.llvm.org/D146602) on PPC, I probably need to create one for PPC only at this moment.

Let me know if any comments. I will post patch shortly.

memset.c92 KBDownload

[tingwang]

Return to the initial proposal after exploring different approaches. Since canCombineStoreAndExtract() is not beneficial to PPC, created another filter for PPC.

[tingwang]

llvm/test/CodeGen/PowerPC/memset-tail.ll

195

Will be eliminated by https://reviews.llvm.org/D139193.

237

Plan to address this pattern in separate patch.

246

Will be eliminated by https://reviews.llvm.org/D139193.

261

Plan to address this pattern in separate patch.

299

Will be eliminated by https://reviews.llvm.org/D139193.

353

Will be eliminated by https://reviews.llvm.org/D139193.

474

Plan to address this pattern in separate patch.

474

Plan to address this pattern in separate patch.

[tingwang]

(1) Rebase after commit D139193.
(2) Add two P10 patterns to match extract-and-store.

Now test case is clean. Gentle ping.

[tingwang]

Rebase && Ping.

[tingwang]

Gentle ping...

[tingwang]

Gentle ping...

[shchenz]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

16828

If using stfd is allowed for tail size 5/6/7, then can we use stfd for tail size 3/4 too? (I assume the change here impacts cases memsetTailV1B3 and memsetTailV1B4?)

llvm/test/CodeGen/PowerPC/memset-tail.ll

245

This seems a legacy issue because I also found same issue in case memsetTailV1B12 and also from the left side of this case.

Is it safe to extend the store length from 23 bytes to 32(or 24) bytes here? There is no clue saying that memory after (char *)p + 7 is writable by the user?

The related logic is in allowsMisalignedMemoryAccesses(). But is it correct that we can safely assume this memset can write more memory even this memset handles aligned memory?

What do you think? @nemanjai

[shchenz]

llvm/test/CodeGen/PowerPC/memset-tail.ll

245

Sorry, please ignore this comment. I didn't realize that the two stores stxsdx and stxvd2x have overlaps. So the real write size is not extended.

[tingwang]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

16828

It seems TargetLowering::findOptimalMemOpLowering() decides the type of each store. I guess if we change the type for the size 3/4 case from i32 to i64, then it will result in stfd.

[shchenz]

This LGTM with some nits.

Let's first target for the memset cases as this is the common case where splat values happens.

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

7271

Nit: this comment needs update?

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

1617

nit: We may need comments here why we don't try to extract constant for ElemSizeInBits 8/16. (I guess the reason is we don't have benefit as we need li to load the index and this li can also be used to load the 8/16 bit imm?

16828

Thanks. Better to add some comment here why we need to set the type to MVT::v8i16

[tingwang]

In D138883#4639161, @shchenz wrote:

This LGTM with some nits.

Let's first target for the memset cases as this is the common case where splat values happens.

Thank you! I will address the remaining comments in the commit.

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

for (unsigned i = 0; i < NumMemOps; i++) {
     if (VTSize > Size) {
       // Issuing an unaligned load / store pair  that overlaps with the previous
       // pair. Adjust the offset accordingly.
       assert(i == NumMemOps-1 && i != 0);
       DstOff -= VTSize - Size;
     }
 
     // If this store is smaller than the largest store see whether we can get
     // the smaller value for free with a truncate.
     SDValue Value = MemSetValue;
     if (VT.bitsLT(LargestVT)) {
+      // Helper function to query least cost index for CombineStoreAndExtract.
+      const auto QueryIndex = [](const TargetLowering &TLI, SelectionDAG &DAG,
+                                 EVT Type, unsigned NumElts, unsigned &Index) {
+        Index = -1U;
+        unsigned Cost = std::numeric_limits<unsigned>::max();
+        bool Ret = false;
+        for (unsigned i = 0; i < NumElts; ++i) {
+          unsigned TmpC;
+          if (TLI.canCombineStoreAndExtract(
+                  Type.getTypeForEVT(*DAG.getContext()),
+                  ConstantInt::get(*DAG.getContext(), APInt(8, i)), TmpC) &&
+              TmpC < Cost) {
+            Cost = TmpC;
+            Index = i;
+            Ret = true;
+          }
+        }
+        return Ret;
+      };
+
+      unsigned Index;
+      unsigned NElts = LargestVT.getSizeInBits() / VT.getSizeInBits();
+      EVT SVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), NElts);
       if (!LargestVT.isVector() && !VT.isVector() &&
           TLI.isTruncateFree(LargestVT, VT))
         Value = DAG.getNode(ISD::TRUNCATE, dl, VT, MemSetValue);
-      else
+      else if (LargestVT.isVector() && !VT.isVector() &&
+               QueryIndex(TLI, DAG, SVT, NElts, Index) &&
+               TLI.isTypeLegal(SVT) &&
+               LargestVT.getSizeInBits() == SVT.getSizeInBits()) {
+        // Target which can combine store(extractelement VectorTy, Idx) can get
+        // the smaller value for free.
+        SDValue TailValue = DAG.getNode(ISD::BITCAST, dl, SVT, MemSetValue);
+        Value = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, TailValue,
+                            DAG.getVectorIdxConstant(Index, dl));
+      } else
         Value = getMemsetValue(Src, VT, DAG, dl);
     }
     assert(Value.getValueType() == VT && "Value with wrong type.");
     SDValue Store = DAG.getStore(
         Chain, dl, Value,
         DAG.getMemBasePlusOffset(Dst, TypeSize::Fixed(DstOff), dl),
         DstPtrInfo.getWithOffset(DstOff), Alignment,
         isVol ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone,
         NewAAInfo);

llvm/lib/Target/PowerPC/PPCISelLowering.h

public:
     bool isCheapToSpeculateCttz(Type *Ty) const override {
       return true;
     }
 
     bool isCheapToSpeculateCtlz(Type *Ty) const override {
       return true;
     }
 
+    bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
+                                   unsigned &Cost) const override;
+
     bool isCtlzFast() const override {
       return true;
     }
 
     bool isEqualityCmpFoldedWithSignedCmp() const override {
       return false;
     }
 

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

 bool PPCTargetLowering::hasSPE() const {
   return Subtarget.hasSPE();
 }
 
 bool PPCTargetLowering::preferIncOfAddToSubOfNot(EVT VT) const {
   return VT.isScalarInteger();
 }
 
+bool PPCTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
+                                                  unsigned &Cost) const {
+  if (!Subtarget.isPPC64() || !Subtarget.hasVSX())
+    return false;
+
+  if (!isa<ConstantInt>(Idx))
+    return false;
+
+  if (auto *VTy = dyn_cast<VectorType>(VectorTy)) {
+    if (VTy->getScalarType()->isIntegerTy()) {
+      unsigned BitWidth = VTy->getScalarSizeInBits();
+      unsigned ElemIdx;
+      // Accept the combine only if the element index matches the one that can
+      // be directly move-from VSR.
+      if (BitWidth == 32) {
+        ElemIdx = Subtarget.isLittleEndian() ? 2 : 1;
+      } else if (BitWidth == 64) {
+        ElemIdx = Subtarget.isLittleEndian() ? 1 : 0;
+      } else {
+        return false;
+      }
+      if (cast<ConstantInt>(Idx)->getZExtValue() == ElemIdx) {
+        Cost = 1;
+        return true;
+      }
+    }
+  }
+  return false;
+}
+
 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch ((PPCISD::NodeType)Opcode) {
   case PPCISD::FIRST_NUMBER:    break;
   case PPCISD::FSEL:            return "PPCISD::FSEL";
   case PPCISD::XSMAXC:          return "PPCISD::XSMAXC";
   case PPCISD::XSMINC:          return "PPCISD::XSMINC";
   case PPCISD::FCFID:           return "PPCISD::FCFID";
   case PPCISD::FCFIDU:          return "PPCISD::FCFIDU";
SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
   SDValue StoreOps[] = { Chain, Swap, Base };
   SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
                                           DAG.getVTList(MVT::Other),
                                           StoreOps, VecTy, MMO);
   DCI.AddToWorklist(Store.getNode());
   return Store;
 }
 
 // Handle DAG combine for STORE (FP_TO_INT F).
 SDValue PPCTargetLowering::combineStoreFPToInt(SDNode *N,
                                                DAGCombinerInfo &DCI) const {
 
   SelectionDAG &DAG = DCI.DAG;
   SDLoc dl(N);
   unsigned Opcode = N->getOperand(1).getOpcode();
 
   assert((Opcode == ISD::FP_TO_SINT || Opcode == ISD::FP_TO_UINT)
          && "Not a FP_TO_INT Instruction!");
 
   SDValue Val = N->getOperand(1).getOperand(0);
   EVT Op1VT = N->getOperand(1).getValueType();
   EVT ResVT = Val.getValueType();
 
   if (!isTypeLegal(ResVT))
     return SDValue();
 
   // Only perform combine for conversion to i64/i32 or power9 i16/i8.
   bool ValidTypeForStoreFltAsInt =
         (Op1VT == MVT::i32 || Op1VT == MVT::i64 ||
          (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8)));
 
   if (ResVT == MVT::f128 && !Subtarget.hasP9Vector())
     return SDValue();
 
   if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Vector() ||
       cast<StoreSDNode>(N)->isTruncatingStore() || !ValidTypeForStoreFltAsInt)
     return SDValue();
 
   // Extend f32 values to f64
   if (ResVT.getScalarSizeInBits() == 32) {
     Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
     DCI.AddToWorklist(Val.getNode());

 
 /// It returns EVT::Other if the type should be determined using generic
 /// target-independent logic.
 EVT PPCTargetLowering::getOptimalMemOpType(
     const MemOp &Op, const AttributeList &FuncAttributes) const {
   if (getTargetMachine().getOptLevel() != CodeGenOpt::None) {
     // We should use Altivec/VSX loads and stores when available. For unaligned
     // addresses, unaligned VSX loads are only fast starting with the P8.
-    if (Subtarget.hasAltivec() && Op.size() >= 16 &&
-        (Op.isAligned(Align(16)) ||
-         ((Op.isMemset() && Subtarget.hasVSX()) || Subtarget.hasP8Vector())))
+    if (Subtarget.hasAltivec() && Op.size() >= 16) {
+      if (Op.isMemset() && Subtarget.hasVSX()) {
+        uint64_t TailSize = Op.size() % 16;
+        // For memset lowering, tail size need be different from vector element
+        // size to allow borrow tail from vector, otherwise constant tail will
+        // be generated.
+        if (TailSize > 2 && TailSize <= 4) {
+          return MVT::v8i16;
+        }
         return MVT::v4i32;
       }
+      if (Op.isAligned(Align(16)) || Subtarget.hasP8Vector())
+        return MVT::v4i32;
+    }
+  }
 
   if (Subtarget.isPPC64()) {
     return MVT::i64;
   }
 
   return MVT::i32;
 }
 

llvm/test/CodeGen/ARM/memset-align.ll

 ; CHECK-NEXT:    vmov.i32 q8, #0x0
 ; CHECK-NEXT:    mov r0, sp
 ; CHECK-NEXT:    mov.w r1, #-1
 ; CHECK-NEXT:    mov r2, r0
 ; CHECK-NEXT:    strd r1, r1, [sp, #8]
 ; CHECK-NEXT:    strd r1, r1, [sp]
 ; CHECK-NEXT:    vst1.64 {d16, d17}, [r2]!
 ; CHECK-NEXT:    str r1, [r2]
+; CHECK-NEXT:    add.w r2, r0, #15
+; CHECK-NEXT:    vst1.32 {d16[0]}, [r2]
 ; CHECK-NEXT:    str r1, [sp, #20]
-; CHECK-NEXT:    movs r1, #0
-; CHECK-NEXT:    str.w r1, [sp, #15]
 ; CHECK-NEXT:    bl callee
 ; CHECK-NEXT:    add sp, #24
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
   %a = alloca %struct.af, align 8
   %0 = bitcast %struct.af* %a to i8*
   %1 = bitcast %struct.af* %a to i8*
   call void @llvm.memset.p0i8.i64(i8* align 8 %1, i8 -1, i64 24, i1 false)
   call void @llvm.memset.p0i8.i64(i8* align 8 %0, i8 0, i64 19, i1 false)
   call void @callee(%struct.af* %a)
   ret void
 }
 
 declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1 immarg)
 declare void @callee(%struct.af*) local_unnamed_addr #1

llvm/test/CodeGen/PowerPC/memset-tail.ll

entry:
   tail call void @llvm.memset.p0.i64(ptr %p, i8 15, i64 25, i1 false)
   ret void
 }
 
 define dso_local void @memsetTailV1B8(ptr nocapture noundef writeonly %p) local_unnamed_addr {
 ; P8-BE-LABEL: memsetTailV1B8:
 ; P8-BE:       # %bb.0: # %entry
 ; P8-BE-NEXT:    vspltisb 2, 15
-; P8-BE-NEXT:    lis 4, 3855
-; P8-BE-NEXT:    ori 4, 4, 3855
-; P8-BE-NEXT:    rldimi 4, 4, 32, 0
+; P8-BE-NEXT:    li 4, 16
+; P8-BE-NEXT:    stxsdx 34, 3, 4
 ; P8-BE-NEXT:    stxvw4x 34, 0, 3
-; P8-BE-NEXT:    std 4, 16(3)
 ; P8-BE-NEXT:    blr
 ;
 ; P9-BE-LABEL: memsetTailV1B8:
 ; P9-BE:       # %bb.0: # %entry
-; P9-BE-NEXT:    lis 4, 3855
 ; P9-BE-NEXT:    xxspltib 0, 15
-; P9-BE-NEXT:    ori 4, 4, 3855
 ; P9-BE-NEXT:    stxv 0, 0(3)
-; P9-BE-NEXT:    rldimi 4, 4, 32, 0
-; P9-BE-NEXT:    std 4, 16(3)
+; P9-BE-NEXT:    stfd 0, 16(3)
 ; P9-BE-NEXT:    blr
 ;
 ; P10-BE-LABEL: memsetTailV1B8:
 ; P10-BE:       # %bb.0: # %entry
-; P10-BE-NEXT:    pli 4, 252645135
-; P10-BE-NEXT:    rldimi 4, 4, 32, 0
-; P10-BE-NEXT:    std 4, 16(3)
 ; P10-BE-NEXT:    xxspltib 0, 15
 ; P10-BE-NEXT:    stxv 0, 0(3)
+; P10-BE-NEXT:    stfd 0, 16(3)
 ; P10-BE-NEXT:    blr
 ;
 ; P8-LE-LABEL: memsetTailV1B8:
 ; P8-LE:       # %bb.0: # %entry
-; P8-LE-NEXT:    lis 4, 3855
 ; P8-LE-NEXT:    vspltisb 2, 15
-; P8-LE-NEXT:    ori 4, 4, 3855
-; P8-LE-NEXT:    rldimi 4, 4, 32, 0
-; P8-LE-NEXT:    std 4, 16(3)
-; P8-LE-NEXT:    stxvd2x 34, 0, 3
+; P8-LE-NEXT:    li 4, 16
+; P8-LE-NEXT:    xxswapd 0, 34
+; P8-LE-NEXT:    stxsdx 34, 3, 4
+; P8-LE-NEXT:    stxvd2x 0, 0, 3
 ; P8-LE-NEXT:    blr
 ;
 ; P9-LE-LABEL: memsetTailV1B8:
 ; P9-LE:       # %bb.0: # %entry
-; P9-LE-NEXT:    lis 4, 3855
 ; P9-LE-NEXT:    xxspltib 0, 15
-; P9-LE-NEXT:    ori 4, 4, 3855
 ; P9-LE-NEXT:    stxv 0, 0(3)
-; P9-LE-NEXT:    rldimi 4, 4, 32, 0
-; P9-LE-NEXT:    std 4, 16(3)
+; P9-LE-NEXT:    stfd 0, 16(3)
 ; P9-LE-NEXT:    blr
 ;
 ; P10-LE-LABEL: memsetTailV1B8:
 ; P10-LE:       # %bb.0: # %entry
-; P10-LE-NEXT:    pli 4, 252645135
-; P10-LE-NEXT:    rldimi 4, 4, 32, 0
-; P10-LE-NEXT:    std 4, 16(3)
 ; P10-LE-NEXT:    xxspltib 0, 15
 ; P10-LE-NEXT:    stxv 0, 0(3)
+; P10-LE-NEXT:    stfd 0, 16(3)
 ; P10-LE-NEXT:    blr
 entry:
   tail call void @llvm.memset.p0.i64(ptr %p, i8 15, i64 24, i1 false)
   ret void
 }
 
 define dso_local void @memsetTailV1B7(ptr nocapture noundef writeonly %p) local_unnamed_addr {
 ; P8-BE-LABEL: memsetTailV1B7:
 ; P8-BE:       # %bb.0: # %entry
-; P8-BE-NEXT:    lis 4, 3855
 ; P8-BE-NEXT:    vspltisb 2, 15
-; P8-BE-NEXT:    li 5, 15
-; P8-BE-NEXT:    ori 4, 4, 3855
-; P8-BE-NEXT:    rldimi 4, 4, 32, 0
-; P8-BE-NEXT:    stdx 4, 3, 5
+; P8-BE-NEXT:    li 4, 15
+; P8-BE-NEXT:    stxsdx 34, 3, 4
 ; P8-BE-NEXT:    stxvw4x 34, 0, 3
 ; P8-BE-NEXT:    blr
 ;
 ; P9-BE-LABEL: memsetTailV1B7:
 ; P9-BE:       # %bb.0: # %entry
-; P9-BE-NEXT:    lis 4, 3855
-; P9-BE-NEXT:    li 5, 15
-; P9-BE-NEXT:    ori 4, 4, 3855
-; P9-BE-NEXT:    rldimi 4, 4, 32, 0
-; P9-BE-NEXT:    stdx 4, 3, 5
 ; P9-BE-NEXT:    xxspltib 0, 15
+; P9-BE-NEXT:    stfd 0, 15(3)
 ; P9-BE-NEXT:    stxv 0, 0(3)
 ; P9-BE-NEXT:    blr
 ;
 ; P10-BE-LABEL: memsetTailV1B7:
 ; P10-BE:       # %bb.0: # %entry
-; P10-BE-NEXT:    pli 4, 252645135
-; P10-BE-NEXT:    rldimi 4, 4, 32, 0
-; P10-BE-NEXT:    pstd 4, 15(3), 0
 ; P10-BE-NEXT:    xxspltib 0, 15
+; P10-BE-NEXT:    mffprd 4, 0
 ; P10-BE-NEXT:    stxv 0, 0(3)
+; P10-BE-NEXT:    pstd 4, 15(3), 0
 ; P10-BE-NEXT:    blr
 ;
 ; P8-LE-LABEL: memsetTailV1B7:
 ; P8-LE:       # %bb.0: # %entry
-; P8-LE-NEXT:    lis 4, 3855
 ; P8-LE-NEXT:    vspltisb 2, 15
-; P8-LE-NEXT:    li 5, 15
-; P8-LE-NEXT:    ori 4, 4, 3855
-; P8-LE-NEXT:    rldimi 4, 4, 32, 0
-; P8-LE-NEXT:    stdx 4, 3, 5
-; P8-LE-NEXT:    stxvd2x 34, 0, 3
+; P8-LE-NEXT:    li 4, 15
+; P8-LE-NEXT:    xxswapd 0, 34
+; P8-LE-NEXT:    stxsdx 34, 3, 4
+; P8-LE-NEXT:    stxvd2x 0, 0, 3
 ; P8-LE-NEXT:    blr
 ;
 ; P9-LE-LABEL: memsetTailV1B7:
 ; P9-LE:       # %bb.0: # %entry
-; P9-LE-NEXT:    lis 4, 3855
-; P9-LE-NEXT:    li 5, 15
-; P9-LE-NEXT:    ori 4, 4, 3855
-; P9-LE-NEXT:    rldimi 4, 4, 32, 0
-; P9-LE-NEXT:    stdx 4, 3, 5
 ; P9-LE-NEXT:    xxspltib 0, 15
+; P9-LE-NEXT:    stfd 0, 15(3)
 ; P9-LE-NEXT:    stxv 0, 0(3)
 ; P9-LE-NEXT:    blr
 ;
 ; P10-LE-LABEL: memsetTailV1B7:
 ; P10-LE:       # %bb.0: # %entry
-; P10-LE-NEXT:    pli 4, 252645135
-; P10-LE-NEXT:    rldimi 4, 4, 32, 0
-; P10-LE-NEXT:    pstd 4, 15(3), 0
 ; P10-LE-NEXT:    xxspltib 0, 15
+; P10-LE-NEXT:    mffprd 4, 0
 ; P10-LE-NEXT:    stxv 0, 0(3)
+; P10-LE-NEXT:    pstd 4, 15(3), 0
 ; P10-LE-NEXT:    blr
 entry:
   tail call void @llvm.memset.p0.i64(ptr %p, i8 15, i64 23, i1 false)
   ret void
 }
 
 define dso_local void @memsetTailV1B4(ptr nocapture noundef writeonly %p) local_unnamed_addr {
 ; P8-BE-LABEL: memsetTailV1B4:
 ; P8-BE:       # %bb.0: # %entry
 ; P8-BE-NEXT:    vspltisb 2, 15
-; P8-BE-NEXT:    lis 4, 3855
-; P8-BE-NEXT:    ori 4, 4, 3855
-; P8-BE-NEXT:    stw 4, 16(3)
+; P8-BE-NEXT:    li 4, 16
+; P8-BE-NEXT:    stxsiwx 34, 3, 4
 ; P8-BE-NEXT:    stxvw4x 34, 0, 3
 ; P8-BE-NEXT:    blr
 ;
 ; P9-BE-LABEL: memsetTailV1B4:
 ; P9-BE:       # %bb.0: # %entry
-; P9-BE-NEXT:    lis 4, 3855
-; P9-BE-NEXT:    ori 4, 4, 3855
-; P9-BE-NEXT:    stw 4, 16(3)
 ; P9-BE-NEXT:    xxspltib 0, 15
+; P9-BE-NEXT:    li 4, 16
+; P9-BE-NEXT:    stfiwx 0, 3, 4
 ; P9-BE-NEXT:    stxv 0, 0(3)
 ; P9-BE-NEXT:    blr
 ;
 ; P10-BE-LABEL: memsetTailV1B4:
 ; P10-BE:       # %bb.0: # %entry
-; P10-BE-NEXT:    pli 4, 252645135
-; P10-BE-NEXT:    stw 4, 16(3)
 ; P10-BE-NEXT:    xxspltib 0, 15
+; P10-BE-NEXT:    li 4, 16
+; P10-BE-NEXT:    stfiwx 0, 3, 4
 ; P10-BE-NEXT:    stxv 0, 0(3)
 ; P10-BE-NEXT:    blr
 ;
 ; P8-LE-LABEL: memsetTailV1B4:
 ; P8-LE:       # %bb.0: # %entry
 ; P8-LE-NEXT:    vspltisb 2, 15
-; P8-LE-NEXT:    lis 4, 3855
-; P8-LE-NEXT:    ori 4, 4, 3855
-; P8-LE-NEXT:    stw 4, 16(3)
-; P8-LE-NEXT:    stxvd2x 34, 0, 3
+; P8-LE-NEXT:    li 4, 16
+; P8-LE-NEXT:    xxswapd 0, 34
+; P8-LE-NEXT:    stxsiwx 34, 3, 4
+; P8-LE-NEXT:    stxvd2x 0, 0, 3
 ; P8-LE-NEXT:    blr
 ;
 ; P9-LE-LABEL: memsetTailV1B4:
 ; P9-LE:       # %bb.0: # %entry
-; P9-LE-NEXT:    lis 4, 3855
-; P9-LE-NEXT:    ori 4, 4, 3855
-; P9-LE-NEXT:    stw 4, 16(3)
 ; P9-LE-NEXT:    xxspltib 0, 15
+; P9-LE-NEXT:    li 4, 16
+; P9-LE-NEXT:    stfiwx 0, 3, 4
 ; P9-LE-NEXT:    stxv 0, 0(3)
 ; P9-LE-NEXT:    blr
 ;
 ; P10-LE-LABEL: memsetTailV1B4:
 ; P10-LE:       # %bb.0: # %entry
-; P10-LE-NEXT:    pli 4, 252645135
-; P10-LE-NEXT:    stw 4, 16(3)
 ; P10-LE-NEXT:    xxspltib 0, 15
+; P10-LE-NEXT:    li 4, 16
+; P10-LE-NEXT:    stfiwx 0, 3, 4
 ; P10-LE-NEXT:    stxv 0, 0(3)
 ; P10-LE-NEXT:    blr
 entry:
   tail call void @llvm.memset.p0.i32(ptr %p, i8 15, i32 20, i1 false)
   ret void
 }
 
 define dso_local void @memsetTailV1B3(ptr nocapture noundef writeonly %p) local_unnamed_addr {
 ; P8-BE-LABEL: memsetTailV1B3:
 ; P8-BE:       # %bb.0: # %entry
 ; P8-BE-NEXT:    vspltisb 2, 15
-; P8-BE-NEXT:    lis 4, 3855
-; P8-BE-NEXT:    ori 4, 4, 3855
+; P8-BE-NEXT:    li 4, 15
+; P8-BE-NEXT:    stxsiwx 34, 3, 4
 ; P8-BE-NEXT:    stxvw4x 34, 0, 3
-; P8-BE-NEXT:    stw 4, 15(3)
 ; P8-BE-NEXT:    blr
 ;
 ; P9-BE-LABEL: memsetTailV1B3:
 ; P9-BE:       # %bb.0: # %entry
-; P9-BE-NEXT:    lis 4, 3855
-; P9-BE-NEXT:    ori 4, 4, 3855
-; P9-BE-NEXT:    stw 4, 15(3)
 ; P9-BE-NEXT:    xxspltib 0, 15
+; P9-BE-NEXT:    li 4, 15
+; P9-BE-NEXT:    stfiwx 0, 3, 4
 ; P9-BE-NEXT:    stxv 0, 0(3)
 ; P9-BE-NEXT:    blr
 ;
 ; P10-BE-LABEL: memsetTailV1B3:
 ; P10-BE:       # %bb.0: # %entry
-; P10-BE-NEXT:    pli 4, 252645135
-; P10-BE-NEXT:    stw 4, 15(3)
 ; P10-BE-NEXT:    xxspltib 0, 15
+; P10-BE-NEXT:    li 4, 15
+; P10-BE-NEXT:    stfiwx 0, 3, 4
 ; P10-BE-NEXT:    stxv 0, 0(3)
 ; P10-BE-NEXT:    blr
 ;
 ; P8-LE-LABEL: memsetTailV1B3:
 ; P8-LE:       # %bb.0: # %entry
 ; P8-LE-NEXT:    vspltisb 2, 15
-; P8-LE-NEXT:    lis 4, 3855
-; P8-LE-NEXT:    ori 4, 4, 3855
-; P8-LE-NEXT:    stw 4, 15(3)
-; P8-LE-NEXT:    stxvd2x 34, 0, 3
+; P8-LE-NEXT:    li 4, 15
+; P8-LE-NEXT:    xxswapd 0, 34
+; P8-LE-NEXT:    stxsiwx 34, 3, 4
+; P8-LE-NEXT:    stxvd2x 0, 0, 3
 ; P8-LE-NEXT:    blr
 ;
 ; P9-LE-LABEL: memsetTailV1B3:
 ; P9-LE:       # %bb.0: # %entry
-; P9-LE-NEXT:    lis 4, 3855
-; P9-LE-NEXT:    ori 4, 4, 3855
-; P9-LE-NEXT:    stw 4, 15(3)
 ; P9-LE-NEXT:    xxspltib 0, 15
+; P9-LE-NEXT:    li 4, 15
+; P9-LE-NEXT:    stfiwx 0, 3, 4
 ; P9-LE-NEXT:    stxv 0, 0(3)
 ; P9-LE-NEXT:    blr
 ;
 ; P10-LE-LABEL: memsetTailV1B3:
 ; P10-LE:       # %bb.0: # %entry
-; P10-LE-NEXT:    pli 4, 252645135
-; P10-LE-NEXT:    stw 4, 15(3)
 ; P10-LE-NEXT:    xxspltib 0, 15
+; P10-LE-NEXT:    li 4, 15
+; P10-LE-NEXT:    stfiwx 0, 3, 4
 ; P10-LE-NEXT:    stxv 0, 0(3)
 ; P10-LE-NEXT:    blr
 entry:
   tail call void @llvm.memset.p0.i64(ptr %p, i8 15, i64 19, i1 false)
   ret void
 }
 
 define dso_local void @memsetTailV1B2(ptr nocapture noundef writeonly %p) local_unnamed_addr {

 ; P9-LE-NEXT:    li 4, -1
 ; P9-LE-NEXT:    xxleqv 0, 0, 0
 ; P9-LE-NEXT:    stb 4, 16(3)
 ; P9-LE-NEXT:    stxv 0, 0(3)
 ; P9-LE-NEXT:    blr
 ;
 ; P10-LE-LABEL: memsetTailV1B1:
 ; P10-LE:       # %bb.0: # %entry
 ; P10-LE-NEXT:    li 4, -1
 ; P10-LE-NEXT:    xxleqv 0, 0, 0
 ; P10-LE-NEXT:    stb 4, 16(3)
 ; P10-LE-NEXT:    stxv 0, 0(3)
 ; P10-LE-NEXT:    blr
 entry:
   tail call void @llvm.memset.p0.i64(ptr %p, i8 -1, i64 17, i1 false)
   ret void
 }

llvm/test/CodeGen/PowerPC/p10-fi-elim.ll

 define dso_local signext i32 @test_FI_elim([40 x i8]* noalias nocapture dereferenceable(40) %arg, [0 x %96]* noalias nocapture nonnull readonly %arg2, [0 x %97]* noalias nocapture nonnull readonly %arg3, [0 x %98]* noalias nocapture nonnull readonly %arg4, %100* noalias nocapture dereferenceable(48) %arg6, %101* noalias nocapture dereferenceable(72) %arg7) local_unnamed_addr #2 {
 ; CHECK-LABEL: test_FI_elim:
 ; CHECK:       # %bb.0: # %bb
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stdu r1, -80(r1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-NEXT:    .cfi_offset lr, 16
-; CHECK-NEXT:    lxv v2, 0(r3)
 ; CHECK-NEXT:    mr r9, r6
 ; CHECK-NEXT:    mr r6, r5
-; CHECK-NEXT:    li r0, 4
-; CHECK-NEXT:    li r11, 3
-; CHECK-NEXT:    std r0, 0(r3)
-; CHECK-NEXT:    stb r11, 0(0)
-; CHECK-NEXT:    li r12, -127
-; CHECK-NEXT:    stb r12, 0(r3)
-; CHECK-NEXT:    li r2, 1
-; CHECK-NEXT:    stb r11, 0(r3)
-; CHECK-NEXT:    stb r12, 0(r3)
-; CHECK-NEXT:    stw r2, 0(r3)
-; CHECK-NEXT:    mfvsrd r5, v2
-; CHECK-NEXT:    vaddudm v3, v2, v2
-; CHECK-NEXT:    pstxv v2, 64(r1), 0
-; CHECK-NEXT:    neg r5, r5
-; CHECK-NEXT:    mfvsrd r10, v3
-; CHECK-NEXT:    std r5, 0(r3)
+; CHECK-NEXT:    li r5, 3
+; CHECK-NEXT:    li r10, -127
+; CHECK-NEXT:    lxv v2, 0(r3)
+; CHECK-NEXT:    stb r5, 0(0)
+; CHECK-NEXT:    stb r10, 0(r3)
+; CHECK-NEXT:    stb r5, 0(r3)
 ; CHECK-NEXT:    lbz r5, 2(r7)
 ; CHECK-NEXT:    mr r7, r9
-; CHECK-NEXT:    neg r10, r10
-; CHECK-NEXT:    std r2, 0(r3)
-; CHECK-NEXT:    std r0, 0(r3)
-; CHECK-NEXT:    std r10, 0(r3)
+; CHECK-NEXT:    li r12, 1
+; CHECK-NEXT:    stb r10, 0(r3)
+; CHECK-NEXT:    stw r12, 0(r3)
+; CHECK-NEXT:    li r11, 4
+; CHECK-NEXT:    std r11, 0(r3)
+; CHECK-NEXT:    vaddudm v4, v2, v2
+; CHECK-NEXT:    vnegd v3, v2
+; CHECK-NEXT:    pstxv v2, 64(r1), 0
 ; CHECK-NEXT:    rlwinm r5, r5, 0, 27, 27
+; CHECK-NEXT:    vnegd v2, v4
+; CHECK-NEXT:    stxsd v3, 0(r3)
+; CHECK-NEXT:    std r12, 0(r3)
+; CHECK-NEXT:    std r11, 0(r3)
 ; CHECK-NEXT:    stb r5, 0(0)
 ; CHECK-NEXT:    lbz r5, 2(r8)
+; CHECK-NEXT:    stxsd v2, 0(r3)
 ; CHECK-NEXT:    rlwinm r5, r5, 0, 27, 27
 ; CHECK-NEXT:    stb r5, 0(r3)
 ; CHECK-NEXT:    li r5, 2
 ; CHECK-NEXT:    stw r5, 0(r3)
 ; CHECK-NEXT:    mr r5, r4
 ; CHECK-NEXT:    bl foo@notoc
 ; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    addi r1, r1, 80