In D125203#3502433, @nemanjai wrote:

Why not also fix this in the front end so that we allow the builtin on the A2 CPU as well (since it's supported)?

Update according to Nemanja's comment: add A2 to frontend isa-v206-instructions feature list, together with test case update.

Update the three test cases introduced in this patch to use opaque-pointer
clang/test/CodeGen/PowerPC/aix-init-ref-null.cpp
clang/test/CodeGen/PowerPC/aix-ref-static-var.cpp
clang/test/CodeGen/PowerPC/aix-ref-tls_init.cpp

Use opaque-pointer in testcase aix-xcoff-ref.ll

During test some case revealed another issue regarding BSSLocal: there maybe some function associated with variable which has storage class BSSLocal (zero initialized). Unfortunately the variable is the association target, and there is no associated metadata attached to the variable. I have to work out a solution for this, incorporating Zheng's comments here. I will update code once the solution is formed.

Add assert to guard MCSection

Update based on Chen Zheng's comments:
(1) Corrected emitXCOFFRefDirective argument, the original one should be fine.
(2) Add assert check to guard against BS and UC mapping class.
(3) Updated code comment and code style.

Update based on comments:
(1) Reuse diag error message.
(2) Update clang test case for those diag messages.
(3) Add TODO comment.

Not required

Update based on Chaofan's suggestions.

Update test case to show that we need D122462 to fix the crash.

Option -mlong-double-128 is not supported on AIX currently, and clang fails due to type mismatch in the fe case. Add check logic to print diag message in this case.

Since this is compatibility support, I'm trying to match the result from XLC in scenarios where there is all kinds of QNaN, SNaN, +/-Infinity, +/-ZERO. Currently maxfl and maxfs still give different result compared with XLC in above scenario. This is one thing I'm still looking into.

In D122462#3407313, @lkail wrote:

Please also add tests.

No perf gain according to some spec test.

In D118316#3300414, @nemanjai wrote:

I am wondering if you have done any performance comparison or even just latency/throughput "back-of-the-envelope" computation for this. It doesn't seem obvious to me that this is better than a CP load. The conversion is a fairly expensive instruction. Another less compelling thing to consider is that in high register pressure situations (for VMX registers), the VSPLTISW may cause a spill.

One thing to note is that this necessarily replaces the cracked lfs instruction which is also expensive, so this transformation may be worthwhile. However, I wonder how this transformation would compare to stopping the conversion from double precision to single precision for constants on Power9 (i.e. return false from ShouldShrinkFPConstant() on Power9). This would of course grow the constant pool in situations where a lot of compact constants are loaded, but presumably this is a somewhat rare situation.

In D118316#3300414, @nemanjai wrote:

I am wondering if you have done any performance comparison or even just latency/throughput "back-of-the-envelope" computation for this. It doesn't seem obvious to me that this is better than a CP load. The conversion is a fairly expensive instruction. Another less compelling thing to consider is that in high register pressure situations (for VMX registers), the VSPLTISW may cause a spill.

One thing to note is that this necessarily replaces the cracked lfs instruction which is also expensive, so this transformation may be worthwhile. However, I wonder how this transformation would compare to stopping the conversion from double precision to single precision for constants on Power9 (i.e. return false from ShouldShrinkFPConstant() on Power9). This would of course grow the constant pool in situations where a lot of compact constants are loaded, but presumably this is a somewhat rare situation.

Used clang-format to tidy the code style

Move the two instructions XS[MAX|MIN]CQP under predicate [IsISA3_1, HasVSX]

(1) Add llvm.maxnum/minnum.f128 check case for P10
(2) Update test case using the script: update_llc_test_checks.py

Renamed PPCISD::XS[MAX|MIN]CDP to PPCISD::XS[MAX|MIN]C, and use the nodes for both dual-precision and quad-precision type-c instructions