Updates:
(1) Do not combine when store node generates additional value(s).
(2) Add getCombineStoreAndExtractIdx() to directly query the index, and do not need to loop through all elements.
(3) If the constant value to be stored is referenced by node other than current Store and the vector node, do not combine.
(4) Do not combine if the constant value is -1U.
(5) Add check to make sure the to-be-extracted vector type is legal.

Saw error in bootstrap.

Some test case to sanity check constants are stored as expected:

As verifier change and baseline test cases have been moved into https://reviews.llvm.org/D145767, update this patch.

Add empty case in Verifier/associated-metadata-aix-xcoff.ll

Address comments:
(1) Duplicated associated test cases to make copies for AIX XCOFF, and added multiple operands and null operand as legal cases.
(2) Updated verifier logic to check for AIX target.
(3) Moved XFAIL check to specific lines.

Address comments:
(1) Add test case to show how associated metadata will be used on AIX (currently not supported, marked with XFAIL).
(2) Add langref changes to explain.

I saw following case failed due to this commit with IPSCCPPass opt -passes="ipsccp"

In D122198#4185848, @stephenpeckham wrote:

I'm not familiar with a lot of this code, but I don't see any obvious errors.

Rebase.

Rebase and update patch
(1) Update verifier check on associated metadata to allow multiple operands for AIX.
(2) Update test cases to use opaque pointer.

Currently this patch does not work due to limit set on associated metadata operand count (forced to be single operand).

commit 87f2e9448e82bbed4ac59bb61bea03256aa5f4de
Author: Matt Arsenault <Matthew.Arsenault@amd.com>
Date:   Mon Jan 9 12:17:38 2023 -0500

In D138883#4181453, @nemanjai wrote:

Sorry, I had unsubmitted comments. Not sure if they still apply.

Attempt to push the logic into DAGCombiner::mergeConsecutiveStores()...

Update StoreSizeInBits check to skip on PowerOf2 bit size less than 8.

(1) Update element type ElemTy which now matches the type expected by both STFIWX and STXSIX PPCISD nodes.
(2) Add missing match pattern for PPCstxsix.

(1) Format code to following coding style guidance.
(2) Fix SplatValue check.
(3) Remaining redundant instructions like mtfprd will be fixed in separate patches.

Plan to continue improve the patch...

Update according to comments:
(1) Removed IsByValArg check which is redundant.
(2) Removed one test case scenario which is redundant.

Continue NIT: maybe remove the first else makes more sense...

Address comment and removed the second else.

Address comments.

Redo the implementation, and now both memset and constant splat array initialization get changed.

Add one more case.

I will try to get similar results by DAG combine. Thanks to Nemanja and Kai's insight!

In D139691#4102735, @nemanjai wrote:

Why do we need this?

1. For LE, why doesn't the swap removal pass remove the swaps rather than relying on this peephole?
2. For AIX, why do we have swaps? We certainly don't swap values we store by default on big endian, so the description of this doesn't explain it at all.

Rebase && Gentle ping.

Gentle ping.

In D140369#4038843, @shchenz wrote:

hmm, another issue cause by inconsistent logic for the tail call check between the IR coro-split pass and the instruction selection pass. Should we make them be consistent to avoid more issues?
For example, can we refactor IsEligibleForTailCallOptimization_64SVR4 and IsEligibleForTailCallOptimization() and call them in the TTI function supportsTailCallFor? I see there is a SelectionDAG &DAG parameter for these two functions, but the DAG is used to get the Caller Function, I think it should be easy to change the SelectionDAG to a Function parameter?

And for mayBeEmittedAsTailCall(), maybe we should also add another patch to extend it for non 64BitELFABI targets?

(1) Use new API to do the check.
(2) Remove assert requirement.
(3) Fixed test case: CHECK-PCREL should not be tailcall.

As suggested by Zheng, I'm looking for a solution that reuse existing functions in PPCISelLowering.

Gentle ping.

Plan to enable 256bit vector ld/st codegen, and then add the motivation case.

Refresh and Ping.

Update patch as following test case pattern changed:
llvm/test/CodeGen/ARM/memset-align.ll

Gentle ping.

Address comment.

In D138883#3955904, @nemanjai wrote:

I think this is useful, but we should ensure we can get rid of the swap that this introduces (in a separate patch).

Test case update.

Add memset2TailV1Bx() cases which does not fit in vspltisb and may require constant pool.

In D138883#3962255, @lkail wrote:

I would expect not only memset, some consecutive stores could also reuse the result of vector split, see https://godbolt.org/z/77aMvncb4.
For

void foo(long a[3]) {
    a[0] = 12;
    a[1] = 12;
    a[2] = 12;
}

foo(long*):                               # @foo(long*)
        .quad   .Lfunc_begin0
        .quad   .TOC.@tocbase
        .quad   0
.Lfunc_begin0:
        xxlxor 0, 0, 0
        li 4, 12
        xxsplti32dx 0, 1, 12
        std 4, 16(3)
        stxv 0, 0(3)
        blr
        .long   0
        .quad   0

We don't reuse the result of xxsplti32dx.

Add memset-tail.ll changes.

Changes in this update:
(1) I was trying to use TTI.getVectorInstrCost() to query instruction cost in PPCTargetLowering::canCombineStoreAndExtract(). However not able to reach TTI, and didn't find any reference to do that in SDAG. Given that the original implementation of canCombineStoreAndExtract() on ARM implemented its own logic to calculate Cost, followed the approach and implemented logic by referring to PPCTTIImpl::getVectorInstrCost().

Realized I need to use PPCTTIImpl::getVectorInstrCost() API to determine the cost of instructions. I'm working on it now.

Update according to comments:
(1) Use existing canCombineStoreAndExtract() instead of creating new.
(2) Nest the else statement properly.
(3) Saw two cases changed due to (1).

Add more test cases according to comment.