[PowerPC] add a peephole to remove redundant swap instructions created by expandVSXStoreForLE

[tingwang]

Summary

The scenario is vector store of splat value on Power8 LE. It is not expected that we see swap instruction before the store.

Vector store on P8 little endian created by expandVSXStoreForLE() will have swap instruction added before the store in PPCISelLowring. If the vector is generated by splat, the swap instruction can be eliminated.

Ideally those swaps should have been removed by ppc-vsx-swaps pass. However due to its limitation, that removal did not happen. This patch does the removal in peephole.

[shchenz]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

644

Can this branch be merged to the above one at line 627? Splat a double word and the double word is a splat of a small unit should also can be removed?

[tingwang]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

644

Sure, I can do the merge to reuse logic.

Are you referring to instructions like xxspltib? I think those are introduced in v3.0, and they will not appear on P8, so I did not include those.

[shchenz]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

644

Oh, I meant the XXPERMDI instruction can be removed like the above branch(at like 627) does. Not referring to any other instructions.

[tingwang]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

644

IMHO, we saw these additional swaps on P8 because of stores, and that's why only saw Immed == 2. I'm not sure of any origin that can produce splat (i.e. Immed == 0 || Immed == 3 like 627) and reach peephole. If there is any such origin, it maybe more interesting to fix in the origin. To me, it is a little bit confused why need to handle splat here?

[shchenz]

LGTM. Maybe wait for some days for other reviews.

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

644

OK, I see. I did some hacks and seems indeed XXPERMDI (as a splat) is never be fed by another splat. So let's keep as it is. And continuously improve this when a case is found.

[nemanjai]

Why do we need this?

1. For LE, why doesn't the swap removal pass remove the swaps rather than relying on this peephole?
2. For AIX, why do we have swaps? We certainly don't swap values we store by default on big endian, so the description of this doesn't explain it at all.

[tingwang]

In D139691#4102735, @nemanjai wrote:

Why do we need this?

1. For LE, why doesn't the swap removal pass remove the swaps rather than relying on this peephole?
2. For AIX, why do we have swaps? We certainly don't swap values we store by default on big endian, so the description of this doesn't explain it at all.

Hi Nemanja,

This scenario indirectly originated from D138883. These additional swaps observed on LE were not removed by ppc-vsx-swaps pass due to its limitations. Since the instruction combination is clear and simple, I weighted peephole a more reliable approach to remove these swaps than ppc-vsx-swaps pass. (IMHO, it cost more to fix in ppc-vsx-swaps pass, not even mention that ppc-vsx-swaps pass sometimes backfires and creates more swaps. I'm a little bit worried that enabling more patterns in ppc-vsx-swaps pass may cause it backfire at me...)

This was intended for LE, and all pattern changes here are related to LE. Sorry I should have high lighted this point, and will provider more information in the description.

By the way, thank you for providing help on D138883. As you suggested, I realized canCombineStoreAndExtract() could be used for the purpose, and did extend the API. Not sure if that serves the purpose well or not?

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

for (MachineInstr &MI : MBB) {
                 .add(MI.getOperand(1));
             break;
           }
           // Splat fed by another splat - switch the output of the first
           // and remove the second.
           DefMI->getOperand(0).setReg(MI.getOperand(0).getReg());
           LLVM_DEBUG(dbgs() << "Removing redundant splat: ");
           LLVM_DEBUG(MI.dump());
+        } else if (Immed == 2 &&
+                   (DefOpc == PPC::VSPLTB || DefOpc == PPC::VSPLTH ||
+                    DefOpc == PPC::VSPLTW || DefOpc == PPC::XXSPLTW)) {
+          // Swap of various vector splats, convert to copy.
+          ToErase = &MI;
+          Simplified = true;
+          LLVM_DEBUG(dbgs() << "Optimizing swap(vsplt[b|h|w]|xxspltw) => "
+                               "copy(vsplt[b|h|w]|xxspltw): ");
+          LLVM_DEBUG(MI.dump());
+          BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
+                  MI.getOperand(0).getReg())
+              .add(MI.getOperand(1));
         }
         break;
       }
       case PPC::VSPLTB:
       case PPC::VSPLTH:
       case PPC::XXSPLTW: {
         unsigned MyOpcode = MI.getOpcode();
         unsigned OpNo = MyOpcode == PPC::XXSPLTW ? 1 : 2;

llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll

 ; RUN: llc < %s -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
 ; RUN:   | FileCheck %s --check-prefix=CHECK-P8
 ; RUN: llc < %s -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
 ; RUN:   | FileCheck %s --check-prefix=CHECK-P9
 
 @a = external local_unnamed_addr global <4 x i32>, align 16
 @pb = external local_unnamed_addr global ptr, align 8
 
 define void @testExpandPostRAPseudo(ptr nocapture readonly %ptr) {
 ; CHECK-P8-LABEL: testExpandPostRAPseudo:
 ; CHECK-P8:  # %bb.0: # %entry
 ; CHECK-P8:    lfiwzx f0, 0, r3
 ; CHECK-P8:    ld r4, .LC0@toc@l(r4)
 ; CHECK-P8:    xxspltw vs0, vs0, 1
-; CHECK-P8:    xxswapd vs0, vs0
 ; CHECK-P8;    stxvd2x vs0, 0, r4
 ; CHECK-P8:    lis r4, 1024
 ; CHECK-P8:    lfiwax f0, 0, r3
 ; CHECK-P8:    addis r3, r2, .LC1@toc@ha
 ; CHECK-P8:    ld r3, .LC1@toc@l(r3)
 ; CHECK-P8:    xscvsxdsp f0, f0
 ; CHECK-P8:    ld r3, 0(r3)
 ; CHECK-P8:    stfsx f0, r3, r4

llvm/test/CodeGen/PowerPC/aix-vsx-splatimm.ll

 ; CHECK-NEXT:    lwz 5, 0(3)
 ; CHECK-NEXT:    slwi 3, 3, 8
 ; CHECK-NEXT:    neg 3, 3
 ; CHECK-NEXT:    srwi 5, 5, 1
 ; CHECK-NEXT:    mtvsrd 34, 3
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    mullw 4, 4, 5
 ; CHECK-NEXT:    vsplth 2, 2, 3
-; CHECK-NEXT:    xxswapd 0, 34
+; CHECK-NEXT:    stxvd2x 34, 0, 3
 ; CHECK-NEXT:    neg 4, 4
 ; CHECK-NEXT:    mtvsrd 35, 4
-; CHECK-NEXT:    stxvd2x 0, 0, 3
 ; CHECK-NEXT:    vsplth 3, 3, 3
-; CHECK-NEXT:    xxswapd 1, 35
-; CHECK-NEXT:    stxvd2x 1, 0, 3
+; CHECK-NEXT:    stxvd2x 35, 0, 3
 bb:
   br i1 undef, label %bb22, label %bb3
 
 bb3:                                              ; preds = %bb
   %i = insertelement <8 x i16> undef, i16 0, i32 0
   %i4 = trunc i32 %arg to i16
   %i5 = mul i16 %i4, -256
   %i6 = insertelement <8 x i16> %i, i16 %i5, i32 1

llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll

 ; CHECK-NOVSX-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: testByteSplat:
 ; CHECK-P7:       # %bb.0: # %entry
 ; CHECK-P7-NEXT:    lvsr v2, 0, r3
 ; CHECK-P7-NEXT:    lvx v3, 0, r3
 ; CHECK-P7-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P7-NEXT:    vspltb v2, v2, 15
-; CHECK-P7-NEXT:    xxswapd vs0, v2
-; CHECK-P7-NEXT:    stxvd2x vs0, 0, r3
+; CHECK-P7-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-P7-NEXT:    blr
 ;
 ; P8-AIX-LABEL: testByteSplat:
 ; P8-AIX:       # %bb.0: # %entry
 ; P8-AIX-NEXT:    lbzx r3, 0, r3
 ; P8-AIX-NEXT:    mtvsrwz v2, r3
 ; P8-AIX-NEXT:    vspltb v2, v2, 7
 ; P8-AIX-NEXT:    stxvw4x v2, 0, r3

llvm/test/CodeGen/PowerPC/load-and-splat.ll

 ; P9-NEXT:    stxv vs0, 0(r3)
 ; P9-NEXT:    blr
 ;
 ; P8-LABEL: test2:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    addi r4, r4, 12
 ; P8-NEXT:    lfiwzx f0, 0, r4
 ; P8-NEXT:    xxspltw vs0, vs0, 1
-; P8-NEXT:    xxswapd vs0, vs0
 ; P8-NEXT:    stxvd2x vs0, 0, r3
 ; P8-NEXT:    blr
 ;
 ; P7-LABEL: test2:
 ; P7:       # %bb.0: # %entry
 ; P7-NEXT:    addi r4, r4, 12
 ; P7-NEXT:    lfiwzx f0, 0, r4
 ; P7-NEXT:    xxspltw vs0, vs0, 1

 ; P9-NEXT:    stxv vs0, 0(r3)
 ; P9-NEXT:    blr
 ;
 ; P8-LABEL: test3:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    addi r4, r4, 12
 ; P8-NEXT:    lfiwzx f0, 0, r4
 ; P8-NEXT:    xxspltw vs0, vs0, 1
-; P8-NEXT:    xxswapd vs0, vs0
 ; P8-NEXT:    stxvd2x vs0, 0, r3
 ; P8-NEXT:    blr
 ;
 ; P7-LABEL: test3:
 ; P7:       # %bb.0: # %entry
 ; P7-NEXT:    addi r4, r4, 12
 ; P7-NEXT:    lfiwzx f0, 0, r4
 ; P7-NEXT:    xxspltw vs0, vs0, 1