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[RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.
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Authored by craig.topper on Nov 25 2022, 7:50 PM.

Details

Summary

Similar to previous patches for ADDI/ADDIW/SLLI/ADD, but restricted
to only cases where the register is x8-x15(GPRC reg class).

I've restricted it so that we can be precise about whether the
resulting instruction would be compressible. Changing the register
allocation may make some other instruction not compressible so we
should try to be accurate.

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Event Timeline

craig.topper created this revision.Nov 25 2022, 7:50 PM
craig.topper requested review of this revision.Nov 25 2022, 7:50 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 25 2022, 7:50 PM

clang-format

asb accepted this revision.Nov 30 2022, 3:08 AM

LGTM.

This revision is now accepted and ready to land.Nov 30 2022, 3:08 AM