[lld][ELF] Support LoongArch

[xen0n]

Summary

This adds support for the LoongArch ELF psABI v2.00 [1] relocation
model to LLD. The deprecated stack-machine-based psABI v1 relocs are not
supported.

The code is tested by successfully bootstrapping a Gentoo/LoongArch
stage3, complete with common GNU userland tools and both the LLVM and
GNU toolchains (GNU toolchain is present only for building glibc,
LLVM+Clang+LLD are used for the rest). Large programs like QEMU are
tested to work as well.

[1]: https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html

[xen0n]

revert the broken TLS IE offset change

[xen0n]

lld/ELF/InputSection.cpp

654

I've located the TLS IE offset logic in the BFD code (IE symbol = offset by 2 GOT entries) and tried to do the same in LLD, but unfortunately the output was broken so I have to revert most of it. Sadly I won't have enough time to investigate before end of year.

[brad]

With the backend enabled, it would be good to work on this further.

[xen0n]

In D138135#4051965, @brad wrote:

With the backend enabled, it would be good to work on this further.

Hi, thanks for the comment! Indeed the target's been enabled by default for a few days now, and no I haven't abandoned the work. It's simply hard to find time to work on this, though.

At this point it's still the test cases that need more work. I've successfully bootstrapped a Gentoo stage3 with this code and a recent LLVM snapshot a while ago, so the code is indeed working, but of course mainlining requires more specific / cheaper tests than distro bootstrapping. I'm not entirely sure that can be done before the LLVM 16 branching, though, however I'll try.

[SixWeining]

According to https://llvm.org/docs/HowToReleaseLLVM.html#release-patch-rules there might be 10 days (before RC1) for us. Hope we can finish it.

lld/test/ELF/loongarch-branch-b16.s

4

Two dashes. :)

4

Ditto.

[xen0n]

Add a couple of tests, implement the R_LARCH_PCALA_LO12 on JIRL kludge

[SixWeining]

Maybe should mention LLD in the title?

[SixWeining]

I just verified the latest change, lld still fail to link llvm and report the error:

ld.lld: error: relocation R_LARCH_PCALA_HI20 cannot be used against symbol '__cxa_atexit'; recompile with -fPIC                                                                              
>>> defined in /usr/lib64/libc.so.6
>>> referenced by atexit.c:46 (../stdlib/atexit.c:46)
>>>               atexit.oS:(atexit) in archive /usr/lib64/libc_nonshared.a
clang-16: error: linker command failed with exit code 1 (use -v to see invocation)
ninja: build stopped: subcommand failed.

[xen0n]

In D138135#4071143, @SixWeining wrote:

I just verified the latest change, lld still fail to link llvm and report the error:

ld.lld: error: relocation R_LARCH_PCALA_HI20 cannot be used against symbol '__cxa_atexit'; recompile with -fPIC                                                                              
>>> defined in /usr/lib64/libc.so.6
>>> referenced by atexit.c:46 (../stdlib/atexit.c:46)
>>>               atexit.oS:(atexit) in archive /usr/lib64/libc_nonshared.a
clang-16: error: linker command failed with exit code 1 (use -v to see invocation)
ninja: build stopped: subcommand failed.

Hmm, let me check after some sleep... I probably should write more tests but unfortunately time's not enough. I'll try to push a new revision tomorrow morning.

[xen0n]

fix PCALA_HI20 behavior in case of PCALA_LO12 on JIRL, and cleanups

[xen0n]

amend comments

[xen0n]

fix a switch arm and tweak comments

[xry111]

FWIW, BFD linker handles R_LARCH_PCALA_HI20 by creating a PLT for every R_LARCH_PCALA_HI20 against an undefined symbol. This can be really annoying if someone happens to make a simple typo in a symbol name (causing an runtime crash which is difficult to be diagnosed). And I guess using such an approach in LLD will annoy LLD maintainers.

We are out here to contribute, to make contact with the FLOSS project maintainers, to establish friendly relations but not to cause trouble, and absolutely not to annoy people. And now, look at what we are doing. ref.

[xen0n]

add test cases for PCALA relocs, fix getLoongArchPageOffset's adjustment to the higher half as uncovered by the tests

[SixWeining]

Verification result: llvm is successfully built/linked by clang/lld with this patch applied.

[MQ-mengqing]

lld/ELF/InputSection.cpp

654

Ping for not getting reply about here for a long time.

File: test.s

la.tls.ie $r4, y
la.tls.gd $r5, y

.section .tbss
.globl y
y:
.word   0
.size   y, 4

Pre-cmd:

$ llvm-mc -filetype=obj --triple=loongarch64 test.s -o test.o
$ ld.lld test.o -shared -o test.lld
$ ld test.o -shared -o test.ld

Compare1:

$ readelf -Wr test.{ld, lld}

test.ld:
0000000000008008  0000000300000007 R_LARCH_TLS_DTPMOD64   0000000000000000 y + 0
0000000000008010  0000000300000009 R_LARCH_TLS_DTPREL64   0000000000000000 y + 0
0000000000008018  000000030000000b R_LARCH_TLS_TPREL64    0000000000000000 y + 0

test.lld:
0000000000020398  0000000100000002 R_LARCH_64             0000000000000000 y + 0
00000000000203a0  0000000100000007 R_LARCH_TLS_DTPMOD64   0000000000000000 y + 0
00000000000203a8  0000000100000009 R_LARCH_TLS_DTPREL64   0000000000000000 y + 0
00000000000203b0  000000010000000b R_LARCH_TLS_TPREL64    0000000000000000 y + 0

Compare2:

$ objdump -d test.{ld, lld}

test.ld:
0000000000000250 <.text>:
 250:	1a000104 	pcalau12i   	$a0, 8(0x8)
 254:	28c06084 	ld.d        	$a0, $a0, 24(0x18)
 258:	1a000105 	pcalau12i   	$a1, 8(0x8)
 25c:	02c020a5 	addi.d      	$a1, $a1, 8(0x8)

test.lld:
00000000000102d0 <.text>:
   102d0:	1a000204 	pcalau12i   	$a0, 16(0x10)
   102d4:	28ce8084 	ld.d        	$a0, $a0, 928(0x3a0)
   102d8:	1a000205 	pcalau12i   	$a1, 16(0x10)
   102dc:	02ce80a5 	addi.d      	$a1, $a1, 928(0x3a0)

[xen0n]

In D138135#4117010, @MQ-mengqing wrote:

Sorry for the late reply, recently I've been too busy to resume work on this patch as much as I'd want to.

Last time I tried out your suggestion but the resulting output binary was invariably broken. I think I'd have to write some more tests to figure out whether the current behavior would be correct despite deviating from BFD behavior.

[xen0n]

rebase

[xen0n]

lld/ELF/InputSection.cpp

654

Actually I'm not sure if the behavior difference is mission-critical, as things fully work (or at least seems to) when I bootstrapped Gentoo with LLVM/Clang. Do you want me to take care of this before merging the whole thing?

[MQ-mengqing]

lld/ELF/InputSection.cpp

654

It not matters, it is hard to happen, maybe. It is a hidden danger
and developers should notice something may wrong if that occurs.
But, I also think it is not mission-critical. It can be documented and
fixed later.

[xen0n]

lld/ELF/InputSection.cpp

654

Okay, I'll soon add the test case but note the current behavioral difference so we can get to fix it later.

Sorry for not handling this as promptly as I'd like to; real life and other reasons kick in.

[xen0n]

• Rebased
• Fixed TLS GD/IE bug pointed out by @MQ-mengqing
• Minor cleanups and test additions (ported from RISCV)

[xen0n]

Use double dashes for llvm-mc invocations in test cases, and add a comment to the tls-gd-and-ie case documenting its edge-case-ness.

[MQ-mengqing]

lld/ELF/Arch/LoongArch.cpp

419

Since TLS_GD also uses GOT64_PC_{HI20, LO12}, it may have something mistake.

[xen0n]

more cleanups to the TLS logic

[xen0n]

lld/ELF/Arch/LoongArch.cpp

419

Thanks for pointing out that; seems I've heavily underestimated the amount of reuse happening! I've just unified about as much TLS logic as possible into the existing GOT case (although I don't have time to write the tests until late night).

[xen0n]

@MQ-mengqing: gentle ping; I believe all issues reported by you are now fixed. Please test if that's really the case. Thanks!

[MQ-mengqing]

I've tested the TLS-relative tests, this patch works well! Thanks for your works, patience and time!

[SixWeining]

This patch has been reviewed and tested for more than 6 months and all comments are well addressed. It looks good to me from the LoongArch side, so I will accept.
@MaskRay Could you help to review this patch once more? Thanks.

[MaskRay]

Thank you for the contribution. This is very well-written. I've put up some comments and will review some technical corners more carefully.

lld/ELF/Arch/LoongArch.cpp

32

It seems that our codebase is not consistent with 0x[a-f] and 0x[A-F], but [a-f] is more common and probably should be preferred for new code.

84

Delete this variable and adjust use sites.

228

This is untested. You can reuse loongarch-elf-flags.s

261

glibc rtld does not use this field. We can delete this override.

342

What are R_LARCH_MARK_LA and R_LARCH_MARK_PCREL? They are untested.

383

https://www.gnu.org/software/libc/ glibc 2.37 has been release. This sentence should be revised.

488

These cases are probably not useful.
Reporting unknown relocation for deprecated/essentially-unused relocation types should be fine.

lld/ELF/Driver.cpp

172

elf32loongarch is untested. Perhaps add RUN lines to emulation-loongarch.s. loongarch-elf-flags.s is possibly not needed.

lld/ELF/InputSection.cpp

692

Is The R_LARCH_GOT64_PC_* relocs are also reused for TLS GD. accurate? Is this just R_LOONGARCH_GOT_PAGE_PC?

694

R_LOONGARCH_GOT_TLSGD_PC does not exist.

lld/ELF/Relocations.cpp

1065

This can be simplified as else if (!sym.isTls() || config->emachine != EM_LOONGARCH)

lld/ELF/ScriptParser.cpp

442

Test this with OUTPUT_FORMAT linker script command.

lld/test/ELF/loongarch-branch-b16.s

11

The encoding is unneeded detail and may change if someone decides to remove spaces between hex pairs. Run llvm-objdump with --no-show-raw-insn

lld/test/ELF/loongarch-pc-aligned.s

16

Consider --section-start

lld/test/ELF/loongarch-pcala-lo12-jirl-shared-error.s

2

foo-error.s can usually be added into foo.s by leveraging split-file.

lld/test/ELF/loongarch-tls-gd-and-ie.s

2

What does loongarch-tls-gd-and-ie.s mean?

[MaskRay]

lld/test/ELF/loongarch-tls-gd.s

133

Avoid LLVM assembler-specific .tbss not recognized by GNU as.
.section .tbss,"awT",@nobits

[xen0n]

rebased and addressed most review comments

[xen0n]

lld/ELF/Arch/LoongArch.cpp

342

AFAIK they serve as markers for external consumers only: R_LARCH_MARK_LA is emitted by binutils for each la.abs, and used by (old) Linux and grub to perform their own relocation; R_LARCH_MARK_PCREL is unused so far. Are test cases still needed in this case?

lld/test/ELF/loongarch-pc-aligned.s

16

Strangely I get error: output file too large for some of the cases (like this one; but not with others). Can't see a reason for this...

lld/test/ELF/loongarch-tls-gd-and-ie.s

2

It's an edge case discovered by @MQ-mengqing and explained in a comment below. I've renamed the test case and moved the comment to top for better visibility.

[xen0n]

Don't check e_flags compatibility for input files that does not contain code.

[xen0n]

Add support for the new R_LARCH_64_PCREL reloc that's only added after LoongArch ELF psABI v2.00, but trivial to support and helpful to the ClangBuiltLinux effort.

[xen0n]

rebase

[MaskRay]

lld/ELF/Arch/LoongArch.cpp

23

This can be rephrase to mention what a page is first, then mention that behaviorally equivalent to the AArch64 adrp. Ideally understanding an arch doesn't require understanding another independent one.

29

" (The official ISA manual gives no such "full names".)" this probably should be dropped. The official ISA manual can improve and I don't hope that we push another commit to fix this.

30

It'd be better to define the helpers after class LoongArch.
The AArch64 style in this particular place is something we'd not do.

38

"The higher bits need ..." appears to describe result -= 0x100000000 but is not clear. An example will work better

156

write32le

195

delete braces

225

mention toString(ctx->objectFiles[0]) . See D134198

395

This link gives "This repository has been archived by the owner on Apr 20, 2023. It is now read-only.". Is it stale?

Is R_LARCH_JIRL_LO12 still planned?

438

It seems that https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html is wrong about GR[rd] = PC + SignExtend({si20, 12'b0}, GRLEN).

The low 12-bits of GR[rd] is zeroed.

452

https://github.com/loongson/LoongArch-Documentation/pull/69 is now a stale link as the repo is archived and may be deleted in the future.

lld/test/ELF/loongarch-pc-aligned.s

9

You can use something like --section-start .rodata=0x11000 --section-start=.text=0x11ffc to replace the linker script.

21

I hope that we can reduce the number of ld.lld invocations.

Does it help to increase the number of instructions in .text?

pcalau12i $a0, %pc_hi20(x)
pcalau12i $a0, %pc_hi20(x)
ld.w      $a0, $a0, %pc_lo12(x)
ld.w      $a0, $a0, %pc_lo12(x)

131

This is complex. This needs a comment to explain how these immediate mean.

170

You can define a macro to repeat the code sequence 3 times so that we don't need many extreme*.t

[MaskRay]

lld/ELF/Arch/LoongArch.cpp

361

This wording may sound irony for a public project. Also, the paragraph is too long.

We could just R_ABS, but the JIRL instruction reuses the relocation type for a different purpose.
This questionable use case is part of glibc 2.37 Scrt1.o (is it true?), which is linked into user programs, so we have to work around it for a while, even if a new relocation type may be introduced in the future.

I wonder why the medium code model designer decides to use pcalau12i+jirl. Range extension thunks are much better.

371

The long description about "* R_LARCH_PCALA_LO12 just places its computed value unmodified" can be simplified to just mention that the computation is different. How it is different is the job of the comment in relocate.

[MaskRay]

lld/ELF/Arch/LoongArch.cpp

407

These R_LARCH_ADD* and R_LARCH_SUB* are untested.

You can use .reloc ., R_LARCH_ADD8, sym to force generating a relocation in a test.

[xen0n]

Addressed all review comments:

• Moved the helpers around the class LoongArch definition
• Adjusted various comments
  • Toned down some rants
  • Replaced links to archived repo with archive.org snapshots or new refreshed links
  • Other fixes
• Renamed getLoongArchPageOffset -> getLoongArchPageDelta, fixed its hi32 adjustment logic and added test cases
• Improve diagnostics message for e_flags mismatch
• Added tests for R_LARCH_MARK_LA and R_LARCH_{ADD,SUB}{8,16,32,64}
• write32le the break insn
• Set defaultCommonPageSize to 16KiB

lld/ELF/Arch/LoongArch.cpp

38

Thanks, I've discovered even the BFD implementation is wrong for some of the edge cases. (This implementation needs a fix as well.) I've added an example and fixed the logic in the latest revision.

342

I've now added R_LARCH_MARK_LA's in the loongarch-abs64.s cases. I can't seem to find any usage of R_LARCH_MARK_PCREL in the wild, not even in the old world binaries, so I'm not sure if removing support for it (instead of treating as no-op per common sense) would be better.

361

I added the rant following R_386_GOT32 and R_386_GOT32X's precedent. I agree though that such wording would better belong somewhere else (e.g. in an issue raised in the ABI specs repo) and I'll use your suggested wording instead.

395

No, AFAIK the repo's information is still current and the repo isn't going away. They archived it for non-technical reasons (maybe not giving the impression that people outside of Loongson can change their official docs at will, before their CLA automation is ready).

I've nevertheless archived the page with archive.org and replaced with a new PR to the document's current home. I expect the discussion to continue but only after they get their CLA mechanism finished.

438

You may be looking at pcaddu12i? That's the same as RISCV auipc. The PCALA relocs all use pcalau12i that indeed has the lower bits zeroing behavior mentioned. See the corresponding documentation source.

452

The repo isn't going anywhere, as explained in another reply, but I've replaced with a new refreshed PR on the currently maintained LA ABI specs repo nevertheless (I've replicated all info there so no context is lost even if the original repo is deleted).

lld/test/ELF/loongarch-pc-aligned.s

9

You can use something like --section-start .rodata=0x11000 --section-start=.text=0x11ffc to replace the linker script.

Sorry, but as I've previously explained as soon as I replace the linker script with the --section-start arguments that really should be equivalent, I instead get errors like ld.lld: error: output file too large: 18446744073709494880 bytes. This doesn't happen with the BFD linker so I suspect something is wrong with the common logic, although I haven't debugged yet.

For now though I've discovered your suggestion somehow works (by ensuring the base address to be always greater than defaultMaxPageSize i.e. 0x10000), and I've amended the cases.

21

Probably no, I have to ensure sufficiently different PC and target values for each case, in order to be able to cover the edge cases. Adding a trivial number of instructions won't help (i.e. I can't put the target value 4GiB away without utilizing --section-start or linker scripts anyway).

Do you mean I should just leave the PC alone and use --defsym for testing multiple offsets at once?

131

I've (programmatically) generated more cases for complete coverage of getLoongArchPageDelta (previously getLoongArchPageOffset), complete with explanations for every immediate there.

170

The linker script inputs are all gone in the latest revision. Can't seem to reduce lld invocations though, happy to see any suggestion.

[MaskRay]

lld/ELF/Arch/LoongArch.cpp

112

This example doesn't trigger the interesting case signLo12 != signHi20. We need a different example.

126

excessively indented

220

Delete nullness check.

We probably should change the parameter to a const reference.

223

drop braces

lld/ELF/InputSection.cpp

656

Delete this comment. This is not fallthrough, which usually means [[fallthrough]].

lld/ELF/Relocations.h

110

... from other architectures.

lld/test/ELF/loongarch-branch-b16.s

23

For error messages, we check the error: prefix.

Fix this elsewhere.

24

Add -NEXT whenever applicable.

lld/test/ELF/loongarch-branch-b21.s

23

For error messages, we check the error: prefix.

lld/test/ELF/loongarch-branch-b26.s

2

I think it helps readability if loongarch-branch-b26.s is merged into loongarch-branch-b21.s.

28

For error messages, we check the error: prefix.

lld/test/ELF/loongarch-interlink.test

76 ↗

(On Diff #538576)

Indent instructions

lld/test/ELF/loongarch-plt.s

84

The column number of 20040: should not be less than the column number of the colon in DIS32-NEXT:.
We may need more indentation for instructions.

[xen0n]

Address all review comments.

[xen0n]

lld/ELF/Arch/LoongArch.cpp

112

Ah, I copied a wrong fixture from my experiments, sorry for that. I've made new examples to cover both directions of adjustment.

lld/test/ELF/loongarch-branch-b16.s

24

Okay. Here it's not applicable though, as the actual diagnostics have >>> defined in --defsym:1 and an empty line in between, which is irrelevant to our intended assertion.

[xen0n]

Friendly ping; ideally I'd like this port to get included in LLVM 17, which will vastly simplify things ecosystem-wide, such as ClangBuiltLinux testing, Gentoo LLVM stagebuilding, and possibly many more large projects depending on lld.

[MaskRay]

In D138135#4517087, @xen0n wrote:

Friendly ping; ideally I'd like this port to get included in LLVM 17, which will vastly simplify things ecosystem-wide, such as ClangBuiltLinux testing, Gentoo LLVM stagebuilding, and possibly many more large projects depending on lld.

This is on my radar and I will take a look again soon. There are also random other LoongArch things I need to take a look and I did. This is totally fine to be cherry picked into the release/17.x branch even after it is created.
I am sorry that I did not respond in time for the initial period of the patch (when it changed from the "WIP" state to the normal in-review state), but I think the request after 3 days may be a bit too quick.
Honestly the linker is probably I care about the most and I don't want to lower the bar. (There are other things that I am concerned with as well, but I may not have too much energy to prevent something less appropriate happen; but if I notice, I'll make a comment).

[xen0n]

In D138135#4517120, @MaskRay wrote:

In D138135#4517087, @xen0n wrote:

Friendly ping; ideally I'd like this port to get included in LLVM 17, which will vastly simplify things ecosystem-wide, such as ClangBuiltLinux testing, Gentoo LLVM stagebuilding, and possibly many more large projects depending on lld.

This is on my radar and I will take a look again soon. There are also random other LoongArch things I need to take a look and I did. This is totally fine to be cherry picked into the release/17.x branch even after it is created.
I am sorry that I did not respond in time for the initial period of the patch (when it changed from the "WIP" state to the normal in-review state), but I think the request after 3 days may be a bit too quick.
Honestly the linker is probably I care about the most and I don't want to lower the bar. (There are other things that I am concerned with as well, but I may not have too much energy to prevent something less appropriate happen; but if I notice, I'll make a comment).

Thanks for the clarification. I didn't know if the release branch cherry-pick could be done in this case so I was a little anxious, sorry for the less-than-a-week ping.

I fully understand your passion and care for the linker and I agree with not lowering the bar; I'll do my best to improve the code together.

[xry111]

In D138135#4517125, @xen0n wrote:

In D138135#4517120, @MaskRay wrote:

In D138135#4517087, @xen0n wrote:

Friendly ping; ideally I'd like this port to get included in LLVM 17, which will vastly simplify things ecosystem-wide, such as ClangBuiltLinux testing, Gentoo LLVM stagebuilding, and possibly many more large projects depending on lld.

This is on my radar and I will take a look again soon. There are also random other LoongArch things I need to take a look and I did. This is totally fine to be cherry picked into the release/17.x branch even after it is created.
I am sorry that I did not respond in time for the initial period of the patch (when it changed from the "WIP" state to the normal in-review state), but I think the request after 3 days may be a bit too quick.
Honestly the linker is probably I care about the most and I don't want to lower the bar. (There are other things that I am concerned with as well, but I may not have too much energy to prevent something less appropriate happen; but if I notice, I'll make a comment).

Thanks for the clarification. I didn't know if the release branch cherry-pick could be done in this case so I was a little anxious, sorry for the less-than-a-week ping.

I fully understand your passion and care for the linker and I agree with not lowering the bar; I'll do my best to improve the code together.

After being disgusted by the code of [another linker] multiple times I now totally agree we must be careful when we write a linker...

[MaskRay]

lld/ELF/Arch/LoongArch.cpp

89

I was quite confused by the description, then I realized that I probably should just figure out the formula myself:)

I wonder whether it's clear if we remove these textual descriptions and focus on the deduction:

// We have to check if the higher 32 bits need adjustment too, due to
// the large code model access pattern:
//
//     pcalau12i       A, %foo_hi20(sym)        // b in [0,0xfff]
//     addi.d          T, zero, %foo_lo12(sym)  // pageoff in [0,0xfff]
//     lu32i.d         T, %foo64_lo20(sym)      // c in [0,0xfffff]
//     lu52i.d         T, T, %foo64_hi12(sym)   // d in [0,0xfff]
//     {ldx,stx,add}.* A, A, T
//
// If we treat the immediates in the operands as unsigned, the adjusted page
// delta (return value) is b<<12 | c<<32 | d<<52.
// We have (pageoff<0x800?pageoff:pageoff-0x1000+0x100000000) + ((b<0x80000?b:b-0x100000)<<12) + (c<<32) + (d<<52) = dest - page(pc).
//
// When pageoff is 0xfff, its contribution to dest-page(pc) is effectively 0xfff-0x1000 + 0x100000000 as the high 32-bits are
// set by lu32i.d+lu52i.d, e.g.
//
//     addi.d    T, zero, -1  ; T = 0xfff'fffff'fffff'fff
//     lu32i.d   T, 1         ; T = 0x000'00001'fffff'fff
//     lu52i.d   T, T, -1     ; T = 0xfff'00001'fffff'fff

229

We probably should change the parameter to a const reference.

Not done?

[SixWeining]

Reminder: update lld/docs/ReleaseNotes.rst and lld/docs/index.rst when we finish this.

[xen0n]

Address review comments from @MaskRay and @SixWeining:

• Rewritten the docs for getLoongArchPageDelta, detailing the calculations;
• Added a missing const qualifier (I apparently misunderstood the review comment);
• Updated the docs.

[MaskRay]

lld/ELF/Arch/LoongArch.cpp

24

delete blank line

42

delete blank line

115

<< needs some parentheses due to operator precedence :)

lld/test/ELF/loongarch-abs64.s

66

delete trailing blank line

lld/test/ELF/loongarch-pcala-lo12-jirl-shared.s

18

Delete addresses for instructions that are not referenced. Fewer addresses makes test updating easier.

[xen0n]

(hopefully) final cosmetic fixes:

• Removed several extra blank lines
• Slightly tweaked getLoongArchPageDelta doc wording again and added parens so the operators in the pseudo-code follows C precedence
• Removed several extraneous disassembly addresses from the loongarch-pcala-lo12-jirl-shared.s test case

[xen0n]

Thanks for all the careful reviews that helped tremendously in improving the code quality (and forcing me to improve my ELF wrangling skills).

I've gone through the especially hard parts (getLoongArchPageDelta in particular; I had to JIT some funclets to ensure the operation is 100% correct) and I believe they should be good to go... And if things go awry I would surely be around to fix. Thanks go to everyone who has helped reviewing this code.

[xry111]

A question: does LLD automatically supports pack-relative-relocs once a new port is added? I'm trying to implement it for LoongArch BFD linker but it seems I don't have enough skill.

[xen0n]

In D138135#4531199, @xry111 wrote:

A question: does LLD automatically supports pack-relative-relocs once a new port is added? I'm trying to implement it for LoongArch BFD linker but it seems I don't have enough skill.

It seems to be the case. Last time I did the Gentoo LLVM bootstrap I saw binaries full with DT_RELR (I didn't remember if I manually forced the flag or not; Gentoo seems to enable it in some base profile anyway) and the glibc rtld consumed them just fine.

[xen0n]

In D138135#4531221, @xen0n wrote:

In D138135#4531199, @xry111 wrote:

A question: does LLD automatically supports pack-relative-relocs once a new port is added? I'm trying to implement it for LoongArch BFD linker but it seems I don't have enough skill.

It seems to be the case. Last time I did the Gentoo LLVM bootstrap I saw binaries full with DT_RELR (I didn't remember if I manually forced the flag or not; Gentoo seems to enable it in some base profile anyway) and the glibc rtld consumed them just fine.

I've just confirmed with a fresh QEMU build that the support is indeed working end-to-end.

[aaron.ballman]

It looks like there's a test failure happening in post-commit from one of the newly added tests: https://lab.llvm.org/buildbot/#/builders/42/builds/10617 Can you investigate (and revert if that's going to take a while to resolve)?

[xry111]

In D138135#4534933, @aaron.ballman wrote:

It looks like there's a test failure happening in post-commit from one of the newly added tests: https://lab.llvm.org/buildbot/#/builders/42/builds/10617 Can you investigate (and revert if that's going to take a while to resolve)?

I guess it's D156293.

[ruiu]

lld/ELF/Arch/LoongArch.cpp

163–164

Don't you need to recompute negativeA after adding 0x1000 to result? That yields a different result if the original result` value happened to be 0x7fff'f000.

lld/ELF/Arch/LoongArch.cpp

+//===- LoongArch.cpp ------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "InputFiles.h"
+#include "OutputSections.h"
+#include "Symbols.h"
+#include "SyntheticSections.h"
+#include "Target.h"
+
+using namespace llvm;
+using namespace llvm::object;
+using namespace llvm::support::endian;
+using namespace llvm::ELF;
+using namespace lld;
+using namespace lld::elf;
+
+// The LoongArch `pcalau12i` is behaviorally equivalent to the AArch64 `adrp`,
+// so a similar concept of "page" also applies here. A "page" is in fact just
+// another way to refer to the 12-bit range allowed by the immediate field of
+// the addi/ld/st instructions.
+//
+// Note: "pcalau12i" stands for something like "PC aligned add upper, from 12th
+// bit, immediate"; LoongArch instructions have no canonical full names,
+// neither English nor Chinese ones, according to the ISA manual.
+static uint64_t getLoongArchPage(uint64_t p) {
+  return p & ~static_cast<uint64_t>(0xFFF);
+}
+
+// Calculate the adjusted page offset between dest and PC.
+//
+// We must specially handle the cases when the low 12 bits of dest are seen
+// as negative, because the instructions consuming it (ld, st, addi, etc.)
+// all sign-extend the immediate, unlike AArch64. The higher bits need
+// tweaking too, due to potential usage in patterns like:
+//
+//     pcalau12i A, %foo_hi20(sym)
+//     addi.d    T, zero, %foo_lo12(sym)
+//     lu32i.d   T, %foo64_lo20(sym)
+//     lu52i.d   T, T, %foo64_hi12(sym)
+//     ldx.d     A, A, T
+//
+// in which case the "pc + hi20" part is separately constructed from the rest
+// which includes the higher 32-bit half and lo12, so the higher 32 bits need a
+// conditional nudge too, due to the signed addition performed by the ldx/stx.
+uint64_t elf::getLoongArchPageOffset(uint64_t dest, uint64_t pc) {
+  uint64_t result = getLoongArchPage(dest) - getLoongArchPage(pc);
+  if ((dest & 0xfff) > 0x7ff) {
+    result += 0x1000;
+    if (static_cast<int64_t>(result) > 0)
+      result -= 0x100000000;
+  }
+  return result;
+}
+
+namespace {
+
+class LoongArch final : public TargetInfo {
+public:
+  LoongArch();
+  uint32_t calcEFlags() const override;
+  int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
+  void writeGotHeader(uint8_t *buf) const override;
+  void writeGotPlt(uint8_t *buf, const Symbol &s) const override;
+  void writeIgotPlt(uint8_t *buf, const Symbol &s) const override;
+  void writePltHeader(uint8_t *buf) const override;
+  void writePlt(uint8_t *buf, const Symbol &sym,
+                uint64_t pltEntryAddr) const override;
+  RelType getDynRel(RelType type) const override;
+  RelExpr getRelExpr(RelType type, const Symbol &s,
+                     const uint8_t *loc) const override;
+  bool usesOnlyLowPageBits(RelType type) const override;
+  void relocate(uint8_t *loc, const Relocation &rel,
+                uint64_t val) const override;
+};
+
+} // end anonymous namespace
+
+const uint64_t dtpOffset = 0;
+
+enum Op {
+  SUB_W = 0x00110000,
+  SUB_D = 0x00118000,
+  BREAK = 0x002a0000,
+  SRLI_W = 0x00448000,
+  SRLI_D = 0x00450000,
+  ADDI_W = 0x02800000,
+  ADDI_D = 0x02c00000,
+  ANDI = 0x03400000,
+  PCADDU12I = 0x1c000000,
+  LD_W = 0x28800000,
+  LD_D = 0x28c00000,
+  JIRL = 0x4c000000,
+};
+
+enum Reg {
+  R_ZERO = 0,
+  R_RA = 1,
+  R_TP = 2,
+  R_T0 = 12,
+  R_T1 = 13,
+  R_T2 = 14,
+  R_T3 = 15,
+};
+
+static uint32_t hi20(uint32_t val) { return (val + 0x800) >> 12; }
+static uint32_t lo12(uint32_t val) { return val & 0xfff; }
+
+static uint32_t insn(uint32_t op, uint32_t d, uint32_t j, uint32_t k) {
+  return op | d | (j << 5) | (k << 10);
+}
+
+// Extract bits v[begin:end], where range is inclusive.
+static uint32_t extractBits(uint64_t v, uint32_t begin, uint32_t end) {
+  return begin == 63 ? v >> end : (v & ((1ULL << (begin + 1)) - 1)) >> end;
+}
+
+static uint32_t setD5k16(uint32_t insn, uint32_t imm) {
+  uint32_t immLo = extractBits(imm, 15, 0);
+  uint32_t immHi = extractBits(imm, 20, 16);
+  return (insn & 0xfc0003e0) | (immLo << 10) | immHi;
+}
+
+static uint32_t setD10k16(uint32_t insn, uint32_t imm) {
+  uint32_t immLo = extractBits(imm, 15, 0);
+  uint32_t immHi = extractBits(imm, 25, 16);
+  return (insn & 0xfc000000) | (immLo << 10) | immHi;
+}
+
+static uint32_t setJ20(uint32_t insn, uint32_t imm) {
+  return (insn & 0xfe00001f) | (extractBits(imm, 19, 0) << 5);
+}
+
+static uint32_t setK12(uint32_t insn, uint32_t imm) {
+  return (insn & 0xffc003ff) | (extractBits(imm, 11, 0) << 10);
+}
+
+static uint32_t setK16(uint32_t insn, uint32_t imm) {
+  return (insn & 0xfc0003ff) | (extractBits(imm, 15, 0) << 10);
+}
+
+static bool isJirl(uint32_t insn) {
+  return (insn & 0xfc000000) == JIRL;
+}
+
+LoongArch::LoongArch() {
+  // The LoongArch ISA itself does not have a limit on page sizes. According to
+  // the ISA manual, the PS (page size) field in MTLB entries and CSR.STLBPS is
+  // 6 bits wide, meaning the maximum page size is 2^63 which is equivalent to
+  // "unlimited".
+  // However, practically the maximum usable page size is constrained by the
+  // kernel implementation, and 64KiB is the biggest non-huge page size
+  // supported by Linux as of v6.1.
+  defaultMaxPageSize = 65536;
+  write32(trapInstr.data(), BREAK); // break 0
+
+  copyRel = R_LARCH_COPY;
+  pltRel = R_LARCH_JUMP_SLOT;
+  relativeRel = R_LARCH_RELATIVE;
+  iRelativeRel = R_LARCH_IRELATIVE;
+
+  if (config->is64) {
+    symbolicRel = R_LARCH_64;
+    tlsModuleIndexRel = R_LARCH_TLS_DTPMOD64;
+    tlsOffsetRel = R_LARCH_TLS_DTPREL64;
+    tlsGotRel = R_LARCH_TLS_TPREL64;
+  } else {
+    symbolicRel = R_LARCH_32;
+    tlsModuleIndexRel = R_LARCH_TLS_DTPMOD32;
+    tlsOffsetRel = R_LARCH_TLS_DTPREL32;
+    tlsGotRel = R_LARCH_TLS_TPREL32;
+  }
+
+  gotRel = symbolicRel;
+
+  // .got[0] = _DYNAMIC
+  gotHeaderEntriesNum = 1;
+
+  // .got.plt[0] = _dl_runtime_resolve, .got.plt[1] = link_map
+  gotPltHeaderEntriesNum = 2;
+
+  pltHeaderSize = 32;
+  pltEntrySize = 16;
+  ipltEntrySize = 16;
+}
+
+static uint32_t getEFlags(InputFile *f) {
+  if (config->is64)
+    return cast<ObjFile<ELF64LE>>(f)->getObj().getHeader().e_flags;
+  return cast<ObjFile<ELF32LE>>(f)->getObj().getHeader().e_flags;
+}
+
+uint32_t LoongArch::calcEFlags() const {
+  // If there are only binary input files (from -b binary), use a
+  // value of 0 for the ELF header flags.
+  if (ctx.objectFiles.empty())
+    return 0;
+
+  uint32_t target = getEFlags(ctx.objectFiles.front());
+
+  for (InputFile *f : ctx.objectFiles) {
+    if ((getEFlags(f) & EF_LOONGARCH_ABI_MODIFIER_MASK) !=
+        (target & EF_LOONGARCH_ABI_MODIFIER_MASK))
+      error(toString(f) +
+            ": cannot link object files with different ABI");
+
+    // We cannot process psABI v1.x / object ABI v0 files (containing stack
+    // relocations), unlike ld.bfd.
+    //
+    // Instead of blindly accepting every v0 object and only failing at
+    // relocation processing time, just disallow interlink altogether. We
+    // don't expect significant usage of object ABI v0 in the wild (the old
+    // world may continue using object ABI v0 for a while, but as it's not
+    // binary-compatible with the upstream i.e. new-world ecosystem, it's not
+    // being considered here).
+    //
+    // There are briefly some new-world systems with object ABI v0 binaries too.
+    // It is because these programs were built before v1 was finalized.
+    // These are not supported either due to the extremely small number of them,
+    // and the few impacted users are advised to simply rebuild world or
+    // reinstall a recent system.
+    if ((getEFlags(f) & EF_LOONGARCH_OBJABI_MASK) != EF_LOONGARCH_OBJABI_V1)
+      error(toString(f) + ": unsupported object file ABI version");
+  }
+
+  return target;
+}
+
+int64_t LoongArch::getImplicitAddend(const uint8_t *buf, RelType type) const {
+  switch (type) {
+  default:
+    internalLinkerError(getErrorLocation(buf),
+                        "cannot read addend for relocation " + toString(type));
+    return 0;
+  case R_LARCH_32:
+  case R_LARCH_TLS_DTPMOD32:
+  case R_LARCH_TLS_DTPREL32:
+  case R_LARCH_TLS_TPREL32:
+    return SignExtend64<32>(read32le(buf));
+  case R_LARCH_64:
+  case R_LARCH_TLS_DTPMOD64:
+  case R_LARCH_TLS_DTPREL64:
+  case R_LARCH_TLS_TPREL64:
+    return read64le(buf);
+  case R_LARCH_RELATIVE:
+  case R_LARCH_IRELATIVE:
+    return config->is64 ? read64le(buf) : read32le(buf);
+  case R_LARCH_NONE:
+  case R_LARCH_JUMP_SLOT:
+    // These relocations are defined as not having an implicit addend.
+    return 0;
+  }
+}
+
+void LoongArch::writeGotHeader(uint8_t *buf) const {
+  if (config->is64)
+    write64le(buf, mainPart->dynamic->getVA());
+  else
+    write32le(buf, mainPart->dynamic->getVA());
+}
+
+void LoongArch::writeGotPlt(uint8_t *buf, const Symbol &s) const {
+  if (config->is64)
+    write64le(buf, in.plt->getVA());
+  else
+    write32le(buf, in.plt->getVA());
+}
+
+void LoongArch::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
+  if (config->writeAddends) {
+    if (config->is64)
+      write64le(buf, s.getVA());
+    else
+      write32le(buf, s.getVA());
+  }
+}
+
+void LoongArch::writePltHeader(uint8_t *buf) const {
+  // The LoongArch PLT is currently structured just like that of RISCV.
+  // Annoyingly, this means the PLT is still using `pcaddu12i` to perform
+  // PC-relative addressing (because `pcaddu12i` is the same as RISCV `auipc`),
+  // in contrast to the AArch64-like page-offset scheme with `pcalau12i` that
+  // is used everywhere else involving PC-relative operations in the LoongArch
+  // ELF psABI v2.00.
+  // The `pcrel_{hi20,lo12}` operators are illustrative only and not really
+  // supported by LoongArch assemblers.
+  //
+  // 1: pcaddu12i $t2, %pcrel_hi20(.got.plt)
+  //    sub.[wd]  $t1, $t1, $t3
+  //    ld.[wd]   $t3, $t2, %pcrel_lo12(1b)  ; t3 = _dl_runtime_resolve
+  //    addi.[wd] $t1, $t1, -pltHeaderSize-12; t1 = &.plt[i] - &.plt[0]
+  //    addi.[wd] $t0, $t2, %pcrel_lo12(1b)
+  //    srli.[wd] $t1, $t1, (is64?1:2)       ; t1 = &.got.plt[i] - &.got.plt[0]
+  //    ld.[wd]   $t0, $t0, Wordsize(t0)     ; t0 = link_map
+  //    jr        $t3
+  uint32_t offset = in.gotPlt->getVA() - in.plt->getVA();
+  uint32_t sub = config->is64 ? SUB_D : SUB_W;
+  uint32_t ld = config->is64 ? LD_D : LD_W;
+  uint32_t addi = config->is64 ? ADDI_D : ADDI_W;
+  uint32_t srli = config->is64 ? SRLI_D : SRLI_W;
+  write32le(buf + 0, insn(PCADDU12I, R_T2, hi20(offset), 0));
+  write32le(buf + 4, insn(sub, R_T1, R_T1, R_T3));
+  write32le(buf + 8, insn(ld, R_T3, R_T2, lo12(offset)));
+  write32le(buf + 12, insn(addi, R_T1, R_T1, lo12(-target->pltHeaderSize - 12)));
+  write32le(buf + 16, insn(addi, R_T0, R_T2, lo12(offset)));
+  write32le(buf + 20, insn(srli, R_T1, R_T1, config->is64 ? 1 : 2));
+  write32le(buf + 24, insn(ld, R_T0, R_T0, config->wordsize));
+  write32le(buf + 28, insn(JIRL, R_ZERO, R_T3, 0));
+}
+
+void LoongArch::writePlt(uint8_t *buf, const Symbol &sym,
+                     uint64_t pltEntryAddr) const {
+  // See the comment in writePltHeader for reason why pcaddu12i is used instead
+  // of the pcalau12i that's more commonly seen in the ELF psABI v2.0 days.
+  //
+  // 1: pcaddu12i $t3, %pcrel_hi20(f@.got.plt)
+  //    ld.[wd]   $t3, $t3, %pcrel_lo12(1b)
+  //    jirl      $t1, $t3, 0
+  //    nop
+  uint32_t offset = sym.getGotPltVA() - pltEntryAddr;
+  write32le(buf + 0, insn(PCADDU12I, R_T3, hi20(offset), 0));
+  write32le(buf + 4,
+            insn(config->is64 ? LD_D : LD_W, R_T3, R_T3, lo12(offset)));
+  write32le(buf + 8, insn(JIRL, R_T1, R_T3, 0));
+  write32le(buf + 12, insn(ANDI, R_ZERO, R_ZERO, 0));
+}
+
+RelType LoongArch::getDynRel(RelType type) const {
+  return type == target->symbolicRel ? type
+                                     : static_cast<RelType>(R_LARCH_NONE);
+}
+
+RelExpr LoongArch::getRelExpr(const RelType type, const Symbol &s,
+                              const uint8_t *loc) const {
+  switch (type) {
+  case R_LARCH_NONE:
+  case R_LARCH_MARK_LA:
+  case R_LARCH_MARK_PCREL:
+    return R_NONE;
+  case R_LARCH_32:
+  case R_LARCH_64:
+  case R_LARCH_ABS_HI20:
+  case R_LARCH_ABS_LO12:
+  case R_LARCH_ABS64_LO20:
+  case R_LARCH_ABS64_HI12:
+    return R_ABS;
+  case R_LARCH_PCALA_LO12:
+    // This may well be just R_ABS and nothing more, but unfortunately some
+    // people had the brilliant idea of reusing the R_LARCH_PCALA_LO12 reloc on
+    // JIRLs, for implementing the medium code model, seemingly for avoiding
+    // having to add another reloc type just for that. The intended use case is
+    // for making the libc_nonshared.a of glibc 2.37+ usable with large
+    // applications like Firefox or Chromium, where an R_LARCH_B26 will overflow
+    // otherwise. See [1] for details.
+    //
+    // This is bad for multiple reasons:
+    //
+    // * R_LARCH_PCALA_LO12 just places its computed value unmodified, but JIRL
+    //   expects its immediate to be pre-shifted by 2 bits, making the reloc
+    //   behavior dependent on the underlying input section content;
+    // * R_LARCH_PCALA_LO12 leaves the upper 16-12+2=6 bits of JIRL's immediate
+    //   operand unusable, making the usage forever a kludge: a proper reloc
+    //   type has to be added *anyway*, to be able to leverage the PCADDU18I +
+    //   JIRL combo, for example.
+    //   (In this case an ISA revision (!) is arguably necessary, because there
+    //   is not a PCALAU18I for stylistic consistency with the other psABI v2.00
+    //   relocs. If PCADDU18I is to be used anyway, that would mean the new
+    //   relocs are PCREL-style instead of PCALA; so for consistency, PCREL
+    //   relocs for the other psABI v2.00 relocs should be added as well...)
+    // * Inspection into the input section must be performed for every
+    //   R_LARCH_PCALA_LO12 record, which is one of the most frequently used
+    //   LoongArch reloc types, but usage of the medium code model is not nearly
+    //   as popular, so arguably ~100% of the checks are in fact wasted for very
+    //   little gain.
+    //
+    // The problem is long known, and already reported with a suggested fix
+    // back in September 2022 [2]. But the pull request has not received any
+    // comment since then, and object code with this usage will soon appear with
+    // the release of glibc 2.37, so we have no choice but to carry the same
+    // kind of workaround as the BFD linker does.
+    //
+    // [1]: https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=9f482b73f41a9a1bbfb173aad0733d1c824c788a
+    // [2]: https://github.com/loongson/LoongArch-Documentation/pull/69
+    return isJirl(read32le(loc)) ? R_PLT : R_ABS;
+  case R_LARCH_TLS_DTPREL32:
+  case R_LARCH_TLS_DTPREL64:
+    return R_DTPREL;
+  case R_LARCH_TLS_TPREL32:
+  case R_LARCH_TLS_TPREL64:
+  case R_LARCH_TLS_LE_HI20:
+  case R_LARCH_TLS_LE_LO12:
+  case R_LARCH_TLS_LE64_LO20:
+  case R_LARCH_TLS_LE64_HI12:
+    return R_TPREL;
+  case R_LARCH_ADD8:
+  case R_LARCH_ADD16:
+  case R_LARCH_ADD32:
+  case R_LARCH_ADD64:
+  case R_LARCH_SUB8:
+  case R_LARCH_SUB16:
+  case R_LARCH_SUB32:
+  case R_LARCH_SUB64:
+    // The LoongArch add/sub relocs behave like the RISCV counterparts; reuse
+    // the RelExpr to avoid code duplication.
+    return R_RISCV_ADD;
+  case R_LARCH_32_PCREL:
+    return R_PC;
+  case R_LARCH_B16:
+  case R_LARCH_B21:
+  case R_LARCH_B26:
+    return R_PLT_PC;
+  case R_LARCH_GOT_PC_HI20:
+  case R_LARCH_GOT64_PC_LO20:
+  case R_LARCH_GOT64_PC_HI12:
+    return R_LOONGARCH_GOT_PAGE_PC;
+  case R_LARCH_GOT_PC_LO12:
+  case R_LARCH_TLS_IE_PC_LO12:
+    return R_LOONGARCH_GOT;
+  case R_LARCH_TLS_LD_PC_HI20:
+  case R_LARCH_TLS_GD_PC_HI20:
+    return R_LOONGARCH_GOT_TLSGD_PAGE_PC;
+  case R_LARCH_TLS_IE_PC_HI20:
+  case R_LARCH_TLS_IE64_PC_LO20:
+  case R_LARCH_TLS_IE64_PC_HI12:
+    return R_LOONGARCH_GOT_TLSIE_PAGE_PC;
+  case R_LARCH_PCALA_HI20:
+    // Why not R_LOONGARCH_PAGE_PC, majority of references don't go through PLT
+    // anyway so why waste time checking only to get everything relaxed back to
+    // it?
+    //
+    // This is again due to the R_LARCH_PCALA_LO12 on JIRL case, where we want
+    // both the HI20 and LO12 to potentially refer to the PLT. But in reality
+    // the HI20 reloc appears earlier, and the relocs don't contain enough
+    // information to let us properly resolve semantics per symbol.
+    // Unlike RISCV, our LO12 relocs *do not* point to their corresponding HI20
+    // relocs, hence it is nearly impossible to 100% accurately determine each
+    // HI20's "flavor" without taking big performance hits, in the presence of
+    // edge cases (e.g. HI20 without pairing LO12, paired LO12 placed so far
+    // apart that relationship is not certain anymore), and programmer mistakes
+    // (e.g. as outlined in https://github.com/loongson/LoongArch-Documentation/pull/69).
+    //
+    // Ideally we would scan in an extra pass for all LO12s on JIRL, then mark
+    // every HI20 reloc referring to the same symbol differently; this is not
+    // feasible with the current function signature of getRelExpr that doesn't
+    // allow for such inter-pass state.
+    //
+    // So, unfortunately we have to again workaround this quirk the same way as
+    // BFD: assuming every R_LARCH_PCALA_HI20 is potentially PLT needing, only
+    // relaxing to R_LOONGARCH_PAGE_PC if it's known not so at a later stage.
+    return R_LOONGARCH_PLT_PAGE_PC;
+  case R_LARCH_PCALA64_LO20:
+  case R_LARCH_PCALA64_HI12:
+    return R_LOONGARCH_PAGE_PC;
+  case R_LARCH_GOT_HI20:
+  case R_LARCH_GOT_LO12:
+  case R_LARCH_GOT64_LO20:
+  case R_LARCH_GOT64_HI12:
+  case R_LARCH_TLS_IE_HI20:
+  case R_LARCH_TLS_IE_LO12:
+  case R_LARCH_TLS_IE64_LO20:
+  case R_LARCH_TLS_IE64_HI12:
+    return R_GOT;
+  case R_LARCH_TLS_LD_HI20:
+    return R_TLSLD_GOT;
+  case R_LARCH_TLS_GD_HI20:
+    return R_TLSGD_GOT;
+  case R_LARCH_RELAX:
+    // LoongArch linker relaxation is not defined yet.
+    return R_NONE;
+
+  // A stack machine (read: global mutable state) is necessary for properly
+  // computing these relocs, and these relocs are already deprecated after
+  // the release of LoongArch ELF psABI v2.00, so we are not going to
+  // implement them.
+  case R_LARCH_SOP_PUSH_PCREL:
+  case R_LARCH_SOP_PUSH_ABSOLUTE:
+  case R_LARCH_SOP_PUSH_DUP:
+  case R_LARCH_SOP_PUSH_GPREL:
+  case R_LARCH_SOP_PUSH_TLS_TPREL:
+  case R_LARCH_SOP_PUSH_TLS_GOT:
+  case R_LARCH_SOP_PUSH_TLS_GD:
+  case R_LARCH_SOP_PUSH_PLT_PCREL:
+  case R_LARCH_SOP_ASSERT:
+  case R_LARCH_SOP_NOT:
+  case R_LARCH_SOP_SUB:
+  case R_LARCH_SOP_SL:
+  case R_LARCH_SOP_SR:
+  case R_LARCH_SOP_ADD:
+  case R_LARCH_SOP_AND:
+  case R_LARCH_SOP_IF_ELSE:
+  case R_LARCH_SOP_POP_32_S_10_5:
+  case R_LARCH_SOP_POP_32_U_10_12:
+  case R_LARCH_SOP_POP_32_S_10_12:
+  case R_LARCH_SOP_POP_32_S_10_16:
+  case R_LARCH_SOP_POP_32_S_10_16_S2:
+  case R_LARCH_SOP_POP_32_S_5_20:
+  case R_LARCH_SOP_POP_32_S_0_5_10_16_S2:
+  case R_LARCH_SOP_POP_32_S_0_10_10_16_S2:
+  case R_LARCH_SOP_POP_32_U:
+  // Nor are we implementing these two reloc types that were probably added
+  // without much thought, and already proposed to be removed.
+  // See https://github.com/loongson/LoongArch-Documentation/issues/51
+  case R_LARCH_ADD24:
+  case R_LARCH_SUB24:
+  // Similarly for these two, long deprecated and unused even before the
+  // inception of LoongArch.
+  case R_LARCH_GNU_VTINHERIT:
+  case R_LARCH_GNU_VTENTRY:
+    error(getErrorLocation(loc) +
+          "cannot handle deprecated relocation " + toString(type) +
+          " against symbol " + toString(s));
+    return R_NONE;
+
+  default:
+    error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) +
+          ") against symbol " + toString(s));
+    return R_NONE;
+  }
+}
+
+bool LoongArch::usesOnlyLowPageBits(RelType type) const {
+  switch (type) {
+  default:
+    return false;
+  case R_LARCH_PCALA_LO12:
+  case R_LARCH_GOT_LO12:
+  case R_LARCH_GOT_PC_LO12:
+  case R_LARCH_TLS_IE_PC_LO12:
+    return true;
+  }
+}
+
+void LoongArch::relocate(uint8_t *loc, const Relocation &rel,
+                         uint64_t val) const {
+  switch (rel.type) {
+  case R_LARCH_32_PCREL:
+    checkInt(loc, val, 32, rel);
+    [[fallthrough]];
+  case R_LARCH_32:
+    write32le(loc, val);
+    return;
+  case R_LARCH_64:
+    write64le(loc, val);
+    return;
+
+  case R_LARCH_B16: {
+    checkInt(loc, val, 18, rel);
+    checkAlignment(loc, val, 4, rel);
+    write32le(loc, setK16(read32le(loc), val >> 2));
+    return;
+  }
+
+  case R_LARCH_B21: {
+    checkInt(loc, val, 23, rel);
+    checkAlignment(loc, val, 4, rel);
+    write32le(loc, setD5k16(read32le(loc), val >> 2));
+    return;
+  }
+
+  case R_LARCH_B26: {
+    checkInt(loc, val, 28, rel);
+    checkAlignment(loc, val, 4, rel);
+    write32le(loc, setD10k16(read32le(loc), val >> 2));
+    return;
+  }
+
+  // Relocs intended for `addi`, `ld` or `st`.
+  case R_LARCH_ABS_LO12:
+  case R_LARCH_PCALA_LO12:
+  case R_LARCH_GOT_PC_LO12:
+  case R_LARCH_GOT_LO12:
+  case R_LARCH_TLS_LE_LO12:
+  case R_LARCH_TLS_IE_PC_LO12:
+  case R_LARCH_TLS_IE_LO12: {
+    // Annoyingly, we have to again inspect the insn word to handle the
+    // R_LARCH_PCALA_LO12 on JIRL case: JIRL wants its immediate's 2 lowest
+    // zeroes removed by us, and the immediate slot width is in fact different.
+    // In this case, process like an R_LARCH_B16 without the overflow check, and
+    // only taking the value's lowest 12 bits.
+    if (rel.type == R_LARCH_PCALA_LO12 && isJirl(read32le(loc))) {
+      checkAlignment(loc, val, 4, rel);
+      val = SignExtend64<12>(val);
+      write32le(loc, setK16(read32le(loc), val >> 2));
+      return;
+    }
+    write32le(loc, setK12(read32le(loc), extractBits(val, 11, 0)));
+    return;
+  }
+
+  // Relocs intended for `lu12i.w` or `pcalau12i`.
+  case R_LARCH_ABS_HI20:
+  case R_LARCH_PCALA_HI20:
+  case R_LARCH_GOT_PC_HI20:
+  case R_LARCH_GOT_HI20:
+  case R_LARCH_TLS_LE_HI20:
+  case R_LARCH_TLS_IE_PC_HI20:
+  case R_LARCH_TLS_IE_HI20:
+  case R_LARCH_TLS_LD_PC_HI20:
+  case R_LARCH_TLS_LD_HI20:
+  case R_LARCH_TLS_GD_PC_HI20:
+  case R_LARCH_TLS_GD_HI20: {
+    write32le(loc, setJ20(read32le(loc), extractBits(val, 31, 12)));
+    return;
+  }
+
+  // Relocs intended for `lu32i.d`.
+  case R_LARCH_ABS64_LO20:
+  case R_LARCH_PCALA64_LO20:
+  case R_LARCH_GOT64_PC_LO20:
+  case R_LARCH_GOT64_LO20:
+  case R_LARCH_TLS_LE64_LO20:
+  case R_LARCH_TLS_IE64_PC_LO20:
+  case R_LARCH_TLS_IE64_LO20: {
+    write32le(loc, setJ20(read32le(loc), extractBits(val, 51, 32)));
+    return;
+  }
+
+  // Relocs intended for `lu52i.d`.
+  case R_LARCH_ABS64_HI12:
+  case R_LARCH_PCALA64_HI12:
+  case R_LARCH_GOT64_PC_HI12:
+  case R_LARCH_GOT64_HI12:
+  case R_LARCH_TLS_LE64_HI12:
+  case R_LARCH_TLS_IE64_PC_HI12:
+  case R_LARCH_TLS_IE64_HI12: {
+    write32le(loc, setK12(read32le(loc), extractBits(val, 63, 52)));
+    return;
+  }
+
+  case R_LARCH_ADD8:
+    *loc += val;
+    return;
+  case R_LARCH_ADD16:
+    write16le(loc, read16le(loc) + val);
+    return;
+  case R_LARCH_ADD32:
+    write32le(loc, read32le(loc) + val);
+    return;
+  case R_LARCH_ADD64:
+    write64le(loc, read64le(loc) + val);
+    return;
+  case R_LARCH_SUB8:
+    *loc -= val;
+    return;
+  case R_LARCH_SUB16:
+    write16le(loc, read16le(loc) - val);
+    return;
+  case R_LARCH_SUB32:
+    write32le(loc, read32le(loc) - val);
+    return;
+  case R_LARCH_SUB64:
+    write64le(loc, read64le(loc) - val);
+    return;
+
+  case R_LARCH_TLS_DTPREL32:
+    write32le(loc, val - dtpOffset);
+    break;
+  case R_LARCH_TLS_DTPREL64:
+    write64le(loc, val - dtpOffset);
+    break;
+
+  case R_LARCH_MARK_LA:
+  case R_LARCH_MARK_PCREL:
+    // no-op
+    return;
+
+  case R_LARCH_RELAX:
+    return; // Ignored (for now)
+
+  default:
+    llvm_unreachable("unknown relocation");
+  }
+}
+
+TargetInfo *elf::getLoongArchTargetInfo() {
+  static LoongArch target;
+  return &target;
+}

lld/ELF/CMakeLists.txt

 
 add_lld_library(lldELF
   AArch64ErrataFix.cpp
   Arch/AArch64.cpp
   Arch/AMDGPU.cpp
   Arch/ARM.cpp
   Arch/AVR.cpp
   Arch/Hexagon.cpp
+  Arch/LoongArch.cpp
   Arch/Mips.cpp
   Arch/MipsArchTree.cpp
   Arch/MSP430.cpp
   Arch/PPC.cpp
   Arch/PPC64.cpp
   Arch/RISCV.cpp
   Arch/SPARCV9.cpp
   Arch/X86.cpp

lld/ELF/Driver.cpp

std::pair<ELFKind, uint16_t> ret =
           .Cases("armelf", "armelf_linux_eabi", {ELF32LEKind, EM_ARM})
           .Cases("armelfb", "armelfb_linux_eabi", {ELF32BEKind, EM_ARM})
           .Case("elf32_x86_64", {ELF32LEKind, EM_X86_64})
           .Cases("elf32btsmip", "elf32btsmipn32", {ELF32BEKind, EM_MIPS})
           .Cases("elf32ltsmip", "elf32ltsmipn32", {ELF32LEKind, EM_MIPS})
           .Case("elf32lriscv", {ELF32LEKind, EM_RISCV})
           .Cases("elf32ppc", "elf32ppclinux", {ELF32BEKind, EM_PPC})
           .Cases("elf32lppc", "elf32lppclinux", {ELF32LEKind, EM_PPC})
+          .Case("elf32loongarch", {ELF32LEKind, EM_LOONGARCH})
           .Case("elf64btsmip", {ELF64BEKind, EM_MIPS})
           .Case("elf64ltsmip", {ELF64LEKind, EM_MIPS})
           .Case("elf64lriscv", {ELF64LEKind, EM_RISCV})
           .Case("elf64ppc", {ELF64BEKind, EM_PPC64})
           .Case("elf64lppc", {ELF64LEKind, EM_PPC64})
           .Cases("elf_amd64", "elf_x86_64", {ELF64LEKind, EM_X86_64})
           .Case("elf_i386", {ELF32LEKind, EM_386})
           .Case("elf_iamcu", {ELF32LEKind, EM_IAMCU})
           .Case("elf64_sparc", {ELF64BEKind, EM_SPARCV9})
           .Case("msp430elf", {ELF32LEKind, EM_MSP430})
           .Case("elf64_amdgpu", {ELF64LEKind, EM_AMDGPU})
+          .Case("elf64loongarch", {ELF64LEKind, EM_LOONGARCH})
           .Default({ELFNoneKind, EM_NONE});
 
   if (ret.first == ELFNoneKind)
     error("unknown emulation: " + emul);
   if (ret.second == EM_MSP430)
     osabi = ELFOSABI_STANDALONE;
   else if (ret.second == EM_AMDGPU)
     osabi = ELFOSABI_AMDGPU_HSA;
for (auto *arg : args.filtered_reverse(OPT_z)) {
     if (s == "rel")
       return false;
     if (s == "rela")
       return true;
   }
 
   // Otherwise use the psABI defined relocation entry format.
   uint16_t m = config->emachine;
-  return m == EM_AARCH64 || m == EM_AMDGPU || m == EM_HEXAGON || m == EM_PPC ||
-         m == EM_PPC64 || m == EM_RISCV || m == EM_X86_64;
+  return m == EM_AARCH64 || m == EM_AMDGPU || m == EM_HEXAGON ||
+         m == EM_LOONGARCH || m == EM_PPC || m == EM_PPC64 || m == EM_RISCV ||
+         m == EM_X86_64;
 }
 
 static void parseClangOption(StringRef opt, const Twine &msg) {
   std::string err;
   raw_string_ostream os(err);
 
   const char *argv[] = {config->progName.data(), opt.data()};
   if (cl::ParseCommandLineOptions(2, argv, "", &os))
config->writeAddends = args.hasFlag(OPT_apply_dynamic_relocs,
                                       OPT_no_apply_dynamic_relocs, false) ||
                          !config->isRela;
   // Validation of dynamic relocation addends is on by default for assertions
   // builds (for supported targets) and disabled otherwise. Ideally we would
   // enable the debug checks for all targets, but currently not all targets
   // have support for reading Elf_Rel addends, so we only enable for a subset.
 #ifndef NDEBUG
   bool checkDynamicRelocsDefault = m == EM_AARCH64 || m == EM_ARM ||
-                                   m == EM_386 || m == EM_MIPS ||
-                                   m == EM_X86_64 || m == EM_RISCV;
+                                   m == EM_386 || m == EM_LOONGARCH ||
+                                   m == EM_MIPS || m == EM_RISCV ||
+                                   m == EM_X86_64;
 #else
   bool checkDynamicRelocsDefault = false;
 #endif
   config->checkDynamicRelocs =
       args.hasFlag(OPT_check_dynamic_relocations,
                    OPT_no_check_dynamic_relocations, checkDynamicRelocsDefault);
   config->tocOptimize =
       args.hasFlag(OPT_toc_optimize, OPT_no_toc_optimize, m == EM_PPC64);

lld/ELF/InputFiles.cpp

case Triple::r600:
     return EM_AMDGPU;
   case Triple::arm:
   case Triple::thumb:
     return EM_ARM;
   case Triple::avr:
     return EM_AVR;
   case Triple::hexagon:
     return EM_HEXAGON;
+  case Triple::loongarch32:
+  case Triple::loongarch64:
+    return EM_LOONGARCH;
   case Triple::mips:
   case Triple::mipsel:
   case Triple::mips64:
   case Triple::mips64el:
     return EM_MIPS;
   case Triple::msp430:
     return EM_MSP430;
   case Triple::ppc:

lld/ELF/InputSection.cpp

 #include "SyntheticSections.h"
 #include "Target.h"
 #include "lld/Common/CommonLinkerContext.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/Compression.h"
 #include "llvm/Support/Endian.h"
 #include "llvm/Support/xxhash.h"
 #include <algorithm>
+#include <atomic>
 #include <mutex>
 #include <vector>
 
 using namespace llvm;
 using namespace llvm::ELF;
 using namespace llvm::object;
 using namespace llvm::support;
 using namespace llvm::support::endian;
return s.getVA(0) + config->wordsize * 2 +
            ((tls->p_vaddr - config->wordsize * 2) & (tls->p_align - 1));
   case EM_MIPS:
   case EM_PPC:
   case EM_PPC64:
     // Adjusted Variant 1. TP is placed with a displacement of 0x7000, which is
     // to allow a signed 16-bit offset to reach 0x1000 of TCB/thread-library
     // data and 0xf000 of the program's TLS segment.
     return s.getVA(0) + (tls->p_vaddr & (tls->p_align - 1)) - 0x7000;
+  case EM_LOONGARCH:
   case EM_RISCV:
     return s.getVA(0) + (tls->p_vaddr & (tls->p_align - 1));
 
     // Variant 2.
   case EM_HEXAGON:
   case EM_SPARCV9:
   case EM_386:
   case EM_X86_64:
uint64_t InputSectionBase::getRelocTargetVA(const InputFile *file, RelType type,
   case R_ADDEND:
     return a;
   case R_RELAX_HINT:
     return 0;
   case R_ARM_SBREL:
     return sym.getVA(a) - getARMStaticBase(sym);
   case R_GOT:
   case R_RELAX_TLS_GD_TO_IE_ABS:
     return sym.getGotVA() + a;
+  case R_LOONGARCH_GOT:
+    // The LoongArch PC-relative GOT relocs are notorious, in that the TLS
+    // relocs share the same reloc type with non-TLS ones for their page
+    // offsets. The arithmetics are different in the TLS case so we have to
+    // duplicate some logic here.
+    if (sym.isTls()) {
+      if (type == R_LARCH_TLS_IE_PC_LO12)
+        // Like R_LOONGARCH_GOT_TLSIE_PAGE_PC but taking the absolute value.
+        return sym.getGotVA() + a;
+      if (sym.hasFlag(NEEDS_TLSGD))
+        // Like R_LOONGARCH_TLSGD_PAGE_PC but taking the absolute value.
+        return in.got->getGlobalDynAddr(sym) + a;
+      if (ctx.needsTlsLd.load(std::memory_order_relaxed))
+        // Like R_TLSLD_PC but taking the absolute value.
+        return in.got->getTlsIndexVA() + a;
+      // Fallthrough; relocate like R_GOT.
+    }
+    return sym.getGotVA() + a;
   case R_GOTONLY_PC:
     return in.got->getVA() + a - p;
   case R_GOTPLTONLY_PC:
     return in.gotPlt->getVA() + a - p;
   case R_GOTREL:
   case R_PPC64_RELAX_TOC:
     return sym.getVA(a) - in.got->getVA();
   case R_GOTPLTREL:
     return sym.getVA(a) - in.gotPlt->getVA();
   case R_GOTPLT:
   case R_RELAX_TLS_GD_TO_IE_GOTPLT:
     return sym.getGotVA() + a - in.gotPlt->getVA();
   case R_TLSLD_GOT_OFF:
   case R_GOT_OFF:
   case R_RELAX_TLS_GD_TO_IE_GOT_OFF:
     return sym.getGotOffset() + a;
   case R_AARCH64_GOT_PAGE_PC:
   case R_AARCH64_RELAX_TLS_GD_TO_IE_PAGE_PC:
     return getAArch64Page(sym.getGotVA() + a) - getAArch64Page(p);
   case R_AARCH64_GOT_PAGE:
     return sym.getGotVA() + a - getAArch64Page(in.got->getVA());
   case R_GOT_PC:
   case R_RELAX_TLS_GD_TO_IE:
     return sym.getGotVA() + a - p;
+  case R_LOONGARCH_GOT_PAGE_PC:
+  case R_LOONGARCH_GOT_TLSIE_PAGE_PC:
+    return getLoongArchPageOffset(sym.getGotVA() + a, p);
   case R_MIPS_GOTREL:
     return sym.getVA(a) - in.mipsGot->getGp(file);
   case R_MIPS_GOT_GP:
     return in.mipsGot->getGp(file) + a;
   case R_MIPS_GOT_GP_PC: {
     // R_MIPS_LO16 expression has R_MIPS_GOT_GP_PC type iif the target
     // is _gp_disp symbol. In that case we should use the following
     // formula for calculation "AHL + GP - P + 4". For details see p. 4-19 at
     // ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
case R_AARCH64_PAGE_PC: {
     return getAArch64Page(val) - getAArch64Page(p);
   }
   case R_RISCV_PC_INDIRECT: {
     if (const Relocation *hiRel = getRISCVPCRelHi20(&sym, a))
       return getRelocTargetVA(file, hiRel->type, hiRel->addend, sym.getVA(),
                               *hiRel->sym, hiRel->expr);
     return 0;
   }
+  case R_LOONGARCH_PAGE_PC:
+    return getLoongArchPageOffset(sym.getVA(a), p);
   case R_PC:
   case R_ARM_PCA: {
     uint64_t dest;
     if (expr == R_ARM_PCA)
       // Some PC relative ARM (Thumb) relocations align down the place.
       p = p & 0xfffffffc;
     if (sym.isUndefined()) {
       // On ARM and AArch64 a branch to an undefined weak resolves to the next
case R_ARM_PCA: {
     }
     return dest - p;
   }
   case R_PLT:
     return sym.getPltVA() + a;
   case R_PLT_PC:
   case R_PPC64_CALL_PLT:
     return sym.getPltVA() + a - p;
+  case R_LOONGARCH_PLT_PAGE_PC:
+    return getLoongArchPageOffset(sym.getPltVA() + a, p);
   case R_PLT_GOTPLT:
     return sym.getPltVA() + a - in.gotPlt->getVA();
   case R_PPC32_PLTREL:
     // R_PPC_PLTREL24 uses the addend (usually 0 or 0x8000) to indicate r30
     // stores _GLOBAL_OFFSET_TABLE_ or .got2+0x8000. The addend is ignored for
     // target VA computation.
     return sym.getPltVA() - p;
   case R_PPC64_CALL: {
uint64_t InputSectionBase::getRelocTargetVA(const InputFile *file, RelType type,
   case R_AARCH64_TLSDESC_PAGE:
     return getAArch64Page(in.got->getTlsDescAddr(sym) + a) - getAArch64Page(p);
   case R_TLSGD_GOT:
     return in.got->getGlobalDynOffset(sym) + a;
   case R_TLSGD_GOTPLT:
     return in.got->getGlobalDynAddr(sym) + a - in.gotPlt->getVA();
   case R_TLSGD_PC:
     return in.got->getGlobalDynAddr(sym) + a - p;
+  case R_LOONGARCH_GOT_TLSGD_PAGE_PC:
+    return getLoongArchPageOffset(in.got->getGlobalDynAddr(sym) + a, p);
   case R_TLSLD_GOTPLT:
     return in.got->getVA() + in.got->getTlsIndexOff() + a - in.gotPlt->getVA();
   case R_TLSLD_GOT:
     return in.got->getTlsIndexOff() + a;
   case R_TLSLD_PC:
     return in.got->getTlsIndexVA() + a - p;
   default:
     llvm_unreachable("invalid expression");

lld/ELF/Relocations.h

enum RelExpr {
   R_PPC32_PLTREL,
   R_PPC64_CALL,
   R_PPC64_CALL_PLT,
   R_PPC64_RELAX_TOC,
   R_PPC64_TOCBASE,
   R_PPC64_RELAX_GOT_PC,
   R_RISCV_ADD,
   R_RISCV_PC_INDIRECT,
+  // Same as R_PC but with page-aligned semantics.
+  R_LOONGARCH_PAGE_PC,
+  // Same as R_PLT_PC but with page-aligned semantics.
+  R_LOONGARCH_PLT_PAGE_PC,
+  // LoongArch GOT relocs are also reused for TLS, so the required semantics
+  // differ from everyone else.
+  R_LOONGARCH_GOT,
+  R_LOONGARCH_GOT_PAGE_PC,
+  R_LOONGARCH_GOT_TLSGD_PAGE_PC,
+  R_LOONGARCH_GOT_TLSIE_PAGE_PC,
 };
 
 // Architecture-neutral representation of relocation.
 struct Relocation {
   RelExpr expr;
   RelType type;
   uint64_t offset;
   int64_t addend;

lld/ELF/Relocations.cpp

 }
 
 static bool isAbsoluteValue(const Symbol &sym) {
   return isAbsolute(sym) || sym.isTls();
 }
 
 // Returns true if Expr refers a PLT entry.
 static bool needsPlt(RelExpr expr) {
-  return oneof<R_PLT, R_PLT_PC, R_PLT_GOTPLT, R_PPC32_PLTREL, R_PPC64_CALL_PLT>(
-      expr);
+  return oneof<R_PLT, R_PLT_PC, R_PLT_GOTPLT, R_LOONGARCH_PLT_PAGE_PC,
+               R_PPC32_PLTREL, R_PPC64_CALL_PLT>(expr);
 }
 
 // Returns true if Expr refers a GOT entry. Note that this function
 // returns false for TLS variables even though they need GOT, because
 // TLS variables uses GOT differently than the regular variables.
 static bool needsGot(RelExpr expr) {
   return oneof<R_GOT, R_GOT_OFF, R_MIPS_GOT_LOCAL_PAGE, R_MIPS_GOT_OFF,
                R_MIPS_GOT_OFF32, R_AARCH64_GOT_PAGE_PC, R_GOT_PC, R_GOTPLT,
-               R_AARCH64_GOT_PAGE>(expr);
+               R_AARCH64_GOT_PAGE, R_LOONGARCH_GOT, R_LOONGARCH_GOT_PAGE_PC>(
+      expr);
 }
 
 // True if this expression is of the form Sym - X, where X is a position in the
 // file (PC, or GOT for example).
 static bool isRelExpr(RelExpr expr) {
   return oneof<R_PC, R_GOTREL, R_GOTPLTREL, R_MIPS_GOTREL, R_PPC64_CALL,
                R_PPC64_RELAX_TOC, R_AARCH64_PAGE_PC, R_RELAX_GOT_PC,
-               R_RISCV_PC_INDIRECT, R_PPC64_RELAX_GOT_PC>(expr);
+               R_RISCV_PC_INDIRECT, R_PPC64_RELAX_GOT_PC, R_LOONGARCH_PAGE_PC>(
+      expr);
 }
 
-
 static RelExpr toPlt(RelExpr expr) {
   switch (expr) {
+  case R_LOONGARCH_PAGE_PC:
+    return R_LOONGARCH_PLT_PAGE_PC;
   case R_PPC64_CALL:
     return R_PPC64_CALL_PLT;
   case R_PC:
     return R_PLT_PC;
   case R_ABS:
     return R_PLT;
   default:
     return expr;
   }
 }
 
 static RelExpr fromPlt(RelExpr expr) {
   // We decided not to use a plt. Optimize a reference to the plt to a
   // reference to the symbol itself.
   switch (expr) {
   case R_PLT_PC:
   case R_PPC32_PLTREL:
     return R_PC;
+  case R_LOONGARCH_PLT_PAGE_PC:
+    return R_LOONGARCH_PAGE_PC;
   case R_PPC64_CALL_PLT:
     return R_PPC64_CALL;
   case R_PLT:
     return R_ABS;
   case R_PLT_GOTPLT:
     return R_GOTPLTREL;
   default:
     return expr;

 bool RelocationScanner::isStaticLinkTimeConstant(RelExpr e, RelType type,
                                                  const Symbol &sym,
                                                  uint64_t relOff) const {
   // These expressions always compute a constant
   if (oneof<R_GOTPLT, R_GOT_OFF, R_RELAX_HINT, R_MIPS_GOT_LOCAL_PAGE,
             R_MIPS_GOTREL, R_MIPS_GOT_OFF, R_MIPS_GOT_OFF32, R_MIPS_GOT_GP_PC,
             R_AARCH64_GOT_PAGE_PC, R_GOT_PC, R_GOTONLY_PC, R_GOTPLTONLY_PC,
             R_PLT_PC, R_PLT_GOTPLT, R_PPC32_PLTREL, R_PPC64_CALL_PLT,
-            R_PPC64_RELAX_TOC, R_RISCV_ADD, R_AARCH64_GOT_PAGE>(e))
+            R_PPC64_RELAX_TOC, R_RISCV_ADD, R_AARCH64_GOT_PAGE,
+            R_LOONGARCH_PLT_PAGE_PC, R_LOONGARCH_GOT, R_LOONGARCH_GOT_PAGE_PC>(
+          e))
     return true;
 
   // These never do, except if the entire file is position dependent or if
   // only the low bits are used.
   if (e == R_GOT || e == R_PLT)
     return target->usesOnlyLowPageBits(type) || !config->isPic;
 
   if (sym.isPreemptible)
if (config->emachine == EM_MIPS) {
       // MIPS ABI has special rules to process GOT entries and doesn't
       // require relocation entries for them. A special case is TLS
       // relocations. In that case dynamic loader applies dynamic
       // relocations to initialize TLS GOT entries.
       // See "Global Offset Table" in Chapter 5 in the following document
       // for detailed description:
       // ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
       in.mipsGot->addEntry(*sec->file, sym, addend, expr);
+    } else if (config->emachine == EM_LOONGARCH) {
+      // Many LoongArch TLS relocs reuse the R_LOONGARCH_GOT type, in which case
+      // the NEEDS_GOT flag shouldn't get set.
+      if (!sym.isTls())
+        sym.setFlags(NEEDS_GOT);
     } else {
       sym.setFlags(NEEDS_GOT);
     }
   } else if (needsPlt(expr)) {
     sym.setFlags(NEEDS_PLT);
   } else if (LLVM_UNLIKELY(isIfunc)) {
     sym.setFlags(HAS_DIRECT_RELOC);
   }
void RelocationScanner::processAux(RelExpr expr, RelType type, uint64_t offset,
   //
   // For MIPS, we don't implement GNU ld's DW_EH_PE_absptr to DW_EH_PE_pcrel
   // conversion. We still emit a dynamic relocation.
   bool canWrite = (sec->flags & SHF_WRITE) ||
                   !(config->zText ||
                     (isa<EhInputSection>(sec) && config->emachine != EM_MIPS));
   if (canWrite) {
     RelType rel = target->getDynRel(type);
-    if (expr == R_GOT || (rel == target->symbolicRel && !sym.isPreemptible)) {
+    if (oneof<R_GOT, R_LOONGARCH_GOT>(expr) ||
+        (rel == target->symbolicRel && !sym.isPreemptible)) {
       addRelativeReloc<true>(*sec, offset, sym, addend, expr, type);
       return;
     } else if (rel != 0) {
       if (config->emachine == EM_MIPS && rel == target->symbolicRel)
         rel = target->relativeRel;
       std::lock_guard<std::mutex> lock(relocMutex);
       sec->getPartition().relaDyn->addSymbolReloc(rel, *sec, offset, sym,
                                                   addend, type);
if (oneof<R_AARCH64_TLSDESC_PAGE, R_TLSDESC, R_TLSDESC_CALL, R_TLSDESC_PC,
       config->shared) {
     if (expr != R_TLSDESC_CALL) {
       sym.setFlags(NEEDS_TLSDESC);
       c.addReloc({expr, type, offset, addend, &sym});
     }
     return 1;
   }
 
-  // ARM, Hexagon and RISC-V do not support GD/LD to IE/LE relaxation.  For
-  // PPC64, if the file has missing R_PPC64_TLSGD/R_PPC64_TLSLD, disable
+  // ARM, Hexagon, LoongArch and RISC-V do not support GD/LD to IE/LE
+  // relaxation.
+  // For PPC64, if the file has missing R_PPC64_TLSGD/R_PPC64_TLSLD, disable
   // relaxation as well.
   bool toExecRelax = !config->shared && config->emachine != EM_ARM &&
                      config->emachine != EM_HEXAGON &&
+                     config->emachine != EM_LOONGARCH &&
                      config->emachine != EM_RISCV &&
                      !c.file->ppc64DisableTLSRelax;
 
   // If we are producing an executable and the symbol is non-preemptable, it
   // must be defined and the code sequence can be relaxed to use Local-Exec.
   //
   // ARM and RISC-V do not support any relaxations for TLS relocations, however,
   // we can omit the DTPMOD dynamic relocations and resolve them at link time
   // because them are always 1. This may be necessary for static linking as
   // DTPMOD may not be expected at load time.
   bool isLocalInExecutable = !sym.isPreemptible && !config->shared;
 
   // Local Dynamic is for access to module local TLS variables, while still
   // being suitable for being dynamically loaded via dlopen. GOT[e0] is the
   // module index, with a special value of 0 for the current module. GOT[e1] is
   // unused. There only needs to be one module index entry.
-  if (oneof<R_TLSLD_GOT, R_TLSLD_GOTPLT, R_TLSLD_PC, R_TLSLD_HINT>(
-          expr)) {
+  if (oneof<R_TLSLD_GOT, R_TLSLD_GOTPLT, R_TLSLD_PC, R_TLSLD_HINT>(expr)) {
     // Local-Dynamic relocs can be relaxed to Local-Exec.
     if (toExecRelax) {
       c.addReloc({target->adjustTlsExpr(type, R_RELAX_TLS_LD_TO_LE), type,
                   offset, addend, &sym});
       return target->getTlsGdRelaxSkip(type);
     }
     if (expr == R_TLSLD_HINT)
       return 1;
static unsigned handleTlsRelocation(RelType type, Symbol &sym,
   // thread pointer is stored in the got. This cannot be relaxed to Local-Exec.
   if (expr == R_TLSLD_GOT_OFF) {
     sym.setFlags(NEEDS_GOT_DTPREL);
     c.addReloc({expr, type, offset, addend, &sym});
     return 1;
   }
 
   if (oneof<R_AARCH64_TLSDESC_PAGE, R_TLSDESC, R_TLSDESC_CALL, R_TLSDESC_PC,
-            R_TLSDESC_GOTPLT, R_TLSGD_GOT, R_TLSGD_GOTPLT, R_TLSGD_PC>(expr)) {
+            R_TLSDESC_GOTPLT, R_TLSGD_GOT, R_TLSGD_GOTPLT, R_TLSGD_PC,
+            R_LOONGARCH_GOT_TLSGD_PAGE_PC>(expr)) {
     if (!toExecRelax) {
       sym.setFlags(NEEDS_TLSGD);
       c.addReloc({expr, type, offset, addend, &sym});
       return 1;
     }
 
     // Global-Dynamic relocs can be relaxed to Initial-Exec or Local-Exec
     // depending on the symbol being locally defined or not.
     if (sym.isPreemptible) {
       sym.setFlags(NEEDS_TLSGD_TO_IE);
       c.addReloc({target->adjustTlsExpr(type, R_RELAX_TLS_GD_TO_IE), type,
                   offset, addend, &sym});
     } else {
       c.addReloc({target->adjustTlsExpr(type, R_RELAX_TLS_GD_TO_LE), type,
                   offset, addend, &sym});
     }
     return target->getTlsGdRelaxSkip(type);
   }
 
-  if (oneof<R_GOT, R_GOTPLT, R_GOT_PC, R_AARCH64_GOT_PAGE_PC, R_GOT_OFF,
-            R_TLSIE_HINT>(expr)) {
+  if (oneof<R_GOT, R_GOTPLT, R_GOT_PC, R_AARCH64_GOT_PAGE_PC,
+            R_LOONGARCH_GOT_TLSIE_PAGE_PC, R_GOT_OFF, R_TLSIE_HINT>(expr)) {
     ctx.hasTlsIe.store(true, std::memory_order_relaxed);
     // Initial-Exec relocs can be relaxed to Local-Exec if the symbol is locally
     // defined.
     if (toExecRelax && isLocalInExecutable) {
       c.addReloc({R_RELAX_TLS_IE_TO_LE, type, offset, addend, &sym});
     } else if (expr != R_TLSIE_HINT) {
       sym.setFlags(NEEDS_TLSIE);
       // R_GOT needs a relative relocation for PIC on i386 and Hexagon.

lld/ELF/ScriptParser.cpp

return StringSwitch<std::pair<ELFKind, uint16_t>>(s)
       .Case("elf32-tradlittlemips", {ELF32LEKind, EM_MIPS})
       .Case("elf32-ntradlittlemips", {ELF32LEKind, EM_MIPS})
       .Case("elf64-tradbigmips", {ELF64BEKind, EM_MIPS})
       .Case("elf64-tradlittlemips", {ELF64LEKind, EM_MIPS})
       .Case("elf32-littleriscv", {ELF32LEKind, EM_RISCV})
       .Case("elf64-littleriscv", {ELF64LEKind, EM_RISCV})
       .Case("elf64-sparc", {ELF64BEKind, EM_SPARCV9})
       .Case("elf32-msp430", {ELF32LEKind, EM_MSP430})
+      .Case("elf32-loongarch", {ELF32LEKind, EM_LOONGARCH})
+      .Case("elf64-loongarch", {ELF64LEKind, EM_LOONGARCH})
       .Default({ELFNoneKind, EM_NONE});
 }
 
 // Parse OUTPUT_FORMAT(bfdname) or OUTPUT_FORMAT(default, big, little). Choose
 // big if -EB is specified, little if -EL is specified, or default if neither is
 // specified.
 void ScriptParser::readOutputFormat() {
   expect("(");

lld/ELF/Target.h

protected:
   uint64_t defaultImageBase = 0x10000;
 };
 
 TargetInfo *getAArch64TargetInfo();
 TargetInfo *getAMDGPUTargetInfo();
 TargetInfo *getARMTargetInfo();
 TargetInfo *getAVRTargetInfo();
 TargetInfo *getHexagonTargetInfo();
+TargetInfo *getLoongArchTargetInfo();
 TargetInfo *getMSP430TargetInfo();
 TargetInfo *getPPC64TargetInfo();
 TargetInfo *getPPCTargetInfo();
 TargetInfo *getRISCVTargetInfo();
 TargetInfo *getSPARCV9TargetInfo();
 TargetInfo *getX86TargetInfo();
 TargetInfo *getX86_64TargetInfo();
 template <class ELFT> TargetInfo *getMipsTargetInfo();

 // Write a prefixed instruction, which is a 4-byte prefix followed by a 4-byte
 // instruction (regardless of endianness). Therefore, the prefix is always in
 // lower memory than the instruction.
 void writePrefixedInstruction(uint8_t *loc, uint64_t insn);
 
 void addPPC64SaveRestore();
 uint64_t getPPC64TocBase();
 uint64_t getAArch64Page(uint64_t expr);
+uint64_t getLoongArchPageOffset(uint64_t dest, uint64_t pc);
 void riscvFinalizeRelax(int passes);
 void mergeRISCVAttributesSections();
 
 LLVM_LIBRARY_VISIBILITY extern const TargetInfo *target;
 TargetInfo *getTarget();
 
 template <class ELFT> bool isMipsPIC(const Defined *sym);
 

lld/ELF/Target.cpp

TargetInfo *elf::getTarget() {
   case EM_AMDGPU:
     return getAMDGPUTargetInfo();
   case EM_ARM:
     return getARMTargetInfo();
   case EM_AVR:
     return getAVRTargetInfo();
   case EM_HEXAGON:
     return getHexagonTargetInfo();
+  case EM_LOONGARCH:
+    return getLoongArchTargetInfo();
   case EM_MIPS:
     switch (config->ekind) {
     case ELF32LEKind:
       return getMipsTargetInfo<ELF32LE>();
     case ELF32BEKind:
       return getMipsTargetInfo<ELF32BE>();
     case ELF64LEKind:
       return getMipsTargetInfo<ELF64LE>();

lld/test/ELF/loongarch-abs64.s

+# REQUIRES: loongarch
+
+# RUN: llvm-mc --filetype=obj --triple=loongarch64-unknown-elf %s -o %t.la64.o
+
+# RUN: ld.lld %t.la64.o --defsym foo=0 --defsym bar=42 -o %t.la64.1
+# RUN: llvm-objdump -d %t.la64.1 | FileCheck --check-prefix=CASE1 %s
+# CASE1:      04 00 00 14   lu12i.w $a0, 0
+# CASE1-NEXT: 84 00 80 03   ori     $a0, $a0, 0
+# CASE1-NEXT: 04 00 00 16   lu32i.d $a0, 0
+# CASE1-NEXT: 84 00 00 03   lu52i.d $a0, $a0, 0
+# CASE1-NEXT: 05 00 00 14   lu12i.w $a1, 0
+# CASE1-NEXT: a5 a8 80 03   ori     $a1, $a1, 42
+# CASE1-NEXT: 05 00 00 16   lu32i.d $a1, 0
+# CASE1-NEXT: a5 00 00 03   lu52i.d $a1, $a1, 0
+
+# RUN: ld.lld %t.la64.o --defsym foo=0x12345678 --defsym bar=0x87654321 -o %t.la64.2
+# RUN: llvm-objdump -d %t.la64.2 | FileCheck --check-prefix=CASE2 %s
+# CASE2:      a4 68 24 14   lu12i.w $a0, 74565
+# CASE2-NEXT: 84 e0 99 03   ori     $a0, $a0, 1656
+# CASE2-NEXT: 04 00 00 16   lu32i.d $a0, 0
+# CASE2-NEXT: 84 00 00 03   lu52i.d $a0, $a0, 0
+# CASE2-NEXT: 85 ca 0e 15   lu12i.w $a1, -493996
+# CASE2-NEXT: a5 84 8c 03   ori     $a1, $a1, 801
+# CASE2-NEXT: 05 00 00 16   lu32i.d $a1, 0
+# CASE2-NEXT: a5 00 00 03   lu52i.d $a1, $a1, 0
+
+# RUN: ld.lld %t.la64.o --defsym foo=0x12345fedcb678 --defsym bar=0xfedcb12345000 -o %t.la64.3
+# RUN: llvm-objdump -d %t.la64.3 | FileCheck --check-prefix=CASE3 %s
+# CASE3:      64 b9 fd 15   lu12i.w $a0, -4661
+# CASE3-NEXT: 84 e0 99 03   ori     $a0, $a0, 1656
+# CASE3-NEXT: a4 68 24 16   lu32i.d $a0, 74565
+# CASE3-NEXT: 84 00 00 03   lu52i.d $a0, $a0, 0
+# CASE3-NEXT: a5 68 24 14   lu12i.w $a1, 74565
+# CASE3-NEXT: a5 00 80 03   ori     $a1, $a1, 0
+# CASE3-NEXT: 65 b9 fd 17   lu32i.d $a1, -4661
+# CASE3-NEXT: a5 00 00 03   lu52i.d $a1, $a1, 0
+
+# RUN: ld.lld %t.la64.o --defsym foo=0xfffffeeeeeddd --defsym bar=0xfff00000f1111222 -o %t.la64.4
+# RUN: llvm-objdump -d %t.la64.4 | FileCheck --check-prefix=CASE4 %s
+# CASE4:      c4 dd dd 15   lu12i.w $a0, -69906
+# CASE4-NEXT: 84 74 b7 03   ori     $a0, $a0, 3549
+# CASE4-NEXT: e4 ff ff 17   lu32i.d $a0, -1
+# CASE4-NEXT: 84 00 00 03   lu52i.d $a0, $a0, 0
+# CASE4-NEXT: 25 22 e2 15   lu12i.w $a1, -61167
+# CASE4-NEXT: a5 88 88 03   ori     $a1, $a1, 546
+# CASE4-NEXT: 05 00 00 16   lu32i.d $a1, 0
+# CASE4-NEXT: a5 fc 3f 03   lu52i.d $a1, $a1, -1
+
+.global _start
+
+_start:
+    lu12i.w $a0, %abs_hi20(foo)
+    ori     $a0, $a0, %abs_lo12(foo)
+    lu32i.d $a0, %abs64_lo20(foo)
+    lu52i.d $a0, $a0, %abs64_hi12(foo)
+
+    lu12i.w $a1, %abs_hi20(bar)
+    ori     $a1, $a1, %abs_lo12(bar)
+    lu32i.d $a1, %abs64_lo20(bar)
+    lu52i.d $a1, $a1, %abs64_hi12(bar)

lld/test/ELF/loongarch-branch-b16.s

+# REQUIRES: loongarch
+
+# RUN: llvm-mc --filetype=obj --triple=loongarch32-unknown-elf %s -o %t.la32.o
+# RUN: llvm-mc --filetype=obj --triple=loongarch64-unknown-elf %s -o %t.la64.o
+
+# RUN: ld.lld %t.la32.o --defsym foo=_start+4 --defsym bar=_start -o %t.la32
+# RUN: ld.lld %t.la64.o --defsym foo=_start+4 --defsym bar=_start -o %t.la64
+# RUN: llvm-objdump -d %t.la32 | FileCheck %s --check-prefix=CHECK-32
+# RUN: llvm-objdump -d %t.la64 | FileCheck %s --check-prefix=CHECK-64
+# CHECK-32: 00 04 00 58   beq     $zero, $zero, 4
+# CHECK-32: 00 fc ff 5f   bne     $zero, $zero, -4
+# CHECK-64: 00 04 00 58   beq     $zero, $zero, 4
+# CHECK-64: 00 fc ff 5f   bne     $zero, $zero, -4
+
+# RUN: ld.lld %t.la32.o --defsym foo=_start+0x1fffc --defsym bar=_start+4-0x20000 -o %t.la32.limits
+# RUN: ld.lld %t.la64.o --defsym foo=_start+0x1fffc --defsym bar=_start+4-0x20000 -o %t.la64.limits
+# RUN: llvm-objdump -d %t.la32.limits | FileCheck --check-prefix=LIMITS-32 %s
+# RUN: llvm-objdump -d %t.la64.limits | FileCheck --check-prefix=LIMITS-64 %s
+# LIMITS-32:      00 fc ff 59   beq     $zero, $zero, 131068
+# LIMITS-32-NEXT: 00 00 00 5e   bne     $zero, $zero, -131072
+# LIMITS-64:      00 fc ff 59   beq     $zero, $zero, 131068
+# LIMITS-64-NEXT: 00 00 00 5e   bne     $zero, $zero, -131072
+
+# RUN: not ld.lld %t.la32.o --defsym foo=_start+0x20000 --defsym bar=_start+4-0x20004 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s
+# RUN: not ld.lld %t.la64.o --defsym foo=_start+0x20000 --defsym bar=_start+4-0x20004 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s
+# ERROR-RANGE: relocation R_LARCH_B16 out of range: 131072 is not in [-131072, 131071]; references 'foo'
+# ERROR-RANGE: relocation R_LARCH_B16 out of range: -131076 is not in [-131072, 131071]; references 'bar'
+
+# RUN: not ld.lld %t.la32.o --defsym foo=_start+1 --defsym bar=_start-1 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-ALIGN-1 %s
+# RUN: not ld.lld %t.la64.o --defsym foo=_start+1 --defsym bar=_start-1 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-ALIGN-1 %s
+# ERROR-ALIGN-1: improper alignment for relocation R_LARCH_B16: 0xFFFFFFFFFFFFFFFB is not aligned to 4 bytes
+
+# RUN: not ld.lld %t.la32.o --defsym foo=_start+2 --defsym bar=_start-2 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-ALIGN-2 %s
+# RUN: not ld.lld %t.la64.o --defsym foo=_start+2 --defsym bar=_start-2 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-ALIGN-2 %s
+# ERROR-ALIGN-2: improper alignment for relocation R_LARCH_B16: 0xFFFFFFFFFFFFFFFA is not aligned to 4 bytes
+
+.global _start
+_start:
+     beq $zero, $zero, foo
+     bne $zero, $zero, bar

lld/test/ELF/loongarch-branch-b21.s

+# REQUIRES: loongarch
+
+# RUN: llvm-mc --filetype=obj --triple=loongarch32-unknown-elf %s -o %t.la32.o
+# RUN: llvm-mc --filetype=obj --triple=loongarch64-unknown-elf %s -o %t.la64.o
+
+# RUN: ld.lld %t.la32.o --defsym foo=_start+4 --defsym bar=_start -o %t.la32
+# RUN: ld.lld %t.la64.o --defsym foo=_start+4 --defsym bar=_start -o %t.la64
+# RUN: llvm-objdump -d %t.la32 | FileCheck %s --check-prefix=CHECK-32
+# RUN: llvm-objdump -d %t.la64 | FileCheck %s --check-prefix=CHECK-64
+# CHECK-32: e0 07 00 40   beqz    $s8, 4
+# CHECK-32: ff ff ff 47   bnez    $s8, -4
+# CHECK-64: e0 07 00 40   beqz    $s8, 4
+# CHECK-64: ff ff ff 47   bnez    $s8, -4
+
+# RUN: ld.lld %t.la32.o --defsym foo=_start+0x3ffffc --defsym bar=_start+4-0x400000 -o %t.la32.limits
+# RUN: ld.lld %t.la64.o --defsym foo=_start+0x3ffffc --defsym bar=_start+4-0x400000 -o %t.la64.limits
+# RUN: llvm-objdump -d %t.la32.limits | FileCheck --check-prefix=LIMITS-32 %s
+# RUN: llvm-objdump -d %t.la64.limits | FileCheck --check-prefix=LIMITS-64 %s
+# LIMITS-32:      ef ff ff 43   beqz    $s8, 4194300
+# LIMITS-32-NEXT: f0 03 00 44   bnez    $s8, -4194304
+# LIMITS-64:      ef ff ff 43   beqz    $s8, 4194300
+# LIMITS-64-NEXT: f0 03 00 44   bnez    $s8, -4194304
+
+# RUN: not ld.lld %t.la32.o --defsym foo=_start+0x400000 --defsym bar=_start+4-0x400004 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s
+# RUN: not ld.lld %t.la64.o --defsym foo=_start+0x400000 --defsym bar=_start+4-0x400004 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s
+# ERROR-RANGE: relocation R_LARCH_B21 out of range: 4194304 is not in [-4194304, 4194303]; references 'foo'
+# ERROR-RANGE: relocation R_LARCH_B21 out of range: -4194308 is not in [-4194304, 4194303]; references 'bar'
+
+# RUN: not ld.lld %t.la32.o --defsym foo=_start+1 --defsym bar=_start-1 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-ALIGN-1 %s
+# RUN: not ld.lld %t.la64.o --defsym foo=_start+1 --defsym bar=_start-1 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-ALIGN-1 %s
+# ERROR-ALIGN-1: improper alignment for relocation R_LARCH_B21: 0xFFFFFFFFFFFFFFFB is not aligned to 4 bytes
+
+# RUN: not ld.lld %t.la32.o --defsym foo=_start+2 --defsym bar=_start-2 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-ALIGN-2 %s
+# RUN: not ld.lld %t.la64.o --defsym foo=_start+2 --defsym bar=_start-2 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-ALIGN-2 %s
+# ERROR-ALIGN-2: improper alignment for relocation R_LARCH_B21: 0xFFFFFFFFFFFFFFFA is not aligned to 4 bytes
+
+.global _start
+_start:
+     beqz $s8, foo
+     bnez $s8, bar

lld/test/ELF/loongarch-branch-b26.s

+# REQUIRES: loongarch
+
+# RUN: llvm-mc --filetype=obj --triple=loongarch32-unknown-elf %s -o %t.la32.o
+# RUN: llvm-mc --filetype=obj --triple=loongarch64-unknown-elf %s -o %t.la64.o
+
+# RUN: ld.lld %t.la32.o --defsym foo=_start+4 --defsym bar=_start -o %t.la32
+# RUN: ld.lld %t.la64.o --defsym foo=_start+4 --defsym bar=_start -o %t.la64
+# RUN: llvm-objdump -d %t.la32 | FileCheck %s --check-prefix=CHECK-32
+# RUN: llvm-objdump -d %t.la64 | FileCheck %s --check-prefix=CHECK-64
+# CHECK-32: 00 04 00 50   b       4
+# CHECK-32: ff ff ff 57   bl      -4
+# CHECK-64: 00 04 00 50   b       4
+# CHECK-64: ff ff ff 57   bl      -4
+
+# RUN: ld.lld %t.la32.o --defsym foo=_start+0x7fffffc --defsym bar=_start+4-0x8000000 -o %t.la32.limits
+# RUN: ld.lld %t.la64.o --defsym foo=_start+0x7fffffc --defsym bar=_start+4-0x8000000 -o %t.la64.limits
+# RUN: llvm-objdump -d %t.la32.limits | FileCheck --check-prefix=LIMITS-32 %s
+# RUN: llvm-objdump -d %t.la64.limits | FileCheck --check-prefix=LIMITS-64 %s
+# LIMITS-32:      ff fd ff 53   b       134217724
+# LIMITS-32-NEXT: 00 02 00 54   bl      -134217728
+# LIMITS-64:      ff fd ff 53   b       134217724
+# LIMITS-64-NEXT: 00 02 00 54   bl      -134217728
+
+# RUN: not ld.lld %t.la32.o --defsym foo=_start+0x8000000 --defsym bar=_start+4-0x8000004 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s
+# RUN: not ld.lld %t.la64.o --defsym foo=_start+0x8000000 --defsym bar=_start+4-0x8000004 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s
+# ERROR-RANGE: relocation R_LARCH_B26 out of range: 134217728 is not in [-134217728, 134217727]; references 'foo'
+# ERROR-RANGE: relocation R_LARCH_B26 out of range: -134217732 is not in [-134217728, 134217727]; references 'bar'
+
+# RUN: not ld.lld %t.la32.o --defsym foo=_start+1 --defsym bar=_start-1 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-ALIGN-1 %s
+# RUN: not ld.lld %t.la64.o --defsym foo=_start+1 --defsym bar=_start-1 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-ALIGN-1 %s
+# ERROR-ALIGN-1: improper alignment for relocation R_LARCH_B26: 0xFFFFFFFFFFFFFFFB is not aligned to 4 bytes
+
+# RUN: not ld.lld %t.la32.o --defsym foo=_start+2 --defsym bar=_start-2 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-ALIGN-2 %s
+# RUN: not ld.lld %t.la64.o --defsym foo=_start+2 --defsym bar=_start-2 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-ALIGN-2 %s
+# ERROR-ALIGN-2: improper alignment for relocation R_LARCH_B26: 0xFFFFFFFFFFFFFFFA is not aligned to 4 bytes
+
+.global _start
+_start:
+     b foo
+     bl bar

lld/test/ELF/loongarch-elf-flags.s

+# REQUIRES: loongarch
+
+# RUN: echo -n "BLOB" > %t.binary
+# RUN: ld.lld -m elf64loongarch -b binary %t.binary -o %t.out
+# RUN: llvm-readobj -h %t.out | FileCheck %s
+
+# CHECK:      Flags [
+# CHECK-NEXT: ]

lld/test/ELF/loongarch-pc-aligned.s

+# REQUIRES: loongarch
+# RUN: rm -rf %t && split-file %s %t
+
+# RUN: llvm-mc --filetype=obj --triple=loongarch32 %t/a.s -o %t/a.la32.o
+# RUN: llvm-mc --filetype=obj --triple=loongarch64 %t/a.s -o %t/a.la64.o
+# RUN: llvm-mc --filetype=obj --triple=loongarch64 %t/extreme.s -o %t/extreme.o
+
+# RUN: ld.lld %t/a.la32.o -T %t/case1.t -o %t/case1.la32
+# RUN: ld.lld %t/a.la64.o -T %t/case1.t -o %t/case1.la64
+# RUN: llvm-objdump -d --no-show-raw-insn %t/case1.la32 | FileCheck %s --check-prefix=CASE1
+# RUN: llvm-objdump -d --no-show-raw-insn %t/case1.la64 | FileCheck %s --check-prefix=CASE1
+# CASE1:      pcalau12i $a0, 0
+# CASE1-NEXT: ld.w      $a0, $a0, 0
+#--- case1.t
+SECTIONS {
+ .rodata 0x1000: { *(.rodata) }
+ .text   0x1ffc: { *(.text) }
+}
+
+# RUN: ld.lld %t/a.la32.o -T %t/case2.t -o %t/case2.la32
+# RUN: ld.lld %t/a.la64.o -T %t/case2.t -o %t/case2.la64
+# RUN: llvm-objdump -d --no-show-raw-insn %t/case2.la32 | FileCheck %s --check-prefix=CASE2
+# RUN: llvm-objdump -d --no-show-raw-insn %t/case2.la64 | FileCheck %s --check-prefix=CASE2
+# CASE2:      pcalau12i $a0, -1
+# CASE2-NEXT: ld.w      $a0, $a0, 0
+#--- case2.t
+SECTIONS {
+ .rodata 0x1000: { *(.rodata) }
+ .text   0x2000: { *(.text) }
+}
+
+# RUN: ld.lld %t/a.la32.o -T %t/case3.t -o %t/case3.la32
+# RUN: ld.lld %t/a.la64.o -T %t/case3.t -o %t/case3.la64
+# RUN: llvm-objdump -d --no-show-raw-insn %t/case3.la32 | FileCheck %s --check-prefix=CASE3
+# RUN: llvm-objdump -d --no-show-raw-insn %t/case3.la64 | FileCheck %s --check-prefix=CASE3
+# CASE3:      pcalau12i $a0, -1
+# CASE3-NEXT: ld.w      $a0, $a0, 2047
+#--- case3.t
+SECTIONS {
+ .rodata 0x17ff: { *(.rodata) }
+ .text   0x2000: { *(.text) }
+}
+
+# RUN: ld.lld %t/a.la32.o -T %t/case4.t -o %t/case4.la32
+# RUN: ld.lld %t/a.la64.o -T %t/case4.t -o %t/case4.la64
+# RUN: llvm-objdump -d --no-show-raw-insn %t/case4.la32 | FileCheck %s --check-prefix=CASE4
+# RUN: llvm-objdump -d --no-show-raw-insn %t/case4.la64 | FileCheck %s --check-prefix=CASE4
+# CASE4:      pcalau12i $a0, 0
+# CASE4-NEXT: ld.w      $a0, $a0, -2048
+#--- case4.t
+SECTIONS {
+ .rodata 0x1800: { *(.rodata) }
+ .text   0x2000: { *(.text) }
+}
+
+# RUN: ld.lld %t/a.la32.o -T %t/case5.t -o %t/case5.la32
+# RUN: ld.lld %t/a.la64.o -T %t/case5.t -o %t/case5.la64
+# RUN: llvm-objdump -d --no-show-raw-insn %t/case5.la32 | FileCheck %s --check-prefix=CASE5
+# RUN: llvm-objdump -d --no-show-raw-insn %t/case5.la64 | FileCheck %s --check-prefix=CASE5
+# CASE5:      pcalau12i $a0, 1
+# CASE5-NEXT: ld.w      $a0, $a0, 4
+#--- case5.t
+SECTIONS {
+ .text   0x001ffc: { *(.text) }
+ .rodata 0x002004: { *(.rodata) }
+}
+
+# RUN: ld.lld %t/a.la32.o -T %t/case6.t -o %t/case6.la32
+# RUN: ld.lld %t/a.la64.o -T %t/case6.t -o %t/case6.la64
+# RUN: llvm-objdump -d --no-show-raw-insn %t/case6.la32 | FileCheck %s --check-prefix=CASE6
+# RUN: llvm-objdump -d --no-show-raw-insn %t/case6.la64 | FileCheck %s --check-prefix=CASE6
+# CASE6:      pcalau12i $a0, 2
+# CASE6-NEXT: ld.w      $a0, $a0, -2048
+#--- case6.t
+SECTIONS {
+ .text   0x001ffc: { *(.text) }
+ .rodata 0x002800: { *(.rodata) }
+}
+
+# RUN: ld.lld %t/a.la32.o -T %t/case7.t -o %t/case7.la32
+# RUN: ld.lld %t/a.la64.o -T %t/case7.t -o %t/case7.la64
+# RUN: llvm-objdump -d --no-show-raw-insn %t/case7.la32 | FileCheck %s --check-prefix=CASE7
+# RUN: llvm-objdump -d --no-show-raw-insn %t/case7.la64 | FileCheck %s --check-prefix=CASE7
+# CASE7:      pcalau12i $a0, 524287
+# CASE7-NEXT: ld.w      $a0, $a0, 291
+#--- case7.t
+SECTIONS {
+ .text   0x0: { *(.text) }
+ .rodata 0x7ffff123: { *(.rodata) }
+}
+
+# RUN: ld.lld %t/a.la32.o -T %t/case8.t -o %t/case8.la32
+# RUN: ld.lld %t/a.la64.o -T %t/case8.t -o %t/case8.la64
+# RUN: llvm-objdump -d --no-show-raw-insn %t/case8.la32 | FileCheck %s --check-prefix=CASE8
+# RUN: llvm-objdump -d --no-show-raw-insn %t/case8.la64 | FileCheck %s --check-prefix=CASE8
+# CASE8:      pcalau12i $a0, -524288
+# CASE8-NEXT: ld.w      $a0, $a0, -1348
+#--- case8.t
+SECTIONS {
+ .text   0x0: { *(.text) }
+ .rodata 0x7ffffabc: { *(.rodata) }
+}
+
+# RUN: ld.lld %t/a.la32.o -T %t/case9.t -o %t/case9.la32
+# RUN: ld.lld %t/a.la64.o -T %t/case9.t -o %t/case9.la64
+# RUN: llvm-objdump -d --no-show-raw-insn %t/case9.la32 | FileCheck %s --check-prefix=CASE9
+# RUN: llvm-objdump -d --no-show-raw-insn %t/case9.la64 | FileCheck %s --check-prefix=CASE9
+# CASE9:      pcalau12i $a0, -524288
+# CASE9-NEXT: ld.w      $a0, $a0, 291
+#--- case9.t
+SECTIONS {
+ .rodata 0x123: { *(.rodata) }
+ .text   0x80000000: { *(.text) }
+}
+
+# RUN: ld.lld %t/extreme.o -T %t/extreme1.t -o %t/extreme1
+# RUN: llvm-objdump -d --no-show-raw-insn %t/extreme1 | FileCheck %s --check-prefix=EXTREME1
+# EXTREME1:      addi.d    $t0, $zero, 291
+# EXTREME1-NEXT: lu32i.d   $t0, -284281
+# EXTREME1-NEXT: lu52i.d   $t0, $t0, -292
+# EXTREME1-NEXT: pcalau12i $t1, 414771
+#--- extreme1.t
+SECTIONS {
+ .rodata 0x123: { *(.rodata) }
+ .text   0x123456789abcdef0: { *(.text) }
+}
+
+# RUN: ld.lld %t/extreme.o -T %t/extreme2.t -o %t/extreme2
+# RUN: llvm-objdump -d --no-show-raw-insn %t/extreme2 | FileCheck %s --check-prefix=EXTREME2
+# EXTREME2:      addi.d    $t0, $zero, -820
+# EXTREME2-NEXT: lu32i.d   $t0, -69907
+# EXTREME2-NEXT: lu52i.d   $t0, $t0, 2047
+# EXTREME2-NEXT: pcalau12i $t1, -139810
+#--- extreme2.t
+SECTIONS {
+ .text   0x0: { *(.text) }
+ .rodata 0x7ffeeeeedddddccc: { *(.rodata) }
+}
+
+# RUN: ld.lld %t/extreme.o -T %t/extreme3.t -o %t/extreme3
+# RUN: llvm-objdump -d --no-show-raw-insn %t/extreme3 | FileCheck %s --check-prefix=EXTREME3
+# EXTREME3:      addi.d    $t0, $zero, -820
+# EXTREME3-NEXT: lu32i.d   $t0, -69906
+# EXTREME3-NEXT: lu52i.d   $t0, $t0, -2048
+# EXTREME3-NEXT: pcalau12i $t1, -139810
+#--- extreme3.t
+SECTIONS {
+ .text   0x0: { *(.text) }
+ .rodata 0x800eeeeedddddccc: { *(.rodata) }
+}
+
+#--- a.s
+.rodata
+x:
+.word 10
+.text
+.global _start
+_start:
+  pcalau12i $a0, %pc_hi20(x)
+  ld.w      $a0, $a0, %pc_lo12(x)
+
+#--- extreme.s
+.rodata
+x:
+.word 10
+.text
+.global _start
+_start:
+  addi.d    $t0, $zero, %pc_lo12(x)
+  lu32i.d   $t0, %pc64_lo20(x)
+  lu52i.d   $t0, $t0, %pc64_hi12(x)
+  pcalau12i $t1, %pc_hi20(x)
+  add.d     $t0, $t0, $t1

lld/test/ELF/loongarch-pcala-lo12-jirl-shared-error.s

+# REQUIRES: loongarch
+
+# RUN: llvm-mc --filetype=obj --triple=loongarch32-unknown-elf %s -o %t.la32.o
+# RUN: llvm-mc --filetype=obj --triple=loongarch64-unknown-elf %s -o %t.la64.o
+
+# RUN: not ld.lld %t.la32.o -shared -o %t.la32.so 2>&1 | FileCheck %s
+# RUN: not ld.lld %t.la64.o -shared -o %t.la64.so 2>&1 | FileCheck %s
+
+.global foo
+foo:
+    pcalau12i   $t0, %pc_hi20(bar)
+    ld.w        $t0, $t0, %pc_lo12(bar)
+
+# CHECK: error: relocation R_LARCH_PCALA_LO12 cannot be used against symbol 'bar'; recompile with -fPIC

lld/test/ELF/loongarch-pcala-lo12-jirl-shared.s

+# REQUIRES: loongarch
+# RUN: rm -rf %t && split-file %s %t
+
+# RUN: llvm-mc --filetype=obj --triple=loongarch32-unknown-elf %t/a.s -o %t/a.la32.o
+# RUN: llvm-mc --filetype=obj --triple=loongarch64-unknown-elf %t/a.s -o %t/a.la64.o
+
+# RUN: ld.lld %t/a.la32.o -shared -T %t/a.t -o %t/a.la32.so
+# RUN: ld.lld %t/a.la64.o -shared -T %t/a.t -o %t/a.la64.so
+
+# RUN: llvm-objdump -d --no-show-raw-insn %t/a.la32.so | FileCheck --check-prefixes=DIS,DIS32 %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t/a.la64.so | FileCheck --check-prefixes=DIS,DIS64 %s
+
+## PLT should be present in this case.
+# DIS:        Disassembly of section .plt:
+# DIS:        <.plt>:
+# DIS:        234020:   pcaddu12i   $t3, 510
+# DIS32-NEXT: 234024:   ld.w    $t3, $t3, 84
+# DIS64-NEXT: 234024:   ld.d    $t3, $t3, 184
+# DIS-NEXT:   234028:   jirl    $t1, $t3, 0
+# DIS-NEXT:   23402c:   nop
+
+# DIS:      Disassembly of section .text:
+# DIS:      <foo>:
+# DIS-NEXT: nop
+# DIS-NEXT: nop
+# DIS-NEXT: nop
+# DIS-NEXT: pcalau12i $t0, -510
+# DIS-NEXT: jirl  $zero, $t0, 32
+
+
+#--- a.t
+SECTIONS {
+ .plt   0x234000: { *(.plt) }
+ .text  0x432000: { *(.text) }
+}
+
+#--- a.s
+.p2align 12
+.global foo
+foo:
+## The nops are for pushing the relocs off page boundary, to better see the
+## page-aligned semantics in action.
+    nop
+    nop
+    nop
+    ## The offsets should be -510 (0x234 - 0x432) and 32 (PLT header size + 0)
+    ## respectively.
+    pcalau12i   $t0, %pc_hi20(bar)
+    jirl        $zero, $t0, %pc_lo12(bar)

lld/test/ELF/loongarch-pcala-lo12-jirl.s

+# REQUIRES: loongarch
+
+# RUN: llvm-mc --filetype=obj --triple=loongarch32-unknown-elf %s -o %t.la32.o
+# RUN: llvm-mc --filetype=obj --triple=loongarch64-unknown-elf %s -o %t.la64.o
+
+# RUN: ld.lld %t.la32.o -o %t.la32
+# RUN: ld.lld %t.la64.o -o %t.la64
+# RUN: llvm-objdump -d --no-show-raw-insn %t.la32 | FileCheck %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t.la64 | FileCheck %s
+# CHECK:      pcalau12i $t0, -1
+# CHECK-NEXT: jirl  $ra, $t0, 564
+# CHECK-NEXT: pcalau12i $t0, 0
+# CHECK-NEXT: jirl  $zero, $t0, -1348
+
+## PLT shouldn't get generated in this case.
+# CHECK-NOT:  Disassembly of section .plt:
+
+.p2align 12
+.org 0x234
+.global foo
+foo:
+    li.w    $a0, 42
+    ret
+
+.org 0xabc
+.global bar
+bar:
+    li.w    $a7, 94
+    syscall 0
+
+.org 0x1000
+.global _start
+_start:
+## The nops are for pushing the relocs off page boundary, to better see the
+## page-aligned semantics in action.
+    nop
+    nop
+    nop
+    pcalau12i   $t0, %pc_hi20(foo)
+    jirl        $ra, $t0, %pc_lo12(foo)
+    pcalau12i   $t0, %pc_hi20(bar)
+    jirl        $zero, $t0, %pc_lo12(bar)

lld/test/ELF/loongarch-plt.s

+# REQUIRES: loongarch
+# RUN: echo '.globl bar, weak; .type bar,@function; .type weak,@function; bar: weak:' > %t1.s
+
+# RUN: llvm-mc --filetype=obj --triple=loongarch32 %t1.s -o %t1.32.o
+# RUN: ld.lld -shared %t1.32.o -soname=t1.32.so -o %t1.32.so
+# RUN: llvm-mc --filetype=obj --triple=loongarch32 %s -o %t.32.o
+# RUN: ld.lld %t.32.o %t1.32.so -z separate-code -o %t.32
+# RUN: llvm-readelf -S -s %t.32 | FileCheck --check-prefixes=SEC,NM %s
+# RUN: llvm-readobj -r %t.32 | FileCheck --check-prefix=RELOC32 %s
+# RUN: llvm-readelf -x .got.plt %t.32 | FileCheck --check-prefix=GOTPLT32 %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t.32 | FileCheck --check-prefixes=DIS,DIS32 %s
+
+# RUN: llvm-mc --filetype=obj --triple=loongarch64 %t1.s -o %t1.64.o
+# RUN: ld.lld -shared %t1.64.o -soname=t1.64.so -o %t1.64.so
+# RUN: llvm-mc --filetype=obj --triple=loongarch64 %s -o %t.64.o
+# RUN: ld.lld %t.64.o %t1.64.so -z separate-code -o %t.64
+# RUN: llvm-readelf -S -s %t.64 | FileCheck --check-prefixes=SEC,NM %s
+# RUN: llvm-readobj -r %t.64 | FileCheck --check-prefix=RELOC64 %s
+# RUN: llvm-readelf -x .got.plt %t.64 | FileCheck --check-prefix=GOTPLT64 %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t.64 | FileCheck --check-prefixes=DIS,DIS64 %s
+
+# SEC: .plt PROGBITS {{0*}}00020020
+
+## A canonical PLT has a non-zero st_value. bar and weak are called but their
+## addresses are not taken, so a canonical PLT is not necessary.
+# NM: {{0*}}00000000 0 FUNC GLOBAL DEFAULT UND bar
+# NM: {{0*}}00000000 0 FUNC WEAK   DEFAULT UND weak
+
+## The .got.plt slots relocated by .rela.plt point to .plt
+## This is required by glibc.
+# RELOC32:      .rela.plt {
+# RELOC32-NEXT:   0x40070 R_LARCH_JUMP_SLOT bar 0x0
+# RELOC32-NEXT:   0x40074 R_LARCH_JUMP_SLOT weak 0x0
+# RELOC32-NEXT: }
+# GOTPLT32:      section '.got.plt'
+# GOTPLT32-NEXT: 0x00040068 00000000 00000000 20000200 20000200
+
+# RELOC64:      .rela.plt {
+# RELOC64-NEXT:   0x400E0 R_LARCH_JUMP_SLOT bar 0x0
+# RELOC64-NEXT:   0x400E8 R_LARCH_JUMP_SLOT weak 0x0
+# RELOC64-NEXT: }
+# GOTPLT64:      section '.got.plt'
+# GOTPLT64-NEXT: 0x000400d0 00000000 00000000 00000000 00000000
+# GOTPLT64-NEXT: 0x000400e0 20000200 00000000 20000200 00000000
+
+# DIS:      <_start>:
+## Direct call
+## foo - . = 0x20010-0x20000 = 16
+# DIS-NEXT:   20000: bl 16
+## bar@plt - . = 0x20040-0x20004 = 60
+# DIS-NEXT:   20004: bl 60
+## bar@plt - . = 0x20040-0x20008 = 56
+# DIS-NEXT:   20008: bl 56
+## weak@plt - . = 0x20050-0x2000c = 68
+# DIS-NEXT:   2000c: bl 68
+# DIS:      <foo>:
+# DIS-NEXT:   20010:
+
+# DIS:      Disassembly of section .plt:
+# DIS:      <.plt>:
+## 32-bit: .got.plt - .plt = 0x40068 - 0x20020 = 4096*32+72
+# DIS32-NEXT:   pcaddu12i $t2, 32
+# DIS32-NEXT:   sub.w   $t1, $t1, $t3
+# DIS32-NEXT:   ld.w    $t3, $t2, 72
+# DIS32-NEXT:   addi.w  $t1, $t1, -44
+# DIS32-NEXT:   addi.w  $t0, $t2, 72
+# DIS32-NEXT:   srli.w  $t1, $t1, 2
+# DIS32-NEXT:   ld.w    $t0, $t0, 4
+# DIS32-NEXT:   jr      $t3
+
+## 64-bit: .got.plt - .plt = 0x400d0 - 0x20020 = 4096*32+176
+# DIS64-NEXT:   pcaddu12i $t2, 32
+# DIS64-NEXT:   sub.d   $t1, $t1, $t3
+# DIS64-NEXT:   ld.d    $t3, $t2, 176
+# DIS64-NEXT:   addi.d  $t1, $t1, -44
+# DIS64-NEXT:   addi.d  $t0, $t2, 176
+# DIS64-NEXT:   srli.d  $t1, $t1, 1
+# DIS64-NEXT:   ld.d    $t0, $t0, 8
+# DIS64-NEXT:   jr      $t3
+
+## 32-bit: &.got.plt[bar]-. = 0x40070-0x20040 = 4096*32+48
+## 64-bit: &.got.plt[bar]-. = 0x400e0-0x20040 = 4096*32+160
+# DIS:   20040: pcaddu12i $t3, 32
+# DIS32-NEXT:   ld.w    $t3, $t3, 48
+# DIS64-NEXT:   ld.d    $t3, $t3, 160
+# DIS-NEXT:     jirl    $t1, $t3, 0
+# DIS-NEXT:     nop
+
+## 32-bit: &.got.plt[weak]-. = 0x40074-0x20050 = 4096*32+36
+## 64-bit: &.got.plt[weak]-. = 0x400e8-0x20050 = 4096*32+152
+# DIS:   20050: pcaddu12i $t3, 32
+# DIS32-NEXT:   ld.w    $t3, $t3, 36
+# DIS64-NEXT:   ld.d    $t3, $t3, 152
+# DIS-NEXT:     jirl    $t1, $t3, 0
+# DIS-NEXT:     nop
+
+.global _start, foo, bar
+.weak weak
+
+_start:
+  bl foo
+  bl bar
+  bl %plt(bar)
+  bl weak
+
+## foo is local and non-preemptible, no PLT is generated.
+foo:
+  ret

lld/test/ELF/loongarch-reloc-pic.s

+# REQUIRES: loongarch
+# RUN: rm -rf %t && split-file %s %t
+
+# RUN: llvm-mc -filetype=obj -triple=loongarch32 %t/32.s -o %t/32.o
+# RUN: llvm-mc -filetype=obj -triple=loongarch64 %t/64.s -o %t/64.o
+# RUN: ld.lld -shared %t/32.o -o %t/32.so
+# RUN: llvm-nm %t/32.so | FileCheck --check-prefix=NM32 %s
+# RUN: llvm-readobj -r %t/32.so | FileCheck --check-prefix=RELOC32 %s
+# RUN: ld.lld -shared %t/64.o -o %t/64.so
+# RUN: llvm-nm %t/64.so | FileCheck --check-prefix=NM64 %s
+# RUN: llvm-readobj -r %t/64.so | FileCheck --check-prefix=RELOC64 %s
+
+## R_LARCH_32 and R_LARCH_64 are absolute relocation types.
+## In PIC mode, they create relative relocations if the symbol is non-preemptable.
+
+# NM32: 000301fc d b
+# NM64: 00030350 d b
+
+# RELOC32:      .rela.dyn {
+# RELOC32-NEXT:   0x301FC R_LARCH_RELATIVE - 0x301FC
+# RELOC32-NEXT:   0x301F8 R_LARCH_32 a 0
+# RELOC32-NEXT: }
+# RELOC64:      .rela.dyn {
+# RELOC64-NEXT:   0x30350 R_LARCH_RELATIVE - 0x30350
+# RELOC64-NEXT:   0x30348 R_LARCH_64 a 0
+# RELOC64-NEXT: }
+
+#--- 32.s
+.globl a, b
+.hidden b
+
+.data
+.long a
+b:
+.long b
+
+#--- 64.s
+.globl a, b
+.hidden b
+
+.data
+.quad a
+b:
+.quad b

lld/test/ELF/loongarch-tls-gd-and-ie.s

+# REQUIRES: loongarch
+
+# RUN: llvm-mc -filetype=obj --triple=loongarch32 %s -o %t.la32.o
+# RUN: ld.lld %t.la32.o -shared -o %t.la32
+# RUN: llvm-mc -filetype=obj --triple=loongarch64 %s -o %t.la64.o
+# RUN: ld.lld %t.la64.o -shared -o %t.la64
+
+# RUN: llvm-readelf -Wr %t.la32 | FileCheck --check-prefix=LA32-REL %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t.la32 | FileCheck --check-prefix=LA32 %s
+
+# RUN: llvm-readelf -Wr %t.la64 | FileCheck --check-prefix=LA64-REL %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t.la64 | FileCheck --check-prefix=LA64 %s
+
+# LA32-REL-NOT:  R_LARCH_32
+# LA32-REL:      00020240  00000206 R_LARCH_TLS_DTPMOD32   00000000   y + 0
+# LA32-REL-NEXT: 00020244  00000208 R_LARCH_TLS_DTPREL32   00000000   y + 0
+# LA32-REL-NEXT: 00020248  0000020a R_LARCH_TLS_TPREL32    00000000   y + 0
+
+# LA64-REL-NOT:  R_LARCH_64
+# LA64-REL:      00000000000203a8  0000000200000007 R_LARCH_TLS_DTPMOD64   0000000000000000 y + 0
+# LA64-REL-NEXT: 00000000000203b0  0000000200000009 R_LARCH_TLS_DTPREL64   0000000000000000 y + 0
+# LA64-REL-NEXT: 00000000000203b8  000000020000000b R_LARCH_TLS_TPREL64    0000000000000000 y + 0
+
+# LA32:      101d4: pcalau12i $a0, 16
+# LA32-NEXT:        ld.w $a0, $a0, 584
+# LA32-NEXT:        pcalau12i $a1, 16
+# LA32-NEXT:        addi.w $a1, $a1, 576
+
+# LA64:      102e0: pcalau12i $a0, 16
+# LA64-NEXT:        ld.d $a0, $a0, 952
+# LA64-NEXT:        pcalau12i $a1, 16
+# LA64-NEXT:        addi.d $a1, $a1, 936
+
+.global _start
+_start:
+la.tls.ie $a0, y  # should refer to the GOT entry relocated by the R_LARCH_TLS_TPRELnn record
+la.tls.gd $a1, y  # should refer to the GOT entry relocated by the R_LARCH_TLS_DTPMODnn record
+
+.section .tbss,"awT",@nobits
+.global y
+y:
+.word 0
+.size y, 4

lld/test/ELF/loongarch-tls-gd.s

+# REQUIRES: loongarch
+# RUN: rm -rf %t && split-file %s %t
+
+## LoongArch psABI doesn't specify TLS relaxation. Though the code sequences are not
+## relaxed, dynamic relocations can be omitted for GD->LE relaxation.
+
+# RUN: llvm-mc -filetype=obj -triple=loongarch32 %t/a.s -o %t/a.32.o
+# RUN: llvm-mc -filetype=obj -triple=loongarch32 %t/bc.s -o %t/bc.32.o
+# RUN: ld.lld -shared -soname=bc.so %t/bc.32.o -o %t/bc.32.so
+# RUN: llvm-mc -filetype=obj -triple=loongarch32 %t/tga.s -o %t/tga.32.o
+# RUN: llvm-mc -filetype=obj -triple=loongarch64 %t/a.s -o %t/a.64.o
+# RUN: llvm-mc -filetype=obj -triple=loongarch64 %t/bc.s -o %t/bc.64.o
+# RUN: ld.lld -shared -soname=bc.so %t/bc.64.o -o %t/bc.64.so
+# RUN: llvm-mc -filetype=obj -triple=loongarch64 %t/tga.s -o %t/tga.64.o
+
+## LA32 GD
+# RUN: ld.lld -shared %t/a.32.o %t/bc.32.o -o %t/gd.32.so
+# RUN: llvm-readobj -r %t/gd.32.so | FileCheck --check-prefix=GD32-REL %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t/gd.32.so | FileCheck --check-prefix=GD32 %s
+
+## LA32 GD -> LE
+# RUN: ld.lld %t/a.32.o %t/bc.32.o %t/tga.32.o -o %t/le.32
+# RUN: llvm-readelf -r %t/le.32 | FileCheck --check-prefix=NOREL %s
+# RUN: llvm-readelf -x .got %t/le.32 | FileCheck --check-prefix=LE32-GOT %s
+# RUN: ld.lld -pie %t/a.32.o %t/bc.32.o %t/tga.32.o -o %t/le-pie.32
+# RUN: llvm-readelf -r %t/le-pie.32 | FileCheck --check-prefix=NOREL %s
+# RUN: llvm-readelf -x .got %t/le-pie.32 | FileCheck --check-prefix=LE32-GOT %s
+
+## LA32 GD -> IE
+# RUN: ld.lld %t/a.32.o %t/bc.32.so %t/tga.32.o -o %t/ie.32
+# RUN: llvm-readobj -r %t/ie.32 | FileCheck --check-prefix=IE32-REL %s
+# RUN: llvm-readelf -x .got %t/ie.32 | FileCheck --check-prefix=IE32-GOT %s
+
+## LA64 GD
+# RUN: ld.lld -shared %t/a.64.o %t/bc.64.o -o %t/gd.64.so
+# RUN: llvm-readobj -r %t/gd.64.so | FileCheck --check-prefix=GD64-REL %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t/gd.64.so | FileCheck --check-prefix=GD64 %s
+
+## LA64 GD -> LE
+# RUN: ld.lld %t/a.64.o %t/bc.64.o %t/tga.64.o -o %t/le.64
+# RUN: llvm-readelf -r %t/le.64 | FileCheck --check-prefix=NOREL %s
+# RUN: llvm-readelf -x .got %t/le.64 | FileCheck --check-prefix=LE64-GOT %s
+# RUN: ld.lld -pie %t/a.64.o %t/bc.64.o %t/tga.64.o -o %t/le-pie.64
+# RUN: llvm-readelf -r %t/le-pie.64 | FileCheck --check-prefix=NOREL %s
+# RUN: llvm-readelf -x .got %t/le-pie.64 | FileCheck --check-prefix=LE64-GOT %s
+
+## LA64 GD -> IE
+# RUN: ld.lld %t/a.64.o %t/bc.64.so %t/tga.64.o -o %t/ie.64
+# RUN: llvm-readobj -r %t/ie.64 | FileCheck --check-prefix=IE64-REL %s
+# RUN: llvm-readelf -x .got %t/ie.64 | FileCheck --check-prefix=IE64-GOT %s
+
+# GD32-REL:      .rela.dyn {
+# GD32-REL-NEXT:   0x20314 R_LARCH_TLS_DTPMOD32 a 0x0
+# GD32-REL-NEXT:   0x20318 R_LARCH_TLS_DTPREL32 a 0x0
+# GD32-REL-NEXT:   0x2031C R_LARCH_TLS_DTPMOD32 b 0x0
+# GD32-REL-NEXT:   0x20320 R_LARCH_TLS_DTPREL32 b 0x0
+# GD32-REL-NEXT: }
+
+## &DTPMOD(a) - . = 0x20314 - 0x10250: 0x10 pages, page offset 0x314
+# GD32:      10250: pcalau12i $a0, 16
+# GD32-NEXT:        addi.w $a0, $a0, 788
+# GD32-NEXT:        bl 56
+
+## &DTPMOD(b) - . = 0x2031c - 0x1025c: 0x10 pages, page offset 0x31c
+# GD32:      1025c: pcalau12i $a0, 16
+# GD32-NEXT:        addi.w $a0, $a0, 796
+# GD32-NEXT:        bl 44
+
+# GD64-REL:      .rela.dyn {
+# GD64-REL-NEXT:   0x204C8 R_LARCH_TLS_DTPMOD64 a 0x0
+# GD64-REL-NEXT:   0x204D0 R_LARCH_TLS_DTPREL64 a 0x0
+# GD64-REL-NEXT:   0x204D8 R_LARCH_TLS_DTPMOD64 b 0x0
+# GD64-REL-NEXT:   0x204E0 R_LARCH_TLS_DTPREL64 b 0x0
+# GD64-REL-NEXT: }
+
+## &DTPMOD(a) - . = 0x204c8 - 0x10398: 0x10 pages, page offset 0x4c8
+# GD64:      10398: pcalau12i $a0, 16
+# GD64-NEXT:        addi.d $a0, $a0, 1224
+# GD64-NEXT:        bl 48
+
+## &DTPMOD(b) - . = 0x204d8 - 0x103a4: 0x10 pages, page offset 0x4d8
+# GD64:      103a4: pcalau12i $a0, 16
+# GD64-NEXT:        addi.d $a0, $a0, 1240
+# GD64-NEXT:        bl 36
+
+# NOREL: no relocations
+
+## .got contains pre-populated values: [a@dtpmod, a@dtprel, b@dtpmod, b@dtprel]
+## a@dtprel = st_value(a) = 0x8
+## b@dtprel = st_value(b) = 0xc
+# LE32-GOT: section '.got':
+# LE32-GOT-NEXT: 0x[[#%x,A:]] [[#%x,GOT:]] 01000000 08000000 01000000
+# LE32-GOT-NEXT: 0x[[#%x,A:]] 0c000000
+# LE64-GOT: section '.got':
+# LE64-GOT-NEXT: 0x[[#%x,A:]] [[#%x,GOT:]] [[#%x,GOT:]] 01000000 00000000
+# LE64-GOT-NEXT: 0x[[#%x,A:]] 08000000 00000000 01000000 00000000
+# LE64-GOT-NEXT: 0x[[#%x,A:]] 0c000000 00000000
+
+## a is local - relaxed to LE - its DTPMOD/DTPREL slots are link-time constants.
+## b is external - DTPMOD/DTPREL dynamic relocations are required.
+# IE32-REL:      .rela.dyn {
+# IE32-REL-NEXT:   0x3022C R_LARCH_TLS_DTPMOD32 b 0x0
+# IE32-REL-NEXT:   0x30230 R_LARCH_TLS_DTPREL32 b 0x0
+# IE32-REL-NEXT: }
+# IE32-GOT:      section '.got':
+# IE32-GOT-NEXT: 0x00030220 c0010300 01000000 08000000 00000000
+# IE32-GOT-NEXT: 0x00030230 00000000
+
+# IE64-REL:      .rela.dyn {
+# IE64-REL-NEXT:   0x30390 R_LARCH_TLS_DTPMOD64 b 0x0
+# IE64-REL-NEXT:   0x30398 R_LARCH_TLS_DTPREL64 b 0x0
+# IE64-REL-NEXT: }
+# IE64-GOT:      section '.got':
+# IE64-GOT-NEXT: 0x00030378 b8020300 00000000 01000000 00000000
+# IE64-GOT-NEXT: 0x00030388 08000000 00000000 00000000 00000000
+# IE64-GOT-NEXT: 0x00030398 00000000 00000000
+
+#--- a.s
+la.tls.gd $a0, a
+bl %plt(__tls_get_addr)
+
+la.tls.gd $a0, b
+bl %plt(__tls_get_addr)
+
+.section .tbss
+.globl a
+.zero 8
+a:
+.zero 4
+
+#--- bc.s
+.tbss
+.globl b, c
+b:
+.zero 4
+c:
+
+#--- tga.s
+.globl __tls_get_addr
+__tls_get_addr:

lld/test/ELF/loongarch-tls-ie.s

+# REQUIRES: loongarch
+# RUN: rm -rf %t && split-file %s %t
+
+# RUN: llvm-mc -filetype=obj -triple=loongarch32 %t/32.s -o %t/32.o
+# RUN: llvm-mc -filetype=obj -triple=loongarch64 %t/64.s -o %t/64.o
+
+## LA32 IE
+# RUN: ld.lld -shared %t/32.o -o %t/32.so
+# RUN: llvm-readobj -r -d %t/32.so | FileCheck --check-prefix=IE32-REL %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t/32.so | FileCheck --check-prefixes=IE32 %s
+
+## LA32 IE -> LE
+# RUN: ld.lld %t/32.o -o %t/32
+# RUN: llvm-readelf -r %t/32 | FileCheck --check-prefix=NOREL %s
+# RUN: llvm-readelf -x .got %t/32 | FileCheck --check-prefix=LE32-GOT %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t/32 | FileCheck --check-prefixes=LE32 %s
+
+## LA64 IE
+# RUN: ld.lld -shared %t/64.o -o %t/64.so
+# RUN: llvm-readobj -r -d %t/64.so | FileCheck --check-prefix=IE64-REL %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t/64.so | FileCheck --check-prefixes=IE64 %s
+
+## LA64 IE -> LE
+# RUN: ld.lld %t/64.o -o %t/64
+# RUN: llvm-readelf -r %t/64 | FileCheck --check-prefix=NOREL %s
+# RUN: llvm-readelf -x .got %t/64 | FileCheck --check-prefix=LE64-GOT %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t/64 | FileCheck --check-prefixes=LE64 %s
+
+# IE32-REL:      FLAGS STATIC_TLS
+# IE32-REL:      .rela.dyn {
+# IE32-REL-NEXT:   0x2021C R_LARCH_TLS_TPREL32 - 0xC
+# IE32-REL-NEXT:   0x20218 R_LARCH_TLS_TPREL32 a 0x0
+# IE32-REL-NEXT: }
+
+# IE64-REL:      FLAGS STATIC_TLS
+# IE64-REL:      .rela.dyn {
+# IE64-REL-NEXT:   0x20378 R_LARCH_TLS_TPREL64 - 0xC
+# IE64-REL-NEXT:   0x20370 R_LARCH_TLS_TPREL64 a 0x0
+# IE64-REL-NEXT: }
+
+## LA32:
+## &.got[0] - . = 0x20218 - 0x101a4: 0x10 pages, page offset 0x218
+## &.got[1] - . = 0x2021c - 0x101b0: 0x10 pages, page offset 0x21c
+# IE32:      101a4: pcalau12i $a4, 16
+# IE32-NEXT:        ld.w $a4, $a4, 536
+# IE32-NEXT:        add.w $a4, $a4, $tp
+# IE32-NEXT: 101b0: pcalau12i $a5, 16
+# IE32-NEXT:        ld.w $a5, $a5, 540
+# IE32-NEXT:        add.w $a5, $a5, $tp
+
+## LA64:
+## &.got[0] - . = 0x20370 - 0x102a0: 0x10 pages, page offset 0x370
+## &.got[1] - . = 0x20378 - 0x102ac: 0x10 pages, page offset 0x378
+# IE64:      102a0: pcalau12i $a4, 16
+# IE64-NEXT:        ld.d $a4, $a4, 880
+# IE64-NEXT:        add.d $a4, $a4, $tp
+# IE64-NEXT: 102ac: pcalau12i $a5, 16
+# IE64-NEXT:        ld.d $a5, $a5, 888
+# IE64-NEXT:        add.d $a5, $a5, $tp
+
+# NOREL: no relocations
+
+# a@tprel = st_value(a) = 0x8
+# b@tprel = st_value(a) = 0xc
+# LE32-GOT: section '.got':
+# LE32-GOT-NEXT: 0x0003012c 00000000 08000000 0c000000
+# LE64-GOT: section '.got':
+# LE64-GOT-NEXT: 0x000301e0 00000000 00000000 08000000 00000000
+# LE64-GOT-NEXT: 0x000301f0 0c000000 00000000
+
+## LA32:
+## &.got[0] - . = 0x30130 - 0x20114: 0x10 pages, page offset 0x130
+## &.got[1] - . = 0x30134 - 0x20120: 0x10 pages, page offset 0x134
+# LE32:      20114: pcalau12i $a4, 16
+# LE32-NEXT:        ld.w $a4, $a4, 304
+# LE32-NEXT:        add.w $a4, $a4, $tp
+# LE32-NEXT: 20120: pcalau12i $a5, 16
+# LE32-NEXT:        ld.w $a5, $a5, 308
+# LE32-NEXT:        add.w $a5, $a5, $tp
+
+## LA64:
+## &.got[0] - . = 0x301e8 - 0x201c8: 0x10 pages, page offset 0x1e8
+## &.got[1] - . = 0x301f0 - 0x201d4: 0x10 pages, page offset 0x1f0
+# LE64:      201c8: pcalau12i $a4, 16
+# LE64-NEXT:        ld.d $a4, $a4, 488
+# LE64-NEXT:        add.d $a4, $a4, $tp
+# LE64-NEXT: 201d4: pcalau12i $a5, 16
+# LE64-NEXT:        ld.d $a5, $a5, 496
+# LE64-NEXT:        add.d $a5, $a5, $tp
+
+#--- 32.s
+la.tls.ie $a4, a
+add.w $a4, $a4, $tp
+la.tls.ie $a5, b
+add.w $a5, $a5, $tp
+
+.section .tbss
+.globl a
+.zero 8
+a:
+.zero 4
+b:
+
+#--- 64.s
+la.tls.ie $a4, a
+add.d $a4, $a4, $tp
+la.tls.ie $a5, b
+add.d $a5, $a5, $tp
+
+.section .tbss
+.globl a
+.zero 8
+a:
+.zero 4
+b:

lld/test/ELF/loongarch-tls-ld.s

+# REQUIRES: loongarch
+# RUN: rm -rf %t && split-file %s %t
+
+## LoongArch psABI doesn't specify TLS relaxation. Though the code sequences are not
+## relaxed, dynamic relocations can be omitted for LD->LE relaxation.
+
+# RUN: llvm-mc -filetype=obj -triple=loongarch32 -position-independent %t/a.s -o %t/a.32.o
+# RUN: llvm-mc -filetype=obj -triple=loongarch32 %t/tga.s -o %t/tga.32.o
+# RUN: llvm-mc -filetype=obj -triple=loongarch64 -position-independent %t/a.s -o %t/a.64.o
+# RUN: llvm-mc -filetype=obj -triple=loongarch64 %t/tga.s -o %t/tga.64.o
+
+## LA32 LD
+# RUN: ld.lld -shared %t/a.32.o -o %t/ld.32.so
+# RUN: llvm-readobj -r %t/ld.32.so | FileCheck --check-prefix=LD32-REL %s
+# RUN: llvm-readelf -x .got %t/ld.32.so | FileCheck --check-prefix=LD32-GOT %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t/ld.32.so | FileCheck --check-prefixes=LD32 %s
+
+## LA32 LD -> LE
+# RUN: ld.lld %t/a.32.o %t/tga.32.o -o %t/le.32
+# RUN: llvm-readelf -r %t/le.32 | FileCheck --check-prefix=NOREL %s
+# RUN: llvm-readelf -x .got %t/le.32 | FileCheck --check-prefix=LE32-GOT %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t/le.32 | FileCheck --check-prefixes=LE32 %s
+
+## LA64 LD
+# RUN: ld.lld -shared %t/a.64.o -o %t/ld.64.so
+# RUN: llvm-readobj -r %t/ld.64.so | FileCheck --check-prefix=LD64-REL %s
+# RUN: llvm-readelf -x .got %t/ld.64.so | FileCheck --check-prefix=LD64-GOT %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t/ld.64.so | FileCheck --check-prefixes=LD64 %s
+
+## LA64 LD -> LE
+# RUN: ld.lld %t/a.64.o %t/tga.64.o -o %t/le.64
+# RUN: llvm-readelf -r %t/le.64 | FileCheck --check-prefix=NOREL %s
+# RUN: llvm-readelf -x .got %t/le.64 | FileCheck --check-prefix=LE64-GOT %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t/le.64 | FileCheck --check-prefixes=LE64 %s
+
+## a@dtprel = st_value(a) = 0 is a link-time constant.
+# LD32-REL:      .rela.dyn {
+# LD32-REL-NEXT:   0x20284 R_LARCH_TLS_DTPMOD32 - 0x0
+# LD32-REL-NEXT: }
+# LD32-GOT:      section '.got':
+# LD32-GOT-NEXT: 0x00020280 10020200 00000000 00000000
+
+# LD64-REL:      .rela.dyn {
+# LD64-REL-NEXT:   0x20408 R_LARCH_TLS_DTPMOD64 - 0x0
+# LD64-REL-NEXT: }
+# LD64-GOT:      section '.got':
+# LD64-GOT-NEXT: 0x00020400 20030200 00000000 00000000 00000000
+# LD64-GOT-NEXT: 0x00020410 00000000 00000000
+
+## LA32: &DTPMOD(a) - . = 0x20284 - 0x101cc: 0x10 pages, page offset 0x284
+# LD32:      101cc: pcalau12i $a0, 16
+# LD32-NEXT:        addi.w $a0, $a0, 644
+# LD32-NEXT:        bl 44
+
+## LA64: &DTPMOD(a) - . = 0x20408 - 0x102e0: 0x10 pages, page offset 0x408
+# LD64:      102e0: pcalau12i $a0, 16
+# LD64-NEXT:        addi.d $a0, $a0, 1032
+# LD64-NEXT:        bl 40
+
+# NOREL: no relocations
+
+## a is local - its DTPMOD/DTPREL slots are link-time constants.
+## a@dtpmod = 1 (main module)
+# LE32-GOT: section '.got':
+# LE32-GOT-NEXT: 0x00030120 00000000 01000000 00000000
+
+# LE64-GOT: section '.got':
+# LE64-GOT-NEXT: 0x000301d8 00000000 00000000 01000000 00000000
+# LE64-GOT-NEXT: 0x000301e8 00000000 00000000
+
+## LA32: DTPMOD(.LANCHOR0) - . = 0x30124 - 0x20114: 0x10 pages, page offset 0x124
+# LE32:      20114: pcalau12i $a0, 16
+# LE32-NEXT:        addi.w $a0, $a0, 292
+# LE32-NEXT:        bl 4
+
+## LA64: DTPMOD(.LANCHOR0) - . = 0x301e0 - 0x201c8: 0x10 pages, page offset 0x1e0
+# LE64:      201c8: pcalau12i $a0, 16
+# LE64-NEXT:        addi.d $a0, $a0, 480
+# LE64-NEXT:        bl 4
+
+#--- a.s
+la.tls.ld $a0, .LANCHOR0
+bl %plt(__tls_get_addr)
+
+.section .tbss,"awT",@nobits
+.set .LANCHOR0, . + 0
+.zero 8
+
+#--- tga.s
+.globl __tls_get_addr
+__tls_get_addr:

lld/test/ELF/loongarch-tls-le.s

+# REQUIRES: loongarch
+
+# RUN: llvm-mc -filetype=obj -triple=loongarch32 %s -o %t.32.o
+# RUN: llvm-mc -filetype=obj -triple=loongarch64 %s -o %t.64.o
+
+# RUN: ld.lld %t.32.o -o %t.32
+# RUN: llvm-nm -p %t.32 | FileCheck --check-prefixes=NM %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t.32 | FileCheck --check-prefixes=LE %s
+
+# RUN: ld.lld %t.64.o -o %t.64
+# RUN: llvm-objdump -d --no-show-raw-insn %t.64 | FileCheck --check-prefixes=LE %s
+
+# RUN: not ld.lld -shared %t.32.o -o /dev/null 2>&1 | FileCheck %s --check-prefix=ERR --implicit-check-not=error:
+
+# ERR: error: relocation R_LARCH_TLS_LE_HI20 against .LANCHOR0 cannot be used with -shared
+# ERR: error: relocation R_LARCH_TLS_LE_LO12 against .LANCHOR0 cannot be used with -shared
+# ERR: error: relocation R_LARCH_TLS_LE_HI20 against a cannot be used with -shared
+# ERR: error: relocation R_LARCH_TLS_LE_LO12 against a cannot be used with -shared
+
+# NM: {{0*}}00000008 b .LANCHOR0
+# NM: {{0*}}00000800 B a
+
+## .LANCHOR0@tprel = 8
+## a@tprel = 0x800
+# LE:      lu12i.w $a0, 0
+# LE-NEXT: ori $a0, $a0, 8
+# LE-NEXT: lu12i.w $a1, 0
+# LE-NEXT: ori $a1, $a1, 2048
+# LE-EMPTY:
+
+.text
+_start:
+la.tls.le $a0, .LANCHOR0
+la.tls.le $a1, a
+
+.section .tbss
+.space 8
+.LANCHOR0:
+.space 0x800-8
+.globl a
+a:
+.zero 4

lld/test/lit.cfg.py

[
         (
             "--targets-built",
             {
                 "AArch64": "aarch64",
                 "AMDGPU": "amdgpu",
                 "ARM": "arm",
                 "AVR": "avr",
                 "Hexagon": "hexagon",
+                "LoongArch": "loongarch",
                 "Mips": "mips",
                 "MSP430": "msp430",
                 "PowerPC": "ppc",
                 "RISCV": "riscv",
                 "Sparc": "sparc",
                 "WebAssembly": "wasm",
                 "X86": "x86",
             },