[XRay] Add initial support for loongarch64

[SixWeining]

Summary

Only support patching FunctionEntry/FunctionExit/FunctionTailExit for now.

[SixWeining]

D140725 is abandoned. Let me defer this change until we support 64bit PC-relative relocation for SymA - SymB.

[SixWeining]

In D140727#4019019, @SixWeining wrote:

D140725 is abandoned. Let me defer this change until we support 64bit PC-relative relocation for SymA - SymB.

Update: R_LARCH_64_PCREL can be emitted after D153872. And I'd like to ask @Ami-zhang to update this patch later.

llvm/test/CodeGen/LoongArch/xray-attribute-instrumentation.ll

12

CHECK-COUNT-11

[MaskRay]

llvm/test/CodeGen/LoongArch/xray-attribute-instrumentation.ll

2

I think you want to read my recent updates to other xray-attribute-instrumentation.ll. Certain changes can make the test less sensitive to non-xray updates.

[Ami-zhang]

(1) Rebase
(2) Make some minor changes to xray-attribute-instrumentation.ll

[MaskRay]

compiler-rt/lib/xray/xray_loongarch64.cpp

154

I know you copy the pattern from other patterns, but we should use TODO here. An unimplemented minor feature is not FIXME.

compiler-rt/lib/xray/xray_trampoline_loongarch64.S

28

You can use .irpc to simplify this a bit. See libunwind/src/UnwindRegistersSave.S

compiler-rt/test/xray/TestCases/Posix/arg1-arg0-logging.cpp

9 ↗

(On Diff #537564)

I added aarch64 support. You may rebase and add loongarch64 on the REQUIRES: line.

compiler-rt/test/xray/TestCases/Posix/basic-filtering.cpp

26 ↗

(On Diff #537564)

Most REQUIRES: x86_64-target-arch are unnecessarily constrained. I just removed them. You may rebase and avoid changes to these test files.

[MaskRay]

compiler-rt/lib/xray/xray_loongarch64.cpp

24

I think the PO_ style actually harms readability. Most instructions are used just once. It's more readable just using the magic number when it is needed paired with an inline comment

Address[10] = insn2RI12(0x02c00000, RegNum::RN_S, ...) // addi.d ...

[SixWeining]

Since R_LARCH_64_PCREL has been supported, we can use version 2 xray and the patch summary should be modified accordingly.

llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp

187

should use version 2:

recordSled(BeginOfSled, MI, Kind, 2);

[Ami-zhang]

compiler-rt/lib/xray/xray_loongarch64.cpp

24

Ok, updated it. Thanks for your suggestion.

154

Done.

compiler-rt/lib/xray/xray_trampoline_loongarch64.S

28

Done.

compiler-rt/test/xray/TestCases/Posix/arg1-arg0-logging.cpp

9 ↗

(On Diff #537564)

Rebased.

compiler-rt/test/xray/TestCases/Posix/basic-filtering.cpp

26 ↗

(On Diff #537564)

Rebased.

llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp

187

Yes, updated it.

llvm/test/CodeGen/LoongArch/xray-attribute-instrumentation.ll

12

Done.

[Ami-zhang]

Rebase and make some improvements.

[xen0n]

compiler-rt/lib/xray/xray_loongarch64.cpp

23–26

I think people usually just declare the register ABI names with decimal numbers for readability?

This is minor but I personally find it slightly distracting to have to think about what's 0xc in decimal (that's the case even though I'm already very familiar with these kinds of thing). Not sure if others also prefer decimals though...

33

Parens not needed in this case. (If you want to enhance readability for those people having difficulties remembering precedence and associativeness of operators, you should instead put the parens around Rj << 5 and Imm << 10...)

I'd suggest re-ordering the operands too, to imitate the expected bit layout of the result.

40

Similarly here.

43–48

Does this look *very* similar to encodeInstruction2RI12? ;-)

Actually, if you don't bounds-check the operands, you only need one helper for each combination of slots involved. Check for example the static uint32_t insn implementation in my D138135, or the auto-generated encoding helpers for the QEMU TCG LoongArch64 port, for some alternative approaches.

59

.tmpN: for it to not look like a directive?

72

All-lowercase i.e. tracing for consistency? Or am I missing something?

74

I think idiomatically it's not "create/delete stack frame" but rather "(de-)allocate" or "setup/teardown"... anyway please fix the usage of articles (put the "the"'s properly) and also add a space after the ; because it's usually aesthetically better.

This is all minor though, and it's not like people will misunderstand anything otherwise, but rather it's mostly just me pushing for more natural English usage.

81

("set back" happens to be an idiomatic phrase verb so I got confused here for ~1 second, so I think it's probably easier to just avoid this coincidence.)

compiler-rt/lib/xray/xray_trampoline_loongarch64.S

84

Use pseudo-instruction for idiomatic expression of intent.

llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp

152–177

We don't have to repeat the instruction pattern when we can just refer people to the source file containing this. Also the comment seems to be explanation for the magic number 11, so it should probably come before the definition.

[Ami-zhang]

compiler-rt/lib/xray/xray_loongarch64.cpp

23–26

Ok, use decimal numbers to declare the register ABI names.

33

What you said makes sense. Thanks for your suggestion and attentiveness. I have adjusted parens and operands order.

40

Done.

43–48

It is indeed similar to encodeInstruction2RI12. Given its exclusive use in this context, I prefer the unified 2RIx format.

Thanks for the suggestion. While we appreciate it, we are more inclined to use one 2RIx format helper here.

59

Use the real .Lxray_sled_endN.

72

It should be a copy from mips. I think it can be written tracing hook or TracingHook. To maintain all-lowercase consistency here, I use tracing hook.

74

Ok, a space after the ; is added. About article the, i also added it. But i am not sure whether the usage of the is proper. If there are any further issues , I would greatly appreciate your feedback.

Thanks for your effort.

81

Done.

compiler-rt/lib/xray/xray_trampoline_loongarch64.S

84

Done.

llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp

152–177

Done.

[Ami-zhang]

Addressed @xen0n's comments.

[xen0n]

Thanks for following up with the suggestions. This now looks mostly okay to me; let's wait for more people to chip in!

[xen0n]

Ah, the patch summary probably needs some update as well. We no longer care about version 0 and the backend changes for R_LARCH_64_PCREL are already in, for example.

[MaskRay]

compiler-rt/lib/xray/xray_trampoline_loongarch64.S

21

The symbol needs to be hidden and consider using some macros. See xray_trampoline_AArch64.S

[MaskRay]

compiler-rt/lib/xray/xray_loongarch64.cpp

31

Early xray code unfortunately does not respect the conventional style that well.
The usual order is static inline

[Ami-zhang]

compiler-rt/lib/xray/xray_loongarch64.cpp

31

Done, adjusted to static inline.

compiler-rt/lib/xray/xray_trampoline_loongarch64.S

21

Ok, I have modified them.
Thanks for your suggestion.

[Ami-zhang]

Hide some symbols and using some macros in asm.

[MaskRay]

One nit about the test.

llvm/test/CodeGen/LoongArch/xray-attribute-instrumentation.ll

25

See llvm/test/CodeGen/X86/xray-attribute-instrumentation.ll. I use something like [[TMP:.Ltmp[0-9]+]]: so that we don't need to adjust the test if the compiler happens to produce more .Ltmp* symbols.

[Ami-zhang]

llvm/test/CodeGen/LoongArch/xray-attribute-instrumentation.ll

25

Done.

[Ami-zhang]

Make xray-attribute-instrumentation.ll less sensitive to .Ltmp/.Lxray_fn_idx label changes

[Ami-zhang]

Remove unnecessary '\' symbol in xray-attribute-instrumentation.ll

clang/lib/Driver/XRayArgs.cpp

if (Triple.isMacOSX()) {
     }
   } else if (Triple.isOSBinFormatELF()) {
     switch (Triple.getArch()) {
     case llvm::Triple::x86_64:
     case llvm::Triple::arm:
     case llvm::Triple::aarch64:
     case llvm::Triple::hexagon:
     case llvm::Triple::ppc64le:
+    case llvm::Triple::loongarch64:
     case llvm::Triple::mips:
     case llvm::Triple::mipsel:
     case llvm::Triple::mips64:
     case llvm::Triple::mips64el:
       break;
     default:
       D.Diag(diag::err_drv_unsupported_opt_for_target)
           << XRayInstrument->getSpelling() << Triple.str();

compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake

 set(ALL_CFI_SUPPORTED_ARCH ${X86} ${X86_64} ${ARM32} ${ARM64} ${MIPS64}
     ${HEXAGON})
 set(ALL_SCUDO_STANDALONE_SUPPORTED_ARCH ${X86} ${X86_64} ${ARM32} ${ARM64}
     ${MIPS32} ${MIPS64} ${PPC64} ${HEXAGON} ${LOONGARCH64} ${RISCV64})
 if(APPLE)
 set(ALL_XRAY_SUPPORTED_ARCH ${X86_64} ${ARM64})
 else()
 set(ALL_XRAY_SUPPORTED_ARCH ${X86_64} ${ARM32} ${ARM64} ${MIPS32} ${MIPS64}
-    powerpc64le ${HEXAGON})
+    powerpc64le ${HEXAGON} ${LOONGARCH64})
 endif()
 set(ALL_SHADOWCALLSTACK_SUPPORTED_ARCH ${ARM64})
 
 if (UNIX)
 set(ALL_ORC_SUPPORTED_ARCH ${X86_64} ${ARM64} ${ARM32})
 endif()
 
 if (WIN32)
   set(ALL_ORC_SUPPORTED_ARCH ${X86_64})
 endif()

compiler-rt/lib/xray/CMakeLists.txt

set(armhf_SOURCES
   ${arm_SOURCES}
   )
 
 set(aarch64_SOURCES
   xray_AArch64.cpp
   xray_trampoline_AArch64.S
   )
 
+set(loongarch64_SOURCES
+  xray_loongarch64.cpp
+  xray_trampoline_loongarch64.S
+  )
+
 set(mips_SOURCES
   xray_mips.cpp
   xray_trampoline_mips.S
   )
 
 set(mipsel_SOURCES
   xray_mips.cpp
   xray_trampoline_mips.S
set(XRAY_ALL_SOURCE_FILES
   ${XRAY_SOURCES}
   ${XRAY_FDR_MODE_SOURCES}
   ${XRAY_BASIC_MODE_SOURCES}
   ${XRAY_PROFILING_MODE_SOURCES}
   ${x86_64_SOURCES}
   ${arm_SOURCES}
   ${armhf_SOURCES}
   ${hexagon_SOURCES}
+  ${loongarch64_SOURCES}
   ${mips_SOURCES}
   ${mipsel_SOURCES}
   ${mips64_SOURCES}
   ${mips64el_SOURCES}
   ${powerpc64le_SOURCES}
   ${XRAY_IMPL_HEADERS}
   )
 list(REMOVE_DUPLICATES XRAY_ALL_SOURCE_FILES)

compiler-rt/lib/xray/xray_interface.cpp

 namespace __xray {
 
 #if defined(__x86_64__)
 static const int16_t cSledLength = 12;
 #elif defined(__aarch64__)
 static const int16_t cSledLength = 32;
 #elif defined(__arm__)
 static const int16_t cSledLength = 28;
+#elif SANITIZER_LOONGARCH64
+static const int16_t cSledLength = 48;
 #elif SANITIZER_MIPS32
 static const int16_t cSledLength = 48;
 #elif SANITIZER_MIPS64
 static const int16_t cSledLength = 64;
 #elif defined(__powerpc64__)
 static const int16_t cSledLength = 8;
 #elif defined(__hexagon__)
 static const int16_t cSledLength = 20;

compiler-rt/lib/xray/xray_loongarch64.cpp

+//===-------- xray_loongarch64.cpp ------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file is a part of XRay, a dynamic runtime instrumentation system.
+//
+// Implementation of loongarch-specific routines.
+//
+//===----------------------------------------------------------------------===//
+#include "sanitizer_common/sanitizer_common.h"
+#include "xray_defs.h"
+#include "xray_interface_internal.h"
+#include <atomic>
+
+namespace __xray {
+
+enum RegNum : uint32_t {
+  RN_RA = 1,
+  RN_SP = 3,
+  RN_T0 = 12,
+  RN_T1 = 13,
+};
+
+// Encode instructions in the 2RIx format, where the primary formats here
+// are 2RI12-type and 2RI16-type.
+static inline uint32_t
+encodeInstruction2RIx(uint32_t Opcode, uint32_t Rd, uint32_t Rj,
+                      uint32_t Imm) XRAY_NEVER_INSTRUMENT {
+  return Opcode | (Imm << 10) | (Rj << 5) | Rd;
+}
+
+// Encode instructions in 1RI20 format, e.g. lu12i.w/lu32i.d.
+static inline uint32_t
+encodeInstruction1RI20(uint32_t Opcode, uint32_t Rd,
+                       uint32_t Imm) XRAY_NEVER_INSTRUMENT {
+  return Opcode | (Imm << 5) | Rd;
+}
+
+static inline bool patchSled(const bool Enable, const uint32_t FuncId,
+                             const XRaySledEntry &Sled,
+                             void (*TracingHook)()) XRAY_NEVER_INSTRUMENT {
+  // When |Enable| == true,
+  // We replace the following compile-time stub (sled):
+  //
+  // .Lxray_sled_beginN:
+  //  B .Lxray_sled_endN
+  //  11 NOPs (44 bytes)
+  // .Lxray_sled_endN:
+  //
+  // With the following runtime patch:
+  //
+  // xray_sled_n:
+  //   addi.d  sp, sp, -16                       ; create the stack frame
+  //   st.d    ra, sp, 8                         ; save the return address
+  //   lu12i.w t0, %abs_hi20(__xray_FunctionEntry/Exit)
+  //   ori     t0, t0, %abs_lo12(__xray_FunctionEntry/Exit)
+  //   lu32i.d t0, %abs64_lo20(__xray_FunctionEntry/Exit)
+  //   lu52i.d t0, t0, %abs64_hi12(__xray_FunctionEntry/Exit)
+  //   lu12i.w t1, %abs_hi20(function_id)
+  //   ori     t1, t1, %abs_lo12(function_id)    ; pass the function id
+  //   jirl    ra, t0, 0                         ; call the tracing hook
+  //   ld.d    ra, sp, 8                         ; restore the return address
+  //   addi.d  sp, sp, 16                        ; de-allocate the stack frame
+  //
+  // Replacement of the first 4-byte instruction should be the last and atomic
+  // operation, so that the user code which reaches the sled concurrently
+  // either jumps over the whole sled, or executes the whole sled when the
+  // latter is ready.
+  //
+  // When |Enable|==false, we set the first instruction in the sled back to
+  //   B #48
+
+  uint32_t *Address = reinterpret_cast<uint32_t *>(Sled.address());
+  if (Enable) {
+    uint32_t LoTracingHookAddr = reinterpret_cast<int64_t>(TracingHook) & 0xfff;
+    uint32_t HiTracingHookAddr =
+        (reinterpret_cast<int64_t>(TracingHook) >> 12) & 0xfffff;
+    uint32_t HigherTracingHookAddr =
+        (reinterpret_cast<int64_t>(TracingHook) >> 32) & 0xfffff;
+    uint32_t HighestTracingHookAddr =
+        (reinterpret_cast<int64_t>(TracingHook) >> 52) & 0xfff;
+    uint32_t LoFunctionID = FuncId & 0xfff;
+    uint32_t HiFunctionID = (FuncId >> 12) & 0xfffff;
+    Address[1] = encodeInstruction2RIx(0x29c00000, RegNum::RN_RA, RegNum::RN_SP,
+                                       0x8); // st.d ra, sp, 8
+    Address[2] = encodeInstruction1RI20(
+        0x14000000, RegNum::RN_T0,
+        HiTracingHookAddr); // lu12i.w t0, HiTracingHookAddr
+    Address[3] = encodeInstruction2RIx(
+        0x03800000, RegNum::RN_T0, RegNum::RN_T0,
+        LoTracingHookAddr); // ori t0, t0, LoTracingHookAddr
+    Address[4] = encodeInstruction1RI20(
+        0x16000000, RegNum::RN_T0,
+        HigherTracingHookAddr); // lu32i.d t0, HigherTracingHookAddr
+    Address[5] = encodeInstruction2RIx(
+        0x03000000, RegNum::RN_T0, RegNum::RN_T0,
+        HighestTracingHookAddr); // lu52i.d t0, t0, HighestTracingHookAddr
+    Address[6] =
+        encodeInstruction1RI20(0x14000000, RegNum::RN_T1,
+                               HiFunctionID); // lu12i.w t1, HiFunctionID
+    Address[7] =
+        encodeInstruction2RIx(0x03800000, RegNum::RN_T1, RegNum::RN_T1,
+                              LoFunctionID); // ori t1, t1, LoFunctionID
+    Address[8] = encodeInstruction2RIx(0x4c000000, RegNum::RN_RA, RegNum::RN_T0,
+                                       0); // jirl ra, t0, 0
+    Address[9] = encodeInstruction2RIx(0x28c00000, RegNum::RN_RA, RegNum::RN_SP,
+                                       0x8); // ld.d ra, sp, 8
+    Address[10] = encodeInstruction2RIx(
+        0x02c00000, RegNum::RN_SP, RegNum::RN_SP, 0x10); // addi.d sp, sp, 16
+    uint32_t CreateStackSpace = encodeInstruction2RIx(
+        0x02c00000, RegNum::RN_SP, RegNum::RN_SP, 0xff0); // addi.d sp, sp, -16
+    std::atomic_store_explicit(
+        reinterpret_cast<std::atomic<uint32_t> *>(Address), CreateStackSpace,
+        std::memory_order_release);
+  } else {
+    std::atomic_store_explicit(
+        reinterpret_cast<std::atomic<uint32_t> *>(Address),
+        uint32_t(0x50003000), std::memory_order_release); // b #48
+  }
+  return true;
+}
+
+bool patchFunctionEntry(const bool Enable, const uint32_t FuncId,
+                        const XRaySledEntry &Sled,
+                        void (*Trampoline)()) XRAY_NEVER_INSTRUMENT {
+  return patchSled(Enable, FuncId, Sled, Trampoline);
+}
+
+bool patchFunctionExit(const bool Enable, const uint32_t FuncId,
+                       const XRaySledEntry &Sled) XRAY_NEVER_INSTRUMENT {
+  return patchSled(Enable, FuncId, Sled, __xray_FunctionExit);
+}
+
+bool patchFunctionTailExit(const bool Enable, const uint32_t FuncId,
+                           const XRaySledEntry &Sled) XRAY_NEVER_INSTRUMENT {
+  // TODO: In the future we'd need to distinguish between non-tail exits and
+  // tail exits for better information preservation.
+  return patchSled(Enable, FuncId, Sled, __xray_FunctionExit);
+}
+
+bool patchCustomEvent(const bool Enable, const uint32_t FuncId,
+                      const XRaySledEntry &Sled) XRAY_NEVER_INSTRUMENT {
+  // FIXME: Implement in loongarch?
+  return false;
+}
+
+bool patchTypedEvent(const bool Enable, const uint32_t FuncId,
+                     const XRaySledEntry &Sled) XRAY_NEVER_INSTRUMENT {
+  // FIXME: Implement in loongarch?
+  return false;
+}
+} // namespace __xray
+
+extern "C" void __xray_ArgLoggerEntry() XRAY_NEVER_INSTRUMENT {
+  // TODO: This will have to be implemented in the trampoline assembly file.
+}

compiler-rt/lib/xray/xray_trampoline_loongarch64.S

+//===-- xray_trampoline_loongarch64.s ---------------------------*- ASM -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file is a part of XRay, a dynamic runtime instrumentation system.
+//
+// This implements the loongarch-specific assembler for the trampolines.
+//
+//===----------------------------------------------------------------------===//
+
+#include "../sanitizer_common/sanitizer_asm.h"
+
+#define FROM_0_TO_7 0,1,2,3,4,5,6,7
+#define FROM_7_TO_0 7,6,5,4,3,2,1,0
+
+.macro SAVE_ARG_REGISTERS
+  .irp i,FROM_7_TO_0
+    st.d  $a\i, $sp, (8 * 8 + 8 * \i)
+  .endr
+  .irp i,FROM_7_TO_0
+    fst.d $f\i, $sp, (8 * \i)
+  .endr
+.endm
+
+.macro RESTORE_ARG_REGISTERS
+  .irp i,FROM_0_TO_7
+    fld.d $f\i, $sp, (8 * \i)
+  .endr
+  .irp i,FROM_0_TO_7
+    ld.d  $a\i, $sp, (8 * 8 + 8 * \i)
+  .endr
+.endm
+
+.macro SAVE_RET_REGISTERS
+  st.d    $a1, $sp, 24
+  st.d    $a0, $sp, 16
+  fst.d   $f1, $sp, 8
+  fst.d   $f0, $sp, 0
+.endm
+
+.macro RESTORE_RET_REGISTERS
+  fld.d   $f0, $sp, 0
+  fld.d   $f1, $sp, 8
+  ld.d    $a0, $sp, 16
+  ld.d    $a1, $sp, 24
+.endm
+
+  .text
+  .file "xray_trampoline_loongarch64.S"
+  .globl ASM_SYMBOL(__xray_FunctionEntry)
+  ASM_HIDDEN(__xray_FunctionEntry)
+  .p2align 2
+  ASM_TYPE_FUNCTION(__xray_FunctionEntry)
+ASM_SYMBOL(__xray_FunctionEntry):
+  .cfi_startproc
+  // Save argument registers before doing any actual work.
+  .cfi_def_cfa_offset 136
+  addi.d  $sp, $sp, -136
+  st.d    $ra, $sp, 128
+  .cfi_offset 1, -8
+  SAVE_ARG_REGISTERS
+
+  la.got  $t2, ASM_SYMBOL(_ZN6__xray19XRayPatchedFunctionE)
+  ld.d    $t2, $t2, 0
+
+  beqz    $t2, FunctionEntry_restore
+
+  // a1=0 means that we are tracing an entry event.
+  move    $a1, $zero
+  // Function ID is in t1 (the first parameter).
+  move    $a0, $t1
+  jirl    $ra, $t2, 0
+
+FunctionEntry_restore:
+  // Restore argument registers.
+  RESTORE_ARG_REGISTERS
+  ld.d    $ra, $sp, 128
+  addi.d  $sp, $sp, 136
+  ret
+FunctionEntry_end:
+  ASM_SIZE(__xray_FunctionEntry)
+  .cfi_endproc
+
+  .text
+  .globl ASM_SYMBOL(__xray_FunctionExit)
+  ASM_HIDDEN(__xray_FunctionExit)
+  .p2align 2
+  ASM_TYPE_FUNCTION(__xray_FunctionExit)
+ASM_SYMBOL(__xray_FunctionExit):
+  .cfi_startproc
+  // Save return registers before doing any actual work.
+  .cfi_def_cfa_offset 48
+  addi.d  $sp, $sp, -48
+  st.d    $ra, $sp, 40
+  .cfi_offset 1, -8
+  st.d    $fp, $sp, 32
+  SAVE_RET_REGISTERS
+
+  la.got  $t2, ASM_SYMBOL(_ZN6__xray19XRayPatchedFunctionE)
+  ld.d    $t2, $t2, 0
+
+  beqz    $t2, FunctionExit_restore
+
+  // a1=1 means that we are tracing an exit event.
+  li.w    $a1, 1
+  // Function ID is in t1 (the first parameter).
+  move    $a0, $t1
+  jirl    $ra, $t2, 0
+
+FunctionExit_restore:
+  // Restore return registers.
+  RESTORE_RET_REGISTERS
+  ld.d    $fp, $sp, 32
+  ld.d    $ra, $sp, 40
+  addi.d  $sp, $sp, 48
+  ret
+
+FunctionExit_end:
+  ASM_SIZE(__xray_FunctionExit)
+  .cfi_endproc

compiler-rt/lib/xray/xray_tsc.h

 
 #else // SANITIZER_FUCHSIA
 
 #if defined(__x86_64__)
 #include "xray_x86_64.inc"
 #elif defined(__powerpc64__)
 #include "xray_powerpc64.inc"
 #elif defined(__arm__) || defined(__aarch64__) || defined(__mips__) ||         \
-    defined(__hexagon__)
+    defined(__hexagon__) || defined(__loongarch_lp64)
 // Emulated TSC.
 // There is no instruction like RDTSCP in user mode on ARM. ARM's CP15 does
 //   not have a constant frequency like TSC on x86(_64), it may go faster
 //   or slower depending on CPU turbo or power saving mode. Furthermore,
 //   to read from CP15 on ARM a kernel modification or a driver is needed.
 //   We can not require this from users of compiler-rt.
 // So on ARM we use clock_gettime() which gives the result in nanoseconds.
 //   To get the measurements per second, we scale this by the number of

compiler-rt/test/xray/TestCases/Posix/c-test.cpp

 // RUN: %clang_xray -g -fxray-modes=xray-basic,xray-fdr,xray-profiling -o %t %s
 // RUN: rm -f xray-log.c-test.*
 // RUN: XRAY_OPTIONS=patch_premain=true:verbosity=1:xray_mode=xray-basic %t \
 // RUN:     2>&1 | FileCheck %s
 // RUN: rm -f xray-log.c-test.*
 //
-// REQUIRES: target={{(aarch64|x86_64)-.*}}
+// REQUIRES: target={{(aarch64|loongarch64|x86_64)-.*}}
 // REQUIRES: built-in-llvm-tree
 __attribute__((xray_always_instrument)) void always() {}
 
 int main() {
   always();
 }
 
 // CHECK: =={{[0-9].*}}==XRay: Log file in '{{.*}}'

compiler-rt/test/xray/TestCases/Posix/fdr-thread-order.cpp

 // RUN: rm -rf %t && mkdir %t
 // RUN: %clangxx_xray -g -std=c++11 %s -o %t.exe
 // RUN: XRAY_OPTIONS="patch_premain=false \
 // RUN:    xray_logfile_base=%t/ xray_mode=xray-fdr verbosity=1" \
 // RUN:    XRAY_FDR_OPTIONS=func_duration_threshold_us=0 %run %t.exe 2>&1 | \
 // RUN:    FileCheck %s
 // RUN: %llvm_xray convert --symbolize --output-format=yaml -instr_map=%t.exe %t/*
 // RUN: %llvm_xray convert --symbolize --output-format=yaml -instr_map=%t.exe %t/* | \
 // RUN:   FileCheck %s --check-prefix TRACE
 
-// REQUIRES: target={{(aarch64|x86_64)-.*}}
+// REQUIRES: target={{(aarch64|loongarch64|x86_64)-.*}}
 // REQUIRES: built-in-llvm-tree
 
 #include "xray/xray_log_interface.h"
 #include <atomic>
 #include <cassert>
 #include <thread>
 
 std::atomic<uint64_t> var{0};

llvm/lib/CodeGen/XRayInstrumentation.cpp

bool XRayInstrumentation::runOnMachineFunction(MachineFunction &MF) {
   }
 
   if (!F.hasFnAttribute("xray-skip-exit")) {
     switch (MF.getTarget().getTargetTriple().getArch()) {
     case Triple::ArchType::arm:
     case Triple::ArchType::thumb:
     case Triple::ArchType::aarch64:
     case Triple::ArchType::hexagon:
+    case Triple::ArchType::loongarch64:
     case Triple::ArchType::mips:
     case Triple::ArchType::mipsel:
     case Triple::ArchType::mips64:
     case Triple::ArchType::mips64el: {
       // For the architectures which don't have a single return instruction
       InstrumentationOptions op;
       op.HandleTailcall = false;
       op.HandleAllReturns = true;

llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h

public:
   void emitInstruction(const MachineInstr *MI) override;
 
   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                        const char *ExtraCode, raw_ostream &OS) override;
   bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
                              const char *ExtraCode, raw_ostream &OS) override;
 
   void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI);
+  void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI);
+  void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI);
+  void emitSled(const MachineInstr &MI, SledKind Kind);
 
   // tblgen'erated function.
   bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
                                    const MachineInstr *MI);
   // Wrapper needed for tblgenned pseudo lowering.
   bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
     return lowerLoongArchMachineOperandToMCOperand(MO, MCOp, *this);
   }
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHASMPRINTER_H

llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp

 //===----------------------------------------------------------------------===//
 
 #include "LoongArchAsmPrinter.h"
 #include "LoongArch.h"
 #include "LoongArchTargetMachine.h"
 #include "MCTargetDesc/LoongArchInstPrinter.h"
 #include "TargetInfo/LoongArchTargetInfo.h"
 #include "llvm/CodeGen/AsmPrinter.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCInstBuilder.h"
 #include "llvm/MC/TargetRegistry.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "loongarch-asm-printer"
 
 // Simple pseudo-instructions have their lowering (with expansion to real
 // instructions) auto-generated.
 #include "LoongArchGenMCPseudoLowering.inc"
 
 void LoongArchAsmPrinter::emitInstruction(const MachineInstr *MI) {
   LoongArch_MC::verifyInstructionPredicates(
       MI->getOpcode(), getSubtargetInfo().getFeatureBits());
 
   // Do any auto-generated pseudo lowerings.
   if (emitPseudoExpansionLowering(*OutStreamer, MI))
     return;
 
   switch (MI->getOpcode()) {
   case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
     LowerPATCHABLE_FUNCTION_ENTER(*MI);
     return;
+  case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
+    LowerPATCHABLE_FUNCTION_EXIT(*MI);
+    return;
+  case TargetOpcode::PATCHABLE_TAIL_CALL:
+    LowerPATCHABLE_TAIL_CALL(*MI);
+    return;
   }
 
   MCInst TmpInst;
   if (!lowerLoongArchMachineInstrToMCInst(MI, TmpInst, *this))
     EmitToStreamer(*OutStreamer, TmpInst);
 }
 
 bool LoongArchAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
if (F.hasFnAttribute("patchable-function-entry")) {
     if (F.getFnAttribute("patchable-function-entry")
             .getValueAsString()
             .getAsInteger(10, Num))
       return;
     emitNops(Num);
     return;
   }
 
-  // TODO: Emit sled here once we get support for XRay.
+  emitSled(MI, SledKind::FUNCTION_ENTER);
+}
+
+void LoongArchAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI) {
+  emitSled(MI, SledKind::FUNCTION_EXIT);
+}
+
+void LoongArchAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI) {
+  emitSled(MI, SledKind::TAIL_CALL);
+}
+
+void LoongArchAsmPrinter::emitSled(const MachineInstr &MI, SledKind Kind) {
+  // For loongarch64 we want to emit the following pattern:
+  //
+  // .Lxray_sled_beginN:
+  //   B .Lxray_sled_endN
+  //   11 NOPs (44 bytes)
+  // .Lxray_sled_endN:
+  //
+  // We need the extra bytes because at runtime they may be used for the
+  // actual pattern defined at compiler-rt/lib/xray/xray_loongarch64.cpp.
+  // The count here should be adjusted accordingly if the implementation
+  // changes.
+  const int8_t NoopsInSledCount = 11;
+  OutStreamer->emitCodeAlignment(Align(4), &getSubtargetInfo());
+  MCSymbol *BeginOfSled = OutContext.createTempSymbol("xray_sled_begin");
+  MCSymbol *EndOfSled = OutContext.createTempSymbol("xray_sled_end");
+  OutStreamer->emitLabel(BeginOfSled);
+  EmitToStreamer(*OutStreamer,
+                 MCInstBuilder(LoongArch::B)
+                     .addExpr(MCSymbolRefExpr::create(EndOfSled, OutContext)));
+  emitNops(NoopsInSledCount);
+  OutStreamer->emitLabel(EndOfSled);
+  recordSled(BeginOfSled, MI, Kind, 2);
 }
 
 bool LoongArchAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
   AsmPrinter::runOnMachineFunction(MF);
+  // Emit the XRay table for this function.
+  emitXRayTable();
   return true;
 }
 
 // Force static initialization.
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLoongArchAsmPrinter() {
   RegisterAsmPrinter<LoongArchAsmPrinter> X(getTheLoongArch32Target());
   RegisterAsmPrinter<LoongArchAsmPrinter> Y(getTheLoongArch64Target());
 }

llvm/lib/Target/LoongArch/LoongArchSubtarget.h

public:
   bool hasExtLBT() const { return HasExtLBT; }
   bool hasLaGlobalWithPcrel() const { return HasLaGlobalWithPcrel; }
   bool hasLaGlobalWithAbs() const { return HasLaGlobalWithAbs; }
   bool hasLaLocalWithAbs() const { return HasLaLocalWithAbs; }
   bool hasUAL() const { return HasUAL; }
   MVT getGRLenVT() const { return GRLenVT; }
   unsigned getGRLen() const { return GRLen; }
   LoongArchABI::ABI getTargetABI() const { return TargetABI; }
+  bool isXRaySupported() const override { return is64Bit(); }
 };
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHSUBTARGET_H

llvm/lib/XRay/InstrumentationMap.cpp

loadObj(StringRef Filename, object::OwningBinary<object::ObjectFile> &ObjFile,
         InstrumentationMap::SledContainer &Sleds,
         InstrumentationMap::FunctionAddressMap &FunctionAddresses,
         InstrumentationMap::FunctionAddressReverseMap &FunctionIds) {
   InstrumentationMap Map;
 
   // Find the section named "xray_instr_map".
   if ((!ObjFile.getBinary()->isELF() && !ObjFile.getBinary()->isMachO()) ||
       !(ObjFile.getBinary()->getArch() == Triple::x86_64 ||
+        ObjFile.getBinary()->getArch() == Triple::loongarch64 ||
         ObjFile.getBinary()->getArch() == Triple::ppc64le ||
         ObjFile.getBinary()->getArch() == Triple::arm ||
         ObjFile.getBinary()->getArch() == Triple::aarch64))
     return make_error<StringError>(
         "File format not supported (only does ELF and Mach-O little endian "
         "64-bit).",
         std::make_error_code(std::errc::not_supported));
 

llvm/test/CodeGen/LoongArch/xray-attribute-instrumentation.ll

+; RUN: llc --mtriple=loongarch64 %s -o - | FileCheck %s
+; RUN: llc --mtriple=loongarch64 -filetype=obj %s -o %t
+; RUN: llvm-readobj -r %t | FileCheck %s --check-prefix=RELOC
+
+define i32 @foo() nounwind noinline uwtable "function-instrument"="xray-always" {
+; CHECK-LABEL: foo:
+; CHECK-LABEL: .Lfunc_begin0:
+; CHECK:       .p2align 2
+; CHECK-LABEL: .Lxray_sled_begin0:
+; CHECK-NEXT:  b .Lxray_sled_end0
+; CHECK-COUNT-11:  nop
+; CHECK-LABEL: .Lxray_sled_end0:
+  ret i32 0
+; CHECK-LABEL: .Lxray_sled_begin1:
+; CHECK-NEXT:  b .Lxray_sled_end1
+; CHECK-COUNT-11:  nop
+; CHECK-NEXT: .Lxray_sled_end1:
+; CHECK-NEXT:  ret
+; CHECK-NEXT: .Lfunc_end0:
+}
+
+; CHECK-LABEL: .section xray_instr_map
+; CHECK-NEXT: .Lxray_sleds_start0:
+; CHECK-NEXT: [[TMP:.Ltmp[0-9]+]]:
+; CHECK-NEXT: .dword .Lxray_sled_begin0-[[TMP]]
+; CHECK-NEXT: .dword .Lfunc_begin0-([[TMP]]+8)
+; CHECK-NEXT: .byte 0x00
+; CHECK-NEXT: .byte 0x01
+; CHECK-NEXT: .byte 0x02
+; CHECK-NEXT: .space 13
+; CHECK-NEXT: [[TMP:.Ltmp[0-9]+]]:
+; CHECK-NEXT: .dword .Lxray_sled_begin1-[[TMP]]
+; CHECK-NEXT: .dword .Lfunc_begin0-([[TMP]]+8)
+; CHECK-NEXT: .byte 0x01
+; CHECK-NEXT: .byte 0x01
+; CHECK-NEXT: .byte 0x02
+; CHECK-NEXT: .space 13
+; CHECK-NEXT: .Lxray_sleds_end0:
+
+; CHECK-LABEL:  .section xray_fn_idx
+; CHECK:      [[IDX:.Lxray_fn_idx[0-9]+]]:
+; CHECK:      .dword .Lxray_sleds_start0-[[IDX]]
+; CHECK-NEXT: .dword 2
+
+; RELOC:      Section ([[#]]) .relaxray_instr_map {
+; RELOC-NEXT:   0x0 R_LARCH_64_PCREL .text 0x0
+; RELOC-NEXT:   0x8 R_LARCH_64_PCREL .text 0x0
+; RELOC-NEXT:   0x20 R_LARCH_64_PCREL .text 0x34
+; RELOC-NEXT:   0x28 R_LARCH_64_PCREL .text 0x0
+; RELOC-NEXT: }
+; RELOC-NEXT: Section ([[#]]) .relaxray_fn_idx {
+; RELOC-NEXT:   0x0 R_LARCH_64_PCREL xray_instr_map 0x0
+; RELOC-NEXT: }
+; RELOC-NEXT: Section ([[#]]) .rela.eh_frame {
+; RELOC-NEXT:   0x1C R_LARCH_32_PCREL .text 0x0
+; RELOC-NEXT: }