[X86] Update LiveVariables in more cases in convertToThreeAddress

[foad]

Summary

Following on from D129634, this patch fixes more X86 CodeGen test
failures with D129213 applied, which adds verification of LiveIntervals
after the TwoAddressInstruction pass runs. These failures only showed up
with LLVM_ENABLE_EXPENSIVE_CHECKS=ON which adds the equivalent of an
implicit -verify-machineinstrs on all tests.

[RKSimon]

LGTM

[yubing]

llvm/lib/Target/X86/X86InstrInfo.cpp

1699

seems it should be "NumRegOperands = 3"
the 3rd operand of VPBROADCASTDZrmk is i32mem:$src instead of a register.

[foad]

llvm/lib/Target/X86/X86InstrInfo.cpp

1699

It needs to be at least 4 for some other opcodes like:

%4:vr512 = VBLENDMPSZrmk killed %3:vk16wm, killed %2:vr512, killed %1:gr64, 1, $noreg, 0, $noreg

Is this causing a problem? If so, maybe the loop at line 1769 needs an Op.isReg() check.

[yubing]

llvm/lib/Target/X86/X86InstrInfo.cpp

1699

adding Op.isReg() check works for me!
my guilty MIR is:

%22:vr512 = VPBROADCASTDZrmk %21:vr512(tied-def 0), killed %20:vk16wm, %stack.1, 1, $noreg, 0, $noreg :: (load (s32) from %stack.1, align 64)

llvm/lib/Target/X86/X86InstrInfo.cpp

case X86::SUB32ri: {
 
     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
                                   .add(Dest)
                                   .addReg(SrcReg, getKillRegState(isKill));
     if (ImplicitOp.getReg() != 0)
       MIB.add(ImplicitOp);
 
     NewMI = addOffset(MIB, -Imm);
+
+    // Add kills if classifyLEAReg created a new register.
+    if (LV && SrcReg != Src.getReg())
+      LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
     break;
   }
 
   case X86::SUB64ri8:
   case X86::SUB64ri32: {
     if (!MI.getOperand(2).isImm())
       return nullptr;
     int64_t Imm = MI.getOperand(2).getImm();
NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
               .add(Dest)
               .add(MI.getOperand(2))
               .add(Src)
               .add(MI.getOperand(3))
               .add(MI.getOperand(4))
               .add(MI.getOperand(5))
               .add(MI.getOperand(6))
               .add(MI.getOperand(7));
+    NumRegOperands = 4;
     break;
   }
 
   case X86::VMOVDQU8Z128rrk:
   case X86::VMOVDQU8Z256rrk:
   case X86::VMOVDQU8Zrrk:
   case X86::VMOVDQU16Z128rrk:
   case X86::VMOVDQU16Z256rrk:

llvm/test/CodeGen/X86/add.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86
-; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefix=X64-LINUX
+; RUN: llc < %s -mtriple=x86_64-linux -verify-machineinstrs | FileCheck %s --check-prefix=X64-LINUX
 ; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s --check-prefix=X64-WIN32
 
 declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32)
 declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32)
 
 ; The immediate can be encoded in a smaller way if the
 ; instruction is a sub instead of an add.
 define i32 @test1(i32 inreg %a) nounwind {

llvm/test/CodeGen/X86/masked_load.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=sse2    | FileCheck %s --check-prefixes=SSE,SSE2
 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=sse4.2  | FileCheck %s --check-prefixes=SSE,SSE42
 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=avx     | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX1
 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=avx2    | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX2
 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=avx512f | FileCheck %s --check-prefixes=AVX,AVX512,AVX512F
 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=avx512f,avx512dq,avx512vl | FileCheck %s --check-prefixes=AVX,AVX512,AVX512VL,AVX512VLDQ
 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=avx512f,avx512bw,avx512vl | FileCheck %s --check-prefixes=AVX,AVX512,AVX512VL,AVX512VLBW
-; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=avx512f,avx512bw,avx512dq,avx512vl | FileCheck %s --check-prefixes=X86-AVX512
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=avx512f,avx512bw,avx512dq,avx512vl -verify-machineinstrs | FileCheck %s --check-prefixes=X86-AVX512
 
 ;
 ; vXf64
 ;
 
 define <1 x double> @load_v1f64_v1i64(<1 x i64> %trigger, ptr %addr, <1 x double> %dst) {
 ; SSE-LABEL: load_v1f64_v1i64:
 ; SSE:       ## %bb.0: