[mlir][spirv] Change td def/class prefix from SPV to SPIRV

[kuhar]

Summary

Tested with check-mlir and check-mlir-integration.

Fixes: https://github.com/llvm/llvm-project/issues/56863

[antiagainst]

Nit: commit message prefix should be "[mlir][spirv]"

[kuhar]

Undo unintended edits.

[kuhar]

In D134649#3815336, @antiagainst wrote:

Nit: commit message prefix should be "[mlir][spirv]"

Gah, I renamed everything except for the commit message :)

mlir/docs/Dialects/SPIR-V.md

 
 SPIR-V compilation should also take into consideration of the execution
 environment, so we generate SPIR-V modules valid for the target environment.
 This is conveyed by the `spirv.target_env` (`spirv::TargetEnvAttr`) attribute. It
 should be of `#spirv.target_env` attribute kind, which is defined as:
 
 ```
 spirv-version    ::= `v1.0` | `v1.1` | ...
-spirv-extension  ::= `SPV_KHR_16bit_storage` | `SPV_EXT_physical_storage_buffer` | ...
+spirv-extension  ::= `SPIRV_KHR_16bit_storage` | `SPIRV_EXT_physical_storage_buffer` | ...
 spirv-capability ::= `Shader` | `Kernel` | `GroupNonUniform` | ...
 
 spirv-extension-list     ::= `[` (spirv-extension-elements)? `]`
 spirv-extension-elements ::= spirv-extension (`,` spirv-extension)*
 
 spirv-capability-list     ::= `[` (spirv-capability-elements)? `]`
 spirv-capability-elements ::= spirv-capability (`,` spirv-capability)*
 
*   A dictionary of target resource limits (see the
     *   `max_compute_workgroup_invocations`
     *   `max_compute_workgroup_size`
 
 For example,
 
 ```
 module attributes {
 spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.3, [Shader, GroupNonUniform], [SPV_KHR_8bit_storage]>,
+    #spirv.vce<v1.3, [Shader, GroupNonUniform], [SPIRV_KHR_8bit_storage]>,
     ARM:IntegratedGPU,
     {
       max_compute_workgroup_invocations = 128 : i32,
       max_compute_workgroup_size = dense<[128, 128, 64]> : vector<3xi32>
     }>
 } { ... }
 ```
 

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVArithmeticOps.td

 
 #ifndef MLIR_DIALECT_SPIRV_IR_ARITHMETIC_OPS
 #define MLIR_DIALECT_SPIRV_IR_ARITHMETIC_OPS
 
 include "mlir/Dialect/SPIRV/IR/SPIRVBase.td"
 include "mlir/Interfaces/InferTypeOpInterface.td"
 include "mlir/Interfaces/SideEffectInterfaces.td"
 
-class SPV_ArithmeticBinaryOp<string mnemonic, Type type,
+class SPIRV_ArithmeticBinaryOp<string mnemonic, Type type,
                                list<Trait> traits = []> :
       // Operands type same as result type.
-      SPV_BinaryOp<mnemonic, type, type,
+      SPIRV_BinaryOp<mnemonic, type, type,
                    !listconcat(traits,
                                [NoSideEffect, SameOperandsAndResultType])> {
   // In addition to normal types arithmetic instructions can support cooperative
   // matrix.
   let arguments = (ins
-    SPV_ScalarOrVectorOrCoopMatrixOf<type>:$operand1,
-    SPV_ScalarOrVectorOrCoopMatrixOf<type>:$operand2
+    SPIRV_ScalarOrVectorOrCoopMatrixOf<type>:$operand1,
+    SPIRV_ScalarOrVectorOrCoopMatrixOf<type>:$operand2
   );
 
   let results = (outs
-    SPV_ScalarOrVectorOrCoopMatrixOf<type>:$result
+    SPIRV_ScalarOrVectorOrCoopMatrixOf<type>:$result
   );
   let assemblyFormat = "operands attr-dict `:` type($result)";
 }
 
-class SPV_ArithmeticUnaryOp<string mnemonic, Type type,
+class SPIRV_ArithmeticUnaryOp<string mnemonic, Type type,
                               list<Trait> traits = []> :
       // Operand type same as result type.
-      SPV_UnaryOp<mnemonic, type, type,
+      SPIRV_UnaryOp<mnemonic, type, type,
                    !listconcat(traits,
                                [NoSideEffect, SameOperandsAndResultType])>;
 
 // -----
 
-def SPV_FAddOp : SPV_ArithmeticBinaryOp<"FAdd", SPV_Float, [Commutative]> {
+def SPIRV_FAddOp : SPIRV_ArithmeticBinaryOp<"FAdd", SPIRV_Float, [Commutative]> {
   let summary = "Floating-point addition of Operand 1 and Operand 2.";
 
   let description = [{
     Result Type must be a scalar or vector of floating-point type.
 
      The types of Operand 1 and Operand 2 both must be the same as Result
     Type.
 
let description = [{
     %4 = spirv.FAdd %0, %1 : f32
     %5 = spirv.FAdd %2, %3 : vector<4xf32>
     ```
   }];
 }
 
 // -----
 
-def SPV_FDivOp : SPV_ArithmeticBinaryOp<"FDiv", SPV_Float, []> {
+def SPIRV_FDivOp : SPIRV_ArithmeticBinaryOp<"FDiv", SPIRV_Float, []> {
   let summary = "Floating-point division of Operand 1 divided by Operand 2.";
 
   let description = [{
     Result Type must be a scalar or vector of floating-point type.
 
      The types of Operand 1 and Operand 2 both must be the same as Result
     Type.
 
let description = [{
     %4 = spirv.FDiv %0, %1 : f32
     %5 = spirv.FDiv %2, %3 : vector<4xf32>
     ```
   }];
 }
 
 // -----
 
-def SPV_FModOp : SPV_ArithmeticBinaryOp<"FMod", SPV_Float, []> {
+def SPIRV_FModOp : SPIRV_ArithmeticBinaryOp<"FMod", SPIRV_Float, []> {
   let summary = [{
     The floating-point remainder whose sign matches the sign of Operand 2.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of floating-point type.
 
      The types of Operand 1 and Operand 2 both must be the same as Result
let description = [{
     %4 = spirv.FMod %0, %1 : f32
     %5 = spirv.FMod %2, %3 : vector<4xf32>
     ```
   }];
 }
 
 // -----
 
-def SPV_FMulOp : SPV_ArithmeticBinaryOp<"FMul", SPV_Float, [Commutative]> {
+def SPIRV_FMulOp : SPIRV_ArithmeticBinaryOp<"FMul", SPIRV_Float, [Commutative]> {
   let summary = "Floating-point multiplication of Operand 1 and Operand 2.";
 
   let description = [{
     Result Type must be a scalar or vector of floating-point type.
 
      The types of Operand 1 and Operand 2 both must be the same as Result
     Type.
 
let description = [{
     %4 = spirv.FMul %0, %1 : f32
     %5 = spirv.FMul %2, %3 : vector<4xf32>
     ```
   }];
 }
 
 // -----
 
-def SPV_FNegateOp : SPV_ArithmeticUnaryOp<"FNegate", SPV_Float, []> {
+def SPIRV_FNegateOp : SPIRV_ArithmeticUnaryOp<"FNegate", SPIRV_Float, []> {
   let summary = [{
     Inverts the sign bit of Operand. (Note, however, that OpFNegate is still
     considered a floating-point instruction, and so is subject to the
     general floating-point rules regarding, for example, subnormals and NaN
     propagation).
   }];
 
   let description = [{
let description = [{
     %1 = spirv.FNegate %0 : f32
     %3 = spirv.FNegate %2 : vector<4xf32>
     ```
   }];
 }
 
 // -----
 
-def SPV_FRemOp : SPV_ArithmeticBinaryOp<"FRem", SPV_Float, []> {
+def SPIRV_FRemOp : SPIRV_ArithmeticBinaryOp<"FRem", SPIRV_Float, []> {
   let summary = [{
     The floating-point remainder whose sign matches the sign of Operand 1.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of floating-point type.
 
      The types of Operand 1 and Operand 2 both must be the same as Result
let description = [{
     %4 = spirv.FRemOp %0, %1 : f32
     %5 = spirv.FRemOp %2, %3 : vector<4xf32>
     ```
   }];
 }
 
 // -----
 
-def SPV_FSubOp : SPV_ArithmeticBinaryOp<"FSub", SPV_Float, []> {
+def SPIRV_FSubOp : SPIRV_ArithmeticBinaryOp<"FSub", SPIRV_Float, []> {
   let summary = "Floating-point subtraction of Operand 2 from Operand 1.";
 
   let description = [{
     Result Type must be a scalar or vector of floating-point type.
 
      The types of Operand 1 and Operand 2 both must be the same as Result
     Type.
 
let description = [{
     %4 = spirv.FRemOp %0, %1 : f32
     %5 = spirv.FRemOp %2, %3 : vector<4xf32>
     ```
   }];
 }
 
 // -----
 
-def SPV_IAddOp : SPV_ArithmeticBinaryOp<"IAdd",
-                                        SPV_Integer,
+def SPIRV_IAddOp : SPIRV_ArithmeticBinaryOp<"IAdd",
+                                        SPIRV_Integer,
                                         [Commutative, UsableInSpecConstantOp]> {
   let summary = "Integer addition of Operand 1 and Operand 2.";
 
   let description = [{
     Result Type must be a scalar or vector of integer type.
 
      The type of Operand 1 and Operand 2  must be a scalar or vector of
     integer type.  They must have the same number of components as Result
let description = [{
     ```
   }];
 
   let hasFolder = 1;
 }
 
 // -----
 
-def SPV_IAddCarryOp : SPV_BinaryOp<"IAddCarry",
-                                   SPV_AnyStruct, SPV_Integer,
+def SPIRV_IAddCarryOp : SPIRV_BinaryOp<"IAddCarry",
+                                   SPIRV_AnyStruct, SPIRV_Integer,
                                    [Commutative, NoSideEffect]> {
   let summary = [{
     Integer addition of Operand 1 and Operand 2, including the carry.
   }];
 
   let description = [{
     Result Type must be from OpTypeStruct.  The struct must have two
     members, and the two members must be the same type.  The member type
let description = [{
 
     ```mlir
     %2 = spirv.IAddCarry %0, %1 : !spirv.struct<(i32, i32)>
     %2 = spirv.IAddCarry %0, %1 : !spirv.struct<(vector<2xi32>, vector<2xi32>)>
     ```
   }];
 
   let arguments = (ins
-    SPV_ScalarOrVectorOf<SPV_Integer>:$operand1,
-    SPV_ScalarOrVectorOf<SPV_Integer>:$operand2
+    SPIRV_ScalarOrVectorOf<SPIRV_Integer>:$operand1,
+    SPIRV_ScalarOrVectorOf<SPIRV_Integer>:$operand2
   );
 
   let results = (outs
-    SPV_AnyStruct:$result
+    SPIRV_AnyStruct:$result
   );
 
   let builders = [
     OpBuilder<(ins "Value":$operand1, "Value":$operand2), [{
       build($_builder, $_state,
             ::mlir::spirv::StructType::get({operand1.getType(), operand1.getType()}),
             operand1, operand2);
     }]>
   ];
 
   let hasVerifier = 1;
 }
 
 // -----
 
-def SPV_IMulOp : SPV_ArithmeticBinaryOp<"IMul",
-                                        SPV_Integer,
+def SPIRV_IMulOp : SPIRV_ArithmeticBinaryOp<"IMul",
+                                        SPIRV_Integer,
                                         [Commutative, UsableInSpecConstantOp]> {
   let summary = "Integer multiplication of Operand 1 and Operand 2.";
 
   let description = [{
     Result Type must be a scalar or vector of integer type.
 
      The type of Operand 1 and Operand 2  must be a scalar or vector of
     integer type.  They must have the same number of components as Result
let description = [{
     ```
   }];
 
   let hasFolder = 1;
 }
 
 // -----
 
-def SPV_ISubOp : SPV_ArithmeticBinaryOp<"ISub",
-                                        SPV_Integer,
+def SPIRV_ISubOp : SPIRV_ArithmeticBinaryOp<"ISub",
+                                        SPIRV_Integer,
                                         [UsableInSpecConstantOp]> {
   let summary = "Integer subtraction of Operand 2 from Operand 1.";
 
   let description = [{
     Result Type must be a scalar or vector of integer type.
 
      The type of Operand 1 and Operand 2  must be a scalar or vector of
     integer type.  They must have the same number of components as Result
let description = [{
     ```
   }];
 
   let hasFolder = 1;
 }
 
 // -----
 
-def SPV_ISubBorrowOp : SPV_BinaryOp<"ISubBorrow", SPV_AnyStruct, SPV_Integer,
+def SPIRV_ISubBorrowOp : SPIRV_BinaryOp<"ISubBorrow", SPIRV_AnyStruct, SPIRV_Integer,
                                     [NoSideEffect]> {
   let summary = [{
     Result is the unsigned integer subtraction of Operand 2 from Operand 1,
     and what it needed to borrow.
   }];
 
   let description = [{
     Result Type must be from OpTypeStruct.  The struct must have two
let description = [{
 
     ```mlir
     %2 = spirv.ISubBorrow %0, %1 : !spirv.struct<(i32, i32)>
     %2 = spirv.ISubBorrow %0, %1 : !spirv.struct<(vector<2xi32>, vector<2xi32>)>
     ```
   }];
 
   let arguments = (ins
-    SPV_ScalarOrVectorOf<SPV_Integer>:$operand1,
-    SPV_ScalarOrVectorOf<SPV_Integer>:$operand2
+    SPIRV_ScalarOrVectorOf<SPIRV_Integer>:$operand1,
+    SPIRV_ScalarOrVectorOf<SPIRV_Integer>:$operand2
   );
 
   let results = (outs
-    SPV_AnyStruct:$result
+    SPIRV_AnyStruct:$result
   );
 
   let builders = [
     OpBuilder<(ins "Value":$operand1, "Value":$operand2), [{
       build($_builder, $_state,
             ::mlir::spirv::StructType::get({operand1.getType(), operand1.getType()}),
             operand1, operand2);
     }]>
   ];
 
   let hasVerifier = 1;
 }
 
 // -----
 
-def SPV_SDivOp : SPV_ArithmeticBinaryOp<"SDiv",
-                                        SPV_Integer,
+def SPIRV_SDivOp : SPIRV_ArithmeticBinaryOp<"SDiv",
+                                        SPIRV_Integer,
                                         [UsableInSpecConstantOp]> {
   let summary = "Signed-integer division of Operand 1 divided by Operand 2.";
 
   let description = [{
     Result Type must be a scalar or vector of integer type.
 
      The type of Operand 1 and Operand 2  must be a scalar or vector of
     integer type.  They must have the same number of components as Result
let description = [{
     %5 = spirv.SDiv %2, %3 : vector<4xi32>
 
     ```
   }];
 }
 
 // -----
 
-def SPV_SModOp : SPV_ArithmeticBinaryOp<"SMod",
-                                        SPV_Integer,
+def SPIRV_SModOp : SPIRV_ArithmeticBinaryOp<"SMod",
+                                        SPIRV_Integer,
                                         [UsableInSpecConstantOp]> {
   let summary = [{
     Signed remainder operation for the remainder whose sign matches the sign
     of Operand 2.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of integer type.
let description = [{
     %5 = spirv.SMod %2, %3 : vector<4xi32>
 
     ```
   }];
 }
 
 // -----
 
-def SPV_SNegateOp : SPV_ArithmeticUnaryOp<"SNegate",
-                                          SPV_Integer,
+def SPIRV_SNegateOp : SPIRV_ArithmeticUnaryOp<"SNegate",
+                                          SPIRV_Integer,
                                           [UsableInSpecConstantOp]> {
   let summary = "Signed-integer subtract of Operand from zero.";
 
   let description = [{
     Result Type must be a scalar or vector of integer type.
 
     Operand’s type  must be a scalar or vector of integer type.  It must
     have the same number of components as Result Type.  The component width
let description = [{
     %1 = spirv.SNegate %0 : i32
     %3 = spirv.SNegate %2 : vector<4xi32>
     ```
   }];
 }
 
 // -----
 
-def SPV_SRemOp : SPV_ArithmeticBinaryOp<"SRem",
-                                        SPV_Integer,
+def SPIRV_SRemOp : SPIRV_ArithmeticBinaryOp<"SRem",
+                                        SPIRV_Integer,
                                         [UsableInSpecConstantOp]> {
   let summary = [{
     Signed remainder operation for the remainder whose sign matches the sign
     of Operand 1.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of integer type.
let description = [{
     %5 = spirv.SRem %2, %3 : vector<4xi32>
 
     ```
   }];
 }
 
 // -----
 
-def SPV_UDivOp : SPV_ArithmeticBinaryOp<"UDiv",
-                                        SPV_Integer,
+def SPIRV_UDivOp : SPIRV_ArithmeticBinaryOp<"UDiv",
+                                        SPIRV_Integer,
                                         [UnsignedOp, UsableInSpecConstantOp]> {
   let summary = "Unsigned-integer division of Operand 1 divided by Operand 2.";
 
   let description = [{
     Result Type must be a scalar or vector of integer type, whose Signedness
     operand is 0.
 
      The types of Operand 1 and Operand 2 both must be the same as Result
let description = [{
     %5 = spirv.UDiv %2, %3 : vector<4xi32>
 
     ```
   }];
 }
 
 // -----
 
-def SPV_VectorTimesScalarOp : SPV_Op<"VectorTimesScalar", [NoSideEffect]> {
+def SPIRV_VectorTimesScalarOp : SPIRV_Op<"VectorTimesScalar", [NoSideEffect]> {
   let summary = "Scale a floating-point vector.";
 
   let description = [{
     Result Type must be a vector of floating-point type.
 
      The type of Vector must be the same as Result Type. Each component of
     Vector is multiplied by Scalar.
 
     Scalar must have the same type as the Component Type in Result Type.
 
     <!-- End of AutoGen section -->
 
     #### Example:
 
     ```mlir
     %0 = spirv.VectorTimesScalar %vector, %scalar : vector<4xf32>
     ```
   }];
 
   let arguments = (ins
-    VectorOfLengthAndType<[2, 3, 4], [SPV_Float]>:$vector,
-    SPV_Float:$scalar
+    VectorOfLengthAndType<[2, 3, 4], [SPIRV_Float]>:$vector,
+    SPIRV_Float:$scalar
   );
 
   let results = (outs
-    VectorOfLengthAndType<[2, 3, 4], [SPV_Float]>:$result
+    VectorOfLengthAndType<[2, 3, 4], [SPIRV_Float]>:$result
   );
 
   let assemblyFormat = "operands attr-dict `:` `(` type(operands) `)` `->` type($result)";
 }
 
 // -----
 
-def SPV_UModOp : SPV_ArithmeticBinaryOp<"UMod",
-                                        SPV_Integer,
+def SPIRV_UModOp : SPIRV_ArithmeticBinaryOp<"UMod",
+                                        SPIRV_Integer,
                                         [UnsignedOp, UsableInSpecConstantOp]> {
   let summary = "Unsigned modulo operation of Operand 1 modulo Operand 2.";
 
   let description = [{
     Result Type must be a scalar or vector of integer type, whose Signedness
     operand is 0.
 
      The types of Operand 1 and Operand 2 both must be the same as Result

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td

 //===-- SPIRVAtomicOps.td - MLIR SPIR-V Atomic Ops ---------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains atomic ops for the SPIR-V dialect. It corresponds to
 // "3.32.18. Atomic Instructions" of the SPIR-V specification.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef MLIR_DIALECT_SPIRV_IR_ATOMIC_OPS
 #define MLIR_DIALECT_SPIRV_IR_ATOMIC_OPS
 
-class SPV_AtomicUpdateOp<string mnemonic, list<Trait> traits = []> :
-  SPV_Op<mnemonic, traits> {
+class SPIRV_AtomicUpdateOp<string mnemonic, list<Trait> traits = []> :
+  SPIRV_Op<mnemonic, traits> {
   let arguments = (ins
-    SPV_AnyPtr:$pointer,
-    SPV_ScopeAttr:$memory_scope,
-    SPV_MemorySemanticsAttr:$semantics
+    SPIRV_AnyPtr:$pointer,
+    SPIRV_ScopeAttr:$memory_scope,
+    SPIRV_MemorySemanticsAttr:$semantics
   );
 
   let results = (outs
-    SPV_Integer:$result
+    SPIRV_Integer:$result
   );
 }
 
-class SPV_AtomicUpdateWithValueOp<string mnemonic, list<Trait> traits = []> :
-  SPV_Op<mnemonic, traits> {
+class SPIRV_AtomicUpdateWithValueOp<string mnemonic, list<Trait> traits = []> :
+  SPIRV_Op<mnemonic, traits> {
   let arguments = (ins
-    SPV_AnyPtr:$pointer,
-    SPV_ScopeAttr:$memory_scope,
-    SPV_MemorySemanticsAttr:$semantics,
-    SPV_Integer:$value
+    SPIRV_AnyPtr:$pointer,
+    SPIRV_ScopeAttr:$memory_scope,
+    SPIRV_MemorySemanticsAttr:$semantics,
+    SPIRV_Integer:$value
   );
 
   let results = (outs
-    SPV_Integer:$result
+    SPIRV_Integer:$result
   );
 
   let builders = [
     OpBuilder<(ins "Value":$pointer, "::mlir::spirv::Scope":$scope,
       "::mlir::spirv::MemorySemantics":$memory, "Value":$value),
     [{build($_builder, $_state, value.getType(), pointer, scope, memory, value);}]>
   ];
 }
 
 // -----
 
-def SPV_AtomicAndOp : SPV_AtomicUpdateWithValueOp<"AtomicAnd", []> {
+def SPIRV_AtomicAndOp : SPIRV_AtomicUpdateWithValueOp<"AtomicAnd", []> {
   let summary = [{
     Perform the following steps atomically with respect to any other atomic
     accesses within Scope to the same location:
   }];
 
   let description = [{
     1) load through Pointer to get an Original Value,
 
let description = [{
     %0 = spirv.AtomicAnd "Device" "None" %pointer, %value :
                        !spirv.ptr<i32, StorageBuffer>
     ```
   }];
 }
 
 // -----
 
-def SPV_AtomicCompareExchangeOp : SPV_Op<"AtomicCompareExchange", []> {
+def SPIRV_AtomicCompareExchangeOp : SPIRV_Op<"AtomicCompareExchange", []> {
   let summary = [{
     Perform the following steps atomically with respect to any other atomic
     accesses within Scope to the same location:
   }];
 
   let description = [{
     1) load through Pointer to get an Original Value,
 
let description = [{
     ```
     %0 = spirv.AtomicCompareExchange "Workgroup" "Acquire" "None"
                                     %pointer, %value, %comparator
                                     : !spirv.ptr<i32, WorkGroup>
     ```
   }];
 
   let arguments = (ins
-    SPV_AnyPtr:$pointer,
-    SPV_ScopeAttr:$memory_scope,
-    SPV_MemorySemanticsAttr:$equal_semantics,
-    SPV_MemorySemanticsAttr:$unequal_semantics,
-    SPV_Integer:$value,
-    SPV_Integer:$comparator
+    SPIRV_AnyPtr:$pointer,
+    SPIRV_ScopeAttr:$memory_scope,
+    SPIRV_MemorySemanticsAttr:$equal_semantics,
+    SPIRV_MemorySemanticsAttr:$unequal_semantics,
+    SPIRV_Integer:$value,
+    SPIRV_Integer:$comparator
   );
 
   let results = (outs
-    SPV_Integer:$result
+    SPIRV_Integer:$result
   );
 }
 
 // -----
 
-def SPV_AtomicCompareExchangeWeakOp : SPV_Op<"AtomicCompareExchangeWeak", []> {
+def SPIRV_AtomicCompareExchangeWeakOp : SPIRV_Op<"AtomicCompareExchangeWeak", []> {
   let summary = "Deprecated (use OpAtomicCompareExchange).";
 
   let description = [{
     Has the same semantics as OpAtomicCompareExchange.
 
     Memory must be a valid memory Scope.
 
     <!-- End of AutoGen section -->
let description = [{
     ```mlir
     %0 = spirv.AtomicCompareExchangeWeak "Workgroup" "Acquire" "None"
                                        %pointer, %value, %comparator
                                        : !spirv.ptr<i32, WorkGroup>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_3>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_3>,
     Extension<[]>,
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 
   let arguments = (ins
-    SPV_AnyPtr:$pointer,
-    SPV_ScopeAttr:$memory_scope,
-    SPV_MemorySemanticsAttr:$equal_semantics,
-    SPV_MemorySemanticsAttr:$unequal_semantics,
-    SPV_Integer:$value,
-    SPV_Integer:$comparator
+    SPIRV_AnyPtr:$pointer,
+    SPIRV_ScopeAttr:$memory_scope,
+    SPIRV_MemorySemanticsAttr:$equal_semantics,
+    SPIRV_MemorySemanticsAttr:$unequal_semantics,
+    SPIRV_Integer:$value,
+    SPIRV_Integer:$comparator
   );
 
   let results = (outs
-    SPV_Integer:$result
+    SPIRV_Integer:$result
   );
 }
 
 // -----
 
-def SPV_AtomicExchangeOp : SPV_Op<"AtomicExchange", []> {
+def SPIRV_AtomicExchangeOp : SPIRV_Op<"AtomicExchange", []> {
   let summary = [{
     Perform the following steps atomically with respect to any other atomic
     accesses within Scope to the same location:
   }];
 
   let description = [{
     1) load through Pointer to get an Original Value,
 
let description = [{
 
     ```
     %0 = spirv.AtomicExchange "Workgroup" "Acquire" %pointer, %value,
                             : !spirv.ptr<i32, WorkGroup>
     ```
   }];
 
   let arguments = (ins
-    SPV_AnyPtr:$pointer,
-    SPV_ScopeAttr:$memory_scope,
-    SPV_MemorySemanticsAttr:$semantics,
-    SPV_Numerical:$value
+    SPIRV_AnyPtr:$pointer,
+    SPIRV_ScopeAttr:$memory_scope,
+    SPIRV_MemorySemanticsAttr:$semantics,
+    SPIRV_Numerical:$value
   );
 
   let results = (outs
-    SPV_Numerical:$result
+    SPIRV_Numerical:$result
   );
 }
 
 // -----
 
-def SPV_EXTAtomicFAddOp : SPV_ExtVendorOp<"AtomicFAdd", []> {
+def SPIRV_EXTAtomicFAddOp : SPIRV_ExtVendorOp<"AtomicFAdd", []> {
   let summary = "TBD";
 
   let description = [{
 
 
     <!-- End of AutoGen section -->
 
     Perform the following steps atomically with respect to any other atomic
let description = [{
 
     ```mlir
     %0 = spirv.EXT.AtomicFAdd "Device" "None" %pointer, %value :
                            !spirv.ptr<f32, StorageBuffer>
     ```mlir
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
-    Extension<[SPV_EXT_shader_atomic_float_add]>,
-    Capability<[SPV_C_AtomicFloat16AddEXT, SPV_C_AtomicFloat32AddEXT, SPV_C_AtomicFloat64AddEXT]>
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[SPIRV_EXT_shader_atomic_float_add]>,
+    Capability<[SPIRV_C_AtomicFloat16AddEXT, SPIRV_C_AtomicFloat32AddEXT, SPIRV_C_AtomicFloat64AddEXT]>
   ];
 
   let arguments = (ins
-    SPV_AnyPtr:$pointer,
-    SPV_ScopeAttr:$memory_scope,
-    SPV_MemorySemanticsAttr:$semantics,
-    SPV_Float:$value
+    SPIRV_AnyPtr:$pointer,
+    SPIRV_ScopeAttr:$memory_scope,
+    SPIRV_MemorySemanticsAttr:$semantics,
+    SPIRV_Float:$value
   );
 
   let results = (outs
-    SPV_Float:$result
+    SPIRV_Float:$result
   );
 }
 
 // -----
 
-def SPV_AtomicIAddOp : SPV_AtomicUpdateWithValueOp<"AtomicIAdd", []> {
+def SPIRV_AtomicIAddOp : SPIRV_AtomicUpdateWithValueOp<"AtomicIAdd", []> {
   let summary = [{
     Perform the following steps atomically with respect to any other atomic
     accesses within Scope to the same location:
   }];
 
   let description = [{
     1) load through Pointer to get an Original Value,
 
let description = [{
     %0 = spirv.AtomicIAdd "Device" "None" %pointer, %value :
                         !spirv.ptr<i32, StorageBuffer>
     ```
   }];
 }
 
 // -----
 
-def SPV_AtomicIDecrementOp : SPV_AtomicUpdateOp<"AtomicIDecrement", []> {
+def SPIRV_AtomicIDecrementOp : SPIRV_AtomicUpdateOp<"AtomicIDecrement", []> {
   let summary = [{
     Perform the following steps atomically with respect to any other atomic
     accesses within Scope to the same location:
   }];
 
   let description = [{
     1) load through Pointer to get an Original Value,
 
let description = [{
     %0 = spirv.AtomicIDecrement "Device" "None" %pointer :
                               !spirv.ptr<i32, StorageBuffer>
     ```
   }];
 }
 
 // -----
 
-def SPV_AtomicIIncrementOp : SPV_AtomicUpdateOp<"AtomicIIncrement", []> {
+def SPIRV_AtomicIIncrementOp : SPIRV_AtomicUpdateOp<"AtomicIIncrement", []> {
   let summary = [{
     Perform the following steps atomically with respect to any other atomic
     accesses within Scope to the same location:
   }];
 
   let description = [{
     1) load through Pointer to get an Original Value,
 
let description = [{
     %0 = spirv.AtomicIncrement "Device" "None" %pointer :
                              !spirv.ptr<i32, StorageBuffer>
     ```
   }];
 }
 
 // -----
 
-def SPV_AtomicISubOp : SPV_AtomicUpdateWithValueOp<"AtomicISub", []> {
+def SPIRV_AtomicISubOp : SPIRV_AtomicUpdateWithValueOp<"AtomicISub", []> {
   let summary = [{
     Perform the following steps atomically with respect to any other atomic
     accesses within Scope to the same location:
   }];
 
   let description = [{
     1) load through Pointer to get an Original Value,
 
let description = [{
     %0 = spirv.AtomicISub "Device" "None" %pointer, %value :
                         !spirv.ptr<i32, StorageBuffer>
     ```
   }];
 }
 
 // -----
 
-def SPV_AtomicOrOp : SPV_AtomicUpdateWithValueOp<"AtomicOr", []> {
+def SPIRV_AtomicOrOp : SPIRV_AtomicUpdateWithValueOp<"AtomicOr", []> {
   let summary = [{
     Perform the following steps atomically with respect to any other atomic
     accesses within Scope to the same location:
   }];
 
   let description = [{
     1) load through Pointer to get an Original Value,
 
let description = [{
     %0 = spirv.AtomicOr "Device" "None" %pointer, %value :
                       !spirv.ptr<i32, StorageBuffer>
     ```
   }];
 }
 
 // -----
 
-def SPV_AtomicSMaxOp : SPV_AtomicUpdateWithValueOp<"AtomicSMax", []> {
+def SPIRV_AtomicSMaxOp : SPIRV_AtomicUpdateWithValueOp<"AtomicSMax", []> {
   let summary = [{
     Perform the following steps atomically with respect to any other atomic
     accesses within Scope to the same location:
   }];
 
   let description = [{
     1) load through Pointer to get an Original Value,
 
let description = [{
     %0 = spirv.AtomicSMax "Device" "None" %pointer, %value :
                         !spirv.ptr<i32, StorageBuffer>
     ```
   }];
 }
 
 // -----
 
-def SPV_AtomicSMinOp : SPV_AtomicUpdateWithValueOp<"AtomicSMin", []> {
+def SPIRV_AtomicSMinOp : SPIRV_AtomicUpdateWithValueOp<"AtomicSMin", []> {
   let summary = [{
     Perform the following steps atomically with respect to any other atomic
     accesses within Scope to the same location:
   }];
 
   let description = [{
     1) load through Pointer to get an Original Value,
 
let description = [{
     %0 = spirv.AtomicSMin "Device" "None" %pointer, %value :
                         !spirv.ptr<i32, StorageBuffer>
     ```
   }];
 }
 
 // -----
 
-def SPV_AtomicUMaxOp : SPV_AtomicUpdateWithValueOp<"AtomicUMax", [UnsignedOp]> {
+def SPIRV_AtomicUMaxOp : SPIRV_AtomicUpdateWithValueOp<"AtomicUMax", [UnsignedOp]> {
   let summary = [{
     Perform the following steps atomically with respect to any other atomic
     accesses within Scope to the same location:
   }];
 
   let description = [{
     1) load through Pointer to get an Original Value,
 
let description = [{
     %0 = spirv.AtomicUMax "Device" "None" %pointer, %value :
                         !spirv.ptr<i32, StorageBuffer>
     ```
   }];
 }
 
 // -----
 
-def SPV_AtomicUMinOp : SPV_AtomicUpdateWithValueOp<"AtomicUMin", [UnsignedOp]> {
+def SPIRV_AtomicUMinOp : SPIRV_AtomicUpdateWithValueOp<"AtomicUMin", [UnsignedOp]> {
   let summary = [{
     Perform the following steps atomically with respect to any other atomic
     accesses within Scope to the same location:
   }];
 
   let description = [{
     1) load through Pointer to get an Original Value,
 
let description = [{
     %0 = spirv.AtomicUMin "Device" "None" %pointer, %value :
                         !spirv.ptr<i32, StorageBuffer>
     ```
   }];
 }
 
 // -----
 
-def SPV_AtomicXorOp : SPV_AtomicUpdateWithValueOp<"AtomicXor", []> {
+def SPIRV_AtomicXorOp : SPIRV_AtomicUpdateWithValueOp<"AtomicXor", []> {
   let summary = [{
     Perform the following steps atomically with respect to any other atomic
     accesses within Scope to the same location:
   }];
 
   let description = [{
     1) load through Pointer to get an Original Value,
 

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAttributes.td

 //
 //===----------------------------------------------------------------------===//
 
 #ifndef MLIR_DIALECT_SPIRV_IR_TARGET_AND_ABI
 #define MLIR_DIALECT_SPIRV_IR_TARGET_AND_ABI
 
 include "mlir/Dialect/SPIRV/IR/SPIRVBase.td"
 
-class SPV_Attr<string attrName, string attrMnemonic>
+class SPIRV_Attr<string attrName, string attrMnemonic>
     : AttrDef<SPIRV_Dialect, attrName> {
   let mnemonic = attrMnemonic;
 }
 
 // For entry functions, this attribute specifies information related to entry
 // points in the generated SPIR-V module:
 // 1) WorkGroup Size.
-def SPV_EntryPointABIAttr : SPV_Attr<"EntryPointABI", "entry_point_abi"> {
+def SPIRV_EntryPointABIAttr : SPIRV_Attr<"EntryPointABI", "entry_point_abi"> {
   let parameters = (ins OptionalParameter<"DenseIntElementsAttr">:$local_size);
   let assemblyFormat = "`<` struct(params) `>`";
 }
 
-def SPV_ExtensionArrayAttr : TypedArrayAttrBase<
-    SPV_ExtensionAttr, "SPIR-V extension array attribute">;
+def SPIRV_ExtensionArrayAttr : TypedArrayAttrBase<
+    SPIRV_ExtensionAttr, "SPIR-V extension array attribute">;
 
-def SPV_CapabilityArrayAttr : TypedArrayAttrBase<
-    SPV_CapabilityAttr, "SPIR-V capability array attribute">;
+def SPIRV_CapabilityArrayAttr : TypedArrayAttrBase<
+    SPIRV_CapabilityAttr, "SPIR-V capability array attribute">;
 
 // Description of cooperative matrix operations supported on the
 // target. Represents `VkCooperativeMatrixPropertiesNV`. See
 // https://www.khronos.org/registry/vulkan/specs/1.2-extensions/man/html/VkCooperativeMatrixPropertiesNV.html
-def SPV_CooperativeMatrixPropertiesNVAttr :
-    SPV_Attr<"CooperativeMatrixPropertiesNV", "coop_matrix_props"> {
+def SPIRV_CooperativeMatrixPropertiesNVAttr :
+    SPIRV_Attr<"CooperativeMatrixPropertiesNV", "coop_matrix_props"> {
   let parameters = (ins
     "int":$m_size,
     "int":$n_size,
     "int":$k_size,
     "mlir::Type":$a_type,
     "mlir::Type":$b_type,
     "mlir::Type":$c_type,
     "mlir::Type":$result_type,
     "mlir::spirv::ScopeAttr":$scope
   );
   let assemblyFormat = "`<` struct(params) `>`";
 }
 
-def SPV_CooperativeMatrixPropertiesNVArrayAttr :
-    TypedArrayAttrBase<SPV_CooperativeMatrixPropertiesNVAttr,
+def SPIRV_CooperativeMatrixPropertiesNVArrayAttr :
+    TypedArrayAttrBase<SPIRV_CooperativeMatrixPropertiesNVAttr,
                        "CooperativeMatrixPropertiesNV array attribute">;
 
 // Description of the supported joint matrix operations. See
-// https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_joint_matrix.asciidoc
-def SPV_JointMatrixPropertiesINTELAttr :
-    SPV_Attr<"JointMatrixPropertiesINTEL", "joint_matrix_props"> {
+// https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPIRV_INTEL_joint_matrix.asciidoc
+def SPIRV_JointMatrixPropertiesINTELAttr :
+    SPIRV_Attr<"JointMatrixPropertiesINTEL", "joint_matrix_props"> {
   let parameters = (ins
     "int":$m_size,
     "int":$n_size,
     "int":$k_size,
     "mlir::Type":$a_type,
     "mlir::Type":$b_type,
     "mlir::Type":$c_type,
     "mlir::Type":$result_type,
     "mlir::spirv::ScopeAttr":$scope
   );
   let assemblyFormat = "`<` struct(params) `>`";
 }
 
-def SPV_JointMatrixPropertiesINTELArrayAttr :
-    TypedArrayAttrBase<SPV_JointMatrixPropertiesINTELAttr,
+def SPIRV_JointMatrixPropertiesINTELArrayAttr :
+    TypedArrayAttrBase<SPIRV_JointMatrixPropertiesINTELAttr,
                        "JointMatrixPropertiesINTEL array attribute">;
 
 // This attribute specifies the limits for various resources on the target
 // architecture.
 //
 // See https://www.khronos.org/registry/vulkan/specs/1.2-extensions/html/vkspec.html#limits
 // for the complete list of limits and their explanation for the Vulkan API.
 // The following ones are those affecting SPIR-V CodeGen. Their default value
 // are the from Vulkan limit requirements:
 // https://www.khronos.org/registry/vulkan/specs/1.2-extensions/html/vkspec.html#limits-minmax
-def SPV_ResourceLimitsAttr : SPV_Attr<"ResourceLimits", "resource_limits"> {
+def SPIRV_ResourceLimitsAttr : SPIRV_Attr<"ResourceLimits", "resource_limits"> {
   let parameters = (ins
     // The maximum total storage size, in bytes, available for variables
     // declared with the Workgroup storage class.
     DefaultValuedParameter<"int", "16384">:$max_compute_shared_memory_size,
 
     // The maximum total number of compute shader invocations in a single local
     // workgroup.
     DefaultValuedParameter<"int", "128">:$max_compute_workgroup_invocations,

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBarrierOps.td

 
 #ifndef MLIR_DIALECT_SPIRV_IR_BARRIER_OPS
 #define MLIR_DIALECT_SPIRV_IR_BARRIER_OPS
 
 include "mlir/Dialect/SPIRV/IR/SPIRVBase.td"
 
 // -----
 
-def SPV_ControlBarrierOp : SPV_Op<"ControlBarrier", []> {
+def SPIRV_ControlBarrierOp : SPIRV_Op<"ControlBarrier", []> {
   let summary = [{
     Wait for other invocations of this module to reach the current point of
     execution.
   }];
 
   let description = [{
     All invocations of this module within Execution scope must reach this
     point of execution before any invocation will proceed beyond it.
let description = [{
 
     ```mlir
     spirv.ControlBarrier "Workgroup", "Device", "Acquire|UniformMemory"
 
     ```
   }];
 
   let arguments = (ins
-    SPV_ScopeAttr:$execution_scope,
-    SPV_ScopeAttr:$memory_scope,
-    SPV_MemorySemanticsAttr:$memory_semantics
+    SPIRV_ScopeAttr:$execution_scope,
+    SPIRV_ScopeAttr:$memory_scope,
+    SPIRV_MemorySemanticsAttr:$memory_semantics
   );
 
   let results = (outs);
 
   let assemblyFormat = [{
     $execution_scope `,` $memory_scope `,` $memory_semantics attr-dict
   }];
 }
 
 // -----
 
-def SPV_MemoryBarrierOp : SPV_Op<"MemoryBarrier", []> {
+def SPIRV_MemoryBarrierOp : SPIRV_Op<"MemoryBarrier", []> {
   let summary = "Control the order that memory accesses are observed.";
 
   let description = [{
     Ensures that memory accesses issued before this instruction will be
     observed before memory accesses issued after this instruction. This
     control is ensured only for memory accesses issued by this invocation
     and observed by another invocation executing within Memory scope. If the
     Vulkan memory model is declared, this ordering only applies to memory
let description = [{
 
     ```mlir
     spirv.MemoryBarrier "Device", "Acquire|UniformMemory"
 
     ```
   }];
 
   let arguments = (ins
-    SPV_ScopeAttr:$memory_scope,
-    SPV_MemorySemanticsAttr:$memory_semantics
+    SPIRV_ScopeAttr:$memory_scope,
+    SPIRV_MemorySemanticsAttr:$memory_semantics
   );
 
   let results = (outs);
 
   let assemblyFormat = "$memory_scope `,` $memory_semantics attr-dict";
 }
 
 #endif // MLIR_DIALECT_SPIRV_IR_BARRIER_OPS

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td

def SPIRV_Dialect : Dialect {
   }];
 }
 
 //===----------------------------------------------------------------------===//
 // Utility definitions
 //===----------------------------------------------------------------------===//
 
 // Wrapper over base BitEnumAttr to set common fields.
-class SPV_BitEnum<string name, string description,
+class SPIRV_BitEnum<string name, string description,
                     list<BitEnumAttrCaseBase> cases>
     : I32BitEnumAttr<name, description, cases> {
   let genSpecializedAttr = 0;
   let cppNamespace = "::mlir::spirv";
 }
-class SPV_BitEnumAttr<string name, string description, string mnemonic,
+class SPIRV_BitEnumAttr<string name, string description, string mnemonic,
                         list<BitEnumAttrCaseBase> cases> :
-    EnumAttr<SPIRV_Dialect, SPV_BitEnum<name, description, cases>, mnemonic> {
+    EnumAttr<SPIRV_Dialect, SPIRV_BitEnum<name, description, cases>, mnemonic> {
   let assemblyFormat = "`<` $value `>`";
 }
 
 // Wrapper over base I32EnumAttr to set common fields.
-class SPV_I32Enum<string name, string description,
+class SPIRV_I32Enum<string name, string description,
                     list<I32EnumAttrCase> cases>
     : I32EnumAttr<name, description, cases> {
   let genSpecializedAttr = 0;
   let cppNamespace = "::mlir::spirv";
 }
-class SPV_I32EnumAttr<string name, string description, string mnemonic,
+class SPIRV_I32EnumAttr<string name, string description, string mnemonic,
                         list<I32EnumAttrCase> cases> :
-    EnumAttr<SPIRV_Dialect, SPV_I32Enum<name, description, cases>, mnemonic> {
+    EnumAttr<SPIRV_Dialect, SPIRV_I32Enum<name, description, cases>, mnemonic> {
   let assemblyFormat = "`<` $value `>`";
 }
 
 //===----------------------------------------------------------------------===//
 // SPIR-V availability definitions
 //===----------------------------------------------------------------------===//
 
-def SPV_V_1_0 : I32EnumAttrCase<"V_1_0", 0, "v1.0">;
-def SPV_V_1_1 : I32EnumAttrCase<"V_1_1", 1, "v1.1">;
-def SPV_V_1_2 : I32EnumAttrCase<"V_1_2", 2, "v1.2">;
-def SPV_V_1_3 : I32EnumAttrCase<"V_1_3", 3, "v1.3">;
-def SPV_V_1_4 : I32EnumAttrCase<"V_1_4", 4, "v1.4">;
-def SPV_V_1_5 : I32EnumAttrCase<"V_1_5", 5, "v1.5">;
-def SPV_V_1_6 : I32EnumAttrCase<"V_1_6", 6, "v1.6">;
+def SPIRV_V_1_0 : I32EnumAttrCase<"V_1_0", 0, "v1.0">;
+def SPIRV_V_1_1 : I32EnumAttrCase<"V_1_1", 1, "v1.1">;
+def SPIRV_V_1_2 : I32EnumAttrCase<"V_1_2", 2, "v1.2">;
+def SPIRV_V_1_3 : I32EnumAttrCase<"V_1_3", 3, "v1.3">;
+def SPIRV_V_1_4 : I32EnumAttrCase<"V_1_4", 4, "v1.4">;
+def SPIRV_V_1_5 : I32EnumAttrCase<"V_1_5", 5, "v1.5">;
+def SPIRV_V_1_6 : I32EnumAttrCase<"V_1_6", 6, "v1.6">;
 
-def SPV_VersionAttr : SPV_I32EnumAttr<
+def SPIRV_VersionAttr : SPIRV_I32EnumAttr<
   "Version", "valid SPIR-V version", "version", [
-    SPV_V_1_0, SPV_V_1_1, SPV_V_1_2, SPV_V_1_3, SPV_V_1_4, SPV_V_1_5,
-    SPV_V_1_6]>;
+    SPIRV_V_1_0, SPIRV_V_1_1, SPIRV_V_1_2, SPIRV_V_1_3, SPIRV_V_1_4, SPIRV_V_1_5,
+    SPIRV_V_1_6]>;
 
 class MinVersion<I32EnumAttrCase min> : MinVersionBase<
-    "QueryMinVersionInterface", SPV_VersionAttr, min> {
+    "QueryMinVersionInterface", SPIRV_VersionAttr, min> {
   let cppNamespace = "::mlir::spirv";
   let interfaceDescription = [{
     Querying interface for minimal required SPIR-V version.
 
     This interface provides a `getMinVersion()` method to query the minimal
     required version for the implementing SPIR-V operation. The returned value
     is a `mlir::spirv::Version` enumerant.
   }];
 }
 
 class MaxVersion<I32EnumAttrCase max> : MaxVersionBase<
-    "QueryMaxVersionInterface", SPV_VersionAttr, max> {
+    "QueryMaxVersionInterface", SPIRV_VersionAttr, max> {
   let cppNamespace = "::mlir::spirv";
   let interfaceDescription = [{
     Querying interface for maximal supported SPIR-V version.
 
     This interface provides a `getMaxVersion()` method to query the maximal
     supported version for the implementing SPIR-V operation. The returned value
     is a `mlir::spirv::Version` enumerant.
   }];
let methods = [InterfaceMethod<
     "::llvm::SmallVector<::llvm::ArrayRef<::mlir::spirv::Capability>, 1>",
     "getCapabilities">];
 }
 
 //===----------------------------------------------------------------------===//
 // SPIR-V target GPU vendor and device definitions
 //===----------------------------------------------------------------------===//
 
-def SPV_DT_CPU           : I32EnumAttrCase<"CPU", 0>;
-def SPV_DT_DiscreteGPU   : I32EnumAttrCase<"DiscreteGPU", 1>;
-def SPV_DT_IntegratedGPU : I32EnumAttrCase<"IntegratedGPU", 2>;
+def SPIRV_DT_CPU           : I32EnumAttrCase<"CPU", 0>;
+def SPIRV_DT_DiscreteGPU   : I32EnumAttrCase<"DiscreteGPU", 1>;
+def SPIRV_DT_IntegratedGPU : I32EnumAttrCase<"IntegratedGPU", 2>;
 // An accelerator other than GPU or CPU
-def SPV_DT_Other         : I32EnumAttrCase<"Other", 3>;
+def SPIRV_DT_Other         : I32EnumAttrCase<"Other", 3>;
 // Information missing.
-def SPV_DT_Unknown       : I32EnumAttrCase<"Unknown", 4>;
+def SPIRV_DT_Unknown       : I32EnumAttrCase<"Unknown", 4>;
 
-def SPV_DeviceTypeAttr : SPV_I32EnumAttr<
+def SPIRV_DeviceTypeAttr : SPIRV_I32EnumAttr<
   "DeviceType", "valid SPIR-V device types", "device_type", [
-    SPV_DT_Other, SPV_DT_IntegratedGPU, SPV_DT_DiscreteGPU,
-    SPV_DT_CPU, SPV_DT_Unknown
+    SPIRV_DT_Other, SPIRV_DT_IntegratedGPU, SPIRV_DT_DiscreteGPU,
+    SPIRV_DT_CPU, SPIRV_DT_Unknown
   ]>;
 
-def SPV_V_AMD         : I32EnumAttrCase<"AMD", 0>;
-def SPV_V_Apple       : I32EnumAttrCase<"Apple", 1>;
-def SPV_V_ARM         : I32EnumAttrCase<"ARM", 2>;
-def SPV_V_Imagination : I32EnumAttrCase<"Imagination", 3>;
-def SPV_V_Intel       : I32EnumAttrCase<"Intel", 4>;
-def SPV_V_NVIDIA      : I32EnumAttrCase<"NVIDIA", 5>;
-def SPV_V_Qualcomm    : I32EnumAttrCase<"Qualcomm", 6>;
-def SPV_V_SwiftShader : I32EnumAttrCase<"SwiftShader", 7>;
-def SPV_V_Unknown     : I32EnumAttrCase<"Unknown", 0xff>;
+def SPIRV_V_AMD         : I32EnumAttrCase<"AMD", 0>;
+def SPIRV_V_Apple       : I32EnumAttrCase<"Apple", 1>;
+def SPIRV_V_ARM         : I32EnumAttrCase<"ARM", 2>;
+def SPIRV_V_Imagination : I32EnumAttrCase<"Imagination", 3>;
+def SPIRV_V_Intel       : I32EnumAttrCase<"Intel", 4>;
+def SPIRV_V_NVIDIA      : I32EnumAttrCase<"NVIDIA", 5>;
+def SPIRV_V_Qualcomm    : I32EnumAttrCase<"Qualcomm", 6>;
+def SPIRV_V_SwiftShader : I32EnumAttrCase<"SwiftShader", 7>;
+def SPIRV_V_Unknown     : I32EnumAttrCase<"Unknown", 0xff>;
 
-def SPV_VendorAttr : SPV_I32EnumAttr<
+def SPIRV_VendorAttr : SPIRV_I32EnumAttr<
   "Vendor", "recognized SPIR-V vendor strings", "vendor", [
-    SPV_V_AMD, SPV_V_Apple, SPV_V_ARM, SPV_V_Imagination,
-    SPV_V_Intel, SPV_V_NVIDIA, SPV_V_Qualcomm, SPV_V_SwiftShader,
-    SPV_V_Unknown
+    SPIRV_V_AMD, SPIRV_V_Apple, SPIRV_V_ARM, SPIRV_V_Imagination,
+    SPIRV_V_Intel, SPIRV_V_NVIDIA, SPIRV_V_Qualcomm, SPIRV_V_SwiftShader,
+    SPIRV_V_Unknown
   ]>;
 
 //===----------------------------------------------------------------------===//
 // SPIR-V extension definitions
 //===----------------------------------------------------------------------===//
 
 // Extensions known to the SPIR-V dialect.
 // https://github.com/KhronosGroup/SPIRV-Registry has the full list.
-def SPV_KHR_16bit_storage                    : I32EnumAttrCase<"SPV_KHR_16bit_storage", 0>;
-def SPV_KHR_8bit_storage                     : I32EnumAttrCase<"SPV_KHR_8bit_storage", 1>;
-def SPV_KHR_device_group                     : I32EnumAttrCase<"SPV_KHR_device_group", 2>;
-def SPV_KHR_float_controls                   : I32EnumAttrCase<"SPV_KHR_float_controls", 3>;
-def SPV_KHR_physical_storage_buffer          : I32EnumAttrCase<"SPV_KHR_physical_storage_buffer", 4>;
-def SPV_KHR_multiview                        : I32EnumAttrCase<"SPV_KHR_multiview", 5>;
-def SPV_KHR_no_integer_wrap_decoration       : I32EnumAttrCase<"SPV_KHR_no_integer_wrap_decoration", 6>;
-def SPV_KHR_post_depth_coverage              : I32EnumAttrCase<"SPV_KHR_post_depth_coverage", 7>;
-def SPV_KHR_shader_atomic_counter_ops        : I32EnumAttrCase<"SPV_KHR_shader_atomic_counter_ops", 8>;
-def SPV_KHR_shader_ballot                    : I32EnumAttrCase<"SPV_KHR_shader_ballot", 9>;
-def SPV_KHR_shader_clock                     : I32EnumAttrCase<"SPV_KHR_shader_clock", 10>;
-def SPV_KHR_shader_draw_parameters           : I32EnumAttrCase<"SPV_KHR_shader_draw_parameters", 11>;
-def SPV_KHR_storage_buffer_storage_class     : I32EnumAttrCase<"SPV_KHR_storage_buffer_storage_class", 12>;
-def SPV_KHR_subgroup_vote                    : I32EnumAttrCase<"SPV_KHR_subgroup_vote", 13>;
-def SPV_KHR_variable_pointers                : I32EnumAttrCase<"SPV_KHR_variable_pointers", 14>;
-def SPV_KHR_vulkan_memory_model              : I32EnumAttrCase<"SPV_KHR_vulkan_memory_model", 15>;
-def SPV_KHR_expect_assume                    : I32EnumAttrCase<"SPV_KHR_expect_assume", 16>;
-def SPV_KHR_integer_dot_product              : I32EnumAttrCase<"SPV_KHR_integer_dot_product", 17>;
-def SPV_KHR_bit_instructions                 : I32EnumAttrCase<"SPV_KHR_bit_instructions", 18>;
-def SPV_KHR_fragment_shading_rate            : I32EnumAttrCase<"SPV_KHR_fragment_shading_rate", 19>;
-def SPV_KHR_workgroup_memory_explicit_layout : I32EnumAttrCase<"SPV_KHR_workgroup_memory_explicit_layout", 20>;
-def SPV_KHR_ray_query                        : I32EnumAttrCase<"SPV_KHR_ray_query", 21>;
-def SPV_KHR_ray_tracing                      : I32EnumAttrCase<"SPV_KHR_ray_tracing", 22>;
-def SPV_KHR_subgroup_uniform_control_flow    : I32EnumAttrCase<"SPV_KHR_subgroup_uniform_control_flow", 23>;
-def SPV_KHR_linkonce_odr                     : I32EnumAttrCase<"SPV_KHR_linkonce_odr", 24>;
-def SPV_KHR_fragment_shader_barycentric      : I32EnumAttrCase<"SPV_KHR_fragment_shader_barycentric", 25>;
-def SPV_KHR_ray_cull_mask                    : I32EnumAttrCase<"SPV_KHR_ray_cull_mask", 26>;
-def SPV_KHR_uniform_group_instructions       : I32EnumAttrCase<"SPV_KHR_uniform_group_instructions", 27>;
-def SPV_KHR_subgroup_rotate                  : I32EnumAttrCase<"SPV_KHR_subgroup_rotate", 28>;
-
-def SPV_EXT_demote_to_helper_invocation  : I32EnumAttrCase<"SPV_EXT_demote_to_helper_invocation", 1000>;
-def SPV_EXT_descriptor_indexing          : I32EnumAttrCase<"SPV_EXT_descriptor_indexing", 1001>;
-def SPV_EXT_fragment_fully_covered       : I32EnumAttrCase<"SPV_EXT_fragment_fully_covered", 1002>;
-def SPV_EXT_fragment_invocation_density  : I32EnumAttrCase<"SPV_EXT_fragment_invocation_density", 1003>;
-def SPV_EXT_fragment_shader_interlock    : I32EnumAttrCase<"SPV_EXT_fragment_shader_interlock", 1004>;
-def SPV_EXT_physical_storage_buffer      : I32EnumAttrCase<"SPV_EXT_physical_storage_buffer", 1005>;
-def SPV_EXT_shader_stencil_export        : I32EnumAttrCase<"SPV_EXT_shader_stencil_export", 1006>;
-def SPV_EXT_shader_viewport_index_layer  : I32EnumAttrCase<"SPV_EXT_shader_viewport_index_layer", 1007>;
-def SPV_EXT_shader_atomic_float_add      : I32EnumAttrCase<"SPV_EXT_shader_atomic_float_add", 1008>;
-def SPV_EXT_shader_atomic_float_min_max  : I32EnumAttrCase<"SPV_EXT_shader_atomic_float_min_max", 1009>;
-def SPV_EXT_shader_image_int64           : I32EnumAttrCase<"SPV_EXT_shader_image_int64", 1010>;
-def SPV_EXT_shader_atomic_float16_add    : I32EnumAttrCase<"SPV_EXT_shader_atomic_float16_add", 1011>;
-
-def SPV_AMD_gpu_shader_half_float_fetch          : I32EnumAttrCase<"SPV_AMD_gpu_shader_half_float_fetch", 2000>;
-def SPV_AMD_shader_ballot                        : I32EnumAttrCase<"SPV_AMD_shader_ballot", 2001>;
-def SPV_AMD_shader_explicit_vertex_parameter     : I32EnumAttrCase<"SPV_AMD_shader_explicit_vertex_parameter", 2002>;
-def SPV_AMD_shader_fragment_mask                 : I32EnumAttrCase<"SPV_AMD_shader_fragment_mask", 2003>;
-def SPV_AMD_shader_image_load_store_lod          : I32EnumAttrCase<"SPV_AMD_shader_image_load_store_lod", 2004>;
-def SPV_AMD_texture_gather_bias_lod              : I32EnumAttrCase<"SPV_AMD_texture_gather_bias_lod", 2005>;
-def SPV_AMD_shader_early_and_late_fragment_tests : I32EnumAttrCase<"SPV_AMD_shader_early_and_late_fragment_tests", 2006>;
-
-def SPV_GOOGLE_decorate_string           : I32EnumAttrCase<"SPV_GOOGLE_decorate_string", 3000>;
-def SPV_GOOGLE_hlsl_functionality1       : I32EnumAttrCase<"SPV_GOOGLE_hlsl_functionality1", 3001>;
-def SPV_GOOGLE_user_type                 : I32EnumAttrCase<"SPV_GOOGLE_user_type", 3002>;
-
-def SPV_INTEL_device_side_avc_motion_estimation  : I32EnumAttrCase<"SPV_INTEL_device_side_avc_motion_estimation", 4000>;
-def SPV_INTEL_media_block_io                     : I32EnumAttrCase<"SPV_INTEL_media_block_io", 4001>;
-def SPV_INTEL_shader_integer_functions2          : I32EnumAttrCase<"SPV_INTEL_shader_integer_functions2", 4002>;
-def SPV_INTEL_subgroups                          : I32EnumAttrCase<"SPV_INTEL_subgroups", 4003>;
-def SPV_INTEL_float_controls2                    : I32EnumAttrCase<"SPV_INTEL_float_controls2", 4004>;
-def SPV_INTEL_function_pointers                  : I32EnumAttrCase<"SPV_INTEL_function_pointers", 4005>;
-def SPV_INTEL_inline_assembly                    : I32EnumAttrCase<"SPV_INTEL_inline_assembly", 4006>;
-def SPV_INTEL_vector_compute                     : I32EnumAttrCase<"SPV_INTEL_vector_compute", 4007>;
-def SPV_INTEL_variable_length_array              : I32EnumAttrCase<"SPV_INTEL_variable_length_array", 4008>;
-def SPV_INTEL_fpga_memory_attributes             : I32EnumAttrCase<"SPV_INTEL_fpga_memory_attributes", 4009>;
-def SPV_INTEL_arbitrary_precision_integers       : I32EnumAttrCase<"SPV_INTEL_arbitrary_precision_integers", 4010>;
-def SPV_INTEL_arbitrary_precision_floating_point : I32EnumAttrCase<"SPV_INTEL_arbitrary_precision_floating_point", 4011>;
-def SPV_INTEL_unstructured_loop_controls         : I32EnumAttrCase<"SPV_INTEL_unstructured_loop_controls", 4012>;
-def SPV_INTEL_fpga_loop_controls                 : I32EnumAttrCase<"SPV_INTEL_fpga_loop_controls", 4013>;
-def SPV_INTEL_kernel_attributes                  : I32EnumAttrCase<"SPV_INTEL_kernel_attributes", 4014>;
-def SPV_INTEL_fpga_memory_accesses               : I32EnumAttrCase<"SPV_INTEL_fpga_memory_accesses", 4015>;
-def SPV_INTEL_fpga_cluster_attributes            : I32EnumAttrCase<"SPV_INTEL_fpga_cluster_attributes", 4016>;
-def SPV_INTEL_loop_fuse                          : I32EnumAttrCase<"SPV_INTEL_loop_fuse", 4017>;
-def SPV_INTEL_fpga_buffer_location               : I32EnumAttrCase<"SPV_INTEL_fpga_buffer_location", 4018>;
-def SPV_INTEL_arbitrary_precision_fixed_point    : I32EnumAttrCase<"SPV_INTEL_arbitrary_precision_fixed_point", 4019>;
-def SPV_INTEL_usm_storage_classes                : I32EnumAttrCase<"SPV_INTEL_usm_storage_classes", 4020>;
-def SPV_INTEL_io_pipes                           : I32EnumAttrCase<"SPV_INTEL_io_pipes", 4021>;
-def SPV_INTEL_blocking_pipes                     : I32EnumAttrCase<"SPV_INTEL_blocking_pipes", 4022>;
-def SPV_INTEL_fpga_reg                           : I32EnumAttrCase<"SPV_INTEL_fpga_reg", 4023>;
-def SPV_INTEL_long_constant_composite            : I32EnumAttrCase<"SPV_INTEL_long_constant_composite", 4024>;
-def SPV_INTEL_optnone                            : I32EnumAttrCase<"SPV_INTEL_optnone", 4025>;
-def SPV_INTEL_debug_module                       : I32EnumAttrCase<"SPV_INTEL_debug_module", 4026>;
-def SPV_INTEL_fp_fast_math_mode                  : I32EnumAttrCase<"SPV_INTEL_fp_fast_math_mode", 4027>;
-def SPV_INTEL_memory_access_aliasing             : I32EnumAttrCase<"SPV_INTEL_memory_access_aliasing", 4028>;
-def SPV_INTEL_split_barrier                      : I32EnumAttrCase<"SPV_INTEL_split_barrier", 4029>;
-def SPV_INTEL_joint_matrix                       : I32EnumAttrCase<"SPV_INTEL_joint_matrix", 4030>;
-
-def SPV_NV_compute_shader_derivatives    : I32EnumAttrCase<"SPV_NV_compute_shader_derivatives", 5000>;
-def SPV_NV_cooperative_matrix            : I32EnumAttrCase<"SPV_NV_cooperative_matrix", 5001>;
-def SPV_NV_fragment_shader_barycentric   : I32EnumAttrCase<"SPV_NV_fragment_shader_barycentric", 5002>;
-def SPV_NV_geometry_shader_passthrough   : I32EnumAttrCase<"SPV_NV_geometry_shader_passthrough", 5003>;
-def SPV_NV_mesh_shader                   : I32EnumAttrCase<"SPV_NV_mesh_shader", 5004>;
-def SPV_NV_ray_tracing                   : I32EnumAttrCase<"SPV_NV_ray_tracing", 5005>;
-def SPV_NV_sample_mask_override_coverage : I32EnumAttrCase<"SPV_NV_sample_mask_override_coverage", 5006>;
-def SPV_NV_shader_image_footprint        : I32EnumAttrCase<"SPV_NV_shader_image_footprint", 5007>;
-def SPV_NV_shader_sm_builtins            : I32EnumAttrCase<"SPV_NV_shader_sm_builtins", 5008>;
-def SPV_NV_shader_subgroup_partitioned   : I32EnumAttrCase<"SPV_NV_shader_subgroup_partitioned", 5009>;
-def SPV_NV_shading_rate                  : I32EnumAttrCase<"SPV_NV_shading_rate", 5010>;
-def SPV_NV_stereo_view_rendering         : I32EnumAttrCase<"SPV_NV_stereo_view_rendering", 5011>;
-def SPV_NV_viewport_array2               : I32EnumAttrCase<"SPV_NV_viewport_array2", 5012>;
-def SPV_NV_bindless_texture              : I32EnumAttrCase<"SPV_NV_bindless_texture", 5013>;
-def SPV_NV_ray_tracing_motion_blur       : I32EnumAttrCase<"SPV_NV_ray_tracing_motion_blur", 5014>;
-
-def SPV_NVX_multiview_per_view_attributes : I32EnumAttrCase<"SPV_NVX_multiview_per_view_attributes", 5015>;
-
-def SPV_ExtensionAttr :
-    SPV_I32EnumAttr<"Extension", "supported SPIR-V extensions", "ext", [
-      SPV_KHR_16bit_storage, SPV_KHR_8bit_storage, SPV_KHR_device_group,
-      SPV_KHR_float_controls, SPV_KHR_physical_storage_buffer, SPV_KHR_multiview,
-      SPV_KHR_no_integer_wrap_decoration, SPV_KHR_post_depth_coverage,
-      SPV_KHR_shader_atomic_counter_ops, SPV_KHR_shader_ballot,
-      SPV_KHR_shader_clock, SPV_KHR_shader_draw_parameters,
-      SPV_KHR_storage_buffer_storage_class, SPV_KHR_subgroup_vote,
-      SPV_KHR_variable_pointers, SPV_KHR_vulkan_memory_model, SPV_KHR_expect_assume,
-      SPV_KHR_integer_dot_product, SPV_KHR_bit_instructions, SPV_KHR_fragment_shading_rate,
-      SPV_KHR_workgroup_memory_explicit_layout, SPV_KHR_ray_query,
-      SPV_KHR_ray_tracing, SPV_KHR_subgroup_uniform_control_flow, SPV_KHR_linkonce_odr,
-      SPV_KHR_fragment_shader_barycentric, SPV_KHR_ray_cull_mask,
-      SPV_KHR_uniform_group_instructions, SPV_KHR_subgroup_rotate,
-      SPV_EXT_demote_to_helper_invocation, SPV_EXT_descriptor_indexing,
-      SPV_EXT_fragment_fully_covered, SPV_EXT_fragment_invocation_density,
-      SPV_EXT_fragment_shader_interlock, SPV_EXT_physical_storage_buffer,
-      SPV_EXT_shader_stencil_export, SPV_EXT_shader_viewport_index_layer,
-      SPV_EXT_shader_atomic_float_add, SPV_EXT_shader_atomic_float_min_max,
-      SPV_EXT_shader_image_int64, SPV_EXT_shader_atomic_float16_add,
-      SPV_AMD_gpu_shader_half_float_fetch, SPV_AMD_shader_ballot,
-      SPV_AMD_shader_explicit_vertex_parameter, SPV_AMD_shader_fragment_mask,
-      SPV_AMD_shader_image_load_store_lod, SPV_AMD_texture_gather_bias_lod,
-      SPV_AMD_shader_early_and_late_fragment_tests,
-      SPV_GOOGLE_decorate_string, SPV_GOOGLE_hlsl_functionality1, SPV_GOOGLE_user_type,
-      SPV_INTEL_device_side_avc_motion_estimation, SPV_INTEL_media_block_io,
-      SPV_INTEL_shader_integer_functions2, SPV_INTEL_subgroups, SPV_INTEL_vector_compute,
-      SPV_INTEL_float_controls2, SPV_INTEL_function_pointers, SPV_INTEL_inline_assembly,
-      SPV_INTEL_variable_length_array, SPV_INTEL_fpga_memory_attributes,
-      SPV_INTEL_unstructured_loop_controls, SPV_INTEL_fpga_loop_controls,
-      SPV_INTEL_arbitrary_precision_integers, SPV_INTEL_arbitrary_precision_floating_point,
-      SPV_INTEL_kernel_attributes, SPV_INTEL_fpga_memory_accesses,
-      SPV_INTEL_fpga_cluster_attributes, SPV_INTEL_loop_fuse,
-      SPV_INTEL_fpga_buffer_location, SPV_INTEL_arbitrary_precision_fixed_point,
-      SPV_INTEL_usm_storage_classes, SPV_INTEL_io_pipes, SPV_INTEL_blocking_pipes,
-      SPV_INTEL_fpga_reg, SPV_INTEL_long_constant_composite, SPV_INTEL_optnone,
-      SPV_INTEL_debug_module, SPV_INTEL_fp_fast_math_mode,
-      SPV_INTEL_memory_access_aliasing, SPV_INTEL_split_barrier, SPV_INTEL_joint_matrix,
-      SPV_NV_compute_shader_derivatives, SPV_NV_cooperative_matrix,
-      SPV_NV_fragment_shader_barycentric, SPV_NV_geometry_shader_passthrough,
-      SPV_NV_mesh_shader, SPV_NV_ray_tracing, SPV_NV_sample_mask_override_coverage,
-      SPV_NV_shader_image_footprint, SPV_NV_shader_sm_builtins,
-      SPV_NV_shader_subgroup_partitioned, SPV_NV_shading_rate,
-      SPV_NV_stereo_view_rendering, SPV_NV_viewport_array2, SPV_NV_bindless_texture,
-      SPV_NV_ray_tracing_motion_blur, SPV_NVX_multiview_per_view_attributes
+def SPIRV_KHR_16bit_storage                    : I32EnumAttrCase<"SPIRV_KHR_16bit_storage", 0>;
+def SPIRV_KHR_8bit_storage                     : I32EnumAttrCase<"SPIRV_KHR_8bit_storage", 1>;
+def SPIRV_KHR_device_group                     : I32EnumAttrCase<"SPIRV_KHR_device_group", 2>;
+def SPIRV_KHR_float_controls                   : I32EnumAttrCase<"SPIRV_KHR_float_controls", 3>;
+def SPIRV_KHR_physical_storage_buffer          : I32EnumAttrCase<"SPIRV_KHR_physical_storage_buffer", 4>;
+def SPIRV_KHR_multiview                        : I32EnumAttrCase<"SPIRV_KHR_multiview", 5>;
+def SPIRV_KHR_no_integer_wrap_decoration       : I32EnumAttrCase<"SPIRV_KHR_no_integer_wrap_decoration", 6>;
+def SPIRV_KHR_post_depth_coverage              : I32EnumAttrCase<"SPIRV_KHR_post_depth_coverage", 7>;
+def SPIRV_KHR_shader_atomic_counter_ops        : I32EnumAttrCase<"SPIRV_KHR_shader_atomic_counter_ops", 8>;
+def SPIRV_KHR_shader_ballot                    : I32EnumAttrCase<"SPIRV_KHR_shader_ballot", 9>;
+def SPIRV_KHR_shader_clock                     : I32EnumAttrCase<"SPIRV_KHR_shader_clock", 10>;
+def SPIRV_KHR_shader_draw_parameters           : I32EnumAttrCase<"SPIRV_KHR_shader_draw_parameters", 11>;
+def SPIRV_KHR_storage_buffer_storage_class     : I32EnumAttrCase<"SPIRV_KHR_storage_buffer_storage_class", 12>;
+def SPIRV_KHR_subgroup_vote                    : I32EnumAttrCase<"SPIRV_KHR_subgroup_vote", 13>;
+def SPIRV_KHR_variable_pointers                : I32EnumAttrCase<"SPIRV_KHR_variable_pointers", 14>;
+def SPIRV_KHR_vulkan_memory_model              : I32EnumAttrCase<"SPIRV_KHR_vulkan_memory_model", 15>;
+def SPIRV_KHR_expect_assume                    : I32EnumAttrCase<"SPIRV_KHR_expect_assume", 16>;
+def SPIRV_KHR_integer_dot_product              : I32EnumAttrCase<"SPIRV_KHR_integer_dot_product", 17>;
+def SPIRV_KHR_bit_instructions                 : I32EnumAttrCase<"SPIRV_KHR_bit_instructions", 18>;
+def SPIRV_KHR_fragment_shading_rate            : I32EnumAttrCase<"SPIRV_KHR_fragment_shading_rate", 19>;
+def SPIRV_KHR_workgroup_memory_explicit_layout : I32EnumAttrCase<"SPIRV_KHR_workgroup_memory_explicit_layout", 20>;
+def SPIRV_KHR_ray_query                        : I32EnumAttrCase<"SPIRV_KHR_ray_query", 21>;
+def SPIRV_KHR_ray_tracing                      : I32EnumAttrCase<"SPIRV_KHR_ray_tracing", 22>;
+def SPIRV_KHR_subgroup_uniform_control_flow    : I32EnumAttrCase<"SPIRV_KHR_subgroup_uniform_control_flow", 23>;
+def SPIRV_KHR_linkonce_odr                     : I32EnumAttrCase<"SPIRV_KHR_linkonce_odr", 24>;
+def SPIRV_KHR_fragment_shader_barycentric      : I32EnumAttrCase<"SPIRV_KHR_fragment_shader_barycentric", 25>;
+def SPIRV_KHR_ray_cull_mask                    : I32EnumAttrCase<"SPIRV_KHR_ray_cull_mask", 26>;
+def SPIRV_KHR_uniform_group_instructions       : I32EnumAttrCase<"SPIRV_KHR_uniform_group_instructions", 27>;
+def SPIRV_KHR_subgroup_rotate                  : I32EnumAttrCase<"SPIRV_KHR_subgroup_rotate", 28>;
+
+def SPIRV_EXT_demote_to_helper_invocation  : I32EnumAttrCase<"SPIRV_EXT_demote_to_helper_invocation", 1000>;
+def SPIRV_EXT_descriptor_indexing          : I32EnumAttrCase<"SPIRV_EXT_descriptor_indexing", 1001>;
+def SPIRV_EXT_fragment_fully_covered       : I32EnumAttrCase<"SPIRV_EXT_fragment_fully_covered", 1002>;
+def SPIRV_EXT_fragment_invocation_density  : I32EnumAttrCase<"SPIRV_EXT_fragment_invocation_density", 1003>;
+def SPIRV_EXT_fragment_shader_interlock    : I32EnumAttrCase<"SPIRV_EXT_fragment_shader_interlock", 1004>;
+def SPIRV_EXT_physical_storage_buffer      : I32EnumAttrCase<"SPIRV_EXT_physical_storage_buffer", 1005>;
+def SPIRV_EXT_shader_stencil_export        : I32EnumAttrCase<"SPIRV_EXT_shader_stencil_export", 1006>;
+def SPIRV_EXT_shader_viewport_index_layer  : I32EnumAttrCase<"SPIRV_EXT_shader_viewport_index_layer", 1007>;
+def SPIRV_EXT_shader_atomic_float_add      : I32EnumAttrCase<"SPIRV_EXT_shader_atomic_float_add", 1008>;
+def SPIRV_EXT_shader_atomic_float_min_max  : I32EnumAttrCase<"SPIRV_EXT_shader_atomic_float_min_max", 1009>;
+def SPIRV_EXT_shader_image_int64           : I32EnumAttrCase<"SPIRV_EXT_shader_image_int64", 1010>;
+def SPIRV_EXT_shader_atomic_float16_add    : I32EnumAttrCase<"SPIRV_EXT_shader_atomic_float16_add", 1011>;
+
+def SPIRV_AMD_gpu_shader_half_float_fetch          : I32EnumAttrCase<"SPIRV_AMD_gpu_shader_half_float_fetch", 2000>;
+def SPIRV_AMD_shader_ballot                        : I32EnumAttrCase<"SPIRV_AMD_shader_ballot", 2001>;
+def SPIRV_AMD_shader_explicit_vertex_parameter     : I32EnumAttrCase<"SPIRV_AMD_shader_explicit_vertex_parameter", 2002>;
+def SPIRV_AMD_shader_fragment_mask                 : I32EnumAttrCase<"SPIRV_AMD_shader_fragment_mask", 2003>;
+def SPIRV_AMD_shader_image_load_store_lod          : I32EnumAttrCase<"SPIRV_AMD_shader_image_load_store_lod", 2004>;
+def SPIRV_AMD_texture_gather_bias_lod              : I32EnumAttrCase<"SPIRV_AMD_texture_gather_bias_lod", 2005>;
+def SPIRV_AMD_shader_early_and_late_fragment_tests : I32EnumAttrCase<"SPIRV_AMD_shader_early_and_late_fragment_tests", 2006>;
+
+def SPIRV_GOOGLE_decorate_string           : I32EnumAttrCase<"SPIRV_GOOGLE_decorate_string", 3000>;
+def SPIRV_GOOGLE_hlsl_functionality1       : I32EnumAttrCase<"SPIRV_GOOGLE_hlsl_functionality1", 3001>;
+def SPIRV_GOOGLE_user_type                 : I32EnumAttrCase<"SPIRV_GOOGLE_user_type", 3002>;
+
+def SPIRV_INTEL_device_side_avc_motion_estimation  : I32EnumAttrCase<"SPIRV_INTEL_device_side_avc_motion_estimation", 4000>;
+def SPIRV_INTEL_media_block_io                     : I32EnumAttrCase<"SPIRV_INTEL_media_block_io", 4001>;
+def SPIRV_INTEL_shader_integer_functions2          : I32EnumAttrCase<"SPIRV_INTEL_shader_integer_functions2", 4002>;
+def SPIRV_INTEL_subgroups                          : I32EnumAttrCase<"SPIRV_INTEL_subgroups", 4003>;
+def SPIRV_INTEL_float_controls2                    : I32EnumAttrCase<"SPIRV_INTEL_float_controls2", 4004>;
+def SPIRV_INTEL_function_pointers                  : I32EnumAttrCase<"SPIRV_INTEL_function_pointers", 4005>;
+def SPIRV_INTEL_inline_assembly                    : I32EnumAttrCase<"SPIRV_INTEL_inline_assembly", 4006>;
+def SPIRV_INTEL_vector_compute                     : I32EnumAttrCase<"SPIRV_INTEL_vector_compute", 4007>;
+def SPIRV_INTEL_variable_length_array              : I32EnumAttrCase<"SPIRV_INTEL_variable_length_array", 4008>;
+def SPIRV_INTEL_fpga_memory_attributes             : I32EnumAttrCase<"SPIRV_INTEL_fpga_memory_attributes", 4009>;
+def SPIRV_INTEL_arbitrary_precision_integers       : I32EnumAttrCase<"SPIRV_INTEL_arbitrary_precision_integers", 4010>;
+def SPIRV_INTEL_arbitrary_precision_floating_point : I32EnumAttrCase<"SPIRV_INTEL_arbitrary_precision_floating_point", 4011>;
+def SPIRV_INTEL_unstructured_loop_controls         : I32EnumAttrCase<"SPIRV_INTEL_unstructured_loop_controls", 4012>;
+def SPIRV_INTEL_fpga_loop_controls                 : I32EnumAttrCase<"SPIRV_INTEL_fpga_loop_controls", 4013>;
+def SPIRV_INTEL_kernel_attributes                  : I32EnumAttrCase<"SPIRV_INTEL_kernel_attributes", 4014>;
+def SPIRV_INTEL_fpga_memory_accesses               : I32EnumAttrCase<"SPIRV_INTEL_fpga_memory_accesses", 4015>;
+def SPIRV_INTEL_fpga_cluster_attributes            : I32EnumAttrCase<"SPIRV_INTEL_fpga_cluster_attributes", 4016>;
+def SPIRV_INTEL_loop_fuse                          : I32EnumAttrCase<"SPIRV_INTEL_loop_fuse", 4017>;
+def SPIRV_INTEL_fpga_buffer_location               : I32EnumAttrCase<"SPIRV_INTEL_fpga_buffer_location", 4018>;
+def SPIRV_INTEL_arbitrary_precision_fixed_point    : I32EnumAttrCase<"SPIRV_INTEL_arbitrary_precision_fixed_point", 4019>;
+def SPIRV_INTEL_usm_storage_classes                : I32EnumAttrCase<"SPIRV_INTEL_usm_storage_classes", 4020>;
+def SPIRV_INTEL_io_pipes                           : I32EnumAttrCase<"SPIRV_INTEL_io_pipes", 4021>;
+def SPIRV_INTEL_blocking_pipes                     : I32EnumAttrCase<"SPIRV_INTEL_blocking_pipes", 4022>;
+def SPIRV_INTEL_fpga_reg                           : I32EnumAttrCase<"SPIRV_INTEL_fpga_reg", 4023>;
+def SPIRV_INTEL_long_constant_composite            : I32EnumAttrCase<"SPIRV_INTEL_long_constant_composite", 4024>;
+def SPIRV_INTEL_optnone                            : I32EnumAttrCase<"SPIRV_INTEL_optnone", 4025>;
+def SPIRV_INTEL_debug_module                       : I32EnumAttrCase<"SPIRV_INTEL_debug_module", 4026>;
+def SPIRV_INTEL_fp_fast_math_mode                  : I32EnumAttrCase<"SPIRV_INTEL_fp_fast_math_mode", 4027>;
+def SPIRV_INTEL_memory_access_aliasing             : I32EnumAttrCase<"SPIRV_INTEL_memory_access_aliasing", 4028>;
+def SPIRV_INTEL_split_barrier                      : I32EnumAttrCase<"SPIRV_INTEL_split_barrier", 4029>;
+def SPIRV_INTEL_joint_matrix                       : I32EnumAttrCase<"SPIRV_INTEL_joint_matrix", 4030>;
+
+def SPIRV_NV_compute_shader_derivatives    : I32EnumAttrCase<"SPIRV_NV_compute_shader_derivatives", 5000>;
+def SPIRV_NV_cooperative_matrix            : I32EnumAttrCase<"SPIRV_NV_cooperative_matrix", 5001>;
+def SPIRV_NV_fragment_shader_barycentric   : I32EnumAttrCase<"SPIRV_NV_fragment_shader_barycentric", 5002>;
+def SPIRV_NV_geometry_shader_passthrough   : I32EnumAttrCase<"SPIRV_NV_geometry_shader_passthrough", 5003>;
+def SPIRV_NV_mesh_shader                   : I32EnumAttrCase<"SPIRV_NV_mesh_shader", 5004>;
+def SPIRV_NV_ray_tracing                   : I32EnumAttrCase<"SPIRV_NV_ray_tracing", 5005>;
+def SPIRV_NV_sample_mask_override_coverage : I32EnumAttrCase<"SPIRV_NV_sample_mask_override_coverage", 5006>;
+def SPIRV_NV_shader_image_footprint        : I32EnumAttrCase<"SPIRV_NV_shader_image_footprint", 5007>;
+def SPIRV_NV_shader_sm_builtins            : I32EnumAttrCase<"SPIRV_NV_shader_sm_builtins", 5008>;
+def SPIRV_NV_shader_subgroup_partitioned   : I32EnumAttrCase<"SPIRV_NV_shader_subgroup_partitioned", 5009>;
+def SPIRV_NV_shading_rate                  : I32EnumAttrCase<"SPIRV_NV_shading_rate", 5010>;
+def SPIRV_NV_stereo_view_rendering         : I32EnumAttrCase<"SPIRV_NV_stereo_view_rendering", 5011>;
+def SPIRV_NV_viewport_array2               : I32EnumAttrCase<"SPIRV_NV_viewport_array2", 5012>;
+def SPIRV_NV_bindless_texture              : I32EnumAttrCase<"SPIRV_NV_bindless_texture", 5013>;
+def SPIRV_NV_ray_tracing_motion_blur       : I32EnumAttrCase<"SPIRV_NV_ray_tracing_motion_blur", 5014>;
+
+def SPIRV_NVX_multiview_per_view_attributes : I32EnumAttrCase<"SPIRV_NVX_multiview_per_view_attributes", 5015>;
+
+def SPIRV_ExtensionAttr :
+    SPIRV_I32EnumAttr<"Extension", "supported SPIR-V extensions", "ext", [
+      SPIRV_KHR_16bit_storage, SPIRV_KHR_8bit_storage, SPIRV_KHR_device_group,
+      SPIRV_KHR_float_controls, SPIRV_KHR_physical_storage_buffer, SPIRV_KHR_multiview,
+      SPIRV_KHR_no_integer_wrap_decoration, SPIRV_KHR_post_depth_coverage,
+      SPIRV_KHR_shader_atomic_counter_ops, SPIRV_KHR_shader_ballot,
+      SPIRV_KHR_shader_clock, SPIRV_KHR_shader_draw_parameters,
+      SPIRV_KHR_storage_buffer_storage_class, SPIRV_KHR_subgroup_vote,
+      SPIRV_KHR_variable_pointers, SPIRV_KHR_vulkan_memory_model, SPIRV_KHR_expect_assume,
+      SPIRV_KHR_integer_dot_product, SPIRV_KHR_bit_instructions, SPIRV_KHR_fragment_shading_rate,
+      SPIRV_KHR_workgroup_memory_explicit_layout, SPIRV_KHR_ray_query,
+      SPIRV_KHR_ray_tracing, SPIRV_KHR_subgroup_uniform_control_flow, SPIRV_KHR_linkonce_odr,
+      SPIRV_KHR_fragment_shader_barycentric, SPIRV_KHR_ray_cull_mask,
+      SPIRV_KHR_uniform_group_instructions, SPIRV_KHR_subgroup_rotate,
+      SPIRV_EXT_demote_to_helper_invocation, SPIRV_EXT_descriptor_indexing,
+      SPIRV_EXT_fragment_fully_covered, SPIRV_EXT_fragment_invocation_density,
+      SPIRV_EXT_fragment_shader_interlock, SPIRV_EXT_physical_storage_buffer,
+      SPIRV_EXT_shader_stencil_export, SPIRV_EXT_shader_viewport_index_layer,
+      SPIRV_EXT_shader_atomic_float_add, SPIRV_EXT_shader_atomic_float_min_max,
+      SPIRV_EXT_shader_image_int64, SPIRV_EXT_shader_atomic_float16_add,
+      SPIRV_AMD_gpu_shader_half_float_fetch, SPIRV_AMD_shader_ballot,
+      SPIRV_AMD_shader_explicit_vertex_parameter, SPIRV_AMD_shader_fragment_mask,
+      SPIRV_AMD_shader_image_load_store_lod, SPIRV_AMD_texture_gather_bias_lod,
+      SPIRV_AMD_shader_early_and_late_fragment_tests,
+      SPIRV_GOOGLE_decorate_string, SPIRV_GOOGLE_hlsl_functionality1, SPIRV_GOOGLE_user_type,
+      SPIRV_INTEL_device_side_avc_motion_estimation, SPIRV_INTEL_media_block_io,
+      SPIRV_INTEL_shader_integer_functions2, SPIRV_INTEL_subgroups, SPIRV_INTEL_vector_compute,
+      SPIRV_INTEL_float_controls2, SPIRV_INTEL_function_pointers, SPIRV_INTEL_inline_assembly,
+      SPIRV_INTEL_variable_length_array, SPIRV_INTEL_fpga_memory_attributes,
+      SPIRV_INTEL_unstructured_loop_controls, SPIRV_INTEL_fpga_loop_controls,
+      SPIRV_INTEL_arbitrary_precision_integers, SPIRV_INTEL_arbitrary_precision_floating_point,
+      SPIRV_INTEL_kernel_attributes, SPIRV_INTEL_fpga_memory_accesses,
+      SPIRV_INTEL_fpga_cluster_attributes, SPIRV_INTEL_loop_fuse,
+      SPIRV_INTEL_fpga_buffer_location, SPIRV_INTEL_arbitrary_precision_fixed_point,
+      SPIRV_INTEL_usm_storage_classes, SPIRV_INTEL_io_pipes, SPIRV_INTEL_blocking_pipes,
+      SPIRV_INTEL_fpga_reg, SPIRV_INTEL_long_constant_composite, SPIRV_INTEL_optnone,
+      SPIRV_INTEL_debug_module, SPIRV_INTEL_fp_fast_math_mode,
+      SPIRV_INTEL_memory_access_aliasing, SPIRV_INTEL_split_barrier, SPIRV_INTEL_joint_matrix,
+      SPIRV_NV_compute_shader_derivatives, SPIRV_NV_cooperative_matrix,
+      SPIRV_NV_fragment_shader_barycentric, SPIRV_NV_geometry_shader_passthrough,
+      SPIRV_NV_mesh_shader, SPIRV_NV_ray_tracing, SPIRV_NV_sample_mask_override_coverage,
+      SPIRV_NV_shader_image_footprint, SPIRV_NV_shader_sm_builtins,
+      SPIRV_NV_shader_subgroup_partitioned, SPIRV_NV_shading_rate,
+      SPIRV_NV_stereo_view_rendering, SPIRV_NV_viewport_array2, SPIRV_NV_bindless_texture,
+      SPIRV_NV_ray_tracing_motion_blur, SPIRV_NVX_multiview_per_view_attributes
     ]>;
 
 //===----------------------------------------------------------------------===//
 // SPIR-V enum definitions
 //===----------------------------------------------------------------------===//
 
 // Begin enum section. Generated from SPIR-V spec; DO NOT MODIFY!
 
-def SPV_C_Matrix                                      : I32EnumAttrCase<"Matrix", 0>;
-def SPV_C_Addresses                                   : I32EnumAttrCase<"Addresses", 4>;
-def SPV_C_Linkage                                     : I32EnumAttrCase<"Linkage", 5>;
-def SPV_C_Kernel                                      : I32EnumAttrCase<"Kernel", 6>;
-def SPV_C_Float16                                     : I32EnumAttrCase<"Float16", 9>;
-def SPV_C_Float64                                     : I32EnumAttrCase<"Float64", 10>;
-def SPV_C_Int64                                       : I32EnumAttrCase<"Int64", 11>;
-def SPV_C_Groups                                      : I32EnumAttrCase<"Groups", 18> {
+def SPIRV_C_Matrix                                      : I32EnumAttrCase<"Matrix", 0>;
+def SPIRV_C_Addresses                                   : I32EnumAttrCase<"Addresses", 4>;
+def SPIRV_C_Linkage                                     : I32EnumAttrCase<"Linkage", 5>;
+def SPIRV_C_Kernel                                      : I32EnumAttrCase<"Kernel", 6>;
+def SPIRV_C_Float16                                     : I32EnumAttrCase<"Float16", 9>;
+def SPIRV_C_Float64                                     : I32EnumAttrCase<"Float64", 10>;
+def SPIRV_C_Int64                                       : I32EnumAttrCase<"Int64", 11>;
+def SPIRV_C_Groups                                      : I32EnumAttrCase<"Groups", 18> {
   list<Availability> availability = [
-    Extension<[SPV_AMD_shader_ballot]>
+    Extension<[SPIRV_AMD_shader_ballot]>
   ];
 }
-def SPV_C_Int16                                       : I32EnumAttrCase<"Int16", 22>;
-def SPV_C_Int8                                        : I32EnumAttrCase<"Int8", 39>;
-def SPV_C_Sampled1D                                   : I32EnumAttrCase<"Sampled1D", 43>;
-def SPV_C_SampledBuffer                               : I32EnumAttrCase<"SampledBuffer", 46>;
-def SPV_C_GroupNonUniform                             : I32EnumAttrCase<"GroupNonUniform", 61> {
+def SPIRV_C_Int16                                       : I32EnumAttrCase<"Int16", 22>;
+def SPIRV_C_Int8                                        : I32EnumAttrCase<"Int8", 39>;
+def SPIRV_C_Sampled1D                                   : I32EnumAttrCase<"Sampled1D", 43>;
+def SPIRV_C_SampledBuffer                               : I32EnumAttrCase<"SampledBuffer", 46>;
+def SPIRV_C_GroupNonUniform                             : I32EnumAttrCase<"GroupNonUniform", 61> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>
+    MinVersion<SPIRV_V_1_3>
   ];
 }
-def SPV_C_ShaderLayer                                 : I32EnumAttrCase<"ShaderLayer", 69> {
+def SPIRV_C_ShaderLayer                                 : I32EnumAttrCase<"ShaderLayer", 69> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>
+    MinVersion<SPIRV_V_1_5>
   ];
 }
-def SPV_C_ShaderViewportIndex                         : I32EnumAttrCase<"ShaderViewportIndex", 70> {
+def SPIRV_C_ShaderViewportIndex                         : I32EnumAttrCase<"ShaderViewportIndex", 70> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>
+    MinVersion<SPIRV_V_1_5>
   ];
 }
-def SPV_C_UniformDecoration                           : I32EnumAttrCase<"UniformDecoration", 71> {
+def SPIRV_C_UniformDecoration                           : I32EnumAttrCase<"UniformDecoration", 71> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_6>
+    MinVersion<SPIRV_V_1_6>
   ];
 }
-def SPV_C_SubgroupBallotKHR                           : I32EnumAttrCase<"SubgroupBallotKHR", 4423> {
+def SPIRV_C_SubgroupBallotKHR                           : I32EnumAttrCase<"SubgroupBallotKHR", 4423> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_shader_ballot]>
+    Extension<[SPIRV_KHR_shader_ballot]>
   ];
 }
-def SPV_C_SubgroupVoteKHR                             : I32EnumAttrCase<"SubgroupVoteKHR", 4431> {
+def SPIRV_C_SubgroupVoteKHR                             : I32EnumAttrCase<"SubgroupVoteKHR", 4431> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_subgroup_vote]>
+    Extension<[SPIRV_KHR_subgroup_vote]>
   ];
 }
-def SPV_C_StorageBuffer16BitAccess                    : I32EnumAttrCase<"StorageBuffer16BitAccess", 4433> {
+def SPIRV_C_StorageBuffer16BitAccess                    : I32EnumAttrCase<"StorageBuffer16BitAccess", 4433> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_16bit_storage]>
+    Extension<[SPIRV_KHR_16bit_storage]>
   ];
 }
-def SPV_C_StoragePushConstant16                       : I32EnumAttrCase<"StoragePushConstant16", 4435> {
+def SPIRV_C_StoragePushConstant16                       : I32EnumAttrCase<"StoragePushConstant16", 4435> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_16bit_storage]>
+    Extension<[SPIRV_KHR_16bit_storage]>
   ];
 }
-def SPV_C_StorageInputOutput16                        : I32EnumAttrCase<"StorageInputOutput16", 4436> {
+def SPIRV_C_StorageInputOutput16                        : I32EnumAttrCase<"StorageInputOutput16", 4436> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_16bit_storage]>
+    Extension<[SPIRV_KHR_16bit_storage]>
   ];
 }
-def SPV_C_DeviceGroup                                 : I32EnumAttrCase<"DeviceGroup", 4437> {
+def SPIRV_C_DeviceGroup                                 : I32EnumAttrCase<"DeviceGroup", 4437> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_device_group]>
+    Extension<[SPIRV_KHR_device_group]>
   ];
 }
-def SPV_C_AtomicStorageOps                            : I32EnumAttrCase<"AtomicStorageOps", 4445> {
+def SPIRV_C_AtomicStorageOps                            : I32EnumAttrCase<"AtomicStorageOps", 4445> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_shader_atomic_counter_ops]>
+    Extension<[SPIRV_KHR_shader_atomic_counter_ops]>
   ];
 }
-def SPV_C_SampleMaskPostDepthCoverage                 : I32EnumAttrCase<"SampleMaskPostDepthCoverage", 4447> {
+def SPIRV_C_SampleMaskPostDepthCoverage                 : I32EnumAttrCase<"SampleMaskPostDepthCoverage", 4447> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_post_depth_coverage]>
+    Extension<[SPIRV_KHR_post_depth_coverage]>
   ];
 }
-def SPV_C_StorageBuffer8BitAccess                     : I32EnumAttrCase<"StorageBuffer8BitAccess", 4448> {
+def SPIRV_C_StorageBuffer8BitAccess                     : I32EnumAttrCase<"StorageBuffer8BitAccess", 4448> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_8bit_storage]>
+    Extension<[SPIRV_KHR_8bit_storage]>
   ];
 }
-def SPV_C_StoragePushConstant8                        : I32EnumAttrCase<"StoragePushConstant8", 4450> {
+def SPIRV_C_StoragePushConstant8                        : I32EnumAttrCase<"StoragePushConstant8", 4450> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_8bit_storage]>
+    Extension<[SPIRV_KHR_8bit_storage]>
   ];
 }
-def SPV_C_DenormPreserve                              : I32EnumAttrCase<"DenormPreserve", 4464> {
+def SPIRV_C_DenormPreserve                              : I32EnumAttrCase<"DenormPreserve", 4464> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_float_controls]>
+    Extension<[SPIRV_KHR_float_controls]>
   ];
 }
-def SPV_C_DenormFlushToZero                           : I32EnumAttrCase<"DenormFlushToZero", 4465> {
+def SPIRV_C_DenormFlushToZero                           : I32EnumAttrCase<"DenormFlushToZero", 4465> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_float_controls]>
+    Extension<[SPIRV_KHR_float_controls]>
   ];
 }
-def SPV_C_SignedZeroInfNanPreserve                    : I32EnumAttrCase<"SignedZeroInfNanPreserve", 4466> {
+def SPIRV_C_SignedZeroInfNanPreserve                    : I32EnumAttrCase<"SignedZeroInfNanPreserve", 4466> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_float_controls]>
+    Extension<[SPIRV_KHR_float_controls]>
   ];
 }
-def SPV_C_RoundingModeRTE                             : I32EnumAttrCase<"RoundingModeRTE", 4467> {
+def SPIRV_C_RoundingModeRTE                             : I32EnumAttrCase<"RoundingModeRTE", 4467> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_float_controls]>
+    Extension<[SPIRV_KHR_float_controls]>
   ];
 }
-def SPV_C_RoundingModeRTZ                             : I32EnumAttrCase<"RoundingModeRTZ", 4468> {
+def SPIRV_C_RoundingModeRTZ                             : I32EnumAttrCase<"RoundingModeRTZ", 4468> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_float_controls]>
+    Extension<[SPIRV_KHR_float_controls]>
   ];
 }
-def SPV_C_ImageFootprintNV                            : I32EnumAttrCase<"ImageFootprintNV", 5282> {
+def SPIRV_C_ImageFootprintNV                            : I32EnumAttrCase<"ImageFootprintNV", 5282> {
   list<Availability> availability = [
-    Extension<[SPV_NV_shader_image_footprint]>
+    Extension<[SPIRV_NV_shader_image_footprint]>
   ];
 }
-def SPV_C_FragmentBarycentricKHR                      : I32EnumAttrCase<"FragmentBarycentricKHR", 5284> {
+def SPIRV_C_FragmentBarycentricKHR                      : I32EnumAttrCase<"FragmentBarycentricKHR", 5284> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_fragment_shader_barycentric, SPV_NV_fragment_shader_barycentric]>
+    Extension<[SPIRV_KHR_fragment_shader_barycentric, SPIRV_NV_fragment_shader_barycentric]>
   ];
 }
-def SPV_C_ComputeDerivativeGroupQuadsNV               : I32EnumAttrCase<"ComputeDerivativeGroupQuadsNV", 5288> {
+def SPIRV_C_ComputeDerivativeGroupQuadsNV               : I32EnumAttrCase<"ComputeDerivativeGroupQuadsNV", 5288> {
   list<Availability> availability = [
-    Extension<[SPV_NV_compute_shader_derivatives]>
+    Extension<[SPIRV_NV_compute_shader_derivatives]>
   ];
 }
-def SPV_C_GroupNonUniformPartitionedNV                : I32EnumAttrCase<"GroupNonUniformPartitionedNV", 5297> {
+def SPIRV_C_GroupNonUniformPartitionedNV                : I32EnumAttrCase<"GroupNonUniformPartitionedNV", 5297> {
   list<Availability> availability = [
-    Extension<[SPV_NV_shader_subgroup_partitioned]>
+    Extension<[SPIRV_NV_shader_subgroup_partitioned]>
   ];
 }
-def SPV_C_VulkanMemoryModel                           : I32EnumAttrCase<"VulkanMemoryModel", 5345> {
+def SPIRV_C_VulkanMemoryModel                           : I32EnumAttrCase<"VulkanMemoryModel", 5345> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>
+    MinVersion<SPIRV_V_1_5>
   ];
 }
-def SPV_C_VulkanMemoryModelDeviceScope                : I32EnumAttrCase<"VulkanMemoryModelDeviceScope", 5346> {
+def SPIRV_C_VulkanMemoryModelDeviceScope                : I32EnumAttrCase<"VulkanMemoryModelDeviceScope", 5346> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>
+    MinVersion<SPIRV_V_1_5>
   ];
 }
-def SPV_C_ComputeDerivativeGroupLinearNV              : I32EnumAttrCase<"ComputeDerivativeGroupLinearNV", 5350> {
+def SPIRV_C_ComputeDerivativeGroupLinearNV              : I32EnumAttrCase<"ComputeDerivativeGroupLinearNV", 5350> {
   list<Availability> availability = [
-    Extension<[SPV_NV_compute_shader_derivatives]>
+    Extension<[SPIRV_NV_compute_shader_derivatives]>
   ];
 }
-def SPV_C_BindlessTextureNV                           : I32EnumAttrCase<"BindlessTextureNV", 5390> {
+def SPIRV_C_BindlessTextureNV                           : I32EnumAttrCase<"BindlessTextureNV", 5390> {
   list<Availability> availability = [
-    Extension<[SPV_NV_bindless_texture]>
+    Extension<[SPIRV_NV_bindless_texture]>
   ];
 }
-def SPV_C_SubgroupShuffleINTEL                        : I32EnumAttrCase<"SubgroupShuffleINTEL", 5568> {
+def SPIRV_C_SubgroupShuffleINTEL                        : I32EnumAttrCase<"SubgroupShuffleINTEL", 5568> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_subgroups]>
+    Extension<[SPIRV_INTEL_subgroups]>
   ];
 }
-def SPV_C_SubgroupBufferBlockIOINTEL                  : I32EnumAttrCase<"SubgroupBufferBlockIOINTEL", 5569> {
+def SPIRV_C_SubgroupBufferBlockIOINTEL                  : I32EnumAttrCase<"SubgroupBufferBlockIOINTEL", 5569> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_subgroups]>
+    Extension<[SPIRV_INTEL_subgroups]>
   ];
 }
-def SPV_C_SubgroupImageBlockIOINTEL                   : I32EnumAttrCase<"SubgroupImageBlockIOINTEL", 5570> {
+def SPIRV_C_SubgroupImageBlockIOINTEL                   : I32EnumAttrCase<"SubgroupImageBlockIOINTEL", 5570> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_subgroups]>
+    Extension<[SPIRV_INTEL_subgroups]>
   ];
 }
-def SPV_C_SubgroupImageMediaBlockIOINTEL              : I32EnumAttrCase<"SubgroupImageMediaBlockIOINTEL", 5579> {
+def SPIRV_C_SubgroupImageMediaBlockIOINTEL              : I32EnumAttrCase<"SubgroupImageMediaBlockIOINTEL", 5579> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_media_block_io]>
+    Extension<[SPIRV_INTEL_media_block_io]>
   ];
 }
-def SPV_C_RoundToInfinityINTEL                        : I32EnumAttrCase<"RoundToInfinityINTEL", 5582> {
+def SPIRV_C_RoundToInfinityINTEL                        : I32EnumAttrCase<"RoundToInfinityINTEL", 5582> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_float_controls2]>
+    Extension<[SPIRV_INTEL_float_controls2]>
   ];
 }
-def SPV_C_FloatingPointModeINTEL                      : I32EnumAttrCase<"FloatingPointModeINTEL", 5583> {
+def SPIRV_C_FloatingPointModeINTEL                      : I32EnumAttrCase<"FloatingPointModeINTEL", 5583> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_float_controls2]>
+    Extension<[SPIRV_INTEL_float_controls2]>
   ];
 }
-def SPV_C_FunctionPointersINTEL                       : I32EnumAttrCase<"FunctionPointersINTEL", 5603> {
+def SPIRV_C_FunctionPointersINTEL                       : I32EnumAttrCase<"FunctionPointersINTEL", 5603> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_function_pointers]>
+    Extension<[SPIRV_INTEL_function_pointers]>
   ];
 }
-def SPV_C_IndirectReferencesINTEL                     : I32EnumAttrCase<"IndirectReferencesINTEL", 5604> {
+def SPIRV_C_IndirectReferencesINTEL                     : I32EnumAttrCase<"IndirectReferencesINTEL", 5604> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_function_pointers]>
+    Extension<[SPIRV_INTEL_function_pointers]>
   ];
 }
-def SPV_C_AsmINTEL                                    : I32EnumAttrCase<"AsmINTEL", 5606> {
+def SPIRV_C_AsmINTEL                                    : I32EnumAttrCase<"AsmINTEL", 5606> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_inline_assembly]>
+    Extension<[SPIRV_INTEL_inline_assembly]>
   ];
 }
-def SPV_C_AtomicFloat32MinMaxEXT                      : I32EnumAttrCase<"AtomicFloat32MinMaxEXT", 5612> {
+def SPIRV_C_AtomicFloat32MinMaxEXT                      : I32EnumAttrCase<"AtomicFloat32MinMaxEXT", 5612> {
   list<Availability> availability = [
-    Extension<[SPV_EXT_shader_atomic_float_min_max]>
+    Extension<[SPIRV_EXT_shader_atomic_float_min_max]>
   ];
 }
-def SPV_C_AtomicFloat64MinMaxEXT                      : I32EnumAttrCase<"AtomicFloat64MinMaxEXT", 5613> {
+def SPIRV_C_AtomicFloat64MinMaxEXT                      : I32EnumAttrCase<"AtomicFloat64MinMaxEXT", 5613> {
   list<Availability> availability = [
-    Extension<[SPV_EXT_shader_atomic_float_min_max]>
+    Extension<[SPIRV_EXT_shader_atomic_float_min_max]>
   ];
 }
-def SPV_C_AtomicFloat16MinMaxEXT                      : I32EnumAttrCase<"AtomicFloat16MinMaxEXT", 5616> {
+def SPIRV_C_AtomicFloat16MinMaxEXT                      : I32EnumAttrCase<"AtomicFloat16MinMaxEXT", 5616> {
   list<Availability> availability = [
-    Extension<[SPV_EXT_shader_atomic_float_min_max]>
+    Extension<[SPIRV_EXT_shader_atomic_float_min_max]>
   ];
 }
-def SPV_C_VectorAnyINTEL                              : I32EnumAttrCase<"VectorAnyINTEL", 5619> {
+def SPIRV_C_VectorAnyINTEL                              : I32EnumAttrCase<"VectorAnyINTEL", 5619> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_vector_compute]>
+    Extension<[SPIRV_INTEL_vector_compute]>
   ];
 }
-def SPV_C_ExpectAssumeKHR                             : I32EnumAttrCase<"ExpectAssumeKHR", 5629> {
+def SPIRV_C_ExpectAssumeKHR                             : I32EnumAttrCase<"ExpectAssumeKHR", 5629> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_expect_assume]>
+    Extension<[SPIRV_KHR_expect_assume]>
   ];
 }
-def SPV_C_SubgroupAvcMotionEstimationINTEL            : I32EnumAttrCase<"SubgroupAvcMotionEstimationINTEL", 5696> {
+def SPIRV_C_SubgroupAvcMotionEstimationINTEL            : I32EnumAttrCase<"SubgroupAvcMotionEstimationINTEL", 5696> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_device_side_avc_motion_estimation]>
+    Extension<[SPIRV_INTEL_device_side_avc_motion_estimation]>
   ];
 }
-def SPV_C_SubgroupAvcMotionEstimationIntraINTEL       : I32EnumAttrCase<"SubgroupAvcMotionEstimationIntraINTEL", 5697> {
+def SPIRV_C_SubgroupAvcMotionEstimationIntraINTEL       : I32EnumAttrCase<"SubgroupAvcMotionEstimationIntraINTEL", 5697> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_device_side_avc_motion_estimation]>
+    Extension<[SPIRV_INTEL_device_side_avc_motion_estimation]>
   ];
 }
-def SPV_C_SubgroupAvcMotionEstimationChromaINTEL      : I32EnumAttrCase<"SubgroupAvcMotionEstimationChromaINTEL", 5698> {
+def SPIRV_C_SubgroupAvcMotionEstimationChromaINTEL      : I32EnumAttrCase<"SubgroupAvcMotionEstimationChromaINTEL", 5698> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_device_side_avc_motion_estimation]>
+    Extension<[SPIRV_INTEL_device_side_avc_motion_estimation]>
   ];
 }
-def SPV_C_VariableLengthArrayINTEL                    : I32EnumAttrCase<"VariableLengthArrayINTEL", 5817> {
+def SPIRV_C_VariableLengthArrayINTEL                    : I32EnumAttrCase<"VariableLengthArrayINTEL", 5817> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_variable_length_array]>
+    Extension<[SPIRV_INTEL_variable_length_array]>
   ];
 }
-def SPV_C_FunctionFloatControlINTEL                   : I32EnumAttrCase<"FunctionFloatControlINTEL", 5821> {
+def SPIRV_C_FunctionFloatControlINTEL                   : I32EnumAttrCase<"FunctionFloatControlINTEL", 5821> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_float_controls2]>
+    Extension<[SPIRV_INTEL_float_controls2]>
   ];
 }
-def SPV_C_FPGAMemoryAttributesINTEL                   : I32EnumAttrCase<"FPGAMemoryAttributesINTEL", 5824> {
+def SPIRV_C_FPGAMemoryAttributesINTEL                   : I32EnumAttrCase<"FPGAMemoryAttributesINTEL", 5824> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_memory_attributes]>
+    Extension<[SPIRV_INTEL_fpga_memory_attributes]>
   ];
 }
-def SPV_C_ArbitraryPrecisionIntegersINTEL             : I32EnumAttrCase<"ArbitraryPrecisionIntegersINTEL", 5844> {
+def SPIRV_C_ArbitraryPrecisionIntegersINTEL             : I32EnumAttrCase<"ArbitraryPrecisionIntegersINTEL", 5844> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_arbitrary_precision_integers]>
+    Extension<[SPIRV_INTEL_arbitrary_precision_integers]>
   ];
 }
-def SPV_C_ArbitraryPrecisionFloatingPointINTEL        : I32EnumAttrCase<"ArbitraryPrecisionFloatingPointINTEL", 5845> {
+def SPIRV_C_ArbitraryPrecisionFloatingPointINTEL        : I32EnumAttrCase<"ArbitraryPrecisionFloatingPointINTEL", 5845> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_arbitrary_precision_floating_point]>
+    Extension<[SPIRV_INTEL_arbitrary_precision_floating_point]>
   ];
 }
-def SPV_C_UnstructuredLoopControlsINTEL               : I32EnumAttrCase<"UnstructuredLoopControlsINTEL", 5886> {
+def SPIRV_C_UnstructuredLoopControlsINTEL               : I32EnumAttrCase<"UnstructuredLoopControlsINTEL", 5886> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_unstructured_loop_controls]>
+    Extension<[SPIRV_INTEL_unstructured_loop_controls]>
   ];
 }
-def SPV_C_FPGALoopControlsINTEL                       : I32EnumAttrCase<"FPGALoopControlsINTEL", 5888> {
+def SPIRV_C_FPGALoopControlsINTEL                       : I32EnumAttrCase<"FPGALoopControlsINTEL", 5888> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_loop_controls]>
+    Extension<[SPIRV_INTEL_fpga_loop_controls]>
   ];
 }
-def SPV_C_KernelAttributesINTEL                       : I32EnumAttrCase<"KernelAttributesINTEL", 5892> {
+def SPIRV_C_KernelAttributesINTEL                       : I32EnumAttrCase<"KernelAttributesINTEL", 5892> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_kernel_attributes]>
+    Extension<[SPIRV_INTEL_kernel_attributes]>
   ];
 }
-def SPV_C_FPGAKernelAttributesINTEL                   : I32EnumAttrCase<"FPGAKernelAttributesINTEL", 5897> {
+def SPIRV_C_FPGAKernelAttributesINTEL                   : I32EnumAttrCase<"FPGAKernelAttributesINTEL", 5897> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_kernel_attributes]>
+    Extension<[SPIRV_INTEL_kernel_attributes]>
   ];
 }
-def SPV_C_FPGAMemoryAccessesINTEL                     : I32EnumAttrCase<"FPGAMemoryAccessesINTEL", 5898> {
+def SPIRV_C_FPGAMemoryAccessesINTEL                     : I32EnumAttrCase<"FPGAMemoryAccessesINTEL", 5898> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_memory_accesses]>
+    Extension<[SPIRV_INTEL_fpga_memory_accesses]>
   ];
 }
-def SPV_C_FPGAClusterAttributesINTEL                  : I32EnumAttrCase<"FPGAClusterAttributesINTEL", 5904> {
+def SPIRV_C_FPGAClusterAttributesINTEL                  : I32EnumAttrCase<"FPGAClusterAttributesINTEL", 5904> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_cluster_attributes]>
+    Extension<[SPIRV_INTEL_fpga_cluster_attributes]>
   ];
 }
-def SPV_C_LoopFuseINTEL                               : I32EnumAttrCase<"LoopFuseINTEL", 5906> {
+def SPIRV_C_LoopFuseINTEL                               : I32EnumAttrCase<"LoopFuseINTEL", 5906> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_loop_fuse]>
+    Extension<[SPIRV_INTEL_loop_fuse]>
   ];
 }
-def SPV_C_MemoryAccessAliasingINTEL                   : I32EnumAttrCase<"MemoryAccessAliasingINTEL", 5910> {
+def SPIRV_C_MemoryAccessAliasingINTEL                   : I32EnumAttrCase<"MemoryAccessAliasingINTEL", 5910> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_memory_access_aliasing]>
+    Extension<[SPIRV_INTEL_memory_access_aliasing]>
   ];
 }
-def SPV_C_FPGABufferLocationINTEL                     : I32EnumAttrCase<"FPGABufferLocationINTEL", 5920> {
+def SPIRV_C_FPGABufferLocationINTEL                     : I32EnumAttrCase<"FPGABufferLocationINTEL", 5920> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_buffer_location]>
+    Extension<[SPIRV_INTEL_fpga_buffer_location]>
   ];
 }
-def SPV_C_ArbitraryPrecisionFixedPointINTEL           : I32EnumAttrCase<"ArbitraryPrecisionFixedPointINTEL", 5922> {
+def SPIRV_C_ArbitraryPrecisionFixedPointINTEL           : I32EnumAttrCase<"ArbitraryPrecisionFixedPointINTEL", 5922> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_arbitrary_precision_fixed_point]>
+    Extension<[SPIRV_INTEL_arbitrary_precision_fixed_point]>
   ];
 }
-def SPV_C_USMStorageClassesINTEL                      : I32EnumAttrCase<"USMStorageClassesINTEL", 5935> {
+def SPIRV_C_USMStorageClassesINTEL                      : I32EnumAttrCase<"USMStorageClassesINTEL", 5935> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_usm_storage_classes]>
+    Extension<[SPIRV_INTEL_usm_storage_classes]>
   ];
 }
-def SPV_C_IOPipesINTEL                                : I32EnumAttrCase<"IOPipesINTEL", 5943> {
+def SPIRV_C_IOPipesINTEL                                : I32EnumAttrCase<"IOPipesINTEL", 5943> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_io_pipes]>
+    Extension<[SPIRV_INTEL_io_pipes]>
   ];
 }
-def SPV_C_BlockingPipesINTEL                          : I32EnumAttrCase<"BlockingPipesINTEL", 5945> {
+def SPIRV_C_BlockingPipesINTEL                          : I32EnumAttrCase<"BlockingPipesINTEL", 5945> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_blocking_pipes]>
+    Extension<[SPIRV_INTEL_blocking_pipes]>
   ];
 }
-def SPV_C_FPGARegINTEL                                : I32EnumAttrCase<"FPGARegINTEL", 5948> {
+def SPIRV_C_FPGARegINTEL                                : I32EnumAttrCase<"FPGARegINTEL", 5948> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_reg]>
+    Extension<[SPIRV_INTEL_fpga_reg]>
   ];
 }
-def SPV_C_DotProductInputAll                          : I32EnumAttrCase<"DotProductInputAll", 6016> {
+def SPIRV_C_DotProductInputAll                          : I32EnumAttrCase<"DotProductInputAll", 6016> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_6>
+    MinVersion<SPIRV_V_1_6>
   ];
 }
-def SPV_C_DotProductInput4x8BitPacked                 : I32EnumAttrCase<"DotProductInput4x8BitPacked", 6018> {
+def SPIRV_C_DotProductInput4x8BitPacked                 : I32EnumAttrCase<"DotProductInput4x8BitPacked", 6018> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_6>
+    MinVersion<SPIRV_V_1_6>
   ];
 }
-def SPV_C_DotProduct                                  : I32EnumAttrCase<"DotProduct", 6019> {
+def SPIRV_C_DotProduct                                  : I32EnumAttrCase<"DotProduct", 6019> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_6>
+    MinVersion<SPIRV_V_1_6>
   ];
 }
-def SPV_C_RayCullMaskKHR                              : I32EnumAttrCase<"RayCullMaskKHR", 6020> {
+def SPIRV_C_RayCullMaskKHR                              : I32EnumAttrCase<"RayCullMaskKHR", 6020> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_cull_mask]>
+    Extension<[SPIRV_KHR_ray_cull_mask]>
   ];
 }
-def SPV_C_BitInstructions                             : I32EnumAttrCase<"BitInstructions", 6025> {
+def SPIRV_C_BitInstructions                             : I32EnumAttrCase<"BitInstructions", 6025> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_bit_instructions]>
+    Extension<[SPIRV_KHR_bit_instructions]>
   ];
 }
-def SPV_C_AtomicFloat32AddEXT                         : I32EnumAttrCase<"AtomicFloat32AddEXT", 6033> {
+def SPIRV_C_AtomicFloat32AddEXT                         : I32EnumAttrCase<"AtomicFloat32AddEXT", 6033> {
   list<Availability> availability = [
-    Extension<[SPV_EXT_shader_atomic_float_add]>
+    Extension<[SPIRV_EXT_shader_atomic_float_add]>
   ];
 }
-def SPV_C_AtomicFloat64AddEXT                         : I32EnumAttrCase<"AtomicFloat64AddEXT", 6034> {
+def SPIRV_C_AtomicFloat64AddEXT                         : I32EnumAttrCase<"AtomicFloat64AddEXT", 6034> {
   list<Availability> availability = [
-    Extension<[SPV_EXT_shader_atomic_float_add]>
+    Extension<[SPIRV_EXT_shader_atomic_float_add]>
   ];
 }
-def SPV_C_LongConstantCompositeINTEL                  : I32EnumAttrCase<"LongConstantCompositeINTEL", 6089> {
+def SPIRV_C_LongConstantCompositeINTEL                  : I32EnumAttrCase<"LongConstantCompositeINTEL", 6089> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_long_constant_composite]>
+    Extension<[SPIRV_INTEL_long_constant_composite]>
   ];
 }
-def SPV_C_OptNoneINTEL                                : I32EnumAttrCase<"OptNoneINTEL", 6094> {
+def SPIRV_C_OptNoneINTEL                                : I32EnumAttrCase<"OptNoneINTEL", 6094> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_optnone]>
+    Extension<[SPIRV_INTEL_optnone]>
   ];
 }
-def SPV_C_AtomicFloat16AddEXT                         : I32EnumAttrCase<"AtomicFloat16AddEXT", 6095> {
+def SPIRV_C_AtomicFloat16AddEXT                         : I32EnumAttrCase<"AtomicFloat16AddEXT", 6095> {
   list<Availability> availability = [
-    Extension<[SPV_EXT_shader_atomic_float16_add]>
+    Extension<[SPIRV_EXT_shader_atomic_float16_add]>
   ];
 }
-def SPV_C_DebugInfoModuleINTEL                        : I32EnumAttrCase<"DebugInfoModuleINTEL", 6114> {
+def SPIRV_C_DebugInfoModuleINTEL                        : I32EnumAttrCase<"DebugInfoModuleINTEL", 6114> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_debug_module]>
+    Extension<[SPIRV_INTEL_debug_module]>
   ];
 }
-def SPV_C_SplitBarrierINTEL                           : I32EnumAttrCase<"SplitBarrierINTEL", 6141> {
+def SPIRV_C_SplitBarrierINTEL                           : I32EnumAttrCase<"SplitBarrierINTEL", 6141> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_split_barrier]>
+    Extension<[SPIRV_INTEL_split_barrier]>
   ];
 }
-def SPV_C_GroupUniformArithmeticKHR                   : I32EnumAttrCase<"GroupUniformArithmeticKHR", 6400> {
+def SPIRV_C_GroupUniformArithmeticKHR                   : I32EnumAttrCase<"GroupUniformArithmeticKHR", 6400> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_uniform_group_instructions]>
+    Extension<[SPIRV_KHR_uniform_group_instructions]>
   ];
 }
-def SPV_C_Shader                                      : I32EnumAttrCase<"Shader", 1> {
-  list<I32EnumAttrCase> implies = [SPV_C_Matrix];
+def SPIRV_C_Shader                                      : I32EnumAttrCase<"Shader", 1> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Matrix];
 }
-def SPV_C_Vector16                                    : I32EnumAttrCase<"Vector16", 7> {
-  list<I32EnumAttrCase> implies = [SPV_C_Kernel];
+def SPIRV_C_Vector16                                    : I32EnumAttrCase<"Vector16", 7> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Kernel];
 }
-def SPV_C_Float16Buffer                               : I32EnumAttrCase<"Float16Buffer", 8> {
-  list<I32EnumAttrCase> implies = [SPV_C_Kernel];
+def SPIRV_C_Float16Buffer                               : I32EnumAttrCase<"Float16Buffer", 8> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Kernel];
 }
-def SPV_C_Int64Atomics                                : I32EnumAttrCase<"Int64Atomics", 12> {
-  list<I32EnumAttrCase> implies = [SPV_C_Int64];
+def SPIRV_C_Int64Atomics                                : I32EnumAttrCase<"Int64Atomics", 12> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Int64];
 }
-def SPV_C_ImageBasic                                  : I32EnumAttrCase<"ImageBasic", 13> {
-  list<I32EnumAttrCase> implies = [SPV_C_Kernel];
+def SPIRV_C_ImageBasic                                  : I32EnumAttrCase<"ImageBasic", 13> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Kernel];
 }
-def SPV_C_Pipes                                       : I32EnumAttrCase<"Pipes", 17> {
-  list<I32EnumAttrCase> implies = [SPV_C_Kernel];
+def SPIRV_C_Pipes                                       : I32EnumAttrCase<"Pipes", 17> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Kernel];
 }
-def SPV_C_DeviceEnqueue                               : I32EnumAttrCase<"DeviceEnqueue", 19> {
-  list<I32EnumAttrCase> implies = [SPV_C_Kernel];
+def SPIRV_C_DeviceEnqueue                               : I32EnumAttrCase<"DeviceEnqueue", 19> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Kernel];
 }
-def SPV_C_LiteralSampler                              : I32EnumAttrCase<"LiteralSampler", 20> {
-  list<I32EnumAttrCase> implies = [SPV_C_Kernel];
+def SPIRV_C_LiteralSampler                              : I32EnumAttrCase<"LiteralSampler", 20> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Kernel];
 }
-def SPV_C_GenericPointer                              : I32EnumAttrCase<"GenericPointer", 38> {
-  list<I32EnumAttrCase> implies = [SPV_C_Addresses];
+def SPIRV_C_GenericPointer                              : I32EnumAttrCase<"GenericPointer", 38> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Addresses];
 }
-def SPV_C_Image1D                                     : I32EnumAttrCase<"Image1D", 44> {
-  list<I32EnumAttrCase> implies = [SPV_C_Sampled1D];
+def SPIRV_C_Image1D                                     : I32EnumAttrCase<"Image1D", 44> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Sampled1D];
 }
-def SPV_C_ImageBuffer                                 : I32EnumAttrCase<"ImageBuffer", 47> {
-  list<I32EnumAttrCase> implies = [SPV_C_SampledBuffer];
+def SPIRV_C_ImageBuffer                                 : I32EnumAttrCase<"ImageBuffer", 47> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_SampledBuffer];
 }
-def SPV_C_NamedBarrier                                : I32EnumAttrCase<"NamedBarrier", 59> {
-  list<I32EnumAttrCase> implies = [SPV_C_Kernel];
+def SPIRV_C_NamedBarrier                                : I32EnumAttrCase<"NamedBarrier", 59> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Kernel];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_1>
+    MinVersion<SPIRV_V_1_1>
   ];
 }
-def SPV_C_GroupNonUniformVote                         : I32EnumAttrCase<"GroupNonUniformVote", 62> {
-  list<I32EnumAttrCase> implies = [SPV_C_GroupNonUniform];
+def SPIRV_C_GroupNonUniformVote                         : I32EnumAttrCase<"GroupNonUniformVote", 62> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_GroupNonUniform];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>
+    MinVersion<SPIRV_V_1_3>
   ];
 }
-def SPV_C_GroupNonUniformArithmetic                   : I32EnumAttrCase<"GroupNonUniformArithmetic", 63> {
-  list<I32EnumAttrCase> implies = [SPV_C_GroupNonUniform];
+def SPIRV_C_GroupNonUniformArithmetic                   : I32EnumAttrCase<"GroupNonUniformArithmetic", 63> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_GroupNonUniform];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>
+    MinVersion<SPIRV_V_1_3>
   ];
 }
-def SPV_C_GroupNonUniformBallot                       : I32EnumAttrCase<"GroupNonUniformBallot", 64> {
-  list<I32EnumAttrCase> implies = [SPV_C_GroupNonUniform];
+def SPIRV_C_GroupNonUniformBallot                       : I32EnumAttrCase<"GroupNonUniformBallot", 64> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_GroupNonUniform];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>
+    MinVersion<SPIRV_V_1_3>
   ];
 }
-def SPV_C_GroupNonUniformShuffle                      : I32EnumAttrCase<"GroupNonUniformShuffle", 65> {
-  list<I32EnumAttrCase> implies = [SPV_C_GroupNonUniform];
+def SPIRV_C_GroupNonUniformShuffle                      : I32EnumAttrCase<"GroupNonUniformShuffle", 65> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_GroupNonUniform];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>
+    MinVersion<SPIRV_V_1_3>
   ];
 }
-def SPV_C_GroupNonUniformShuffleRelative              : I32EnumAttrCase<"GroupNonUniformShuffleRelative", 66> {
-  list<I32EnumAttrCase> implies = [SPV_C_GroupNonUniform];
+def SPIRV_C_GroupNonUniformShuffleRelative              : I32EnumAttrCase<"GroupNonUniformShuffleRelative", 66> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_GroupNonUniform];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>
+    MinVersion<SPIRV_V_1_3>
   ];
 }
-def SPV_C_GroupNonUniformClustered                    : I32EnumAttrCase<"GroupNonUniformClustered", 67> {
-  list<I32EnumAttrCase> implies = [SPV_C_GroupNonUniform];
+def SPIRV_C_GroupNonUniformClustered                    : I32EnumAttrCase<"GroupNonUniformClustered", 67> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_GroupNonUniform];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>
+    MinVersion<SPIRV_V_1_3>
   ];
 }
-def SPV_C_GroupNonUniformQuad                         : I32EnumAttrCase<"GroupNonUniformQuad", 68> {
-  list<I32EnumAttrCase> implies = [SPV_C_GroupNonUniform];
+def SPIRV_C_GroupNonUniformQuad                         : I32EnumAttrCase<"GroupNonUniformQuad", 68> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_GroupNonUniform];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>
+    MinVersion<SPIRV_V_1_3>
   ];
 }
-def SPV_C_StorageUniform16                            : I32EnumAttrCase<"StorageUniform16", 4434> {
-  list<I32EnumAttrCase> implies = [SPV_C_StorageBuffer16BitAccess];
+def SPIRV_C_StorageUniform16                            : I32EnumAttrCase<"StorageUniform16", 4434> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_StorageBuffer16BitAccess];
   list<Availability> availability = [
-    Extension<[SPV_KHR_16bit_storage]>
+    Extension<[SPIRV_KHR_16bit_storage]>
   ];
 }
-def SPV_C_UniformAndStorageBuffer8BitAccess           : I32EnumAttrCase<"UniformAndStorageBuffer8BitAccess", 4449> {
-  list<I32EnumAttrCase> implies = [SPV_C_StorageBuffer8BitAccess];
+def SPIRV_C_UniformAndStorageBuffer8BitAccess           : I32EnumAttrCase<"UniformAndStorageBuffer8BitAccess", 4449> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_StorageBuffer8BitAccess];
   list<Availability> availability = [
-    Extension<[SPV_KHR_8bit_storage]>
+    Extension<[SPIRV_KHR_8bit_storage]>
   ];
 }
-def SPV_C_UniformTexelBufferArrayDynamicIndexing      : I32EnumAttrCase<"UniformTexelBufferArrayDynamicIndexing", 5304> {
-  list<I32EnumAttrCase> implies = [SPV_C_SampledBuffer];
+def SPIRV_C_UniformTexelBufferArrayDynamicIndexing      : I32EnumAttrCase<"UniformTexelBufferArrayDynamicIndexing", 5304> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_SampledBuffer];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>
+    MinVersion<SPIRV_V_1_5>
   ];
 }
-def SPV_C_VectorComputeINTEL                          : I32EnumAttrCase<"VectorComputeINTEL", 5617> {
-  list<I32EnumAttrCase> implies = [SPV_C_VectorAnyINTEL];
+def SPIRV_C_VectorComputeINTEL                          : I32EnumAttrCase<"VectorComputeINTEL", 5617> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_VectorAnyINTEL];
   list<Availability> availability = [
-    Extension<[SPV_INTEL_vector_compute]>
+    Extension<[SPIRV_INTEL_vector_compute]>
   ];
 }
-def SPV_C_FPFastMathModeINTEL                         : I32EnumAttrCase<"FPFastMathModeINTEL", 5837> {
-  list<I32EnumAttrCase> implies = [SPV_C_Kernel];
+def SPIRV_C_FPFastMathModeINTEL                         : I32EnumAttrCase<"FPFastMathModeINTEL", 5837> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Kernel];
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fp_fast_math_mode]>
+    Extension<[SPIRV_INTEL_fp_fast_math_mode]>
   ];
 }
-def SPV_C_DotProductInput4x8Bit                       : I32EnumAttrCase<"DotProductInput4x8Bit", 6017> {
-  list<I32EnumAttrCase> implies = [SPV_C_Int8];
+def SPIRV_C_DotProductInput4x8Bit                       : I32EnumAttrCase<"DotProductInput4x8Bit", 6017> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Int8];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_6>
+    MinVersion<SPIRV_V_1_6>
   ];
 }
-def SPV_C_GroupNonUniformRotateKHR                    : I32EnumAttrCase<"GroupNonUniformRotateKHR", 6026> {
-  list<I32EnumAttrCase> implies = [SPV_C_GroupNonUniform];
+def SPIRV_C_GroupNonUniformRotateKHR                    : I32EnumAttrCase<"GroupNonUniformRotateKHR", 6026> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_GroupNonUniform];
   list<Availability> availability = [
-    Extension<[SPV_KHR_subgroup_rotate]>
+    Extension<[SPIRV_KHR_subgroup_rotate]>
   ];
 }
-def SPV_C_Geometry                                    : I32EnumAttrCase<"Geometry", 2> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_Geometry                                    : I32EnumAttrCase<"Geometry", 2> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_Tessellation                                : I32EnumAttrCase<"Tessellation", 3> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_Tessellation                                : I32EnumAttrCase<"Tessellation", 3> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_ImageReadWrite                              : I32EnumAttrCase<"ImageReadWrite", 14> {
-  list<I32EnumAttrCase> implies = [SPV_C_ImageBasic];
+def SPIRV_C_ImageReadWrite                              : I32EnumAttrCase<"ImageReadWrite", 14> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_ImageBasic];
 }
-def SPV_C_ImageMipmap                                 : I32EnumAttrCase<"ImageMipmap", 15> {
-  list<I32EnumAttrCase> implies = [SPV_C_ImageBasic];
+def SPIRV_C_ImageMipmap                                 : I32EnumAttrCase<"ImageMipmap", 15> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_ImageBasic];
 }
-def SPV_C_AtomicStorage                               : I32EnumAttrCase<"AtomicStorage", 21> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_AtomicStorage                               : I32EnumAttrCase<"AtomicStorage", 21> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_ImageGatherExtended                         : I32EnumAttrCase<"ImageGatherExtended", 25> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_ImageGatherExtended                         : I32EnumAttrCase<"ImageGatherExtended", 25> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_StorageImageMultisample                     : I32EnumAttrCase<"StorageImageMultisample", 27> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_StorageImageMultisample                     : I32EnumAttrCase<"StorageImageMultisample", 27> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_UniformBufferArrayDynamicIndexing           : I32EnumAttrCase<"UniformBufferArrayDynamicIndexing", 28> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_UniformBufferArrayDynamicIndexing           : I32EnumAttrCase<"UniformBufferArrayDynamicIndexing", 28> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_SampledImageArrayDynamicIndexing            : I32EnumAttrCase<"SampledImageArrayDynamicIndexing", 29> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_SampledImageArrayDynamicIndexing            : I32EnumAttrCase<"SampledImageArrayDynamicIndexing", 29> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_StorageBufferArrayDynamicIndexing           : I32EnumAttrCase<"StorageBufferArrayDynamicIndexing", 30> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_StorageBufferArrayDynamicIndexing           : I32EnumAttrCase<"StorageBufferArrayDynamicIndexing", 30> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_StorageImageArrayDynamicIndexing            : I32EnumAttrCase<"StorageImageArrayDynamicIndexing", 31> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_StorageImageArrayDynamicIndexing            : I32EnumAttrCase<"StorageImageArrayDynamicIndexing", 31> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_ClipDistance                                : I32EnumAttrCase<"ClipDistance", 32> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_ClipDistance                                : I32EnumAttrCase<"ClipDistance", 32> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_CullDistance                                : I32EnumAttrCase<"CullDistance", 33> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_CullDistance                                : I32EnumAttrCase<"CullDistance", 33> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_SampleRateShading                           : I32EnumAttrCase<"SampleRateShading", 35> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_SampleRateShading                           : I32EnumAttrCase<"SampleRateShading", 35> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_SampledRect                                 : I32EnumAttrCase<"SampledRect", 37> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_SampledRect                                 : I32EnumAttrCase<"SampledRect", 37> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_InputAttachment                             : I32EnumAttrCase<"InputAttachment", 40> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_InputAttachment                             : I32EnumAttrCase<"InputAttachment", 40> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_SparseResidency                             : I32EnumAttrCase<"SparseResidency", 41> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_SparseResidency                             : I32EnumAttrCase<"SparseResidency", 41> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_MinLod                                      : I32EnumAttrCase<"MinLod", 42> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_MinLod                                      : I32EnumAttrCase<"MinLod", 42> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_SampledCubeArray                            : I32EnumAttrCase<"SampledCubeArray", 45> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_SampledCubeArray                            : I32EnumAttrCase<"SampledCubeArray", 45> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_ImageMSArray                                : I32EnumAttrCase<"ImageMSArray", 48> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_ImageMSArray                                : I32EnumAttrCase<"ImageMSArray", 48> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_StorageImageExtendedFormats                 : I32EnumAttrCase<"StorageImageExtendedFormats", 49> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_StorageImageExtendedFormats                 : I32EnumAttrCase<"StorageImageExtendedFormats", 49> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_ImageQuery                                  : I32EnumAttrCase<"ImageQuery", 50> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_ImageQuery                                  : I32EnumAttrCase<"ImageQuery", 50> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_DerivativeControl                           : I32EnumAttrCase<"DerivativeControl", 51> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_DerivativeControl                           : I32EnumAttrCase<"DerivativeControl", 51> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_InterpolationFunction                       : I32EnumAttrCase<"InterpolationFunction", 52> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_InterpolationFunction                       : I32EnumAttrCase<"InterpolationFunction", 52> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_TransformFeedback                           : I32EnumAttrCase<"TransformFeedback", 53> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_TransformFeedback                           : I32EnumAttrCase<"TransformFeedback", 53> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_StorageImageReadWithoutFormat               : I32EnumAttrCase<"StorageImageReadWithoutFormat", 55> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_StorageImageReadWithoutFormat               : I32EnumAttrCase<"StorageImageReadWithoutFormat", 55> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_StorageImageWriteWithoutFormat              : I32EnumAttrCase<"StorageImageWriteWithoutFormat", 56> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_StorageImageWriteWithoutFormat              : I32EnumAttrCase<"StorageImageWriteWithoutFormat", 56> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
 }
-def SPV_C_SubgroupDispatch                            : I32EnumAttrCase<"SubgroupDispatch", 58> {
-  list<I32EnumAttrCase> implies = [SPV_C_DeviceEnqueue];
+def SPIRV_C_SubgroupDispatch                            : I32EnumAttrCase<"SubgroupDispatch", 58> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_DeviceEnqueue];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_1>
+    MinVersion<SPIRV_V_1_1>
   ];
 }
-def SPV_C_PipeStorage                                 : I32EnumAttrCase<"PipeStorage", 60> {
-  list<I32EnumAttrCase> implies = [SPV_C_Pipes];
+def SPIRV_C_PipeStorage                                 : I32EnumAttrCase<"PipeStorage", 60> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Pipes];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_1>
+    MinVersion<SPIRV_V_1_1>
   ];
 }
-def SPV_C_FragmentShadingRateKHR                      : I32EnumAttrCase<"FragmentShadingRateKHR", 4422> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_FragmentShadingRateKHR                      : I32EnumAttrCase<"FragmentShadingRateKHR", 4422> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_KHR_fragment_shading_rate]>
+    Extension<[SPIRV_KHR_fragment_shading_rate]>
   ];
 }
-def SPV_C_DrawParameters                              : I32EnumAttrCase<"DrawParameters", 4427> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_DrawParameters                              : I32EnumAttrCase<"DrawParameters", 4427> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_KHR_shader_draw_parameters]>
+    Extension<[SPIRV_KHR_shader_draw_parameters]>
   ];
 }
-def SPV_C_WorkgroupMemoryExplicitLayoutKHR            : I32EnumAttrCase<"WorkgroupMemoryExplicitLayoutKHR", 4428> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_WorkgroupMemoryExplicitLayoutKHR            : I32EnumAttrCase<"WorkgroupMemoryExplicitLayoutKHR", 4428> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_KHR_workgroup_memory_explicit_layout]>
+    Extension<[SPIRV_KHR_workgroup_memory_explicit_layout]>
   ];
 }
-def SPV_C_WorkgroupMemoryExplicitLayout16BitAccessKHR : I32EnumAttrCase<"WorkgroupMemoryExplicitLayout16BitAccessKHR", 4430> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_WorkgroupMemoryExplicitLayout16BitAccessKHR : I32EnumAttrCase<"WorkgroupMemoryExplicitLayout16BitAccessKHR", 4430> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_KHR_workgroup_memory_explicit_layout]>
+    Extension<[SPIRV_KHR_workgroup_memory_explicit_layout]>
   ];
 }
-def SPV_C_MultiView                                   : I32EnumAttrCase<"MultiView", 4439> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_MultiView                                   : I32EnumAttrCase<"MultiView", 4439> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_KHR_multiview]>
+    Extension<[SPIRV_KHR_multiview]>
   ];
 }
-def SPV_C_VariablePointersStorageBuffer               : I32EnumAttrCase<"VariablePointersStorageBuffer", 4441> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_VariablePointersStorageBuffer               : I32EnumAttrCase<"VariablePointersStorageBuffer", 4441> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_KHR_variable_pointers]>
+    Extension<[SPIRV_KHR_variable_pointers]>
   ];
 }
-def SPV_C_RayQueryProvisionalKHR                      : I32EnumAttrCase<"RayQueryProvisionalKHR", 4471> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_RayQueryProvisionalKHR                      : I32EnumAttrCase<"RayQueryProvisionalKHR", 4471> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_query]>
+    Extension<[SPIRV_KHR_ray_query]>
   ];
 }
-def SPV_C_RayQueryKHR                                 : I32EnumAttrCase<"RayQueryKHR", 4472> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_RayQueryKHR                                 : I32EnumAttrCase<"RayQueryKHR", 4472> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_query]>
+    Extension<[SPIRV_KHR_ray_query]>
   ];
 }
-def SPV_C_RayTracingKHR                               : I32EnumAttrCase<"RayTracingKHR", 4479> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_RayTracingKHR                               : I32EnumAttrCase<"RayTracingKHR", 4479> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing]>
+    Extension<[SPIRV_KHR_ray_tracing]>
   ];
 }
-def SPV_C_Float16ImageAMD                             : I32EnumAttrCase<"Float16ImageAMD", 5008> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_Float16ImageAMD                             : I32EnumAttrCase<"Float16ImageAMD", 5008> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_AMD_gpu_shader_half_float_fetch]>
+    Extension<[SPIRV_AMD_gpu_shader_half_float_fetch]>
   ];
 }
-def SPV_C_ImageGatherBiasLodAMD                       : I32EnumAttrCase<"ImageGatherBiasLodAMD", 5009> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_ImageGatherBiasLodAMD                       : I32EnumAttrCase<"ImageGatherBiasLodAMD", 5009> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_AMD_texture_gather_bias_lod]>
+    Extension<[SPIRV_AMD_texture_gather_bias_lod]>
   ];
 }
-def SPV_C_FragmentMaskAMD                             : I32EnumAttrCase<"FragmentMaskAMD", 5010> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_FragmentMaskAMD                             : I32EnumAttrCase<"FragmentMaskAMD", 5010> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_AMD_shader_fragment_mask]>
+    Extension<[SPIRV_AMD_shader_fragment_mask]>
   ];
 }
-def SPV_C_StencilExportEXT                            : I32EnumAttrCase<"StencilExportEXT", 5013> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_StencilExportEXT                            : I32EnumAttrCase<"StencilExportEXT", 5013> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_EXT_shader_stencil_export]>
+    Extension<[SPIRV_EXT_shader_stencil_export]>
   ];
 }
-def SPV_C_ImageReadWriteLodAMD                        : I32EnumAttrCase<"ImageReadWriteLodAMD", 5015> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_ImageReadWriteLodAMD                        : I32EnumAttrCase<"ImageReadWriteLodAMD", 5015> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_AMD_shader_image_load_store_lod]>
+    Extension<[SPIRV_AMD_shader_image_load_store_lod]>
   ];
 }
-def SPV_C_Int64ImageEXT                               : I32EnumAttrCase<"Int64ImageEXT", 5016> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_Int64ImageEXT                               : I32EnumAttrCase<"Int64ImageEXT", 5016> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_EXT_shader_image_int64]>
+    Extension<[SPIRV_EXT_shader_image_int64]>
   ];
 }
-def SPV_C_ShaderClockKHR                              : I32EnumAttrCase<"ShaderClockKHR", 5055> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_ShaderClockKHR                              : I32EnumAttrCase<"ShaderClockKHR", 5055> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_KHR_shader_clock]>
+    Extension<[SPIRV_KHR_shader_clock]>
   ];
 }
-def SPV_C_FragmentFullyCoveredEXT                     : I32EnumAttrCase<"FragmentFullyCoveredEXT", 5265> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_FragmentFullyCoveredEXT                     : I32EnumAttrCase<"FragmentFullyCoveredEXT", 5265> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_EXT_fragment_fully_covered]>
+    Extension<[SPIRV_EXT_fragment_fully_covered]>
   ];
 }
-def SPV_C_MeshShadingNV                               : I32EnumAttrCase<"MeshShadingNV", 5266> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_MeshShadingNV                               : I32EnumAttrCase<"MeshShadingNV", 5266> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_NV_mesh_shader]>
+    Extension<[SPIRV_NV_mesh_shader]>
   ];
 }
-def SPV_C_FragmentDensityEXT                          : I32EnumAttrCase<"FragmentDensityEXT", 5291> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_FragmentDensityEXT                          : I32EnumAttrCase<"FragmentDensityEXT", 5291> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_EXT_fragment_invocation_density, SPV_NV_shading_rate]>
+    Extension<[SPIRV_EXT_fragment_invocation_density, SPIRV_NV_shading_rate]>
   ];
 }
-def SPV_C_ShaderNonUniform                            : I32EnumAttrCase<"ShaderNonUniform", 5301> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_ShaderNonUniform                            : I32EnumAttrCase<"ShaderNonUniform", 5301> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>
+    MinVersion<SPIRV_V_1_5>
   ];
 }
-def SPV_C_RuntimeDescriptorArray                      : I32EnumAttrCase<"RuntimeDescriptorArray", 5302> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_RuntimeDescriptorArray                      : I32EnumAttrCase<"RuntimeDescriptorArray", 5302> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>
+    MinVersion<SPIRV_V_1_5>
   ];
 }
-def SPV_C_StorageTexelBufferArrayDynamicIndexing      : I32EnumAttrCase<"StorageTexelBufferArrayDynamicIndexing", 5305> {
-  list<I32EnumAttrCase> implies = [SPV_C_ImageBuffer];
+def SPIRV_C_StorageTexelBufferArrayDynamicIndexing      : I32EnumAttrCase<"StorageTexelBufferArrayDynamicIndexing", 5305> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_ImageBuffer];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>
+    MinVersion<SPIRV_V_1_5>
   ];
 }
-def SPV_C_RayTracingNV                                : I32EnumAttrCase<"RayTracingNV", 5340> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_RayTracingNV                                : I32EnumAttrCase<"RayTracingNV", 5340> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_NV_ray_tracing]>
+    Extension<[SPIRV_NV_ray_tracing]>
   ];
 }
-def SPV_C_RayTracingMotionBlurNV                      : I32EnumAttrCase<"RayTracingMotionBlurNV", 5341> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_RayTracingMotionBlurNV                      : I32EnumAttrCase<"RayTracingMotionBlurNV", 5341> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_NV_ray_tracing_motion_blur]>
+    Extension<[SPIRV_NV_ray_tracing_motion_blur]>
   ];
 }
-def SPV_C_PhysicalStorageBufferAddresses              : I32EnumAttrCase<"PhysicalStorageBufferAddresses", 5347> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_PhysicalStorageBufferAddresses              : I32EnumAttrCase<"PhysicalStorageBufferAddresses", 5347> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_EXT_physical_storage_buffer, SPV_KHR_physical_storage_buffer]>
+    Extension<[SPIRV_EXT_physical_storage_buffer, SPIRV_KHR_physical_storage_buffer]>
   ];
 }
-def SPV_C_RayTracingProvisionalKHR                    : I32EnumAttrCase<"RayTracingProvisionalKHR", 5353> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_RayTracingProvisionalKHR                    : I32EnumAttrCase<"RayTracingProvisionalKHR", 5353> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing]>
+    Extension<[SPIRV_KHR_ray_tracing]>
   ];
 }
-def SPV_C_CooperativeMatrixNV                         : I32EnumAttrCase<"CooperativeMatrixNV", 5357> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_CooperativeMatrixNV                         : I32EnumAttrCase<"CooperativeMatrixNV", 5357> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_NV_cooperative_matrix]>
+    Extension<[SPIRV_NV_cooperative_matrix]>
   ];
 }
-def SPV_C_FragmentShaderSampleInterlockEXT            : I32EnumAttrCase<"FragmentShaderSampleInterlockEXT", 5363> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_FragmentShaderSampleInterlockEXT            : I32EnumAttrCase<"FragmentShaderSampleInterlockEXT", 5363> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_EXT_fragment_shader_interlock]>
+    Extension<[SPIRV_EXT_fragment_shader_interlock]>
   ];
 }
-def SPV_C_FragmentShaderShadingRateInterlockEXT       : I32EnumAttrCase<"FragmentShaderShadingRateInterlockEXT", 5372> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_FragmentShaderShadingRateInterlockEXT       : I32EnumAttrCase<"FragmentShaderShadingRateInterlockEXT", 5372> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_EXT_fragment_shader_interlock]>
+    Extension<[SPIRV_EXT_fragment_shader_interlock]>
   ];
 }
-def SPV_C_ShaderSMBuiltinsNV                          : I32EnumAttrCase<"ShaderSMBuiltinsNV", 5373> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_ShaderSMBuiltinsNV                          : I32EnumAttrCase<"ShaderSMBuiltinsNV", 5373> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_NV_shader_sm_builtins]>
+    Extension<[SPIRV_NV_shader_sm_builtins]>
   ];
 }
-def SPV_C_FragmentShaderPixelInterlockEXT             : I32EnumAttrCase<"FragmentShaderPixelInterlockEXT", 5378> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_FragmentShaderPixelInterlockEXT             : I32EnumAttrCase<"FragmentShaderPixelInterlockEXT", 5378> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_EXT_fragment_shader_interlock]>
+    Extension<[SPIRV_EXT_fragment_shader_interlock]>
   ];
 }
-def SPV_C_DemoteToHelperInvocation                    : I32EnumAttrCase<"DemoteToHelperInvocation", 5379> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_DemoteToHelperInvocation                    : I32EnumAttrCase<"DemoteToHelperInvocation", 5379> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_6>
+    MinVersion<SPIRV_V_1_6>
   ];
 }
-def SPV_C_IntegerFunctions2INTEL                      : I32EnumAttrCase<"IntegerFunctions2INTEL", 5584> {
-  list<I32EnumAttrCase> implies = [SPV_C_Shader];
+def SPIRV_C_IntegerFunctions2INTEL                      : I32EnumAttrCase<"IntegerFunctions2INTEL", 5584> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
   list<Availability> availability = [
-    Extension<[SPV_INTEL_shader_integer_functions2]>
+    Extension<[SPIRV_INTEL_shader_integer_functions2]>
   ];
 }
-def SPV_C_TessellationPointSize                       : I32EnumAttrCase<"TessellationPointSize", 23> {
-  list<I32EnumAttrCase> implies = [SPV_C_Tessellation];
+def SPIRV_C_TessellationPointSize                       : I32EnumAttrCase<"TessellationPointSize", 23> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Tessellation];
 }
-def SPV_C_GeometryPointSize                           : I32EnumAttrCase<"GeometryPointSize", 24> {
-  list<I32EnumAttrCase> implies = [SPV_C_Geometry];
+def SPIRV_C_GeometryPointSize                           : I32EnumAttrCase<"GeometryPointSize", 24> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Geometry];
 }
-def SPV_C_ImageCubeArray                              : I32EnumAttrCase<"ImageCubeArray", 34> {
-  list<I32EnumAttrCase> implies = [SPV_C_SampledCubeArray];
+def SPIRV_C_ImageCubeArray                              : I32EnumAttrCase<"ImageCubeArray", 34> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_SampledCubeArray];
 }
-def SPV_C_ImageRect                                   : I32EnumAttrCase<"ImageRect", 36> {
-  list<I32EnumAttrCase> implies = [SPV_C_SampledRect];
+def SPIRV_C_ImageRect                                   : I32EnumAttrCase<"ImageRect", 36> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_SampledRect];
 }
-def SPV_C_GeometryStreams                             : I32EnumAttrCase<"GeometryStreams", 54> {
-  list<I32EnumAttrCase> implies = [SPV_C_Geometry];
+def SPIRV_C_GeometryStreams                             : I32EnumAttrCase<"GeometryStreams", 54> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Geometry];
 }
-def SPV_C_MultiViewport                               : I32EnumAttrCase<"MultiViewport", 57> {
-  list<I32EnumAttrCase> implies = [SPV_C_Geometry];
+def SPIRV_C_MultiViewport                               : I32EnumAttrCase<"MultiViewport", 57> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Geometry];
 }
-def SPV_C_WorkgroupMemoryExplicitLayout8BitAccessKHR  : I32EnumAttrCase<"WorkgroupMemoryExplicitLayout8BitAccessKHR", 4429> {
-  list<I32EnumAttrCase> implies = [SPV_C_WorkgroupMemoryExplicitLayoutKHR];
+def SPIRV_C_WorkgroupMemoryExplicitLayout8BitAccessKHR  : I32EnumAttrCase<"WorkgroupMemoryExplicitLayout8BitAccessKHR", 4429> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_WorkgroupMemoryExplicitLayoutKHR];
   list<Availability> availability = [
-    Extension<[SPV_KHR_workgroup_memory_explicit_layout]>
+    Extension<[SPIRV_KHR_workgroup_memory_explicit_layout]>
   ];
 }
-def SPV_C_VariablePointers                            : I32EnumAttrCase<"VariablePointers", 4442> {
-  list<I32EnumAttrCase> implies = [SPV_C_VariablePointersStorageBuffer];
+def SPIRV_C_VariablePointers                            : I32EnumAttrCase<"VariablePointers", 4442> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_VariablePointersStorageBuffer];
   list<Availability> availability = [
-    Extension<[SPV_KHR_variable_pointers]>
+    Extension<[SPIRV_KHR_variable_pointers]>
   ];
 }
-def SPV_C_RayTraversalPrimitiveCullingKHR             : I32EnumAttrCase<"RayTraversalPrimitiveCullingKHR", 4478> {
-  list<I32EnumAttrCase> implies = [SPV_C_RayQueryKHR, SPV_C_RayTracingKHR];
+def SPIRV_C_RayTraversalPrimitiveCullingKHR             : I32EnumAttrCase<"RayTraversalPrimitiveCullingKHR", 4478> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_RayQueryKHR, SPIRV_C_RayTracingKHR];
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_query, SPV_KHR_ray_tracing]>
+    Extension<[SPIRV_KHR_ray_query, SPIRV_KHR_ray_tracing]>
   ];
 }
-def SPV_C_SampleMaskOverrideCoverageNV                : I32EnumAttrCase<"SampleMaskOverrideCoverageNV", 5249> {
-  list<I32EnumAttrCase> implies = [SPV_C_SampleRateShading];
+def SPIRV_C_SampleMaskOverrideCoverageNV                : I32EnumAttrCase<"SampleMaskOverrideCoverageNV", 5249> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_SampleRateShading];
   list<Availability> availability = [
-    Extension<[SPV_NV_sample_mask_override_coverage]>
+    Extension<[SPIRV_NV_sample_mask_override_coverage]>
   ];
 }
-def SPV_C_GeometryShaderPassthroughNV                 : I32EnumAttrCase<"GeometryShaderPassthroughNV", 5251> {
-  list<I32EnumAttrCase> implies = [SPV_C_Geometry];
+def SPIRV_C_GeometryShaderPassthroughNV                 : I32EnumAttrCase<"GeometryShaderPassthroughNV", 5251> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_Geometry];
   list<Availability> availability = [
-    Extension<[SPV_NV_geometry_shader_passthrough]>
+    Extension<[SPIRV_NV_geometry_shader_passthrough]>
   ];
 }
-def SPV_C_PerViewAttributesNV                         : I32EnumAttrCase<"PerViewAttributesNV", 5260> {
-  list<I32EnumAttrCase> implies = [SPV_C_MultiView];
+def SPIRV_C_PerViewAttributesNV                         : I32EnumAttrCase<"PerViewAttributesNV", 5260> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_MultiView];
   list<Availability> availability = [
-    Extension<[SPV_NVX_multiview_per_view_attributes]>
+    Extension<[SPIRV_NVX_multiview_per_view_attributes]>
   ];
 }
-def SPV_C_InputAttachmentArrayDynamicIndexing         : I32EnumAttrCase<"InputAttachmentArrayDynamicIndexing", 5303> {
-  list<I32EnumAttrCase> implies = [SPV_C_InputAttachment];
+def SPIRV_C_InputAttachmentArrayDynamicIndexing         : I32EnumAttrCase<"InputAttachmentArrayDynamicIndexing", 5303> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_InputAttachment];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>
+    MinVersion<SPIRV_V_1_5>
   ];
 }
-def SPV_C_UniformBufferArrayNonUniformIndexing        : I32EnumAttrCase<"UniformBufferArrayNonUniformIndexing", 5306> {
-  list<I32EnumAttrCase> implies = [SPV_C_ShaderNonUniform];
+def SPIRV_C_UniformBufferArrayNonUniformIndexing        : I32EnumAttrCase<"UniformBufferArrayNonUniformIndexing", 5306> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_ShaderNonUniform];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>
+    MinVersion<SPIRV_V_1_5>
   ];
 }
-def SPV_C_SampledImageArrayNonUniformIndexing         : I32EnumAttrCase<"SampledImageArrayNonUniformIndexing", 5307> {
-  list<I32EnumAttrCase> implies = [SPV_C_ShaderNonUniform];
+def SPIRV_C_SampledImageArrayNonUniformIndexing         : I32EnumAttrCase<"SampledImageArrayNonUniformIndexing", 5307> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_ShaderNonUniform];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>
+    MinVersion<SPIRV_V_1_5>
   ];
 }
-def SPV_C_StorageBufferArrayNonUniformIndexing        : I32EnumAttrCase<"StorageBufferArrayNonUniformIndexing", 5308> {
-  list<I32EnumAttrCase> implies = [SPV_C_ShaderNonUniform];
+def SPIRV_C_StorageBufferArrayNonUniformIndexing        : I32EnumAttrCase<"StorageBufferArrayNonUniformIndexing", 5308> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_ShaderNonUniform];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>
+    MinVersion<SPIRV_V_1_5>
   ];
 }
-def SPV_C_StorageImageArrayNonUniformIndexing         : I32EnumAttrCase<"StorageImageArrayNonUniformIndexing", 5309> {
-  list<I32EnumAttrCase> implies = [SPV_C_ShaderNonUniform];
+def SPIRV_C_StorageImageArrayNonUniformIndexing         : I32EnumAttrCase<"StorageImageArrayNonUniformIndexing", 5309> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_ShaderNonUniform];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>
+    MinVersion<SPIRV_V_1_5>
   ];
 }
-def SPV_C_InputAttachmentArrayNonUniformIndexing      : I32EnumAttrCase<"InputAttachmentArrayNonUniformIndexing", 5310> {
-  list<I32EnumAttrCase> implies = [SPV_C_InputAttachment, SPV_C_ShaderNonUniform];
+def SPIRV_C_InputAttachmentArrayNonUniformIndexing      : I32EnumAttrCase<"InputAttachmentArrayNonUniformIndexing", 5310> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_InputAttachment, SPIRV_C_ShaderNonUniform];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>
+    MinVersion<SPIRV_V_1_5>
   ];
 }
-def SPV_C_UniformTexelBufferArrayNonUniformIndexing   : I32EnumAttrCase<"UniformTexelBufferArrayNonUniformIndexing", 5311> {
-  list<I32EnumAttrCase> implies = [SPV_C_SampledBuffer, SPV_C_ShaderNonUniform];
+def SPIRV_C_UniformTexelBufferArrayNonUniformIndexing   : I32EnumAttrCase<"UniformTexelBufferArrayNonUniformIndexing", 5311> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_SampledBuffer, SPIRV_C_ShaderNonUniform];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>
+    MinVersion<SPIRV_V_1_5>
   ];
 }
-def SPV_C_StorageTexelBufferArrayNonUniformIndexing   : I32EnumAttrCase<"StorageTexelBufferArrayNonUniformIndexing", 5312> {
-  list<I32EnumAttrCase> implies = [SPV_C_ImageBuffer, SPV_C_ShaderNonUniform];
+def SPIRV_C_StorageTexelBufferArrayNonUniformIndexing   : I32EnumAttrCase<"StorageTexelBufferArrayNonUniformIndexing", 5312> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_ImageBuffer, SPIRV_C_ShaderNonUniform];
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>
+    MinVersion<SPIRV_V_1_5>
   ];
 }
-def SPV_C_ShaderViewportIndexLayerEXT                 : I32EnumAttrCase<"ShaderViewportIndexLayerEXT", 5254> {
-  list<I32EnumAttrCase> implies = [SPV_C_MultiViewport];
+def SPIRV_C_ShaderViewportIndexLayerEXT                 : I32EnumAttrCase<"ShaderViewportIndexLayerEXT", 5254> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_MultiViewport];
   list<Availability> availability = [
-    Extension<[SPV_EXT_shader_viewport_index_layer]>
+    Extension<[SPIRV_EXT_shader_viewport_index_layer]>
   ];
 }
-def SPV_C_ShaderViewportMaskNV                        : I32EnumAttrCase<"ShaderViewportMaskNV", 5255> {
-  list<I32EnumAttrCase> implies = [SPV_C_ShaderViewportIndexLayerEXT];
+def SPIRV_C_ShaderViewportMaskNV                        : I32EnumAttrCase<"ShaderViewportMaskNV", 5255> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_ShaderViewportIndexLayerEXT];
   list<Availability> availability = [
-    Extension<[SPV_NV_viewport_array2]>
+    Extension<[SPIRV_NV_viewport_array2]>
   ];
 }
-def SPV_C_ShaderStereoViewNV                          : I32EnumAttrCase<"ShaderStereoViewNV", 5259> {
-  list<I32EnumAttrCase> implies = [SPV_C_ShaderViewportMaskNV];
+def SPIRV_C_ShaderStereoViewNV                          : I32EnumAttrCase<"ShaderStereoViewNV", 5259> {
+  list<I32EnumAttrCase> implies = [SPIRV_C_ShaderViewportMaskNV];
   list<Availability> availability = [
-    Extension<[SPV_NV_stereo_view_rendering]>
+    Extension<[SPIRV_NV_stereo_view_rendering]>
   ];
 }
 
-def SPV_C_JointMatrixINTEL                         : I32EnumAttrCase<"JointMatrixINTEL", 6118> {
+def SPIRV_C_JointMatrixINTEL                         : I32EnumAttrCase<"JointMatrixINTEL", 6118> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_joint_matrix]>
+    Extension<[SPIRV_INTEL_joint_matrix]>
   ];
 }
 
-def SPV_CapabilityAttr :
-    SPV_I32EnumAttr<"Capability", "valid SPIR-V Capability", "capability", [
-      SPV_C_Matrix, SPV_C_Addresses, SPV_C_Linkage, SPV_C_Kernel, SPV_C_Float16,
-      SPV_C_Float64, SPV_C_Int64, SPV_C_Groups, SPV_C_Int16, SPV_C_Int8,
-      SPV_C_Sampled1D, SPV_C_SampledBuffer, SPV_C_GroupNonUniform, SPV_C_ShaderLayer,
-      SPV_C_ShaderViewportIndex, SPV_C_UniformDecoration, SPV_C_SubgroupBallotKHR,
-      SPV_C_SubgroupVoteKHR, SPV_C_StorageBuffer16BitAccess,
-      SPV_C_StoragePushConstant16, SPV_C_StorageInputOutput16, SPV_C_DeviceGroup,
-      SPV_C_AtomicStorageOps, SPV_C_SampleMaskPostDepthCoverage,
-      SPV_C_StorageBuffer8BitAccess, SPV_C_StoragePushConstant8,
-      SPV_C_DenormPreserve, SPV_C_DenormFlushToZero, SPV_C_SignedZeroInfNanPreserve,
-      SPV_C_RoundingModeRTE, SPV_C_RoundingModeRTZ, SPV_C_ImageFootprintNV,
-      SPV_C_FragmentBarycentricKHR, SPV_C_ComputeDerivativeGroupQuadsNV,
-      SPV_C_GroupNonUniformPartitionedNV, SPV_C_VulkanMemoryModel,
-      SPV_C_VulkanMemoryModelDeviceScope, SPV_C_ComputeDerivativeGroupLinearNV,
-      SPV_C_BindlessTextureNV, SPV_C_SubgroupShuffleINTEL,
-      SPV_C_SubgroupBufferBlockIOINTEL, SPV_C_SubgroupImageBlockIOINTEL,
-      SPV_C_SubgroupImageMediaBlockIOINTEL, SPV_C_RoundToInfinityINTEL,
-      SPV_C_FloatingPointModeINTEL, SPV_C_FunctionPointersINTEL,
-      SPV_C_IndirectReferencesINTEL, SPV_C_AsmINTEL, SPV_C_AtomicFloat32MinMaxEXT,
-      SPV_C_AtomicFloat64MinMaxEXT, SPV_C_AtomicFloat16MinMaxEXT,
-      SPV_C_VectorAnyINTEL, SPV_C_ExpectAssumeKHR,
-      SPV_C_SubgroupAvcMotionEstimationINTEL,
-      SPV_C_SubgroupAvcMotionEstimationIntraINTEL,
-      SPV_C_SubgroupAvcMotionEstimationChromaINTEL, SPV_C_VariableLengthArrayINTEL,
-      SPV_C_FunctionFloatControlINTEL, SPV_C_FPGAMemoryAttributesINTEL,
-      SPV_C_ArbitraryPrecisionIntegersINTEL,
-      SPV_C_ArbitraryPrecisionFloatingPointINTEL,
-      SPV_C_UnstructuredLoopControlsINTEL, SPV_C_FPGALoopControlsINTEL,
-      SPV_C_KernelAttributesINTEL, SPV_C_FPGAKernelAttributesINTEL,
-      SPV_C_FPGAMemoryAccessesINTEL, SPV_C_FPGAClusterAttributesINTEL,
-      SPV_C_LoopFuseINTEL, SPV_C_MemoryAccessAliasingINTEL,
-      SPV_C_FPGABufferLocationINTEL, SPV_C_ArbitraryPrecisionFixedPointINTEL,
-      SPV_C_USMStorageClassesINTEL, SPV_C_IOPipesINTEL, SPV_C_BlockingPipesINTEL,
-      SPV_C_FPGARegINTEL, SPV_C_DotProductInputAll,
-      SPV_C_DotProductInput4x8BitPacked, SPV_C_DotProduct, SPV_C_RayCullMaskKHR,
-      SPV_C_BitInstructions, SPV_C_AtomicFloat32AddEXT, SPV_C_AtomicFloat64AddEXT,
-      SPV_C_LongConstantCompositeINTEL, SPV_C_OptNoneINTEL,
-      SPV_C_AtomicFloat16AddEXT, SPV_C_DebugInfoModuleINTEL, SPV_C_SplitBarrierINTEL,
-      SPV_C_GroupUniformArithmeticKHR, SPV_C_Shader, SPV_C_Vector16,
-      SPV_C_Float16Buffer, SPV_C_Int64Atomics, SPV_C_ImageBasic, SPV_C_Pipes,
-      SPV_C_DeviceEnqueue, SPV_C_LiteralSampler, SPV_C_GenericPointer, SPV_C_Image1D,
-      SPV_C_ImageBuffer, SPV_C_NamedBarrier, SPV_C_GroupNonUniformVote,
-      SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformBallot,
-      SPV_C_GroupNonUniformShuffle, SPV_C_GroupNonUniformShuffleRelative,
-      SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformQuad,
-      SPV_C_StorageUniform16, SPV_C_UniformAndStorageBuffer8BitAccess,
-      SPV_C_UniformTexelBufferArrayDynamicIndexing, SPV_C_VectorComputeINTEL,
-      SPV_C_FPFastMathModeINTEL, SPV_C_DotProductInput4x8Bit,
-      SPV_C_GroupNonUniformRotateKHR, SPV_C_Geometry, SPV_C_Tessellation,
-      SPV_C_ImageReadWrite, SPV_C_ImageMipmap, SPV_C_AtomicStorage,
-      SPV_C_ImageGatherExtended, SPV_C_StorageImageMultisample,
-      SPV_C_UniformBufferArrayDynamicIndexing,
-      SPV_C_SampledImageArrayDynamicIndexing,
-      SPV_C_StorageBufferArrayDynamicIndexing,
-      SPV_C_StorageImageArrayDynamicIndexing, SPV_C_ClipDistance, SPV_C_CullDistance,
-      SPV_C_SampleRateShading, SPV_C_SampledRect, SPV_C_InputAttachment,
-      SPV_C_SparseResidency, SPV_C_MinLod, SPV_C_SampledCubeArray,
-      SPV_C_ImageMSArray, SPV_C_StorageImageExtendedFormats, SPV_C_ImageQuery,
-      SPV_C_DerivativeControl, SPV_C_InterpolationFunction, SPV_C_TransformFeedback,
-      SPV_C_StorageImageReadWithoutFormat, SPV_C_StorageImageWriteWithoutFormat,
-      SPV_C_SubgroupDispatch, SPV_C_PipeStorage, SPV_C_FragmentShadingRateKHR,
-      SPV_C_DrawParameters, SPV_C_WorkgroupMemoryExplicitLayoutKHR,
-      SPV_C_WorkgroupMemoryExplicitLayout16BitAccessKHR, SPV_C_MultiView,
-      SPV_C_VariablePointersStorageBuffer, SPV_C_RayQueryProvisionalKHR,
-      SPV_C_RayQueryKHR, SPV_C_RayTracingKHR, SPV_C_Float16ImageAMD,
-      SPV_C_ImageGatherBiasLodAMD, SPV_C_FragmentMaskAMD, SPV_C_StencilExportEXT,
-      SPV_C_ImageReadWriteLodAMD, SPV_C_Int64ImageEXT, SPV_C_ShaderClockKHR,
-      SPV_C_FragmentFullyCoveredEXT, SPV_C_MeshShadingNV, SPV_C_FragmentDensityEXT,
-      SPV_C_ShaderNonUniform, SPV_C_RuntimeDescriptorArray,
-      SPV_C_StorageTexelBufferArrayDynamicIndexing, SPV_C_RayTracingNV,
-      SPV_C_RayTracingMotionBlurNV, SPV_C_PhysicalStorageBufferAddresses,
-      SPV_C_RayTracingProvisionalKHR, SPV_C_CooperativeMatrixNV,
-      SPV_C_FragmentShaderSampleInterlockEXT,
-      SPV_C_FragmentShaderShadingRateInterlockEXT, SPV_C_ShaderSMBuiltinsNV,
-      SPV_C_FragmentShaderPixelInterlockEXT, SPV_C_DemoteToHelperInvocation,
-      SPV_C_IntegerFunctions2INTEL, SPV_C_TessellationPointSize,
-      SPV_C_GeometryPointSize, SPV_C_ImageCubeArray, SPV_C_ImageRect,
-      SPV_C_GeometryStreams, SPV_C_MultiViewport,
-      SPV_C_WorkgroupMemoryExplicitLayout8BitAccessKHR, SPV_C_VariablePointers,
-      SPV_C_RayTraversalPrimitiveCullingKHR, SPV_C_SampleMaskOverrideCoverageNV,
-      SPV_C_GeometryShaderPassthroughNV, SPV_C_PerViewAttributesNV,
-      SPV_C_InputAttachmentArrayDynamicIndexing,
-      SPV_C_UniformBufferArrayNonUniformIndexing,
-      SPV_C_SampledImageArrayNonUniformIndexing,
-      SPV_C_StorageBufferArrayNonUniformIndexing,
-      SPV_C_StorageImageArrayNonUniformIndexing,
-      SPV_C_InputAttachmentArrayNonUniformIndexing,
-      SPV_C_UniformTexelBufferArrayNonUniformIndexing,
-      SPV_C_StorageTexelBufferArrayNonUniformIndexing,
-      SPV_C_ShaderViewportIndexLayerEXT, SPV_C_ShaderViewportMaskNV,
-      SPV_C_ShaderStereoViewNV, SPV_C_JointMatrixINTEL
+def SPIRV_CapabilityAttr :
+    SPIRV_I32EnumAttr<"Capability", "valid SPIR-V Capability", "capability", [
+      SPIRV_C_Matrix, SPIRV_C_Addresses, SPIRV_C_Linkage, SPIRV_C_Kernel, SPIRV_C_Float16,
+      SPIRV_C_Float64, SPIRV_C_Int64, SPIRV_C_Groups, SPIRV_C_Int16, SPIRV_C_Int8,
+      SPIRV_C_Sampled1D, SPIRV_C_SampledBuffer, SPIRV_C_GroupNonUniform, SPIRV_C_ShaderLayer,
+      SPIRV_C_ShaderViewportIndex, SPIRV_C_UniformDecoration, SPIRV_C_SubgroupBallotKHR,
+      SPIRV_C_SubgroupVoteKHR, SPIRV_C_StorageBuffer16BitAccess,
+      SPIRV_C_StoragePushConstant16, SPIRV_C_StorageInputOutput16, SPIRV_C_DeviceGroup,
+      SPIRV_C_AtomicStorageOps, SPIRV_C_SampleMaskPostDepthCoverage,
+      SPIRV_C_StorageBuffer8BitAccess, SPIRV_C_StoragePushConstant8,
+      SPIRV_C_DenormPreserve, SPIRV_C_DenormFlushToZero, SPIRV_C_SignedZeroInfNanPreserve,
+      SPIRV_C_RoundingModeRTE, SPIRV_C_RoundingModeRTZ, SPIRV_C_ImageFootprintNV,
+      SPIRV_C_FragmentBarycentricKHR, SPIRV_C_ComputeDerivativeGroupQuadsNV,
+      SPIRV_C_GroupNonUniformPartitionedNV, SPIRV_C_VulkanMemoryModel,
+      SPIRV_C_VulkanMemoryModelDeviceScope, SPIRV_C_ComputeDerivativeGroupLinearNV,
+      SPIRV_C_BindlessTextureNV, SPIRV_C_SubgroupShuffleINTEL,
+      SPIRV_C_SubgroupBufferBlockIOINTEL, SPIRV_C_SubgroupImageBlockIOINTEL,
+      SPIRV_C_SubgroupImageMediaBlockIOINTEL, SPIRV_C_RoundToInfinityINTEL,
+      SPIRV_C_FloatingPointModeINTEL, SPIRV_C_FunctionPointersINTEL,
+      SPIRV_C_IndirectReferencesINTEL, SPIRV_C_AsmINTEL, SPIRV_C_AtomicFloat32MinMaxEXT,
+      SPIRV_C_AtomicFloat64MinMaxEXT, SPIRV_C_AtomicFloat16MinMaxEXT,
+      SPIRV_C_VectorAnyINTEL, SPIRV_C_ExpectAssumeKHR,
+      SPIRV_C_SubgroupAvcMotionEstimationINTEL,
+      SPIRV_C_SubgroupAvcMotionEstimationIntraINTEL,
+      SPIRV_C_SubgroupAvcMotionEstimationChromaINTEL, SPIRV_C_VariableLengthArrayINTEL,
+      SPIRV_C_FunctionFloatControlINTEL, SPIRV_C_FPGAMemoryAttributesINTEL,
+      SPIRV_C_ArbitraryPrecisionIntegersINTEL,
+      SPIRV_C_ArbitraryPrecisionFloatingPointINTEL,
+      SPIRV_C_UnstructuredLoopControlsINTEL, SPIRV_C_FPGALoopControlsINTEL,
+      SPIRV_C_KernelAttributesINTEL, SPIRV_C_FPGAKernelAttributesINTEL,
+      SPIRV_C_FPGAMemoryAccessesINTEL, SPIRV_C_FPGAClusterAttributesINTEL,
+      SPIRV_C_LoopFuseINTEL, SPIRV_C_MemoryAccessAliasingINTEL,
+      SPIRV_C_FPGABufferLocationINTEL, SPIRV_C_ArbitraryPrecisionFixedPointINTEL,
+      SPIRV_C_USMStorageClassesINTEL, SPIRV_C_IOPipesINTEL, SPIRV_C_BlockingPipesINTEL,
+      SPIRV_C_FPGARegINTEL, SPIRV_C_DotProductInputAll,
+      SPIRV_C_DotProductInput4x8BitPacked, SPIRV_C_DotProduct, SPIRV_C_RayCullMaskKHR,
+      SPIRV_C_BitInstructions, SPIRV_C_AtomicFloat32AddEXT, SPIRV_C_AtomicFloat64AddEXT,
+      SPIRV_C_LongConstantCompositeINTEL, SPIRV_C_OptNoneINTEL,
+      SPIRV_C_AtomicFloat16AddEXT, SPIRV_C_DebugInfoModuleINTEL, SPIRV_C_SplitBarrierINTEL,
+      SPIRV_C_GroupUniformArithmeticKHR, SPIRV_C_Shader, SPIRV_C_Vector16,
+      SPIRV_C_Float16Buffer, SPIRV_C_Int64Atomics, SPIRV_C_ImageBasic, SPIRV_C_Pipes,
+      SPIRV_C_DeviceEnqueue, SPIRV_C_LiteralSampler, SPIRV_C_GenericPointer, SPIRV_C_Image1D,
+      SPIRV_C_ImageBuffer, SPIRV_C_NamedBarrier, SPIRV_C_GroupNonUniformVote,
+      SPIRV_C_GroupNonUniformArithmetic, SPIRV_C_GroupNonUniformBallot,
+      SPIRV_C_GroupNonUniformShuffle, SPIRV_C_GroupNonUniformShuffleRelative,
+      SPIRV_C_GroupNonUniformClustered, SPIRV_C_GroupNonUniformQuad,
+      SPIRV_C_StorageUniform16, SPIRV_C_UniformAndStorageBuffer8BitAccess,
+      SPIRV_C_UniformTexelBufferArrayDynamicIndexing, SPIRV_C_VectorComputeINTEL,
+      SPIRV_C_FPFastMathModeINTEL, SPIRV_C_DotProductInput4x8Bit,
+      SPIRV_C_GroupNonUniformRotateKHR, SPIRV_C_Geometry, SPIRV_C_Tessellation,
+      SPIRV_C_ImageReadWrite, SPIRV_C_ImageMipmap, SPIRV_C_AtomicStorage,
+      SPIRV_C_ImageGatherExtended, SPIRV_C_StorageImageMultisample,
+      SPIRV_C_UniformBufferArrayDynamicIndexing,
+      SPIRV_C_SampledImageArrayDynamicIndexing,
+      SPIRV_C_StorageBufferArrayDynamicIndexing,
+      SPIRV_C_StorageImageArrayDynamicIndexing, SPIRV_C_ClipDistance, SPIRV_C_CullDistance,
+      SPIRV_C_SampleRateShading, SPIRV_C_SampledRect, SPIRV_C_InputAttachment,
+      SPIRV_C_SparseResidency, SPIRV_C_MinLod, SPIRV_C_SampledCubeArray,
+      SPIRV_C_ImageMSArray, SPIRV_C_StorageImageExtendedFormats, SPIRV_C_ImageQuery,
+      SPIRV_C_DerivativeControl, SPIRV_C_InterpolationFunction, SPIRV_C_TransformFeedback,
+      SPIRV_C_StorageImageReadWithoutFormat, SPIRV_C_StorageImageWriteWithoutFormat,
+      SPIRV_C_SubgroupDispatch, SPIRV_C_PipeStorage, SPIRV_C_FragmentShadingRateKHR,
+      SPIRV_C_DrawParameters, SPIRV_C_WorkgroupMemoryExplicitLayoutKHR,
+      SPIRV_C_WorkgroupMemoryExplicitLayout16BitAccessKHR, SPIRV_C_MultiView,
+      SPIRV_C_VariablePointersStorageBuffer, SPIRV_C_RayQueryProvisionalKHR,
+      SPIRV_C_RayQueryKHR, SPIRV_C_RayTracingKHR, SPIRV_C_Float16ImageAMD,
+      SPIRV_C_ImageGatherBiasLodAMD, SPIRV_C_FragmentMaskAMD, SPIRV_C_StencilExportEXT,
+      SPIRV_C_ImageReadWriteLodAMD, SPIRV_C_Int64ImageEXT, SPIRV_C_ShaderClockKHR,
+      SPIRV_C_FragmentFullyCoveredEXT, SPIRV_C_MeshShadingNV, SPIRV_C_FragmentDensityEXT,
+      SPIRV_C_ShaderNonUniform, SPIRV_C_RuntimeDescriptorArray,
+      SPIRV_C_StorageTexelBufferArrayDynamicIndexing, SPIRV_C_RayTracingNV,
+      SPIRV_C_RayTracingMotionBlurNV, SPIRV_C_PhysicalStorageBufferAddresses,
+      SPIRV_C_RayTracingProvisionalKHR, SPIRV_C_CooperativeMatrixNV,
+      SPIRV_C_FragmentShaderSampleInterlockEXT,
+      SPIRV_C_FragmentShaderShadingRateInterlockEXT, SPIRV_C_ShaderSMBuiltinsNV,
+      SPIRV_C_FragmentShaderPixelInterlockEXT, SPIRV_C_DemoteToHelperInvocation,
+      SPIRV_C_IntegerFunctions2INTEL, SPIRV_C_TessellationPointSize,
+      SPIRV_C_GeometryPointSize, SPIRV_C_ImageCubeArray, SPIRV_C_ImageRect,
+      SPIRV_C_GeometryStreams, SPIRV_C_MultiViewport,
+      SPIRV_C_WorkgroupMemoryExplicitLayout8BitAccessKHR, SPIRV_C_VariablePointers,
+      SPIRV_C_RayTraversalPrimitiveCullingKHR, SPIRV_C_SampleMaskOverrideCoverageNV,
+      SPIRV_C_GeometryShaderPassthroughNV, SPIRV_C_PerViewAttributesNV,
+      SPIRV_C_InputAttachmentArrayDynamicIndexing,
+      SPIRV_C_UniformBufferArrayNonUniformIndexing,
+      SPIRV_C_SampledImageArrayNonUniformIndexing,
+      SPIRV_C_StorageBufferArrayNonUniformIndexing,
+      SPIRV_C_StorageImageArrayNonUniformIndexing,
+      SPIRV_C_InputAttachmentArrayNonUniformIndexing,
+      SPIRV_C_UniformTexelBufferArrayNonUniformIndexing,
+      SPIRV_C_StorageTexelBufferArrayNonUniformIndexing,
+      SPIRV_C_ShaderViewportIndexLayerEXT, SPIRV_C_ShaderViewportMaskNV,
+      SPIRV_C_ShaderStereoViewNV, SPIRV_C_JointMatrixINTEL
     ]>;
 
-def SPV_AM_Logical                 : I32EnumAttrCase<"Logical", 0>;
-def SPV_AM_Physical32              : I32EnumAttrCase<"Physical32", 1> {
+def SPIRV_AM_Logical                 : I32EnumAttrCase<"Logical", 0>;
+def SPIRV_AM_Physical32              : I32EnumAttrCase<"Physical32", 1> {
   list<Availability> availability = [
-    Capability<[SPV_C_Addresses]>
+    Capability<[SPIRV_C_Addresses]>
   ];
 }
-def SPV_AM_Physical64              : I32EnumAttrCase<"Physical64", 2> {
+def SPIRV_AM_Physical64              : I32EnumAttrCase<"Physical64", 2> {
   list<Availability> availability = [
-    Capability<[SPV_C_Addresses]>
+    Capability<[SPIRV_C_Addresses]>
   ];
 }
-def SPV_AM_PhysicalStorageBuffer64 : I32EnumAttrCase<"PhysicalStorageBuffer64", 5348> {
+def SPIRV_AM_PhysicalStorageBuffer64 : I32EnumAttrCase<"PhysicalStorageBuffer64", 5348> {
   list<Availability> availability = [
-    Extension<[SPV_EXT_physical_storage_buffer, SPV_KHR_physical_storage_buffer]>,
-    Capability<[SPV_C_PhysicalStorageBufferAddresses]>
+    Extension<[SPIRV_EXT_physical_storage_buffer, SPIRV_KHR_physical_storage_buffer]>,
+    Capability<[SPIRV_C_PhysicalStorageBufferAddresses]>
   ];
 }
 
-def SPV_AddressingModelAttr :
-    SPV_I32EnumAttr<"AddressingModel", "valid SPIR-V AddressingModel", "addressing_model", [
-      SPV_AM_Logical, SPV_AM_Physical32, SPV_AM_Physical64,
-      SPV_AM_PhysicalStorageBuffer64
+def SPIRV_AddressingModelAttr :
+    SPIRV_I32EnumAttr<"AddressingModel", "valid SPIR-V AddressingModel", "addressing_model", [
+      SPIRV_AM_Logical, SPIRV_AM_Physical32, SPIRV_AM_Physical64,
+      SPIRV_AM_PhysicalStorageBuffer64
     ]>;
 
-def SPV_BI_Position                    : I32EnumAttrCase<"Position", 0> {
+def SPIRV_BI_Position                    : I32EnumAttrCase<"Position", 0> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_BI_PointSize                   : I32EnumAttrCase<"PointSize", 1> {
+def SPIRV_BI_PointSize                   : I32EnumAttrCase<"PointSize", 1> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_BI_ClipDistance                : I32EnumAttrCase<"ClipDistance", 3> {
+def SPIRV_BI_ClipDistance                : I32EnumAttrCase<"ClipDistance", 3> {
   list<Availability> availability = [
-    Capability<[SPV_C_ClipDistance]>
+    Capability<[SPIRV_C_ClipDistance]>
   ];
 }
-def SPV_BI_CullDistance                : I32EnumAttrCase<"CullDistance", 4> {
+def SPIRV_BI_CullDistance                : I32EnumAttrCase<"CullDistance", 4> {
   list<Availability> availability = [
-    Capability<[SPV_C_CullDistance]>
+    Capability<[SPIRV_C_CullDistance]>
   ];
 }
-def SPV_BI_VertexId                    : I32EnumAttrCase<"VertexId", 5> {
+def SPIRV_BI_VertexId                    : I32EnumAttrCase<"VertexId", 5> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_BI_InstanceId                  : I32EnumAttrCase<"InstanceId", 6> {
+def SPIRV_BI_InstanceId                  : I32EnumAttrCase<"InstanceId", 6> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_BI_PrimitiveId                 : I32EnumAttrCase<"PrimitiveId", 7> {
+def SPIRV_BI_PrimitiveId                 : I32EnumAttrCase<"PrimitiveId", 7> {
   list<Availability> availability = [
-    Capability<[SPV_C_Geometry, SPV_C_MeshShadingNV, SPV_C_RayTracingKHR, SPV_C_RayTracingNV, SPV_C_Tessellation]>
+    Capability<[SPIRV_C_Geometry, SPIRV_C_MeshShadingNV, SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV, SPIRV_C_Tessellation]>
   ];
 }
-def SPV_BI_InvocationId                : I32EnumAttrCase<"InvocationId", 8> {
+def SPIRV_BI_InvocationId                : I32EnumAttrCase<"InvocationId", 8> {
   list<Availability> availability = [
-    Capability<[SPV_C_Geometry, SPV_C_Tessellation]>
+    Capability<[SPIRV_C_Geometry, SPIRV_C_Tessellation]>
   ];
 }
-def SPV_BI_Layer                       : I32EnumAttrCase<"Layer", 9> {
+def SPIRV_BI_Layer                       : I32EnumAttrCase<"Layer", 9> {
   list<Availability> availability = [
-    Capability<[SPV_C_Geometry, SPV_C_MeshShadingNV, SPV_C_ShaderLayer, SPV_C_ShaderViewportIndexLayerEXT]>
+    Capability<[SPIRV_C_Geometry, SPIRV_C_MeshShadingNV, SPIRV_C_ShaderLayer, SPIRV_C_ShaderViewportIndexLayerEXT]>
   ];
 }
-def SPV_BI_ViewportIndex               : I32EnumAttrCase<"ViewportIndex", 10> {
+def SPIRV_BI_ViewportIndex               : I32EnumAttrCase<"ViewportIndex", 10> {
   list<Availability> availability = [
-    Capability<[SPV_C_MeshShadingNV, SPV_C_MultiViewport, SPV_C_ShaderViewportIndex, SPV_C_ShaderViewportIndexLayerEXT]>
+    Capability<[SPIRV_C_MeshShadingNV, SPIRV_C_MultiViewport, SPIRV_C_ShaderViewportIndex, SPIRV_C_ShaderViewportIndexLayerEXT]>
   ];
 }
-def SPV_BI_TessLevelOuter              : I32EnumAttrCase<"TessLevelOuter", 11> {
+def SPIRV_BI_TessLevelOuter              : I32EnumAttrCase<"TessLevelOuter", 11> {
   list<Availability> availability = [
-    Capability<[SPV_C_Tessellation]>
+    Capability<[SPIRV_C_Tessellation]>
   ];
 }
-def SPV_BI_TessLevelInner              : I32EnumAttrCase<"TessLevelInner", 12> {
+def SPIRV_BI_TessLevelInner              : I32EnumAttrCase<"TessLevelInner", 12> {
   list<Availability> availability = [
-    Capability<[SPV_C_Tessellation]>
+    Capability<[SPIRV_C_Tessellation]>
   ];
 }
-def SPV_BI_TessCoord                   : I32EnumAttrCase<"TessCoord", 13> {
+def SPIRV_BI_TessCoord                   : I32EnumAttrCase<"TessCoord", 13> {
   list<Availability> availability = [
-    Capability<[SPV_C_Tessellation]>
+    Capability<[SPIRV_C_Tessellation]>
   ];
 }
-def SPV_BI_PatchVertices               : I32EnumAttrCase<"PatchVertices", 14> {
+def SPIRV_BI_PatchVertices               : I32EnumAttrCase<"PatchVertices", 14> {
   list<Availability> availability = [
-    Capability<[SPV_C_Tessellation]>
+    Capability<[SPIRV_C_Tessellation]>
   ];
 }
-def SPV_BI_FragCoord                   : I32EnumAttrCase<"FragCoord", 15> {
+def SPIRV_BI_FragCoord                   : I32EnumAttrCase<"FragCoord", 15> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_BI_PointCoord                  : I32EnumAttrCase<"PointCoord", 16> {
+def SPIRV_BI_PointCoord                  : I32EnumAttrCase<"PointCoord", 16> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_BI_FrontFacing                 : I32EnumAttrCase<"FrontFacing", 17> {
+def SPIRV_BI_FrontFacing                 : I32EnumAttrCase<"FrontFacing", 17> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_BI_SampleId                    : I32EnumAttrCase<"SampleId", 18> {
+def SPIRV_BI_SampleId                    : I32EnumAttrCase<"SampleId", 18> {
   list<Availability> availability = [
-    Capability<[SPV_C_SampleRateShading]>
+    Capability<[SPIRV_C_SampleRateShading]>
   ];
 }
-def SPV_BI_SamplePosition              : I32EnumAttrCase<"SamplePosition", 19> {
+def SPIRV_BI_SamplePosition              : I32EnumAttrCase<"SamplePosition", 19> {
   list<Availability> availability = [
-    Capability<[SPV_C_SampleRateShading]>
+    Capability<[SPIRV_C_SampleRateShading]>
   ];
 }
-def SPV_BI_SampleMask                  : I32EnumAttrCase<"SampleMask", 20> {
+def SPIRV_BI_SampleMask                  : I32EnumAttrCase<"SampleMask", 20> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_BI_FragDepth                   : I32EnumAttrCase<"FragDepth", 22> {
+def SPIRV_BI_FragDepth                   : I32EnumAttrCase<"FragDepth", 22> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_BI_HelperInvocation            : I32EnumAttrCase<"HelperInvocation", 23> {
+def SPIRV_BI_HelperInvocation            : I32EnumAttrCase<"HelperInvocation", 23> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_BI_NumWorkgroups               : I32EnumAttrCase<"NumWorkgroups", 24>;
-def SPV_BI_WorkgroupSize               : I32EnumAttrCase<"WorkgroupSize", 25>;
-def SPV_BI_WorkgroupId                 : I32EnumAttrCase<"WorkgroupId", 26>;
-def SPV_BI_LocalInvocationId           : I32EnumAttrCase<"LocalInvocationId", 27>;
-def SPV_BI_GlobalInvocationId          : I32EnumAttrCase<"GlobalInvocationId", 28>;
-def SPV_BI_LocalInvocationIndex        : I32EnumAttrCase<"LocalInvocationIndex", 29>;
-def SPV_BI_WorkDim                     : I32EnumAttrCase<"WorkDim", 30> {
+def SPIRV_BI_NumWorkgroups               : I32EnumAttrCase<"NumWorkgroups", 24>;
+def SPIRV_BI_WorkgroupSize               : I32EnumAttrCase<"WorkgroupSize", 25>;
+def SPIRV_BI_WorkgroupId                 : I32EnumAttrCase<"WorkgroupId", 26>;
+def SPIRV_BI_LocalInvocationId           : I32EnumAttrCase<"LocalInvocationId", 27>;
+def SPIRV_BI_GlobalInvocationId          : I32EnumAttrCase<"GlobalInvocationId", 28>;
+def SPIRV_BI_LocalInvocationIndex        : I32EnumAttrCase<"LocalInvocationIndex", 29>;
+def SPIRV_BI_WorkDim                     : I32EnumAttrCase<"WorkDim", 30> {
   list<Availability> availability = [
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_BI_GlobalSize                  : I32EnumAttrCase<"GlobalSize", 31> {
+def SPIRV_BI_GlobalSize                  : I32EnumAttrCase<"GlobalSize", 31> {
   list<Availability> availability = [
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_BI_EnqueuedWorkgroupSize       : I32EnumAttrCase<"EnqueuedWorkgroupSize", 32> {
+def SPIRV_BI_EnqueuedWorkgroupSize       : I32EnumAttrCase<"EnqueuedWorkgroupSize", 32> {
   list<Availability> availability = [
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_BI_GlobalOffset                : I32EnumAttrCase<"GlobalOffset", 33> {
+def SPIRV_BI_GlobalOffset                : I32EnumAttrCase<"GlobalOffset", 33> {
   list<Availability> availability = [
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_BI_GlobalLinearId              : I32EnumAttrCase<"GlobalLinearId", 34> {
+def SPIRV_BI_GlobalLinearId              : I32EnumAttrCase<"GlobalLinearId", 34> {
   list<Availability> availability = [
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_BI_SubgroupSize                : I32EnumAttrCase<"SubgroupSize", 36> {
+def SPIRV_BI_SubgroupSize                : I32EnumAttrCase<"SubgroupSize", 36> {
   list<Availability> availability = [
-    Capability<[SPV_C_GroupNonUniform, SPV_C_Kernel, SPV_C_SubgroupBallotKHR]>
+    Capability<[SPIRV_C_GroupNonUniform, SPIRV_C_Kernel, SPIRV_C_SubgroupBallotKHR]>
   ];
 }
-def SPV_BI_SubgroupMaxSize             : I32EnumAttrCase<"SubgroupMaxSize", 37> {
+def SPIRV_BI_SubgroupMaxSize             : I32EnumAttrCase<"SubgroupMaxSize", 37> {
   list<Availability> availability = [
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_BI_NumSubgroups                : I32EnumAttrCase<"NumSubgroups", 38> {
+def SPIRV_BI_NumSubgroups                : I32EnumAttrCase<"NumSubgroups", 38> {
   list<Availability> availability = [
-    Capability<[SPV_C_GroupNonUniform, SPV_C_Kernel]>
+    Capability<[SPIRV_C_GroupNonUniform, SPIRV_C_Kernel]>
   ];
 }
-def SPV_BI_NumEnqueuedSubgroups        : I32EnumAttrCase<"NumEnqueuedSubgroups", 39> {
+def SPIRV_BI_NumEnqueuedSubgroups        : I32EnumAttrCase<"NumEnqueuedSubgroups", 39> {
   list<Availability> availability = [
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_BI_SubgroupId                  : I32EnumAttrCase<"SubgroupId", 40> {
+def SPIRV_BI_SubgroupId                  : I32EnumAttrCase<"SubgroupId", 40> {
   list<Availability> availability = [
-    Capability<[SPV_C_GroupNonUniform, SPV_C_Kernel]>
+    Capability<[SPIRV_C_GroupNonUniform, SPIRV_C_Kernel]>
   ];
 }
-def SPV_BI_SubgroupLocalInvocationId   : I32EnumAttrCase<"SubgroupLocalInvocationId", 41> {
+def SPIRV_BI_SubgroupLocalInvocationId   : I32EnumAttrCase<"SubgroupLocalInvocationId", 41> {
   list<Availability> availability = [
-    Capability<[SPV_C_GroupNonUniform, SPV_C_Kernel, SPV_C_SubgroupBallotKHR]>
+    Capability<[SPIRV_C_GroupNonUniform, SPIRV_C_Kernel, SPIRV_C_SubgroupBallotKHR]>
   ];
 }
-def SPV_BI_VertexIndex                 : I32EnumAttrCase<"VertexIndex", 42> {
+def SPIRV_BI_VertexIndex                 : I32EnumAttrCase<"VertexIndex", 42> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_BI_InstanceIndex               : I32EnumAttrCase<"InstanceIndex", 43> {
+def SPIRV_BI_InstanceIndex               : I32EnumAttrCase<"InstanceIndex", 43> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_BI_SubgroupEqMask              : I32EnumAttrCase<"SubgroupEqMask", 4416> {
+def SPIRV_BI_SubgroupEqMask              : I32EnumAttrCase<"SubgroupEqMask", 4416> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>,
-    Capability<[SPV_C_GroupNonUniformBallot, SPV_C_SubgroupBallotKHR]>
+    MinVersion<SPIRV_V_1_3>,
+    Capability<[SPIRV_C_GroupNonUniformBallot, SPIRV_C_SubgroupBallotKHR]>
   ];
 }
-def SPV_BI_SubgroupGeMask              : I32EnumAttrCase<"SubgroupGeMask", 4417> {
+def SPIRV_BI_SubgroupGeMask              : I32EnumAttrCase<"SubgroupGeMask", 4417> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>,
-    Capability<[SPV_C_GroupNonUniformBallot, SPV_C_SubgroupBallotKHR]>
+    MinVersion<SPIRV_V_1_3>,
+    Capability<[SPIRV_C_GroupNonUniformBallot, SPIRV_C_SubgroupBallotKHR]>
   ];
 }
-def SPV_BI_SubgroupGtMask              : I32EnumAttrCase<"SubgroupGtMask", 4418> {
+def SPIRV_BI_SubgroupGtMask              : I32EnumAttrCase<"SubgroupGtMask", 4418> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>,
-    Capability<[SPV_C_GroupNonUniformBallot, SPV_C_SubgroupBallotKHR]>
+    MinVersion<SPIRV_V_1_3>,
+    Capability<[SPIRV_C_GroupNonUniformBallot, SPIRV_C_SubgroupBallotKHR]>
   ];
 }
-def SPV_BI_SubgroupLeMask              : I32EnumAttrCase<"SubgroupLeMask", 4419> {
+def SPIRV_BI_SubgroupLeMask              : I32EnumAttrCase<"SubgroupLeMask", 4419> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>,
-    Capability<[SPV_C_GroupNonUniformBallot, SPV_C_SubgroupBallotKHR]>
+    MinVersion<SPIRV_V_1_3>,
+    Capability<[SPIRV_C_GroupNonUniformBallot, SPIRV_C_SubgroupBallotKHR]>
   ];
 }
-def SPV_BI_SubgroupLtMask              : I32EnumAttrCase<"SubgroupLtMask", 4420> {
+def SPIRV_BI_SubgroupLtMask              : I32EnumAttrCase<"SubgroupLtMask", 4420> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>,
-    Capability<[SPV_C_GroupNonUniformBallot, SPV_C_SubgroupBallotKHR]>
+    MinVersion<SPIRV_V_1_3>,
+    Capability<[SPIRV_C_GroupNonUniformBallot, SPIRV_C_SubgroupBallotKHR]>
   ];
 }
-def SPV_BI_BaseVertex                  : I32EnumAttrCase<"BaseVertex", 4424> {
+def SPIRV_BI_BaseVertex                  : I32EnumAttrCase<"BaseVertex", 4424> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_shader_draw_parameters]>,
-    Capability<[SPV_C_DrawParameters]>
+    Extension<[SPIRV_KHR_shader_draw_parameters]>,
+    Capability<[SPIRV_C_DrawParameters]>
   ];
 }
-def SPV_BI_BaseInstance                : I32EnumAttrCase<"BaseInstance", 4425> {
+def SPIRV_BI_BaseInstance                : I32EnumAttrCase<"BaseInstance", 4425> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_shader_draw_parameters]>,
-    Capability<[SPV_C_DrawParameters]>
+    Extension<[SPIRV_KHR_shader_draw_parameters]>,
+    Capability<[SPIRV_C_DrawParameters]>
   ];
 }
-def SPV_BI_DrawIndex                   : I32EnumAttrCase<"DrawIndex", 4426> {
+def SPIRV_BI_DrawIndex                   : I32EnumAttrCase<"DrawIndex", 4426> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_shader_draw_parameters, SPV_NV_mesh_shader]>,
-    Capability<[SPV_C_DrawParameters, SPV_C_MeshShadingNV]>
+    Extension<[SPIRV_KHR_shader_draw_parameters, SPIRV_NV_mesh_shader]>,
+    Capability<[SPIRV_C_DrawParameters, SPIRV_C_MeshShadingNV]>
   ];
 }
-def SPV_BI_PrimitiveShadingRateKHR     : I32EnumAttrCase<"PrimitiveShadingRateKHR", 4432> {
+def SPIRV_BI_PrimitiveShadingRateKHR     : I32EnumAttrCase<"PrimitiveShadingRateKHR", 4432> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_fragment_shading_rate]>,
-    Capability<[SPV_C_FragmentShadingRateKHR]>
+    Extension<[SPIRV_KHR_fragment_shading_rate]>,
+    Capability<[SPIRV_C_FragmentShadingRateKHR]>
   ];
 }
-def SPV_BI_DeviceIndex                 : I32EnumAttrCase<"DeviceIndex", 4438> {
+def SPIRV_BI_DeviceIndex                 : I32EnumAttrCase<"DeviceIndex", 4438> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_device_group]>,
-    Capability<[SPV_C_DeviceGroup]>
+    Extension<[SPIRV_KHR_device_group]>,
+    Capability<[SPIRV_C_DeviceGroup]>
   ];
 }
-def SPV_BI_ViewIndex                   : I32EnumAttrCase<"ViewIndex", 4440> {
+def SPIRV_BI_ViewIndex                   : I32EnumAttrCase<"ViewIndex", 4440> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_multiview]>,
-    Capability<[SPV_C_MultiView]>
+    Extension<[SPIRV_KHR_multiview]>,
+    Capability<[SPIRV_C_MultiView]>
   ];
 }
-def SPV_BI_ShadingRateKHR              : I32EnumAttrCase<"ShadingRateKHR", 4444> {
+def SPIRV_BI_ShadingRateKHR              : I32EnumAttrCase<"ShadingRateKHR", 4444> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_fragment_shading_rate]>,
-    Capability<[SPV_C_FragmentShadingRateKHR]>
+    Extension<[SPIRV_KHR_fragment_shading_rate]>,
+    Capability<[SPIRV_C_FragmentShadingRateKHR]>
   ];
 }
-def SPV_BI_BaryCoordNoPerspAMD         : I32EnumAttrCase<"BaryCoordNoPerspAMD", 4992> {
+def SPIRV_BI_BaryCoordNoPerspAMD         : I32EnumAttrCase<"BaryCoordNoPerspAMD", 4992> {
   list<Availability> availability = [
-    Extension<[SPV_AMD_shader_explicit_vertex_parameter]>
+    Extension<[SPIRV_AMD_shader_explicit_vertex_parameter]>
   ];
 }
-def SPV_BI_BaryCoordNoPerspCentroidAMD : I32EnumAttrCase<"BaryCoordNoPerspCentroidAMD", 4993> {
+def SPIRV_BI_BaryCoordNoPerspCentroidAMD : I32EnumAttrCase<"BaryCoordNoPerspCentroidAMD", 4993> {
   list<Availability> availability = [
-    Extension<[SPV_AMD_shader_explicit_vertex_parameter]>
+    Extension<[SPIRV_AMD_shader_explicit_vertex_parameter]>
   ];
 }
-def SPV_BI_BaryCoordNoPerspSampleAMD   : I32EnumAttrCase<"BaryCoordNoPerspSampleAMD", 4994> {
+def SPIRV_BI_BaryCoordNoPerspSampleAMD   : I32EnumAttrCase<"BaryCoordNoPerspSampleAMD", 4994> {
   list<Availability> availability = [
-    Extension<[SPV_AMD_shader_explicit_vertex_parameter]>
+    Extension<[SPIRV_AMD_shader_explicit_vertex_parameter]>
   ];
 }
-def SPV_BI_BaryCoordSmoothAMD          : I32EnumAttrCase<"BaryCoordSmoothAMD", 4995> {
+def SPIRV_BI_BaryCoordSmoothAMD          : I32EnumAttrCase<"BaryCoordSmoothAMD", 4995> {
   list<Availability> availability = [
-    Extension<[SPV_AMD_shader_explicit_vertex_parameter]>
+    Extension<[SPIRV_AMD_shader_explicit_vertex_parameter]>
   ];
 }
-def SPV_BI_BaryCoordSmoothCentroidAMD  : I32EnumAttrCase<"BaryCoordSmoothCentroidAMD", 4996> {
+def SPIRV_BI_BaryCoordSmoothCentroidAMD  : I32EnumAttrCase<"BaryCoordSmoothCentroidAMD", 4996> {
   list<Availability> availability = [
-    Extension<[SPV_AMD_shader_explicit_vertex_parameter]>
+    Extension<[SPIRV_AMD_shader_explicit_vertex_parameter]>
   ];
 }
-def SPV_BI_BaryCoordSmoothSampleAMD    : I32EnumAttrCase<"BaryCoordSmoothSampleAMD", 4997> {
+def SPIRV_BI_BaryCoordSmoothSampleAMD    : I32EnumAttrCase<"BaryCoordSmoothSampleAMD", 4997> {
   list<Availability> availability = [
-    Extension<[SPV_AMD_shader_explicit_vertex_parameter]>
+    Extension<[SPIRV_AMD_shader_explicit_vertex_parameter]>
   ];
 }
-def SPV_BI_BaryCoordPullModelAMD       : I32EnumAttrCase<"BaryCoordPullModelAMD", 4998> {
+def SPIRV_BI_BaryCoordPullModelAMD       : I32EnumAttrCase<"BaryCoordPullModelAMD", 4998> {
   list<Availability> availability = [
-    Extension<[SPV_AMD_shader_explicit_vertex_parameter]>
+    Extension<[SPIRV_AMD_shader_explicit_vertex_parameter]>
   ];
 }
-def SPV_BI_FragStencilRefEXT           : I32EnumAttrCase<"FragStencilRefEXT", 5014> {
+def SPIRV_BI_FragStencilRefEXT           : I32EnumAttrCase<"FragStencilRefEXT", 5014> {
   list<Availability> availability = [
-    Extension<[SPV_EXT_shader_stencil_export]>,
-    Capability<[SPV_C_StencilExportEXT]>
+    Extension<[SPIRV_EXT_shader_stencil_export]>,
+    Capability<[SPIRV_C_StencilExportEXT]>
   ];
 }
-def SPV_BI_ViewportMaskNV              : I32EnumAttrCase<"ViewportMaskNV", 5253> {
+def SPIRV_BI_ViewportMaskNV              : I32EnumAttrCase<"ViewportMaskNV", 5253> {
   list<Availability> availability = [
-    Extension<[SPV_NV_mesh_shader, SPV_NV_viewport_array2]>,
-    Capability<[SPV_C_MeshShadingNV, SPV_C_ShaderViewportMaskNV]>
+    Extension<[SPIRV_NV_mesh_shader, SPIRV_NV_viewport_array2]>,
+    Capability<[SPIRV_C_MeshShadingNV, SPIRV_C_ShaderViewportMaskNV]>
   ];
 }
-def SPV_BI_SecondaryPositionNV         : I32EnumAttrCase<"SecondaryPositionNV", 5257> {
+def SPIRV_BI_SecondaryPositionNV         : I32EnumAttrCase<"SecondaryPositionNV", 5257> {
   list<Availability> availability = [
-    Extension<[SPV_NV_stereo_view_rendering]>,
-    Capability<[SPV_C_ShaderStereoViewNV]>
+    Extension<[SPIRV_NV_stereo_view_rendering]>,
+    Capability<[SPIRV_C_ShaderStereoViewNV]>
   ];
 }
-def SPV_BI_SecondaryViewportMaskNV     : I32EnumAttrCase<"SecondaryViewportMaskNV", 5258> {
+def SPIRV_BI_SecondaryViewportMaskNV     : I32EnumAttrCase<"SecondaryViewportMaskNV", 5258> {
   list<Availability> availability = [
-    Extension<[SPV_NV_stereo_view_rendering]>,
-    Capability<[SPV_C_ShaderStereoViewNV]>
+    Extension<[SPIRV_NV_stereo_view_rendering]>,
+    Capability<[SPIRV_C_ShaderStereoViewNV]>
   ];
 }
-def SPV_BI_PositionPerViewNV           : I32EnumAttrCase<"PositionPerViewNV", 5261> {
+def SPIRV_BI_PositionPerViewNV           : I32EnumAttrCase<"PositionPerViewNV", 5261> {
   list<Availability> availability = [
-    Extension<[SPV_NVX_multiview_per_view_attributes, SPV_NV_mesh_shader]>,
-    Capability<[SPV_C_MeshShadingNV, SPV_C_PerViewAttributesNV]>
+    Extension<[SPIRV_NVX_multiview_per_view_attributes, SPIRV_NV_mesh_shader]>,
+    Capability<[SPIRV_C_MeshShadingNV, SPIRV_C_PerViewAttributesNV]>
   ];
 }
-def SPV_BI_ViewportMaskPerViewNV       : I32EnumAttrCase<"ViewportMaskPerViewNV", 5262> {
+def SPIRV_BI_ViewportMaskPerViewNV       : I32EnumAttrCase<"ViewportMaskPerViewNV", 5262> {
   list<Availability> availability = [
-    Extension<[SPV_NVX_multiview_per_view_attributes, SPV_NV_mesh_shader]>,
-    Capability<[SPV_C_MeshShadingNV, SPV_C_PerViewAttributesNV]>
+    Extension<[SPIRV_NVX_multiview_per_view_attributes, SPIRV_NV_mesh_shader]>,
+    Capability<[SPIRV_C_MeshShadingNV, SPIRV_C_PerViewAttributesNV]>
   ];
 }
-def SPV_BI_FullyCoveredEXT             : I32EnumAttrCase<"FullyCoveredEXT", 5264> {
+def SPIRV_BI_FullyCoveredEXT             : I32EnumAttrCase<"FullyCoveredEXT", 5264> {
   list<Availability> availability = [
-    Extension<[SPV_EXT_fragment_fully_covered]>,
-    Capability<[SPV_C_FragmentFullyCoveredEXT]>
+    Extension<[SPIRV_EXT_fragment_fully_covered]>,
+    Capability<[SPIRV_C_FragmentFullyCoveredEXT]>
   ];
 }
-def SPV_BI_TaskCountNV                 : I32EnumAttrCase<"TaskCountNV", 5274> {
+def SPIRV_BI_TaskCountNV                 : I32EnumAttrCase<"TaskCountNV", 5274> {
   list<Availability> availability = [
-    Extension<[SPV_NV_mesh_shader]>,
-    Capability<[SPV_C_MeshShadingNV]>
+    Extension<[SPIRV_NV_mesh_shader]>,
+    Capability<[SPIRV_C_MeshShadingNV]>
   ];
 }
-def SPV_BI_PrimitiveCountNV            : I32EnumAttrCase<"PrimitiveCountNV", 5275> {
+def SPIRV_BI_PrimitiveCountNV            : I32EnumAttrCase<"PrimitiveCountNV", 5275> {
   list<Availability> availability = [
-    Extension<[SPV_NV_mesh_shader]>,
-    Capability<[SPV_C_MeshShadingNV]>
+    Extension<[SPIRV_NV_mesh_shader]>,
+    Capability<[SPIRV_C_MeshShadingNV]>
   ];
 }
-def SPV_BI_PrimitiveIndicesNV          : I32EnumAttrCase<"PrimitiveIndicesNV", 5276> {
+def SPIRV_BI_PrimitiveIndicesNV          : I32EnumAttrCase<"PrimitiveIndicesNV", 5276> {
   list<Availability> availability = [
-    Extension<[SPV_NV_mesh_shader]>,
-    Capability<[SPV_C_MeshShadingNV]>
+    Extension<[SPIRV_NV_mesh_shader]>,
+    Capability<[SPIRV_C_MeshShadingNV]>
   ];
 }
-def SPV_BI_ClipDistancePerViewNV       : I32EnumAttrCase<"ClipDistancePerViewNV", 5277> {
+def SPIRV_BI_ClipDistancePerViewNV       : I32EnumAttrCase<"ClipDistancePerViewNV", 5277> {
   list<Availability> availability = [
-    Extension<[SPV_NV_mesh_shader]>,
-    Capability<[SPV_C_MeshShadingNV]>
+    Extension<[SPIRV_NV_mesh_shader]>,
+    Capability<[SPIRV_C_MeshShadingNV]>
   ];
 }
-def SPV_BI_CullDistancePerViewNV       : I32EnumAttrCase<"CullDistancePerViewNV", 5278> {
+def SPIRV_BI_CullDistancePerViewNV       : I32EnumAttrCase<"CullDistancePerViewNV", 5278> {
   list<Availability> availability = [
-    Extension<[SPV_NV_mesh_shader]>,
-    Capability<[SPV_C_MeshShadingNV]>
+    Extension<[SPIRV_NV_mesh_shader]>,
+    Capability<[SPIRV_C_MeshShadingNV]>
   ];
 }
-def SPV_BI_LayerPerViewNV              : I32EnumAttrCase<"LayerPerViewNV", 5279> {
+def SPIRV_BI_LayerPerViewNV              : I32EnumAttrCase<"LayerPerViewNV", 5279> {
   list<Availability> availability = [
-    Extension<[SPV_NV_mesh_shader]>,
-    Capability<[SPV_C_MeshShadingNV]>
+    Extension<[SPIRV_NV_mesh_shader]>,
+    Capability<[SPIRV_C_MeshShadingNV]>
   ];
 }
-def SPV_BI_MeshViewCountNV             : I32EnumAttrCase<"MeshViewCountNV", 5280> {
+def SPIRV_BI_MeshViewCountNV             : I32EnumAttrCase<"MeshViewCountNV", 5280> {
   list<Availability> availability = [
-    Extension<[SPV_NV_mesh_shader]>,
-    Capability<[SPV_C_MeshShadingNV]>
+    Extension<[SPIRV_NV_mesh_shader]>,
+    Capability<[SPIRV_C_MeshShadingNV]>
   ];
 }
-def SPV_BI_MeshViewIndicesNV           : I32EnumAttrCase<"MeshViewIndicesNV", 5281> {
+def SPIRV_BI_MeshViewIndicesNV           : I32EnumAttrCase<"MeshViewIndicesNV", 5281> {
   list<Availability> availability = [
-    Extension<[SPV_NV_mesh_shader]>,
-    Capability<[SPV_C_MeshShadingNV]>
+    Extension<[SPIRV_NV_mesh_shader]>,
+    Capability<[SPIRV_C_MeshShadingNV]>
   ];
 }
-def SPV_BI_BaryCoordKHR                : I32EnumAttrCase<"BaryCoordKHR", 5286> {
+def SPIRV_BI_BaryCoordKHR                : I32EnumAttrCase<"BaryCoordKHR", 5286> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_fragment_shader_barycentric, SPV_NV_fragment_shader_barycentric]>,
-    Capability<[SPV_C_FragmentBarycentricKHR]>
+    Extension<[SPIRV_KHR_fragment_shader_barycentric, SPIRV_NV_fragment_shader_barycentric]>,
+    Capability<[SPIRV_C_FragmentBarycentricKHR]>
   ];
 }
-def SPV_BI_BaryCoordNoPerspKHR         : I32EnumAttrCase<"BaryCoordNoPerspKHR", 5287> {
+def SPIRV_BI_BaryCoordNoPerspKHR         : I32EnumAttrCase<"BaryCoordNoPerspKHR", 5287> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_fragment_shader_barycentric, SPV_NV_fragment_shader_barycentric]>,
-    Capability<[SPV_C_FragmentBarycentricKHR]>
+    Extension<[SPIRV_KHR_fragment_shader_barycentric, SPIRV_NV_fragment_shader_barycentric]>,
+    Capability<[SPIRV_C_FragmentBarycentricKHR]>
   ];
 }
-def SPV_BI_FragSizeEXT                 : I32EnumAttrCase<"FragSizeEXT", 5292> {
+def SPIRV_BI_FragSizeEXT                 : I32EnumAttrCase<"FragSizeEXT", 5292> {
   list<Availability> availability = [
-    Extension<[SPV_EXT_fragment_invocation_density, SPV_NV_shading_rate]>,
-    Capability<[SPV_C_FragmentDensityEXT]>
+    Extension<[SPIRV_EXT_fragment_invocation_density, SPIRV_NV_shading_rate]>,
+    Capability<[SPIRV_C_FragmentDensityEXT]>
   ];
 }
-def SPV_BI_FragInvocationCountEXT      : I32EnumAttrCase<"FragInvocationCountEXT", 5293> {
+def SPIRV_BI_FragInvocationCountEXT      : I32EnumAttrCase<"FragInvocationCountEXT", 5293> {
   list<Availability> availability = [
-    Extension<[SPV_EXT_fragment_invocation_density, SPV_NV_shading_rate]>,
-    Capability<[SPV_C_FragmentDensityEXT]>
+    Extension<[SPIRV_EXT_fragment_invocation_density, SPIRV_NV_shading_rate]>,
+    Capability<[SPIRV_C_FragmentDensityEXT]>
   ];
 }
-def SPV_BI_LaunchIdKHR                 : I32EnumAttrCase<"LaunchIdKHR", 5319> {
+def SPIRV_BI_LaunchIdKHR                 : I32EnumAttrCase<"LaunchIdKHR", 5319> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>,
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Extension<[SPIRV_KHR_ray_tracing, SPIRV_NV_ray_tracing]>,
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_BI_LaunchSizeKHR               : I32EnumAttrCase<"LaunchSizeKHR", 5320> {
+def SPIRV_BI_LaunchSizeKHR               : I32EnumAttrCase<"LaunchSizeKHR", 5320> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>,
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Extension<[SPIRV_KHR_ray_tracing, SPIRV_NV_ray_tracing]>,
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_BI_WorldRayOriginKHR           : I32EnumAttrCase<"WorldRayOriginKHR", 5321> {
+def SPIRV_BI_WorldRayOriginKHR           : I32EnumAttrCase<"WorldRayOriginKHR", 5321> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>,
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Extension<[SPIRV_KHR_ray_tracing, SPIRV_NV_ray_tracing]>,
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_BI_WorldRayDirectionKHR        : I32EnumAttrCase<"WorldRayDirectionKHR", 5322> {
+def SPIRV_BI_WorldRayDirectionKHR        : I32EnumAttrCase<"WorldRayDirectionKHR", 5322> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>,
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Extension<[SPIRV_KHR_ray_tracing, SPIRV_NV_ray_tracing]>,
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_BI_ObjectRayOriginKHR          : I32EnumAttrCase<"ObjectRayOriginKHR", 5323> {
+def SPIRV_BI_ObjectRayOriginKHR          : I32EnumAttrCase<"ObjectRayOriginKHR", 5323> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>,
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Extension<[SPIRV_KHR_ray_tracing, SPIRV_NV_ray_tracing]>,
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_BI_ObjectRayDirectionKHR       : I32EnumAttrCase<"ObjectRayDirectionKHR", 5324> {
+def SPIRV_BI_ObjectRayDirectionKHR       : I32EnumAttrCase<"ObjectRayDirectionKHR", 5324> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>,
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Extension<[SPIRV_KHR_ray_tracing, SPIRV_NV_ray_tracing]>,
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_BI_RayTminKHR                  : I32EnumAttrCase<"RayTminKHR", 5325> {
+def SPIRV_BI_RayTminKHR                  : I32EnumAttrCase<"RayTminKHR", 5325> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>,
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Extension<[SPIRV_KHR_ray_tracing, SPIRV_NV_ray_tracing]>,
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_BI_RayTmaxKHR                  : I32EnumAttrCase<"RayTmaxKHR", 5326> {
+def SPIRV_BI_RayTmaxKHR                  : I32EnumAttrCase<"RayTmaxKHR", 5326> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>,
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Extension<[SPIRV_KHR_ray_tracing, SPIRV_NV_ray_tracing]>,
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_BI_InstanceCustomIndexKHR      : I32EnumAttrCase<"InstanceCustomIndexKHR", 5327> {
+def SPIRV_BI_InstanceCustomIndexKHR      : I32EnumAttrCase<"InstanceCustomIndexKHR", 5327> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>,
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Extension<[SPIRV_KHR_ray_tracing, SPIRV_NV_ray_tracing]>,
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_BI_ObjectToWorldKHR            : I32EnumAttrCase<"ObjectToWorldKHR", 5330> {
+def SPIRV_BI_ObjectToWorldKHR            : I32EnumAttrCase<"ObjectToWorldKHR", 5330> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>,
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Extension<[SPIRV_KHR_ray_tracing, SPIRV_NV_ray_tracing]>,
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_BI_WorldToObjectKHR            : I32EnumAttrCase<"WorldToObjectKHR", 5331> {
+def SPIRV_BI_WorldToObjectKHR            : I32EnumAttrCase<"WorldToObjectKHR", 5331> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>,
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Extension<[SPIRV_KHR_ray_tracing, SPIRV_NV_ray_tracing]>,
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_BI_HitTNV                      : I32EnumAttrCase<"HitTNV", 5332> {
+def SPIRV_BI_HitTNV                      : I32EnumAttrCase<"HitTNV", 5332> {
   list<Availability> availability = [
-    Extension<[SPV_NV_ray_tracing]>,
-    Capability<[SPV_C_RayTracingNV]>
+    Extension<[SPIRV_NV_ray_tracing]>,
+    Capability<[SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_BI_HitKindKHR                  : I32EnumAttrCase<"HitKindKHR", 5333> {
+def SPIRV_BI_HitKindKHR                  : I32EnumAttrCase<"HitKindKHR", 5333> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>,
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Extension<[SPIRV_KHR_ray_tracing, SPIRV_NV_ray_tracing]>,
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_BI_CurrentRayTimeNV            : I32EnumAttrCase<"CurrentRayTimeNV", 5334> {
+def SPIRV_BI_CurrentRayTimeNV            : I32EnumAttrCase<"CurrentRayTimeNV", 5334> {
   list<Availability> availability = [
-    Extension<[SPV_NV_ray_tracing_motion_blur]>,
-    Capability<[SPV_C_RayTracingMotionBlurNV]>
+    Extension<[SPIRV_NV_ray_tracing_motion_blur]>,
+    Capability<[SPIRV_C_RayTracingMotionBlurNV]>
   ];
 }
-def SPV_BI_IncomingRayFlagsKHR         : I32EnumAttrCase<"IncomingRayFlagsKHR", 5351> {
+def SPIRV_BI_IncomingRayFlagsKHR         : I32EnumAttrCase<"IncomingRayFlagsKHR", 5351> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>,
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Extension<[SPIRV_KHR_ray_tracing, SPIRV_NV_ray_tracing]>,
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_BI_RayGeometryIndexKHR         : I32EnumAttrCase<"RayGeometryIndexKHR", 5352> {
+def SPIRV_BI_RayGeometryIndexKHR         : I32EnumAttrCase<"RayGeometryIndexKHR", 5352> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing]>,
-    Capability<[SPV_C_RayTracingKHR]>
+    Extension<[SPIRV_KHR_ray_tracing]>,
+    Capability<[SPIRV_C_RayTracingKHR]>
   ];
 }
-def SPV_BI_WarpsPerSMNV                : I32EnumAttrCase<"WarpsPerSMNV", 5374> {
+def SPIRV_BI_WarpsPerSMNV                : I32EnumAttrCase<"WarpsPerSMNV", 5374> {
   list<Availability> availability = [
-    Extension<[SPV_NV_shader_sm_builtins]>,
-    Capability<[SPV_C_ShaderSMBuiltinsNV]>
+    Extension<[SPIRV_NV_shader_sm_builtins]>,
+    Capability<[SPIRV_C_ShaderSMBuiltinsNV]>
   ];
 }
-def SPV_BI_SMCountNV                   : I32EnumAttrCase<"SMCountNV", 5375> {
+def SPIRV_BI_SMCountNV                   : I32EnumAttrCase<"SMCountNV", 5375> {
   list<Availability> availability = [
-    Extension<[SPV_NV_shader_sm_builtins]>,
-    Capability<[SPV_C_ShaderSMBuiltinsNV]>
+    Extension<[SPIRV_NV_shader_sm_builtins]>,
+    Capability<[SPIRV_C_ShaderSMBuiltinsNV]>
   ];
 }
-def SPV_BI_WarpIDNV                    : I32EnumAttrCase<"WarpIDNV", 5376> {
+def SPIRV_BI_WarpIDNV                    : I32EnumAttrCase<"WarpIDNV", 5376> {
   list<Availability> availability = [
-    Extension<[SPV_NV_shader_sm_builtins]>,
-    Capability<[SPV_C_ShaderSMBuiltinsNV]>
+    Extension<[SPIRV_NV_shader_sm_builtins]>,
+    Capability<[SPIRV_C_ShaderSMBuiltinsNV]>
   ];
 }
-def SPV_BI_SMIDNV                      : I32EnumAttrCase<"SMIDNV", 5377> {
+def SPIRV_BI_SMIDNV                      : I32EnumAttrCase<"SMIDNV", 5377> {
   list<Availability> availability = [
-    Extension<[SPV_NV_shader_sm_builtins]>,
-    Capability<[SPV_C_ShaderSMBuiltinsNV]>
+    Extension<[SPIRV_NV_shader_sm_builtins]>,
+    Capability<[SPIRV_C_ShaderSMBuiltinsNV]>
   ];
 }
-def SPV_BI_CullMaskKHR                 : I32EnumAttrCase<"CullMaskKHR", 6021> {
+def SPIRV_BI_CullMaskKHR                 : I32EnumAttrCase<"CullMaskKHR", 6021> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_cull_mask]>,
-    Capability<[SPV_C_RayCullMaskKHR]>
+    Extension<[SPIRV_KHR_ray_cull_mask]>,
+    Capability<[SPIRV_C_RayCullMaskKHR]>
   ];
 }
 
-def SPV_BuiltInAttr :
-    SPV_I32EnumAttr<"BuiltIn", "valid SPIR-V BuiltIn", "built_in", [
-      SPV_BI_Position, SPV_BI_PointSize, SPV_BI_ClipDistance, SPV_BI_CullDistance,
-      SPV_BI_VertexId, SPV_BI_InstanceId, SPV_BI_PrimitiveId, SPV_BI_InvocationId,
-      SPV_BI_Layer, SPV_BI_ViewportIndex, SPV_BI_TessLevelOuter,
-      SPV_BI_TessLevelInner, SPV_BI_TessCoord, SPV_BI_PatchVertices,
-      SPV_BI_FragCoord, SPV_BI_PointCoord, SPV_BI_FrontFacing, SPV_BI_SampleId,
-      SPV_BI_SamplePosition, SPV_BI_SampleMask, SPV_BI_FragDepth,
-      SPV_BI_HelperInvocation, SPV_BI_NumWorkgroups, SPV_BI_WorkgroupSize,
-      SPV_BI_WorkgroupId, SPV_BI_LocalInvocationId, SPV_BI_GlobalInvocationId,
-      SPV_BI_LocalInvocationIndex, SPV_BI_WorkDim, SPV_BI_GlobalSize,
-      SPV_BI_EnqueuedWorkgroupSize, SPV_BI_GlobalOffset, SPV_BI_GlobalLinearId,
-      SPV_BI_SubgroupSize, SPV_BI_SubgroupMaxSize, SPV_BI_NumSubgroups,
-      SPV_BI_NumEnqueuedSubgroups, SPV_BI_SubgroupId,
-      SPV_BI_SubgroupLocalInvocationId, SPV_BI_VertexIndex, SPV_BI_InstanceIndex,
-      SPV_BI_SubgroupEqMask, SPV_BI_SubgroupGeMask, SPV_BI_SubgroupGtMask,
-      SPV_BI_SubgroupLeMask, SPV_BI_SubgroupLtMask, SPV_BI_BaseVertex,
-      SPV_BI_BaseInstance, SPV_BI_DrawIndex, SPV_BI_PrimitiveShadingRateKHR,
-      SPV_BI_DeviceIndex, SPV_BI_ViewIndex, SPV_BI_ShadingRateKHR,
-      SPV_BI_BaryCoordNoPerspAMD, SPV_BI_BaryCoordNoPerspCentroidAMD,
-      SPV_BI_BaryCoordNoPerspSampleAMD, SPV_BI_BaryCoordSmoothAMD,
-      SPV_BI_BaryCoordSmoothCentroidAMD, SPV_BI_BaryCoordSmoothSampleAMD,
-      SPV_BI_BaryCoordPullModelAMD, SPV_BI_FragStencilRefEXT, SPV_BI_ViewportMaskNV,
-      SPV_BI_SecondaryPositionNV, SPV_BI_SecondaryViewportMaskNV,
-      SPV_BI_PositionPerViewNV, SPV_BI_ViewportMaskPerViewNV, SPV_BI_FullyCoveredEXT,
-      SPV_BI_TaskCountNV, SPV_BI_PrimitiveCountNV, SPV_BI_PrimitiveIndicesNV,
-      SPV_BI_ClipDistancePerViewNV, SPV_BI_CullDistancePerViewNV,
-      SPV_BI_LayerPerViewNV, SPV_BI_MeshViewCountNV, SPV_BI_MeshViewIndicesNV,
-      SPV_BI_BaryCoordKHR, SPV_BI_BaryCoordNoPerspKHR, SPV_BI_FragSizeEXT,
-      SPV_BI_FragInvocationCountEXT, SPV_BI_LaunchIdKHR, SPV_BI_LaunchSizeKHR,
-      SPV_BI_WorldRayOriginKHR, SPV_BI_WorldRayDirectionKHR,
-      SPV_BI_ObjectRayOriginKHR, SPV_BI_ObjectRayDirectionKHR, SPV_BI_RayTminKHR,
-      SPV_BI_RayTmaxKHR, SPV_BI_InstanceCustomIndexKHR, SPV_BI_ObjectToWorldKHR,
-      SPV_BI_WorldToObjectKHR, SPV_BI_HitTNV, SPV_BI_HitKindKHR,
-      SPV_BI_CurrentRayTimeNV, SPV_BI_IncomingRayFlagsKHR,
-      SPV_BI_RayGeometryIndexKHR, SPV_BI_WarpsPerSMNV, SPV_BI_SMCountNV,
-      SPV_BI_WarpIDNV, SPV_BI_SMIDNV, SPV_BI_CullMaskKHR
+def SPIRV_BuiltInAttr :
+    SPIRV_I32EnumAttr<"BuiltIn", "valid SPIR-V BuiltIn", "built_in", [
+      SPIRV_BI_Position, SPIRV_BI_PointSize, SPIRV_BI_ClipDistance, SPIRV_BI_CullDistance,
+      SPIRV_BI_VertexId, SPIRV_BI_InstanceId, SPIRV_BI_PrimitiveId, SPIRV_BI_InvocationId,
+      SPIRV_BI_Layer, SPIRV_BI_ViewportIndex, SPIRV_BI_TessLevelOuter,
+      SPIRV_BI_TessLevelInner, SPIRV_BI_TessCoord, SPIRV_BI_PatchVertices,
+      SPIRV_BI_FragCoord, SPIRV_BI_PointCoord, SPIRV_BI_FrontFacing, SPIRV_BI_SampleId,
+      SPIRV_BI_SamplePosition, SPIRV_BI_SampleMask, SPIRV_BI_FragDepth,
+      SPIRV_BI_HelperInvocation, SPIRV_BI_NumWorkgroups, SPIRV_BI_WorkgroupSize,
+      SPIRV_BI_WorkgroupId, SPIRV_BI_LocalInvocationId, SPIRV_BI_GlobalInvocationId,
+      SPIRV_BI_LocalInvocationIndex, SPIRV_BI_WorkDim, SPIRV_BI_GlobalSize,
+      SPIRV_BI_EnqueuedWorkgroupSize, SPIRV_BI_GlobalOffset, SPIRV_BI_GlobalLinearId,
+      SPIRV_BI_SubgroupSize, SPIRV_BI_SubgroupMaxSize, SPIRV_BI_NumSubgroups,
+      SPIRV_BI_NumEnqueuedSubgroups, SPIRV_BI_SubgroupId,
+      SPIRV_BI_SubgroupLocalInvocationId, SPIRV_BI_VertexIndex, SPIRV_BI_InstanceIndex,
+      SPIRV_BI_SubgroupEqMask, SPIRV_BI_SubgroupGeMask, SPIRV_BI_SubgroupGtMask,
+      SPIRV_BI_SubgroupLeMask, SPIRV_BI_SubgroupLtMask, SPIRV_BI_BaseVertex,
+      SPIRV_BI_BaseInstance, SPIRV_BI_DrawIndex, SPIRV_BI_PrimitiveShadingRateKHR,
+      SPIRV_BI_DeviceIndex, SPIRV_BI_ViewIndex, SPIRV_BI_ShadingRateKHR,
+      SPIRV_BI_BaryCoordNoPerspAMD, SPIRV_BI_BaryCoordNoPerspCentroidAMD,
+      SPIRV_BI_BaryCoordNoPerspSampleAMD, SPIRV_BI_BaryCoordSmoothAMD,
+      SPIRV_BI_BaryCoordSmoothCentroidAMD, SPIRV_BI_BaryCoordSmoothSampleAMD,
+      SPIRV_BI_BaryCoordPullModelAMD, SPIRV_BI_FragStencilRefEXT, SPIRV_BI_ViewportMaskNV,
+      SPIRV_BI_SecondaryPositionNV, SPIRV_BI_SecondaryViewportMaskNV,
+      SPIRV_BI_PositionPerViewNV, SPIRV_BI_ViewportMaskPerViewNV, SPIRV_BI_FullyCoveredEXT,
+      SPIRV_BI_TaskCountNV, SPIRV_BI_PrimitiveCountNV, SPIRV_BI_PrimitiveIndicesNV,
+      SPIRV_BI_ClipDistancePerViewNV, SPIRV_BI_CullDistancePerViewNV,
+      SPIRV_BI_LayerPerViewNV, SPIRV_BI_MeshViewCountNV, SPIRV_BI_MeshViewIndicesNV,
+      SPIRV_BI_BaryCoordKHR, SPIRV_BI_BaryCoordNoPerspKHR, SPIRV_BI_FragSizeEXT,
+      SPIRV_BI_FragInvocationCountEXT, SPIRV_BI_LaunchIdKHR, SPIRV_BI_LaunchSizeKHR,
+      SPIRV_BI_WorldRayOriginKHR, SPIRV_BI_WorldRayDirectionKHR,
+      SPIRV_BI_ObjectRayOriginKHR, SPIRV_BI_ObjectRayDirectionKHR, SPIRV_BI_RayTminKHR,
+      SPIRV_BI_RayTmaxKHR, SPIRV_BI_InstanceCustomIndexKHR, SPIRV_BI_ObjectToWorldKHR,
+      SPIRV_BI_WorldToObjectKHR, SPIRV_BI_HitTNV, SPIRV_BI_HitKindKHR,
+      SPIRV_BI_CurrentRayTimeNV, SPIRV_BI_IncomingRayFlagsKHR,
+      SPIRV_BI_RayGeometryIndexKHR, SPIRV_BI_WarpsPerSMNV, SPIRV_BI_SMCountNV,
+      SPIRV_BI_WarpIDNV, SPIRV_BI_SMIDNV, SPIRV_BI_CullMaskKHR
     ]>;
 
-def SPV_D_RelaxedPrecision                   : I32EnumAttrCase<"RelaxedPrecision", 0> {
+def SPIRV_D_RelaxedPrecision                   : I32EnumAttrCase<"RelaxedPrecision", 0> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_D_SpecId                             : I32EnumAttrCase<"SpecId", 1> {
+def SPIRV_D_SpecId                             : I32EnumAttrCase<"SpecId", 1> {
   list<Availability> availability = [
-    Capability<[SPV_C_Kernel, SPV_C_Shader]>
+    Capability<[SPIRV_C_Kernel, SPIRV_C_Shader]>
   ];
 }
-def SPV_D_Block                              : I32EnumAttrCase<"Block", 2> {
+def SPIRV_D_Block                              : I32EnumAttrCase<"Block", 2> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_D_BufferBlock                        : I32EnumAttrCase<"BufferBlock", 3> {
+def SPIRV_D_BufferBlock                        : I32EnumAttrCase<"BufferBlock", 3> {
   list<Availability> availability = [
-    MaxVersion<SPV_V_1_3>,
-    Capability<[SPV_C_Shader]>
+    MaxVersion<SPIRV_V_1_3>,
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_D_RowMajor                           : I32EnumAttrCase<"RowMajor", 4> {
+def SPIRV_D_RowMajor                           : I32EnumAttrCase<"RowMajor", 4> {
   list<Availability> availability = [
-    Capability<[SPV_C_Matrix]>
+    Capability<[SPIRV_C_Matrix]>
   ];
 }
-def SPV_D_ColMajor                           : I32EnumAttrCase<"ColMajor", 5> {
+def SPIRV_D_ColMajor                           : I32EnumAttrCase<"ColMajor", 5> {
   list<Availability> availability = [
-    Capability<[SPV_C_Matrix]>
+    Capability<[SPIRV_C_Matrix]>
   ];
 }
-def SPV_D_ArrayStride                        : I32EnumAttrCase<"ArrayStride", 6> {
+def SPIRV_D_ArrayStride                        : I32EnumAttrCase<"ArrayStride", 6> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_D_MatrixStride                       : I32EnumAttrCase<"MatrixStride", 7> {
+def SPIRV_D_MatrixStride                       : I32EnumAttrCase<"MatrixStride", 7> {
   list<Availability> availability = [
-    Capability<[SPV_C_Matrix]>
+    Capability<[SPIRV_C_Matrix]>
   ];
 }
-def SPV_D_GLSLShared                         : I32EnumAttrCase<"GLSLShared", 8> {
+def SPIRV_D_GLSLShared                         : I32EnumAttrCase<"GLSLShared", 8> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_D_GLSLPacked                         : I32EnumAttrCase<"GLSLPacked", 9> {
+def SPIRV_D_GLSLPacked                         : I32EnumAttrCase<"GLSLPacked", 9> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_D_CPacked                            : I32EnumAttrCase<"CPacked", 10> {
+def SPIRV_D_CPacked                            : I32EnumAttrCase<"CPacked", 10> {
   list<Availability> availability = [
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_D_BuiltIn                            : I32EnumAttrCase<"BuiltIn", 11>;
-def SPV_D_NoPerspective                      : I32EnumAttrCase<"NoPerspective", 13> {
+def SPIRV_D_BuiltIn                            : I32EnumAttrCase<"BuiltIn", 11>;
+def SPIRV_D_NoPerspective                      : I32EnumAttrCase<"NoPerspective", 13> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_D_Flat                               : I32EnumAttrCase<"Flat", 14> {
+def SPIRV_D_Flat                               : I32EnumAttrCase<"Flat", 14> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_D_Patch                              : I32EnumAttrCase<"Patch", 15> {
+def SPIRV_D_Patch                              : I32EnumAttrCase<"Patch", 15> {
   list<Availability> availability = [
-    Capability<[SPV_C_Tessellation]>
+    Capability<[SPIRV_C_Tessellation]>
   ];
 }
-def SPV_D_Centroid                           : I32EnumAttrCase<"Centroid", 16> {
+def SPIRV_D_Centroid                           : I32EnumAttrCase<"Centroid", 16> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_D_Sample                             : I32EnumAttrCase<"Sample", 17> {
+def SPIRV_D_Sample                             : I32EnumAttrCase<"Sample", 17> {
   list<Availability> availability = [
-    Capability<[SPV_C_SampleRateShading]>
+    Capability<[SPIRV_C_SampleRateShading]>
   ];
 }
-def SPV_D_Invariant                          : I32EnumAttrCase<"Invariant", 18> {
+def SPIRV_D_Invariant                          : I32EnumAttrCase<"Invariant", 18> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_D_Restrict                           : I32EnumAttrCase<"Restrict", 19>;
-def SPV_D_Aliased                            : I32EnumAttrCase<"Aliased", 20>;
-def SPV_D_Volatile                           : I32EnumAttrCase<"Volatile", 21>;
-def SPV_D_Constant                           : I32EnumAttrCase<"Constant", 22> {
+def SPIRV_D_Restrict                           : I32EnumAttrCase<"Restrict", 19>;
+def SPIRV_D_Aliased                            : I32EnumAttrCase<"Aliased", 20>;
+def SPIRV_D_Volatile                           : I32EnumAttrCase<"Volatile", 21>;
+def SPIRV_D_Constant                           : I32EnumAttrCase<"Constant", 22> {
   list<Availability> availability = [
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_D_Coherent                           : I32EnumAttrCase<"Coherent", 23>;
-def SPV_D_NonWritable                        : I32EnumAttrCase<"NonWritable", 24>;
-def SPV_D_NonReadable                        : I32EnumAttrCase<"NonReadable", 25>;
-def SPV_D_Uniform                            : I32EnumAttrCase<"Uniform", 26> {
+def SPIRV_D_Coherent                           : I32EnumAttrCase<"Coherent", 23>;
+def SPIRV_D_NonWritable                        : I32EnumAttrCase<"NonWritable", 24>;
+def SPIRV_D_NonReadable                        : I32EnumAttrCase<"NonReadable", 25>;
+def SPIRV_D_Uniform                            : I32EnumAttrCase<"Uniform", 26> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader, SPV_C_UniformDecoration]>
+    Capability<[SPIRV_C_Shader, SPIRV_C_UniformDecoration]>
   ];
 }
-def SPV_D_UniformId                          : I32EnumAttrCase<"UniformId", 27> {
+def SPIRV_D_UniformId                          : I32EnumAttrCase<"UniformId", 27> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>,
-    Capability<[SPV_C_Shader, SPV_C_UniformDecoration]>
+    MinVersion<SPIRV_V_1_4>,
+    Capability<[SPIRV_C_Shader, SPIRV_C_UniformDecoration]>
   ];
 }
-def SPV_D_SaturatedConversion                : I32EnumAttrCase<"SaturatedConversion", 28> {
+def SPIRV_D_SaturatedConversion                : I32EnumAttrCase<"SaturatedConversion", 28> {
   list<Availability> availability = [
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_D_Stream                             : I32EnumAttrCase<"Stream", 29> {
+def SPIRV_D_Stream                             : I32EnumAttrCase<"Stream", 29> {
   list<Availability> availability = [
-    Capability<[SPV_C_GeometryStreams]>
+    Capability<[SPIRV_C_GeometryStreams]>
   ];
 }
-def SPV_D_Location                           : I32EnumAttrCase<"Location", 30> {
+def SPIRV_D_Location                           : I32EnumAttrCase<"Location", 30> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_D_Component                          : I32EnumAttrCase<"Component", 31> {
+def SPIRV_D_Component                          : I32EnumAttrCase<"Component", 31> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_D_Index                              : I32EnumAttrCase<"Index", 32> {
+def SPIRV_D_Index                              : I32EnumAttrCase<"Index", 32> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_D_Binding                            : I32EnumAttrCase<"Binding", 33> {
+def SPIRV_D_Binding                            : I32EnumAttrCase<"Binding", 33> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_D_DescriptorSet                      : I32EnumAttrCase<"DescriptorSet", 34> {
+def SPIRV_D_DescriptorSet                      : I32EnumAttrCase<"DescriptorSet", 34> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_D_Offset                             : I32EnumAttrCase<"Offset", 35> {
+def SPIRV_D_Offset                             : I32EnumAttrCase<"Offset", 35> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_D_XfbBuffer                          : I32EnumAttrCase<"XfbBuffer", 36> {
+def SPIRV_D_XfbBuffer                          : I32EnumAttrCase<"XfbBuffer", 36> {
   list<Availability> availability = [
-    Capability<[SPV_C_TransformFeedback]>
+    Capability<[SPIRV_C_TransformFeedback]>
   ];
 }
-def SPV_D_XfbStride                          : I32EnumAttrCase<"XfbStride", 37> {
+def SPIRV_D_XfbStride                          : I32EnumAttrCase<"XfbStride", 37> {
   list<Availability> availability = [
-    Capability<[SPV_C_TransformFeedback]>
+    Capability<[SPIRV_C_TransformFeedback]>
   ];
 }
-def SPV_D_FuncParamAttr                      : I32EnumAttrCase<"FuncParamAttr", 38> {
+def SPIRV_D_FuncParamAttr                      : I32EnumAttrCase<"FuncParamAttr", 38> {
   list<Availability> availability = [
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_D_FPRoundingMode                     : I32EnumAttrCase<"FPRoundingMode", 39>;
-def SPV_D_FPFastMathMode                     : I32EnumAttrCase<"FPFastMathMode", 40> {
+def SPIRV_D_FPRoundingMode                     : I32EnumAttrCase<"FPRoundingMode", 39>;
+def SPIRV_D_FPFastMathMode                     : I32EnumAttrCase<"FPFastMathMode", 40> {
   list<Availability> availability = [
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_D_LinkageAttributes                  : I32EnumAttrCase<"LinkageAttributes", 41> {
+def SPIRV_D_LinkageAttributes                  : I32EnumAttrCase<"LinkageAttributes", 41> {
   list<Availability> availability = [
-    Capability<[SPV_C_Linkage]>
+    Capability<[SPIRV_C_Linkage]>
   ];
 }
-def SPV_D_NoContraction                      : I32EnumAttrCase<"NoContraction", 42> {
+def SPIRV_D_NoContraction                      : I32EnumAttrCase<"NoContraction", 42> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_D_InputAttachmentIndex               : I32EnumAttrCase<"InputAttachmentIndex", 43> {
+def SPIRV_D_InputAttachmentIndex               : I32EnumAttrCase<"InputAttachmentIndex", 43> {
   list<Availability> availability = [
-    Capability<[SPV_C_InputAttachment]>
+    Capability<[SPIRV_C_InputAttachment]>
   ];
 }
-def SPV_D_Alignment                          : I32EnumAttrCase<"Alignment", 44> {
+def SPIRV_D_Alignment                          : I32EnumAttrCase<"Alignment", 44> {
   list<Availability> availability = [
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_D_MaxByteOffset                      : I32EnumAttrCase<"MaxByteOffset", 45> {
+def SPIRV_D_MaxByteOffset                      : I32EnumAttrCase<"MaxByteOffset", 45> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_1>,
-    Capability<[SPV_C_Addresses]>
+    MinVersion<SPIRV_V_1_1>,
+    Capability<[SPIRV_C_Addresses]>
   ];
 }
-def SPV_D_AlignmentId                        : I32EnumAttrCase<"AlignmentId", 46> {
+def SPIRV_D_AlignmentId                        : I32EnumAttrCase<"AlignmentId", 46> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_2>,
-    Capability<[SPV_C_Kernel]>
+    MinVersion<SPIRV_V_1_2>,
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_D_MaxByteOffsetId                    : I32EnumAttrCase<"MaxByteOffsetId", 47> {
+def SPIRV_D_MaxByteOffsetId                    : I32EnumAttrCase<"MaxByteOffsetId", 47> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_2>,
-    Capability<[SPV_C_Addresses]>
+    MinVersion<SPIRV_V_1_2>,
+    Capability<[SPIRV_C_Addresses]>
   ];
 }
-def SPV_D_NoSignedWrap                       : I32EnumAttrCase<"NoSignedWrap", 4469> {
+def SPIRV_D_NoSignedWrap                       : I32EnumAttrCase<"NoSignedWrap", 4469> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_no_integer_wrap_decoration]>
+    Extension<[SPIRV_KHR_no_integer_wrap_decoration]>
   ];
 }
-def SPV_D_NoUnsignedWrap                     : I32EnumAttrCase<"NoUnsignedWrap", 4470> {
+def SPIRV_D_NoUnsignedWrap                     : I32EnumAttrCase<"NoUnsignedWrap", 4470> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_no_integer_wrap_decoration]>
+    Extension<[SPIRV_KHR_no_integer_wrap_decoration]>
   ];
 }
-def SPV_D_ExplicitInterpAMD                  : I32EnumAttrCase<"ExplicitInterpAMD", 4999> {
+def SPIRV_D_ExplicitInterpAMD                  : I32EnumAttrCase<"ExplicitInterpAMD", 4999> {
   list<Availability> availability = [
-    Extension<[SPV_AMD_shader_explicit_vertex_parameter]>
+    Extension<[SPIRV_AMD_shader_explicit_vertex_parameter]>
   ];
 }
-def SPV_D_OverrideCoverageNV                 : I32EnumAttrCase<"OverrideCoverageNV", 5248> {
+def SPIRV_D_OverrideCoverageNV                 : I32EnumAttrCase<"OverrideCoverageNV", 5248> {
   list<Availability> availability = [
-    Extension<[SPV_NV_sample_mask_override_coverage]>,
-    Capability<[SPV_C_SampleMaskOverrideCoverageNV]>
+    Extension<[SPIRV_NV_sample_mask_override_coverage]>,
+    Capability<[SPIRV_C_SampleMaskOverrideCoverageNV]>
   ];
 }
-def SPV_D_PassthroughNV                      : I32EnumAttrCase<"PassthroughNV", 5250> {
+def SPIRV_D_PassthroughNV                      : I32EnumAttrCase<"PassthroughNV", 5250> {
   list<Availability> availability = [
-    Extension<[SPV_NV_geometry_shader_passthrough]>,
-    Capability<[SPV_C_GeometryShaderPassthroughNV]>
+    Extension<[SPIRV_NV_geometry_shader_passthrough]>,
+    Capability<[SPIRV_C_GeometryShaderPassthroughNV]>
   ];
 }
-def SPV_D_ViewportRelativeNV                 : I32EnumAttrCase<"ViewportRelativeNV", 5252> {
+def SPIRV_D_ViewportRelativeNV                 : I32EnumAttrCase<"ViewportRelativeNV", 5252> {
   list<Availability> availability = [
-    Capability<[SPV_C_ShaderViewportMaskNV]>
+    Capability<[SPIRV_C_ShaderViewportMaskNV]>
   ];
 }
-def SPV_D_SecondaryViewportRelativeNV        : I32EnumAttrCase<"SecondaryViewportRelativeNV", 5256> {
+def SPIRV_D_SecondaryViewportRelativeNV        : I32EnumAttrCase<"SecondaryViewportRelativeNV", 5256> {
   list<Availability> availability = [
-    Extension<[SPV_NV_stereo_view_rendering]>,
-    Capability<[SPV_C_ShaderStereoViewNV]>
+    Extension<[SPIRV_NV_stereo_view_rendering]>,
+    Capability<[SPIRV_C_ShaderStereoViewNV]>
   ];
 }
-def SPV_D_PerPrimitiveNV                     : I32EnumAttrCase<"PerPrimitiveNV", 5271> {
+def SPIRV_D_PerPrimitiveNV                     : I32EnumAttrCase<"PerPrimitiveNV", 5271> {
   list<Availability> availability = [
-    Extension<[SPV_NV_mesh_shader]>,
-    Capability<[SPV_C_MeshShadingNV]>
+    Extension<[SPIRV_NV_mesh_shader]>,
+    Capability<[SPIRV_C_MeshShadingNV]>
   ];
 }
-def SPV_D_PerViewNV                          : I32EnumAttrCase<"PerViewNV", 5272> {
+def SPIRV_D_PerViewNV                          : I32EnumAttrCase<"PerViewNV", 5272> {
   list<Availability> availability = [
-    Extension<[SPV_NV_mesh_shader]>,
-    Capability<[SPV_C_MeshShadingNV]>
+    Extension<[SPIRV_NV_mesh_shader]>,
+    Capability<[SPIRV_C_MeshShadingNV]>
   ];
 }
-def SPV_D_PerTaskNV                          : I32EnumAttrCase<"PerTaskNV", 5273> {
+def SPIRV_D_PerTaskNV                          : I32EnumAttrCase<"PerTaskNV", 5273> {
   list<Availability> availability = [
-    Extension<[SPV_NV_mesh_shader]>,
-    Capability<[SPV_C_MeshShadingNV]>
+    Extension<[SPIRV_NV_mesh_shader]>,
+    Capability<[SPIRV_C_MeshShadingNV]>
   ];
 }
-def SPV_D_PerVertexKHR                       : I32EnumAttrCase<"PerVertexKHR", 5285> {
+def SPIRV_D_PerVertexKHR                       : I32EnumAttrCase<"PerVertexKHR", 5285> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_fragment_shader_barycentric, SPV_NV_fragment_shader_barycentric]>,
-    Capability<[SPV_C_FragmentBarycentricKHR]>
+    Extension<[SPIRV_KHR_fragment_shader_barycentric, SPIRV_NV_fragment_shader_barycentric]>,
+    Capability<[SPIRV_C_FragmentBarycentricKHR]>
   ];
 }
-def SPV_D_NonUniform                         : I32EnumAttrCase<"NonUniform", 5300> {
+def SPIRV_D_NonUniform                         : I32EnumAttrCase<"NonUniform", 5300> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
-    Capability<[SPV_C_ShaderNonUniform]>
+    MinVersion<SPIRV_V_1_5>,
+    Capability<[SPIRV_C_ShaderNonUniform]>
   ];
 }
-def SPV_D_RestrictPointer                    : I32EnumAttrCase<"RestrictPointer", 5355> {
+def SPIRV_D_RestrictPointer                    : I32EnumAttrCase<"RestrictPointer", 5355> {
   list<Availability> availability = [
-    Extension<[SPV_EXT_physical_storage_buffer, SPV_KHR_physical_storage_buffer]>,
-    Capability<[SPV_C_PhysicalStorageBufferAddresses]>
+    Extension<[SPIRV_EXT_physical_storage_buffer, SPIRV_KHR_physical_storage_buffer]>,
+    Capability<[SPIRV_C_PhysicalStorageBufferAddresses]>
   ];
 }
-def SPV_D_AliasedPointer                     : I32EnumAttrCase<"AliasedPointer", 5356> {
+def SPIRV_D_AliasedPointer                     : I32EnumAttrCase<"AliasedPointer", 5356> {
   list<Availability> availability = [
-    Extension<[SPV_EXT_physical_storage_buffer, SPV_KHR_physical_storage_buffer]>,
-    Capability<[SPV_C_PhysicalStorageBufferAddresses]>
+    Extension<[SPIRV_EXT_physical_storage_buffer, SPIRV_KHR_physical_storage_buffer]>,
+    Capability<[SPIRV_C_PhysicalStorageBufferAddresses]>
   ];
 }
-def SPV_D_BindlessSamplerNV                  : I32EnumAttrCase<"BindlessSamplerNV", 5398> {
+def SPIRV_D_BindlessSamplerNV                  : I32EnumAttrCase<"BindlessSamplerNV", 5398> {
   list<Availability> availability = [
-    Capability<[SPV_C_BindlessTextureNV]>
+    Capability<[SPIRV_C_BindlessTextureNV]>
   ];
 }
-def SPV_D_BindlessImageNV                    : I32EnumAttrCase<"BindlessImageNV", 5399> {
+def SPIRV_D_BindlessImageNV                    : I32EnumAttrCase<"BindlessImageNV", 5399> {
   list<Availability> availability = [
-    Capability<[SPV_C_BindlessTextureNV]>
+    Capability<[SPIRV_C_BindlessTextureNV]>
   ];
 }
-def SPV_D_BoundSamplerNV                     : I32EnumAttrCase<"BoundSamplerNV", 5400> {
+def SPIRV_D_BoundSamplerNV                     : I32EnumAttrCase<"BoundSamplerNV", 5400> {
   list<Availability> availability = [
-    Capability<[SPV_C_BindlessTextureNV]>
+    Capability<[SPIRV_C_BindlessTextureNV]>
   ];
 }
-def SPV_D_BoundImageNV                       : I32EnumAttrCase<"BoundImageNV", 5401> {
+def SPIRV_D_BoundImageNV                       : I32EnumAttrCase<"BoundImageNV", 5401> {
   list<Availability> availability = [
-    Capability<[SPV_C_BindlessTextureNV]>
+    Capability<[SPIRV_C_BindlessTextureNV]>
   ];
 }
-def SPV_D_SIMTCallINTEL                      : I32EnumAttrCase<"SIMTCallINTEL", 5599> {
+def SPIRV_D_SIMTCallINTEL                      : I32EnumAttrCase<"SIMTCallINTEL", 5599> {
   list<Availability> availability = [
-    Capability<[SPV_C_VectorComputeINTEL]>
+    Capability<[SPIRV_C_VectorComputeINTEL]>
   ];
 }
-def SPV_D_ReferencedIndirectlyINTEL          : I32EnumAttrCase<"ReferencedIndirectlyINTEL", 5602> {
+def SPIRV_D_ReferencedIndirectlyINTEL          : I32EnumAttrCase<"ReferencedIndirectlyINTEL", 5602> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_function_pointers]>,
-    Capability<[SPV_C_IndirectReferencesINTEL]>
+    Extension<[SPIRV_INTEL_function_pointers]>,
+    Capability<[SPIRV_C_IndirectReferencesINTEL]>
   ];
 }
-def SPV_D_ClobberINTEL                       : I32EnumAttrCase<"ClobberINTEL", 5607> {
+def SPIRV_D_ClobberINTEL                       : I32EnumAttrCase<"ClobberINTEL", 5607> {
   list<Availability> availability = [
-    Capability<[SPV_C_AsmINTEL]>
+    Capability<[SPIRV_C_AsmINTEL]>
   ];
 }
-def SPV_D_SideEffectsINTEL                   : I32EnumAttrCase<"SideEffectsINTEL", 5608> {
+def SPIRV_D_SideEffectsINTEL                   : I32EnumAttrCase<"SideEffectsINTEL", 5608> {
   list<Availability> availability = [
-    Capability<[SPV_C_AsmINTEL]>
+    Capability<[SPIRV_C_AsmINTEL]>
   ];
 }
-def SPV_D_VectorComputeVariableINTEL         : I32EnumAttrCase<"VectorComputeVariableINTEL", 5624> {
+def SPIRV_D_VectorComputeVariableINTEL         : I32EnumAttrCase<"VectorComputeVariableINTEL", 5624> {
   list<Availability> availability = [
-    Capability<[SPV_C_VectorComputeINTEL]>
+    Capability<[SPIRV_C_VectorComputeINTEL]>
   ];
 }
-def SPV_D_FuncParamIOKindINTEL               : I32EnumAttrCase<"FuncParamIOKindINTEL", 5625> {
+def SPIRV_D_FuncParamIOKindINTEL               : I32EnumAttrCase<"FuncParamIOKindINTEL", 5625> {
   list<Availability> availability = [
-    Capability<[SPV_C_VectorComputeINTEL]>
+    Capability<[SPIRV_C_VectorComputeINTEL]>
   ];
 }
-def SPV_D_VectorComputeFunctionINTEL         : I32EnumAttrCase<"VectorComputeFunctionINTEL", 5626> {
+def SPIRV_D_VectorComputeFunctionINTEL         : I32EnumAttrCase<"VectorComputeFunctionINTEL", 5626> {
   list<Availability> availability = [
-    Capability<[SPV_C_VectorComputeINTEL]>
+    Capability<[SPIRV_C_VectorComputeINTEL]>
   ];
 }
-def SPV_D_StackCallINTEL                     : I32EnumAttrCase<"StackCallINTEL", 5627> {
+def SPIRV_D_StackCallINTEL                     : I32EnumAttrCase<"StackCallINTEL", 5627> {
   list<Availability> availability = [
-    Capability<[SPV_C_VectorComputeINTEL]>
+    Capability<[SPIRV_C_VectorComputeINTEL]>
   ];
 }
-def SPV_D_GlobalVariableOffsetINTEL          : I32EnumAttrCase<"GlobalVariableOffsetINTEL", 5628> {
+def SPIRV_D_GlobalVariableOffsetINTEL          : I32EnumAttrCase<"GlobalVariableOffsetINTEL", 5628> {
   list<Availability> availability = [
-    Capability<[SPV_C_VectorComputeINTEL]>
+    Capability<[SPIRV_C_VectorComputeINTEL]>
   ];
 }
-def SPV_D_CounterBuffer                      : I32EnumAttrCase<"CounterBuffer", 5634> {
+def SPIRV_D_CounterBuffer                      : I32EnumAttrCase<"CounterBuffer", 5634> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>
+    MinVersion<SPIRV_V_1_4>
   ];
 }
-def SPV_D_UserSemantic                       : I32EnumAttrCase<"UserSemantic", 5635> {
+def SPIRV_D_UserSemantic                       : I32EnumAttrCase<"UserSemantic", 5635> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>
+    MinVersion<SPIRV_V_1_4>
   ];
 }
-def SPV_D_UserTypeGOOGLE                     : I32EnumAttrCase<"UserTypeGOOGLE", 5636> {
+def SPIRV_D_UserTypeGOOGLE                     : I32EnumAttrCase<"UserTypeGOOGLE", 5636> {
   list<Availability> availability = [
-    Extension<[SPV_GOOGLE_user_type]>
+    Extension<[SPIRV_GOOGLE_user_type]>
   ];
 }
-def SPV_D_FunctionRoundingModeINTEL          : I32EnumAttrCase<"FunctionRoundingModeINTEL", 5822> {
+def SPIRV_D_FunctionRoundingModeINTEL          : I32EnumAttrCase<"FunctionRoundingModeINTEL", 5822> {
   list<Availability> availability = [
-    Capability<[SPV_C_FunctionFloatControlINTEL]>
+    Capability<[SPIRV_C_FunctionFloatControlINTEL]>
   ];
 }
-def SPV_D_FunctionDenormModeINTEL            : I32EnumAttrCase<"FunctionDenormModeINTEL", 5823> {
+def SPIRV_D_FunctionDenormModeINTEL            : I32EnumAttrCase<"FunctionDenormModeINTEL", 5823> {
   list<Availability> availability = [
-    Capability<[SPV_C_FunctionFloatControlINTEL]>
+    Capability<[SPIRV_C_FunctionFloatControlINTEL]>
   ];
 }
-def SPV_D_RegisterINTEL                      : I32EnumAttrCase<"RegisterINTEL", 5825> {
+def SPIRV_D_RegisterINTEL                      : I32EnumAttrCase<"RegisterINTEL", 5825> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_memory_attributes]>,
-    Capability<[SPV_C_FPGAMemoryAttributesINTEL]>
+    Extension<[SPIRV_INTEL_fpga_memory_attributes]>,
+    Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]>
   ];
 }
-def SPV_D_MemoryINTEL                        : I32EnumAttrCase<"MemoryINTEL", 5826> {
+def SPIRV_D_MemoryINTEL                        : I32EnumAttrCase<"MemoryINTEL", 5826> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_memory_attributes]>,
-    Capability<[SPV_C_FPGAMemoryAttributesINTEL]>
+    Extension<[SPIRV_INTEL_fpga_memory_attributes]>,
+    Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]>
   ];
 }
-def SPV_D_NumbanksINTEL                      : I32EnumAttrCase<"NumbanksINTEL", 5827> {
+def SPIRV_D_NumbanksINTEL                      : I32EnumAttrCase<"NumbanksINTEL", 5827> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_memory_attributes]>,
-    Capability<[SPV_C_FPGAMemoryAttributesINTEL]>
+    Extension<[SPIRV_INTEL_fpga_memory_attributes]>,
+    Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]>
   ];
 }
-def SPV_D_BankwidthINTEL                     : I32EnumAttrCase<"BankwidthINTEL", 5828> {
+def SPIRV_D_BankwidthINTEL                     : I32EnumAttrCase<"BankwidthINTEL", 5828> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_memory_attributes]>,
-    Capability<[SPV_C_FPGAMemoryAttributesINTEL]>
+    Extension<[SPIRV_INTEL_fpga_memory_attributes]>,
+    Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]>
   ];
 }
-def SPV_D_MaxPrivateCopiesINTEL              : I32EnumAttrCase<"MaxPrivateCopiesINTEL", 5829> {
+def SPIRV_D_MaxPrivateCopiesINTEL              : I32EnumAttrCase<"MaxPrivateCopiesINTEL", 5829> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_memory_attributes]>,
-    Capability<[SPV_C_FPGAMemoryAttributesINTEL]>
+    Extension<[SPIRV_INTEL_fpga_memory_attributes]>,
+    Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]>
   ];
 }
-def SPV_D_SinglepumpINTEL                    : I32EnumAttrCase<"SinglepumpINTEL", 5830> {
+def SPIRV_D_SinglepumpINTEL                    : I32EnumAttrCase<"SinglepumpINTEL", 5830> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_memory_attributes]>,
-    Capability<[SPV_C_FPGAMemoryAttributesINTEL]>
+    Extension<[SPIRV_INTEL_fpga_memory_attributes]>,
+    Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]>
   ];
 }
-def SPV_D_DoublepumpINTEL                    : I32EnumAttrCase<"DoublepumpINTEL", 5831> {
+def SPIRV_D_DoublepumpINTEL                    : I32EnumAttrCase<"DoublepumpINTEL", 5831> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_memory_attributes]>,
-    Capability<[SPV_C_FPGAMemoryAttributesINTEL]>
+    Extension<[SPIRV_INTEL_fpga_memory_attributes]>,
+    Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]>
   ];
 }
-def SPV_D_MaxReplicatesINTEL                 : I32EnumAttrCase<"MaxReplicatesINTEL", 5832> {
+def SPIRV_D_MaxReplicatesINTEL                 : I32EnumAttrCase<"MaxReplicatesINTEL", 5832> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_memory_attributes]>,
-    Capability<[SPV_C_FPGAMemoryAttributesINTEL]>
+    Extension<[SPIRV_INTEL_fpga_memory_attributes]>,
+    Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]>
   ];
 }
-def SPV_D_SimpleDualPortINTEL                : I32EnumAttrCase<"SimpleDualPortINTEL", 5833> {
+def SPIRV_D_SimpleDualPortINTEL                : I32EnumAttrCase<"SimpleDualPortINTEL", 5833> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_memory_attributes]>,
-    Capability<[SPV_C_FPGAMemoryAttributesINTEL]>
+    Extension<[SPIRV_INTEL_fpga_memory_attributes]>,
+    Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]>
   ];
 }
-def SPV_D_MergeINTEL                         : I32EnumAttrCase<"MergeINTEL", 5834> {
+def SPIRV_D_MergeINTEL                         : I32EnumAttrCase<"MergeINTEL", 5834> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_memory_attributes]>,
-    Capability<[SPV_C_FPGAMemoryAttributesINTEL]>
+    Extension<[SPIRV_INTEL_fpga_memory_attributes]>,
+    Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]>
   ];
 }
-def SPV_D_BankBitsINTEL                      : I32EnumAttrCase<"BankBitsINTEL", 5835> {
+def SPIRV_D_BankBitsINTEL                      : I32EnumAttrCase<"BankBitsINTEL", 5835> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_memory_attributes]>,
-    Capability<[SPV_C_FPGAMemoryAttributesINTEL]>
+    Extension<[SPIRV_INTEL_fpga_memory_attributes]>,
+    Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]>
   ];
 }
-def SPV_D_ForcePow2DepthINTEL                : I32EnumAttrCase<"ForcePow2DepthINTEL", 5836> {
+def SPIRV_D_ForcePow2DepthINTEL                : I32EnumAttrCase<"ForcePow2DepthINTEL", 5836> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_memory_attributes]>,
-    Capability<[SPV_C_FPGAMemoryAttributesINTEL]>
+    Extension<[SPIRV_INTEL_fpga_memory_attributes]>,
+    Capability<[SPIRV_C_FPGAMemoryAttributesINTEL]>
   ];
 }
-def SPV_D_BurstCoalesceINTEL                 : I32EnumAttrCase<"BurstCoalesceINTEL", 5899> {
+def SPIRV_D_BurstCoalesceINTEL                 : I32EnumAttrCase<"BurstCoalesceINTEL", 5899> {
   list<Availability> availability = [
-    Capability<[SPV_C_FPGAMemoryAccessesINTEL]>
+    Capability<[SPIRV_C_FPGAMemoryAccessesINTEL]>
   ];
 }
-def SPV_D_CacheSizeINTEL                     : I32EnumAttrCase<"CacheSizeINTEL", 5900> {
+def SPIRV_D_CacheSizeINTEL                     : I32EnumAttrCase<"CacheSizeINTEL", 5900> {
   list<Availability> availability = [
-    Capability<[SPV_C_FPGAMemoryAccessesINTEL]>
+    Capability<[SPIRV_C_FPGAMemoryAccessesINTEL]>
   ];
 }
-def SPV_D_DontStaticallyCoalesceINTEL        : I32EnumAttrCase<"DontStaticallyCoalesceINTEL", 5901> {
+def SPIRV_D_DontStaticallyCoalesceINTEL        : I32EnumAttrCase<"DontStaticallyCoalesceINTEL", 5901> {
   list<Availability> availability = [
-    Capability<[SPV_C_FPGAMemoryAccessesINTEL]>
+    Capability<[SPIRV_C_FPGAMemoryAccessesINTEL]>
   ];
 }
-def SPV_D_PrefetchINTEL                      : I32EnumAttrCase<"PrefetchINTEL", 5902> {
+def SPIRV_D_PrefetchINTEL                      : I32EnumAttrCase<"PrefetchINTEL", 5902> {
   list<Availability> availability = [
-    Capability<[SPV_C_FPGAMemoryAccessesINTEL]>
+    Capability<[SPIRV_C_FPGAMemoryAccessesINTEL]>
   ];
 }
-def SPV_D_StallEnableINTEL                   : I32EnumAttrCase<"StallEnableINTEL", 5905> {
+def SPIRV_D_StallEnableINTEL                   : I32EnumAttrCase<"StallEnableINTEL", 5905> {
   list<Availability> availability = [
-    Capability<[SPV_C_FPGAClusterAttributesINTEL]>
+    Capability<[SPIRV_C_FPGAClusterAttributesINTEL]>
   ];
 }
-def SPV_D_FuseLoopsInFunctionINTEL           : I32EnumAttrCase<"FuseLoopsInFunctionINTEL", 5907> {
+def SPIRV_D_FuseLoopsInFunctionINTEL           : I32EnumAttrCase<"FuseLoopsInFunctionINTEL", 5907> {
   list<Availability> availability = [
-    Capability<[SPV_C_LoopFuseINTEL]>
+    Capability<[SPIRV_C_LoopFuseINTEL]>
   ];
 }
-def SPV_D_AliasScopeINTEL                    : I32EnumAttrCase<"AliasScopeINTEL", 5914> {
+def SPIRV_D_AliasScopeINTEL                    : I32EnumAttrCase<"AliasScopeINTEL", 5914> {
   list<Availability> availability = [
-    Capability<[SPV_C_MemoryAccessAliasingINTEL]>
+    Capability<[SPIRV_C_MemoryAccessAliasingINTEL]>
   ];
 }
-def SPV_D_NoAliasINTEL                       : I32EnumAttrCase<"NoAliasINTEL", 5915> {
+def SPIRV_D_NoAliasINTEL                       : I32EnumAttrCase<"NoAliasINTEL", 5915> {
   list<Availability> availability = [
-    Capability<[SPV_C_MemoryAccessAliasingINTEL]>
+    Capability<[SPIRV_C_MemoryAccessAliasingINTEL]>
   ];
 }
-def SPV_D_BufferLocationINTEL                : I32EnumAttrCase<"BufferLocationINTEL", 5921> {
+def SPIRV_D_BufferLocationINTEL                : I32EnumAttrCase<"BufferLocationINTEL", 5921> {
   list<Availability> availability = [
-    Capability<[SPV_C_FPGABufferLocationINTEL]>
+    Capability<[SPIRV_C_FPGABufferLocationINTEL]>
   ];
 }
-def SPV_D_IOPipeStorageINTEL                 : I32EnumAttrCase<"IOPipeStorageINTEL", 5944> {
+def SPIRV_D_IOPipeStorageINTEL                 : I32EnumAttrCase<"IOPipeStorageINTEL", 5944> {
   list<Availability> availability = [
-    Capability<[SPV_C_IOPipesINTEL]>
+    Capability<[SPIRV_C_IOPipesINTEL]>
   ];
 }
-def SPV_D_FunctionFloatingPointModeINTEL     : I32EnumAttrCase<"FunctionFloatingPointModeINTEL", 6080> {
+def SPIRV_D_FunctionFloatingPointModeINTEL     : I32EnumAttrCase<"FunctionFloatingPointModeINTEL", 6080> {
   list<Availability> availability = [
-    Capability<[SPV_C_FunctionFloatControlINTEL]>
+    Capability<[SPIRV_C_FunctionFloatControlINTEL]>
   ];
 }
-def SPV_D_SingleElementVectorINTEL           : I32EnumAttrCase<"SingleElementVectorINTEL", 6085> {
+def SPIRV_D_SingleElementVectorINTEL           : I32EnumAttrCase<"SingleElementVectorINTEL", 6085> {
   list<Availability> availability = [
-    Capability<[SPV_C_VectorComputeINTEL]>
+    Capability<[SPIRV_C_VectorComputeINTEL]>
   ];
 }
-def SPV_D_VectorComputeCallableFunctionINTEL : I32EnumAttrCase<"VectorComputeCallableFunctionINTEL", 6087> {
+def SPIRV_D_VectorComputeCallableFunctionINTEL : I32EnumAttrCase<"VectorComputeCallableFunctionINTEL", 6087> {
   list<Availability> availability = [
-    Capability<[SPV_C_VectorComputeINTEL]>
+    Capability<[SPIRV_C_VectorComputeINTEL]>
   ];
 }
-def SPV_D_MediaBlockIOINTEL                  : I32EnumAttrCase<"MediaBlockIOINTEL", 6140> {
+def SPIRV_D_MediaBlockIOINTEL                  : I32EnumAttrCase<"MediaBlockIOINTEL", 6140> {
   list<Availability> availability = [
-    Capability<[SPV_C_VectorComputeINTEL]>
+    Capability<[SPIRV_C_VectorComputeINTEL]>
   ];
 }
 
-def SPV_DecorationAttr :
-    SPV_I32EnumAttr<"Decoration", "valid SPIR-V Decoration", "decoration", [
-      SPV_D_RelaxedPrecision, SPV_D_SpecId, SPV_D_Block, SPV_D_BufferBlock,
-      SPV_D_RowMajor, SPV_D_ColMajor, SPV_D_ArrayStride, SPV_D_MatrixStride,
-      SPV_D_GLSLShared, SPV_D_GLSLPacked, SPV_D_CPacked, SPV_D_BuiltIn,
-      SPV_D_NoPerspective, SPV_D_Flat, SPV_D_Patch, SPV_D_Centroid, SPV_D_Sample,
-      SPV_D_Invariant, SPV_D_Restrict, SPV_D_Aliased, SPV_D_Volatile, SPV_D_Constant,
-      SPV_D_Coherent, SPV_D_NonWritable, SPV_D_NonReadable, SPV_D_Uniform,
-      SPV_D_UniformId, SPV_D_SaturatedConversion, SPV_D_Stream, SPV_D_Location,
-      SPV_D_Component, SPV_D_Index, SPV_D_Binding, SPV_D_DescriptorSet, SPV_D_Offset,
-      SPV_D_XfbBuffer, SPV_D_XfbStride, SPV_D_FuncParamAttr, SPV_D_FPRoundingMode,
-      SPV_D_FPFastMathMode, SPV_D_LinkageAttributes, SPV_D_NoContraction,
-      SPV_D_InputAttachmentIndex, SPV_D_Alignment, SPV_D_MaxByteOffset,
-      SPV_D_AlignmentId, SPV_D_MaxByteOffsetId, SPV_D_NoSignedWrap,
-      SPV_D_NoUnsignedWrap, SPV_D_ExplicitInterpAMD, SPV_D_OverrideCoverageNV,
-      SPV_D_PassthroughNV, SPV_D_ViewportRelativeNV,
-      SPV_D_SecondaryViewportRelativeNV, SPV_D_PerPrimitiveNV, SPV_D_PerViewNV,
-      SPV_D_PerTaskNV, SPV_D_PerVertexKHR, SPV_D_NonUniform, SPV_D_RestrictPointer,
-      SPV_D_AliasedPointer, SPV_D_BindlessSamplerNV, SPV_D_BindlessImageNV,
-      SPV_D_BoundSamplerNV, SPV_D_BoundImageNV, SPV_D_SIMTCallINTEL,
-      SPV_D_ReferencedIndirectlyINTEL, SPV_D_ClobberINTEL, SPV_D_SideEffectsINTEL,
-      SPV_D_VectorComputeVariableINTEL, SPV_D_FuncParamIOKindINTEL,
-      SPV_D_VectorComputeFunctionINTEL, SPV_D_StackCallINTEL,
-      SPV_D_GlobalVariableOffsetINTEL, SPV_D_CounterBuffer, SPV_D_UserSemantic,
-      SPV_D_UserTypeGOOGLE, SPV_D_FunctionRoundingModeINTEL,
-      SPV_D_FunctionDenormModeINTEL, SPV_D_RegisterINTEL, SPV_D_MemoryINTEL,
-      SPV_D_NumbanksINTEL, SPV_D_BankwidthINTEL, SPV_D_MaxPrivateCopiesINTEL,
-      SPV_D_SinglepumpINTEL, SPV_D_DoublepumpINTEL, SPV_D_MaxReplicatesINTEL,
-      SPV_D_SimpleDualPortINTEL, SPV_D_MergeINTEL, SPV_D_BankBitsINTEL,
-      SPV_D_ForcePow2DepthINTEL, SPV_D_BurstCoalesceINTEL, SPV_D_CacheSizeINTEL,
-      SPV_D_DontStaticallyCoalesceINTEL, SPV_D_PrefetchINTEL, SPV_D_StallEnableINTEL,
-      SPV_D_FuseLoopsInFunctionINTEL, SPV_D_AliasScopeINTEL, SPV_D_NoAliasINTEL,
-      SPV_D_BufferLocationINTEL, SPV_D_IOPipeStorageINTEL,
-      SPV_D_FunctionFloatingPointModeINTEL, SPV_D_SingleElementVectorINTEL,
-      SPV_D_VectorComputeCallableFunctionINTEL, SPV_D_MediaBlockIOINTEL
+def SPIRV_DecorationAttr :
+    SPIRV_I32EnumAttr<"Decoration", "valid SPIR-V Decoration", "decoration", [
+      SPIRV_D_RelaxedPrecision, SPIRV_D_SpecId, SPIRV_D_Block, SPIRV_D_BufferBlock,
+      SPIRV_D_RowMajor, SPIRV_D_ColMajor, SPIRV_D_ArrayStride, SPIRV_D_MatrixStride,
+      SPIRV_D_GLSLShared, SPIRV_D_GLSLPacked, SPIRV_D_CPacked, SPIRV_D_BuiltIn,
+      SPIRV_D_NoPerspective, SPIRV_D_Flat, SPIRV_D_Patch, SPIRV_D_Centroid, SPIRV_D_Sample,
+      SPIRV_D_Invariant, SPIRV_D_Restrict, SPIRV_D_Aliased, SPIRV_D_Volatile, SPIRV_D_Constant,
+      SPIRV_D_Coherent, SPIRV_D_NonWritable, SPIRV_D_NonReadable, SPIRV_D_Uniform,
+      SPIRV_D_UniformId, SPIRV_D_SaturatedConversion, SPIRV_D_Stream, SPIRV_D_Location,
+      SPIRV_D_Component, SPIRV_D_Index, SPIRV_D_Binding, SPIRV_D_DescriptorSet, SPIRV_D_Offset,
+      SPIRV_D_XfbBuffer, SPIRV_D_XfbStride, SPIRV_D_FuncParamAttr, SPIRV_D_FPRoundingMode,
+      SPIRV_D_FPFastMathMode, SPIRV_D_LinkageAttributes, SPIRV_D_NoContraction,
+      SPIRV_D_InputAttachmentIndex, SPIRV_D_Alignment, SPIRV_D_MaxByteOffset,
+      SPIRV_D_AlignmentId, SPIRV_D_MaxByteOffsetId, SPIRV_D_NoSignedWrap,
+      SPIRV_D_NoUnsignedWrap, SPIRV_D_ExplicitInterpAMD, SPIRV_D_OverrideCoverageNV,
+      SPIRV_D_PassthroughNV, SPIRV_D_ViewportRelativeNV,
+      SPIRV_D_SecondaryViewportRelativeNV, SPIRV_D_PerPrimitiveNV, SPIRV_D_PerViewNV,
+      SPIRV_D_PerTaskNV, SPIRV_D_PerVertexKHR, SPIRV_D_NonUniform, SPIRV_D_RestrictPointer,
+      SPIRV_D_AliasedPointer, SPIRV_D_BindlessSamplerNV, SPIRV_D_BindlessImageNV,
+      SPIRV_D_BoundSamplerNV, SPIRV_D_BoundImageNV, SPIRV_D_SIMTCallINTEL,
+      SPIRV_D_ReferencedIndirectlyINTEL, SPIRV_D_ClobberINTEL, SPIRV_D_SideEffectsINTEL,
+      SPIRV_D_VectorComputeVariableINTEL, SPIRV_D_FuncParamIOKindINTEL,
+      SPIRV_D_VectorComputeFunctionINTEL, SPIRV_D_StackCallINTEL,
+      SPIRV_D_GlobalVariableOffsetINTEL, SPIRV_D_CounterBuffer, SPIRV_D_UserSemantic,
+      SPIRV_D_UserTypeGOOGLE, SPIRV_D_FunctionRoundingModeINTEL,
+      SPIRV_D_FunctionDenormModeINTEL, SPIRV_D_RegisterINTEL, SPIRV_D_MemoryINTEL,
+      SPIRV_D_NumbanksINTEL, SPIRV_D_BankwidthINTEL, SPIRV_D_MaxPrivateCopiesINTEL,
+      SPIRV_D_SinglepumpINTEL, SPIRV_D_DoublepumpINTEL, SPIRV_D_MaxReplicatesINTEL,
+      SPIRV_D_SimpleDualPortINTEL, SPIRV_D_MergeINTEL, SPIRV_D_BankBitsINTEL,
+      SPIRV_D_ForcePow2DepthINTEL, SPIRV_D_BurstCoalesceINTEL, SPIRV_D_CacheSizeINTEL,
+      SPIRV_D_DontStaticallyCoalesceINTEL, SPIRV_D_PrefetchINTEL, SPIRV_D_StallEnableINTEL,
+      SPIRV_D_FuseLoopsInFunctionINTEL, SPIRV_D_AliasScopeINTEL, SPIRV_D_NoAliasINTEL,
+      SPIRV_D_BufferLocationINTEL, SPIRV_D_IOPipeStorageINTEL,
+      SPIRV_D_FunctionFloatingPointModeINTEL, SPIRV_D_SingleElementVectorINTEL,
+      SPIRV_D_VectorComputeCallableFunctionINTEL, SPIRV_D_MediaBlockIOINTEL
     ]>;
 
-def SPV_D_1D          : I32EnumAttrCase<"Dim1D", 0> {
+def SPIRV_D_1D          : I32EnumAttrCase<"Dim1D", 0> {
   list<Availability> availability = [
-    Capability<[SPV_C_Image1D, SPV_C_Sampled1D]>
+    Capability<[SPIRV_C_Image1D, SPIRV_C_Sampled1D]>
   ];
 }
-def SPV_D_2D          : I32EnumAttrCase<"Dim2D", 1> {
+def SPIRV_D_2D          : I32EnumAttrCase<"Dim2D", 1> {
   list<Availability> availability = [
-    Capability<[SPV_C_ImageMSArray, SPV_C_Kernel, SPV_C_Shader]>
+    Capability<[SPIRV_C_ImageMSArray, SPIRV_C_Kernel, SPIRV_C_Shader]>
   ];
 }
-def SPV_D_3D          : I32EnumAttrCase<"Dim3D", 2>;
-def SPV_D_Cube        : I32EnumAttrCase<"Cube", 3> {
+def SPIRV_D_3D          : I32EnumAttrCase<"Dim3D", 2>;
+def SPIRV_D_Cube        : I32EnumAttrCase<"Cube", 3> {
   list<Availability> availability = [
-    Capability<[SPV_C_ImageCubeArray, SPV_C_Shader]>
+    Capability<[SPIRV_C_ImageCubeArray, SPIRV_C_Shader]>
   ];
 }
-def SPV_D_Rect        : I32EnumAttrCase<"Rect", 4> {
+def SPIRV_D_Rect        : I32EnumAttrCase<"Rect", 4> {
   list<Availability> availability = [
-    Capability<[SPV_C_ImageRect, SPV_C_SampledRect]>
+    Capability<[SPIRV_C_ImageRect, SPIRV_C_SampledRect]>
   ];
 }
-def SPV_D_Buffer      : I32EnumAttrCase<"Buffer", 5> {
+def SPIRV_D_Buffer      : I32EnumAttrCase<"Buffer", 5> {
   list<Availability> availability = [
-    Capability<[SPV_C_ImageBuffer, SPV_C_SampledBuffer]>
+    Capability<[SPIRV_C_ImageBuffer, SPIRV_C_SampledBuffer]>
   ];
 }
-def SPV_D_SubpassData : I32EnumAttrCase<"SubpassData", 6> {
+def SPIRV_D_SubpassData : I32EnumAttrCase<"SubpassData", 6> {
   list<Availability> availability = [
-    Capability<[SPV_C_InputAttachment]>
+    Capability<[SPIRV_C_InputAttachment]>
   ];
 }
 
-def SPV_DimAttr :
-    SPV_I32EnumAttr<"Dim", "valid SPIR-V Dim", "dim", [
-      SPV_D_1D, SPV_D_2D, SPV_D_3D, SPV_D_Cube, SPV_D_Rect, SPV_D_Buffer,
-      SPV_D_SubpassData
+def SPIRV_DimAttr :
+    SPIRV_I32EnumAttr<"Dim", "valid SPIR-V Dim", "dim", [
+      SPIRV_D_1D, SPIRV_D_2D, SPIRV_D_3D, SPIRV_D_Cube, SPIRV_D_Rect, SPIRV_D_Buffer,
+      SPIRV_D_SubpassData
     ]>;
 
-def SPV_EM_Invocations                      : I32EnumAttrCase<"Invocations", 0> {
+def SPIRV_EM_Invocations                      : I32EnumAttrCase<"Invocations", 0> {
   list<Availability> availability = [
-    Capability<[SPV_C_Geometry]>
+    Capability<[SPIRV_C_Geometry]>
   ];
 }
-def SPV_EM_SpacingEqual                     : I32EnumAttrCase<"SpacingEqual", 1> {
+def SPIRV_EM_SpacingEqual                     : I32EnumAttrCase<"SpacingEqual", 1> {
   list<Availability> availability = [
-    Capability<[SPV_C_Tessellation]>
+    Capability<[SPIRV_C_Tessellation]>
   ];
 }
-def SPV_EM_SpacingFractionalEven            : I32EnumAttrCase<"SpacingFractionalEven", 2> {
+def SPIRV_EM_SpacingFractionalEven            : I32EnumAttrCase<"SpacingFractionalEven", 2> {
   list<Availability> availability = [
-    Capability<[SPV_C_Tessellation]>
+    Capability<[SPIRV_C_Tessellation]>
   ];
 }
-def SPV_EM_SpacingFractionalOdd             : I32EnumAttrCase<"SpacingFractionalOdd", 3> {
+def SPIRV_EM_SpacingFractionalOdd             : I32EnumAttrCase<"SpacingFractionalOdd", 3> {
   list<Availability> availability = [
-    Capability<[SPV_C_Tessellation]>
+    Capability<[SPIRV_C_Tessellation]>
   ];
 }
-def SPV_EM_VertexOrderCw                    : I32EnumAttrCase<"VertexOrderCw", 4> {
+def SPIRV_EM_VertexOrderCw                    : I32EnumAttrCase<"VertexOrderCw", 4> {
   list<Availability> availability = [
-    Capability<[SPV_C_Tessellation]>
+    Capability<[SPIRV_C_Tessellation]>
   ];
 }
-def SPV_EM_VertexOrderCcw                   : I32EnumAttrCase<"VertexOrderCcw", 5> {
+def SPIRV_EM_VertexOrderCcw                   : I32EnumAttrCase<"VertexOrderCcw", 5> {
   list<Availability> availability = [
-    Capability<[SPV_C_Tessellation]>
+    Capability<[SPIRV_C_Tessellation]>
   ];
 }
-def SPV_EM_PixelCenterInteger               : I32EnumAttrCase<"PixelCenterInteger", 6> {
+def SPIRV_EM_PixelCenterInteger               : I32EnumAttrCase<"PixelCenterInteger", 6> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_EM_OriginUpperLeft                  : I32EnumAttrCase<"OriginUpperLeft", 7> {
+def SPIRV_EM_OriginUpperLeft                  : I32EnumAttrCase<"OriginUpperLeft", 7> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_EM_OriginLowerLeft                  : I32EnumAttrCase<"OriginLowerLeft", 8> {
+def SPIRV_EM_OriginLowerLeft                  : I32EnumAttrCase<"OriginLowerLeft", 8> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_EM_EarlyFragmentTests               : I32EnumAttrCase<"EarlyFragmentTests", 9> {
+def SPIRV_EM_EarlyFragmentTests               : I32EnumAttrCase<"EarlyFragmentTests", 9> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_EM_PointMode                        : I32EnumAttrCase<"PointMode", 10> {
+def SPIRV_EM_PointMode                        : I32EnumAttrCase<"PointMode", 10> {
   list<Availability> availability = [
-    Capability<[SPV_C_Tessellation]>
+    Capability<[SPIRV_C_Tessellation]>
   ];
 }
-def SPV_EM_Xfb                              : I32EnumAttrCase<"Xfb", 11> {
+def SPIRV_EM_Xfb                              : I32EnumAttrCase<"Xfb", 11> {
   list<Availability> availability = [
-    Capability<[SPV_C_TransformFeedback]>
+    Capability<[SPIRV_C_TransformFeedback]>
   ];
 }
-def SPV_EM_DepthReplacing                   : I32EnumAttrCase<"DepthReplacing", 12> {
+def SPIRV_EM_DepthReplacing                   : I32EnumAttrCase<"DepthReplacing", 12> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_EM_DepthGreater                     : I32EnumAttrCase<"DepthGreater", 14> {
+def SPIRV_EM_DepthGreater                     : I32EnumAttrCase<"DepthGreater", 14> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_EM_DepthLess                        : I32EnumAttrCase<"DepthLess", 15> {
+def SPIRV_EM_DepthLess                        : I32EnumAttrCase<"DepthLess", 15> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_EM_DepthUnchanged                   : I32EnumAttrCase<"DepthUnchanged", 16> {
+def SPIRV_EM_DepthUnchanged                   : I32EnumAttrCase<"DepthUnchanged", 16> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_EM_LocalSize                        : I32EnumAttrCase<"LocalSize", 17>;
-def SPV_EM_LocalSizeHint                    : I32EnumAttrCase<"LocalSizeHint", 18> {
+def SPIRV_EM_LocalSize                        : I32EnumAttrCase<"LocalSize", 17>;
+def SPIRV_EM_LocalSizeHint                    : I32EnumAttrCase<"LocalSizeHint", 18> {
   list<Availability> availability = [
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_EM_InputPoints                      : I32EnumAttrCase<"InputPoints", 19> {
+def SPIRV_EM_InputPoints                      : I32EnumAttrCase<"InputPoints", 19> {
   list<Availability> availability = [
-    Capability<[SPV_C_Geometry]>
+    Capability<[SPIRV_C_Geometry]>
   ];
 }
-def SPV_EM_InputLines                       : I32EnumAttrCase<"InputLines", 20> {
+def SPIRV_EM_InputLines                       : I32EnumAttrCase<"InputLines", 20> {
   list<Availability> availability = [
-    Capability<[SPV_C_Geometry]>
+    Capability<[SPIRV_C_Geometry]>
   ];
 }
-def SPV_EM_InputLinesAdjacency              : I32EnumAttrCase<"InputLinesAdjacency", 21> {
+def SPIRV_EM_InputLinesAdjacency              : I32EnumAttrCase<"InputLinesAdjacency", 21> {
   list<Availability> availability = [
-    Capability<[SPV_C_Geometry]>
+    Capability<[SPIRV_C_Geometry]>
   ];
 }
-def SPV_EM_Triangles                        : I32EnumAttrCase<"Triangles", 22> {
+def SPIRV_EM_Triangles                        : I32EnumAttrCase<"Triangles", 22> {
   list<Availability> availability = [
-    Capability<[SPV_C_Geometry, SPV_C_Tessellation]>
+    Capability<[SPIRV_C_Geometry, SPIRV_C_Tessellation]>
   ];
 }
-def SPV_EM_InputTrianglesAdjacency          : I32EnumAttrCase<"InputTrianglesAdjacency", 23> {
+def SPIRV_EM_InputTrianglesAdjacency          : I32EnumAttrCase<"InputTrianglesAdjacency", 23> {
   list<Availability> availability = [
-    Capability<[SPV_C_Geometry]>
+    Capability<[SPIRV_C_Geometry]>
   ];
 }
-def SPV_EM_Quads                            : I32EnumAttrCase<"Quads", 24> {
+def SPIRV_EM_Quads                            : I32EnumAttrCase<"Quads", 24> {
   list<Availability> availability = [
-    Capability<[SPV_C_Tessellation]>
+    Capability<[SPIRV_C_Tessellation]>
   ];
 }
-def SPV_EM_Isolines                         : I32EnumAttrCase<"Isolines", 25> {
+def SPIRV_EM_Isolines                         : I32EnumAttrCase<"Isolines", 25> {
   list<Availability> availability = [
-    Capability<[SPV_C_Tessellation]>
+    Capability<[SPIRV_C_Tessellation]>
   ];
 }
-def SPV_EM_OutputVertices                   : I32EnumAttrCase<"OutputVertices", 26> {
+def SPIRV_EM_OutputVertices                   : I32EnumAttrCase<"OutputVertices", 26> {
   list<Availability> availability = [
-    Capability<[SPV_C_Geometry, SPV_C_MeshShadingNV, SPV_C_Tessellation]>
+    Capability<[SPIRV_C_Geometry, SPIRV_C_MeshShadingNV, SPIRV_C_Tessellation]>
   ];
 }
-def SPV_EM_OutputPoints                     : I32EnumAttrCase<"OutputPoints", 27> {
+def SPIRV_EM_OutputPoints                     : I32EnumAttrCase<"OutputPoints", 27> {
   list<Availability> availability = [
-    Capability<[SPV_C_Geometry, SPV_C_MeshShadingNV]>
+    Capability<[SPIRV_C_Geometry, SPIRV_C_MeshShadingNV]>
   ];
 }
-def SPV_EM_OutputLineStrip                  : I32EnumAttrCase<"OutputLineStrip", 28> {
+def SPIRV_EM_OutputLineStrip                  : I32EnumAttrCase<"OutputLineStrip", 28> {
   list<Availability> availability = [
-    Capability<[SPV_C_Geometry]>
+    Capability<[SPIRV_C_Geometry]>
   ];
 }
-def SPV_EM_OutputTriangleStrip              : I32EnumAttrCase<"OutputTriangleStrip", 29> {
+def SPIRV_EM_OutputTriangleStrip              : I32EnumAttrCase<"OutputTriangleStrip", 29> {
   list<Availability> availability = [
-    Capability<[SPV_C_Geometry]>
+    Capability<[SPIRV_C_Geometry]>
   ];
 }
-def SPV_EM_VecTypeHint                      : I32EnumAttrCase<"VecTypeHint", 30> {
+def SPIRV_EM_VecTypeHint                      : I32EnumAttrCase<"VecTypeHint", 30> {
   list<Availability> availability = [
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_EM_ContractionOff                   : I32EnumAttrCase<"ContractionOff", 31> {
+def SPIRV_EM_ContractionOff                   : I32EnumAttrCase<"ContractionOff", 31> {
   list<Availability> availability = [
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_EM_Initializer                      : I32EnumAttrCase<"Initializer", 33> {
+def SPIRV_EM_Initializer                      : I32EnumAttrCase<"Initializer", 33> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_1>,
-    Capability<[SPV_C_Kernel]>
+    MinVersion<SPIRV_V_1_1>,
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_EM_Finalizer                        : I32EnumAttrCase<"Finalizer", 34> {
+def SPIRV_EM_Finalizer                        : I32EnumAttrCase<"Finalizer", 34> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_1>,
-    Capability<[SPV_C_Kernel]>
+    MinVersion<SPIRV_V_1_1>,
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_EM_SubgroupSize                     : I32EnumAttrCase<"SubgroupSize", 35> {
+def SPIRV_EM_SubgroupSize                     : I32EnumAttrCase<"SubgroupSize", 35> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_1>,
-    Capability<[SPV_C_SubgroupDispatch]>
+    MinVersion<SPIRV_V_1_1>,
+    Capability<[SPIRV_C_SubgroupDispatch]>
   ];
 }
-def SPV_EM_SubgroupsPerWorkgroup            : I32EnumAttrCase<"SubgroupsPerWorkgroup", 36> {
+def SPIRV_EM_SubgroupsPerWorkgroup            : I32EnumAttrCase<"SubgroupsPerWorkgroup", 36> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_1>,
-    Capability<[SPV_C_SubgroupDispatch]>
+    MinVersion<SPIRV_V_1_1>,
+    Capability<[SPIRV_C_SubgroupDispatch]>
   ];
 }
-def SPV_EM_SubgroupsPerWorkgroupId          : I32EnumAttrCase<"SubgroupsPerWorkgroupId", 37> {
+def SPIRV_EM_SubgroupsPerWorkgroupId          : I32EnumAttrCase<"SubgroupsPerWorkgroupId", 37> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_2>,
-    Capability<[SPV_C_SubgroupDispatch]>
+    MinVersion<SPIRV_V_1_2>,
+    Capability<[SPIRV_C_SubgroupDispatch]>
   ];
 }
-def SPV_EM_LocalSizeId                      : I32EnumAttrCase<"LocalSizeId", 38> {
+def SPIRV_EM_LocalSizeId                      : I32EnumAttrCase<"LocalSizeId", 38> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_2>
+    MinVersion<SPIRV_V_1_2>
   ];
 }
-def SPV_EM_LocalSizeHintId                  : I32EnumAttrCase<"LocalSizeHintId", 39> {
+def SPIRV_EM_LocalSizeHintId                  : I32EnumAttrCase<"LocalSizeHintId", 39> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_2>,
-    Capability<[SPV_C_Kernel]>
+    MinVersion<SPIRV_V_1_2>,
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_EM_SubgroupUniformControlFlowKHR    : I32EnumAttrCase<"SubgroupUniformControlFlowKHR", 4421> {
+def SPIRV_EM_SubgroupUniformControlFlowKHR    : I32EnumAttrCase<"SubgroupUniformControlFlowKHR", 4421> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_subgroup_uniform_control_flow]>,
-    Capability<[SPV_C_Shader]>
+    Extension<[SPIRV_KHR_subgroup_uniform_control_flow]>,
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_EM_PostDepthCoverage                : I32EnumAttrCase<"PostDepthCoverage", 4446> {
+def SPIRV_EM_PostDepthCoverage                : I32EnumAttrCase<"PostDepthCoverage", 4446> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_post_depth_coverage]>,
-    Capability<[SPV_C_SampleMaskPostDepthCoverage]>
+    Extension<[SPIRV_KHR_post_depth_coverage]>,
+    Capability<[SPIRV_C_SampleMaskPostDepthCoverage]>
   ];
 }
-def SPV_EM_DenormPreserve                   : I32EnumAttrCase<"DenormPreserve", 4459> {
+def SPIRV_EM_DenormPreserve                   : I32EnumAttrCase<"DenormPreserve", 4459> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_float_controls]>,
-    Capability<[SPV_C_DenormPreserve]>
+    Extension<[SPIRV_KHR_float_controls]>,
+    Capability<[SPIRV_C_DenormPreserve]>
   ];
 }
-def SPV_EM_DenormFlushToZero                : I32EnumAttrCase<"DenormFlushToZero", 4460> {
+def SPIRV_EM_DenormFlushToZero                : I32EnumAttrCase<"DenormFlushToZero", 4460> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_float_controls]>,
-    Capability<[SPV_C_DenormFlushToZero]>
+    Extension<[SPIRV_KHR_float_controls]>,
+    Capability<[SPIRV_C_DenormFlushToZero]>
   ];
 }
-def SPV_EM_SignedZeroInfNanPreserve         : I32EnumAttrCase<"SignedZeroInfNanPreserve", 4461> {
+def SPIRV_EM_SignedZeroInfNanPreserve         : I32EnumAttrCase<"SignedZeroInfNanPreserve", 4461> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_float_controls]>,
-    Capability<[SPV_C_SignedZeroInfNanPreserve]>
+    Extension<[SPIRV_KHR_float_controls]>,
+    Capability<[SPIRV_C_SignedZeroInfNanPreserve]>
   ];
 }
-def SPV_EM_RoundingModeRTE                  : I32EnumAttrCase<"RoundingModeRTE", 4462> {
+def SPIRV_EM_RoundingModeRTE                  : I32EnumAttrCase<"RoundingModeRTE", 4462> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_float_controls]>,
-    Capability<[SPV_C_RoundingModeRTE]>
+    Extension<[SPIRV_KHR_float_controls]>,
+    Capability<[SPIRV_C_RoundingModeRTE]>
   ];
 }
-def SPV_EM_RoundingModeRTZ                  : I32EnumAttrCase<"RoundingModeRTZ", 4463> {
+def SPIRV_EM_RoundingModeRTZ                  : I32EnumAttrCase<"RoundingModeRTZ", 4463> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_float_controls]>,
-    Capability<[SPV_C_RoundingModeRTZ]>
+    Extension<[SPIRV_KHR_float_controls]>,
+    Capability<[SPIRV_C_RoundingModeRTZ]>
   ];
 }
-def SPV_EM_EarlyAndLateFragmentTestsAMD     : I32EnumAttrCase<"EarlyAndLateFragmentTestsAMD", 5017> {
+def SPIRV_EM_EarlyAndLateFragmentTestsAMD     : I32EnumAttrCase<"EarlyAndLateFragmentTestsAMD", 5017> {
   list<Availability> availability = [
-    Extension<[SPV_AMD_shader_early_and_late_fragment_tests]>,
-    Capability<[SPV_C_Shader]>
+    Extension<[SPIRV_AMD_shader_early_and_late_fragment_tests]>,
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_EM_StencilRefReplacingEXT           : I32EnumAttrCase<"StencilRefReplacingEXT", 5027> {
+def SPIRV_EM_StencilRefReplacingEXT           : I32EnumAttrCase<"StencilRefReplacingEXT", 5027> {
   list<Availability> availability = [
-    Extension<[SPV_EXT_shader_stencil_export]>,
-    Capability<[SPV_C_StencilExportEXT]>
+    Extension<[SPIRV_EXT_shader_stencil_export]>,
+    Capability<[SPIRV_C_StencilExportEXT]>
   ];
 }
-def SPV_EM_StencilRefUnchangedFrontAMD      : I32EnumAttrCase<"StencilRefUnchangedFrontAMD", 5079> {
+def SPIRV_EM_StencilRefUnchangedFrontAMD      : I32EnumAttrCase<"StencilRefUnchangedFrontAMD", 5079> {
   list<Availability> availability = [
-    Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>,
-    Capability<[SPV_C_StencilExportEXT]>
+    Extension<[SPIRV_AMD_shader_early_and_late_fragment_tests, SPIRV_EXT_shader_stencil_export]>,
+    Capability<[SPIRV_C_StencilExportEXT]>
   ];
 }
-def SPV_EM_StencilRefGreaterFrontAMD        : I32EnumAttrCase<"StencilRefGreaterFrontAMD", 5080> {
+def SPIRV_EM_StencilRefGreaterFrontAMD        : I32EnumAttrCase<"StencilRefGreaterFrontAMD", 5080> {
   list<Availability> availability = [
-    Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>,
-    Capability<[SPV_C_StencilExportEXT]>
+    Extension<[SPIRV_AMD_shader_early_and_late_fragment_tests, SPIRV_EXT_shader_stencil_export]>,
+    Capability<[SPIRV_C_StencilExportEXT]>
   ];
 }
-def SPV_EM_StencilRefLessFrontAMD           : I32EnumAttrCase<"StencilRefLessFrontAMD", 5081> {
+def SPIRV_EM_StencilRefLessFrontAMD           : I32EnumAttrCase<"StencilRefLessFrontAMD", 5081> {
   list<Availability> availability = [
-    Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>,
-    Capability<[SPV_C_StencilExportEXT]>
+    Extension<[SPIRV_AMD_shader_early_and_late_fragment_tests, SPIRV_EXT_shader_stencil_export]>,
+    Capability<[SPIRV_C_StencilExportEXT]>
   ];
 }
-def SPV_EM_StencilRefUnchangedBackAMD       : I32EnumAttrCase<"StencilRefUnchangedBackAMD", 5082> {
+def SPIRV_EM_StencilRefUnchangedBackAMD       : I32EnumAttrCase<"StencilRefUnchangedBackAMD", 5082> {
   list<Availability> availability = [
-    Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>,
-    Capability<[SPV_C_StencilExportEXT]>
+    Extension<[SPIRV_AMD_shader_early_and_late_fragment_tests, SPIRV_EXT_shader_stencil_export]>,
+    Capability<[SPIRV_C_StencilExportEXT]>
   ];
 }
-def SPV_EM_StencilRefGreaterBackAMD         : I32EnumAttrCase<"StencilRefGreaterBackAMD", 5083> {
+def SPIRV_EM_StencilRefGreaterBackAMD         : I32EnumAttrCase<"StencilRefGreaterBackAMD", 5083> {
   list<Availability> availability = [
-    Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>,
-    Capability<[SPV_C_StencilExportEXT]>
+    Extension<[SPIRV_AMD_shader_early_and_late_fragment_tests, SPIRV_EXT_shader_stencil_export]>,
+    Capability<[SPIRV_C_StencilExportEXT]>
   ];
 }
-def SPV_EM_StencilRefLessBackAMD            : I32EnumAttrCase<"StencilRefLessBackAMD", 5084> {
+def SPIRV_EM_StencilRefLessBackAMD            : I32EnumAttrCase<"StencilRefLessBackAMD", 5084> {
   list<Availability> availability = [
-    Extension<[SPV_AMD_shader_early_and_late_fragment_tests, SPV_EXT_shader_stencil_export]>,
-    Capability<[SPV_C_StencilExportEXT]>
+    Extension<[SPIRV_AMD_shader_early_and_late_fragment_tests, SPIRV_EXT_shader_stencil_export]>,
+    Capability<[SPIRV_C_StencilExportEXT]>
   ];
 }
-def SPV_EM_OutputLinesNV                    : I32EnumAttrCase<"OutputLinesNV", 5269> {
+def SPIRV_EM_OutputLinesNV                    : I32EnumAttrCase<"OutputLinesNV", 5269> {
   list<Availability> availability = [
-    Extension<[SPV_NV_mesh_shader]>,
-    Capability<[SPV_C_MeshShadingNV]>
+    Extension<[SPIRV_NV_mesh_shader]>,
+    Capability<[SPIRV_C_MeshShadingNV]>
   ];
 }
-def SPV_EM_OutputPrimitivesNV               : I32EnumAttrCase<"OutputPrimitivesNV", 5270> {
+def SPIRV_EM_OutputPrimitivesNV               : I32EnumAttrCase<"OutputPrimitivesNV", 5270> {
   list<Availability> availability = [
-    Extension<[SPV_NV_mesh_shader]>,
-    Capability<[SPV_C_MeshShadingNV]>
+    Extension<[SPIRV_NV_mesh_shader]>,
+    Capability<[SPIRV_C_MeshShadingNV]>
   ];
 }
-def SPV_EM_DerivativeGroupQuadsNV           : I32EnumAttrCase<"DerivativeGroupQuadsNV", 5289> {
+def SPIRV_EM_DerivativeGroupQuadsNV           : I32EnumAttrCase<"DerivativeGroupQuadsNV", 5289> {
   list<Availability> availability = [
-    Extension<[SPV_NV_compute_shader_derivatives]>,
-    Capability<[SPV_C_ComputeDerivativeGroupQuadsNV]>
+    Extension<[SPIRV_NV_compute_shader_derivatives]>,
+    Capability<[SPIRV_C_ComputeDerivativeGroupQuadsNV]>
   ];
 }
-def SPV_EM_DerivativeGroupLinearNV          : I32EnumAttrCase<"DerivativeGroupLinearNV", 5290> {
+def SPIRV_EM_DerivativeGroupLinearNV          : I32EnumAttrCase<"DerivativeGroupLinearNV", 5290> {
   list<Availability> availability = [
-    Extension<[SPV_NV_compute_shader_derivatives]>,
-    Capability<[SPV_C_ComputeDerivativeGroupLinearNV]>
+    Extension<[SPIRV_NV_compute_shader_derivatives]>,
+    Capability<[SPIRV_C_ComputeDerivativeGroupLinearNV]>
   ];
 }
-def SPV_EM_OutputTrianglesNV                : I32EnumAttrCase<"OutputTrianglesNV", 5298> {
+def SPIRV_EM_OutputTrianglesNV                : I32EnumAttrCase<"OutputTrianglesNV", 5298> {
   list<Availability> availability = [
-    Extension<[SPV_NV_mesh_shader]>,
-    Capability<[SPV_C_MeshShadingNV]>
+    Extension<[SPIRV_NV_mesh_shader]>,
+    Capability<[SPIRV_C_MeshShadingNV]>
   ];
 }
-def SPV_EM_PixelInterlockOrderedEXT         : I32EnumAttrCase<"PixelInterlockOrderedEXT", 5366> {
+def SPIRV_EM_PixelInterlockOrderedEXT         : I32EnumAttrCase<"PixelInterlockOrderedEXT", 5366> {
   list<Availability> availability = [
-    Extension<[SPV_EXT_fragment_shader_interlock]>,
-    Capability<[SPV_C_FragmentShaderPixelInterlockEXT]>
+    Extension<[SPIRV_EXT_fragment_shader_interlock]>,
+    Capability<[SPIRV_C_FragmentShaderPixelInterlockEXT]>
   ];
 }
-def SPV_EM_PixelInterlockUnorderedEXT       : I32EnumAttrCase<"PixelInterlockUnorderedEXT", 5367> {
+def SPIRV_EM_PixelInterlockUnorderedEXT       : I32EnumAttrCase<"PixelInterlockUnorderedEXT", 5367> {
   list<Availability> availability = [
-    Extension<[SPV_EXT_fragment_shader_interlock]>,
-    Capability<[SPV_C_FragmentShaderPixelInterlockEXT]>
+    Extension<[SPIRV_EXT_fragment_shader_interlock]>,
+    Capability<[SPIRV_C_FragmentShaderPixelInterlockEXT]>
   ];
 }
-def SPV_EM_SampleInterlockOrderedEXT        : I32EnumAttrCase<"SampleInterlockOrderedEXT", 5368> {
+def SPIRV_EM_SampleInterlockOrderedEXT        : I32EnumAttrCase<"SampleInterlockOrderedEXT", 5368> {
   list<Availability> availability = [
-    Extension<[SPV_EXT_fragment_shader_interlock]>,
-    Capability<[SPV_C_FragmentShaderSampleInterlockEXT]>
+    Extension<[SPIRV_EXT_fragment_shader_interlock]>,
+    Capability<[SPIRV_C_FragmentShaderSampleInterlockEXT]>
   ];
 }
-def SPV_EM_SampleInterlockUnorderedEXT      : I32EnumAttrCase<"SampleInterlockUnorderedEXT", 5369> {
+def SPIRV_EM_SampleInterlockUnorderedEXT      : I32EnumAttrCase<"SampleInterlockUnorderedEXT", 5369> {
   list<Availability> availability = [
-    Extension<[SPV_EXT_fragment_shader_interlock]>,
-    Capability<[SPV_C_FragmentShaderSampleInterlockEXT]>
+    Extension<[SPIRV_EXT_fragment_shader_interlock]>,
+    Capability<[SPIRV_C_FragmentShaderSampleInterlockEXT]>
   ];
 }
-def SPV_EM_ShadingRateInterlockOrderedEXT   : I32EnumAttrCase<"ShadingRateInterlockOrderedEXT", 5370> {
+def SPIRV_EM_ShadingRateInterlockOrderedEXT   : I32EnumAttrCase<"ShadingRateInterlockOrderedEXT", 5370> {
   list<Availability> availability = [
-    Extension<[SPV_EXT_fragment_shader_interlock]>,
-    Capability<[SPV_C_FragmentShaderShadingRateInterlockEXT]>
+    Extension<[SPIRV_EXT_fragment_shader_interlock]>,
+    Capability<[SPIRV_C_FragmentShaderShadingRateInterlockEXT]>
   ];
 }
-def SPV_EM_ShadingRateInterlockUnorderedEXT : I32EnumAttrCase<"ShadingRateInterlockUnorderedEXT", 5371> {
+def SPIRV_EM_ShadingRateInterlockUnorderedEXT : I32EnumAttrCase<"ShadingRateInterlockUnorderedEXT", 5371> {
   list<Availability> availability = [
-    Extension<[SPV_EXT_fragment_shader_interlock]>,
-    Capability<[SPV_C_FragmentShaderShadingRateInterlockEXT]>
+    Extension<[SPIRV_EXT_fragment_shader_interlock]>,
+    Capability<[SPIRV_C_FragmentShaderShadingRateInterlockEXT]>
   ];
 }
-def SPV_EM_SharedLocalMemorySizeINTEL       : I32EnumAttrCase<"SharedLocalMemorySizeINTEL", 5618> {
+def SPIRV_EM_SharedLocalMemorySizeINTEL       : I32EnumAttrCase<"SharedLocalMemorySizeINTEL", 5618> {
   list<Availability> availability = [
-    Capability<[SPV_C_VectorComputeINTEL]>
+    Capability<[SPIRV_C_VectorComputeINTEL]>
   ];
 }
-def SPV_EM_RoundingModeRTPINTEL             : I32EnumAttrCase<"RoundingModeRTPINTEL", 5620> {
+def SPIRV_EM_RoundingModeRTPINTEL             : I32EnumAttrCase<"RoundingModeRTPINTEL", 5620> {
   list<Availability> availability = [
-    Capability<[SPV_C_RoundToInfinityINTEL]>
+    Capability<[SPIRV_C_RoundToInfinityINTEL]>
   ];
 }
-def SPV_EM_RoundingModeRTNINTEL             : I32EnumAttrCase<"RoundingModeRTNINTEL", 5621> {
+def SPIRV_EM_RoundingModeRTNINTEL             : I32EnumAttrCase<"RoundingModeRTNINTEL", 5621> {
   list<Availability> availability = [
-    Capability<[SPV_C_RoundToInfinityINTEL]>
+    Capability<[SPIRV_C_RoundToInfinityINTEL]>
   ];
 }
-def SPV_EM_FloatingPointModeALTINTEL        : I32EnumAttrCase<"FloatingPointModeALTINTEL", 5622> {
+def SPIRV_EM_FloatingPointModeALTINTEL        : I32EnumAttrCase<"FloatingPointModeALTINTEL", 5622> {
   list<Availability> availability = [
-    Capability<[SPV_C_RoundToInfinityINTEL]>
+    Capability<[SPIRV_C_RoundToInfinityINTEL]>
   ];
 }
-def SPV_EM_FloatingPointModeIEEEINTEL       : I32EnumAttrCase<"FloatingPointModeIEEEINTEL", 5623> {
+def SPIRV_EM_FloatingPointModeIEEEINTEL       : I32EnumAttrCase<"FloatingPointModeIEEEINTEL", 5623> {
   list<Availability> availability = [
-    Capability<[SPV_C_RoundToInfinityINTEL]>
+    Capability<[SPIRV_C_RoundToInfinityINTEL]>
   ];
 }
-def SPV_EM_MaxWorkgroupSizeINTEL            : I32EnumAttrCase<"MaxWorkgroupSizeINTEL", 5893> {
+def SPIRV_EM_MaxWorkgroupSizeINTEL            : I32EnumAttrCase<"MaxWorkgroupSizeINTEL", 5893> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_kernel_attributes]>,
-    Capability<[SPV_C_KernelAttributesINTEL]>
+    Extension<[SPIRV_INTEL_kernel_attributes]>,
+    Capability<[SPIRV_C_KernelAttributesINTEL]>
   ];
 }
-def SPV_EM_MaxWorkDimINTEL                  : I32EnumAttrCase<"MaxWorkDimINTEL", 5894> {
+def SPIRV_EM_MaxWorkDimINTEL                  : I32EnumAttrCase<"MaxWorkDimINTEL", 5894> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_kernel_attributes]>,
-    Capability<[SPV_C_KernelAttributesINTEL]>
+    Extension<[SPIRV_INTEL_kernel_attributes]>,
+    Capability<[SPIRV_C_KernelAttributesINTEL]>
   ];
 }
-def SPV_EM_NoGlobalOffsetINTEL              : I32EnumAttrCase<"NoGlobalOffsetINTEL", 5895> {
+def SPIRV_EM_NoGlobalOffsetINTEL              : I32EnumAttrCase<"NoGlobalOffsetINTEL", 5895> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_kernel_attributes]>,
-    Capability<[SPV_C_KernelAttributesINTEL]>
+    Extension<[SPIRV_INTEL_kernel_attributes]>,
+    Capability<[SPIRV_C_KernelAttributesINTEL]>
   ];
 }
-def SPV_EM_NumSIMDWorkitemsINTEL            : I32EnumAttrCase<"NumSIMDWorkitemsINTEL", 5896> {
+def SPIRV_EM_NumSIMDWorkitemsINTEL            : I32EnumAttrCase<"NumSIMDWorkitemsINTEL", 5896> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_kernel_attributes]>,
-    Capability<[SPV_C_FPGAKernelAttributesINTEL]>
+    Extension<[SPIRV_INTEL_kernel_attributes]>,
+    Capability<[SPIRV_C_FPGAKernelAttributesINTEL]>
   ];
 }
-def SPV_EM_SchedulerTargetFmaxMhzINTEL      : I32EnumAttrCase<"SchedulerTargetFmaxMhzINTEL", 5903> {
+def SPIRV_EM_SchedulerTargetFmaxMhzINTEL      : I32EnumAttrCase<"SchedulerTargetFmaxMhzINTEL", 5903> {
   list<Availability> availability = [
-    Capability<[SPV_C_FPGAKernelAttributesINTEL]>
+    Capability<[SPIRV_C_FPGAKernelAttributesINTEL]>
   ];
 }
-def SPV_EM_NamedBarrierCountINTEL           : I32EnumAttrCase<"NamedBarrierCountINTEL", 6417> {
+def SPIRV_EM_NamedBarrierCountINTEL           : I32EnumAttrCase<"NamedBarrierCountINTEL", 6417> {
   list<Availability> availability = [
-    Capability<[SPV_C_VectorComputeINTEL]>
+    Capability<[SPIRV_C_VectorComputeINTEL]>
   ];
 }
 
-def SPV_ExecutionModeAttr :
-    SPV_I32EnumAttr<"ExecutionMode", "valid SPIR-V ExecutionMode", "execution_mode", [
-      SPV_EM_Invocations, SPV_EM_SpacingEqual, SPV_EM_SpacingFractionalEven,
-      SPV_EM_SpacingFractionalOdd, SPV_EM_VertexOrderCw, SPV_EM_VertexOrderCcw,
-      SPV_EM_PixelCenterInteger, SPV_EM_OriginUpperLeft, SPV_EM_OriginLowerLeft,
-      SPV_EM_EarlyFragmentTests, SPV_EM_PointMode, SPV_EM_Xfb, SPV_EM_DepthReplacing,
-      SPV_EM_DepthGreater, SPV_EM_DepthLess, SPV_EM_DepthUnchanged, SPV_EM_LocalSize,
-      SPV_EM_LocalSizeHint, SPV_EM_InputPoints, SPV_EM_InputLines,
-      SPV_EM_InputLinesAdjacency, SPV_EM_Triangles, SPV_EM_InputTrianglesAdjacency,
-      SPV_EM_Quads, SPV_EM_Isolines, SPV_EM_OutputVertices, SPV_EM_OutputPoints,
-      SPV_EM_OutputLineStrip, SPV_EM_OutputTriangleStrip, SPV_EM_VecTypeHint,
-      SPV_EM_ContractionOff, SPV_EM_Initializer, SPV_EM_Finalizer,
-      SPV_EM_SubgroupSize, SPV_EM_SubgroupsPerWorkgroup,
-      SPV_EM_SubgroupsPerWorkgroupId, SPV_EM_LocalSizeId, SPV_EM_LocalSizeHintId,
-      SPV_EM_SubgroupUniformControlFlowKHR, SPV_EM_PostDepthCoverage,
-      SPV_EM_DenormPreserve, SPV_EM_DenormFlushToZero,
-      SPV_EM_SignedZeroInfNanPreserve, SPV_EM_RoundingModeRTE,
-      SPV_EM_RoundingModeRTZ, SPV_EM_EarlyAndLateFragmentTestsAMD,
-      SPV_EM_StencilRefReplacingEXT, SPV_EM_StencilRefUnchangedFrontAMD,
-      SPV_EM_StencilRefGreaterFrontAMD, SPV_EM_StencilRefLessFrontAMD,
-      SPV_EM_StencilRefUnchangedBackAMD, SPV_EM_StencilRefGreaterBackAMD,
-      SPV_EM_StencilRefLessBackAMD, SPV_EM_OutputLinesNV, SPV_EM_OutputPrimitivesNV,
-      SPV_EM_DerivativeGroupQuadsNV, SPV_EM_DerivativeGroupLinearNV,
-      SPV_EM_OutputTrianglesNV, SPV_EM_PixelInterlockOrderedEXT,
-      SPV_EM_PixelInterlockUnorderedEXT, SPV_EM_SampleInterlockOrderedEXT,
-      SPV_EM_SampleInterlockUnorderedEXT, SPV_EM_ShadingRateInterlockOrderedEXT,
-      SPV_EM_ShadingRateInterlockUnorderedEXT, SPV_EM_SharedLocalMemorySizeINTEL,
-      SPV_EM_RoundingModeRTPINTEL, SPV_EM_RoundingModeRTNINTEL,
-      SPV_EM_FloatingPointModeALTINTEL, SPV_EM_FloatingPointModeIEEEINTEL,
-      SPV_EM_MaxWorkgroupSizeINTEL, SPV_EM_MaxWorkDimINTEL,
-      SPV_EM_NoGlobalOffsetINTEL, SPV_EM_NumSIMDWorkitemsINTEL,
-      SPV_EM_SchedulerTargetFmaxMhzINTEL, SPV_EM_NamedBarrierCountINTEL
+def SPIRV_ExecutionModeAttr :
+    SPIRV_I32EnumAttr<"ExecutionMode", "valid SPIR-V ExecutionMode", "execution_mode", [
+      SPIRV_EM_Invocations, SPIRV_EM_SpacingEqual, SPIRV_EM_SpacingFractionalEven,
+      SPIRV_EM_SpacingFractionalOdd, SPIRV_EM_VertexOrderCw, SPIRV_EM_VertexOrderCcw,
+      SPIRV_EM_PixelCenterInteger, SPIRV_EM_OriginUpperLeft, SPIRV_EM_OriginLowerLeft,
+      SPIRV_EM_EarlyFragmentTests, SPIRV_EM_PointMode, SPIRV_EM_Xfb, SPIRV_EM_DepthReplacing,
+      SPIRV_EM_DepthGreater, SPIRV_EM_DepthLess, SPIRV_EM_DepthUnchanged, SPIRV_EM_LocalSize,
+      SPIRV_EM_LocalSizeHint, SPIRV_EM_InputPoints, SPIRV_EM_InputLines,
+      SPIRV_EM_InputLinesAdjacency, SPIRV_EM_Triangles, SPIRV_EM_InputTrianglesAdjacency,
+      SPIRV_EM_Quads, SPIRV_EM_Isolines, SPIRV_EM_OutputVertices, SPIRV_EM_OutputPoints,
+      SPIRV_EM_OutputLineStrip, SPIRV_EM_OutputTriangleStrip, SPIRV_EM_VecTypeHint,
+      SPIRV_EM_ContractionOff, SPIRV_EM_Initializer, SPIRV_EM_Finalizer,
+      SPIRV_EM_SubgroupSize, SPIRV_EM_SubgroupsPerWorkgroup,
+      SPIRV_EM_SubgroupsPerWorkgroupId, SPIRV_EM_LocalSizeId, SPIRV_EM_LocalSizeHintId,
+      SPIRV_EM_SubgroupUniformControlFlowKHR, SPIRV_EM_PostDepthCoverage,
+      SPIRV_EM_DenormPreserve, SPIRV_EM_DenormFlushToZero,
+      SPIRV_EM_SignedZeroInfNanPreserve, SPIRV_EM_RoundingModeRTE,
+      SPIRV_EM_RoundingModeRTZ, SPIRV_EM_EarlyAndLateFragmentTestsAMD,
+      SPIRV_EM_StencilRefReplacingEXT, SPIRV_EM_StencilRefUnchangedFrontAMD,
+      SPIRV_EM_StencilRefGreaterFrontAMD, SPIRV_EM_StencilRefLessFrontAMD,
+      SPIRV_EM_StencilRefUnchangedBackAMD, SPIRV_EM_StencilRefGreaterBackAMD,
+      SPIRV_EM_StencilRefLessBackAMD, SPIRV_EM_OutputLinesNV, SPIRV_EM_OutputPrimitivesNV,
+      SPIRV_EM_DerivativeGroupQuadsNV, SPIRV_EM_DerivativeGroupLinearNV,
+      SPIRV_EM_OutputTrianglesNV, SPIRV_EM_PixelInterlockOrderedEXT,
+      SPIRV_EM_PixelInterlockUnorderedEXT, SPIRV_EM_SampleInterlockOrderedEXT,
+      SPIRV_EM_SampleInterlockUnorderedEXT, SPIRV_EM_ShadingRateInterlockOrderedEXT,
+      SPIRV_EM_ShadingRateInterlockUnorderedEXT, SPIRV_EM_SharedLocalMemorySizeINTEL,
+      SPIRV_EM_RoundingModeRTPINTEL, SPIRV_EM_RoundingModeRTNINTEL,
+      SPIRV_EM_FloatingPointModeALTINTEL, SPIRV_EM_FloatingPointModeIEEEINTEL,
+      SPIRV_EM_MaxWorkgroupSizeINTEL, SPIRV_EM_MaxWorkDimINTEL,
+      SPIRV_EM_NoGlobalOffsetINTEL, SPIRV_EM_NumSIMDWorkitemsINTEL,
+      SPIRV_EM_SchedulerTargetFmaxMhzINTEL, SPIRV_EM_NamedBarrierCountINTEL
     ]>;
 
-def SPV_EM_Vertex                 : I32EnumAttrCase<"Vertex", 0> {
+def SPIRV_EM_Vertex                 : I32EnumAttrCase<"Vertex", 0> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_EM_TessellationControl    : I32EnumAttrCase<"TessellationControl", 1> {
+def SPIRV_EM_TessellationControl    : I32EnumAttrCase<"TessellationControl", 1> {
   list<Availability> availability = [
-    Capability<[SPV_C_Tessellation]>
+    Capability<[SPIRV_C_Tessellation]>
   ];
 }
-def SPV_EM_TessellationEvaluation : I32EnumAttrCase<"TessellationEvaluation", 2> {
+def SPIRV_EM_TessellationEvaluation : I32EnumAttrCase<"TessellationEvaluation", 2> {
   list<Availability> availability = [
-    Capability<[SPV_C_Tessellation]>
+    Capability<[SPIRV_C_Tessellation]>
   ];
 }
-def SPV_EM_Geometry               : I32EnumAttrCase<"Geometry", 3> {
+def SPIRV_EM_Geometry               : I32EnumAttrCase<"Geometry", 3> {
   list<Availability> availability = [
-    Capability<[SPV_C_Geometry]>
+    Capability<[SPIRV_C_Geometry]>
   ];
 }
-def SPV_EM_Fragment               : I32EnumAttrCase<"Fragment", 4> {
+def SPIRV_EM_Fragment               : I32EnumAttrCase<"Fragment", 4> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_EM_GLCompute              : I32EnumAttrCase<"GLCompute", 5> {
+def SPIRV_EM_GLCompute              : I32EnumAttrCase<"GLCompute", 5> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_EM_Kernel                 : I32EnumAttrCase<"Kernel", 6> {
+def SPIRV_EM_Kernel                 : I32EnumAttrCase<"Kernel", 6> {
   list<Availability> availability = [
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_EM_TaskNV                 : I32EnumAttrCase<"TaskNV", 5267> {
+def SPIRV_EM_TaskNV                 : I32EnumAttrCase<"TaskNV", 5267> {
   list<Availability> availability = [
-    Capability<[SPV_C_MeshShadingNV]>
+    Capability<[SPIRV_C_MeshShadingNV]>
   ];
 }
-def SPV_EM_MeshNV                 : I32EnumAttrCase<"MeshNV", 5268> {
+def SPIRV_EM_MeshNV                 : I32EnumAttrCase<"MeshNV", 5268> {
   list<Availability> availability = [
-    Capability<[SPV_C_MeshShadingNV]>
+    Capability<[SPIRV_C_MeshShadingNV]>
   ];
 }
-def SPV_EM_RayGenerationKHR       : I32EnumAttrCase<"RayGenerationKHR", 5313> {
+def SPIRV_EM_RayGenerationKHR       : I32EnumAttrCase<"RayGenerationKHR", 5313> {
   list<Availability> availability = [
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_EM_IntersectionKHR        : I32EnumAttrCase<"IntersectionKHR", 5314> {
+def SPIRV_EM_IntersectionKHR        : I32EnumAttrCase<"IntersectionKHR", 5314> {
   list<Availability> availability = [
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_EM_AnyHitKHR              : I32EnumAttrCase<"AnyHitKHR", 5315> {
+def SPIRV_EM_AnyHitKHR              : I32EnumAttrCase<"AnyHitKHR", 5315> {
   list<Availability> availability = [
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_EM_ClosestHitKHR          : I32EnumAttrCase<"ClosestHitKHR", 5316> {
+def SPIRV_EM_ClosestHitKHR          : I32EnumAttrCase<"ClosestHitKHR", 5316> {
   list<Availability> availability = [
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_EM_MissKHR                : I32EnumAttrCase<"MissKHR", 5317> {
+def SPIRV_EM_MissKHR                : I32EnumAttrCase<"MissKHR", 5317> {
   list<Availability> availability = [
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_EM_CallableKHR            : I32EnumAttrCase<"CallableKHR", 5318> {
+def SPIRV_EM_CallableKHR            : I32EnumAttrCase<"CallableKHR", 5318> {
   list<Availability> availability = [
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
 
-def SPV_ExecutionModelAttr :
-    SPV_I32EnumAttr<"ExecutionModel", "valid SPIR-V ExecutionModel", "execution_model", [
-      SPV_EM_Vertex, SPV_EM_TessellationControl, SPV_EM_TessellationEvaluation,
-      SPV_EM_Geometry, SPV_EM_Fragment, SPV_EM_GLCompute, SPV_EM_Kernel,
-      SPV_EM_TaskNV, SPV_EM_MeshNV, SPV_EM_RayGenerationKHR, SPV_EM_IntersectionKHR,
-      SPV_EM_AnyHitKHR, SPV_EM_ClosestHitKHR, SPV_EM_MissKHR, SPV_EM_CallableKHR
+def SPIRV_ExecutionModelAttr :
+    SPIRV_I32EnumAttr<"ExecutionModel", "valid SPIR-V ExecutionModel", "execution_model", [
+      SPIRV_EM_Vertex, SPIRV_EM_TessellationControl, SPIRV_EM_TessellationEvaluation,
+      SPIRV_EM_Geometry, SPIRV_EM_Fragment, SPIRV_EM_GLCompute, SPIRV_EM_Kernel,
+      SPIRV_EM_TaskNV, SPIRV_EM_MeshNV, SPIRV_EM_RayGenerationKHR, SPIRV_EM_IntersectionKHR,
+      SPIRV_EM_AnyHitKHR, SPIRV_EM_ClosestHitKHR, SPIRV_EM_MissKHR, SPIRV_EM_CallableKHR
     ]>;
 
-def SPV_FC_None         : I32BitEnumAttrCaseNone<"None">;
-def SPV_FC_Inline       : I32BitEnumAttrCaseBit<"Inline", 0>;
-def SPV_FC_DontInline   : I32BitEnumAttrCaseBit<"DontInline", 1>;
-def SPV_FC_Pure         : I32BitEnumAttrCaseBit<"Pure", 2>;
-def SPV_FC_Const        : I32BitEnumAttrCaseBit<"Const", 3>;
-def SPV_FC_OptNoneINTEL : I32BitEnumAttrCaseBit<"OptNoneINTEL", 16> {
+def SPIRV_FC_None         : I32BitEnumAttrCaseNone<"None">;
+def SPIRV_FC_Inline       : I32BitEnumAttrCaseBit<"Inline", 0>;
+def SPIRV_FC_DontInline   : I32BitEnumAttrCaseBit<"DontInline", 1>;
+def SPIRV_FC_Pure         : I32BitEnumAttrCaseBit<"Pure", 2>;
+def SPIRV_FC_Const        : I32BitEnumAttrCaseBit<"Const", 3>;
+def SPIRV_FC_OptNoneINTEL : I32BitEnumAttrCaseBit<"OptNoneINTEL", 16> {
   list<Availability> availability = [
-    Capability<[SPV_C_OptNoneINTEL]>
+    Capability<[SPIRV_C_OptNoneINTEL]>
   ];
 }
 
-def SPV_FunctionControlAttr :
-    SPV_BitEnumAttr<"FunctionControl", "valid SPIR-V FunctionControl", "function_control", [
-      SPV_FC_None, SPV_FC_Inline, SPV_FC_DontInline, SPV_FC_Pure, SPV_FC_Const,
-      SPV_FC_OptNoneINTEL
+def SPIRV_FunctionControlAttr :
+    SPIRV_BitEnumAttr<"FunctionControl", "valid SPIR-V FunctionControl", "function_control", [
+      SPIRV_FC_None, SPIRV_FC_Inline, SPIRV_FC_DontInline, SPIRV_FC_Pure, SPIRV_FC_Const,
+      SPIRV_FC_OptNoneINTEL
     ]>;
 
-def SPV_GO_Reduce                     : I32EnumAttrCase<"Reduce", 0> {
+def SPIRV_GO_Reduce                     : I32EnumAttrCase<"Reduce", 0> {
   list<Availability> availability = [
-    Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformBallot, SPV_C_Kernel]>
+    Capability<[SPIRV_C_GroupNonUniformArithmetic, SPIRV_C_GroupNonUniformBallot, SPIRV_C_Kernel]>
   ];
 }
-def SPV_GO_InclusiveScan              : I32EnumAttrCase<"InclusiveScan", 1> {
+def SPIRV_GO_InclusiveScan              : I32EnumAttrCase<"InclusiveScan", 1> {
   list<Availability> availability = [
-    Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformBallot, SPV_C_Kernel]>
+    Capability<[SPIRV_C_GroupNonUniformArithmetic, SPIRV_C_GroupNonUniformBallot, SPIRV_C_Kernel]>
   ];
 }
-def SPV_GO_ExclusiveScan              : I32EnumAttrCase<"ExclusiveScan", 2> {
+def SPIRV_GO_ExclusiveScan              : I32EnumAttrCase<"ExclusiveScan", 2> {
   list<Availability> availability = [
-    Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformBallot, SPV_C_Kernel]>
+    Capability<[SPIRV_C_GroupNonUniformArithmetic, SPIRV_C_GroupNonUniformBallot, SPIRV_C_Kernel]>
   ];
 }
-def SPV_GO_ClusteredReduce            : I32EnumAttrCase<"ClusteredReduce", 3> {
+def SPIRV_GO_ClusteredReduce            : I32EnumAttrCase<"ClusteredReduce", 3> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_3>,
-    Capability<[SPV_C_GroupNonUniformClustered]>
+    MinVersion<SPIRV_V_1_3>,
+    Capability<[SPIRV_C_GroupNonUniformClustered]>
   ];
 }
-def SPV_GO_PartitionedReduceNV        : I32EnumAttrCase<"PartitionedReduceNV", 6> {
+def SPIRV_GO_PartitionedReduceNV        : I32EnumAttrCase<"PartitionedReduceNV", 6> {
   list<Availability> availability = [
-    Extension<[SPV_NV_shader_subgroup_partitioned]>,
-    Capability<[SPV_C_GroupNonUniformPartitionedNV]>
+    Extension<[SPIRV_NV_shader_subgroup_partitioned]>,
+    Capability<[SPIRV_C_GroupNonUniformPartitionedNV]>
   ];
 }
-def SPV_GO_PartitionedInclusiveScanNV : I32EnumAttrCase<"PartitionedInclusiveScanNV", 7> {
+def SPIRV_GO_PartitionedInclusiveScanNV : I32EnumAttrCase<"PartitionedInclusiveScanNV", 7> {
   list<Availability> availability = [
-    Extension<[SPV_NV_shader_subgroup_partitioned]>,
-    Capability<[SPV_C_GroupNonUniformPartitionedNV]>
+    Extension<[SPIRV_NV_shader_subgroup_partitioned]>,
+    Capability<[SPIRV_C_GroupNonUniformPartitionedNV]>
   ];
 }
-def SPV_GO_PartitionedExclusiveScanNV : I32EnumAttrCase<"PartitionedExclusiveScanNV", 8> {
+def SPIRV_GO_PartitionedExclusiveScanNV : I32EnumAttrCase<"PartitionedExclusiveScanNV", 8> {
   list<Availability> availability = [
-    Extension<[SPV_NV_shader_subgroup_partitioned]>,
-    Capability<[SPV_C_GroupNonUniformPartitionedNV]>
+    Extension<[SPIRV_NV_shader_subgroup_partitioned]>,
+    Capability<[SPIRV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
-def SPV_GroupOperationAttr :
-    SPV_I32EnumAttr<"GroupOperation", "valid SPIR-V GroupOperation", "group_operation", [
-      SPV_GO_Reduce, SPV_GO_InclusiveScan, SPV_GO_ExclusiveScan,
-      SPV_GO_ClusteredReduce, SPV_GO_PartitionedReduceNV,
-      SPV_GO_PartitionedInclusiveScanNV, SPV_GO_PartitionedExclusiveScanNV
+def SPIRV_GroupOperationAttr :
+    SPIRV_I32EnumAttr<"GroupOperation", "valid SPIR-V GroupOperation", "group_operation", [
+      SPIRV_GO_Reduce, SPIRV_GO_InclusiveScan, SPIRV_GO_ExclusiveScan,
+      SPIRV_GO_ClusteredReduce, SPIRV_GO_PartitionedReduceNV,
+      SPIRV_GO_PartitionedInclusiveScanNV, SPIRV_GO_PartitionedExclusiveScanNV
     ]>;
 
-def SPV_IF_Unknown      : I32EnumAttrCase<"Unknown", 0>;
-def SPV_IF_Rgba32f      : I32EnumAttrCase<"Rgba32f", 1> {
+def SPIRV_IF_Unknown      : I32EnumAttrCase<"Unknown", 0>;
+def SPIRV_IF_Rgba32f      : I32EnumAttrCase<"Rgba32f", 1> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_IF_Rgba16f      : I32EnumAttrCase<"Rgba16f", 2> {
+def SPIRV_IF_Rgba16f      : I32EnumAttrCase<"Rgba16f", 2> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_IF_R32f         : I32EnumAttrCase<"R32f", 3> {
+def SPIRV_IF_R32f         : I32EnumAttrCase<"R32f", 3> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_IF_Rgba8        : I32EnumAttrCase<"Rgba8", 4> {
+def SPIRV_IF_Rgba8        : I32EnumAttrCase<"Rgba8", 4> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_IF_Rgba8Snorm   : I32EnumAttrCase<"Rgba8Snorm", 5> {
+def SPIRV_IF_Rgba8Snorm   : I32EnumAttrCase<"Rgba8Snorm", 5> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_IF_Rg32f        : I32EnumAttrCase<"Rg32f", 6> {
+def SPIRV_IF_Rg32f        : I32EnumAttrCase<"Rg32f", 6> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_Rg16f        : I32EnumAttrCase<"Rg16f", 7> {
+def SPIRV_IF_Rg16f        : I32EnumAttrCase<"Rg16f", 7> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_R11fG11fB10f : I32EnumAttrCase<"R11fG11fB10f", 8> {
+def SPIRV_IF_R11fG11fB10f : I32EnumAttrCase<"R11fG11fB10f", 8> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_R16f         : I32EnumAttrCase<"R16f", 9> {
+def SPIRV_IF_R16f         : I32EnumAttrCase<"R16f", 9> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_Rgba16       : I32EnumAttrCase<"Rgba16", 10> {
+def SPIRV_IF_Rgba16       : I32EnumAttrCase<"Rgba16", 10> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_Rgb10A2      : I32EnumAttrCase<"Rgb10A2", 11> {
+def SPIRV_IF_Rgb10A2      : I32EnumAttrCase<"Rgb10A2", 11> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_Rg16         : I32EnumAttrCase<"Rg16", 12> {
+def SPIRV_IF_Rg16         : I32EnumAttrCase<"Rg16", 12> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_Rg8          : I32EnumAttrCase<"Rg8", 13> {
+def SPIRV_IF_Rg8          : I32EnumAttrCase<"Rg8", 13> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_R16          : I32EnumAttrCase<"R16", 14> {
+def SPIRV_IF_R16          : I32EnumAttrCase<"R16", 14> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_R8           : I32EnumAttrCase<"R8", 15> {
+def SPIRV_IF_R8           : I32EnumAttrCase<"R8", 15> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_Rgba16Snorm  : I32EnumAttrCase<"Rgba16Snorm", 16> {
+def SPIRV_IF_Rgba16Snorm  : I32EnumAttrCase<"Rgba16Snorm", 16> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_Rg16Snorm    : I32EnumAttrCase<"Rg16Snorm", 17> {
+def SPIRV_IF_Rg16Snorm    : I32EnumAttrCase<"Rg16Snorm", 17> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_Rg8Snorm     : I32EnumAttrCase<"Rg8Snorm", 18> {
+def SPIRV_IF_Rg8Snorm     : I32EnumAttrCase<"Rg8Snorm", 18> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_R16Snorm     : I32EnumAttrCase<"R16Snorm", 19> {
+def SPIRV_IF_R16Snorm     : I32EnumAttrCase<"R16Snorm", 19> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_R8Snorm      : I32EnumAttrCase<"R8Snorm", 20> {
+def SPIRV_IF_R8Snorm      : I32EnumAttrCase<"R8Snorm", 20> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_Rgba32i      : I32EnumAttrCase<"Rgba32i", 21> {
+def SPIRV_IF_Rgba32i      : I32EnumAttrCase<"Rgba32i", 21> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_IF_Rgba16i      : I32EnumAttrCase<"Rgba16i", 22> {
+def SPIRV_IF_Rgba16i      : I32EnumAttrCase<"Rgba16i", 22> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_IF_Rgba8i       : I32EnumAttrCase<"Rgba8i", 23> {
+def SPIRV_IF_Rgba8i       : I32EnumAttrCase<"Rgba8i", 23> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_IF_R32i         : I32EnumAttrCase<"R32i", 24> {
+def SPIRV_IF_R32i         : I32EnumAttrCase<"R32i", 24> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_IF_Rg32i        : I32EnumAttrCase<"Rg32i", 25> {
+def SPIRV_IF_Rg32i        : I32EnumAttrCase<"Rg32i", 25> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_Rg16i        : I32EnumAttrCase<"Rg16i", 26> {
+def SPIRV_IF_Rg16i        : I32EnumAttrCase<"Rg16i", 26> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_Rg8i         : I32EnumAttrCase<"Rg8i", 27> {
+def SPIRV_IF_Rg8i         : I32EnumAttrCase<"Rg8i", 27> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_R16i         : I32EnumAttrCase<"R16i", 28> {
+def SPIRV_IF_R16i         : I32EnumAttrCase<"R16i", 28> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_R8i          : I32EnumAttrCase<"R8i", 29> {
+def SPIRV_IF_R8i          : I32EnumAttrCase<"R8i", 29> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_Rgba32ui     : I32EnumAttrCase<"Rgba32ui", 30> {
+def SPIRV_IF_Rgba32ui     : I32EnumAttrCase<"Rgba32ui", 30> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_IF_Rgba16ui     : I32EnumAttrCase<"Rgba16ui", 31> {
+def SPIRV_IF_Rgba16ui     : I32EnumAttrCase<"Rgba16ui", 31> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_IF_Rgba8ui      : I32EnumAttrCase<"Rgba8ui", 32> {
+def SPIRV_IF_Rgba8ui      : I32EnumAttrCase<"Rgba8ui", 32> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_IF_R32ui        : I32EnumAttrCase<"R32ui", 33> {
+def SPIRV_IF_R32ui        : I32EnumAttrCase<"R32ui", 33> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_IF_Rgb10a2ui    : I32EnumAttrCase<"Rgb10a2ui", 34> {
+def SPIRV_IF_Rgb10a2ui    : I32EnumAttrCase<"Rgb10a2ui", 34> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_Rg32ui       : I32EnumAttrCase<"Rg32ui", 35> {
+def SPIRV_IF_Rg32ui       : I32EnumAttrCase<"Rg32ui", 35> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_Rg16ui       : I32EnumAttrCase<"Rg16ui", 36> {
+def SPIRV_IF_Rg16ui       : I32EnumAttrCase<"Rg16ui", 36> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_Rg8ui        : I32EnumAttrCase<"Rg8ui", 37> {
+def SPIRV_IF_Rg8ui        : I32EnumAttrCase<"Rg8ui", 37> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_R16ui        : I32EnumAttrCase<"R16ui", 38> {
+def SPIRV_IF_R16ui        : I32EnumAttrCase<"R16ui", 38> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_R8ui         : I32EnumAttrCase<"R8ui", 39> {
+def SPIRV_IF_R8ui         : I32EnumAttrCase<"R8ui", 39> {
   list<Availability> availability = [
-    Capability<[SPV_C_StorageImageExtendedFormats]>
+    Capability<[SPIRV_C_StorageImageExtendedFormats]>
   ];
 }
-def SPV_IF_R64ui        : I32EnumAttrCase<"R64ui", 40> {
+def SPIRV_IF_R64ui        : I32EnumAttrCase<"R64ui", 40> {
   list<Availability> availability = [
-    Capability<[SPV_C_Int64ImageEXT]>
+    Capability<[SPIRV_C_Int64ImageEXT]>
   ];
 }
-def SPV_IF_R64i         : I32EnumAttrCase<"R64i", 41> {
+def SPIRV_IF_R64i         : I32EnumAttrCase<"R64i", 41> {
   list<Availability> availability = [
-    Capability<[SPV_C_Int64ImageEXT]>
+    Capability<[SPIRV_C_Int64ImageEXT]>
   ];
 }
 
-def SPV_ImageFormatAttr :
-    SPV_I32EnumAttr<"ImageFormat", "valid SPIR-V ImageFormat", "image_format", [
-      SPV_IF_Unknown, SPV_IF_Rgba32f, SPV_IF_Rgba16f, SPV_IF_R32f, SPV_IF_Rgba8,
-      SPV_IF_Rgba8Snorm, SPV_IF_Rg32f, SPV_IF_Rg16f, SPV_IF_R11fG11fB10f,
-      SPV_IF_R16f, SPV_IF_Rgba16, SPV_IF_Rgb10A2, SPV_IF_Rg16, SPV_IF_Rg8,
-      SPV_IF_R16, SPV_IF_R8, SPV_IF_Rgba16Snorm, SPV_IF_Rg16Snorm, SPV_IF_Rg8Snorm,
-      SPV_IF_R16Snorm, SPV_IF_R8Snorm, SPV_IF_Rgba32i, SPV_IF_Rgba16i, SPV_IF_Rgba8i,
-      SPV_IF_R32i, SPV_IF_Rg32i, SPV_IF_Rg16i, SPV_IF_Rg8i, SPV_IF_R16i, SPV_IF_R8i,
-      SPV_IF_Rgba32ui, SPV_IF_Rgba16ui, SPV_IF_Rgba8ui, SPV_IF_R32ui,
-      SPV_IF_Rgb10a2ui, SPV_IF_Rg32ui, SPV_IF_Rg16ui, SPV_IF_Rg8ui, SPV_IF_R16ui,
-      SPV_IF_R8ui, SPV_IF_R64ui, SPV_IF_R64i
+def SPIRV_ImageFormatAttr :
+    SPIRV_I32EnumAttr<"ImageFormat", "valid SPIR-V ImageFormat", "image_format", [
+      SPIRV_IF_Unknown, SPIRV_IF_Rgba32f, SPIRV_IF_Rgba16f, SPIRV_IF_R32f, SPIRV_IF_Rgba8,
+      SPIRV_IF_Rgba8Snorm, SPIRV_IF_Rg32f, SPIRV_IF_Rg16f, SPIRV_IF_R11fG11fB10f,
+      SPIRV_IF_R16f, SPIRV_IF_Rgba16, SPIRV_IF_Rgb10A2, SPIRV_IF_Rg16, SPIRV_IF_Rg8,
+      SPIRV_IF_R16, SPIRV_IF_R8, SPIRV_IF_Rgba16Snorm, SPIRV_IF_Rg16Snorm, SPIRV_IF_Rg8Snorm,
+      SPIRV_IF_R16Snorm, SPIRV_IF_R8Snorm, SPIRV_IF_Rgba32i, SPIRV_IF_Rgba16i, SPIRV_IF_Rgba8i,
+      SPIRV_IF_R32i, SPIRV_IF_Rg32i, SPIRV_IF_Rg16i, SPIRV_IF_Rg8i, SPIRV_IF_R16i, SPIRV_IF_R8i,
+      SPIRV_IF_Rgba32ui, SPIRV_IF_Rgba16ui, SPIRV_IF_Rgba8ui, SPIRV_IF_R32ui,
+      SPIRV_IF_Rgb10a2ui, SPIRV_IF_Rg32ui, SPIRV_IF_Rg16ui, SPIRV_IF_Rg8ui, SPIRV_IF_R16ui,
+      SPIRV_IF_R8ui, SPIRV_IF_R64ui, SPIRV_IF_R64i
     ]>;
 
-def SPV_IO_None               : I32BitEnumAttrCaseNone<"None">;
-def SPV_IO_Bias               : I32BitEnumAttrCaseBit<"Bias", 0> {
+def SPIRV_IO_None               : I32BitEnumAttrCaseNone<"None">;
+def SPIRV_IO_Bias               : I32BitEnumAttrCaseBit<"Bias", 0> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_IO_Lod                : I32BitEnumAttrCaseBit<"Lod", 1>;
-def SPV_IO_Grad               : I32BitEnumAttrCaseBit<"Grad", 2>;
-def SPV_IO_ConstOffset        : I32BitEnumAttrCaseBit<"ConstOffset", 3>;
-def SPV_IO_Offset             : I32BitEnumAttrCaseBit<"Offset", 4> {
+def SPIRV_IO_Lod                : I32BitEnumAttrCaseBit<"Lod", 1>;
+def SPIRV_IO_Grad               : I32BitEnumAttrCaseBit<"Grad", 2>;
+def SPIRV_IO_ConstOffset        : I32BitEnumAttrCaseBit<"ConstOffset", 3>;
+def SPIRV_IO_Offset             : I32BitEnumAttrCaseBit<"Offset", 4> {
   list<Availability> availability = [
-    Capability<[SPV_C_ImageGatherExtended]>
+    Capability<[SPIRV_C_ImageGatherExtended]>
   ];
 }
-def SPV_IO_ConstOffsets       : I32BitEnumAttrCaseBit<"ConstOffsets", 5> {
+def SPIRV_IO_ConstOffsets       : I32BitEnumAttrCaseBit<"ConstOffsets", 5> {
   list<Availability> availability = [
-    Capability<[SPV_C_ImageGatherExtended]>
+    Capability<[SPIRV_C_ImageGatherExtended]>
   ];
 }
-def SPV_IO_Sample             : I32BitEnumAttrCaseBit<"Sample", 6>;
-def SPV_IO_MinLod             : I32BitEnumAttrCaseBit<"MinLod", 7> {
+def SPIRV_IO_Sample             : I32BitEnumAttrCaseBit<"Sample", 6>;
+def SPIRV_IO_MinLod             : I32BitEnumAttrCaseBit<"MinLod", 7> {
   list<Availability> availability = [
-    Capability<[SPV_C_MinLod]>
+    Capability<[SPIRV_C_MinLod]>
   ];
 }
-def SPV_IO_MakeTexelAvailable : I32BitEnumAttrCaseBit<"MakeTexelAvailable", 8> {
+def SPIRV_IO_MakeTexelAvailable : I32BitEnumAttrCaseBit<"MakeTexelAvailable", 8> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
-    Capability<[SPV_C_VulkanMemoryModel]>
+    MinVersion<SPIRV_V_1_5>,
+    Capability<[SPIRV_C_VulkanMemoryModel]>
   ];
 }
-def SPV_IO_MakeTexelVisible   : I32BitEnumAttrCaseBit<"MakeTexelVisible", 9> {
+def SPIRV_IO_MakeTexelVisible   : I32BitEnumAttrCaseBit<"MakeTexelVisible", 9> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
-    Capability<[SPV_C_VulkanMemoryModel]>
+    MinVersion<SPIRV_V_1_5>,
+    Capability<[SPIRV_C_VulkanMemoryModel]>
   ];
 }
-def SPV_IO_NonPrivateTexel    : I32BitEnumAttrCaseBit<"NonPrivateTexel", 10> {
+def SPIRV_IO_NonPrivateTexel    : I32BitEnumAttrCaseBit<"NonPrivateTexel", 10> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
-    Capability<[SPV_C_VulkanMemoryModel]>
+    MinVersion<SPIRV_V_1_5>,
+    Capability<[SPIRV_C_VulkanMemoryModel]>
   ];
 }
-def SPV_IO_VolatileTexel      : I32BitEnumAttrCaseBit<"VolatileTexel", 11> {
+def SPIRV_IO_VolatileTexel      : I32BitEnumAttrCaseBit<"VolatileTexel", 11> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
-    Capability<[SPV_C_VulkanMemoryModel]>
+    MinVersion<SPIRV_V_1_5>,
+    Capability<[SPIRV_C_VulkanMemoryModel]>
   ];
 }
-def SPV_IO_SignExtend         : I32BitEnumAttrCaseBit<"SignExtend", 12> {
+def SPIRV_IO_SignExtend         : I32BitEnumAttrCaseBit<"SignExtend", 12> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>
+    MinVersion<SPIRV_V_1_4>
   ];
 }
-def SPV_IO_Offsets            : I32BitEnumAttrCaseBit<"Offsets", 16>;
-def SPV_IO_ZeroExtend         : I32BitEnumAttrCaseBit<"ZeroExtend", 13> {
+def SPIRV_IO_Offsets            : I32BitEnumAttrCaseBit<"Offsets", 16>;
+def SPIRV_IO_ZeroExtend         : I32BitEnumAttrCaseBit<"ZeroExtend", 13> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>
+    MinVersion<SPIRV_V_1_4>
   ];
 }
-def SPV_IO_Nontemporal        : I32BitEnumAttrCaseBit<"Nontemporal", 14> {
+def SPIRV_IO_Nontemporal        : I32BitEnumAttrCaseBit<"Nontemporal", 14> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_6>
+    MinVersion<SPIRV_V_1_6>
   ];
 }
 
-def SPV_ImageOperandsAttr :
-    SPV_BitEnumAttr<"ImageOperands", "valid SPIR-V ImageOperands", "image_operands", [
-      SPV_IO_None, SPV_IO_Bias, SPV_IO_Lod, SPV_IO_Grad, SPV_IO_ConstOffset,
-      SPV_IO_Offset, SPV_IO_ConstOffsets, SPV_IO_Sample, SPV_IO_MinLod,
-      SPV_IO_MakeTexelAvailable, SPV_IO_MakeTexelVisible, SPV_IO_NonPrivateTexel,
-      SPV_IO_VolatileTexel, SPV_IO_SignExtend, SPV_IO_Offsets, SPV_IO_ZeroExtend,
-      SPV_IO_Nontemporal
+def SPIRV_ImageOperandsAttr :
+    SPIRV_BitEnumAttr<"ImageOperands", "valid SPIR-V ImageOperands", "image_operands", [
+      SPIRV_IO_None, SPIRV_IO_Bias, SPIRV_IO_Lod, SPIRV_IO_Grad, SPIRV_IO_ConstOffset,
+      SPIRV_IO_Offset, SPIRV_IO_ConstOffsets, SPIRV_IO_Sample, SPIRV_IO_MinLod,
+      SPIRV_IO_MakeTexelAvailable, SPIRV_IO_MakeTexelVisible, SPIRV_IO_NonPrivateTexel,
+      SPIRV_IO_VolatileTexel, SPIRV_IO_SignExtend, SPIRV_IO_Offsets, SPIRV_IO_ZeroExtend,
+      SPIRV_IO_Nontemporal
     ]>;
 
-def SPV_LT_Export      : I32EnumAttrCase<"Export", 0> {
+def SPIRV_LT_Export      : I32EnumAttrCase<"Export", 0> {
   list<Availability> availability = [
-    Capability<[SPV_C_Linkage]>
+    Capability<[SPIRV_C_Linkage]>
   ];
 }
-def SPV_LT_Import      : I32EnumAttrCase<"Import", 1> {
+def SPIRV_LT_Import      : I32EnumAttrCase<"Import", 1> {
   list<Availability> availability = [
-    Capability<[SPV_C_Linkage]>
+    Capability<[SPIRV_C_Linkage]>
   ];
 }
-def SPV_LT_LinkOnceODR : I32EnumAttrCase<"LinkOnceODR", 2> {
+def SPIRV_LT_LinkOnceODR : I32EnumAttrCase<"LinkOnceODR", 2> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_linkonce_odr]>,
-    Capability<[SPV_C_Linkage]>
+    Extension<[SPIRV_KHR_linkonce_odr]>,
+    Capability<[SPIRV_C_Linkage]>
   ];
 }
 
-def SPV_LinkageTypeAttr :
-    SPV_I32EnumAttr<"LinkageType", "valid SPIR-V LinkageType", "linkage_type", [
-      SPV_LT_Export, SPV_LT_Import, SPV_LT_LinkOnceODR
+def SPIRV_LinkageTypeAttr :
+    SPIRV_I32EnumAttr<"LinkageType", "valid SPIR-V LinkageType", "linkage_type", [
+      SPIRV_LT_Export, SPIRV_LT_Import, SPIRV_LT_LinkOnceODR
     ]>;
 
-def SPV_LC_None                      : I32BitEnumAttrCaseNone<"None">;
-def SPV_LC_Unroll                    : I32BitEnumAttrCaseBit<"Unroll", 0>;
-def SPV_LC_DontUnroll                : I32BitEnumAttrCaseBit<"DontUnroll", 1>;
-def SPV_LC_DependencyInfinite        : I32BitEnumAttrCaseBit<"DependencyInfinite", 2> {
+def SPIRV_LC_None                      : I32BitEnumAttrCaseNone<"None">;
+def SPIRV_LC_Unroll                    : I32BitEnumAttrCaseBit<"Unroll", 0>;
+def SPIRV_LC_DontUnroll                : I32BitEnumAttrCaseBit<"DontUnroll", 1>;
+def SPIRV_LC_DependencyInfinite        : I32BitEnumAttrCaseBit<"DependencyInfinite", 2> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_1>
+    MinVersion<SPIRV_V_1_1>
   ];
 }
-def SPV_LC_DependencyLength          : I32BitEnumAttrCaseBit<"DependencyLength", 3> {
+def SPIRV_LC_DependencyLength          : I32BitEnumAttrCaseBit<"DependencyLength", 3> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_1>
+    MinVersion<SPIRV_V_1_1>
   ];
 }
-def SPV_LC_MinIterations             : I32BitEnumAttrCaseBit<"MinIterations", 4> {
+def SPIRV_LC_MinIterations             : I32BitEnumAttrCaseBit<"MinIterations", 4> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>
+    MinVersion<SPIRV_V_1_4>
   ];
 }
-def SPV_LC_MaxIterations             : I32BitEnumAttrCaseBit<"MaxIterations", 5> {
+def SPIRV_LC_MaxIterations             : I32BitEnumAttrCaseBit<"MaxIterations", 5> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>
+    MinVersion<SPIRV_V_1_4>
   ];
 }
-def SPV_LC_IterationMultiple         : I32BitEnumAttrCaseBit<"IterationMultiple", 6> {
+def SPIRV_LC_IterationMultiple         : I32BitEnumAttrCaseBit<"IterationMultiple", 6> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>
+    MinVersion<SPIRV_V_1_4>
   ];
 }
-def SPV_LC_PeelCount                 : I32BitEnumAttrCaseBit<"PeelCount", 7> {
+def SPIRV_LC_PeelCount                 : I32BitEnumAttrCaseBit<"PeelCount", 7> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>
+    MinVersion<SPIRV_V_1_4>
   ];
 }
-def SPV_LC_PartialCount              : I32BitEnumAttrCaseBit<"PartialCount", 8> {
+def SPIRV_LC_PartialCount              : I32BitEnumAttrCaseBit<"PartialCount", 8> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_4>
+    MinVersion<SPIRV_V_1_4>
   ];
 }
-def SPV_LC_InitiationIntervalINTEL   : I32BitEnumAttrCaseBit<"InitiationIntervalINTEL", 16> {
+def SPIRV_LC_InitiationIntervalINTEL   : I32BitEnumAttrCaseBit<"InitiationIntervalINTEL", 16> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_loop_controls]>,
-    Capability<[SPV_C_FPGALoopControlsINTEL]>
+    Extension<[SPIRV_INTEL_fpga_loop_controls]>,
+    Capability<[SPIRV_C_FPGALoopControlsINTEL]>
   ];
 }
-def SPV_LC_LoopCoalesceINTEL         : I32BitEnumAttrCaseBit<"LoopCoalesceINTEL", 20> {
+def SPIRV_LC_LoopCoalesceINTEL         : I32BitEnumAttrCaseBit<"LoopCoalesceINTEL", 20> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_loop_controls]>,
-    Capability<[SPV_C_FPGALoopControlsINTEL]>
+    Extension<[SPIRV_INTEL_fpga_loop_controls]>,
+    Capability<[SPIRV_C_FPGALoopControlsINTEL]>
   ];
 }
-def SPV_LC_MaxConcurrencyINTEL       : I32BitEnumAttrCaseBit<"MaxConcurrencyINTEL", 17> {
+def SPIRV_LC_MaxConcurrencyINTEL       : I32BitEnumAttrCaseBit<"MaxConcurrencyINTEL", 17> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_loop_controls]>,
-    Capability<[SPV_C_FPGALoopControlsINTEL]>
+    Extension<[SPIRV_INTEL_fpga_loop_controls]>,
+    Capability<[SPIRV_C_FPGALoopControlsINTEL]>
   ];
 }
-def SPV_LC_MaxInterleavingINTEL      : I32BitEnumAttrCaseBit<"MaxInterleavingINTEL", 21> {
+def SPIRV_LC_MaxInterleavingINTEL      : I32BitEnumAttrCaseBit<"MaxInterleavingINTEL", 21> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_loop_controls]>,
-    Capability<[SPV_C_FPGALoopControlsINTEL]>
+    Extension<[SPIRV_INTEL_fpga_loop_controls]>,
+    Capability<[SPIRV_C_FPGALoopControlsINTEL]>
   ];
 }
-def SPV_LC_DependencyArrayINTEL      : I32BitEnumAttrCaseBit<"DependencyArrayINTEL", 18> {
+def SPIRV_LC_DependencyArrayINTEL      : I32BitEnumAttrCaseBit<"DependencyArrayINTEL", 18> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_loop_controls]>,
-    Capability<[SPV_C_FPGALoopControlsINTEL]>
+    Extension<[SPIRV_INTEL_fpga_loop_controls]>,
+    Capability<[SPIRV_C_FPGALoopControlsINTEL]>
   ];
 }
-def SPV_LC_SpeculatedIterationsINTEL : I32BitEnumAttrCaseBit<"SpeculatedIterationsINTEL", 22> {
+def SPIRV_LC_SpeculatedIterationsINTEL : I32BitEnumAttrCaseBit<"SpeculatedIterationsINTEL", 22> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_loop_controls]>,
-    Capability<[SPV_C_FPGALoopControlsINTEL]>
+    Extension<[SPIRV_INTEL_fpga_loop_controls]>,
+    Capability<[SPIRV_C_FPGALoopControlsINTEL]>
   ];
 }
-def SPV_LC_PipelineEnableINTEL       : I32BitEnumAttrCaseBit<"PipelineEnableINTEL", 19> {
+def SPIRV_LC_PipelineEnableINTEL       : I32BitEnumAttrCaseBit<"PipelineEnableINTEL", 19> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_loop_controls]>,
-    Capability<[SPV_C_FPGALoopControlsINTEL]>
+    Extension<[SPIRV_INTEL_fpga_loop_controls]>,
+    Capability<[SPIRV_C_FPGALoopControlsINTEL]>
   ];
 }
-def SPV_LC_NoFusionINTEL             : I32BitEnumAttrCaseBit<"NoFusionINTEL", 23> {
+def SPIRV_LC_NoFusionINTEL             : I32BitEnumAttrCaseBit<"NoFusionINTEL", 23> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_fpga_loop_controls]>,
-    Capability<[SPV_C_FPGALoopControlsINTEL]>
+    Extension<[SPIRV_INTEL_fpga_loop_controls]>,
+    Capability<[SPIRV_C_FPGALoopControlsINTEL]>
   ];
 }
 
-def SPV_LoopControlAttr :
-    SPV_BitEnumAttr<"LoopControl", "valid SPIR-V LoopControl", "loop_control", [
-      SPV_LC_None, SPV_LC_Unroll, SPV_LC_DontUnroll, SPV_LC_DependencyInfinite,
-      SPV_LC_DependencyLength, SPV_LC_MinIterations, SPV_LC_MaxIterations,
-      SPV_LC_IterationMultiple, SPV_LC_PeelCount, SPV_LC_PartialCount,
-      SPV_LC_InitiationIntervalINTEL, SPV_LC_LoopCoalesceINTEL,
-      SPV_LC_MaxConcurrencyINTEL, SPV_LC_MaxInterleavingINTEL,
-      SPV_LC_DependencyArrayINTEL, SPV_LC_SpeculatedIterationsINTEL,
-      SPV_LC_PipelineEnableINTEL, SPV_LC_NoFusionINTEL
+def SPIRV_LoopControlAttr :
+    SPIRV_BitEnumAttr<"LoopControl", "valid SPIR-V LoopControl", "loop_control", [
+      SPIRV_LC_None, SPIRV_LC_Unroll, SPIRV_LC_DontUnroll, SPIRV_LC_DependencyInfinite,
+      SPIRV_LC_DependencyLength, SPIRV_LC_MinIterations, SPIRV_LC_MaxIterations,
+      SPIRV_LC_IterationMultiple, SPIRV_LC_PeelCount, SPIRV_LC_PartialCount,
+      SPIRV_LC_InitiationIntervalINTEL, SPIRV_LC_LoopCoalesceINTEL,
+      SPIRV_LC_MaxConcurrencyINTEL, SPIRV_LC_MaxInterleavingINTEL,
+      SPIRV_LC_DependencyArrayINTEL, SPIRV_LC_SpeculatedIterationsINTEL,
+      SPIRV_LC_PipelineEnableINTEL, SPIRV_LC_NoFusionINTEL
     ]>;
 
-def SPV_MA_None                 : I32BitEnumAttrCaseNone<"None">;
-def SPV_MA_Volatile             : I32BitEnumAttrCaseBit<"Volatile", 0>;
-def SPV_MA_Aligned              : I32BitEnumAttrCaseBit<"Aligned", 1>;
-def SPV_MA_Nontemporal          : I32BitEnumAttrCaseBit<"Nontemporal", 2>;
-def SPV_MA_MakePointerAvailable : I32BitEnumAttrCaseBit<"MakePointerAvailable", 3> {
+def SPIRV_MA_None                 : I32BitEnumAttrCaseNone<"None">;
+def SPIRV_MA_Volatile             : I32BitEnumAttrCaseBit<"Volatile", 0>;
+def SPIRV_MA_Aligned              : I32BitEnumAttrCaseBit<"Aligned", 1>;
+def SPIRV_MA_Nontemporal          : I32BitEnumAttrCaseBit<"Nontemporal", 2>;
+def SPIRV_MA_MakePointerAvailable : I32BitEnumAttrCaseBit<"MakePointerAvailable", 3> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
-    Capability<[SPV_C_VulkanMemoryModel]>
+    MinVersion<SPIRV_V_1_5>,
+    Capability<[SPIRV_C_VulkanMemoryModel]>
   ];
 }
-def SPV_MA_MakePointerVisible   : I32BitEnumAttrCaseBit<"MakePointerVisible", 4> {
+def SPIRV_MA_MakePointerVisible   : I32BitEnumAttrCaseBit<"MakePointerVisible", 4> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
-    Capability<[SPV_C_VulkanMemoryModel]>
+    MinVersion<SPIRV_V_1_5>,
+    Capability<[SPIRV_C_VulkanMemoryModel]>
   ];
 }
-def SPV_MA_NonPrivatePointer    : I32BitEnumAttrCaseBit<"NonPrivatePointer", 5> {
+def SPIRV_MA_NonPrivatePointer    : I32BitEnumAttrCaseBit<"NonPrivatePointer", 5> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
-    Capability<[SPV_C_VulkanMemoryModel]>
+    MinVersion<SPIRV_V_1_5>,
+    Capability<[SPIRV_C_VulkanMemoryModel]>
   ];
 }
-def SPV_MA_AliasScopeINTELMask  : I32BitEnumAttrCaseBit<"AliasScopeINTELMask", 16> {
+def SPIRV_MA_AliasScopeINTELMask  : I32BitEnumAttrCaseBit<"AliasScopeINTELMask", 16> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_memory_access_aliasing]>,
-    Capability<[SPV_C_MemoryAccessAliasingINTEL]>
+    Extension<[SPIRV_INTEL_memory_access_aliasing]>,
+    Capability<[SPIRV_C_MemoryAccessAliasingINTEL]>
   ];
 }
-def SPV_MA_NoAliasINTELMask     : I32BitEnumAttrCaseBit<"NoAliasINTELMask", 17> {
+def SPIRV_MA_NoAliasINTELMask     : I32BitEnumAttrCaseBit<"NoAliasINTELMask", 17> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_memory_access_aliasing]>,
-    Capability<[SPV_C_MemoryAccessAliasingINTEL]>
+    Extension<[SPIRV_INTEL_memory_access_aliasing]>,
+    Capability<[SPIRV_C_MemoryAccessAliasingINTEL]>
   ];
 }
 
-def SPV_MemoryAccessAttr :
-    SPV_BitEnumAttr<"MemoryAccess", "valid SPIR-V MemoryAccess", "memory_access", [
-      SPV_MA_None, SPV_MA_Volatile, SPV_MA_Aligned, SPV_MA_Nontemporal,
-      SPV_MA_MakePointerAvailable, SPV_MA_MakePointerVisible,
-      SPV_MA_NonPrivatePointer, SPV_MA_AliasScopeINTELMask, SPV_MA_NoAliasINTELMask
+def SPIRV_MemoryAccessAttr :
+    SPIRV_BitEnumAttr<"MemoryAccess", "valid SPIR-V MemoryAccess", "memory_access", [
+      SPIRV_MA_None, SPIRV_MA_Volatile, SPIRV_MA_Aligned, SPIRV_MA_Nontemporal,
+      SPIRV_MA_MakePointerAvailable, SPIRV_MA_MakePointerVisible,
+      SPIRV_MA_NonPrivatePointer, SPIRV_MA_AliasScopeINTELMask, SPIRV_MA_NoAliasINTELMask
     ]>;
 
-def SPV_MM_Simple  : I32EnumAttrCase<"Simple", 0> {
+def SPIRV_MM_Simple  : I32EnumAttrCase<"Simple", 0> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_MM_GLSL450 : I32EnumAttrCase<"GLSL450", 1> {
+def SPIRV_MM_GLSL450 : I32EnumAttrCase<"GLSL450", 1> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_MM_OpenCL  : I32EnumAttrCase<"OpenCL", 2> {
+def SPIRV_MM_OpenCL  : I32EnumAttrCase<"OpenCL", 2> {
   list<Availability> availability = [
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
-def SPV_MM_Vulkan  : I32EnumAttrCase<"Vulkan", 3> {
+def SPIRV_MM_Vulkan  : I32EnumAttrCase<"Vulkan", 3> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_vulkan_memory_model]>,
-    Capability<[SPV_C_VulkanMemoryModel]>
+    Extension<[SPIRV_KHR_vulkan_memory_model]>,
+    Capability<[SPIRV_C_VulkanMemoryModel]>
   ];
 }
 
-def SPV_MemoryModelAttr :
-    SPV_I32EnumAttr<"MemoryModel", "valid SPIR-V MemoryModel", "memory_model", [
-      SPV_MM_Simple, SPV_MM_GLSL450, SPV_MM_OpenCL, SPV_MM_Vulkan
+def SPIRV_MemoryModelAttr :
+    SPIRV_I32EnumAttr<"MemoryModel", "valid SPIR-V MemoryModel", "memory_model", [
+      SPIRV_MM_Simple, SPIRV_MM_GLSL450, SPIRV_MM_OpenCL, SPIRV_MM_Vulkan
     ]>;
 
-def SPV_MS_None                   : I32BitEnumAttrCaseNone<"None">;
-def SPV_MS_Acquire                : I32BitEnumAttrCaseBit<"Acquire", 1>;
-def SPV_MS_Release                : I32BitEnumAttrCaseBit<"Release", 2>;
-def SPV_MS_AcquireRelease         : I32BitEnumAttrCaseBit<"AcquireRelease", 3>;
-def SPV_MS_SequentiallyConsistent : I32BitEnumAttrCaseBit<"SequentiallyConsistent", 4>;
-def SPV_MS_UniformMemory          : I32BitEnumAttrCaseBit<"UniformMemory", 6> {
+def SPIRV_MS_None                   : I32BitEnumAttrCaseNone<"None">;
+def SPIRV_MS_Acquire                : I32BitEnumAttrCaseBit<"Acquire", 1>;
+def SPIRV_MS_Release                : I32BitEnumAttrCaseBit<"Release", 2>;
+def SPIRV_MS_AcquireRelease         : I32BitEnumAttrCaseBit<"AcquireRelease", 3>;
+def SPIRV_MS_SequentiallyConsistent : I32BitEnumAttrCaseBit<"SequentiallyConsistent", 4>;
+def SPIRV_MS_UniformMemory          : I32BitEnumAttrCaseBit<"UniformMemory", 6> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_MS_SubgroupMemory         : I32BitEnumAttrCaseBit<"SubgroupMemory", 7>;
-def SPV_MS_WorkgroupMemory        : I32BitEnumAttrCaseBit<"WorkgroupMemory", 8>;
-def SPV_MS_CrossWorkgroupMemory   : I32BitEnumAttrCaseBit<"CrossWorkgroupMemory", 9>;
-def SPV_MS_AtomicCounterMemory    : I32BitEnumAttrCaseBit<"AtomicCounterMemory", 10> {
+def SPIRV_MS_SubgroupMemory         : I32BitEnumAttrCaseBit<"SubgroupMemory", 7>;
+def SPIRV_MS_WorkgroupMemory        : I32BitEnumAttrCaseBit<"WorkgroupMemory", 8>;
+def SPIRV_MS_CrossWorkgroupMemory   : I32BitEnumAttrCaseBit<"CrossWorkgroupMemory", 9>;
+def SPIRV_MS_AtomicCounterMemory    : I32BitEnumAttrCaseBit<"AtomicCounterMemory", 10> {
   list<Availability> availability = [
-    Capability<[SPV_C_AtomicStorage]>
+    Capability<[SPIRV_C_AtomicStorage]>
   ];
 }
-def SPV_MS_ImageMemory            : I32BitEnumAttrCaseBit<"ImageMemory", 11>;
-def SPV_MS_OutputMemory           : I32BitEnumAttrCaseBit<"OutputMemory", 12> {
+def SPIRV_MS_ImageMemory            : I32BitEnumAttrCaseBit<"ImageMemory", 11>;
+def SPIRV_MS_OutputMemory           : I32BitEnumAttrCaseBit<"OutputMemory", 12> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
-    Capability<[SPV_C_VulkanMemoryModel]>
+    MinVersion<SPIRV_V_1_5>,
+    Capability<[SPIRV_C_VulkanMemoryModel]>
   ];
 }
-def SPV_MS_MakeAvailable          : I32BitEnumAttrCaseBit<"MakeAvailable", 13> {
+def SPIRV_MS_MakeAvailable          : I32BitEnumAttrCaseBit<"MakeAvailable", 13> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
-    Capability<[SPV_C_VulkanMemoryModel]>
+    MinVersion<SPIRV_V_1_5>,
+    Capability<[SPIRV_C_VulkanMemoryModel]>
   ];
 }
-def SPV_MS_MakeVisible            : I32BitEnumAttrCaseBit<"MakeVisible", 14> {
+def SPIRV_MS_MakeVisible            : I32BitEnumAttrCaseBit<"MakeVisible", 14> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
-    Capability<[SPV_C_VulkanMemoryModel]>
+    MinVersion<SPIRV_V_1_5>,
+    Capability<[SPIRV_C_VulkanMemoryModel]>
   ];
 }
-def SPV_MS_Volatile               : I32BitEnumAttrCaseBit<"Volatile", 15> {
+def SPIRV_MS_Volatile               : I32BitEnumAttrCaseBit<"Volatile", 15> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_vulkan_memory_model]>,
-    Capability<[SPV_C_VulkanMemoryModel]>
+    Extension<[SPIRV_KHR_vulkan_memory_model]>,
+    Capability<[SPIRV_C_VulkanMemoryModel]>
   ];
 }
 
-def SPV_MemorySemanticsAttr :
-    SPV_BitEnumAttr<"MemorySemantics", "valid SPIR-V MemorySemantics", "memory_semantics", [
-      SPV_MS_None, SPV_MS_Acquire, SPV_MS_Release, SPV_MS_AcquireRelease,
-      SPV_MS_SequentiallyConsistent, SPV_MS_UniformMemory, SPV_MS_SubgroupMemory,
-      SPV_MS_WorkgroupMemory, SPV_MS_CrossWorkgroupMemory,
-      SPV_MS_AtomicCounterMemory, SPV_MS_ImageMemory, SPV_MS_OutputMemory,
-      SPV_MS_MakeAvailable, SPV_MS_MakeVisible, SPV_MS_Volatile
+def SPIRV_MemorySemanticsAttr :
+    SPIRV_BitEnumAttr<"MemorySemantics", "valid SPIR-V MemorySemantics", "memory_semantics", [
+      SPIRV_MS_None, SPIRV_MS_Acquire, SPIRV_MS_Release, SPIRV_MS_AcquireRelease,
+      SPIRV_MS_SequentiallyConsistent, SPIRV_MS_UniformMemory, SPIRV_MS_SubgroupMemory,
+      SPIRV_MS_WorkgroupMemory, SPIRV_MS_CrossWorkgroupMemory,
+      SPIRV_MS_AtomicCounterMemory, SPIRV_MS_ImageMemory, SPIRV_MS_OutputMemory,
+      SPIRV_MS_MakeAvailable, SPIRV_MS_MakeVisible, SPIRV_MS_Volatile
     ]>;
 
-def SPV_S_CrossDevice   : I32EnumAttrCase<"CrossDevice", 0>;
-def SPV_S_Device        : I32EnumAttrCase<"Device", 1>;
-def SPV_S_Workgroup     : I32EnumAttrCase<"Workgroup", 2>;
-def SPV_S_Subgroup      : I32EnumAttrCase<"Subgroup", 3>;
-def SPV_S_Invocation    : I32EnumAttrCase<"Invocation", 4>;
-def SPV_S_QueueFamily   : I32EnumAttrCase<"QueueFamily", 5> {
+def SPIRV_S_CrossDevice   : I32EnumAttrCase<"CrossDevice", 0>;
+def SPIRV_S_Device        : I32EnumAttrCase<"Device", 1>;
+def SPIRV_S_Workgroup     : I32EnumAttrCase<"Workgroup", 2>;
+def SPIRV_S_Subgroup      : I32EnumAttrCase<"Subgroup", 3>;
+def SPIRV_S_Invocation    : I32EnumAttrCase<"Invocation", 4>;
+def SPIRV_S_QueueFamily   : I32EnumAttrCase<"QueueFamily", 5> {
   list<Availability> availability = [
-    MinVersion<SPV_V_1_5>,
-    Capability<[SPV_C_VulkanMemoryModel]>
+    MinVersion<SPIRV_V_1_5>,
+    Capability<[SPIRV_C_VulkanMemoryModel]>
   ];
 }
-def SPV_S_ShaderCallKHR : I32EnumAttrCase<"ShaderCallKHR", 6> {
+def SPIRV_S_ShaderCallKHR : I32EnumAttrCase<"ShaderCallKHR", 6> {
   list<Availability> availability = [
-    Capability<[SPV_C_RayTracingKHR]>
+    Capability<[SPIRV_C_RayTracingKHR]>
   ];
 }
 
-def SPV_ScopeAttr :
-    SPV_I32EnumAttr<"Scope", "valid SPIR-V Scope", "scope", [
-      SPV_S_CrossDevice, SPV_S_Device, SPV_S_Workgroup, SPV_S_Subgroup,
-      SPV_S_Invocation, SPV_S_QueueFamily, SPV_S_ShaderCallKHR
+def SPIRV_ScopeAttr :
+    SPIRV_I32EnumAttr<"Scope", "valid SPIR-V Scope", "scope", [
+      SPIRV_S_CrossDevice, SPIRV_S_Device, SPIRV_S_Workgroup, SPIRV_S_Subgroup,
+      SPIRV_S_Invocation, SPIRV_S_QueueFamily, SPIRV_S_ShaderCallKHR
     ]>;
 
-def SPV_SC_None        : I32BitEnumAttrCaseNone<"None">;
-def SPV_SC_Flatten     : I32BitEnumAttrCaseBit<"Flatten", 0>;
-def SPV_SC_DontFlatten : I32BitEnumAttrCaseBit<"DontFlatten", 1>;
-
-def SPV_SelectionControlAttr :
-    SPV_BitEnumAttr<"SelectionControl", "valid SPIR-V SelectionControl", "selection_control", [
-      SPV_SC_None, SPV_SC_Flatten, SPV_SC_DontFlatten
+def SPIRV_SC_None        : I32BitEnumAttrCaseNone<"None">;
+def SPIRV_SC_Flatten     : I32BitEnumAttrCaseBit<"Flatten", 0>;
+def SPIRV_SC_DontFlatten : I32BitEnumAttrCaseBit<"DontFlatten", 1>;
+
+def SPIRV_SelectionControlAttr :
+    SPIRV_BitEnumAttr<"SelectionControl", "valid SPIR-V SelectionControl", "selection_control", [
+      SPIRV_SC_None, SPIRV_SC_Flatten, SPIRV_SC_DontFlatten
     ]>;
 
-def SPV_SC_UniformConstant         : I32EnumAttrCase<"UniformConstant", 0>;
-def SPV_SC_Input                   : I32EnumAttrCase<"Input", 1>;
-def SPV_SC_Uniform                 : I32EnumAttrCase<"Uniform", 2> {
+def SPIRV_SC_UniformConstant         : I32EnumAttrCase<"UniformConstant", 0>;
+def SPIRV_SC_Input                   : I32EnumAttrCase<"Input", 1>;
+def SPIRV_SC_Uniform                 : I32EnumAttrCase<"Uniform", 2> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_SC_Output                  : I32EnumAttrCase<"Output", 3> {
+def SPIRV_SC_Output                  : I32EnumAttrCase<"Output", 3> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_SC_Workgroup               : I32EnumAttrCase<"Workgroup", 4>;
-def SPV_SC_CrossWorkgroup          : I32EnumAttrCase<"CrossWorkgroup", 5>;
-def SPV_SC_Private                 : I32EnumAttrCase<"Private", 6> {
+def SPIRV_SC_Workgroup               : I32EnumAttrCase<"Workgroup", 4>;
+def SPIRV_SC_CrossWorkgroup          : I32EnumAttrCase<"CrossWorkgroup", 5>;
+def SPIRV_SC_Private                 : I32EnumAttrCase<"Private", 6> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader, SPV_C_VectorComputeINTEL]>
+    Capability<[SPIRV_C_Shader, SPIRV_C_VectorComputeINTEL]>
   ];
 }
-def SPV_SC_Function                : I32EnumAttrCase<"Function", 7>;
-def SPV_SC_Generic                 : I32EnumAttrCase<"Generic", 8> {
+def SPIRV_SC_Function                : I32EnumAttrCase<"Function", 7>;
+def SPIRV_SC_Generic                 : I32EnumAttrCase<"Generic", 8> {
   list<Availability> availability = [
-    Capability<[SPV_C_GenericPointer]>
+    Capability<[SPIRV_C_GenericPointer]>
   ];
 }
-def SPV_SC_PushConstant            : I32EnumAttrCase<"PushConstant", 9> {
+def SPIRV_SC_PushConstant            : I32EnumAttrCase<"PushConstant", 9> {
   list<Availability> availability = [
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_SC_AtomicCounter           : I32EnumAttrCase<"AtomicCounter", 10> {
+def SPIRV_SC_AtomicCounter           : I32EnumAttrCase<"AtomicCounter", 10> {
   list<Availability> availability = [
-    Capability<[SPV_C_AtomicStorage]>
+    Capability<[SPIRV_C_AtomicStorage]>
   ];
 }
-def SPV_SC_Image                   : I32EnumAttrCase<"Image", 11>;
-def SPV_SC_StorageBuffer           : I32EnumAttrCase<"StorageBuffer", 12> {
+def SPIRV_SC_Image                   : I32EnumAttrCase<"Image", 11>;
+def SPIRV_SC_StorageBuffer           : I32EnumAttrCase<"StorageBuffer", 12> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_storage_buffer_storage_class, SPV_KHR_variable_pointers]>,
-    Capability<[SPV_C_Shader]>
+    Extension<[SPIRV_KHR_storage_buffer_storage_class, SPIRV_KHR_variable_pointers]>,
+    Capability<[SPIRV_C_Shader]>
   ];
 }
-def SPV_SC_CallableDataKHR         : I32EnumAttrCase<"CallableDataKHR", 5328> {
+def SPIRV_SC_CallableDataKHR         : I32EnumAttrCase<"CallableDataKHR", 5328> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>,
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Extension<[SPIRV_KHR_ray_tracing, SPIRV_NV_ray_tracing]>,
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_SC_IncomingCallableDataKHR : I32EnumAttrCase<"IncomingCallableDataKHR", 5329> {
+def SPIRV_SC_IncomingCallableDataKHR : I32EnumAttrCase<"IncomingCallableDataKHR", 5329> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>,
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Extension<[SPIRV_KHR_ray_tracing, SPIRV_NV_ray_tracing]>,
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_SC_RayPayloadKHR           : I32EnumAttrCase<"RayPayloadKHR", 5338> {
+def SPIRV_SC_RayPayloadKHR           : I32EnumAttrCase<"RayPayloadKHR", 5338> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>,
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Extension<[SPIRV_KHR_ray_tracing, SPIRV_NV_ray_tracing]>,
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_SC_HitAttributeKHR         : I32EnumAttrCase<"HitAttributeKHR", 5339> {
+def SPIRV_SC_HitAttributeKHR         : I32EnumAttrCase<"HitAttributeKHR", 5339> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>,
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Extension<[SPIRV_KHR_ray_tracing, SPIRV_NV_ray_tracing]>,
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_SC_IncomingRayPayloadKHR   : I32EnumAttrCase<"IncomingRayPayloadKHR", 5342> {
+def SPIRV_SC_IncomingRayPayloadKHR   : I32EnumAttrCase<"IncomingRayPayloadKHR", 5342> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>,
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Extension<[SPIRV_KHR_ray_tracing, SPIRV_NV_ray_tracing]>,
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_SC_ShaderRecordBufferKHR   : I32EnumAttrCase<"ShaderRecordBufferKHR", 5343> {
+def SPIRV_SC_ShaderRecordBufferKHR   : I32EnumAttrCase<"ShaderRecordBufferKHR", 5343> {
   list<Availability> availability = [
-    Extension<[SPV_KHR_ray_tracing, SPV_NV_ray_tracing]>,
-    Capability<[SPV_C_RayTracingKHR, SPV_C_RayTracingNV]>
+    Extension<[SPIRV_KHR_ray_tracing, SPIRV_NV_ray_tracing]>,
+    Capability<[SPIRV_C_RayTracingKHR, SPIRV_C_RayTracingNV]>
   ];
 }
-def SPV_SC_PhysicalStorageBuffer   : I32EnumAttrCase<"PhysicalStorageBuffer", 5349> {
+def SPIRV_SC_PhysicalStorageBuffer   : I32EnumAttrCase<"PhysicalStorageBuffer", 5349> {
   list<Availability> availability = [
-    Extension<[SPV_EXT_physical_storage_buffer, SPV_KHR_physical_storage_buffer]>,
-    Capability<[SPV_C_PhysicalStorageBufferAddresses]>
+    Extension<[SPIRV_EXT_physical_storage_buffer, SPIRV_KHR_physical_storage_buffer]>,
+    Capability<[SPIRV_C_PhysicalStorageBufferAddresses]>
   ];
 }
-def SPV_SC_CodeSectionINTEL        : I32EnumAttrCase<"CodeSectionINTEL", 5605> {
+def SPIRV_SC_CodeSectionINTEL        : I32EnumAttrCase<"CodeSectionINTEL", 5605> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_function_pointers]>,
-    Capability<[SPV_C_FunctionPointersINTEL]>
+    Extension<[SPIRV_INTEL_function_pointers]>,
+    Capability<[SPIRV_C_FunctionPointersINTEL]>
   ];
 }
-def SPV_SC_DeviceOnlyINTEL         : I32EnumAttrCase<"DeviceOnlyINTEL", 5936> {
+def SPIRV_SC_DeviceOnlyINTEL         : I32EnumAttrCase<"DeviceOnlyINTEL", 5936> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_usm_storage_classes]>,
-    Capability<[SPV_C_USMStorageClassesINTEL]>
+    Extension<[SPIRV_INTEL_usm_storage_classes]>,
+    Capability<[SPIRV_C_USMStorageClassesINTEL]>
   ];
 }
-def SPV_SC_HostOnlyINTEL           : I32EnumAttrCase<"HostOnlyINTEL", 5937> {
+def SPIRV_SC_HostOnlyINTEL           : I32EnumAttrCase<"HostOnlyINTEL", 5937> {
   list<Availability> availability = [
-    Extension<[SPV_INTEL_usm_storage_classes]>,
-    Capability<[SPV_C_USMStorageClassesINTEL]>
+    Extension<[SPIRV_INTEL_usm_storage_classes]>,
+    Capability<[SPIRV_C_USMStorageClassesINTEL]>
   ];
 }
 
-def SPV_StorageClassAttr :
-    SPV_I32EnumAttr<"StorageClass", "valid SPIR-V StorageClass", "storage_class", [
-      SPV_SC_UniformConstant, SPV_SC_Input, SPV_SC_Uniform, SPV_SC_Output,
-      SPV_SC_Workgroup, SPV_SC_CrossWorkgroup, SPV_SC_Private, SPV_SC_Function,
-      SPV_SC_Generic, SPV_SC_PushConstant, SPV_SC_AtomicCounter, SPV_SC_Image,
-      SPV_SC_StorageBuffer, SPV_SC_CallableDataKHR, SPV_SC_IncomingCallableDataKHR,
-      SPV_SC_RayPayloadKHR, SPV_SC_HitAttributeKHR, SPV_SC_IncomingRayPayloadKHR,
-      SPV_SC_ShaderRecordBufferKHR, SPV_SC_PhysicalStorageBuffer,
-      SPV_SC_CodeSectionINTEL, SPV_SC_DeviceOnlyINTEL, SPV_SC_HostOnlyINTEL
+def SPIRV_StorageClassAttr :
+    SPIRV_I32EnumAttr<"StorageClass", "valid SPIR-V StorageClass", "storage_class", [
+      SPIRV_SC_UniformConstant, SPIRV_SC_Input, SPIRV_SC_Uniform, SPIRV_SC_Output,
+      SPIRV_SC_Workgroup, SPIRV_SC_CrossWorkgroup, SPIRV_SC_Private, SPIRV_SC_Function,
+      SPIRV_SC_Generic, SPIRV_SC_PushConstant, SPIRV_SC_AtomicCounter, SPIRV_SC_Image,
+      SPIRV_SC_StorageBuffer, SPIRV_SC_CallableDataKHR, SPIRV_SC_IncomingCallableDataKHR,
+      SPIRV_SC_RayPayloadKHR, SPIRV_SC_HitAttributeKHR, SPIRV_SC_IncomingRayPayloadKHR,
+      SPIRV_SC_ShaderRecordBufferKHR, SPIRV_SC_PhysicalStorageBuffer,
+      SPIRV_SC_CodeSectionINTEL, SPIRV_SC_DeviceOnlyINTEL, SPIRV_SC_HostOnlyINTEL
     ]>;
 
 // End enum section. Generated from SPIR-V spec; DO NOT MODIFY!
 
 // Enums added manually that are not part of SPIR-V spec
 
-def SPV_IDI_NoDepth      : I32EnumAttrCase<"NoDepth", 0>;
-def SPV_IDI_IsDepth      : I32EnumAttrCase<"IsDepth", 1>;
-def SPV_IDI_DepthUnknown : I32EnumAttrCase<"DepthUnknown", 2>;
+def SPIRV_IDI_NoDepth      : I32EnumAttrCase<"NoDepth", 0>;
+def SPIRV_IDI_IsDepth      : I32EnumAttrCase<"IsDepth", 1>;
+def SPIRV_IDI_DepthUnknown : I32EnumAttrCase<"DepthUnknown", 2>;
 
-def SPV_DepthAttr : SPV_I32EnumAttr<
+def SPIRV_DepthAttr : SPIRV_I32EnumAttr<
   "ImageDepthInfo", "valid SPIR-V Image Depth specification",
-  "image_depth_info", [SPV_IDI_NoDepth, SPV_IDI_IsDepth, SPV_IDI_DepthUnknown]>;
+  "image_depth_info", [SPIRV_IDI_NoDepth, SPIRV_IDI_IsDepth, SPIRV_IDI_DepthUnknown]>;
 
-def SPV_IAI_NonArrayed : I32EnumAttrCase<"NonArrayed", 0>;
-def SPV_IAI_Arrayed    : I32EnumAttrCase<"Arrayed", 1>;
+def SPIRV_IAI_NonArrayed : I32EnumAttrCase<"NonArrayed", 0>;
+def SPIRV_IAI_Arrayed    : I32EnumAttrCase<"Arrayed", 1>;
 
-def SPV_ArrayedAttr : SPV_I32EnumAttr<
+def SPIRV_ArrayedAttr : SPIRV_I32EnumAttr<
   "ImageArrayedInfo", "valid SPIR-V Image Arrayed specification",
-  "image_arrayed_info", [SPV_IAI_NonArrayed, SPV_IAI_Arrayed]>;
+  "image_arrayed_info", [SPIRV_IAI_NonArrayed, SPIRV_IAI_Arrayed]>;
 
-def SPV_ISI_SingleSampled : I32EnumAttrCase<"SingleSampled", 0>;
-def SPV_ISI_MultiSampled  : I32EnumAttrCase<"MultiSampled", 1>;
+def SPIRV_ISI_SingleSampled : I32EnumAttrCase<"SingleSampled", 0>;
+def SPIRV_ISI_MultiSampled  : I32EnumAttrCase<"MultiSampled", 1>;
 
-def SPV_SamplingAttr: SPV_I32EnumAttr<
+def SPIRV_SamplingAttr: SPIRV_I32EnumAttr<
   "ImageSamplingInfo", "valid SPIR-V Image Sampling specification",
-  "image_sampling_info", [SPV_ISI_SingleSampled, SPV_ISI_MultiSampled]>;
+  "image_sampling_info", [SPIRV_ISI_SingleSampled, SPIRV_ISI_MultiSampled]>;
 
-def SPV_ISUI_SamplerUnknown : I32EnumAttrCase<"SamplerUnknown", 0>;
-def SPV_ISUI_NeedSampler    : I32EnumAttrCase<"NeedSampler", 1>;
-def SPV_ISUI_NoSampler      : I32EnumAttrCase<"NoSampler", 2>;
+def SPIRV_ISUI_SamplerUnknown : I32EnumAttrCase<"SamplerUnknown", 0>;
+def SPIRV_ISUI_NeedSampler    : I32EnumAttrCase<"NeedSampler", 1>;
+def SPIRV_ISUI_NoSampler      : I32EnumAttrCase<"NoSampler", 2>;
 
-def SPV_SamplerUseAttr: SPV_I32EnumAttr<
+def SPIRV_SamplerUseAttr: SPIRV_I32EnumAttr<
   "ImageSamplerUseInfo", "valid SPIR-V Sampler Use specification",
   "image_sampler_use_info",
-  [SPV_ISUI_SamplerUnknown, SPV_ISUI_NeedSampler, SPV_ISUI_NoSampler]>;
+  [SPIRV_ISUI_SamplerUnknown, SPIRV_ISUI_NeedSampler, SPIRV_ISUI_NoSampler]>;
 
-def SPV_ML_ColumnMajor : I32EnumAttrCase<"ColumnMajor", 0>;
-def SPV_ML_RowMajor    : I32EnumAttrCase<"RowMajor", 1>;
-def SPV_ML_PackedA     : I32EnumAttrCase<"PackedA", 2>;
-def SPV_ML_PackedB     : I32EnumAttrCase<"PackedB", 3>;
-
-def SPV_MatrixLayoutAttr  :
-    SPV_I32EnumAttr<"MatrixLayout", "valid SPIR-V MatrixLayout", "matrixLayout", [
-      SPV_ML_ColumnMajor, SPV_ML_RowMajor, SPV_ML_PackedA, SPV_ML_PackedB
+def SPIRV_ML_ColumnMajor : I32EnumAttrCase<"ColumnMajor", 0>;
+def SPIRV_ML_RowMajor    : I32EnumAttrCase<"RowMajor", 1>;
+def SPIRV_ML_PackedA     : I32EnumAttrCase<"PackedA", 2>;
+def SPIRV_ML_PackedB     : I32EnumAttrCase<"PackedB", 3>;
+
+def SPIRV_MatrixLayoutAttr  :
+    SPIRV_I32EnumAttr<"MatrixLayout", "valid SPIR-V MatrixLayout", "matrixLayout", [
+      SPIRV_ML_ColumnMajor, SPIRV_ML_RowMajor, SPIRV_ML_PackedA, SPIRV_ML_PackedB
     ]>;
 
 //===----------------------------------------------------------------------===//
 // SPIR-V attribute definitions
 //===----------------------------------------------------------------------===//
 
-def SPV_VerCapExtAttr : DialectAttr<
+def SPIRV_VerCapExtAttr : DialectAttr<
     SPIRV_Dialect,
     CPred<"$_self.isa<::mlir::spirv::VerCapExtAttr>()">,
     "version-capability-extension attribute"> {
   let storageType = "::mlir::spirv::VerCapExtAttr";
   let returnType = "::mlir::spirv::VerCapExtAttr";
   let convertFromStorage = "$_self";
 }
 
 //===----------------------------------------------------------------------===//
 // SPIR-V type definitions
 //===----------------------------------------------------------------------===//
 
 class IOrUI<int width>
     : Type<Or<[CPred<"$_self.isSignlessInteger(" # width # ")">,
                CPred<"$_self.isUnsignedInteger(" # width # ")">]>,
            width # "-bit signless/unsigned integer"> {
   int bitwidth = width;
 }
 
 class SignlessOrUnsignedIntOfWidths<list<int> widths> :
     AnyTypeOf<!foreach(w, widths, IOrUI<w>),
               !interleave(widths, "/") # "-bit signless/unsigned integer">;
 
-def SPV_IsArrayType : CPred<"$_self.isa<::mlir::spirv::ArrayType>()">;
-def SPV_IsCooperativeMatrixType :
+def SPIRV_IsArrayType : CPred<"$_self.isa<::mlir::spirv::ArrayType>()">;
+def SPIRV_IsCooperativeMatrixType :
   CPred<"$_self.isa<::mlir::spirv::CooperativeMatrixNVType>()">;
-def SPV_IsImageType : CPred<"$_self.isa<::mlir::spirv::ImageType>()">;
-def SPV_IsJointMatrixType :
+def SPIRV_IsImageType : CPred<"$_self.isa<::mlir::spirv::ImageType>()">;
+def SPIRV_IsJointMatrixType :
   CPred<"$_self.isa<::mlir::spirv::JointMatrixINTELType>()">;
-def SPV_IsMatrixType : CPred<"$_self.isa<::mlir::spirv::MatrixType>()">;
-def SPV_IsPtrType : CPred<"$_self.isa<::mlir::spirv::PointerType>()">;
-def SPV_IsRTArrayType : CPred<"$_self.isa<::mlir::spirv::RuntimeArrayType>()">;
-def SPV_IsSampledImageType : CPred<"$_self.isa<::mlir::spirv::SampledImageType>()">;
-def SPV_IsStructType : CPred<"$_self.isa<::mlir::spirv::StructType>()">;
+def SPIRV_IsMatrixType : CPred<"$_self.isa<::mlir::spirv::MatrixType>()">;
+def SPIRV_IsPtrType : CPred<"$_self.isa<::mlir::spirv::PointerType>()">;
+def SPIRV_IsRTArrayType : CPred<"$_self.isa<::mlir::spirv::RuntimeArrayType>()">;
+def SPIRV_IsSampledImageType : CPred<"$_self.isa<::mlir::spirv::SampledImageType>()">;
+def SPIRV_IsStructType : CPred<"$_self.isa<::mlir::spirv::StructType>()">;
 
 
 // See https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#_types
 // for the definition of the following types and type categories.
 
-def SPV_Void : TypeAlias<NoneType, "void">;
-def SPV_Bool : TypeAlias<I1, "bool">;
-def SPV_Integer : AnyIntOfWidths<[8, 16, 32, 64]>;
-def SPV_Int32 : TypeAlias<I32, "Int32">;
-def SPV_Float32 : TypeAlias<F32, "Float32">;
-def SPV_Float : FloatOfWidths<[16, 32, 64]>;
-def SPV_Float16or32 : FloatOfWidths<[16, 32]>;
-def SPV_Vector : VectorOfLengthAndType<[2, 3, 4, 8, 16],
-                                       [SPV_Bool, SPV_Integer, SPV_Float]>;
+def SPIRV_Void : TypeAlias<NoneType, "void">;
+def SPIRV_Bool : TypeAlias<I1, "bool">;
+def SPIRV_Integer : AnyIntOfWidths<[8, 16, 32, 64]>;
+def SPIRV_Int32 : TypeAlias<I32, "Int32">;
+def SPIRV_Float32 : TypeAlias<F32, "Float32">;
+def SPIRV_Float : FloatOfWidths<[16, 32, 64]>;
+def SPIRV_Float16or32 : FloatOfWidths<[16, 32]>;
+def SPIRV_Vector : VectorOfLengthAndType<[2, 3, 4, 8, 16],
+                                       [SPIRV_Bool, SPIRV_Integer, SPIRV_Float]>;
 // Component type check is done in the type parser for the following SPIR-V
 // dialect-specific types so we use "Any" here.
-def SPV_AnyPtr : DialectType<SPIRV_Dialect, SPV_IsPtrType,
+def SPIRV_AnyPtr : DialectType<SPIRV_Dialect, SPIRV_IsPtrType,
                              "any SPIR-V pointer type">;
-def SPV_AnyArray : DialectType<SPIRV_Dialect, SPV_IsArrayType,
+def SPIRV_AnyArray : DialectType<SPIRV_Dialect, SPIRV_IsArrayType,
                                "any SPIR-V array type">;
-def SPV_AnyCooperativeMatrix : DialectType<SPIRV_Dialect,
-                               SPV_IsCooperativeMatrixType,
+def SPIRV_AnyCooperativeMatrix : DialectType<SPIRV_Dialect,
+                               SPIRV_IsCooperativeMatrixType,
                                "any SPIR-V cooperative matrix type">;
-def SPV_AnyImage : DialectType<SPIRV_Dialect, SPV_IsImageType,
+def SPIRV_AnyImage : DialectType<SPIRV_Dialect, SPIRV_IsImageType,
                                 "any SPIR-V image type">;
-def SPV_AnyJointMatrix : DialectType<SPIRV_Dialect, SPV_IsJointMatrixType,
+def SPIRV_AnyJointMatrix : DialectType<SPIRV_Dialect, SPIRV_IsJointMatrixType,
                                 "any SPIR-V joint matrix type">;
-def SPV_AnyMatrix : DialectType<SPIRV_Dialect, SPV_IsMatrixType,
+def SPIRV_AnyMatrix : DialectType<SPIRV_Dialect, SPIRV_IsMatrixType,
                                 "any SPIR-V matrix type">;
-def SPV_AnyRTArray : DialectType<SPIRV_Dialect, SPV_IsRTArrayType,
+def SPIRV_AnyRTArray : DialectType<SPIRV_Dialect, SPIRV_IsRTArrayType,
                                  "any SPIR-V runtime array type">;
-def SPV_AnyStruct : DialectType<SPIRV_Dialect, SPV_IsStructType,
+def SPIRV_AnyStruct : DialectType<SPIRV_Dialect, SPIRV_IsStructType,
                                 "any SPIR-V struct type">;
-def SPV_AnySampledImage : DialectType<SPIRV_Dialect, SPV_IsSampledImageType,
+def SPIRV_AnySampledImage : DialectType<SPIRV_Dialect, SPIRV_IsSampledImageType,
                                 "any SPIR-V sampled image type">;
 
-def SPV_Numerical : AnyTypeOf<[SPV_Integer, SPV_Float]>;
-def SPV_Scalar : AnyTypeOf<[SPV_Numerical, SPV_Bool]>;
-def SPV_Aggregate : AnyTypeOf<[SPV_AnyArray, SPV_AnyRTArray, SPV_AnyStruct]>;
-def SPV_Composite :
-    AnyTypeOf<[SPV_Vector, SPV_AnyArray, SPV_AnyRTArray, SPV_AnyStruct,
-               SPV_AnyCooperativeMatrix, SPV_AnyJointMatrix, SPV_AnyMatrix]>;
-def SPV_Type : AnyTypeOf<[
-    SPV_Void, SPV_Bool, SPV_Integer, SPV_Float, SPV_Vector,
-    SPV_AnyPtr, SPV_AnyArray, SPV_AnyRTArray, SPV_AnyStruct,
-    SPV_AnyCooperativeMatrix, SPV_AnyJointMatrix, SPV_AnyMatrix,
-    SPV_AnySampledImage
+def SPIRV_Numerical : AnyTypeOf<[SPIRV_Integer, SPIRV_Float]>;
+def SPIRV_Scalar : AnyTypeOf<[SPIRV_Numerical, SPIRV_Bool]>;
+def SPIRV_Aggregate : AnyTypeOf<[SPIRV_AnyArray, SPIRV_AnyRTArray, SPIRV_AnyStruct]>;
+def SPIRV_Composite :
+    AnyTypeOf<[SPIRV_Vector, SPIRV_AnyArray, SPIRV_AnyRTArray, SPIRV_AnyStruct,
+               SPIRV_AnyCooperativeMatrix, SPIRV_AnyJointMatrix, SPIRV_AnyMatrix]>;
+def SPIRV_Type : AnyTypeOf<[
+    SPIRV_Void, SPIRV_Bool, SPIRV_Integer, SPIRV_Float, SPIRV_Vector,
+    SPIRV_AnyPtr, SPIRV_AnyArray, SPIRV_AnyRTArray, SPIRV_AnyStruct,
+    SPIRV_AnyCooperativeMatrix, SPIRV_AnyJointMatrix, SPIRV_AnyMatrix,
+    SPIRV_AnySampledImage
   ]>;
 
-def SPV_SignedInt : SignedIntOfWidths<[8, 16, 32, 64]>;
-def SPV_SignlessOrUnsignedInt : SignlessOrUnsignedIntOfWidths<[8, 16, 32, 64]>;
+def SPIRV_SignedInt : SignedIntOfWidths<[8, 16, 32, 64]>;
+def SPIRV_SignlessOrUnsignedInt : SignlessOrUnsignedIntOfWidths<[8, 16, 32, 64]>;
 
-class SPV_CoopMatrixOfType<list<Type> allowedTypes> :
-  ContainerType<AnyTypeOf<allowedTypes>, SPV_IsCooperativeMatrixType,
+class SPIRV_CoopMatrixOfType<list<Type> allowedTypes> :
+  ContainerType<AnyTypeOf<allowedTypes>, SPIRV_IsCooperativeMatrixType,
     "$_self.cast<::mlir::spirv::CooperativeMatrixNVType>().getElementType()",
     "Cooperative Matrix">;
 
-class SPV_JointMatrixOfType<list<Type> allowedTypes> :
-  ContainerType<AnyTypeOf<allowedTypes>, SPV_IsJointMatrixType,
+class SPIRV_JointMatrixOfType<list<Type> allowedTypes> :
+  ContainerType<AnyTypeOf<allowedTypes>, SPIRV_IsJointMatrixType,
     "$_self.cast<::mlir::spirv::JointMatrixINTELType>().getElementType()",
     "Joint Matrix">;
 
-class SPV_ScalarOrVectorOf<Type type> :
+class SPIRV_ScalarOrVectorOf<Type type> :
     AnyTypeOf<[type, VectorOfLengthAndType<[2, 3, 4, 8, 16], [type]>]>;
 
-class SPV_ScalarOrVectorOrCoopMatrixOf<Type type> :
+class SPIRV_ScalarOrVectorOrCoopMatrixOf<Type type> :
     AnyTypeOf<[type, VectorOfLengthAndType<[2, 3, 4, 8, 16], [type]>,
-               SPV_CoopMatrixOfType<[type]>]>;
+               SPIRV_CoopMatrixOfType<[type]>]>;
 
-def SPV_ScalarOrVector : AnyTypeOf<[SPV_Scalar, SPV_Vector]>;
-def SPV_ScalarOrVectorOrPtr : AnyTypeOf<[SPV_ScalarOrVector, SPV_AnyPtr]>;
+def SPIRV_ScalarOrVector : AnyTypeOf<[SPIRV_Scalar, SPIRV_Vector]>;
+def SPIRV_ScalarOrVectorOrPtr : AnyTypeOf<[SPIRV_ScalarOrVector, SPIRV_AnyPtr]>;
 
-class SPV_Vec4<Type type> : VectorOfLengthAndType<[4], [type]>;
-def SPV_IntVec4 : SPV_Vec4<SPV_Integer>;
-def SPV_IOrUIVec4 : SPV_Vec4<SPV_SignlessOrUnsignedInt>;
-def SPV_Int32Vec4 : SPV_Vec4<AnyI32>;
+class SPIRV_Vec4<Type type> : VectorOfLengthAndType<[4], [type]>;
+def SPIRV_IntVec4 : SPIRV_Vec4<SPIRV_Integer>;
+def SPIRV_IOrUIVec4 : SPIRV_Vec4<SPIRV_SignlessOrUnsignedInt>;
+def SPIRV_Int32Vec4 : SPIRV_Vec4<AnyI32>;
 
 // TODO: From 1.4, this should also include Composite type.
-def SPV_SelectType : AnyTypeOf<[SPV_Scalar, SPV_Vector, SPV_AnyPtr]>;
+def SPIRV_SelectType : AnyTypeOf<[SPIRV_Scalar, SPIRV_Vector, SPIRV_AnyPtr]>;
 
 //===----------------------------------------------------------------------===//
 // SPIR-V OpTrait definitions
 //===----------------------------------------------------------------------===//
 
 // Check that an op can only be used within the scope of a function-like op.
 def InFunctionScope : PredOpTrait<
   "op must appear in a function-like op's block",

 def SignedOp : NativeOpTrait<"spirv::SignedOp">;
 
 def UsableInSpecConstantOp : NativeOpTrait<"spirv::UsableInSpecConstantOp">;
 
 //===----------------------------------------------------------------------===//
 // SPIR-V opcode specification
 //===----------------------------------------------------------------------===//
 
-class SPV_OpCode<string name, int val> {
+class SPIRV_OpCode<string name, int val> {
   // Name used as reference to retrieve the opcode
   string opname = name;
 
   // Opcode associated with the name
   int opcode = val;
 }
 
 // Begin opcode section. Generated from SPIR-V spec; DO NOT MODIFY!
 
-def SPV_OC_OpNop                        : I32EnumAttrCase<"OpNop", 0>;
-def SPV_OC_OpUndef                      : I32EnumAttrCase<"OpUndef", 1>;
-def SPV_OC_OpSourceContinued            : I32EnumAttrCase<"OpSourceContinued", 2>;
-def SPV_OC_OpSource                     : I32EnumAttrCase<"OpSource", 3>;
-def SPV_OC_OpSourceExtension            : I32EnumAttrCase<"OpSourceExtension", 4>;
-def SPV_OC_OpName                       : I32EnumAttrCase<"OpName", 5>;
-def SPV_OC_OpMemberName                 : I32EnumAttrCase<"OpMemberName", 6>;
-def SPV_OC_OpString                     : I32EnumAttrCase<"OpString", 7>;
-def SPV_OC_OpLine                       : I32EnumAttrCase<"OpLine", 8>;
-def SPV_OC_OpExtension                  : I32EnumAttrCase<"OpExtension", 10>;
-def SPV_OC_OpExtInstImport              : I32EnumAttrCase<"OpExtInstImport", 11>;
-def SPV_OC_OpExtInst                    : I32EnumAttrCase<"OpExtInst", 12>;
-def SPV_OC_OpMemoryModel                : I32EnumAttrCase<"OpMemoryModel", 14>;
-def SPV_OC_OpEntryPoint                 : I32EnumAttrCase<"OpEntryPoint", 15>;
-def SPV_OC_OpExecutionMode              : I32EnumAttrCase<"OpExecutionMode", 16>;
-def SPV_OC_OpCapability                 : I32EnumAttrCase<"OpCapability", 17>;
-def SPV_OC_OpTypeVoid                   : I32EnumAttrCase<"OpTypeVoid", 19>;
-def SPV_OC_OpTypeBool                   : I32EnumAttrCase<"OpTypeBool", 20>;
-def SPV_OC_OpTypeInt                    : I32EnumAttrCase<"OpTypeInt", 21>;
-def SPV_OC_OpTypeFloat                  : I32EnumAttrCase<"OpTypeFloat", 22>;
-def SPV_OC_OpTypeVector                 : I32EnumAttrCase<"OpTypeVector", 23>;
-def SPV_OC_OpTypeMatrix                 : I32EnumAttrCase<"OpTypeMatrix", 24>;
-def SPV_OC_OpTypeImage                  : I32EnumAttrCase<"OpTypeImage", 25>;
-def SPV_OC_OpTypeSampledImage           : I32EnumAttrCase<"OpTypeSampledImage", 27>;
-def SPV_OC_OpTypeArray                  : I32EnumAttrCase<"OpTypeArray", 28>;
-def SPV_OC_OpTypeRuntimeArray           : I32EnumAttrCase<"OpTypeRuntimeArray", 29>;
-def SPV_OC_OpTypeStruct                 : I32EnumAttrCase<"OpTypeStruct", 30>;
-def SPV_OC_OpTypePointer                : I32EnumAttrCase<"OpTypePointer", 32>;
-def SPV_OC_OpTypeFunction               : I32EnumAttrCase<"OpTypeFunction", 33>;
-def SPV_OC_OpTypeForwardPointer         : I32EnumAttrCase<"OpTypeForwardPointer", 39>;
-def SPV_OC_OpConstantTrue               : I32EnumAttrCase<"OpConstantTrue", 41>;
-def SPV_OC_OpConstantFalse              : I32EnumAttrCase<"OpConstantFalse", 42>;
-def SPV_OC_OpConstant                   : I32EnumAttrCase<"OpConstant", 43>;
-def SPV_OC_OpConstantComposite          : I32EnumAttrCase<"OpConstantComposite", 44>;
-def SPV_OC_OpConstantNull               : I32EnumAttrCase<"OpConstantNull", 46>;
-def SPV_OC_OpSpecConstantTrue           : I32EnumAttrCase<"OpSpecConstantTrue", 48>;
-def SPV_OC_OpSpecConstantFalse          : I32EnumAttrCase<"OpSpecConstantFalse", 49>;
-def SPV_OC_OpSpecConstant               : I32EnumAttrCase<"OpSpecConstant", 50>;
-def SPV_OC_OpSpecConstantComposite      : I32EnumAttrCase<"OpSpecConstantComposite", 51>;
-def SPV_OC_OpSpecConstantOp             : I32EnumAttrCase<"OpSpecConstantOp", 52>;
-def SPV_OC_OpFunction                   : I32EnumAttrCase<"OpFunction", 54>;
-def SPV_OC_OpFunctionParameter          : I32EnumAttrCase<"OpFunctionParameter", 55>;
-def SPV_OC_OpFunctionEnd                : I32EnumAttrCase<"OpFunctionEnd", 56>;
-def SPV_OC_OpFunctionCall               : I32EnumAttrCase<"OpFunctionCall", 57>;
-def SPV_OC_OpVariable                   : I32EnumAttrCase<"OpVariable", 59>;
-def SPV_OC_OpLoad                       : I32EnumAttrCase<"OpLoad", 61>;
-def SPV_OC_OpStore                      : I32EnumAttrCase<"OpStore", 62>;
-def SPV_OC_OpCopyMemory                 : I32EnumAttrCase<"OpCopyMemory", 63>;
-def SPV_OC_OpAccessChain                : I32EnumAttrCase<"OpAccessChain", 65>;
-def SPV_OC_OpPtrAccessChain             : I32EnumAttrCase<"OpPtrAccessChain", 67>;
-def SPV_OC_OpInBoundsPtrAccessChain     : I32EnumAttrCase<"OpInBoundsPtrAccessChain", 70>;
-def SPV_OC_OpDecorate                   : I32EnumAttrCase<"OpDecorate", 71>;
-def SPV_OC_OpMemberDecorate             : I32EnumAttrCase<"OpMemberDecorate", 72>;
-def SPV_OC_OpVectorExtractDynamic       : I32EnumAttrCase<"OpVectorExtractDynamic", 77>;
-def SPV_OC_OpVectorInsertDynamic        : I32EnumAttrCase<"OpVectorInsertDynamic", 78>;
-def SPV_OC_OpVectorShuffle              : I32EnumAttrCase<"OpVectorShuffle", 79>;
-def SPV_OC_OpCompositeConstruct         : I32EnumAttrCase<"OpCompositeConstruct", 80>;
-def SPV_OC_OpCompositeExtract           : I32EnumAttrCase<"OpCompositeExtract", 81>;
-def SPV_OC_OpCompositeInsert            : I32EnumAttrCase<"OpCompositeInsert", 82>;
-def SPV_OC_OpTranspose                  : I32EnumAttrCase<"OpTranspose", 84>;
-def SPV_OC_OpImageDrefGather            : I32EnumAttrCase<"OpImageDrefGather", 97>;
-def SPV_OC_OpImage                      : I32EnumAttrCase<"OpImage", 100>;
-def SPV_OC_OpImageQuerySize             : I32EnumAttrCase<"OpImageQuerySize", 104>;
-def SPV_OC_OpConvertFToU                : I32EnumAttrCase<"OpConvertFToU", 109>;
-def SPV_OC_OpConvertFToS                : I32EnumAttrCase<"OpConvertFToS", 110>;
-def SPV_OC_OpConvertSToF                : I32EnumAttrCase<"OpConvertSToF", 111>;
-def SPV_OC_OpConvertUToF                : I32EnumAttrCase<"OpConvertUToF", 112>;
-def SPV_OC_OpUConvert                   : I32EnumAttrCase<"OpUConvert", 113>;
-def SPV_OC_OpSConvert                   : I32EnumAttrCase<"OpSConvert", 114>;
-def SPV_OC_OpFConvert                   : I32EnumAttrCase<"OpFConvert", 115>;
-def SPV_OC_OpPtrCastToGeneric           : I32EnumAttrCase<"OpPtrCastToGeneric", 121>;
-def SPV_OC_OpGenericCastToPtr           : I32EnumAttrCase<"OpGenericCastToPtr", 122>;
-def SPV_OC_OpGenericCastToPtrExplicit   : I32EnumAttrCase<"OpGenericCastToPtrExplicit", 123>;
-def SPV_OC_OpBitcast                    : I32EnumAttrCase<"OpBitcast", 124>;
-def SPV_OC_OpSNegate                    : I32EnumAttrCase<"OpSNegate", 126>;
-def SPV_OC_OpFNegate                    : I32EnumAttrCase<"OpFNegate", 127>;
-def SPV_OC_OpIAdd                       : I32EnumAttrCase<"OpIAdd", 128>;
-def SPV_OC_OpFAdd                       : I32EnumAttrCase<"OpFAdd", 129>;
-def SPV_OC_OpISub                       : I32EnumAttrCase<"OpISub", 130>;
-def SPV_OC_OpFSub                       : I32EnumAttrCase<"OpFSub", 131>;
-def SPV_OC_OpIMul                       : I32EnumAttrCase<"OpIMul", 132>;
-def SPV_OC_OpFMul                       : I32EnumAttrCase<"OpFMul", 133>;
-def SPV_OC_OpUDiv                       : I32EnumAttrCase<"OpUDiv", 134>;
-def SPV_OC_OpSDiv                       : I32EnumAttrCase<"OpSDiv", 135>;
-def SPV_OC_OpFDiv                       : I32EnumAttrCase<"OpFDiv", 136>;
-def SPV_OC_OpUMod                       : I32EnumAttrCase<"OpUMod", 137>;
-def SPV_OC_OpSRem                       : I32EnumAttrCase<"OpSRem", 138>;
-def SPV_OC_OpSMod                       : I32EnumAttrCase<"OpSMod", 139>;
-def SPV_OC_OpFRem                       : I32EnumAttrCase<"OpFRem", 140>;
-def SPV_OC_OpFMod                       : I32EnumAttrCase<"OpFMod", 141>;
-def SPV_OC_OpVectorTimesScalar          : I32EnumAttrCase<"OpVectorTimesScalar", 142>;
-def SPV_OC_OpMatrixTimesScalar          : I32EnumAttrCase<"OpMatrixTimesScalar", 143>;
-def SPV_OC_OpMatrixTimesMatrix          : I32EnumAttrCase<"OpMatrixTimesMatrix", 146>;
-def SPV_OC_OpIAddCarry                  : I32EnumAttrCase<"OpIAddCarry", 149>;
-def SPV_OC_OpISubBorrow                 : I32EnumAttrCase<"OpISubBorrow", 150>;
-def SPV_OC_OpIsNan                      : I32EnumAttrCase<"OpIsNan", 156>;
-def SPV_OC_OpIsInf                      : I32EnumAttrCase<"OpIsInf", 157>;
-def SPV_OC_OpOrdered                    : I32EnumAttrCase<"OpOrdered", 162>;
-def SPV_OC_OpUnordered                  : I32EnumAttrCase<"OpUnordered", 163>;
-def SPV_OC_OpLogicalEqual               : I32EnumAttrCase<"OpLogicalEqual", 164>;
-def SPV_OC_OpLogicalNotEqual            : I32EnumAttrCase<"OpLogicalNotEqual", 165>;
-def SPV_OC_OpLogicalOr                  : I32EnumAttrCase<"OpLogicalOr", 166>;
-def SPV_OC_OpLogicalAnd                 : I32EnumAttrCase<"OpLogicalAnd", 167>;
-def SPV_OC_OpLogicalNot                 : I32EnumAttrCase<"OpLogicalNot", 168>;
-def SPV_OC_OpSelect                     : I32EnumAttrCase<"OpSelect", 169>;
-def SPV_OC_OpIEqual                     : I32EnumAttrCase<"OpIEqual", 170>;
-def SPV_OC_OpINotEqual                  : I32EnumAttrCase<"OpINotEqual", 171>;
-def SPV_OC_OpUGreaterThan               : I32EnumAttrCase<"OpUGreaterThan", 172>;
-def SPV_OC_OpSGreaterThan               : I32EnumAttrCase<"OpSGreaterThan", 173>;
-def SPV_OC_OpUGreaterThanEqual          : I32EnumAttrCase<"OpUGreaterThanEqual", 174>;
-def SPV_OC_OpSGreaterThanEqual          : I32EnumAttrCase<"OpSGreaterThanEqual", 175>;
-def SPV_OC_OpULessThan                  : I32EnumAttrCase<"OpULessThan", 176>;
-def SPV_OC_OpSLessThan                  : I32EnumAttrCase<"OpSLessThan", 177>;
-def SPV_OC_OpULessThanEqual             : I32EnumAttrCase<"OpULessThanEqual", 178>;
-def SPV_OC_OpSLessThanEqual             : I32EnumAttrCase<"OpSLessThanEqual", 179>;
-def SPV_OC_OpFOrdEqual                  : I32EnumAttrCase<"OpFOrdEqual", 180>;
-def SPV_OC_OpFUnordEqual                : I32EnumAttrCase<"OpFUnordEqual", 181>;
-def SPV_OC_OpFOrdNotEqual               : I32EnumAttrCase<"OpFOrdNotEqual", 182>;
-def SPV_OC_OpFUnordNotEqual             : I32EnumAttrCase<"OpFUnordNotEqual", 183>;
-def SPV_OC_OpFOrdLessThan               : I32EnumAttrCase<"OpFOrdLessThan", 184>;
-def SPV_OC_OpFUnordLessThan             : I32EnumAttrCase<"OpFUnordLessThan", 185>;
-def SPV_OC_OpFOrdGreaterThan            : I32EnumAttrCase<"OpFOrdGreaterThan", 186>;
-def SPV_OC_OpFUnordGreaterThan          : I32EnumAttrCase<"OpFUnordGreaterThan", 187>;
-def SPV_OC_OpFOrdLessThanEqual          : I32EnumAttrCase<"OpFOrdLessThanEqual", 188>;
-def SPV_OC_OpFUnordLessThanEqual        : I32EnumAttrCase<"OpFUnordLessThanEqual", 189>;
-def SPV_OC_OpFOrdGreaterThanEqual       : I32EnumAttrCase<"OpFOrdGreaterThanEqual", 190>;
-def SPV_OC_OpFUnordGreaterThanEqual     : I32EnumAttrCase<"OpFUnordGreaterThanEqual", 191>;
-def SPV_OC_OpShiftRightLogical          : I32EnumAttrCase<"OpShiftRightLogical", 194>;
-def SPV_OC_OpShiftRightArithmetic       : I32EnumAttrCase<"OpShiftRightArithmetic", 195>;
-def SPV_OC_OpShiftLeftLogical           : I32EnumAttrCase<"OpShiftLeftLogical", 196>;
-def SPV_OC_OpBitwiseOr                  : I32EnumAttrCase<"OpBitwiseOr", 197>;
-def SPV_OC_OpBitwiseXor                 : I32EnumAttrCase<"OpBitwiseXor", 198>;
-def SPV_OC_OpBitwiseAnd                 : I32EnumAttrCase<"OpBitwiseAnd", 199>;
-def SPV_OC_OpNot                        : I32EnumAttrCase<"OpNot", 200>;
-def SPV_OC_OpBitFieldInsert             : I32EnumAttrCase<"OpBitFieldInsert", 201>;
-def SPV_OC_OpBitFieldSExtract           : I32EnumAttrCase<"OpBitFieldSExtract", 202>;
-def SPV_OC_OpBitFieldUExtract           : I32EnumAttrCase<"OpBitFieldUExtract", 203>;
-def SPV_OC_OpBitReverse                 : I32EnumAttrCase<"OpBitReverse", 204>;
-def SPV_OC_OpBitCount                   : I32EnumAttrCase<"OpBitCount", 205>;
-def SPV_OC_OpControlBarrier             : I32EnumAttrCase<"OpControlBarrier", 224>;
-def SPV_OC_OpMemoryBarrier              : I32EnumAttrCase<"OpMemoryBarrier", 225>;
-def SPV_OC_OpAtomicExchange             : I32EnumAttrCase<"OpAtomicExchange", 229>;
-def SPV_OC_OpAtomicCompareExchange      : I32EnumAttrCase<"OpAtomicCompareExchange", 230>;
-def SPV_OC_OpAtomicCompareExchangeWeak  : I32EnumAttrCase<"OpAtomicCompareExchangeWeak", 231>;
-def SPV_OC_OpAtomicIIncrement           : I32EnumAttrCase<"OpAtomicIIncrement", 232>;
-def SPV_OC_OpAtomicIDecrement           : I32EnumAttrCase<"OpAtomicIDecrement", 233>;
-def SPV_OC_OpAtomicIAdd                 : I32EnumAttrCase<"OpAtomicIAdd", 234>;
-def SPV_OC_OpAtomicISub                 : I32EnumAttrCase<"OpAtomicISub", 235>;
-def SPV_OC_OpAtomicSMin                 : I32EnumAttrCase<"OpAtomicSMin", 236>;
-def SPV_OC_OpAtomicUMin                 : I32EnumAttrCase<"OpAtomicUMin", 237>;
-def SPV_OC_OpAtomicSMax                 : I32EnumAttrCase<"OpAtomicSMax", 238>;
-def SPV_OC_OpAtomicUMax                 : I32EnumAttrCase<"OpAtomicUMax", 239>;
-def SPV_OC_OpAtomicAnd                  : I32EnumAttrCase<"OpAtomicAnd", 240>;
-def SPV_OC_OpAtomicOr                   : I32EnumAttrCase<"OpAtomicOr", 241>;
-def SPV_OC_OpAtomicXor                  : I32EnumAttrCase<"OpAtomicXor", 242>;
-def SPV_OC_OpPhi                        : I32EnumAttrCase<"OpPhi", 245>;
-def SPV_OC_OpLoopMerge                  : I32EnumAttrCase<"OpLoopMerge", 246>;
-def SPV_OC_OpSelectionMerge             : I32EnumAttrCase<"OpSelectionMerge", 247>;
-def SPV_OC_OpLabel                      : I32EnumAttrCase<"OpLabel", 248>;
-def SPV_OC_OpBranch                     : I32EnumAttrCase<"OpBranch", 249>;
-def SPV_OC_OpBranchConditional          : I32EnumAttrCase<"OpBranchConditional", 250>;
-def SPV_OC_OpReturn                     : I32EnumAttrCase<"OpReturn", 253>;
-def SPV_OC_OpReturnValue                : I32EnumAttrCase<"OpReturnValue", 254>;
-def SPV_OC_OpUnreachable                : I32EnumAttrCase<"OpUnreachable", 255>;
-def SPV_OC_OpGroupBroadcast             : I32EnumAttrCase<"OpGroupBroadcast", 263>;
-def SPV_OC_OpNoLine                     : I32EnumAttrCase<"OpNoLine", 317>;
-def SPV_OC_OpModuleProcessed            : I32EnumAttrCase<"OpModuleProcessed", 330>;
-def SPV_OC_OpGroupNonUniformElect       : I32EnumAttrCase<"OpGroupNonUniformElect", 333>;
-def SPV_OC_OpGroupNonUniformBroadcast   : I32EnumAttrCase<"OpGroupNonUniformBroadcast", 337>;
-def SPV_OC_OpGroupNonUniformBallot      : I32EnumAttrCase<"OpGroupNonUniformBallot", 339>;
-def SPV_OC_OpGroupNonUniformShuffle     : I32EnumAttrCase<"OpGroupNonUniformShuffle", 345>;
-def SPV_OC_OpGroupNonUniformShuffleXor  : I32EnumAttrCase<"OpGroupNonUniformShuffleXor", 346>;
-def SPV_OC_OpGroupNonUniformShuffleUp   : I32EnumAttrCase<"OpGroupNonUniformShuffleUp", 347>;
-def SPV_OC_OpGroupNonUniformShuffleDown : I32EnumAttrCase<"OpGroupNonUniformShuffleDown", 348>;
-def SPV_OC_OpGroupNonUniformIAdd        : I32EnumAttrCase<"OpGroupNonUniformIAdd", 349>;
-def SPV_OC_OpGroupNonUniformFAdd        : I32EnumAttrCase<"OpGroupNonUniformFAdd", 350>;
-def SPV_OC_OpGroupNonUniformIMul        : I32EnumAttrCase<"OpGroupNonUniformIMul", 351>;
-def SPV_OC_OpGroupNonUniformFMul        : I32EnumAttrCase<"OpGroupNonUniformFMul", 352>;
-def SPV_OC_OpGroupNonUniformSMin        : I32EnumAttrCase<"OpGroupNonUniformSMin", 353>;
-def SPV_OC_OpGroupNonUniformUMin        : I32EnumAttrCase<"OpGroupNonUniformUMin", 354>;
-def SPV_OC_OpGroupNonUniformFMin        : I32EnumAttrCase<"OpGroupNonUniformFMin", 355>;
-def SPV_OC_OpGroupNonUniformSMax        : I32EnumAttrCase<"OpGroupNonUniformSMax", 356>;
-def SPV_OC_OpGroupNonUniformUMax        : I32EnumAttrCase<"OpGroupNonUniformUMax", 357>;
-def SPV_OC_OpGroupNonUniformFMax        : I32EnumAttrCase<"OpGroupNonUniformFMax", 358>;
-def SPV_OC_OpSubgroupBallotKHR          : I32EnumAttrCase<"OpSubgroupBallotKHR", 4421>;
-def SPV_OC_OpTypeCooperativeMatrixNV    : I32EnumAttrCase<"OpTypeCooperativeMatrixNV", 5358>;
-def SPV_OC_OpCooperativeMatrixLoadNV    : I32EnumAttrCase<"OpCooperativeMatrixLoadNV", 5359>;
-def SPV_OC_OpCooperativeMatrixStoreNV   : I32EnumAttrCase<"OpCooperativeMatrixStoreNV", 5360>;
-def SPV_OC_OpCooperativeMatrixMulAddNV  : I32EnumAttrCase<"OpCooperativeMatrixMulAddNV", 5361>;
-def SPV_OC_OpCooperativeMatrixLengthNV  : I32EnumAttrCase<"OpCooperativeMatrixLengthNV", 5362>;
-def SPV_OC_OpSubgroupBlockReadINTEL     : I32EnumAttrCase<"OpSubgroupBlockReadINTEL", 5575>;
-def SPV_OC_OpSubgroupBlockWriteINTEL    : I32EnumAttrCase<"OpSubgroupBlockWriteINTEL", 5576>;
-def SPV_OC_OpAssumeTrueKHR              : I32EnumAttrCase<"OpAssumeTrueKHR", 5630>;
-def SPV_OC_OpAtomicFAddEXT              : I32EnumAttrCase<"OpAtomicFAddEXT", 6035>;
-
-def SPV_OC_OpTypeJointMatrixINTEL       : I32EnumAttrCase<"OpTypeJointMatrixINTEL", 6119>;
-def SPV_OC_OpJointMatrixLoadINTEL       : I32EnumAttrCase<"OpJointMatrixLoadINTEL", 6120>;
-def SPV_OC_OpJointMatrixStoreINTEL      : I32EnumAttrCase<"OpJointMatrixStoreINTEL", 6121>;
-def SPV_OC_OpJointMatrixMadINTEL        : I32EnumAttrCase<"OpJointMatrixMadINTEL", 6122>;
-def SPV_OC_OpTypejointMatrixWorkItemLengthINTEL : I32EnumAttrCase<"OpJointMatrixWorkItemLengthINTEL", 6410>;
-
-def SPV_OpcodeAttr :
-    SPV_I32EnumAttr<"Opcode", "valid SPIR-V instructions", "opcode", [
-      SPV_OC_OpNop, SPV_OC_OpUndef, SPV_OC_OpSourceContinued, SPV_OC_OpSource,
-      SPV_OC_OpSourceExtension, SPV_OC_OpName, SPV_OC_OpMemberName, SPV_OC_OpString,
-      SPV_OC_OpLine, SPV_OC_OpExtension, SPV_OC_OpExtInstImport, SPV_OC_OpExtInst,
-      SPV_OC_OpMemoryModel, SPV_OC_OpEntryPoint, SPV_OC_OpExecutionMode,
-      SPV_OC_OpCapability, SPV_OC_OpTypeVoid, SPV_OC_OpTypeBool, SPV_OC_OpTypeInt,
-      SPV_OC_OpTypeFloat, SPV_OC_OpTypeVector, SPV_OC_OpTypeMatrix,
-      SPV_OC_OpTypeImage, SPV_OC_OpTypeSampledImage, SPV_OC_OpTypeArray,
-      SPV_OC_OpTypeRuntimeArray, SPV_OC_OpTypeStruct, SPV_OC_OpTypePointer,
-      SPV_OC_OpTypeFunction, SPV_OC_OpTypeForwardPointer, SPV_OC_OpConstantTrue,
-      SPV_OC_OpConstantFalse, SPV_OC_OpConstant, SPV_OC_OpConstantComposite,
-      SPV_OC_OpConstantNull, SPV_OC_OpSpecConstantTrue, SPV_OC_OpSpecConstantFalse,
-      SPV_OC_OpSpecConstant, SPV_OC_OpSpecConstantComposite, SPV_OC_OpSpecConstantOp,
-      SPV_OC_OpFunction, SPV_OC_OpFunctionParameter, SPV_OC_OpFunctionEnd,
-      SPV_OC_OpFunctionCall, SPV_OC_OpVariable, SPV_OC_OpLoad, SPV_OC_OpStore,
-      SPV_OC_OpCopyMemory, SPV_OC_OpAccessChain, SPV_OC_OpPtrAccessChain,
-      SPV_OC_OpInBoundsPtrAccessChain, SPV_OC_OpDecorate, SPV_OC_OpMemberDecorate,
-      SPV_OC_OpVectorExtractDynamic, SPV_OC_OpVectorInsertDynamic,
-      SPV_OC_OpVectorShuffle, SPV_OC_OpCompositeConstruct, SPV_OC_OpCompositeExtract,
-      SPV_OC_OpCompositeInsert, SPV_OC_OpTranspose, SPV_OC_OpImageDrefGather,
-      SPV_OC_OpImage, SPV_OC_OpImageQuerySize, SPV_OC_OpConvertFToU,
-      SPV_OC_OpConvertFToS, SPV_OC_OpConvertSToF, SPV_OC_OpConvertUToF,
-      SPV_OC_OpUConvert, SPV_OC_OpSConvert, SPV_OC_OpFConvert, SPV_OC_OpPtrCastToGeneric, 
-      SPV_OC_OpGenericCastToPtr, SPV_OC_OpGenericCastToPtrExplicit, SPV_OC_OpBitcast,
-      SPV_OC_OpSNegate, SPV_OC_OpFNegate, SPV_OC_OpIAdd, SPV_OC_OpFAdd,
-      SPV_OC_OpISub, SPV_OC_OpFSub, SPV_OC_OpIMul, SPV_OC_OpFMul, SPV_OC_OpUDiv,
-      SPV_OC_OpSDiv, SPV_OC_OpFDiv, SPV_OC_OpUMod, SPV_OC_OpSRem, SPV_OC_OpSMod,
-      SPV_OC_OpFRem, SPV_OC_OpFMod, SPV_OC_OpVectorTimesScalar,
-      SPV_OC_OpMatrixTimesScalar, SPV_OC_OpMatrixTimesMatrix, SPV_OC_OpIAddCarry,
-      SPV_OC_OpISubBorrow, SPV_OC_OpIsNan, SPV_OC_OpIsInf, SPV_OC_OpOrdered,
-      SPV_OC_OpUnordered, SPV_OC_OpLogicalEqual, SPV_OC_OpLogicalNotEqual,
-      SPV_OC_OpLogicalOr, SPV_OC_OpLogicalAnd, SPV_OC_OpLogicalNot, SPV_OC_OpSelect,
-      SPV_OC_OpIEqual, SPV_OC_OpINotEqual, SPV_OC_OpUGreaterThan,
-      SPV_OC_OpSGreaterThan, SPV_OC_OpUGreaterThanEqual, SPV_OC_OpSGreaterThanEqual,
-      SPV_OC_OpULessThan, SPV_OC_OpSLessThan, SPV_OC_OpULessThanEqual,
-      SPV_OC_OpSLessThanEqual, SPV_OC_OpFOrdEqual, SPV_OC_OpFUnordEqual,
-      SPV_OC_OpFOrdNotEqual, SPV_OC_OpFUnordNotEqual, SPV_OC_OpFOrdLessThan,
-      SPV_OC_OpFUnordLessThan, SPV_OC_OpFOrdGreaterThan, SPV_OC_OpFUnordGreaterThan,
-      SPV_OC_OpFOrdLessThanEqual, SPV_OC_OpFUnordLessThanEqual,
-      SPV_OC_OpFOrdGreaterThanEqual, SPV_OC_OpFUnordGreaterThanEqual,
-      SPV_OC_OpShiftRightLogical, SPV_OC_OpShiftRightArithmetic,
-      SPV_OC_OpShiftLeftLogical, SPV_OC_OpBitwiseOr, SPV_OC_OpBitwiseXor,
-      SPV_OC_OpBitwiseAnd, SPV_OC_OpNot, SPV_OC_OpBitFieldInsert,
-      SPV_OC_OpBitFieldSExtract, SPV_OC_OpBitFieldUExtract, SPV_OC_OpBitReverse,
-      SPV_OC_OpBitCount, SPV_OC_OpControlBarrier, SPV_OC_OpMemoryBarrier,
-      SPV_OC_OpAtomicExchange, SPV_OC_OpAtomicCompareExchange,
-      SPV_OC_OpAtomicCompareExchangeWeak, SPV_OC_OpAtomicIIncrement,
-      SPV_OC_OpAtomicIDecrement, SPV_OC_OpAtomicIAdd, SPV_OC_OpAtomicISub,
-      SPV_OC_OpAtomicSMin, SPV_OC_OpAtomicUMin, SPV_OC_OpAtomicSMax,
-      SPV_OC_OpAtomicUMax, SPV_OC_OpAtomicAnd, SPV_OC_OpAtomicOr, SPV_OC_OpAtomicXor,
-      SPV_OC_OpPhi, SPV_OC_OpLoopMerge, SPV_OC_OpSelectionMerge, SPV_OC_OpLabel,
-      SPV_OC_OpBranch, SPV_OC_OpBranchConditional, SPV_OC_OpReturn,
-      SPV_OC_OpReturnValue, SPV_OC_OpUnreachable, SPV_OC_OpGroupBroadcast,
-      SPV_OC_OpNoLine, SPV_OC_OpModuleProcessed, SPV_OC_OpGroupNonUniformElect,
-      SPV_OC_OpGroupNonUniformBroadcast, SPV_OC_OpGroupNonUniformBallot,
-      SPV_OC_OpGroupNonUniformShuffle, SPV_OC_OpGroupNonUniformShuffleXor,
-      SPV_OC_OpGroupNonUniformShuffleUp, SPV_OC_OpGroupNonUniformShuffleDown,
-      SPV_OC_OpGroupNonUniformIAdd, SPV_OC_OpGroupNonUniformFAdd,
-      SPV_OC_OpGroupNonUniformIMul, SPV_OC_OpGroupNonUniformFMul,
-      SPV_OC_OpGroupNonUniformSMin, SPV_OC_OpGroupNonUniformUMin,
-      SPV_OC_OpGroupNonUniformFMin, SPV_OC_OpGroupNonUniformSMax,
-      SPV_OC_OpGroupNonUniformUMax, SPV_OC_OpGroupNonUniformFMax,
-      SPV_OC_OpSubgroupBallotKHR, SPV_OC_OpTypeCooperativeMatrixNV,
-      SPV_OC_OpCooperativeMatrixLoadNV, SPV_OC_OpCooperativeMatrixStoreNV,
-      SPV_OC_OpCooperativeMatrixMulAddNV, SPV_OC_OpCooperativeMatrixLengthNV,
-      SPV_OC_OpSubgroupBlockReadINTEL, SPV_OC_OpSubgroupBlockWriteINTEL,
-      SPV_OC_OpAssumeTrueKHR, SPV_OC_OpAtomicFAddEXT,
-
-      SPV_OC_OpTypeJointMatrixINTEL, SPV_OC_OpJointMatrixLoadINTEL,
-      SPV_OC_OpJointMatrixStoreINTEL, SPV_OC_OpJointMatrixMadINTEL,
-      SPV_OC_OpTypejointMatrixWorkItemLengthINTEL
+def SPIRV_OC_OpNop                        : I32EnumAttrCase<"OpNop", 0>;
+def SPIRV_OC_OpUndef                      : I32EnumAttrCase<"OpUndef", 1>;
+def SPIRV_OC_OpSourceContinued            : I32EnumAttrCase<"OpSourceContinued", 2>;
+def SPIRV_OC_OpSource                     : I32EnumAttrCase<"OpSource", 3>;
+def SPIRV_OC_OpSourceExtension            : I32EnumAttrCase<"OpSourceExtension", 4>;
+def SPIRV_OC_OpName                       : I32EnumAttrCase<"OpName", 5>;
+def SPIRV_OC_OpMemberName                 : I32EnumAttrCase<"OpMemberName", 6>;
+def SPIRV_OC_OpString                     : I32EnumAttrCase<"OpString", 7>;
+def SPIRV_OC_OpLine                       : I32EnumAttrCase<"OpLine", 8>;
+def SPIRV_OC_OpExtension                  : I32EnumAttrCase<"OpExtension", 10>;
+def SPIRV_OC_OpExtInstImport              : I32EnumAttrCase<"OpExtInstImport", 11>;
+def SPIRV_OC_OpExtInst                    : I32EnumAttrCase<"OpExtInst", 12>;
+def SPIRV_OC_OpMemoryModel                : I32EnumAttrCase<"OpMemoryModel", 14>;
+def SPIRV_OC_OpEntryPoint                 : I32EnumAttrCase<"OpEntryPoint", 15>;
+def SPIRV_OC_OpExecutionMode              : I32EnumAttrCase<"OpExecutionMode", 16>;
+def SPIRV_OC_OpCapability                 : I32EnumAttrCase<"OpCapability", 17>;
+def SPIRV_OC_OpTypeVoid                   : I32EnumAttrCase<"OpTypeVoid", 19>;
+def SPIRV_OC_OpTypeBool                   : I32EnumAttrCase<"OpTypeBool", 20>;
+def SPIRV_OC_OpTypeInt                    : I32EnumAttrCase<"OpTypeInt", 21>;
+def SPIRV_OC_OpTypeFloat                  : I32EnumAttrCase<"OpTypeFloat", 22>;
+def SPIRV_OC_OpTypeVector                 : I32EnumAttrCase<"OpTypeVector", 23>;
+def SPIRV_OC_OpTypeMatrix                 : I32EnumAttrCase<"OpTypeMatrix", 24>;
+def SPIRV_OC_OpTypeImage                  : I32EnumAttrCase<"OpTypeImage", 25>;
+def SPIRV_OC_OpTypeSampledImage           : I32EnumAttrCase<"OpTypeSampledImage", 27>;
+def SPIRV_OC_OpTypeArray                  : I32EnumAttrCase<"OpTypeArray", 28>;
+def SPIRV_OC_OpTypeRuntimeArray           : I32EnumAttrCase<"OpTypeRuntimeArray", 29>;
+def SPIRV_OC_OpTypeStruct                 : I32EnumAttrCase<"OpTypeStruct", 30>;
+def SPIRV_OC_OpTypePointer                : I32EnumAttrCase<"OpTypePointer", 32>;
+def SPIRV_OC_OpTypeFunction               : I32EnumAttrCase<"OpTypeFunction", 33>;
+def SPIRV_OC_OpTypeForwardPointer         : I32EnumAttrCase<"OpTypeForwardPointer", 39>;
+def SPIRV_OC_OpConstantTrue               : I32EnumAttrCase<"OpConstantTrue", 41>;
+def SPIRV_OC_OpConstantFalse              : I32EnumAttrCase<"OpConstantFalse", 42>;
+def SPIRV_OC_OpConstant                   : I32EnumAttrCase<"OpConstant", 43>;
+def SPIRV_OC_OpConstantComposite          : I32EnumAttrCase<"OpConstantComposite", 44>;
+def SPIRV_OC_OpConstantNull               : I32EnumAttrCase<"OpConstantNull", 46>;
+def SPIRV_OC_OpSpecConstantTrue           : I32EnumAttrCase<"OpSpecConstantTrue", 48>;
+def SPIRV_OC_OpSpecConstantFalse          : I32EnumAttrCase<"OpSpecConstantFalse", 49>;
+def SPIRV_OC_OpSpecConstant               : I32EnumAttrCase<"OpSpecConstant", 50>;
+def SPIRV_OC_OpSpecConstantComposite      : I32EnumAttrCase<"OpSpecConstantComposite", 51>;
+def SPIRV_OC_OpSpecConstantOp             : I32EnumAttrCase<"OpSpecConstantOp", 52>;
+def SPIRV_OC_OpFunction                   : I32EnumAttrCase<"OpFunction", 54>;
+def SPIRV_OC_OpFunctionParameter          : I32EnumAttrCase<"OpFunctionParameter", 55>;
+def SPIRV_OC_OpFunctionEnd                : I32EnumAttrCase<"OpFunctionEnd", 56>;
+def SPIRV_OC_OpFunctionCall               : I32EnumAttrCase<"OpFunctionCall", 57>;
+def SPIRV_OC_OpVariable                   : I32EnumAttrCase<"OpVariable", 59>;
+def SPIRV_OC_OpLoad                       : I32EnumAttrCase<"OpLoad", 61>;
+def SPIRV_OC_OpStore                      : I32EnumAttrCase<"OpStore", 62>;
+def SPIRV_OC_OpCopyMemory                 : I32EnumAttrCase<"OpCopyMemory", 63>;
+def SPIRV_OC_OpAccessChain                : I32EnumAttrCase<"OpAccessChain", 65>;
+def SPIRV_OC_OpPtrAccessChain             : I32EnumAttrCase<"OpPtrAccessChain", 67>;
+def SPIRV_OC_OpInBoundsPtrAccessChain     : I32EnumAttrCase<"OpInBoundsPtrAccessChain", 70>;
+def SPIRV_OC_OpDecorate                   : I32EnumAttrCase<"OpDecorate", 71>;
+def SPIRV_OC_OpMemberDecorate             : I32EnumAttrCase<"OpMemberDecorate", 72>;
+def SPIRV_OC_OpVectorExtractDynamic       : I32EnumAttrCase<"OpVectorExtractDynamic", 77>;
+def SPIRV_OC_OpVectorInsertDynamic        : I32EnumAttrCase<"OpVectorInsertDynamic", 78>;
+def SPIRV_OC_OpVectorShuffle              : I32EnumAttrCase<"OpVectorShuffle", 79>;
+def SPIRV_OC_OpCompositeConstruct         : I32EnumAttrCase<"OpCompositeConstruct", 80>;
+def SPIRV_OC_OpCompositeExtract           : I32EnumAttrCase<"OpCompositeExtract", 81>;
+def SPIRV_OC_OpCompositeInsert            : I32EnumAttrCase<"OpCompositeInsert", 82>;
+def SPIRV_OC_OpTranspose                  : I32EnumAttrCase<"OpTranspose", 84>;
+def SPIRV_OC_OpImageDrefGather            : I32EnumAttrCase<"OpImageDrefGather", 97>;
+def SPIRV_OC_OpImage                      : I32EnumAttrCase<"OpImage", 100>;
+def SPIRV_OC_OpImageQuerySize             : I32EnumAttrCase<"OpImageQuerySize", 104>;
+def SPIRV_OC_OpConvertFToU                : I32EnumAttrCase<"OpConvertFToU", 109>;
+def SPIRV_OC_OpConvertFToS                : I32EnumAttrCase<"OpConvertFToS", 110>;
+def SPIRV_OC_OpConvertSToF                : I32EnumAttrCase<"OpConvertSToF", 111>;
+def SPIRV_OC_OpConvertUToF                : I32EnumAttrCase<"OpConvertUToF", 112>;
+def SPIRV_OC_OpUConvert                   : I32EnumAttrCase<"OpUConvert", 113>;
+def SPIRV_OC_OpSConvert                   : I32EnumAttrCase<"OpSConvert", 114>;
+def SPIRV_OC_OpFConvert                   : I32EnumAttrCase<"OpFConvert", 115>;
+def SPIRV_OC_OpPtrCastToGeneric           : I32EnumAttrCase<"OpPtrCastToGeneric", 121>;
+def SPIRV_OC_OpGenericCastToPtr           : I32EnumAttrCase<"OpGenericCastToPtr", 122>;
+def SPIRV_OC_OpGenericCastToPtrExplicit   : I32EnumAttrCase<"OpGenericCastToPtrExplicit", 123>;
+def SPIRV_OC_OpBitcast                    : I32EnumAttrCase<"OpBitcast", 124>;
+def SPIRV_OC_OpSNegate                    : I32EnumAttrCase<"OpSNegate", 126>;
+def SPIRV_OC_OpFNegate                    : I32EnumAttrCase<"OpFNegate", 127>;
+def SPIRV_OC_OpIAdd                       : I32EnumAttrCase<"OpIAdd", 128>;
+def SPIRV_OC_OpFAdd                       : I32EnumAttrCase<"OpFAdd", 129>;
+def SPIRV_OC_OpISub                       : I32EnumAttrCase<"OpISub", 130>;
+def SPIRV_OC_OpFSub                       : I32EnumAttrCase<"OpFSub", 131>;
+def SPIRV_OC_OpIMul                       : I32EnumAttrCase<"OpIMul", 132>;
+def SPIRV_OC_OpFMul                       : I32EnumAttrCase<"OpFMul", 133>;
+def SPIRV_OC_OpUDiv                       : I32EnumAttrCase<"OpUDiv", 134>;
+def SPIRV_OC_OpSDiv                       : I32EnumAttrCase<"OpSDiv", 135>;
+def SPIRV_OC_OpFDiv                       : I32EnumAttrCase<"OpFDiv", 136>;
+def SPIRV_OC_OpUMod                       : I32EnumAttrCase<"OpUMod", 137>;
+def SPIRV_OC_OpSRem                       : I32EnumAttrCase<"OpSRem", 138>;
+def SPIRV_OC_OpSMod                       : I32EnumAttrCase<"OpSMod", 139>;
+def SPIRV_OC_OpFRem                       : I32EnumAttrCase<"OpFRem", 140>;
+def SPIRV_OC_OpFMod                       : I32EnumAttrCase<"OpFMod", 141>;
+def SPIRV_OC_OpVectorTimesScalar          : I32EnumAttrCase<"OpVectorTimesScalar", 142>;
+def SPIRV_OC_OpMatrixTimesScalar          : I32EnumAttrCase<"OpMatrixTimesScalar", 143>;
+def SPIRV_OC_OpMatrixTimesMatrix          : I32EnumAttrCase<"OpMatrixTimesMatrix", 146>;
+def SPIRV_OC_OpIAddCarry                  : I32EnumAttrCase<"OpIAddCarry", 149>;
+def SPIRV_OC_OpISubBorrow                 : I32EnumAttrCase<"OpISubBorrow", 150>;
+def SPIRV_OC_OpIsNan                      : I32EnumAttrCase<"OpIsNan", 156>;
+def SPIRV_OC_OpIsInf                      : I32EnumAttrCase<"OpIsInf", 157>;
+def SPIRV_OC_OpOrdered                    : I32EnumAttrCase<"OpOrdered", 162>;
+def SPIRV_OC_OpUnordered                  : I32EnumAttrCase<"OpUnordered", 163>;
+def SPIRV_OC_OpLogicalEqual               : I32EnumAttrCase<"OpLogicalEqual", 164>;
+def SPIRV_OC_OpLogicalNotEqual            : I32EnumAttrCase<"OpLogicalNotEqual", 165>;
+def SPIRV_OC_OpLogicalOr                  : I32EnumAttrCase<"OpLogicalOr", 166>;
+def SPIRV_OC_OpLogicalAnd                 : I32EnumAttrCase<"OpLogicalAnd", 167>;
+def SPIRV_OC_OpLogicalNot                 : I32EnumAttrCase<"OpLogicalNot", 168>;
+def SPIRV_OC_OpSelect                     : I32EnumAttrCase<"OpSelect", 169>;
+def SPIRV_OC_OpIEqual                     : I32EnumAttrCase<"OpIEqual", 170>;
+def SPIRV_OC_OpINotEqual                  : I32EnumAttrCase<"OpINotEqual", 171>;
+def SPIRV_OC_OpUGreaterThan               : I32EnumAttrCase<"OpUGreaterThan", 172>;
+def SPIRV_OC_OpSGreaterThan               : I32EnumAttrCase<"OpSGreaterThan", 173>;
+def SPIRV_OC_OpUGreaterThanEqual          : I32EnumAttrCase<"OpUGreaterThanEqual", 174>;
+def SPIRV_OC_OpSGreaterThanEqual          : I32EnumAttrCase<"OpSGreaterThanEqual", 175>;
+def SPIRV_OC_OpULessThan                  : I32EnumAttrCase<"OpULessThan", 176>;
+def SPIRV_OC_OpSLessThan                  : I32EnumAttrCase<"OpSLessThan", 177>;
+def SPIRV_OC_OpULessThanEqual             : I32EnumAttrCase<"OpULessThanEqual", 178>;
+def SPIRV_OC_OpSLessThanEqual             : I32EnumAttrCase<"OpSLessThanEqual", 179>;
+def SPIRV_OC_OpFOrdEqual                  : I32EnumAttrCase<"OpFOrdEqual", 180>;
+def SPIRV_OC_OpFUnordEqual                : I32EnumAttrCase<"OpFUnordEqual", 181>;
+def SPIRV_OC_OpFOrdNotEqual               : I32EnumAttrCase<"OpFOrdNotEqual", 182>;
+def SPIRV_OC_OpFUnordNotEqual             : I32EnumAttrCase<"OpFUnordNotEqual", 183>;
+def SPIRV_OC_OpFOrdLessThan               : I32EnumAttrCase<"OpFOrdLessThan", 184>;
+def SPIRV_OC_OpFUnordLessThan             : I32EnumAttrCase<"OpFUnordLessThan", 185>;
+def SPIRV_OC_OpFOrdGreaterThan            : I32EnumAttrCase<"OpFOrdGreaterThan", 186>;
+def SPIRV_OC_OpFUnordGreaterThan          : I32EnumAttrCase<"OpFUnordGreaterThan", 187>;
+def SPIRV_OC_OpFOrdLessThanEqual          : I32EnumAttrCase<"OpFOrdLessThanEqual", 188>;
+def SPIRV_OC_OpFUnordLessThanEqual        : I32EnumAttrCase<"OpFUnordLessThanEqual", 189>;
+def SPIRV_OC_OpFOrdGreaterThanEqual       : I32EnumAttrCase<"OpFOrdGreaterThanEqual", 190>;
+def SPIRV_OC_OpFUnordGreaterThanEqual     : I32EnumAttrCase<"OpFUnordGreaterThanEqual", 191>;
+def SPIRV_OC_OpShiftRightLogical          : I32EnumAttrCase<"OpShiftRightLogical", 194>;
+def SPIRV_OC_OpShiftRightArithmetic       : I32EnumAttrCase<"OpShiftRightArithmetic", 195>;
+def SPIRV_OC_OpShiftLeftLogical           : I32EnumAttrCase<"OpShiftLeftLogical", 196>;
+def SPIRV_OC_OpBitwiseOr                  : I32EnumAttrCase<"OpBitwiseOr", 197>;
+def SPIRV_OC_OpBitwiseXor                 : I32EnumAttrCase<"OpBitwiseXor", 198>;
+def SPIRV_OC_OpBitwiseAnd                 : I32EnumAttrCase<"OpBitwiseAnd", 199>;
+def SPIRV_OC_OpNot                        : I32EnumAttrCase<"OpNot", 200>;
+def SPIRV_OC_OpBitFieldInsert             : I32EnumAttrCase<"OpBitFieldInsert", 201>;
+def SPIRV_OC_OpBitFieldSExtract           : I32EnumAttrCase<"OpBitFieldSExtract", 202>;
+def SPIRV_OC_OpBitFieldUExtract           : I32EnumAttrCase<"OpBitFieldUExtract", 203>;
+def SPIRV_OC_OpBitReverse                 : I32EnumAttrCase<"OpBitReverse", 204>;
+def SPIRV_OC_OpBitCount                   : I32EnumAttrCase<"OpBitCount", 205>;
+def SPIRV_OC_OpControlBarrier             : I32EnumAttrCase<"OpControlBarrier", 224>;
+def SPIRV_OC_OpMemoryBarrier              : I32EnumAttrCase<"OpMemoryBarrier", 225>;
+def SPIRV_OC_OpAtomicExchange             : I32EnumAttrCase<"OpAtomicExchange", 229>;
+def SPIRV_OC_OpAtomicCompareExchange      : I32EnumAttrCase<"OpAtomicCompareExchange", 230>;
+def SPIRV_OC_OpAtomicCompareExchangeWeak  : I32EnumAttrCase<"OpAtomicCompareExchangeWeak", 231>;
+def SPIRV_OC_OpAtomicIIncrement           : I32EnumAttrCase<"OpAtomicIIncrement", 232>;
+def SPIRV_OC_OpAtomicIDecrement           : I32EnumAttrCase<"OpAtomicIDecrement", 233>;
+def SPIRV_OC_OpAtomicIAdd                 : I32EnumAttrCase<"OpAtomicIAdd", 234>;
+def SPIRV_OC_OpAtomicISub                 : I32EnumAttrCase<"OpAtomicISub", 235>;
+def SPIRV_OC_OpAtomicSMin                 : I32EnumAttrCase<"OpAtomicSMin", 236>;
+def SPIRV_OC_OpAtomicUMin                 : I32EnumAttrCase<"OpAtomicUMin", 237>;
+def SPIRV_OC_OpAtomicSMax                 : I32EnumAttrCase<"OpAtomicSMax", 238>;
+def SPIRV_OC_OpAtomicUMax                 : I32EnumAttrCase<"OpAtomicUMax", 239>;
+def SPIRV_OC_OpAtomicAnd                  : I32EnumAttrCase<"OpAtomicAnd", 240>;
+def SPIRV_OC_OpAtomicOr                   : I32EnumAttrCase<"OpAtomicOr", 241>;
+def SPIRV_OC_OpAtomicXor                  : I32EnumAttrCase<"OpAtomicXor", 242>;
+def SPIRV_OC_OpPhi                        : I32EnumAttrCase<"OpPhi", 245>;
+def SPIRV_OC_OpLoopMerge                  : I32EnumAttrCase<"OpLoopMerge", 246>;
+def SPIRV_OC_OpSelectionMerge             : I32EnumAttrCase<"OpSelectionMerge", 247>;
+def SPIRV_OC_OpLabel                      : I32EnumAttrCase<"OpLabel", 248>;
+def SPIRV_OC_OpBranch                     : I32EnumAttrCase<"OpBranch", 249>;
+def SPIRV_OC_OpBranchConditional          : I32EnumAttrCase<"OpBranchConditional", 250>;
+def SPIRV_OC_OpReturn                     : I32EnumAttrCase<"OpReturn", 253>;
+def SPIRV_OC_OpReturnValue                : I32EnumAttrCase<"OpReturnValue", 254>;
+def SPIRV_OC_OpUnreachable                : I32EnumAttrCase<"OpUnreachable", 255>;
+def SPIRV_OC_OpGroupBroadcast             : I32EnumAttrCase<"OpGroupBroadcast", 263>;
+def SPIRV_OC_OpNoLine                     : I32EnumAttrCase<"OpNoLine", 317>;
+def SPIRV_OC_OpModuleProcessed            : I32EnumAttrCase<"OpModuleProcessed", 330>;
+def SPIRV_OC_OpGroupNonUniformElect       : I32EnumAttrCase<"OpGroupNonUniformElect", 333>;
+def SPIRV_OC_OpGroupNonUniformBroadcast   : I32EnumAttrCase<"OpGroupNonUniformBroadcast", 337>;
+def SPIRV_OC_OpGroupNonUniformBallot      : I32EnumAttrCase<"OpGroupNonUniformBallot", 339>;
+def SPIRV_OC_OpGroupNonUniformShuffle     : I32EnumAttrCase<"OpGroupNonUniformShuffle", 345>;
+def SPIRV_OC_OpGroupNonUniformShuffleXor  : I32EnumAttrCase<"OpGroupNonUniformShuffleXor", 346>;
+def SPIRV_OC_OpGroupNonUniformShuffleUp   : I32EnumAttrCase<"OpGroupNonUniformShuffleUp", 347>;
+def SPIRV_OC_OpGroupNonUniformShuffleDown : I32EnumAttrCase<"OpGroupNonUniformShuffleDown", 348>;
+def SPIRV_OC_OpGroupNonUniformIAdd        : I32EnumAttrCase<"OpGroupNonUniformIAdd", 349>;
+def SPIRV_OC_OpGroupNonUniformFAdd        : I32EnumAttrCase<"OpGroupNonUniformFAdd", 350>;
+def SPIRV_OC_OpGroupNonUniformIMul        : I32EnumAttrCase<"OpGroupNonUniformIMul", 351>;
+def SPIRV_OC_OpGroupNonUniformFMul        : I32EnumAttrCase<"OpGroupNonUniformFMul", 352>;
+def SPIRV_OC_OpGroupNonUniformSMin        : I32EnumAttrCase<"OpGroupNonUniformSMin", 353>;
+def SPIRV_OC_OpGroupNonUniformUMin        : I32EnumAttrCase<"OpGroupNonUniformUMin", 354>;
+def SPIRV_OC_OpGroupNonUniformFMin        : I32EnumAttrCase<"OpGroupNonUniformFMin", 355>;
+def SPIRV_OC_OpGroupNonUniformSMax        : I32EnumAttrCase<"OpGroupNonUniformSMax", 356>;
+def SPIRV_OC_OpGroupNonUniformUMax        : I32EnumAttrCase<"OpGroupNonUniformUMax", 357>;
+def SPIRV_OC_OpGroupNonUniformFMax        : I32EnumAttrCase<"OpGroupNonUniformFMax", 358>;
+def SPIRV_OC_OpSubgroupBallotKHR          : I32EnumAttrCase<"OpSubgroupBallotKHR", 4421>;
+def SPIRV_OC_OpTypeCooperativeMatrixNV    : I32EnumAttrCase<"OpTypeCooperativeMatrixNV", 5358>;
+def SPIRV_OC_OpCooperativeMatrixLoadNV    : I32EnumAttrCase<"OpCooperativeMatrixLoadNV", 5359>;
+def SPIRV_OC_OpCooperativeMatrixStoreNV   : I32EnumAttrCase<"OpCooperativeMatrixStoreNV", 5360>;
+def SPIRV_OC_OpCooperativeMatrixMulAddNV  : I32EnumAttrCase<"OpCooperativeMatrixMulAddNV", 5361>;
+def SPIRV_OC_OpCooperativeMatrixLengthNV  : I32EnumAttrCase<"OpCooperativeMatrixLengthNV", 5362>;
+def SPIRV_OC_OpSubgroupBlockReadINTEL     : I32EnumAttrCase<"OpSubgroupBlockReadINTEL", 5575>;
+def SPIRV_OC_OpSubgroupBlockWriteINTEL    : I32EnumAttrCase<"OpSubgroupBlockWriteINTEL", 5576>;
+def SPIRV_OC_OpAssumeTrueKHR              : I32EnumAttrCase<"OpAssumeTrueKHR", 5630>;
+def SPIRV_OC_OpAtomicFAddEXT              : I32EnumAttrCase<"OpAtomicFAddEXT", 6035>;
+
+def SPIRV_OC_OpTypeJointMatrixINTEL       : I32EnumAttrCase<"OpTypeJointMatrixINTEL", 6119>;
+def SPIRV_OC_OpJointMatrixLoadINTEL       : I32EnumAttrCase<"OpJointMatrixLoadINTEL", 6120>;
+def SPIRV_OC_OpJointMatrixStoreINTEL      : I32EnumAttrCase<"OpJointMatrixStoreINTEL", 6121>;
+def SPIRV_OC_OpJointMatrixMadINTEL        : I32EnumAttrCase<"OpJointMatrixMadINTEL", 6122>;
+def SPIRV_OC_OpTypejointMatrixWorkItemLengthINTEL : I32EnumAttrCase<"OpJointMatrixWorkItemLengthINTEL", 6410>;
+
+def SPIRV_OpcodeAttr :
+    SPIRV_I32EnumAttr<"Opcode", "valid SPIR-V instructions", "opcode", [
+      SPIRV_OC_OpNop, SPIRV_OC_OpUndef, SPIRV_OC_OpSourceContinued, SPIRV_OC_OpSource,
+      SPIRV_OC_OpSourceExtension, SPIRV_OC_OpName, SPIRV_OC_OpMemberName, SPIRV_OC_OpString,
+      SPIRV_OC_OpLine, SPIRV_OC_OpExtension, SPIRV_OC_OpExtInstImport, SPIRV_OC_OpExtInst,
+      SPIRV_OC_OpMemoryModel, SPIRV_OC_OpEntryPoint, SPIRV_OC_OpExecutionMode,
+      SPIRV_OC_OpCapability, SPIRV_OC_OpTypeVoid, SPIRV_OC_OpTypeBool, SPIRV_OC_OpTypeInt,
+      SPIRV_OC_OpTypeFloat, SPIRV_OC_OpTypeVector, SPIRV_OC_OpTypeMatrix,
+      SPIRV_OC_OpTypeImage, SPIRV_OC_OpTypeSampledImage, SPIRV_OC_OpTypeArray,
+      SPIRV_OC_OpTypeRuntimeArray, SPIRV_OC_OpTypeStruct, SPIRV_OC_OpTypePointer,
+      SPIRV_OC_OpTypeFunction, SPIRV_OC_OpTypeForwardPointer, SPIRV_OC_OpConstantTrue,
+      SPIRV_OC_OpConstantFalse, SPIRV_OC_OpConstant, SPIRV_OC_OpConstantComposite,
+      SPIRV_OC_OpConstantNull, SPIRV_OC_OpSpecConstantTrue, SPIRV_OC_OpSpecConstantFalse,
+      SPIRV_OC_OpSpecConstant, SPIRV_OC_OpSpecConstantComposite, SPIRV_OC_OpSpecConstantOp,
+      SPIRV_OC_OpFunction, SPIRV_OC_OpFunctionParameter, SPIRV_OC_OpFunctionEnd,
+      SPIRV_OC_OpFunctionCall, SPIRV_OC_OpVariable, SPIRV_OC_OpLoad, SPIRV_OC_OpStore,
+      SPIRV_OC_OpCopyMemory, SPIRV_OC_OpAccessChain, SPIRV_OC_OpPtrAccessChain,
+      SPIRV_OC_OpInBoundsPtrAccessChain, SPIRV_OC_OpDecorate, SPIRV_OC_OpMemberDecorate,
+      SPIRV_OC_OpVectorExtractDynamic, SPIRV_OC_OpVectorInsertDynamic,
+      SPIRV_OC_OpVectorShuffle, SPIRV_OC_OpCompositeConstruct, SPIRV_OC_OpCompositeExtract,
+      SPIRV_OC_OpCompositeInsert, SPIRV_OC_OpTranspose, SPIRV_OC_OpImageDrefGather,
+      SPIRV_OC_OpImage, SPIRV_OC_OpImageQuerySize, SPIRV_OC_OpConvertFToU,
+      SPIRV_OC_OpConvertFToS, SPIRV_OC_OpConvertSToF, SPIRV_OC_OpConvertUToF,
+      SPIRV_OC_OpUConvert, SPIRV_OC_OpSConvert, SPIRV_OC_OpFConvert, SPIRV_OC_OpPtrCastToGeneric, 
+      SPIRV_OC_OpGenericCastToPtr, SPIRV_OC_OpGenericCastToPtrExplicit, SPIRV_OC_OpBitcast,
+      SPIRV_OC_OpSNegate, SPIRV_OC_OpFNegate, SPIRV_OC_OpIAdd, SPIRV_OC_OpFAdd,
+      SPIRV_OC_OpISub, SPIRV_OC_OpFSub, SPIRV_OC_OpIMul, SPIRV_OC_OpFMul, SPIRV_OC_OpUDiv,
+      SPIRV_OC_OpSDiv, SPIRV_OC_OpFDiv, SPIRV_OC_OpUMod, SPIRV_OC_OpSRem, SPIRV_OC_OpSMod,
+      SPIRV_OC_OpFRem, SPIRV_OC_OpFMod, SPIRV_OC_OpVectorTimesScalar,
+      SPIRV_OC_OpMatrixTimesScalar, SPIRV_OC_OpMatrixTimesMatrix, SPIRV_OC_OpIAddCarry,
+      SPIRV_OC_OpISubBorrow, SPIRV_OC_OpIsNan, SPIRV_OC_OpIsInf, SPIRV_OC_OpOrdered,
+      SPIRV_OC_OpUnordered, SPIRV_OC_OpLogicalEqual, SPIRV_OC_OpLogicalNotEqual,
+      SPIRV_OC_OpLogicalOr, SPIRV_OC_OpLogicalAnd, SPIRV_OC_OpLogicalNot, SPIRV_OC_OpSelect,
+      SPIRV_OC_OpIEqual, SPIRV_OC_OpINotEqual, SPIRV_OC_OpUGreaterThan,
+      SPIRV_OC_OpSGreaterThan, SPIRV_OC_OpUGreaterThanEqual, SPIRV_OC_OpSGreaterThanEqual,
+      SPIRV_OC_OpULessThan, SPIRV_OC_OpSLessThan, SPIRV_OC_OpULessThanEqual,
+      SPIRV_OC_OpSLessThanEqual, SPIRV_OC_OpFOrdEqual, SPIRV_OC_OpFUnordEqual,
+      SPIRV_OC_OpFOrdNotEqual, SPIRV_OC_OpFUnordNotEqual, SPIRV_OC_OpFOrdLessThan,
+      SPIRV_OC_OpFUnordLessThan, SPIRV_OC_OpFOrdGreaterThan, SPIRV_OC_OpFUnordGreaterThan,
+      SPIRV_OC_OpFOrdLessThanEqual, SPIRV_OC_OpFUnordLessThanEqual,
+      SPIRV_OC_OpFOrdGreaterThanEqual, SPIRV_OC_OpFUnordGreaterThanEqual,
+      SPIRV_OC_OpShiftRightLogical, SPIRV_OC_OpShiftRightArithmetic,
+      SPIRV_OC_OpShiftLeftLogical, SPIRV_OC_OpBitwiseOr, SPIRV_OC_OpBitwiseXor,
+      SPIRV_OC_OpBitwiseAnd, SPIRV_OC_OpNot, SPIRV_OC_OpBitFieldInsert,
+      SPIRV_OC_OpBitFieldSExtract, SPIRV_OC_OpBitFieldUExtract, SPIRV_OC_OpBitReverse,
+      SPIRV_OC_OpBitCount, SPIRV_OC_OpControlBarrier, SPIRV_OC_OpMemoryBarrier,
+      SPIRV_OC_OpAtomicExchange, SPIRV_OC_OpAtomicCompareExchange,
+      SPIRV_OC_OpAtomicCompareExchangeWeak, SPIRV_OC_OpAtomicIIncrement,
+      SPIRV_OC_OpAtomicIDecrement, SPIRV_OC_OpAtomicIAdd, SPIRV_OC_OpAtomicISub,
+      SPIRV_OC_OpAtomicSMin, SPIRV_OC_OpAtomicUMin, SPIRV_OC_OpAtomicSMax,
+      SPIRV_OC_OpAtomicUMax, SPIRV_OC_OpAtomicAnd, SPIRV_OC_OpAtomicOr, SPIRV_OC_OpAtomicXor,
+      SPIRV_OC_OpPhi, SPIRV_OC_OpLoopMerge, SPIRV_OC_OpSelectionMerge, SPIRV_OC_OpLabel,
+      SPIRV_OC_OpBranch, SPIRV_OC_OpBranchConditional, SPIRV_OC_OpReturn,
+      SPIRV_OC_OpReturnValue, SPIRV_OC_OpUnreachable, SPIRV_OC_OpGroupBroadcast,
+      SPIRV_OC_OpNoLine, SPIRV_OC_OpModuleProcessed, SPIRV_OC_OpGroupNonUniformElect,
+      SPIRV_OC_OpGroupNonUniformBroadcast, SPIRV_OC_OpGroupNonUniformBallot,
+      SPIRV_OC_OpGroupNonUniformShuffle, SPIRV_OC_OpGroupNonUniformShuffleXor,
+      SPIRV_OC_OpGroupNonUniformShuffleUp, SPIRV_OC_OpGroupNonUniformShuffleDown,
+      SPIRV_OC_OpGroupNonUniformIAdd, SPIRV_OC_OpGroupNonUniformFAdd,
+      SPIRV_OC_OpGroupNonUniformIMul, SPIRV_OC_OpGroupNonUniformFMul,
+      SPIRV_OC_OpGroupNonUniformSMin, SPIRV_OC_OpGroupNonUniformUMin,
+      SPIRV_OC_OpGroupNonUniformFMin, SPIRV_OC_OpGroupNonUniformSMax,
+      SPIRV_OC_OpGroupNonUniformUMax, SPIRV_OC_OpGroupNonUniformFMax,
+      SPIRV_OC_OpSubgroupBallotKHR, SPIRV_OC_OpTypeCooperativeMatrixNV,
+      SPIRV_OC_OpCooperativeMatrixLoadNV, SPIRV_OC_OpCooperativeMatrixStoreNV,
+      SPIRV_OC_OpCooperativeMatrixMulAddNV, SPIRV_OC_OpCooperativeMatrixLengthNV,
+      SPIRV_OC_OpSubgroupBlockReadINTEL, SPIRV_OC_OpSubgroupBlockWriteINTEL,
+      SPIRV_OC_OpAssumeTrueKHR, SPIRV_OC_OpAtomicFAddEXT,
+
+      SPIRV_OC_OpTypeJointMatrixINTEL, SPIRV_OC_OpJointMatrixLoadINTEL,
+      SPIRV_OC_OpJointMatrixStoreINTEL, SPIRV_OC_OpJointMatrixMadINTEL,
+      SPIRV_OC_OpTypejointMatrixWorkItemLengthINTEL
     ]>;
 
 // End opcode section. Generated from SPIR-V spec; DO NOT MODIFY!
 
 //===----------------------------------------------------------------------===//
 // SPIR-V op definitions
 //===----------------------------------------------------------------------===//
 
 // Base class for all SPIR-V ops.
-class SPV_Op<string mnemonic, list<Trait> traits = []> :
+class SPIRV_Op<string mnemonic, list<Trait> traits = []> :
     Op<SPIRV_Dialect, mnemonic, !listconcat(traits, [
          // TODO: We don't need all of the following traits for every op; only
          // the suitable ones should be added automatically after ODS supports
          // dialect-specific contents.
          DeclareOpInterfaceMethods<QueryMinVersionInterface>,
          DeclareOpInterfaceMethods<QueryMaxVersionInterface>,
          DeclareOpInterfaceMethods<QueryExtensionInterface>,
          DeclareOpInterfaceMethods<QueryCapabilityInterface>
        ])> {
   // Availability specification for this op itself.
   list<Availability> availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
     Capability<[]>
   ];
 
   // For each SPIR-V op, the following static functions need to be defined
-  // in SPVOps.cpp:
+  // in SPIRVOps.cpp:
   //
   // * ParseResult <op-c++-class-name>::parse(OpAsmParser &parser,
   //                                          OperationState &result)
   // * void <op-c++-class-name>::print(OpAsmPrinter &p)
   // * LogicalResult <op-c++-class-name>::verify()
   let hasCustomAssemblyFormat = 1;
   let hasVerifier = 1;
 
class SPIRV_Op<string mnemonic, list<Trait> traits = []> :
   //
   // Note:
   // 1) If hasOpcode is set but autogenSerialization is not set, the
   //    (de)serializer dispatch method still calls the above method for
   //    (de)serializing this op.
   // 2) If hasOpcode is not set, but autogenSerialization is set, the
   //    above methods for (de)serialization are generated, but there is no
   //    entry added in the dispatch tables to invoke these methods. The
-  //    dispatch needs to be handled manually. SPV_ExtInstOps are an
+  //    dispatch needs to be handled manually. SPIRV_ExtInstOps are an
   //    example of this.
   bit autogenSerialization = 1;
 }
 
-class SPV_UnaryOp<string mnemonic, Type resultType, Type operandType,
+class SPIRV_UnaryOp<string mnemonic, Type resultType, Type operandType,
                     list<Trait> traits = []> :
-      SPV_Op<mnemonic, traits> {
+      SPIRV_Op<mnemonic, traits> {
   let arguments = (ins
-    SPV_ScalarOrVectorOf<operandType>:$operand
+    SPIRV_ScalarOrVectorOf<operandType>:$operand
   );
 
   let results = (outs
-    SPV_ScalarOrVectorOf<resultType>:$result
+    SPIRV_ScalarOrVectorOf<resultType>:$result
   );
 
   let assemblyFormat = "$operand `:` type($operand) attr-dict";
   // No additional verification needed in addition to the ODS-generated ones.
   let hasVerifier = 0;
 }
 
-class SPV_BinaryOp<string mnemonic, Type resultType, Type operandsType,
+class SPIRV_BinaryOp<string mnemonic, Type resultType, Type operandsType,
                      list<Trait> traits = []> :
-      SPV_Op<mnemonic, traits> {
+      SPIRV_Op<mnemonic, traits> {
   let arguments = (ins
-    SPV_ScalarOrVectorOf<operandsType>:$operand1,
-    SPV_ScalarOrVectorOf<operandsType>:$operand2
+    SPIRV_ScalarOrVectorOf<operandsType>:$operand1,
+    SPIRV_ScalarOrVectorOf<operandsType>:$operand2
   );
 
   let results = (outs
-    SPV_ScalarOrVectorOf<resultType>:$result
+    SPIRV_ScalarOrVectorOf<resultType>:$result
   );
 
   // No additional verification needed in addition to the ODS-generated ones.
   let hasVerifier = 0;
 }
 
-class SPV_ExtInstOp<string mnemonic, string setPrefix, string setName,
+class SPIRV_ExtInstOp<string mnemonic, string setPrefix, string setName,
                       int opcode, list<Trait> traits = []> :
-  SPV_Op<setPrefix # "." # mnemonic, traits> {
+  SPIRV_Op<setPrefix # "." # mnemonic, traits> {
 
   // Extended instruction sets have no direct opcode (they share the
   // same `OpExtInst` instruction). So the hasOpcode field is set to
   // false. So no entry corresponding to these ops are added in the
   // dispatch functions for (de)serialization. The methods for
   // (de)serialization are still automatically generated (since
   // autogenSerialization remains 1). A separate method is generated
   // for dispatching extended instruction set ops.
   let hasOpcode = 0;
 
   // Opcode within extended instruction set.
   int extendedInstOpcode = opcode;
 
   // Name used to import the extended instruction set.
   string extendedInstSetName = setName;
 }
 
 // Base classes for SPIR-V vendor ops. These have opcode in the form of
 // Op<Name><VENDOR>, e.g., OpCooperativeMatrixStoreNV.
-class SPV_VendorOp<string mnemonic, string vendorName,
+class SPIRV_VendorOp<string mnemonic, string vendorName,
                      list<Trait> traits = []> :
-  SPV_Op<vendorName # "." # mnemonic, traits> {
+  SPIRV_Op<vendorName # "." # mnemonic, traits> {
   string spirvOpName = "Op" # mnemonic # vendorName;
 }
 
-class SPV_ExtVendorOp<string mnemonic, list<Trait> traits = []> :
-  SPV_VendorOp<mnemonic, "EXT", traits> {
+class SPIRV_ExtVendorOp<string mnemonic, list<Trait> traits = []> :
+  SPIRV_VendorOp<mnemonic, "EXT", traits> {
 }
 
-class SPV_KhrVendorOp<string mnemonic, list<Trait> traits = []> :
-  SPV_VendorOp<mnemonic, "KHR", traits> {
+class SPIRV_KhrVendorOp<string mnemonic, list<Trait> traits = []> :
+  SPIRV_VendorOp<mnemonic, "KHR", traits> {
 }
 
-class SPV_IntelVendorOp<string mnemonic, list<Trait> traits = []> :
-  SPV_VendorOp<mnemonic, "INTEL", traits> {
+class SPIRV_IntelVendorOp<string mnemonic, list<Trait> traits = []> :
+  SPIRV_VendorOp<mnemonic, "INTEL", traits> {
 }
 
-class SPV_NvVendorOp<string mnemonic, list<Trait> traits = []> :
-  SPV_VendorOp<mnemonic, "NV", traits> {
+class SPIRV_NvVendorOp<string mnemonic, list<Trait> traits = []> :
+  SPIRV_VendorOp<mnemonic, "NV", traits> {
 }
 
 #endif // MLIR_DIALECT_SPIRV_IR_BASE

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td

 //===----------------------------------------------------------------------===//
 
 #ifndef MLIR_DIALECT_SPIRV_IR_BIT_OPS
 #define MLIR_DIALECT_SPIRV_IR_BIT_OPS
 
 include "mlir/Dialect/SPIRV/IR/SPIRVBase.td"
 include "mlir/Interfaces/SideEffectInterfaces.td"
 
-class SPV_BitBinaryOp<string mnemonic, list<Trait> traits = []> :
-      // All the operands type used in bit instructions are SPV_Integer.
-      SPV_BinaryOp<mnemonic, SPV_Integer, SPV_Integer,
+class SPIRV_BitBinaryOp<string mnemonic, list<Trait> traits = []> :
+      // All the operands type used in bit instructions are SPIRV_Integer.
+      SPIRV_BinaryOp<mnemonic, SPIRV_Integer, SPIRV_Integer,
                    !listconcat(traits,
-                               [NoSideEffect, SameOperandsAndResultType])> {                                 
+                               [NoSideEffect, SameOperandsAndResultType])> {
   let assemblyFormat = "operands attr-dict `:` type($result)";
 }
 
-class SPV_BitFieldExtractOp<string mnemonic, list<Trait> traits = []> :
-      SPV_Op<mnemonic, !listconcat(traits,
+class SPIRV_BitFieldExtractOp<string mnemonic, list<Trait> traits = []> :
+      SPIRV_Op<mnemonic, !listconcat(traits,
              [NoSideEffect, AllTypesMatch<["base", "result"]>])> {
   let arguments = (ins
-    SPV_ScalarOrVectorOf<SPV_Integer>:$base,
-    SPV_Integer:$offset,
-    SPV_Integer:$count
+    SPIRV_ScalarOrVectorOf<SPIRV_Integer>:$base,
+    SPIRV_Integer:$offset,
+    SPIRV_Integer:$count
   );
 
   let results = (outs
-    SPV_ScalarOrVectorOf<SPV_Integer>:$result
+    SPIRV_ScalarOrVectorOf<SPIRV_Integer>:$result
   );
 
   let hasVerifier = 0;
 
   let assemblyFormat = [{
     operands attr-dict `:` type($base) `,` type($offset) `,` type($count)
   }];
 }
 
-class SPV_BitUnaryOp<string mnemonic, list<Trait> traits = []> :
-      SPV_UnaryOp<mnemonic, SPV_Integer, SPV_Integer,
+class SPIRV_BitUnaryOp<string mnemonic, list<Trait> traits = []> :
+      SPIRV_UnaryOp<mnemonic, SPIRV_Integer, SPIRV_Integer,
                    !listconcat(traits,
                                [NoSideEffect, SameOperandsAndResultType])>;
 
-class SPV_ShiftOp<string mnemonic, list<Trait> traits = []> :
-      SPV_BinaryOp<mnemonic, SPV_Integer, SPV_Integer,
+class SPIRV_ShiftOp<string mnemonic, list<Trait> traits = []> :
+      SPIRV_BinaryOp<mnemonic, SPIRV_Integer, SPIRV_Integer,
                    !listconcat(traits,
                                [NoSideEffect, SameOperandsAndResultShape,
                                 AllTypesMatch<["operand1", "result"]>])> {
   let assemblyFormat = [{
     operands attr-dict `:` type($operand1) `,` type($operand2)
   }];
   let hasVerifier = 1;
 }
 
 // -----
 
-def SPV_BitCountOp : SPV_BitUnaryOp<"BitCount", []> {
+def SPIRV_BitCountOp : SPIRV_BitUnaryOp<"BitCount", []> {
   let summary = "Count the number of set bits in an object.";
 
   let description = [{
      Results are computed per component.
 
     Result Type must be a scalar or vector of integer type.  The components
     must be wide enough to hold the unsigned Width of Base as an unsigned
     value. That is, no sign bit is needed or counted when checking for a
let description = [{
     %2 = spirv.BitCount %0: i32
     %3 = spirv.BitCount %1: vector<4xi32>
     ```
   }];
 }
 
 // -----
 
-def SPV_BitFieldInsertOp : SPV_Op<"BitFieldInsert",
+def SPIRV_BitFieldInsertOp : SPIRV_Op<"BitFieldInsert",
     [NoSideEffect, AllTypesMatch<["base", "insert", "result"]>]> {
   let summary = [{
     Make a copy of an object, with a modified bit field that comes from
     another object.
   }];
 
   let description = [{
      Results are computed per component.
let description = [{
     #### Example:
 
     ```mlir
     %0 = spirv.BitFieldInsert %base, %insert, %offset, %count : vector<3xi32>, i8, i8
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_BitInstructions, SPV_C_Shader]>
+    Capability<[SPIRV_C_BitInstructions, SPIRV_C_Shader]>
   ];
 
   let arguments = (ins
-    SPV_ScalarOrVectorOf<SPV_Integer>:$base,
-    SPV_ScalarOrVectorOf<SPV_Integer>:$insert,
-    SPV_Integer:$offset,
-    SPV_Integer:$count
+    SPIRV_ScalarOrVectorOf<SPIRV_Integer>:$base,
+    SPIRV_ScalarOrVectorOf<SPIRV_Integer>:$insert,
+    SPIRV_Integer:$offset,
+    SPIRV_Integer:$count
   );
 
   let results = (outs
-    SPV_ScalarOrVectorOf<SPV_Integer>:$result
+    SPIRV_ScalarOrVectorOf<SPIRV_Integer>:$result
   );
 
   let hasVerifier = 0;
 
   let assemblyFormat = [{
     operands attr-dict `:` type($base) `,` type($offset) `,` type($count)
   }];
 }
 
 // -----
 
-def SPV_BitFieldSExtractOp : SPV_BitFieldExtractOp<"BitFieldSExtract",
+def SPIRV_BitFieldSExtractOp : SPIRV_BitFieldExtractOp<"BitFieldSExtract",
                                                    [SignedOp]> {
   let summary = "Extract a bit field from an object, with sign extension.";
 
   let description = [{
      Results are computed per component.
 
     Result Type must be a scalar or vector of integer type.
 
let description = [{
     #### Example:
 
     ```mlir
     %0 = spirv.BitFieldSExtract %base, %offset, %count : vector<3xi32>, i8, i8
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_BitInstructions, SPV_C_Shader]>
+    Capability<[SPIRV_C_BitInstructions, SPIRV_C_Shader]>
   ];
 }
 
 // -----
 
-def SPV_BitFieldUExtractOp : SPV_BitFieldExtractOp<"BitFieldUExtract",
+def SPIRV_BitFieldUExtractOp : SPIRV_BitFieldExtractOp<"BitFieldUExtract",
                                                    [UnsignedOp]> {
   let summary = "Extract a bit field from an object, without sign extension.";
 
   let description = [{
     The semantics are the same as with OpBitFieldSExtract with the exception
     that there is no sign extension. The remaining bits of the result will
     all be 0.
 
let description = [{
     #### Example:
 
     ```mlir
     %0 = spirv.BitFieldUExtract %base, %offset, %count : vector<3xi32>, i8, i8
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_BitInstructions, SPV_C_Shader]>
+    Capability<[SPIRV_C_BitInstructions, SPIRV_C_Shader]>
   ];
 }
 
 // -----
 
-def SPV_BitReverseOp : SPV_BitUnaryOp<"BitReverse", []> {
+def SPIRV_BitReverseOp : SPIRV_BitUnaryOp<"BitReverse", []> {
   let summary = "Reverse the bits in an object.";
 
   let description = [{
      Results are computed per component.
 
     Result Type must be a scalar or vector of integer type.
 
      The type of Base must be the same as Result Type.
let description = [{
 
     ```mlir
     %2 = spirv.BitReverse %0 : i32
     %3 = spirv.BitReverse %1 : vector<4xi32>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_BitInstructions, SPV_C_Shader]>
+    Capability<[SPIRV_C_BitInstructions, SPIRV_C_Shader]>
   ];
 }
 
 // -----
 
-def SPV_BitwiseAndOp : SPV_BitBinaryOp<"BitwiseAnd",
+def SPIRV_BitwiseAndOp : SPIRV_BitBinaryOp<"BitwiseAnd",
                                        [Commutative, UsableInSpecConstantOp]> {
   let summary = [{
     Result is 1 if both Operand 1 and Operand 2 are 1. Result is 0 if either
     Operand 1 or Operand 2 are 0.
   }];
 
   let description = [{
      Results are computed per component, and within each component, per bit.
let description = [{
     %2 = spirv.BitwiseAnd %0, %1 : i32
     %2 = spirv.BitwiseAnd %0, %1 : vector<4xi32>
     ```
   }];
 }
 
 // -----
 
-def SPV_BitwiseOrOp : SPV_BitBinaryOp<"BitwiseOr",
+def SPIRV_BitwiseOrOp : SPIRV_BitBinaryOp<"BitwiseOr",
                                       [Commutative, UsableInSpecConstantOp]> {
   let summary = [{
     Result is 1 if either Operand 1 or Operand 2 is 1. Result is 0 if both
     Operand 1 and Operand 2 are 0.
   }];
 
   let description = [{
      Results are computed per component, and within each component, per bit.
let description = [{
     %2 = spirv.BitwiseOr %0, %1 : i32
     %2 = spirv.BitwiseOr %0, %1 : vector<4xi32>
     ```
   }];
 }
 
 // -----
 
-def SPV_BitwiseXorOp : SPV_BitBinaryOp<"BitwiseXor",
+def SPIRV_BitwiseXorOp : SPIRV_BitBinaryOp<"BitwiseXor",
                                        [Commutative, UsableInSpecConstantOp]> {
   let summary = [{
     Result is 1 if exactly one of Operand 1 or Operand 2 is 1. Result is 0
     if Operand 1 and Operand 2 have the same value.
   }];
 
   let description = [{
      Results are computed per component, and within each component, per bit.
let description = [{
     %2 = spirv.BitwiseXor %0, %1 : i32
     %2 = spirv.BitwiseXor %0, %1 : vector<4xi32>
     ```
   }];
 }
 
 // -----
 
-def SPV_ShiftLeftLogicalOp : SPV_ShiftOp<"ShiftLeftLogical",
+def SPIRV_ShiftLeftLogicalOp : SPIRV_ShiftOp<"ShiftLeftLogical",
                                          [UsableInSpecConstantOp]> {
   let summary = [{
     Shift the bits in Base left by the number of bits specified in Shift.
     The least-significant bits are zero filled.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of integer type.
let description = [{
     %2 = spirv.ShiftLeftLogical %0, %1 : i32, i16
     %5 = spirv.ShiftLeftLogical %3, %4 : vector<3xi32>, vector<3xi16>
     ```
   }];
 }
 
 // -----
 
-def SPV_ShiftRightArithmeticOp : SPV_ShiftOp<"ShiftRightArithmetic",
+def SPIRV_ShiftRightArithmeticOp : SPIRV_ShiftOp<"ShiftRightArithmetic",
                                              [UsableInSpecConstantOp]> {
   let summary = [{
     Shift the bits in Base right by the number of bits specified in Shift.
     The most-significant bits are filled with the sign bit from Base.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of integer type.
let description = [{
     %2 = spirv.ShiftRightArithmetic %0, %1 : i32, i16
     %5 = spirv.ShiftRightArithmetic %3, %4 : vector<3xi32>, vector<3xi16>
     ```
   }];
 }
 
 // -----
 
-def SPV_ShiftRightLogicalOp : SPV_ShiftOp<"ShiftRightLogical",
+def SPIRV_ShiftRightLogicalOp : SPIRV_ShiftOp<"ShiftRightLogical",
                                           [UsableInSpecConstantOp]> {
   let summary = [{
     Shift the bits in Base right by the number of bits specified in Shift.
     The most-significant bits are zero filled.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of integer type.
let description = [{
     %2 = spirv.ShiftRightLogical %0, %1 : i32, i16
     %5 = spirv.ShiftRightLogical %3, %4 : vector<3xi32>, vector<3xi16>
     ```
   }];
 }
 
 // -----
 
-def SPV_NotOp : SPV_BitUnaryOp<"Not", [UsableInSpecConstantOp]> {
+def SPIRV_NotOp : SPIRV_BitUnaryOp<"Not", [UsableInSpecConstantOp]> {
   let summary = "Complement the bits of Operand.";
 
   let description = [{
      Results are computed per component, and within each component, per bit.
 
     Result Type must be a scalar or vector of integer type.
 
     Operand's type  must be a scalar or vector of integer type.  It must

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCLOps.td

 
 include "mlir/Dialect/SPIRV/IR/SPIRVBase.td"
 
 //===----------------------------------------------------------------------===//
 // SPIR-V OpenCL opcode specification.
 //===----------------------------------------------------------------------===//
 
 // Base class for all OpenCL ops.
-class SPV_CLOp<string mnemonic, int opcode, list<Trait> traits = []> :
-  SPV_ExtInstOp<mnemonic, "CL", "OpenCL.std", opcode, traits> {
+class SPIRV_CLOp<string mnemonic, int opcode, list<Trait> traits = []> :
+  SPIRV_ExtInstOp<mnemonic, "CL", "OpenCL.std", opcode, traits> {
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
 
 // Base class for OpenCL unary ops.
-class SPV_CLUnaryOp<string mnemonic, int opcode, Type resultType,
+class SPIRV_CLUnaryOp<string mnemonic, int opcode, Type resultType,
                       Type operandType, list<Trait> traits = []> :
-  SPV_CLOp<mnemonic, opcode, !listconcat([NoSideEffect], traits)> {
+  SPIRV_CLOp<mnemonic, opcode, !listconcat([NoSideEffect], traits)> {
 
   let arguments = (ins
-    SPV_ScalarOrVectorOf<operandType>:$operand
+    SPIRV_ScalarOrVectorOf<operandType>:$operand
   );
 
   let results = (outs
-    SPV_ScalarOrVectorOf<resultType>:$result
+    SPIRV_ScalarOrVectorOf<resultType>:$result
   );
 
   let assemblyFormat = "$operand `:` type($operand) attr-dict";
 
   let hasVerifier = 0;
 }
 
 // Base class for OpenCL Unary arithmetic ops where return type matches
 // the operand type.
-class SPV_CLUnaryArithmeticOp<string mnemonic, int opcode, Type type,
+class SPIRV_CLUnaryArithmeticOp<string mnemonic, int opcode, Type type,
                                 list<Trait> traits = []> :
-  SPV_CLUnaryOp<mnemonic, opcode, type, type,
+  SPIRV_CLUnaryOp<mnemonic, opcode, type, type,
                  traits # [SameOperandsAndResultType]>;
 
 // Base class for OpenCL binary ops.
-class SPV_CLBinaryOp<string mnemonic, int opcode, Type resultType,
+class SPIRV_CLBinaryOp<string mnemonic, int opcode, Type resultType,
                        Type operandType, list<Trait> traits = []> :
-  SPV_CLOp<mnemonic, opcode, !listconcat([NoSideEffect], traits)> {
+  SPIRV_CLOp<mnemonic, opcode, !listconcat([NoSideEffect], traits)> {
 
   let arguments = (ins
-    SPV_ScalarOrVectorOf<operandType>:$lhs,
-    SPV_ScalarOrVectorOf<operandType>:$rhs
+    SPIRV_ScalarOrVectorOf<operandType>:$lhs,
+    SPIRV_ScalarOrVectorOf<operandType>:$rhs
   );
 
   let results = (outs
-    SPV_ScalarOrVectorOf<resultType>:$result
+    SPIRV_ScalarOrVectorOf<resultType>:$result
   );
 
   let hasVerifier = 0;
 }
 
 // Base class for OpenCL Binary arithmetic ops where operand types and
 // return type matches.
-class SPV_CLBinaryArithmeticOp<string mnemonic, int opcode, Type type,
+class SPIRV_CLBinaryArithmeticOp<string mnemonic, int opcode, Type type,
                                  list<Trait> traits = []> :
-  SPV_CLBinaryOp<mnemonic, opcode, type, type,
+  SPIRV_CLBinaryOp<mnemonic, opcode, type, type,
                   traits # [SameOperandsAndResultType]> {
   let assemblyFormat = "operands attr-dict `:` type($result)";
 }
 
 // Base class for OpenCL binary ops.
-class SPV_CLTernaryOp<string mnemonic, int opcode, Type resultType,
+class SPIRV_CLTernaryOp<string mnemonic, int opcode, Type resultType,
                       Type operandType, list<Trait> traits = []> :
-  SPV_CLOp<mnemonic, opcode, !listconcat([NoSideEffect], traits)> {
+  SPIRV_CLOp<mnemonic, opcode, !listconcat([NoSideEffect], traits)> {
 
   let arguments = (ins
-    SPV_ScalarOrVectorOf<operandType>:$x,
-    SPV_ScalarOrVectorOf<operandType>:$y,
-    SPV_ScalarOrVectorOf<operandType>:$z
+    SPIRV_ScalarOrVectorOf<operandType>:$x,
+    SPIRV_ScalarOrVectorOf<operandType>:$y,
+    SPIRV_ScalarOrVectorOf<operandType>:$z
   );
 
   let results = (outs
-    SPV_ScalarOrVectorOf<resultType>:$result
+    SPIRV_ScalarOrVectorOf<resultType>:$result
   );
 
   let hasVerifier = 0;
 }
 
 // Base class for OpenCL Ternary arithmetic ops where operand types and
 // return type matches.
-class SPV_CLTernaryArithmeticOp<string mnemonic, int opcode, Type type,
+class SPIRV_CLTernaryArithmeticOp<string mnemonic, int opcode, Type type,
                                   list<Trait> traits = []> :
-  SPV_CLTernaryOp<mnemonic, opcode, type, type,
+  SPIRV_CLTernaryOp<mnemonic, opcode, type, type,
                   traits # [SameOperandsAndResultType]> {
   let assemblyFormat = "operands attr-dict `:` type($result)";
 }
 
 
 
 // -----
 
-def SPV_CLCeilOp : SPV_CLUnaryArithmeticOp<"ceil", 12, SPV_Float> {
+def SPIRV_CLCeilOp : SPIRV_CLUnaryArithmeticOp<"ceil", 12, SPIRV_Float> {
   let summary = [{
     Round x to integral value using the round to positive infinity rounding
     mode.
   }];
 
   let description = [{
     Result Type and x must be floating-point or vector(2,3,4,8,16) of
     floating-point values.
let description = [{
     %2 = spirv.CL.ceil %0 : f32
     %3 = spirv.CL.ceil %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_CLCosOp : SPV_CLUnaryArithmeticOp<"cos", 14, SPV_Float> {
+def SPIRV_CLCosOp : SPIRV_CLUnaryArithmeticOp<"cos", 14, SPIRV_Float> {
   let summary = "Compute the cosine of x radians.";
 
   let description = [{
     Result Type and x must be floating-point or vector(2,3,4,8,16) of
     floating-point values.
 
     All of the operands, including the Result Type operand, must be of the
     same type.
let description = [{
     %2 = spirv.CL.cos %0 : f32
     %3 = spirv.CL.cos %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_CLErfOp : SPV_CLUnaryArithmeticOp<"erf", 18, SPV_Float> {
+def SPIRV_CLErfOp : SPIRV_CLUnaryArithmeticOp<"erf", 18, SPIRV_Float> {
   let summary = [{
     Error function of x encountered in integrating the normal distribution.
   }];
 
   let description = [{
     Result Type and x must be floating-point or vector(2,3,4,8,16) of
     floating-point values.
 
let description = [{
     %2 = spirv.CL.erf %0 : f32
     %3 = spirv.CL.erf %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_CLExpOp : SPV_CLUnaryArithmeticOp<"exp", 19, SPV_Float> {
+def SPIRV_CLExpOp : SPIRV_CLUnaryArithmeticOp<"exp", 19, SPIRV_Float> {
   let summary = "Exponentiation of Operand 1";
 
   let description = [{
     Compute the base-e exponential of x. (i.e. ex)
 
     Result Type and x must be floating-point or vector(2,3,4,8,16) of
     floating-point values.
 
let description = [{
     %2 = spirv.CL.exp %0 : f32
     %3 = spirv.CL.exp %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_CLFAbsOp : SPV_CLUnaryArithmeticOp<"fabs", 23, SPV_Float> {
+def SPIRV_CLFAbsOp : SPIRV_CLUnaryArithmeticOp<"fabs", 23, SPIRV_Float> {
   let summary = "Absolute value of operand";
 
   let description = [{
     Compute the absolute value of x.
 
     Result Type and x must be floating-point or vector(2,3,4,8,16) of
     floating-point values.
 
let description = [{
     %2 = spirv.CL.fabs %0 : f32
     %3 = spirv.CL.fabs %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_CLFloorOp : SPV_CLUnaryArithmeticOp<"floor", 25, SPV_Float> {
+def SPIRV_CLFloorOp : SPIRV_CLUnaryArithmeticOp<"floor", 25, SPIRV_Float> {
   let summary = [{
     Round x to the integral value using the round to negative infinity
     rounding mode.
   }];
 
   let description = [{
     Result Type and x must be floating-point or vector(2,3,4,8,16) of
     floating-point values.
let description = [{
     %2 = spirv.CL.floor %0 : f32
     %3 = spirv.CL.ceifloorl %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_CLFmaOp : SPV_CLTernaryArithmeticOp<"fma", 26, SPV_Float> {
+def SPIRV_CLFmaOp : SPIRV_CLTernaryArithmeticOp<"fma", 26, SPIRV_Float> {
   let summary = [{
     Compute the correctly rounded floating-point representation of the sum
     of c with the infinitely precise product of a and b. Rounding of
     intermediate products shall not occur. Edge case results are per the
     IEEE 754-2008 standard.
   }];
 
   let description = [{
let description = [{
     %0 = spirv.CL.fma %a, %b, %c : f32
     %1 = spirv.CL.fma %a, %b, %c : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_CLFMaxOp : SPV_CLBinaryArithmeticOp<"fmax", 27, SPV_Float> {
+def SPIRV_CLFMaxOp : SPIRV_CLBinaryArithmeticOp<"fmax", 27, SPIRV_Float> {
   let summary = "Return maximum of two floating-point operands";
 
   let description = [{
     Returns y if x < y, otherwise it returns x. If one argument is a NaN,
     Fmax returns the other argument. If both arguments are NaNs, Fmax returns a NaN.
 
-    Result Type, x and y must be floating-point or vector(2,3,4,8,16) 
+    Result Type, x and y must be floating-point or vector(2,3,4,8,16)
     of floating-point values.
 
-    All of the operands, including the Result Type operand, 
+    All of the operands, including the Result Type operand,
     must be of the same type.
 
     <!-- End of AutoGen section -->
     ```
     float-scalar-vector-type ::= float-type |
                                  `vector<` integer-literal `x` float-type `>`
     fmax-op ::= ssa-id `=` `spirv.CL.fmax` ssa-use `:`
                 float-scalar-vector-type
     ```
     #### Example:
 
     ```mlir
     %2 = spirv.CL.fmax %0, %1 : f32
     %3 = spirv.CL.fmax %0, %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_CLFMinOp : SPV_CLBinaryArithmeticOp<"fmin", 28, SPV_Float> {
+def SPIRV_CLFMinOp : SPIRV_CLBinaryArithmeticOp<"fmin", 28, SPIRV_Float> {
   let summary = "Return minimum of two floating-point operands";
 
   let description = [{
-    Returns y if y < x, otherwise it returns x. If one argument is a NaN, Fmin returns the other argument. 
+    Returns y if y < x, otherwise it returns x. If one argument is a NaN, Fmin returns the other argument.
     If both arguments are NaNs, Fmin returns a NaN.
 
     Result Type,x and y must be floating-point or vector(2,3,4,8,16) of floating-point values.
 
     All of the operands, including the Result Type operand, must be of the same type.
 
 
     <!-- End of AutoGen section -->
let description = [{
     %2 = spirv.CL.fmin %0, %1 : f32
     %3 = spirv.CL.fmin %0, %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_CLLogOp : SPV_CLUnaryArithmeticOp<"log", 37, SPV_Float> {
+def SPIRV_CLLogOp : SPIRV_CLUnaryArithmeticOp<"log", 37, SPIRV_Float> {
   let summary = "Compute the natural logarithm of x.";
 
   let description = [{
     Result Type and x must be floating-point or vector(2,3,4,8,16) of
     floating-point values.
 
     All of the operands, including the Result Type operand, must be of the
     same type.
let description = [{
     %2 = spirv.CL.log %0 : f32
     %3 = spirv.CL.log %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_CLPowOp : SPV_CLBinaryArithmeticOp<"pow", 48, SPV_Float> {
+def SPIRV_CLPowOp : SPIRV_CLBinaryArithmeticOp<"pow", 48, SPIRV_Float> {
   let summary = "Compute x to the power y.";
 
   let description = [{
     Result Type, x and y must be floating-point or vector(2,3,4,8,16) of
     floating-point values.
 
     All of the operands, including the Result Type operand, must be of the
     same type.
let description = [{
     %2 = spirv.CL.pow %0, %1 : f32
     %3 = spirv.CL.pow %0, %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_CLRoundOp : SPV_CLUnaryArithmeticOp<"round", 55, SPV_Float> {
+def SPIRV_CLRoundOp : SPIRV_CLUnaryArithmeticOp<"round", 55, SPIRV_Float> {
   let summary = [{
     Return the integral value nearest to x rounding halfway cases away from
     zero, regardless of the current rounding direction.
   }];
 
   let description = [{
     Result Type and x must be floating-point or vector(2,3,4,8,16) of
     floating-point values.
let description = [{
     %2 = spirv.CL.round %0 : f32
     %3 = spirv.CL.round %0 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_CLRsqrtOp : SPV_CLUnaryArithmeticOp<"rsqrt", 56, SPV_Float> {
+def SPIRV_CLRsqrtOp : SPIRV_CLUnaryArithmeticOp<"rsqrt", 56, SPIRV_Float> {
   let summary = "Compute inverse square root of x.";
 
   let description = [{
     Result Type and x must be floating-point or vector(2,3,4,8,16) of
     floating-point values.
 
     All of the operands, including the Result Type operand, must be of the
     same type.
let description = [{
     %2 = spirv.CL.rsqrt %0 : f32
     %3 = spirv.CL.rsqrt %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_CLSinOp : SPV_CLUnaryArithmeticOp<"sin", 57, SPV_Float> {
+def SPIRV_CLSinOp : SPIRV_CLUnaryArithmeticOp<"sin", 57, SPIRV_Float> {
   let summary = "Compute sine of x radians.";
 
   let description = [{
     Result Type and x must be floating-point or vector(2,3,4,8,16) of
     floating-point values.
 
     All of the operands, including the Result Type operand, must be of the
     same type.
let description = [{
     %2 = spirv.CL.sin %0 : f32
     %3 = spirv.CL.sin %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_CLSqrtOp : SPV_CLUnaryArithmeticOp<"sqrt", 61, SPV_Float> {
+def SPIRV_CLSqrtOp : SPIRV_CLUnaryArithmeticOp<"sqrt", 61, SPIRV_Float> {
   let summary = "Compute square root of x.";
 
   let description = [{
     Result Type and x must be floating-point or vector(2,3,4,8,16) of
     floating-point values.
 
     All of the operands, including the Result Type operand, must be of the
     same type.
let description = [{
     %2 = spirv.CL.sqrt %0 : f32
     %3 = spirv.CL.sqrt %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_CLTanhOp : SPV_CLUnaryArithmeticOp<"tanh", 63, SPV_Float> {
+def SPIRV_CLTanhOp : SPIRV_CLUnaryArithmeticOp<"tanh", 63, SPIRV_Float> {
   let summary = "Compute hyperbolic tangent of x radians.";
 
   let description = [{
     Result Type and x must be floating-point or vector(2,3,4,8,16) of
     floating-point values.
 
     All of the operands, including the Result Type operand, must be of the
     same type.
let description = [{
     %2 = spirv.CL.tanh %0 : f32
     %3 = spirv.CL.tanh %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_CLSAbsOp : SPV_CLUnaryArithmeticOp<"s_abs", 141, SPV_Integer> {
+def SPIRV_CLSAbsOp : SPIRV_CLUnaryArithmeticOp<"s_abs", 141, SPIRV_Integer> {
   let summary = "Absolute value of operand";
 
   let description = [{
     Returns |x|, where x is treated as signed integer.
 
     Result Type and x must be integer or vector(2,3,4,8,16) of
     integer values.
 
let description = [{
     %2 = spirv.CL.s_abs %0 : i32
     %3 = spirv.CL.s_abs %1 : vector<3xi16>
     ```
   }];
 }
 
 // -----
 
-def SPV_CLSMaxOp : SPV_CLBinaryArithmeticOp<"s_max", 156, SPV_Integer> {
+def SPIRV_CLSMaxOp : SPIRV_CLBinaryArithmeticOp<"s_max", 156, SPIRV_Integer> {
   let summary = "Return maximum of two signed integer operands";
 
   let description = [{
     Returns y if x < y, otherwise it returns x, where x and y are treated as signed integers.
 
     Result Type,x and y must be integer or vector(2,3,4,8,16) of integer values.
 
     All of the operands, including the Result Type operand, must be of the same type.
let description = [{
     %2 = spirv.CL.s_max %0, %1 : i32
     %3 = spirv.CL.s_max %0, %1 : vector<3xi16>
     ```
   }];
 }
 
 // -----
 
-def SPV_CLUMaxOp : SPV_CLBinaryArithmeticOp<"u_max", 157, SPV_Integer> {
+def SPIRV_CLUMaxOp : SPIRV_CLBinaryArithmeticOp<"u_max", 157, SPIRV_Integer> {
   let summary = "Return maximum of two unsigned integer operands";
 
   let description = [{
     Returns y if x < y, otherwise it returns x, where x and y are treated as unsigned integers.
 
     Result Type,x and y must be integer or vector(2,3,4,8,16) of integer values.
 
     All of the operands, including the Result Type operand, must be of the same type.
 
     <!-- End of AutoGen section -->
     ```
     integer-scalar-vector-type ::= integer-type |
                                    `vector<` integer-literal `x` integer-type `>`
     umax-op ::= ssa-id `=` `spirv.CL.u_max` ssa-use `:`
                 integer-scalar-vector-type
     ```
     #### Example:
     ```mlir
     %2 = spirv.CL.u_max %0, %1 : i32
     %3 = spirv.CL.u_max %0, %1 : vector<3xi16>
     ```
   }];
 }
 
-def SPV_CLSMinOp : SPV_CLBinaryArithmeticOp<"s_min", 158, SPV_Integer> {
+def SPIRV_CLSMinOp : SPIRV_CLBinaryArithmeticOp<"s_min", 158, SPIRV_Integer> {
   let summary = "Return minimum of two signed integer operands";
 
   let description = [{
     Returns y if x < y, otherwise it returns x, where x and y are treated as signed integers.
 
     Result Type,x and y must be integer or vector(2,3,4,8,16) of integer values.
 
     All of the operands, including the Result Type operand, must be of the same type.
let description = [{
     %2 = spirv.CL.s_min %0, %1 : i32
     %3 = spirv.CL.s_min %0, %1 : vector<3xi16>
     ```
   }];
 }
 
 // -----
 
-def SPV_CLUMinOp : SPV_CLBinaryArithmeticOp<"u_min", 159, SPV_Integer> {
+def SPIRV_CLUMinOp : SPIRV_CLBinaryArithmeticOp<"u_min", 159, SPIRV_Integer> {
   let summary = "Return minimum of two unsigned integer operands";
 
   let description = [{
     Returns y if x < y, otherwise it returns x, where x and y are treated as unsigned integers.
 
     Result Type,x and y must be integer or vector(2,3,4,8,16) of integer values.
 
     All of the operands, including the Result Type operand, must be of the same type.

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCastOps.td

 //===----------------------------------------------------------------------===//
 
 #ifndef MLIR_DIALECT_SPIRV_IR_CAST_OPS
 #define MLIR_DIALECT_SPIRV_IR_CAST_OPS
 
 include "mlir/Dialect/SPIRV/IR/SPIRVBase.td"
 include "mlir/Interfaces/SideEffectInterfaces.td"
 
-class SPV_CastOp<string mnemonic, Type resultType, Type operandType,
+class SPIRV_CastOp<string mnemonic, Type resultType, Type operandType,
                    list<Trait> traits = []> :
-      SPV_Op<mnemonic,
+      SPIRV_Op<mnemonic,
              !listconcat(traits,
                          [NoSideEffect, SameOperandsAndResultShape])> {
   let arguments = (ins
-    SPV_ScalarOrVectorOrCoopMatrixOf<operandType>:$operand
+    SPIRV_ScalarOrVectorOrCoopMatrixOf<operandType>:$operand
   );
 
   let results = (outs
-    SPV_ScalarOrVectorOrCoopMatrixOf<resultType>:$result
+    SPIRV_ScalarOrVectorOrCoopMatrixOf<resultType>:$result
   );
   let assemblyFormat = [{
     $operand attr-dict `:` type($operand) `to` type($result)
   }];
 }
 
 // -----
 
-def SPV_BitcastOp : SPV_Op<"Bitcast", [NoSideEffect]> {
+def SPIRV_BitcastOp : SPIRV_Op<"Bitcast", [NoSideEffect]> {
   let summary = "Bit pattern-preserving type conversion.";
 
   let description = [{
     Result Type must be an OpTypePointer, or a scalar or vector of
     numerical-type.
 
     Operand must have a type of OpTypePointer, or a scalar or vector of
     numerical-type. It must be a different type than Result Type.
let description = [{
     ```mlir
     %1 = spirv.Bitcast %0 : f32 to i32
     %1 = spirv.Bitcast %0 : vector<2xf32> to i64
     %1 = spirv.Bitcast %0 : !spirv.ptr<f32, Function> to !spirv.ptr<i32, Function>
     ```
   }];
 
   let arguments = (ins
-    SPV_ScalarOrVectorOrPtr:$operand
+    SPIRV_ScalarOrVectorOrPtr:$operand
   );
 
   let results = (outs
-    SPV_ScalarOrVectorOrPtr:$result
+    SPIRV_ScalarOrVectorOrPtr:$result
   );
 
   let assemblyFormat = [{
     $operand attr-dict `:` type($operand) `to` type($result)
   }];
   let hasCanonicalizer = 1;
 }
 
 // -----
 
-def SPV_ConvertFToSOp : SPV_CastOp<"ConvertFToS", SPV_Integer, SPV_Float, []> {
+def SPIRV_ConvertFToSOp : SPIRV_CastOp<"ConvertFToS", SPIRV_Integer, SPIRV_Float, []> {
   let summary = [{
     Convert value numerically from floating point to signed integer, with
     round toward 0.0.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of integer type.
 
let description = [{
     %1 = spirv.ConvertFToS %0 : f32 to i32
     %3 = spirv.ConvertFToS %2 : vector<3xf32> to vector<3xi32>
     ```
   }];
 }
 
 // -----
 
-def SPV_ConvertFToUOp : SPV_CastOp<"ConvertFToU", SPV_Integer, SPV_Float, []> {
+def SPIRV_ConvertFToUOp : SPIRV_CastOp<"ConvertFToU", SPIRV_Integer, SPIRV_Float, []> {
   let summary = [{
     Convert value numerically from floating point to unsigned integer, with
     round toward 0.0.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of integer type, whose Signedness
     operand is 0.
let description = [{
     %1 = spirv.ConvertFToU %0 : f32 to i32
     %3 = spirv.ConvertFToU %2 : vector<3xf32> to vector<3xi32>
     ```
   }];
 }
 
 // -----
 
-def SPV_ConvertSToFOp : SPV_CastOp<"ConvertSToF",
-                                   SPV_Float,
-                                   SPV_Integer,
+def SPIRV_ConvertSToFOp : SPIRV_CastOp<"ConvertSToF",
+                                   SPIRV_Float,
+                                   SPIRV_Integer,
                                    [SignedOp]> {
   let summary = [{
     Convert value numerically from signed integer to floating point.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of floating-point type.
 
let description = [{
     %1 = spirv.ConvertSToF %0 : i32 to f32
     %3 = spirv.ConvertSToF %2 : vector<3xi32> to vector<3xf32>
     ```
   }];
 }
 
 // -----
 
-def SPV_ConvertUToFOp : SPV_CastOp<"ConvertUToF",
-                                   SPV_Float,
-                                   SPV_Integer,
+def SPIRV_ConvertUToFOp : SPIRV_CastOp<"ConvertUToF",
+                                   SPIRV_Float,
+                                   SPIRV_Integer,
                                    [UnsignedOp]> {
   let summary = [{
     Convert value numerically from unsigned integer to floating point.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of floating-point type.
 
let description = [{
     %1 = spirv.ConvertUToF %0 : i32 to f32
     %3 = spirv.ConvertUToF %2 : vector<3xi32> to vector<3xf32>
     ```
   }];
 }
 
 // -----
 
-def SPV_FConvertOp : SPV_CastOp<"FConvert",
-                                SPV_Float,
-                                SPV_Float,
+def SPIRV_FConvertOp : SPIRV_CastOp<"FConvert",
+                                SPIRV_Float,
+                                SPIRV_Float,
                                 [UsableInSpecConstantOp]> {
   let summary = [{
     Convert value numerically from one floating-point width to another
     width.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of floating-point type.
let description = [{
     %1 = spirv.FConvertOp %0 : f32 to f64
     %3 = spirv.FConvertOp %2 : vector<3xf32> to vector<3xf64>
     ```
   }];
 }
 
 // -----
 
-def SPV_SConvertOp : SPV_CastOp<"SConvert",
-                                SPV_Integer,
-                                SPV_Integer,
+def SPIRV_SConvertOp : SPIRV_CastOp<"SConvert",
+                                SPIRV_Integer,
+                                SPIRV_Integer,
                                 [UsableInSpecConstantOp, SignedOp]> {
   let summary = [{
     Convert signed width.  This is either a truncate or a sign extend.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of integer type.
 
let description = [{
     %1 = spirv.SConvertOp %0 : i32 to i64
     %3 = spirv.SConvertOp %2 : vector<3xi32> to vector<3xi64>
     ```
   }];
 }
 
 // -----
 
-def SPV_UConvertOp : SPV_CastOp<"UConvert",
-                                SPV_Integer,
-                                SPV_Integer,
+def SPIRV_UConvertOp : SPIRV_CastOp<"UConvert",
+                                SPIRV_Integer,
+                                SPIRV_Integer,
                                 [UnsignedOp, UsableInSpecConstantOp]> {
   let summary = [{
     Convert unsigned width. This is either a truncate or a zero extend.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of integer type, whose Signedness
     operand is 0.
let description = [{
     ```mlir
     %1 = spirv.UConvertOp %0 : i32 to i64
     %3 = spirv.UConvertOp %2 : vector<3xi32> to vector<3xi64>
     ```
   }];
 }
 
 // -----
-def SPV_PtrCastToGenericOp : SPV_Op<"PtrCastToGeneric", [NoSideEffect]> {
+def SPIRV_PtrCastToGenericOp : SPIRV_Op<"PtrCastToGeneric", [NoSideEffect]> {
   let summary = "Convert a pointer’s Storage Class to Generic.";
 
   let description = [{
     Result Type must be an OpTypePointer. Its Storage Class must be Generic.
 
     Pointer must point to the Workgroup, CrossWorkgroup, or Function Storage
     Class.
 
     Result Type and Pointer must point to the same type.
 
     <!-- End of AutoGen section -->
 
     #### Example:
 
     ```mlir
-    %1 = spirv.PtrCastToGenericOp %0 : !spirv.ptr<f32, CrossWorkGroup> to 
+    %1 = spirv.PtrCastToGenericOp %0 : !spirv.ptr<f32, CrossWorkGroup> to
          !spirv.ptr<f32, Generic>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 
   let arguments = (ins
-    SPV_AnyPtr:$pointer
+    SPIRV_AnyPtr:$pointer
   );
 
   let results = (outs
-    SPV_AnyPtr:$result
+    SPIRV_AnyPtr:$result
   );
 
   let assemblyFormat = [{
     $pointer attr-dict `:` type($pointer) `to` type($result)
   }];
 }
 
 // -----
 
-def SPV_GenericCastToPtrOp : SPV_Op<"GenericCastToPtr", [NoSideEffect]> {
+def SPIRV_GenericCastToPtrOp : SPIRV_Op<"GenericCastToPtr", [NoSideEffect]> {
   let summary = "Convert a pointer’s Storage Class to a non-Generic class.";
 
   let description = [{
     Result Type must be an OpTypePointer. Its Storage Class must be
     Workgroup, CrossWorkgroup, or Function.
 
     Pointer must point to the Generic Storage Class.
 
     Result Type and Pointer must point to the same type.
 
     <!-- End of AutoGen section -->
 
     #### Example:
 
     ```mlir
        %1 = spirv.GenericCastToPtrOp %0 : !spirv.ptr<f32, Generic> to
        !spirv.ptr<f32, CrossWorkGroup>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 
   let arguments = (ins
-    SPV_AnyPtr:$pointer
+    SPIRV_AnyPtr:$pointer
   );
 
   let results = (outs
-    SPV_AnyPtr:$result
+    SPIRV_AnyPtr:$result
   );
 
   let assemblyFormat = [{
     $pointer attr-dict `:` type($pointer) `to` type($result)
   }];
 }
 
 // -----
 
-def SPV_GenericCastToPtrExplicitOp : SPV_Op<"GenericCastToPtrExplicit", [NoSideEffect]> {
+def SPIRV_GenericCastToPtrExplicitOp : SPIRV_Op<"GenericCastToPtrExplicit", [NoSideEffect]> {
   let summary = [{
     Attempts to explicitly convert Pointer to Storage storage-class pointer
     value.
   }];
 
   let description = [{
     Result Type must be an OpTypePointer. Its Storage Class must be Storage.
 
let description = [{
 
     ```mlir
        %1 = spirv.GenericCastToPtrExplicitOp %0 : !spirv.ptr<f32, Generic> to
        !spirv.ptr<f32, CrossWorkGroup>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 
   let arguments = (ins
-    SPV_AnyPtr:$pointer
+    SPIRV_AnyPtr:$pointer
   );
 
   let results = (outs
-    SPV_AnyPtr:$result
+    SPIRV_AnyPtr:$result
   );
 
   let assemblyFormat = [{
     $pointer attr-dict `:` type($pointer) `to` type($result)
   }];
 
   let autogenSerialization = 0;
 }
 
 #endif // MLIR_DIALECT_SPIRV_IR_CAST_OPS

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCompositeOps.td

 #ifndef MLIR_DIALECT_SPIRV_IR_COMPOSITE_OPS
 #define MLIR_DIALECT_SPIRV_IR_COMPOSITE_OPS
 
 include "mlir/Dialect/SPIRV/IR/SPIRVBase.td"
 include "mlir/Interfaces/SideEffectInterfaces.td"
 
 // -----
 
-def SPV_CompositeConstructOp : SPV_Op<"CompositeConstruct", [NoSideEffect]> {
+def SPIRV_CompositeConstructOp : SPIRV_Op<"CompositeConstruct", [NoSideEffect]> {
   let summary = [{
     Construct a new composite object from a set of constituent objects.
   }];
 
   let description = [{
     Result Type must be a composite type, whose top-level
     members/elements/components/columns have the same type as the types of
     the operands, with one exception. The exception is that for constructing
let description = [{
     #### Example:
 
     ```mlir
     %0 = spirv.CompositeConstruct %1, %2, %3 : vector<3xf32>
     ```
   }];
 
   let arguments = (ins
-    Variadic<SPV_Type>:$constituents
+    Variadic<SPIRV_Type>:$constituents
   );
 
   let results = (outs
-    SPV_Composite:$result
+    SPIRV_Composite:$result
   );
 
   let assemblyFormat = [{
     $constituents attr-dict `:` `(` type(operands) `)` `->` type($result)
   }];
 }
 
 // -----
 
-def SPV_CompositeExtractOp : SPV_Op<"CompositeExtract",
+def SPIRV_CompositeExtractOp : SPIRV_Op<"CompositeExtract",
                                         [NoSideEffect, UsableInSpecConstantOp]> {
   let summary = "Extract a part of a composite object.";
 
   let description = [{
     Result Type must be the type of object selected by the last provided
     index.  The instruction result is the extracted object.
 
     Composite is the composite to extract from.
 
let description = [{
     %0 = spirv.Variable : !spirv.ptr<!spirv.array<4x!spirv.array<4xf32>>, Function>
     %1 = spirv.Load "Function" %0 ["Volatile"] : !spirv.array<4x!spirv.array<4xf32>>
     %2 = spirv.CompositeExtract %1[1 : i32] : !spirv.array<4x!spirv.array<4xf32>>
     ```
 
   }];
 
   let arguments = (ins
-    SPV_Composite:$composite,
+    SPIRV_Composite:$composite,
     I32ArrayAttr:$indices
   );
 
   let results = (outs
-    SPV_Type:$component
+    SPIRV_Type:$component
   );
 
   let builders = [
     OpBuilder<(ins "Value":$composite, "ArrayRef<int32_t>":$indices)>
   ];
 
   let hasFolder = 1;
 }
 
 // -----
 
-def SPV_CompositeInsertOp : SPV_Op<"CompositeInsert",
+def SPIRV_CompositeInsertOp : SPIRV_Op<"CompositeInsert",
                                        [NoSideEffect, UsableInSpecConstantOp]> {
   let summary = [{
     Make a copy of a composite object, while modifying one part of it.
   }];
 
   let description = [{
     Result Type must be the same type as Composite.
 
     Object is the object to use as the modified part.
let description = [{
     #### Example:
 
     ```mlir
     %0 = spirv.CompositeInsert %object, %composite[1 : i32] : f32 into !spirv.array<4xf32>
     ```
   }];
 
   let arguments = (ins
-    SPV_Type:$object,
-    SPV_Composite:$composite,
+    SPIRV_Type:$object,
+    SPIRV_Composite:$composite,
     I32ArrayAttr:$indices
   );
 
   let results = (outs
-    SPV_Composite:$result
+    SPIRV_Composite:$result
   );
 
   let builders = [
     OpBuilder<(ins "Value":$object, "Value":$composite,
                       "ArrayRef<int32_t>":$indices)>
   ];
 }
 
 // -----
 
-def SPV_VectorExtractDynamicOp : SPV_Op<"VectorExtractDynamic", [
+def SPIRV_VectorExtractDynamicOp : SPIRV_Op<"VectorExtractDynamic", [
     NoSideEffect,
     TypesMatchWith<"type of 'result' matches element type of 'vector'",
                    "vector", "result",
                    "$_self.cast<mlir::VectorType>().getElementType()">]> {
   let summary = [{
     Extract a single, dynamically selected, component of a vector.
   }];
 
let description = [{
     #### Example:
 
     ```
     %2 = spirv.VectorExtractDynamic %0[%1] : vector<8xf32>, i32
     ```
   }];
 
   let arguments = (ins
-    SPV_Vector:$vector,
-    SPV_Integer:$index
+    SPIRV_Vector:$vector,
+    SPIRV_Integer:$index
   );
 
   let results = (outs
-    SPV_Scalar:$result
+    SPIRV_Scalar:$result
   );
 
   let hasVerifier = 0;
 
   let assemblyFormat = [{
     $vector `[` $index `]` attr-dict `:` type($vector) `,` type($index)
   }];
 }
 
 // -----
 
-def SPV_VectorInsertDynamicOp : SPV_Op<"VectorInsertDynamic", [
+def SPIRV_VectorInsertDynamicOp : SPIRV_Op<"VectorInsertDynamic", [
     NoSideEffect,
     TypesMatchWith<
       "type of 'component' matches element type of 'vector'",
       "vector", "component",
       "$_self.cast<mlir::VectorType>().getElementType()">,
     AllTypesMatch<["vector", "result"]>]> {
   let summary = [{
     Make a copy of a vector, with a single, variably selected, component
let description = [{
 
     ```
     %scalar = ... : f32
     %2 = spirv.VectorInsertDynamic %scalar %0[%1] : f32, vector<8xf32>, i32
     ```
   }];
 
   let arguments = (ins
-    SPV_Vector:$vector,
-    SPV_Scalar:$component,
-    SPV_Integer:$index
+    SPIRV_Vector:$vector,
+    SPIRV_Scalar:$component,
+    SPIRV_Integer:$index
   );
 
   let results = (outs
-    SPV_Vector:$result
+    SPIRV_Vector:$result
   );
 
   let hasVerifier = 0;
 
   let assemblyFormat = [{
     $component `,` $vector `[` $index `]` attr-dict `:` type($vector) `,` type($index)
   }];
 }
 
 // -----
 
-def SPV_VectorShuffleOp : SPV_Op<"VectorShuffle", [
+def SPIRV_VectorShuffleOp : SPIRV_Op<"VectorShuffle", [
     NoSideEffect, AllElementTypesMatch<["vector1", "vector2", "result"]>]> {
   let summary = [{
     Select arbitrary components from two vectors to make a new vector.
   }];
 
   let description = [{
     Result Type must be an OpTypeVector. The number of components in Result
     Type must be the same as the number of Component operands.
let description = [{
     ```mlir
     %0 = spirv.VectorShuffle [1: i32, 3: i32, 5: i32]
                            %vector1: vector<4xf32>, %vector2: vector<2xf32>
                         -> vector<3xf32>
     ```
   }];
 
   let arguments = (ins
-    SPV_Vector:$vector1,
-    SPV_Vector:$vector2,
+    SPIRV_Vector:$vector1,
+    SPIRV_Vector:$vector2,
     I32ArrayAttr:$components
   );
 
   let results = (outs
-    SPV_Vector:$result
+    SPIRV_Vector:$result
   );
 
   let assemblyFormat = [{
     attr-dict $components $vector1 `:` type($vector1) `,`
                           $vector2 `:` type($vector2) `->` type($result)
   }];
 }
 
 // -----
 
 #endif // MLIR_DIALECT_SPIRV_IR_COMPOSITE_OPS

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVControlFlowOps.td

 
 include "mlir/Dialect/SPIRV/IR/SPIRVBase.td"
 include "mlir/Interfaces/CallInterfaces.td"
 include "mlir/Interfaces/ControlFlowInterfaces.td"
 include "mlir/Interfaces/SideEffectInterfaces.td"
 
 // -----
 
-def SPV_BranchOp : SPV_Op<"Branch", [
+def SPIRV_BranchOp : SPIRV_Op<"Branch", [
     DeclareOpInterfaceMethods<BranchOpInterface>, InFunctionScope, NoSideEffect,
     Terminator]> {
   let summary = "Unconditional branch to target block.";
 
   let description = [{
     This instruction must be the last instruction in a block.
 
     <!-- End of AutoGen section -->
 
     ```
     branch-op ::= `spirv.Branch` successor
     successor ::= bb-id branch-use-list?
     branch-use-list ::= `(` ssa-use-list `:` type-list-no-parens `)`
     ```
 
     #### Example:
 
     ```mlir
     spirv.Branch ^target
     spirv.Branch ^target(%0, %1: i32, f32)
     ```
   }];
 
-  let arguments = (ins Variadic<SPV_Type>:$targetOperands);
+  let arguments = (ins Variadic<SPIRV_Type>:$targetOperands);
 
   let results = (outs);
 
   let successors = (successor AnySuccessor:$target);
 
   let hasVerifier = 0;
 
   let builders = [
def SPIRV_BranchOp : SPIRV_Op<"Branch", [
 
   let assemblyFormat = [{
     $target (`(` $targetOperands^ `:` type($targetOperands) `)`)? attr-dict
   }];
 }
 
 // -----
 
-def SPV_BranchConditionalOp : SPV_Op<"BranchConditional", [
+def SPIRV_BranchConditionalOp : SPIRV_Op<"BranchConditional", [
     AttrSizedOperandSegments, DeclareOpInterfaceMethods<BranchOpInterface>,
     InFunctionScope, NoSideEffect, Terminator]> {
   let summary = [{
     If Condition is true, branch to true block, otherwise branch to false
     block.
   }];
 
   let description = [{
let description = [{
 
     ```mlir
     spirv.BranchConditional %condition, ^true_branch, ^false_branch
     spirv.BranchConditional %condition, ^true_branch(%0: i32), ^false_branch(%1: i32)
     ```
   }];
 
   let arguments = (ins
-    SPV_Bool:$condition,
-    Variadic<SPV_Type>:$trueTargetOperands,
-    Variadic<SPV_Type>:$falseTargetOperands,
+    SPIRV_Bool:$condition,
+    Variadic<SPIRV_Type>:$trueTargetOperands,
+    Variadic<SPIRV_Type>:$falseTargetOperands,
     OptionalAttr<I32ArrayAttr>:$branch_weights
   );
 
   let results = (outs);
 
   let successors = (successor AnySuccessor:$trueTarget,
                               AnySuccessor:$falseTarget);
 
private:
     unsigned getFalseBlockArgumentIndex() {
       return getTrueBlockArgumentIndex() + getNumTrueBlockArguments();
     }
   }];
 }
 
 // -----
 
-def SPV_FunctionCallOp : SPV_Op<"FunctionCall", [
+def SPIRV_FunctionCallOp : SPIRV_Op<"FunctionCall", [
     InFunctionScope, DeclareOpInterfaceMethods<CallOpInterface>]> {
   let summary = "Call a function.";
 
   let description = [{
     Result Type is the type of the return value of the function. It must be
     the same as the Return Type operand of the Function Type operand of the
     Function operand.
 
let description = [{
     ```mlir
     spirv.FunctionCall @f_void(%arg0) : (i32) ->  ()
     %0 = spirv.FunctionCall @f_iadd(%arg0, %arg1) : (i32, i32) -> i32
     ```
   }];
 
   let arguments = (ins
     FlatSymbolRefAttr:$callee,
-    Variadic<SPV_Type>:$arguments
+    Variadic<SPIRV_Type>:$arguments
   );
 
   let results = (outs
-    Optional<SPV_Type>:$return_value
+    Optional<SPIRV_Type>:$return_value
   );
 
   let autogenSerialization = 0;
 
   let assemblyFormat = [{
     $callee `(` $arguments `)` attr-dict `:`
       functional-type($arguments, results)
   }];
 }
 
 // -----
 
-def SPV_LoopOp : SPV_Op<"mlir.loop", [InFunctionScope]> {
+def SPIRV_LoopOp : SPIRV_Op<"mlir.loop", [InFunctionScope]> {
   let summary = "Define a structured loop.";
 
   let description = [{
     SPIR-V can explicitly declare structured control-flow constructs using merge
     instructions. These explicitly declare a header block before the control
     flow diverges and a merge block where control flow subsequently converges.
     These blocks delimit constructs that must nest, and can only be entered
     and exited in structured ways. See "2.11. Structured Control Flow" of the
let description = [{
     header block, which is the second block. The loop merge block should be the
     last block. The merge block should only contain a `spirv.mlir.merge` op.
     The continue block should be the second to last block and it should have a
     branch to the loop header block. The loop continue block should be the only
     block, except the entry block, branching to the header block.
   }];
 
   let arguments = (ins
-    SPV_LoopControlAttr:$loop_control
+    SPIRV_LoopControlAttr:$loop_control
   );
 
   let results = (outs);
 
   let regions = (region AnyRegion:$body);
 
   let builders = [OpBuilder<(ins)>];
 
def SPIRV_LoopOp : SPIRV_Op<"mlir.loop", [InFunctionScope]> {
   let autogenSerialization = 0;
 
   let hasVerifier = 0;
   let hasRegionVerifier = 1;
 }
 
 // -----
 
-def SPV_MergeOp : SPV_Op<"mlir.merge", [NoSideEffect, Terminator]> {
+def SPIRV_MergeOp : SPIRV_Op<"mlir.merge", [NoSideEffect, Terminator]> {
   let summary = "A special terminator for merging a structured selection/loop.";
 
   let description = [{
     We use `spirv.mlir.selection`/`spirv.mlir.loop` for modelling structured selection/loop.
     This op is a terminator used inside their regions to mean jumping to the
     merge point, which is the next op following the `spirv.mlir.selection` or
     `spirv.mlir.loop` op. This op does not have a corresponding instruction in the
     SPIR-V binary format; it's solely for structural purpose.
   }];
 
   let arguments = (ins);
 
   let results = (outs);
 
   let assemblyFormat = "attr-dict";
 
   let hasOpcode = 0;
 
   let autogenSerialization = 0;
 }
 
 // -----
 
-def SPV_ReturnOp : SPV_Op<"Return", [InFunctionScope, NoSideEffect,
+def SPIRV_ReturnOp : SPIRV_Op<"Return", [InFunctionScope, NoSideEffect,
                                      Terminator]> {
   let summary = "Return with no value from a function with void return type.";
 
   let description = [{
     This instruction must be the last instruction in a block.
 
     <!-- End of AutoGen section -->
 
     ```
     return-op ::= `spirv.Return`
     ```
   }];
 
   let arguments = (ins);
 
   let results = (outs);
 
   let assemblyFormat = "attr-dict";
 }
 
 // -----
 
-def SPV_UnreachableOp : SPV_Op<"Unreachable", [InFunctionScope, Terminator]> {
+def SPIRV_UnreachableOp : SPIRV_Op<"Unreachable", [InFunctionScope, Terminator]> {
   let summary = "Behavior is undefined if this instruction is executed.";
 
   let description = [{
     This instruction must be the last instruction in a block.
 
     <!-- End of AutoGen section -->
 
     ```
     unreachable-op ::= `spirv.Unreachable`
     ```
   }];
 
   let arguments = (ins);
 
   let results = (outs);
 
   let assemblyFormat = "attr-dict";
 }
 
 // -----
 
-def SPV_ReturnValueOp : SPV_Op<"ReturnValue", [InFunctionScope, NoSideEffect,
+def SPIRV_ReturnValueOp : SPIRV_Op<"ReturnValue", [InFunctionScope, NoSideEffect,
                                                Terminator]> {
   let summary = "Return a value from a function.";
 
   let description = [{
     Value is the value returned, by copy, and must match the Return Type
     operand of the OpTypeFunction type of the OpFunction body this return
     instruction is in.
 
     This instruction must be the last instruction in a block.
 
     <!-- End of AutoGen section -->
 
     ```
     return-value-op ::= `spirv.ReturnValue` ssa-use `:` spirv-type
     ```
 
     #### Example:
 
     ```mlir
     spirv.ReturnValue %0 : f32
     ```
   }];
 
   let arguments = (ins
-    SPV_Type:$value
+    SPIRV_Type:$value
   );
 
   let results = (outs);
 
   let assemblyFormat = "$value attr-dict `:` type($value)";
 }
 
-def SPV_SelectionOp : SPV_Op<"mlir.selection", [InFunctionScope]> {
+def SPIRV_SelectionOp : SPIRV_Op<"mlir.selection", [InFunctionScope]> {
   let summary = "Define a structured selection.";
 
   let description = [{
     SPIR-V can explicitly declare structured control-flow constructs using merge
     instructions. These explicitly declare a header block before the control
     flow diverges and a merge block where control flow subsequently converges.
     These blocks delimit constructs that must nest, and can only be entered
     and exited in structured ways. See "2.11. Structured Control Flow" of the
     SPIR-V spec for more details.
 
     Instead of having a `spirv.SelectionMerge` op to directly model selection
     merge instruction for indicating the merge target, we use regions to delimit
     the boundary of the selection: the merge target is the next op following the
     `spirv.mlir.selection` op. This way it's easier to discover all blocks belonging to
     the selection and it plays nicer with the MLIR system.
 
     The `spirv.mlir.selection` region should contain at least two blocks: one selection
     header block, and one selection merge. The selection header block should be
     the first block. The selection merge block should be the last block.
     The merge block should only contain a `spirv.mlir.merge` op.
   }];
 
   let arguments = (ins
-    SPV_SelectionControlAttr:$selection_control
+    SPIRV_SelectionControlAttr:$selection_control
   );
 
   let results = (outs);
 
   let regions = (region AnyRegion:$body);
 
   let extraClassDeclaration = [{
     /// Returns the selection header block.

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCooperativeMatrixOps.td

 //
 //===----------------------------------------------------------------------===//
 
 #ifndef MLIR_DIALECT_SPIRV_IR_COOPERATIVE_MATRIX_OPS
 #define MLIR_DIALECT_SPIRV_IR_COOPERATIVE_MATRIX_OPS
 
 // -----
 
-def SPV_NVCooperativeMatrixLengthOp : SPV_NvVendorOp<"CooperativeMatrixLength",
+def SPIRV_NVCooperativeMatrixLengthOp : SPIRV_NvVendorOp<"CooperativeMatrixLength",
   [NoSideEffect]> {
-  let summary = "See extension SPV_NV_cooperative_matrix";
+  let summary = "See extension SPIRV_NV_cooperative_matrix";
 
   let description = [{
     Number of components of a cooperative matrix type accessible to each
     invocation when treated as a composite.
 
     Result Type must be an OpTypeInt with 32-bit Width and 0 Signedness.
 
     Type is a cooperative matrix type.
 
     ``` {.ebnf}
     cooperative-matrix-length-op ::= ssa-id `=` `spirv.NV.CooperativeMatrixLength
                                     ` : ` cooperative-matrix-type
     ```
 
     For example:
 
     ```
     %0 = spirv.NV.CooperativeMatrixLength : !spirv.coopmatrix<Subgroup, i32, 8, 16>
     ```
   }];
 
   let assemblyFormat = "attr-dict `:` $cooperative_matrix_type";
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
-    Extension<[SPV_NV_cooperative_matrix]>,
-    Capability<[SPV_C_CooperativeMatrixNV]>
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[SPIRV_NV_cooperative_matrix]>,
+    Capability<[SPIRV_C_CooperativeMatrixNV]>
   ];
 
   let arguments = (ins
     TypeAttr:$cooperative_matrix_type
   );
 
   let results = (outs
-    SPV_Int32:$result
+    SPIRV_Int32:$result
   );
   let hasVerifier = 0;
 }
 
 // -----
 
-def SPV_NVCooperativeMatrixLoadOp : SPV_NvVendorOp<"CooperativeMatrixLoad", []> {
-  let summary = "See extension SPV_NV_cooperative_matrix";
+def SPIRV_NVCooperativeMatrixLoadOp : SPIRV_NvVendorOp<"CooperativeMatrixLoad", []> {
+  let summary = "See extension SPIRV_NV_cooperative_matrix";
 
   let description = [{
     Load a cooperative matrix through a pointer.
 
     Result Type is the type of the loaded object. It must be a cooperative
     matrix type.
 
     Pointer is a pointer into an array. Its type must be an OpTypePointer whose
     Type operand is a scalar or vector type. The storage class of Pointer must
-    be Workgroup, StorageBuffer, or (if SPV_EXT_physical_storage_buffer is
+    be Workgroup, StorageBuffer, or (if SPIRV_EXT_physical_storage_buffer is
     supported) PhysicalStorageBufferEXT.
 
     Stride is the number of elements in the array in memory between the first
     component of consecutive rows (or columns) in the result. It must be a
     scalar integer type.
 
     ColumnMajor indicates whether the values loaded from memory are arranged in
     column-major or row-major order. It must be a boolean constant instruction,
let description = [{
 
     ```
     %0 = spirv.NV.CooperativeMatrixLoad %ptr, %stride, %colMajor
          : !spirv.ptr<i32, StorageBuffer> as !spirv.coopmatrix<i32, Workgroup, 16, 8>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
-    Extension<[SPV_NV_cooperative_matrix]>,
-    Capability<[SPV_C_CooperativeMatrixNV]>
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[SPIRV_NV_cooperative_matrix]>,
+    Capability<[SPIRV_C_CooperativeMatrixNV]>
   ];
 
   let arguments = (ins
-    SPV_AnyPtr:$pointer,
-    SPV_Integer:$stride,
-    SPV_Bool:$columnmajor,
-    OptionalAttr<SPV_MemoryAccessAttr>:$memory_access
+    SPIRV_AnyPtr:$pointer,
+    SPIRV_Integer:$stride,
+    SPIRV_Bool:$columnmajor,
+    OptionalAttr<SPIRV_MemoryAccessAttr>:$memory_access
   );
 
   let results = (outs
-    SPV_AnyCooperativeMatrix:$result
+    SPIRV_AnyCooperativeMatrix:$result
   );
 }
 
 // -----
 
-def SPV_NVCooperativeMatrixMulAddOp : SPV_NvVendorOp<"CooperativeMatrixMulAdd",
+def SPIRV_NVCooperativeMatrixMulAddOp : SPIRV_NvVendorOp<"CooperativeMatrixMulAdd",
   [NoSideEffect, AllTypesMatch<["c", "result"]>]> {
-  let summary = "See extension SPV_NV_cooperative_matrix";
+  let summary = "See extension SPIRV_NV_cooperative_matrix";
 
   let description = [{
     Linear-algebraic matrix multiply of A by B and then component-wise add C.
     The order of the operations is implementation-dependent. The internal
     precision of floating-point operations is defined by the client API.
     Integer operations are performed at the precision of the Result Type and are
     exact unless there is overflow or underflow, in which case the result is
     undefined.
let description = [{
     ```
   }];
 
   let assemblyFormat = [{
     operands attr-dict`:` type($a) `,` type($b) `->` type($c)
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
-    Extension<[SPV_NV_cooperative_matrix]>,
-    Capability<[SPV_C_CooperativeMatrixNV]>
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[SPIRV_NV_cooperative_matrix]>,
+    Capability<[SPIRV_C_CooperativeMatrixNV]>
   ];
 
   let arguments = (ins
-    SPV_AnyCooperativeMatrix:$a,
-    SPV_AnyCooperativeMatrix:$b,
-    SPV_AnyCooperativeMatrix:$c
+    SPIRV_AnyCooperativeMatrix:$a,
+    SPIRV_AnyCooperativeMatrix:$b,
+    SPIRV_AnyCooperativeMatrix:$c
   );
 
   let results = (outs
-    SPV_AnyCooperativeMatrix:$result
+    SPIRV_AnyCooperativeMatrix:$result
   );
 }
 
 // -----
 
-def SPV_NVCooperativeMatrixStoreOp : SPV_NvVendorOp<"CooperativeMatrixStore", []> {
-  let summary = "See extension SPV_NV_cooperative_matrix";
+def SPIRV_NVCooperativeMatrixStoreOp : SPIRV_NvVendorOp<"CooperativeMatrixStore", []> {
+  let summary = "See extension SPIRV_NV_cooperative_matrix";
 
   let description = [{
     Store a cooperative matrix through a pointer.
 
     Pointer is a pointer into an array. Its type must be an OpTypePointer whose
     Type operand is a scalar or vector type. The storage class of Pointer must
-    be Workgroup, StorageBuffer, or (if SPV_EXT_physical_storage_buffer is
+    be Workgroup, StorageBuffer, or (if SPIRV_EXT_physical_storage_buffer is
     supported) PhysicalStorageBufferEXT.
 
     Object is the object to store. Its type must be an
     OpTypeCooperativeMatrixNV.
 
     Stride is the number of elements in the array in memory between the first
     component of consecutive rows (or columns) in the result. It must be a
     scalar integer type.
let description = [{
 
     ```
       spirv.NV.CooperativeMatrixStore %arg0, %arg2, %arg1, %arg3 :
         !spirv.ptr<i32, StorageBuffer>, !spirv.coopmatrix<Workgroup, i32, 16, 8>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
-    Extension<[SPV_NV_cooperative_matrix]>,
-    Capability<[SPV_C_CooperativeMatrixNV]>
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[SPIRV_NV_cooperative_matrix]>,
+    Capability<[SPIRV_C_CooperativeMatrixNV]>
   ];
 
   let arguments = (ins
-    SPV_AnyPtr:$pointer,
-    SPV_AnyCooperativeMatrix:$object,
-    SPV_Integer:$stride,
-    SPV_Bool:$columnmajor,
-    OptionalAttr<SPV_MemoryAccessAttr>:$memory_access
+    SPIRV_AnyPtr:$pointer,
+    SPIRV_AnyCooperativeMatrix:$object,
+    SPIRV_Integer:$stride,
+    SPIRV_Bool:$columnmajor,
+    OptionalAttr<SPIRV_MemoryAccessAttr>:$memory_access
   );
 
   let results = (outs);
 }
 
 // -----
 
 #endif // MLIR_DIALECT_SPIRV_IR_COOPERATIVE_MATRIX_OPS

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGLOps.td

 include "mlir/Dialect/SPIRV/IR/SPIRVBase.td"
 include "mlir/Interfaces/SideEffectInterfaces.td"
 
 //===----------------------------------------------------------------------===//
 // SPIR-V GLSL 4.50 opcode specification.
 //===----------------------------------------------------------------------===//
 
 // Base class for all OpenGL ops.
-class SPV_GLOp<string mnemonic, int opcode, list<Trait> traits = []> :
-  SPV_ExtInstOp<mnemonic, "GL", "GLSL.std.450", opcode, traits> {
+class SPIRV_GLOp<string mnemonic, int opcode, list<Trait> traits = []> :
+  SPIRV_ExtInstOp<mnemonic, "GL", "GLSL.std.450", opcode, traits> {
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 }
 
 // Base class for GL unary ops.
-class SPV_GLUnaryOp<string mnemonic, int opcode, Type resultType,
+class SPIRV_GLUnaryOp<string mnemonic, int opcode, Type resultType,
                       Type operandType, list<Trait> traits = []> :
-  SPV_GLOp<mnemonic, opcode, !listconcat([NoSideEffect], traits)> {
+  SPIRV_GLOp<mnemonic, opcode, !listconcat([NoSideEffect], traits)> {
 
   let arguments = (ins
-    SPV_ScalarOrVectorOf<operandType>:$operand
+    SPIRV_ScalarOrVectorOf<operandType>:$operand
   );
 
   let results = (outs
-    SPV_ScalarOrVectorOf<resultType>:$result
+    SPIRV_ScalarOrVectorOf<resultType>:$result
   );
 
   let hasVerifier = 0;
 }
 
 // Base class for GL Unary arithmetic ops where return type matches
 // the operand type.
-class SPV_GLUnaryArithmeticOp<string mnemonic, int opcode, Type type,
+class SPIRV_GLUnaryArithmeticOp<string mnemonic, int opcode, Type type,
                                 list<Trait> traits = []> :
-  SPV_GLUnaryOp<mnemonic, opcode, type, type,
+  SPIRV_GLUnaryOp<mnemonic, opcode, type, type,
                   traits # [SameOperandsAndResultType]> {
   let assemblyFormat = "$operand `:` type($operand) attr-dict";
 }
 
 // Base class for GL binary ops.
-class SPV_GLBinaryOp<string mnemonic, int opcode, Type resultType,
+class SPIRV_GLBinaryOp<string mnemonic, int opcode, Type resultType,
                         Type operandType, list<Trait> traits = []> :
-  SPV_GLOp<mnemonic, opcode, !listconcat([NoSideEffect], traits)> {
+  SPIRV_GLOp<mnemonic, opcode, !listconcat([NoSideEffect], traits)> {
 
   let arguments = (ins
-    SPV_ScalarOrVectorOf<operandType>:$lhs,
-    SPV_ScalarOrVectorOf<operandType>:$rhs
+    SPIRV_ScalarOrVectorOf<operandType>:$lhs,
+    SPIRV_ScalarOrVectorOf<operandType>:$rhs
   );
 
   let results = (outs
-    SPV_ScalarOrVectorOf<resultType>:$result
+    SPIRV_ScalarOrVectorOf<resultType>:$result
   );
 
   let hasVerifier = 0;
 }
 
 // Base class for GL Binary arithmetic ops where operand types and
 // return type matches.
-class SPV_GLBinaryArithmeticOp<string mnemonic, int opcode, Type type,
+class SPIRV_GLBinaryArithmeticOp<string mnemonic, int opcode, Type type,
                                  list<Trait> traits = []> :
-  SPV_GLBinaryOp<mnemonic, opcode, type, type,
+  SPIRV_GLBinaryOp<mnemonic, opcode, type, type,
                    traits # [SameOperandsAndResultType]> {
   let assemblyFormat = "operands attr-dict `:` type($result)";
 }
 
 // Base class for GL ternary ops.
-class SPV_GLTernaryArithmeticOp<string mnemonic, int opcode, Type type,
+class SPIRV_GLTernaryArithmeticOp<string mnemonic, int opcode, Type type,
                         list<Trait> traits = []> :
-  SPV_GLOp<mnemonic, opcode, !listconcat([NoSideEffect], traits)> {
+  SPIRV_GLOp<mnemonic, opcode, !listconcat([NoSideEffect], traits)> {
 
   let arguments = (ins
-    SPV_ScalarOrVectorOf<type>:$x,
-    SPV_ScalarOrVectorOf<type>:$y,
-    SPV_ScalarOrVectorOf<type>:$z
+    SPIRV_ScalarOrVectorOf<type>:$x,
+    SPIRV_ScalarOrVectorOf<type>:$y,
+    SPIRV_ScalarOrVectorOf<type>:$z
   );
 
   let results = (outs
-    SPV_ScalarOrVectorOf<type>:$result
+    SPIRV_ScalarOrVectorOf<type>:$result
   );
 
   let hasCustomAssemblyFormat = 1;
   let hasVerifier = 0;
 }
 
 // -----
 
-def SPV_GLFAbsOp : SPV_GLUnaryArithmeticOp<"FAbs", 4, SPV_Float> {
+def SPIRV_GLFAbsOp : SPIRV_GLUnaryArithmeticOp<"FAbs", 4, SPIRV_Float> {
   let summary = "Absolute value of operand";
 
   let description = [{
     Result is x if x >= 0; otherwise result is -x.
 
     The operand x must be a scalar or vector whose component type is
     floating-point.
 
let description = [{
     %2 = spirv.GL.FAbs %0 : f32
     %3 = spirv.GL.FAbs %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLSAbsOp : SPV_GLUnaryArithmeticOp<"SAbs", 5, SPV_Integer> {
+def SPIRV_GLSAbsOp : SPIRV_GLUnaryArithmeticOp<"SAbs", 5, SPIRV_Integer> {
   let summary = "Absolute value of operand";
 
   let description = [{
     Result is x if x ≥ 0; otherwise result is -x, where x is interpreted as a
     signed integer.
 
     Result Type and the type of x must both be integer scalar or integer vector
     types. Result Type and operand types must have the same number of components
let description = [{
     %2 = spirv.GL.SAbs %0 : i32
     %3 = spirv.GL.SAbs %1 : vector<3xi16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLCeilOp : SPV_GLUnaryArithmeticOp<"Ceil", 9, SPV_Float> {
+def SPIRV_GLCeilOp : SPIRV_GLUnaryArithmeticOp<"Ceil", 9, SPIRV_Float> {
   let summary = "Rounds up to the next whole number";
 
   let description = [{
     Result is the value equal to the nearest whole number that is greater than
     or equal to x.
 
     The operand x must be a scalar or vector whose component type is
     floating-point.
let description = [{
     %2 = spirv.GL.Ceil %0 : f32
     %3 = spirv.GL.Ceil %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLCosOp : SPV_GLUnaryArithmeticOp<"Cos", 14, SPV_Float16or32> {
+def SPIRV_GLCosOp : SPIRV_GLUnaryArithmeticOp<"Cos", 14, SPIRV_Float16or32> {
   let summary = "Cosine of operand in radians";
 
   let description = [{
     The standard trigonometric cosine of x radians.
 
     The operand x must be a scalar or vector whose component type is 16-bit or
     32-bit floating-point.
 
let description = [{
     %2 = spirv.GL.Cos %0 : f32
     %3 = spirv.GL.Cos %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLSinOp : SPV_GLUnaryArithmeticOp<"Sin", 13, SPV_Float16or32> {
+def SPIRV_GLSinOp : SPIRV_GLUnaryArithmeticOp<"Sin", 13, SPIRV_Float16or32> {
   let summary = "Sine of operand in radians";
 
   let description = [{
     The standard trigonometric sine of x radians.
 
     The operand x must be a scalar or vector whose component type is 16-bit or
     32-bit floating-point.
 
let description = [{
     %2 = spirv.GL.Sin %0 : f32
     %3 = spirv.GL.Sin %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLTanOp : SPV_GLUnaryArithmeticOp<"Tan", 15, SPV_Float16or32> {
+def SPIRV_GLTanOp : SPIRV_GLUnaryArithmeticOp<"Tan", 15, SPIRV_Float16or32> {
   let summary = "Tangent of operand in radians";
 
   let description = [{
     The standard trigonometric tangent of x radians.
 
     The operand x must be a scalar or vector whose component type is 16-bit or
     32-bit floating-point.
 
let description = [{
     %2 = spirv.GL.Tan %0 : f32
     %3 = spirv.GL.Tan %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLAsinOp : SPV_GLUnaryArithmeticOp<"Asin", 16, SPV_Float16or32> {
+def SPIRV_GLAsinOp : SPIRV_GLUnaryArithmeticOp<"Asin", 16, SPIRV_Float16or32> {
   let summary = "Arc Sine of operand in radians";
 
   let description = [{
     The standard trigonometric arc sine of x radians.
 
     Result is an angle, in radians, whose sine is x. The range of result values
     is [-π / 2, π / 2]. Result is undefined if abs x > 1.
 
let description = [{
     %2 = spirv.GL.Asin %0 : f32
     %3 = spirv.GL.Asin %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLAcosOp : SPV_GLUnaryArithmeticOp<"Acos", 17, SPV_Float16or32> {
+def SPIRV_GLAcosOp : SPIRV_GLUnaryArithmeticOp<"Acos", 17, SPIRV_Float16or32> {
   let summary = "Arc Cosine of operand in radians";
 
   let description = [{
     The standard trigonometric arc cosine of x radians.
 
     Result is an angle, in radians, whose cosine is x. The range of result
     values is [0, π]. Result is undefined if abs x > 1.
 
let description = [{
     %2 = spirv.GL.Acos %0 : f32
     %3 = spirv.GL.Acos %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLAtanOp : SPV_GLUnaryArithmeticOp<"Atan", 18, SPV_Float16or32> {
+def SPIRV_GLAtanOp : SPIRV_GLUnaryArithmeticOp<"Atan", 18, SPIRV_Float16or32> {
   let summary = "Arc Tangent of operand in radians";
 
   let description = [{
     The standard trigonometric arc tangent of x radians.
 
     Result is an angle, in radians, whose tangent is y_over_x. The range of
     result values is [-π / 2, π / 2].
 
let description = [{
     %2 = spirv.GL.Atan %0 : f32
     %3 = spirv.GL.Atan %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLExpOp : SPV_GLUnaryArithmeticOp<"Exp", 27, SPV_Float16or32> {
+def SPIRV_GLExpOp : SPIRV_GLUnaryArithmeticOp<"Exp", 27, SPIRV_Float16or32> {
   let summary = "Exponentiation of Operand 1";
 
   let description = [{
     Result is the natural exponentiation of x; e^x.
 
     The operand x must be a scalar or vector whose component type is
     16-bit or 32-bit floating-point.
 
let description = [{
     %2 = spirv.GL.Exp %0 : f32
     %3 = spirv.GL.Exp %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLFloorOp : SPV_GLUnaryArithmeticOp<"Floor", 8, SPV_Float> {
+def SPIRV_GLFloorOp : SPIRV_GLUnaryArithmeticOp<"Floor", 8, SPIRV_Float> {
   let summary = "Rounds down to the next whole number";
 
   let description = [{
     Result is the value equal to the nearest whole number that is less than or
     equal to x.
 
     The operand x must be a scalar or vector whose component type is
     floating-point.
let description = [{
     %2 = spirv.GL.Floor %0 : f32
     %3 = spirv.GL.Floor %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLRoundOp: SPV_GLUnaryArithmeticOp<"Round", 1, SPV_Float> {
+def SPIRV_GLRoundOp: SPIRV_GLUnaryArithmeticOp<"Round", 1, SPIRV_Float> {
   let summary = "Rounds to the whole number";
 
   let description = [{
     Result is the value equal to the nearest whole number.
 
     The operand x must be a scalar or vector whose component type is
     floating-point.
 
let description = [{
     %2 = spirv.GL.Round %0 : f32
     %3 = spirv.GL.Round %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLInverseSqrtOp : SPV_GLUnaryArithmeticOp<"InverseSqrt", 32, SPV_Float> {
+def SPIRV_GLInverseSqrtOp : SPIRV_GLUnaryArithmeticOp<"InverseSqrt", 32, SPIRV_Float> {
   let summary = "Reciprocal of sqrt(operand)";
 
   let description = [{
     Result is the reciprocal of sqrt x. Result is undefined if x <= 0.
 
     The operand x must be a scalar or vector whose component type is
     floating-point.
 
let description = [{
     %2 = spirv.GL.InverseSqrt %0 : f32
     %3 = spirv.GL.InverseSqrt %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLLogOp : SPV_GLUnaryArithmeticOp<"Log", 28, SPV_Float16or32> {
+def SPIRV_GLLogOp : SPIRV_GLUnaryArithmeticOp<"Log", 28, SPIRV_Float16or32> {
   let summary = "Natural logarithm of the operand";
 
   let description = [{
     Result is the natural logarithm of x, i.e., the value y which satisfies the
     equation x = ey. Result is undefined if x <= 0.
 
     The operand x must be a scalar or vector whose component type is 16-bit or
     32-bit floating-point.
let description = [{
     %2 = spirv.GL.Log %0 : f32
     %3 = spirv.GL.Log %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLFMaxOp : SPV_GLBinaryArithmeticOp<"FMax", 40, SPV_Float> {
+def SPIRV_GLFMaxOp : SPIRV_GLBinaryArithmeticOp<"FMax", 40, SPIRV_Float> {
   let summary = "Return maximum of two floating-point operands";
 
   let description = [{
     Result is y if x < y; otherwise result is x. Which operand is the
     result is undefined if one of the operands is a NaN.
 
     The operands must all be a scalar or vector whose component type
     is floating-point.
let description = [{
     %2 = spirv.GL.FMax %0, %1 : f32
     %3 = spirv.GL.FMax %0, %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLUMaxOp : SPV_GLBinaryArithmeticOp<"UMax", 41, SPV_Integer> {
+def SPIRV_GLUMaxOp : SPIRV_GLBinaryArithmeticOp<"UMax", 41, SPIRV_Integer> {
   let summary = "Return maximum of two unsigned integer operands";
 
   let description = [{
     Result is y if x < y; otherwise result is x, where x and y are interpreted
     as unsigned integers.
 
     Result Type and the type of x and y must both be integer scalar or integer
     vector types. Result Type and operand types must have the same number of
let description = [{
     %2 = spirv.GL.UMax %0, %1 : i32
     %3 = spirv.GL.UMax %0, %1 : vector<3xi16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLSMaxOp : SPV_GLBinaryArithmeticOp<"SMax", 42, SPV_Integer> {
+def SPIRV_GLSMaxOp : SPIRV_GLBinaryArithmeticOp<"SMax", 42, SPIRV_Integer> {
   let summary = "Return maximum of two signed integer operands";
 
   let description = [{
     Result is y if x < y; otherwise result is x, where x and y are interpreted
     as signed integers.
 
     Result Type and the type of x and y must both be integer scalar or integer
     vector types. Result Type and operand types must have the same number of
let description = [{
     %2 = spirv.GL.SMax %0, %1 : i32
     %3 = spirv.GL.SMax %0, %1 : vector<3xi16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLFMinOp : SPV_GLBinaryArithmeticOp<"FMin", 37, SPV_Float> {
+def SPIRV_GLFMinOp : SPIRV_GLBinaryArithmeticOp<"FMin", 37, SPIRV_Float> {
   let summary = "Return minimum of two floating-point operands";
 
   let description = [{
     Result is y if y < x; otherwise result is x. Which operand is the result is
     undefined if one of the operands is a NaN.
 
     The operands must all be a scalar or vector whose component type is
     floating-point.
let description = [{
     %2 = spirv.GL.FMin %0, %1 : f32
     %3 = spirv.GL.FMin %0, %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLUMinOp : SPV_GLBinaryArithmeticOp<"UMin", 38, SPV_Integer> {
+def SPIRV_GLUMinOp : SPIRV_GLBinaryArithmeticOp<"UMin", 38, SPIRV_Integer> {
   let summary = "Return minimum of two unsigned integer operands";
 
   let description = [{
     Result is y if y < x; otherwise result is x, where x and y are interpreted
     as unsigned integers.
 
     Result Type and the type of x and y must both be integer scalar or integer
     vector types. Result Type and operand types must have the same number of
let description = [{
     %2 = spirv.GL.UMin %0, %1 : i32
     %3 = spirv.GL.UMin %0, %1 : vector<3xi16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLSMinOp : SPV_GLBinaryArithmeticOp<"SMin", 39, SPV_Integer> {
+def SPIRV_GLSMinOp : SPIRV_GLBinaryArithmeticOp<"SMin", 39, SPIRV_Integer> {
   let summary = "Return minimum of two signed integer operands";
 
   let description = [{
     Result is y if y < x; otherwise result is x, where x and y are interpreted
     as signed integers.
 
     Result Type and the type of x and y must both be integer scalar or integer
     vector types. Result Type and operand types must have the same number of
let description = [{
     %2 = spirv.GL.SMin %0, %1 : i32
     %3 = spirv.GL.SMin %0, %1 : vector<3xi16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLPowOp : SPV_GLBinaryArithmeticOp<"Pow", 26, SPV_Float16or32> {
+def SPIRV_GLPowOp : SPIRV_GLBinaryArithmeticOp<"Pow", 26, SPIRV_Float16or32> {
   let summary = "Return x raised to the y power of two operands";
 
   let description = [{
     Result is x raised to the y power; x^y.
 
     Result is undefined if x = 0 and y ≤ 0.
 
     The operand x and y must be a scalar or vector whose component type is
let description = [{
     %2 = spirv.GL.Pow %0, %1 : f32
     %3 = spirv.GL.Pow %0, %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLFSignOp : SPV_GLUnaryArithmeticOp<"FSign", 6, SPV_Float> {
+def SPIRV_GLFSignOp : SPIRV_GLUnaryArithmeticOp<"FSign", 6, SPIRV_Float> {
   let summary = "Returns the sign of the operand";
 
   let description = [{
     Result is 1.0 if x > 0, 0.0 if x = 0, or -1.0 if x < 0.
 
     The operand x must be a scalar or vector whose component type is
     floating-point.
 
let description = [{
     %2 = spirv.GL.FSign %0 : f32
     %3 = spirv.GL.FSign %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLSSignOp : SPV_GLUnaryArithmeticOp<"SSign", 7, SPV_Integer> {
+def SPIRV_GLSSignOp : SPIRV_GLUnaryArithmeticOp<"SSign", 7, SPIRV_Integer> {
   let summary = "Returns the sign of the operand";
 
   let description = [{
     Result is 1 if x > 0, 0 if x = 0, or -1 if x < 0, where x is interpreted as
     a signed integer.
 
     Result Type and the type of x must both be integer scalar or integer vector
     types. Result Type and operand types must have the same number of components
let description = [{
     %2 = spirv.GL.SSign %0 : i32
     %3 = spirv.GL.SSign %1 : vector<3xi16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLSqrtOp : SPV_GLUnaryArithmeticOp<"Sqrt", 31, SPV_Float> {
+def SPIRV_GLSqrtOp : SPIRV_GLUnaryArithmeticOp<"Sqrt", 31, SPIRV_Float> {
   let summary = "Returns the square root of the operand";
 
   let description = [{
     Result is the square root of x. Result is undefined if x < 0.
 
     The operand x must be a scalar or vector whose component type is
     floating-point.
 
let description = [{
     %2 = spirv.GL.Sqrt %0 : f32
     %3 = spirv.GL.Sqrt %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLSinhOp : SPV_GLUnaryArithmeticOp<"Sinh", 19, SPV_Float16or32> {
+def SPIRV_GLSinhOp : SPIRV_GLUnaryArithmeticOp<"Sinh", 19, SPIRV_Float16or32> {
   let summary = "Hyperbolic sine of operand in radians";
 
   let description = [{
     Hyperbolic sine of x radians.
 
     The operand x must be a scalar or vector whose component type is 16-bit or
     32-bit floating-point.
 
let description = [{
     %2 = spirv.GL.Sinh %0 : f32
     %3 = spirv.GL.Sinh %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLCoshOp : SPV_GLUnaryArithmeticOp<"Cosh", 20, SPV_Float16or32> {
+def SPIRV_GLCoshOp : SPIRV_GLUnaryArithmeticOp<"Cosh", 20, SPIRV_Float16or32> {
   let summary = "Hyperbolic cosine of operand in radians";
 
   let description = [{
     Hyperbolic cosine of x radians.
 
     The operand x must be a scalar or vector whose component type is 16-bit or
     32-bit floating-point.
 
let description = [{
     %2 = spirv.GL.Cosh %0 : f32
     %3 = spirv.GL.Cosh %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLTanhOp : SPV_GLUnaryArithmeticOp<"Tanh", 21, SPV_Float16or32> {
+def SPIRV_GLTanhOp : SPIRV_GLUnaryArithmeticOp<"Tanh", 21, SPIRV_Float16or32> {
   let summary = "Hyperbolic tangent of operand in radians";
 
   let description = [{
     Hyperbolic tangent of x radians.
 
     The operand x must be a scalar or vector whose component type is 16-bit or
     32-bit floating-point.
 
let description = [{
     %2 = spirv.GL.Tanh %0 : f32
     %3 = spirv.GL.Tanh %1 : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLFClampOp : SPV_GLTernaryArithmeticOp<"FClamp", 43, SPV_Float> {
+def SPIRV_GLFClampOp : SPIRV_GLTernaryArithmeticOp<"FClamp", 43, SPIRV_Float> {
   let summary = "Clamp x between min and max values.";
 
   let description = [{
     Result is min(max(x, minVal), maxVal). The resulting value is undefined if
     minVal > maxVal. The semantics used by min() and max() are those of FMin and
     FMax.
 
     The operands must all be a scalar or vector whose component type is
let description = [{
     %2 = spirv.GL.FClamp %x, %min, %max : f32
     %3 = spirv.GL.FClamp %x, %min, %max : vector<3xf16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLUClampOp : SPV_GLTernaryArithmeticOp<"UClamp", 44, SPV_Integer> {
+def SPIRV_GLUClampOp : SPIRV_GLTernaryArithmeticOp<"UClamp", 44, SPIRV_Integer> {
   let summary = "Clamp x between min and max values.";
 
   let description = [{
     Result is min(max(x, minVal), maxVal), where x, minVal and maxVal are
     interpreted as unsigned integers. The resulting value is undefined if
     minVal > maxVal.
 
     Result Type and the type of the operands must both be integer scalar or
let description = [{
     %2 = spirv.GL.UClamp %x, %min, %max : i32
     %3 = spirv.GL.UClamp %x, %min, %max : vector<3xui16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLSClampOp : SPV_GLTernaryArithmeticOp<"SClamp", 45, SPV_Integer> {
+def SPIRV_GLSClampOp : SPIRV_GLTernaryArithmeticOp<"SClamp", 45, SPIRV_Integer> {
   let summary = "Clamp x between min and max values.";
 
   let description = [{
     Result is min(max(x, minVal), maxVal), where x, minVal and maxVal are
     interpreted as signed integers. The resulting value is undefined if
     minVal > maxVal.
 
     Result Type and the type of the operands must both be integer scalar or
let description = [{
     %2 = spirv.GL.SClamp %x, %min, %max : si32
     %3 = spirv.GL.SClamp %x, %min, %max : vector<3xsi16>
     ```
   }];
 }
 
 // -----
 
-def SPV_GLFmaOp : SPV_GLTernaryArithmeticOp<"Fma", 50, SPV_Float> {
+def SPIRV_GLFmaOp : SPIRV_GLTernaryArithmeticOp<"Fma", 50, SPIRV_Float> {
   let summary = "Computes a * b + c.";
 
   let description = [{
     In uses where this operation is decorated with NoContraction:
 
     - fma is considered a single operation, whereas the expression a * b + c
       is considered two operations.
     - The precision of fma can differ from the precision of the expression
let description = [{
     %0 = spirv.GL.Fma %a, %b, %c : f32
     %1 = spirv.GL.Fma %a, %b, %c : vector<3xf16>
     ```
   }];
 }
 
 // ----
 
-def SPV_GLFrexpStructOp : SPV_GLOp<"FrexpStruct", 52, [NoSideEffect]> {
+def SPIRV_GLFrexpStructOp : SPIRV_GLOp<"FrexpStruct", 52, [NoSideEffect]> {
   let summary = "Splits x into two components such that x = significand * 2^exponent";
 
   let description = [{
     Result is a structure containing x split into a floating-point significand
     in the range (-1.0, 0.5] or [0.5, 1.0) and an integral exponent of 2, such that:
 
     x = significand * 2^exponent
 
let description = [{
 
     ```mlir
     %2 = spirv.GL.FrexpStruct %0 : f32 -> !spirv.struct<f32, i32>
     %3 = spirv.GL.FrexpStruct %0 : vector<3xf32> -> !spirv.struct<vector<3xf32>, vector<3xi32>>
     ```
   }];
 
   let arguments = (ins
-    SPV_ScalarOrVectorOf<SPV_Float>:$operand
+    SPIRV_ScalarOrVectorOf<SPIRV_Float>:$operand
   );
 
   let results = (outs
-    SPV_AnyStruct:$result
+    SPIRV_AnyStruct:$result
   );
 
   let assemblyFormat = [{
     attr-dict $operand `:` type($operand) `->` type($result)
   }];
 }
 
-def SPV_GLLdexpOp :
-  SPV_GLOp<"Ldexp", 53, [
+def SPIRV_GLLdexpOp :
+  SPIRV_GLOp<"Ldexp", 53, [
       NoSideEffect, AllTypesMatch<["x", "y"]>]> {
   let summary = "Builds y such that y = significand * 2^exponent";
 
   let description = [{
     Builds a floating-point number from x and the corresponding
     integral exponent of two in exp:
 
     significand * 2^exponent
let description = [{
 
     ```mlir
     %y = spirv.GL.Ldexp %x : f32, %exp : i32 -> f32
     %y = spirv.GL.Ldexp %x : vector<3xf32>, %exp : vector<3xi32> -> vector<3xf32>
     ```
   }];
 
   let arguments = (ins
-    SPV_ScalarOrVectorOf<SPV_Float>:$x,
-    SPV_ScalarOrVectorOf<SPV_Integer>:$exp
+    SPIRV_ScalarOrVectorOf<SPIRV_Float>:$x,
+    SPIRV_ScalarOrVectorOf<SPIRV_Integer>:$exp
   );
 
   let results = (outs
-    SPV_ScalarOrVectorOf<SPV_Float>:$y
+    SPIRV_ScalarOrVectorOf<SPIRV_Float>:$y
   );
 
   let assemblyFormat = [{
     attr-dict $x `:` type($x) `,` $exp `:` type($exp) `->` type($y)
   }];
 }
 
-def SPV_GLFMixOp :
-  SPV_GLOp<"FMix", 46, [
+def SPIRV_GLFMixOp :
+  SPIRV_GLOp<"FMix", 46, [
       NoSideEffect, AllTypesMatch<["x", "y", "a", "result"]>]> {
   let summary = "Builds the linear blend of x and y";
 
   let description = [{
     Result is the linear blend of x and y, i.e., x * (1 - a) + y * a.
 
     The operands must all be a scalar or vector whose component type is floating-point.
 
     Result Type and the type of all operands must be the same type. Results are computed per component.
 
     <!-- End of AutoGen section -->
 
     #### Example:
 
     ```mlir
     %0 = spirv.GL.FMix %x : f32, %y : f32, %a : f32 -> f32
     %0 = spirv.GL.FMix %x : vector<4xf32>, %y : vector<4xf32>, %a : vector<4xf32> -> vector<4xf32>
     ```
   }];
 
   let arguments = (ins
-    SPV_ScalarOrVectorOf<SPV_Float>:$x,
-    SPV_ScalarOrVectorOf<SPV_Float>:$y,
-    SPV_ScalarOrVectorOf<SPV_Float>:$a
+    SPIRV_ScalarOrVectorOf<SPIRV_Float>:$x,
+    SPIRV_ScalarOrVectorOf<SPIRV_Float>:$y,
+    SPIRV_ScalarOrVectorOf<SPIRV_Float>:$a
   );
 
   let results = (outs
-    SPV_ScalarOrVectorOf<SPV_Float>:$result
+    SPIRV_ScalarOrVectorOf<SPIRV_Float>:$result
   );
 
   let assemblyFormat = [{
     attr-dict $x `:` type($x) `,` $y `:` type($y) `,` $a `:` type($a) `->` type($result)
   }];
 
   let hasVerifier = 0;
 }
 
-def SPV_GLFindUMsbOp : SPV_GLUnaryArithmeticOp<"FindUMsb", 75, SPV_Int32> {
+def SPIRV_GLFindUMsbOp : SPIRV_GLUnaryArithmeticOp<"FindUMsb", 75, SPIRV_Int32> {
   let summary = "Unsigned-integer most-significant bit";
 
   let description = [{
     Results in the bit number of the most-significant 1-bit in the binary
     representation of Value. If Value is 0, the result is -1.
 
     Result Type and the type of Value must both be integer scalar or
     integer vector types. Result Type and operand types must have the
     same number of components with the same component width. Results are
     computed per component.
 
     This instruction is currently limited to 32-bit width components.
   }];
 }
 
 #endif // MLIR_DIALECT_SPIRV_IR_GL_OPS

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td

 //
 //===----------------------------------------------------------------------===//
 
 #ifndef MLIR_DIALECT_SPIRV_IR_GROUP_OPS
 #define MLIR_DIALECT_SPIRV_IR_GROUP_OPS
 
 // -----
 
-def SPV_GroupBroadcastOp : SPV_Op<"GroupBroadcast",
-  [NoSideEffect, AllTypesMatch<["value", "result"]>]> {
+def SPIRV_GroupBroadcastOp : SPIRV_Op<"GroupBroadcast",
+                              [NoSideEffect,
+                               AllTypesMatch<["value", "result"]>]> {
   let summary = [{
     Broadcast the Value of the invocation identified by the local id LocalId
     to the result of all invocations in the group.
   }];
 
   let description = [{
     All invocations of this module within Execution must reach this point of
     execution.
let description = [{
     %vector_localid = ... : vector<3xi32>
     %0 = spirv.GroupBroadcast "Subgroup" %scalar_value, %scalar_localid : f32, i32
     %1 = spirv.GroupBroadcast "Workgroup" %vector_value, %vector_localid :
       vector<4xf32>, vector<3xi32>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_Groups]>
+    Capability<[SPIRV_C_Groups]>
   ];
 
   let arguments = (ins
-    SPV_ScopeAttr:$execution_scope,
-    SPV_Type:$value,
-    SPV_ScalarOrVectorOf<SPV_Integer>:$localid
+    SPIRV_ScopeAttr:$execution_scope,
+    SPIRV_Type:$value,
+    SPIRV_ScalarOrVectorOf<SPIRV_Integer>:$localid
   );
 
   let results = (outs
-    SPV_Type:$result
+    SPIRV_Type:$result
   );
 
   let assemblyFormat = [{
     $execution_scope operands attr-dict `:` type($value) `,` type($localid)
   }];
 }
 
 // -----
 
-def SPV_KHRSubgroupBallotOp : SPV_KhrVendorOp<"SubgroupBallot", []> {
-  let summary = "See extension SPV_KHR_shader_ballot";
+def SPIRV_KHRSubgroupBallotOp : SPIRV_KhrVendorOp<"SubgroupBallot", []> {
+  let summary = "See extension SPIRV_KHR_shader_ballot";
 
   let description = [{
     Computes a bitfield value combining the Predicate value from all invocations
     in the current Subgroup that execute the same dynamic instance of this
     instruction. The bit is set to one if the corresponding invocation is active
     and the predicate is evaluated to true; otherwise, it is set to zero.
 
     Predicate must be a Boolean type.
let description = [{
     #### Example:
 
     ```mlir
     %0 = spirv.KHR.SubgroupBallot %predicate : vector<4xi32>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
-    Extension<[SPV_KHR_shader_ballot]>,
-    Capability<[SPV_C_SubgroupBallotKHR]>
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[SPIRV_KHR_shader_ballot]>,
+    Capability<[SPIRV_C_SubgroupBallotKHR]>
   ];
 
   let arguments = (ins
-    SPV_Bool:$predicate
+    SPIRV_Bool:$predicate
   );
 
   let results = (outs
-    SPV_Int32Vec4:$result
+    SPIRV_Int32Vec4:$result
   );
 
   let hasVerifier = 0;
 
   let assemblyFormat = "$predicate attr-dict `:` type($result)";
 }
 
 // -----
 
-def SPV_INTELSubgroupBlockReadOp : SPV_IntelVendorOp<"SubgroupBlockRead", []> {
-  let summary = "See extension SPV_INTEL_subgroups";
+def SPIRV_INTELSubgroupBlockReadOp : SPIRV_IntelVendorOp<"SubgroupBlockRead", []> {
+  let summary = "See extension SPIRV_INTEL_subgroups";
 
   let description = [{
     Reads one or more components of Result data for each invocation in the
     subgroup from the specified Ptr as a block operation.
 
     The data is read strided, so the first value read is:
     Ptr[ SubgroupLocalInvocationId ]
 
let description = [{
     #### Example:
 
     ```
     %0 = spirv.INTEL.SubgroupBlockRead "StorageBuffer" %ptr : i32
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
-    Extension<[SPV_INTEL_subgroups]>,
-    Capability<[SPV_C_SubgroupBufferBlockIOINTEL]>
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[SPIRV_INTEL_subgroups]>,
+    Capability<[SPIRV_C_SubgroupBufferBlockIOINTEL]>
   ];
 
   let arguments = (ins
-    SPV_AnyPtr:$ptr
+    SPIRV_AnyPtr:$ptr
   );
 
   let results = (outs
-    SPV_Type:$value
+    SPIRV_Type:$value
   );
 }
 
 // -----
 
-def SPV_INTELSubgroupBlockWriteOp : SPV_IntelVendorOp<"SubgroupBlockWrite", []> {
-  let summary = "See extension SPV_INTEL_subgroups";
+def SPIRV_INTELSubgroupBlockWriteOp : SPIRV_IntelVendorOp<"SubgroupBlockWrite", []> {
+  let summary = "See extension SPIRV_INTEL_subgroups";
 
   let description = [{
     Writes one or more components of Data for each invocation in the subgroup
     from the specified Ptr as a block operation.
 
     The data is written strided, so the first value is written to:
     Ptr[ SubgroupLocalInvocationId ]
 
let description = [{
     #### Example:
 
     ```
     spirv.INTEL.SubgroupBlockWrite "StorageBuffer" %ptr, %value : i32
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
-    Extension<[SPV_INTEL_subgroups]>,
-    Capability<[SPV_C_SubgroupBufferBlockIOINTEL]>
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[SPIRV_INTEL_subgroups]>,
+    Capability<[SPIRV_C_SubgroupBufferBlockIOINTEL]>
   ];
 
   let arguments = (ins
-    SPV_AnyPtr:$ptr,
-    SPV_Type:$value
+    SPIRV_AnyPtr:$ptr,
+    SPIRV_Type:$value
   );
 
   let results = (outs);
 }
 
 // -----
 
 #endif // MLIR_DIALECT_SPIRV_IR_GROUP_OPS

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVImageOps.td

 #ifndef MLIR_DIALECT_SPIRV_IR_IMAGE_OPS
 #define MLIR_DIALECT_SPIRV_IR_IMAGE_OPS
 
 include "mlir/Dialect/SPIRV/IR/SPIRVBase.td"
 include "mlir/Interfaces/SideEffectInterfaces.td"
 
 // -----
 
-def SPV_ImageDrefGatherOp : SPV_Op<"ImageDrefGather", [NoSideEffect]> {
+def SPIRV_ImageDrefGatherOp : SPIRV_Op<"ImageDrefGather", [NoSideEffect]> {
   let summary = "Gathers the requested depth-comparison from four texels.";
 
   let description = [{
     Result Type must be a vector of four components of floating-point type
     or integer type.  Its components must be the same as Sampled Type of the
     underlying OpTypeImage (unless that underlying Sampled Type is
     OpTypeVoid). It has one component per gathered texel.
 
let description = [{
 
     ```mlir
     %0 = spirv.ImageDrefGather %1 : !spirv.sampled_image<!spirv.image<i32, Dim2D, NoDepth, NonArrayed, SingleSampled, NoSampler, Unknown>>, %2 : vector<4xf32>, %3 : f32 -> vector<4xi32>
     %0 = spirv.ImageDrefGather %1 : !spirv.sampled_image<!spirv.image<i32, Dim2D, NoDepth, NonArrayed, SingleSampled, NoSampler, Unknown>>, %2 : vector<4xf32>, %3 : f32 ["NonPrivateTexel"] : f32, f32 -> vector<4xi32>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_Shader]>
+    Capability<[SPIRV_C_Shader]>
   ];
 
   let arguments = (ins
-    SPV_AnySampledImage:$sampledimage,
-    SPV_ScalarOrVectorOf<SPV_Float>:$coordinate,
-    SPV_Float:$dref,
-    OptionalAttr<SPV_ImageOperandsAttr>:$imageoperands,
-    Variadic<SPV_Type>:$operand_arguments
+    SPIRV_AnySampledImage:$sampledimage,
+    SPIRV_ScalarOrVectorOf<SPIRV_Float>:$coordinate,
+    SPIRV_Float:$dref,
+    OptionalAttr<SPIRV_ImageOperandsAttr>:$imageoperands,
+    Variadic<SPIRV_Type>:$operand_arguments
   );
 
   let results = (outs
-    SPV_Vector:$result
+    SPIRV_Vector:$result
   );
 
   let assemblyFormat = [{$sampledimage `:` type($sampledimage) `,`
                          $coordinate `:` type($coordinate) `,` $dref `:` type($dref)
                          custom<ImageOperands>($imageoperands)
                          ( `(` $operand_arguments^ `:` type($operand_arguments) `)`)?
                          attr-dict
                          `->` type($result)}];
 }
 
 // -----
 
-def SPV_ImageQuerySizeOp : SPV_Op<"ImageQuerySize", [NoSideEffect]> {
+def SPIRV_ImageQuerySizeOp : SPIRV_Op<"ImageQuerySize", [NoSideEffect]> {
   let summary = "Query the dimensions of Image, with no level of detail.";
 
   let description = [{
     Result Type must be an integer type scalar or vector.  The number of
     components must be:
 
     1 for the 1D and Buffer dimensionalities,
 
let description = [{
     %3 = spirv.ImageQuerySize %0 : !spirv.image<i32, Dim1D, NoDepth, NonArrayed, SingleSampled, NoSampler, Unknown> -> i32
     %4 = spirv.ImageQuerySize %1 : !spirv.image<i32, Dim2D, NoDepth, NonArrayed, SingleSampled, NoSampler, Unknown> -> vector<2xi32>
     %5 = spirv.ImageQuerySize %2 : !spirv.image<i32, Dim2D, NoDepth, Arrayed, SingleSampled, NoSampler, Unknown> -> vector<3xi32>
     ```
 
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_ImageQuery, SPV_C_Kernel]>
+    Capability<[SPIRV_C_ImageQuery, SPIRV_C_Kernel]>
   ];
 
   let arguments = (ins
-    SPV_AnyImage:$image
+    SPIRV_AnyImage:$image
   );
 
   let results = (outs
-    SPV_ScalarOrVectorOf<SPV_Integer>:$result
+    SPIRV_ScalarOrVectorOf<SPIRV_Integer>:$result
   );
 
   let assemblyFormat = "attr-dict $image `:` type($image) `->` type($result)";
 }
 
 // -----
 
-def SPV_ImageOp : SPV_Op<"Image",
+def SPIRV_ImageOp : SPIRV_Op<"Image",
     [NoSideEffect,
      TypesMatchWith<"type of 'result' matches image type of 'sampledimage'",
                     "sampledimage", "result",
                     "$_self.cast<spirv::SampledImageType>().getImageType()">]> {
   let summary = "Extract the image from a sampled image.";
 
   let description = [{
     Result Type must be OpTypeImage.
 
     Sampled Image must have type OpTypeSampledImage whose Image Type is the
     same as Result Type.
 
     <!-- End of AutoGen section -->
 
     #### Example:
 
     ```mlir
     %0 = spirv.Image %1 : !spirv.sampled_image<!spirv.image<f32, Cube, NoDepth, NonArrayed, SingleSampled, NoSampler, Unknown>>
     ```
   }];
 
   let arguments = (ins
-    SPV_AnySampledImage:$sampledimage
+    SPIRV_AnySampledImage:$sampledimage
   );
 
   let results = (outs
-    SPV_AnyImage:$result
+    SPIRV_AnyImage:$result
   );
 
   let assemblyFormat = "attr-dict $sampledimage `:` type($sampledimage)";
 
   let hasVerifier = 0;
 }
 
 #endif // MLIR_DIALECT_SPIRV_IR_GL_OPS

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVJointMatrixOps.td

 //
 //===----------------------------------------------------------------------===//
 
 #ifndef MLIR_DIALECT_SPIRV_IR_JOINT_MATRIX_OPS
 #define MLIR_DIALECT_SPIRV_IR_JOINT_MATRIX_OPS
 
 // -----
 
-def SPV_INTELJointMatrixWorkItemLengthOp : SPV_IntelVendorOp<"JointMatrixWorkItemLength",
+def SPIRV_INTELJointMatrixWorkItemLengthOp : SPIRV_IntelVendorOp<"JointMatrixWorkItemLength",
   [NoSideEffect]> {
-  let summary = "See extension SPV_INTEL_joint_matrix";
+  let summary = "See extension SPIRV_INTEL_joint_matrix";
 
   let description = [{
     Return number of components owned by the current work-item in
     a joint matrix.
 
     Result Type must be an 32-bit unsigned integer type scalar.
 
     Type is a joint matrix type.
 
     ``` {.ebnf}
     joint-matrix-length-op ::= ssa-id `=` `spirv.INTEL.JointMatrixWorkItemLength
                                     ` : ` joint-matrix-type
     ```
 
     For example:
 
     ```
     %0 = spirv.INTEL.JointMatrixWorkItemLength : !spirv.jointmatrix<Subgroup, i32, 8, 16>
     ```
   }];
 
   let assemblyFormat = "attr-dict `:` $joint_matrix_type";
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
-    Extension<[SPV_INTEL_joint_matrix]>,
-    Capability<[SPV_C_JointMatrixINTEL]>
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[SPIRV_INTEL_joint_matrix]>,
+    Capability<[SPIRV_C_JointMatrixINTEL]>
   ];
 
   let arguments = (ins
     TypeAttr:$joint_matrix_type
   );
 
   let results = (outs
-    SPV_Int32:$result
+    SPIRV_Int32:$result
   );
   let hasVerifier = 0;
 }
 
 // -----
 
-def SPV_INTELJointMatrixLoadOp : SPV_IntelVendorOp<"JointMatrixLoad", []> {
-  let summary = "See extension SPV_INTEL_joint_matrix";
+def SPIRV_INTELJointMatrixLoadOp : SPIRV_IntelVendorOp<"JointMatrixLoad", []> {
+  let summary = "See extension SPIRV_INTEL_joint_matrix";
 
   let description = [{
     Load a matrix through a pointer.
 
     Result Type is the type of the loaded matrix. It must be OpTypeJointMatrixINTEL.
 
     Pointer is the pointer to load through. It specifies start of memory region where
     elements of the matrix are stored and arranged according to Layout.
let description = [{
     ```
   }];
 
   let assemblyFormat = [{
     $scope $layout operands attr-dict `:` `(` type(operands) `)` `->` type($result)
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
-    Extension<[SPV_INTEL_joint_matrix]>,
-    Capability<[SPV_C_JointMatrixINTEL]>
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[SPIRV_INTEL_joint_matrix]>,
+    Capability<[SPIRV_C_JointMatrixINTEL]>
   ];
 
   let arguments = (ins
-    SPV_AnyPtr:$pointer,
-    SPV_Integer:$stride,
-    SPV_MatrixLayoutAttr:$layout,
-    SPV_ScopeAttr:$scope,
-    OptionalAttr<SPV_MemoryAccessAttr>:$memory_access,
+    SPIRV_AnyPtr:$pointer,
+    SPIRV_Integer:$stride,
+    SPIRV_MatrixLayoutAttr:$layout,
+    SPIRV_ScopeAttr:$scope,
+    OptionalAttr<SPIRV_MemoryAccessAttr>:$memory_access,
     OptionalAttr<I32Attr>:$alignment
   );
 
   let results = (outs
-    SPV_AnyJointMatrix:$result
+    SPIRV_AnyJointMatrix:$result
   );
 }
 
 // -----
 
-def SPV_INTELJointMatrixMadOp : SPV_IntelVendorOp<"JointMatrixMad",
+def SPIRV_INTELJointMatrixMadOp : SPIRV_IntelVendorOp<"JointMatrixMad",
   [NoSideEffect, AllTypesMatch<["c", "result"]>]> {
-  let summary = "See extension SPV_INTEL_joint_matrix";
+  let summary = "See extension SPIRV_INTEL_joint_matrix";
 
   let description = [{
     Multiply matrix A by matrix B and add matrix C to the result
     of the multiplication: A*B+C. Here A is a M x K matrix, B is
     a K x N matrix and C is a M x N matrix.
 
     Behavior is undefined if sizes of operands do not meet the
     conditions above. All operands and the Result Type must be
def SPIRV_INTELJointMatrixMadOp : SPIRV_IntelVendorOp<"JointMatrixMad",
 
   }];
 
   let assemblyFormat = [{
     $scope operands attr-dict`:` type($a) `,` type($b) `->` type($c)
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
-    Extension<[SPV_INTEL_joint_matrix]>,
-    Capability<[SPV_C_JointMatrixINTEL]>
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[SPIRV_INTEL_joint_matrix]>,
+    Capability<[SPIRV_C_JointMatrixINTEL]>
   ];
 
   let arguments = (ins
-    SPV_AnyJointMatrix:$a,
-    SPV_AnyJointMatrix:$b,
-    SPV_AnyJointMatrix:$c,
-    SPV_ScopeAttr:$scope
+    SPIRV_AnyJointMatrix:$a,
+    SPIRV_AnyJointMatrix:$b,
+    SPIRV_AnyJointMatrix:$c,
+    SPIRV_ScopeAttr:$scope
   );
 
   let results = (outs
-    SPV_AnyJointMatrix:$result
+    SPIRV_AnyJointMatrix:$result
   );
 }
 
 // -----
 
-def SPV_INTELJointMatrixStoreOp : SPV_IntelVendorOp<"JointMatrixStore", []> {
-  let summary = "See extension SPV_INTEL_joint_matrix";
+def SPIRV_INTELJointMatrixStoreOp : SPIRV_IntelVendorOp<"JointMatrixStore", []> {
+  let summary = "See extension SPIRV_INTEL_joint_matrix";
 
   let description = [{
     Store a matrix through a pointer.
 
     Pointer is the pointer to store through. It specifies
     start of memory region where elements of the matrix must
     be stored and arranged according to Layout.
 
def SPIRV_INTELJointMatrixStoreOp : SPIRV_IntelVendorOp<"JointMatrixStore", []> {
 
   }];
 
    let assemblyFormat = [{
     $scope $layout operands attr-dict `:` `(` type(operands) `)`
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
-    Extension<[SPV_INTEL_joint_matrix]>,
-    Capability<[SPV_C_JointMatrixINTEL]>
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[SPIRV_INTEL_joint_matrix]>,
+    Capability<[SPIRV_C_JointMatrixINTEL]>
   ];
 
   let arguments = (ins
-    SPV_AnyPtr:$pointer,
-    SPV_AnyJointMatrix:$object,
-    SPV_Integer:$stride,
-    SPV_MatrixLayoutAttr:$layout,
-    SPV_ScopeAttr:$scope,
-    OptionalAttr<SPV_MemoryAccessAttr>:$memory_access,
+    SPIRV_AnyPtr:$pointer,
+    SPIRV_AnyJointMatrix:$object,
+    SPIRV_Integer:$stride,
+    SPIRV_MatrixLayoutAttr:$layout,
+    SPIRV_ScopeAttr:$scope,
+    OptionalAttr<SPIRV_MemoryAccessAttr>:$memory_access,
     OptionalAttr<I32Attr>:$alignment
   );
 
   let results = (outs);
 }
 
 // -----
 
 #endif // MLIR_DIALECT_SPIRV_IR_JOINT_MATRIX_OPS

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVLogicalOps.td

 //===----------------------------------------------------------------------===//
 
 #ifndef MLIR_DIALECT_SPIRV_IR_LOGICAL_OPS
 #define MLIR_DIALECT_SPIRV_IR_LOGICAL_OPS
 
 include "mlir/Dialect/SPIRV/IR/SPIRVBase.td"
 include "mlir/Interfaces/SideEffectInterfaces.td"
 
-class SPV_LogicalBinaryOp<string mnemonic, Type operandsType,
+class SPIRV_LogicalBinaryOp<string mnemonic, Type operandsType,
                             list<Trait> traits = []> :
-      // Result type is SPV_Bool.
-      SPV_BinaryOp<mnemonic, SPV_Bool, operandsType,
+      // Result type is SPIRV_Bool.
+      SPIRV_BinaryOp<mnemonic, SPIRV_Bool, operandsType,
                    !listconcat(traits, [
                      NoSideEffect, SameTypeOperands,
                      SameOperandsAndResultShape,
                      TypesMatchWith<"type of result to correspond to the `i1` "
                                     "equivalent of the operand",
                                     "operand1", "result",
                                     "getUnaryOpResultType($_self)"
                      >])> {
   let assemblyFormat = "$operand1 `,` $operand2 `:` type($operand1) attr-dict";
 
   let builders = [
     OpBuilder<(ins "Value":$lhs, "Value":$rhs),
     [{::buildLogicalBinaryOp($_builder, $_state, lhs, rhs);}]>
   ];
 }
 
-class SPV_LogicalUnaryOp<string mnemonic, Type operandType,
+class SPIRV_LogicalUnaryOp<string mnemonic, Type operandType,
                          list<Trait> traits = []> :
-      // Result type is SPV_Bool.
-      SPV_UnaryOp<mnemonic, SPV_Bool, operandType,
+      // Result type is SPIRV_Bool.
+      SPIRV_UnaryOp<mnemonic, SPIRV_Bool, operandType,
                   !listconcat(traits, [
                      NoSideEffect, SameTypeOperands, SameOperandsAndResultShape,
                      TypesMatchWith<"type of result to correspond to the `i1` "
                                     "equivalent of the operand",
                                     "operand", "result",
                                     "getUnaryOpResultType($_self)"
                      >])> {
   let assemblyFormat = "$operand `:` type($operand) attr-dict";
 
   let builders = [
     OpBuilder<(ins "Value":$value),
     [{::buildLogicalUnaryOp($_builder, $_state, value);}]>
   ];
 }
 
 // -----
 
-def SPV_FOrdEqualOp : SPV_LogicalBinaryOp<"FOrdEqual", SPV_Float, [Commutative]> {
+def SPIRV_FOrdEqualOp : SPIRV_LogicalBinaryOp<"FOrdEqual", SPIRV_Float, [Commutative]> {
   let summary = "Floating-point comparison for being ordered and equal.";
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
      The type of Operand 1 and Operand 2  must be a scalar or vector of
     floating-point type.  They must have the same type, and they must have
     the same number of components as Result Type.
let description = [{
     %4 = spirv.FOrdEqual %0, %1 : f32
     %5 = spirv.FOrdEqual %2, %3 : vector<4xf32>
     ```
   }];
 }
 
 // -----
 
-def SPV_FOrdGreaterThanOp : SPV_LogicalBinaryOp<"FOrdGreaterThan", SPV_Float, []> {
+def SPIRV_FOrdGreaterThanOp : SPIRV_LogicalBinaryOp<"FOrdGreaterThan", SPIRV_Float, []> {
   let summary = [{
     Floating-point comparison if operands are ordered and Operand 1 is
     greater than  Operand 2.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
let description = [{
     %4 = spirv.FOrdGreaterThan %0, %1 : f32
     %5 = spirv.FOrdGreaterThan %2, %3 : vector<4xf32>
     ```
   }];
 }
 
 // -----
 
-def SPV_FOrdGreaterThanEqualOp : SPV_LogicalBinaryOp<"FOrdGreaterThanEqual", SPV_Float, []> {
+def SPIRV_FOrdGreaterThanEqualOp : SPIRV_LogicalBinaryOp<"FOrdGreaterThanEqual", SPIRV_Float, []> {
   let summary = [{
     Floating-point comparison if operands are ordered and Operand 1 is
     greater than or equal to Operand 2.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
let description = [{
     %4 = spirv.FOrdGreaterThanEqual %0, %1 : f32
     %5 = spirv.FOrdGreaterThanEqual %2, %3 : vector<4xf32>
     ```
   }];
 }
 
 // -----
 
-def SPV_FOrdLessThanOp : SPV_LogicalBinaryOp<"FOrdLessThan", SPV_Float, []> {
+def SPIRV_FOrdLessThanOp : SPIRV_LogicalBinaryOp<"FOrdLessThan", SPIRV_Float, []> {
   let summary = [{
     Floating-point comparison if operands are ordered and Operand 1 is less
     than Operand 2.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
let description = [{
     %4 = spirv.FOrdLessThan %0, %1 : f32
     %5 = spirv.FOrdLessThan %2, %3 : vector<4xf32>
     ```
   }];
 }
 
 // -----
 
-def SPV_FOrdLessThanEqualOp : SPV_LogicalBinaryOp<"FOrdLessThanEqual", SPV_Float, []> {
+def SPIRV_FOrdLessThanEqualOp : SPIRV_LogicalBinaryOp<"FOrdLessThanEqual", SPIRV_Float, []> {
   let summary = [{
     Floating-point comparison if operands are ordered and Operand 1 is less
     than or equal to Operand 2.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
let description = [{
     %4 = spirv.FOrdLessThanEqual %0, %1 : f32
     %5 = spirv.FOrdLessThanEqual %2, %3 : vector<4xf32>
     ```
   }];
 }
 
 // -----
 
-def SPV_FOrdNotEqualOp : SPV_LogicalBinaryOp<"FOrdNotEqual", SPV_Float, [Commutative]> {
+def SPIRV_FOrdNotEqualOp : SPIRV_LogicalBinaryOp<"FOrdNotEqual", SPIRV_Float, [Commutative]> {
   let summary = "Floating-point comparison for being ordered and not equal.";
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
      The type of Operand 1 and Operand 2  must be a scalar or vector of
     floating-point type.  They must have the same type, and they must have
     the same number of components as Result Type.
let description = [{
     %4 = spirv.FOrdNotEqual %0, %1 : f32
     %5 = spirv.FOrdNotEqual %2, %3 : vector<4xf32>
     ```
   }];
 }
 
 // -----
 
-def SPV_FUnordEqualOp : SPV_LogicalBinaryOp<"FUnordEqual", SPV_Float, [Commutative]> {
+def SPIRV_FUnordEqualOp : SPIRV_LogicalBinaryOp<"FUnordEqual", SPIRV_Float, [Commutative]> {
   let summary = "Floating-point comparison for being unordered or equal.";
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
      The type of Operand 1 and Operand 2  must be a scalar or vector of
     floating-point type.  They must have the same type, and they must have
     the same number of components as Result Type.
let description = [{
     %4 = spirv.FUnordEqual %0, %1 : f32
     %5 = spirv.FUnordEqual %2, %3 : vector<4xf32>
     ```
   }];
 }
 
 // -----
 
-def SPV_FUnordGreaterThanOp : SPV_LogicalBinaryOp<"FUnordGreaterThan", SPV_Float, []> {
+def SPIRV_FUnordGreaterThanOp : SPIRV_LogicalBinaryOp<"FUnordGreaterThan", SPIRV_Float, []> {
   let summary = [{
     Floating-point comparison if operands are unordered or Operand 1 is
     greater than  Operand 2.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
let description = [{
     %4 = spirv.FUnordGreaterThan %0, %1 : f32
     %5 = spirv.FUnordGreaterThan %2, %3 : vector<4xf32>
     ```
   }];
 }
 
 // -----
 
-def SPV_FUnordGreaterThanEqualOp : SPV_LogicalBinaryOp<"FUnordGreaterThanEqual", SPV_Float, []> {
+def SPIRV_FUnordGreaterThanEqualOp : SPIRV_LogicalBinaryOp<"FUnordGreaterThanEqual", SPIRV_Float, []> {
   let summary = [{
     Floating-point comparison if operands are unordered or Operand 1 is
     greater than or equal to Operand 2.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
let description = [{
     %4 = spirv.FUnordGreaterThanEqual %0, %1 : f32
     %5 = spirv.FUnordGreaterThanEqual %2, %3 : vector<4xf32>
     ```
   }];
 }
 
 // -----
 
-def SPV_FUnordLessThanOp : SPV_LogicalBinaryOp<"FUnordLessThan", SPV_Float, []> {
+def SPIRV_FUnordLessThanOp : SPIRV_LogicalBinaryOp<"FUnordLessThan", SPIRV_Float, []> {
   let summary = [{
     Floating-point comparison if operands are unordered or Operand 1 is less
     than Operand 2.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
let description = [{
     %4 = spirv.FUnordLessThan %0, %1 : f32
     %5 = spirv.FUnordLessThan %2, %3 : vector<4xf32>
     ```
   }];
 }
 
 // -----
 
-def SPV_FUnordLessThanEqualOp : SPV_LogicalBinaryOp<"FUnordLessThanEqual", SPV_Float, []> {
+def SPIRV_FUnordLessThanEqualOp : SPIRV_LogicalBinaryOp<"FUnordLessThanEqual", SPIRV_Float, []> {
   let summary = [{
     Floating-point comparison if operands are unordered or Operand 1 is less
     than or equal to Operand 2.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
let description = [{
     %4 = spirv.FUnordLessThanEqual %0, %1 : f32
     %5 = spirv.FUnordLessThanEqual %2, %3 : vector<4xf32>
     ```
   }];
 }
 
 // -----
 
-def SPV_FUnordNotEqualOp : SPV_LogicalBinaryOp<"FUnordNotEqual", SPV_Float, [Commutative]> {
+def SPIRV_FUnordNotEqualOp : SPIRV_LogicalBinaryOp<"FUnordNotEqual", SPIRV_Float, [Commutative]> {
   let summary = "Floating-point comparison for being unordered or not equal.";
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
      The type of Operand 1 and Operand 2  must be a scalar or vector of
     floating-point type.  They must have the same type, and they must have
     the same number of components as Result Type.
let description = [{
     %4 = spirv.FUnordNotEqual %0, %1 : f32
     %5 = spirv.FUnordNotEqual %2, %3 : vector<4xf32>
     ```
   }];
 }
 
 // -----
 
-def SPV_IEqualOp : SPV_LogicalBinaryOp<"IEqual",
-                                       SPV_Integer,
+def SPIRV_IEqualOp : SPIRV_LogicalBinaryOp<"IEqual",
+                                       SPIRV_Integer,
                                        [Commutative, UsableInSpecConstantOp]> {
   let summary = "Integer comparison for equality.";
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
      The type of Operand 1 and Operand 2  must be a scalar or vector of
     integer type.  They must have the same component width, and they must
let description = [{
     %5 = spirv.IEqual %2, %3 : vector<4xi32>
 
     ```
   }];
 }
 
 // -----
 
-def SPV_INotEqualOp : SPV_LogicalBinaryOp<"INotEqual",
-                                          SPV_Integer,
+def SPIRV_INotEqualOp : SPIRV_LogicalBinaryOp<"INotEqual",
+                                          SPIRV_Integer,
                                           [Commutative, UsableInSpecConstantOp]> {
   let summary = "Integer comparison for inequality.";
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
      The type of Operand 1 and Operand 2  must be a scalar or vector of
     integer type.  They must have the same component width, and they must
let description = [{
     %5 = spirv.INotEqual %2, %3 : vector<4xi32>
 
     ```
   }];
 }
 
 // -----
 
-def SPV_IsInfOp : SPV_LogicalUnaryOp<"IsInf", SPV_Float, []> {
+def SPIRV_IsInfOp : SPIRV_LogicalUnaryOp<"IsInf", SPIRV_Float, []> {
   let summary = "Result is true if x is an IEEE Inf, otherwise result is false";
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
     x must be a scalar or vector of floating-point type.  It must have the
     same number of components as Result Type.
 
let description = [{
     %2 = spirv.IsInf %0: f32
     %3 = spirv.IsInf %1: vector<4xi32>
     ```
   }];
 }
 
 // -----
 
-def SPV_IsNanOp : SPV_LogicalUnaryOp<"IsNan", SPV_Float, []> {
+def SPIRV_IsNanOp : SPIRV_LogicalUnaryOp<"IsNan", SPIRV_Float, []> {
   let summary = [{
     Result is true if x is an IEEE NaN, otherwise result is false.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
     x must be a scalar or vector of floating-point type.  It must have the
let description = [{
     %2 = spirv.IsNan %0: f32
     %3 = spirv.IsNan %1: vector<4xi32>
     ```
   }];
 }
 
 // -----
 
-def SPV_LogicalAndOp : SPV_LogicalBinaryOp<"LogicalAnd",
-                                           SPV_Bool,
+def SPIRV_LogicalAndOp : SPIRV_LogicalBinaryOp<"LogicalAnd",
+                                           SPIRV_Bool,
                                            [Commutative,
                                             UsableInSpecConstantOp]> {
   let summary = [{
     Result is true if both Operand 1 and Operand 2 are true. Result is false
     if either Operand 1 or Operand 2 are false.
   }];
 
   let description = [{
let description = [{
     ```
   }];
 
   let hasFolder = 1;
 }
 
 // -----
 
-def SPV_LogicalEqualOp : SPV_LogicalBinaryOp<"LogicalEqual",
-                                             SPV_Bool,
+def SPIRV_LogicalEqualOp : SPIRV_LogicalBinaryOp<"LogicalEqual",
+                                             SPIRV_Bool,
                                              [Commutative,
                                               UsableInSpecConstantOp]> {
   let summary = [{
     Result is true if Operand 1 and Operand 2 have the same value. Result is
     false if Operand 1 and Operand 2 have different values.
   }];
 
   let description = [{
let description = [{
     %2 = spirv.LogicalEqual %0, %1 : i1
     %2 = spirv.LogicalEqual %0, %1 : vector<4xi1>
     ```
   }];
 }
 
 // -----
 
-def SPV_LogicalNotOp : SPV_LogicalUnaryOp<"LogicalNot",
-                                          SPV_Bool,
+def SPIRV_LogicalNotOp : SPIRV_LogicalUnaryOp<"LogicalNot",
+                                          SPIRV_Bool,
                                           [UsableInSpecConstantOp]> {
   let summary = [{
     Result is true if Operand is false.  Result is false if Operand is true.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
let description = [{
     ```
   }];
 
   let hasCanonicalizer = 1;
 }
 
 // -----
 
-def SPV_LogicalNotEqualOp : SPV_LogicalBinaryOp<"LogicalNotEqual",
-                                                SPV_Bool,
+def SPIRV_LogicalNotEqualOp : SPIRV_LogicalBinaryOp<"LogicalNotEqual",
+                                                SPIRV_Bool,
                                                 [Commutative,
                                                  UsableInSpecConstantOp]> {
   let summary = [{
     Result is true if Operand 1 and Operand 2 have different values. Result
     is false if Operand 1 and Operand 2 have the same value.
   }];
 
   let description = [{
let description = [{
     %2 = spirv.LogicalNotEqual %0, %1 : i1
     %2 = spirv.LogicalNotEqual %0, %1 : vector<4xi1>
     ```
   }];
 }
 
 // -----
 
-def SPV_LogicalOrOp : SPV_LogicalBinaryOp<"LogicalOr",
-                                          SPV_Bool,
+def SPIRV_LogicalOrOp : SPIRV_LogicalBinaryOp<"LogicalOr",
+                                          SPIRV_Bool,
                                           [Commutative,
                                            UsableInSpecConstantOp]> {
   let summary = [{
     Result is true if either Operand 1 or Operand 2 is true. Result is false
     if both Operand 1 and Operand 2 are false.
   }];
 
   let description = [{
let description = [{
     ```
   }];
 
   let hasFolder = 1;
 }
 
 // -----
 
-def SPV_OrderedOp : SPV_LogicalBinaryOp<"Ordered", SPV_Float, [Commutative]> {
+def SPIRV_OrderedOp : SPIRV_LogicalBinaryOp<"Ordered", SPIRV_Float, [Commutative]> {
   let summary = [{
     Result is true if both x == x and y == y are true, where IEEE comparison
     is used, otherwise result is false.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
let description = [{
 
     ```
     %4 = spirv.Ordered %0, %1 : f32
     %5 = spirv.Ordered %2, %3 : vector<4xf32>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
 
 // -----
 
-def SPV_SGreaterThanOp : SPV_LogicalBinaryOp<"SGreaterThan",
-                                             SPV_Integer,
+def SPIRV_SGreaterThanOp : SPIRV_LogicalBinaryOp<"SGreaterThan",
+                                             SPIRV_Integer,
                                              [UsableInSpecConstantOp, SignedOp]> {
   let summary = [{
     Signed-integer comparison if Operand 1 is greater than  Operand 2.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
let description = [{
     %5 = spirv.SGreaterThan %2, %3 : vector<4xi32>
 
     ```
   }];
 }
 
 // -----
 
-def SPV_SGreaterThanEqualOp : SPV_LogicalBinaryOp<"SGreaterThanEqual",
-                                                  SPV_Integer,
+def SPIRV_SGreaterThanEqualOp : SPIRV_LogicalBinaryOp<"SGreaterThanEqual",
+                                                  SPIRV_Integer,
                                                   [UsableInSpecConstantOp,
                                                    SignedOp]> {
   let summary = [{
     Signed-integer comparison if Operand 1 is greater than or equal to
     Operand 2.
   }];
 
   let description = [{
let description = [{
     %5 = spirv.SGreaterThanEqual %2, %3 : vector<4xi32>
 
     ```
   }];
 }
 
 // -----
 
-def SPV_SLessThanOp : SPV_LogicalBinaryOp<"SLessThan",
-                                          SPV_Integer,
+def SPIRV_SLessThanOp : SPIRV_LogicalBinaryOp<"SLessThan",
+                                          SPIRV_Integer,
                                           [UsableInSpecConstantOp, SignedOp]> {
   let summary = [{
     Signed-integer comparison if Operand 1 is less than Operand 2.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
let description = [{
     %5 = spirv.SLessThan %2, %3 : vector<4xi32>
 
     ```
   }];
 }
 
 // -----
 
-def SPV_SLessThanEqualOp : SPV_LogicalBinaryOp<"SLessThanEqual",
-                                               SPV_Integer,
+def SPIRV_SLessThanEqualOp : SPIRV_LogicalBinaryOp<"SLessThanEqual",
+                                               SPIRV_Integer,
                                                [UsableInSpecConstantOp,
                                                 SignedOp]> {
   let summary = [{
     Signed-integer comparison if Operand 1 is less than or equal to Operand
     2.
   }];
 
   let description = [{
let description = [{
     %5 = spirv.SLessThanEqual %2, %3 : vector<4xi32>
 
     ```
   }];
 }
 
 // -----
 
-def SPV_SelectOp : SPV_Op<"Select",
+def SPIRV_SelectOp : SPIRV_Op<"Select",
     [NoSideEffect,
      AllTypesMatch<["true_value", "false_value", "result"]>,
      UsableInSpecConstantOp]> {
   let summary = [{
     Select between two objects. Before version 1.4, results are only
     computed per component.
   }];
 
let description = [{
     ```mlir
     %3 = spirv.Select %0, %1, %2 : i1, f32
     %3 = spirv.Select %0, %1, %2 : i1, vector<3xi32>
     %3 = spirv.Select %0, %1, %2 : vector<3xi1>, vector<3xf32>
     ```
   }];
 
   let arguments = (ins
-    SPV_ScalarOrVectorOf<SPV_Bool>:$condition,
-    SPV_SelectType:$true_value,
-    SPV_SelectType:$false_value
+    SPIRV_ScalarOrVectorOf<SPIRV_Bool>:$condition,
+    SPIRV_SelectType:$true_value,
+    SPIRV_SelectType:$false_value
   );
 
   let results = (outs
-    SPV_SelectType:$result
+    SPIRV_SelectType:$result
   );
 
   let assemblyFormat = [{
     operands attr-dict `:` type($condition) `,` type($result)
   }];
 }
 
 // -----
 
-def SPV_UGreaterThanOp : SPV_LogicalBinaryOp<"UGreaterThan",
-                                             SPV_Integer,
+def SPIRV_UGreaterThanOp : SPIRV_LogicalBinaryOp<"UGreaterThan",
+                                             SPIRV_Integer,
                                              [UnsignedOp,
                                               UsableInSpecConstantOp]> {
   let summary = [{
     Unsigned-integer comparison if Operand 1 is greater than  Operand 2.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
let description = [{
     %5 = spirv.UGreaterThan %2, %3 : vector<4xi32>
 
     ```
   }];
 }
 
 // -----
 
-def SPV_UGreaterThanEqualOp : SPV_LogicalBinaryOp<"UGreaterThanEqual",
-                                                  SPV_Integer,
+def SPIRV_UGreaterThanEqualOp : SPIRV_LogicalBinaryOp<"UGreaterThanEqual",
+                                                  SPIRV_Integer,
                                                   [UnsignedOp,
                                                    UsableInSpecConstantOp]> {
   let summary = [{
     Unsigned-integer comparison if Operand 1 is greater than or equal to
     Operand 2.
   }];
 
   let description = [{
let description = [{
     %5 = spirv.UGreaterThanEqual %2, %3 : vector<4xi32>
 
     ```
   }];
 }
 
 // -----
 
-def SPV_ULessThanOp : SPV_LogicalBinaryOp<"ULessThan",
-                                          SPV_Integer,
+def SPIRV_ULessThanOp : SPIRV_LogicalBinaryOp<"ULessThan",
+                                          SPIRV_Integer,
                                           [UnsignedOp, UsableInSpecConstantOp]> {
   let summary = [{
     Unsigned-integer comparison if Operand 1 is less than Operand 2.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
let description = [{
     %5 = spirv.ULessThan %2, %3 : vector<4xi32>
 
     ```
   }];
 }
 
 // -----
 
-def SPV_UnorderedOp : SPV_LogicalBinaryOp<"Unordered", SPV_Float, [Commutative]> {
+def SPIRV_UnorderedOp : SPIRV_LogicalBinaryOp<"Unordered", SPIRV_Float, [Commutative]> {
   let summary = [{
     Result is true if either x or y is an IEEE NaN, otherwise result is
     false.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of Boolean type.
 
let description = [{
 
     ```
     %4 = spirv.Unordered %0, %1 : f32
     %5 = spirv.Unordered %2, %3 : vector<4xf32>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_Kernel]>
+    Capability<[SPIRV_C_Kernel]>
   ];
 }
 
 // -----
 
-def SPV_ULessThanEqualOp : SPV_LogicalBinaryOp<"ULessThanEqual",
-                                               SPV_Integer,
+def SPIRV_ULessThanEqualOp : SPIRV_LogicalBinaryOp<"ULessThanEqual",
+                                               SPIRV_Integer,
                                                [UnsignedOp,
                                                 UsableInSpecConstantOp]> {
   let summary = [{
     Unsigned-integer comparison if Operand 1 is less than or equal to
     Operand 2.
   }];
 
   let description = [{

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMatrixOps.td

 //===----------------------------------------------------------------------===//
 
 #ifndef MLIR_DIALECT_SPIRV_IR_MATRIX_OPS
 #define MLIR_DIALECT_SPIRV_IR_MATRIX_OPS
 include "mlir/Interfaces/SideEffectInterfaces.td"
 
 // -----
 
-def SPV_MatrixTimesMatrixOp : SPV_Op<"MatrixTimesMatrix", [NoSideEffect]> {
+def SPIRV_MatrixTimesMatrixOp : SPIRV_Op<"MatrixTimesMatrix", [NoSideEffect]> {
   let summary = "Linear-algebraic multiply of LeftMatrix X RightMatrix.";
 
   let description = [{
     Result Type must be an OpTypeMatrix whose Column Type is a vector of
     floating-point type.
 
     LeftMatrix must be a matrix whose Column Type is the same as the Column
     Type in Result Type.
let description = [{
     ```
     %0 = spirv.MatrixTimesMatrix %matrix_1, %matrix_2 :
         !spirv.matrix<4 x vector<3xf32>>, !spirv.matrix<3 x vector<4xf32>> ->
         !spirv.matrix<4 x vector<4xf32>>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_Matrix]>
+    Capability<[SPIRV_C_Matrix]>
   ];
 
   let arguments = (ins
-    SPV_AnyMatrix:$leftmatrix,
-    SPV_AnyMatrix:$rightmatrix
+    SPIRV_AnyMatrix:$leftmatrix,
+    SPIRV_AnyMatrix:$rightmatrix
   );
 
   let results = (outs
-    SPV_AnyMatrix:$result
+    SPIRV_AnyMatrix:$result
   );
 
   let assemblyFormat = [{
     operands attr-dict `:` type($leftmatrix) `,` type($rightmatrix) `->` type($result)
   }];
 }
 
 // -----
 
-def SPV_MatrixTimesScalarOp : SPV_Op<"MatrixTimesScalar", [NoSideEffect]> {
+def SPIRV_MatrixTimesScalarOp : SPIRV_Op<"MatrixTimesScalar", [NoSideEffect]> {
   let summary = "Scale a floating-point matrix.";
 
   let description = [{
     Result Type must be an OpTypeMatrix whose Column Type is a vector of
     floating-point type.
 
      The type of Matrix must be the same as Result Type. Each component in
     each column in Matrix is multiplied by Scalar.
let description = [{
 
     %0 = spirv.MatrixTimesScalar %matrix, %scalar :
     !spirv.matrix<3 x vector<3xf32>>, f32 -> !spirv.matrix<3 x vector<3xf32>>
 
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_Matrix]>
+    Capability<[SPIRV_C_Matrix]>
   ];
 
   let arguments = (ins
-    SPV_AnyMatrix:$matrix,
-    SPV_Float:$scalar
+    SPIRV_AnyMatrix:$matrix,
+    SPIRV_Float:$scalar
   );
 
   let results = (outs
-    SPV_AnyMatrix:$result
+    SPIRV_AnyMatrix:$result
   );
 
   // TODO: we need just one matrix type given that the input and result are the
   // same and the scalar's type can be deduced from it.
   let assemblyFormat = [{
     operands attr-dict `:` type($matrix) `,` type($scalar) `->` type($result)
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_Matrix]>
+    Capability<[SPIRV_C_Matrix]>
   ];
 }
 
 // -----
 
-def SPV_TransposeOp : SPV_Op<"Transpose", [NoSideEffect]> {
+def SPIRV_TransposeOp : SPIRV_Op<"Transpose", [NoSideEffect]> {
   let summary = "Transpose a matrix.";
 
   let description = [{
     Result Type must be an OpTypeMatrix.
 
     Matrix must be an object of type OpTypeMatrix. The number of columns and
     the column size of Matrix must be the reverse of those in Result Type.
     The types of the scalar components in Matrix and Result Type must be the
let description = [{
     ```
     %0 = spirv.Transpose %matrix: !spirv.matrix<2 x vector<3xf32>> ->
     !spirv.matrix<3 x vector<2xf32>>
 
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_Matrix]>
+    Capability<[SPIRV_C_Matrix]>
   ];
 
   let arguments = (ins
-    SPV_AnyMatrix:$matrix
+    SPIRV_AnyMatrix:$matrix
   );
 
   let results = (outs
-    SPV_AnyMatrix:$result
+    SPIRV_AnyMatrix:$result
   );
 
   let assemblyFormat = [{
     operands attr-dict `:` type($matrix) `->` type($result)
   }];
 }
 
 // -----
 
 #endif // MLIR_DIALECT_SPIRV_IR_MATRIX_OPS

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td

 
 #ifndef MLIR_DIALECT_SPIRV_IR_MEMORY_OPS
 #define MLIR_DIALECT_SPIRV_IR_MEMORY_OPS
 
 include "mlir/Dialect/SPIRV/IR/SPIRVBase.td"
 
 // -----
 
-def SPV_AccessChainOp : SPV_Op<"AccessChain", [NoSideEffect]> {
+def SPIRV_AccessChainOp : SPIRV_Op<"AccessChain", [NoSideEffect]> {
   let summary = "Create a pointer into a composite object.";
 
   let description = [{
     Result Type must be an OpTypePointer. Its Type operand must be the type
     reached by walking the Base’s type hierarchy down to the last provided
     index in Indexes, and its Storage Class operand must be the same as the
     Storage Class of Base.
 
let description = [{
     %0 = "spirv.Constant"() { value = 1: i32} : () -> i32
     %1 = spirv.Variable : !spirv.ptr<!spirv.struct<f32, !spirv.array<4xf32>>, Function>
     %2 = spirv.AccessChain %1[%0] : !spirv.ptr<!spirv.struct<f32, !spirv.array<4xf32>>, Function>
     %3 = spirv.Load "Function" %2 ["Volatile"] : !spirv.array<4xf32>
     ```
   }];
 
   let arguments = (ins
-    SPV_AnyPtr:$base_ptr,
-    Variadic<SPV_Integer>:$indices
+    SPIRV_AnyPtr:$base_ptr,
+    Variadic<SPIRV_Integer>:$indices
   );
 
   let results = (outs
-    SPV_AnyPtr:$component_ptr
+    SPIRV_AnyPtr:$component_ptr
   );
 
   let builders = [OpBuilder<(ins "Value":$basePtr, "ValueRange":$indices)>];
 
   let hasCanonicalizer = 1;
 }
 
 // -----
 
-def SPV_CopyMemoryOp : SPV_Op<"CopyMemory", []> {
+def SPIRV_CopyMemoryOp : SPIRV_Op<"CopyMemory", []> {
   let summary = [{
     Copy from the memory pointed to by Source to the memory pointed to by
     Target. Both operands must be non-void pointers and having the same <id>
     Type operand in their OpTypePointer type declaration.  Matching Storage
     Class is not required.  The amount of memory copied is the size of the
     type pointed to. The copied type must have a fixed size; i.e., it must
     not be, nor include, any OpTypeRuntimeArray types.
   }];
let description = [{
     ```mlir
     %0 = spirv.Variable : !spirv.ptr<f32, Function>
     %1 = spirv.Variable : !spirv.ptr<f32, Function>
     spirv.CopyMemory "Function" %0, "Function" %1 : f32
     ```
   }];
 
   let arguments = (ins
-    SPV_AnyPtr:$target,
-    SPV_AnyPtr:$source,
-    OptionalAttr<SPV_MemoryAccessAttr>:$memory_access,
+    SPIRV_AnyPtr:$target,
+    SPIRV_AnyPtr:$source,
+    OptionalAttr<SPIRV_MemoryAccessAttr>:$memory_access,
     OptionalAttr<I32Attr>:$alignment,
-    OptionalAttr<SPV_MemoryAccessAttr>:$source_memory_access,
+    OptionalAttr<SPIRV_MemoryAccessAttr>:$source_memory_access,
     OptionalAttr<I32Attr>:$source_alignment
   );
 
   let results = (outs);
 
   let autogenSerialization = 0;
 }
 
 // -----
 
-def SPV_InBoundsPtrAccessChainOp : SPV_Op<"InBoundsPtrAccessChain", [NoSideEffect]> {
+def SPIRV_InBoundsPtrAccessChainOp : SPIRV_Op<"InBoundsPtrAccessChain", [NoSideEffect]> {
   let summary = [{
     Has the same semantics as OpPtrAccessChain, with the addition that the
     resulting pointer is known to point within the base object.
   }];
 
   let description = [{
 
 
let description = [{
     func @inbounds_ptr_access_chain(%arg0: !spirv.ptr<f32, CrossWorkgroup>, %arg1 : i64) -> () {
       %0 = spirv.InBoundsPtrAccessChain %arg0[%arg1] : !spirv.ptr<f32, CrossWorkgroup>, i64
       ...
     }
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_Addresses]>
+    Capability<[SPIRV_C_Addresses]>
   ];
 
   let arguments = (ins
-    SPV_AnyPtr:$base_ptr,
-    SPV_Integer:$element,
-    Variadic<SPV_Integer>:$indices
+    SPIRV_AnyPtr:$base_ptr,
+    SPIRV_Integer:$element,
+    Variadic<SPIRV_Integer>:$indices
   );
 
   let results = (outs
-    SPV_AnyPtr:$result
+    SPIRV_AnyPtr:$result
   );
 
   let builders = [OpBuilder<(ins "Value":$basePtr, "Value":$element, "ValueRange":$indices)>];
 }
 
 // -----
 
-def SPV_LoadOp : SPV_Op<"Load", []> {
+def SPIRV_LoadOp : SPIRV_Op<"Load", []> {
   let summary = "Load through a pointer.";
 
   let description = [{
     Result Type is the type of the loaded object. It must be a type with
     fixed size; i.e., it cannot be, nor include, any OpTypeRuntimeArray
     types.
 
     Pointer is the pointer to load through.  Its type must be an
let description = [{
     %0 = spirv.Variable : !spirv.ptr<f32, Function>
     %1 = spirv.Load "Function" %0 : f32
     %2 = spirv.Load "Function" %0 ["Volatile"] : f32
     %3 = spirv.Load "Function" %0 ["Aligned", 4] : f32
     ```
   }];
 
   let arguments = (ins
-    SPV_AnyPtr:$ptr,
-    OptionalAttr<SPV_MemoryAccessAttr>:$memory_access,
+    SPIRV_AnyPtr:$ptr,
+    OptionalAttr<SPIRV_MemoryAccessAttr>:$memory_access,
     OptionalAttr<I32Attr>:$alignment
   );
 
   let results = (outs
-    SPV_Type:$value
+    SPIRV_Type:$value
   );
 
   let builders = [
     OpBuilder<(ins "Value":$basePtr,
       CArg<"MemoryAccessAttr", "{}">:$memory_access,
       CArg<"IntegerAttr", "{}">:$alignment)>
   ];
 }
 
 // -----
 
-def SPV_PtrAccessChainOp : SPV_Op<"PtrAccessChain", [NoSideEffect]> {
+def SPIRV_PtrAccessChainOp : SPIRV_Op<"PtrAccessChain", [NoSideEffect]> {
   let summary = [{
     Has the same semantics as OpAccessChain, with the addition of the
     Element operand.
   }];
 
   let description = [{
     Element is used to do an initial dereference of Base: Base is treated as
     the address of an element in an array, and a new element address is
let description = [{
     func @ptr_access_chain(%arg0: !spirv.ptr<f32, CrossWorkgroup>, %arg1 : i64) -> () {
       %0 = spirv.PtrAccessChain %arg0[%arg1] : !spirv.ptr<f32, CrossWorkgroup>, i64
       ...
     }
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_Addresses, SPV_C_PhysicalStorageBufferAddresses, SPV_C_VariablePointers, SPV_C_VariablePointersStorageBuffer]>
+    Capability<[SPIRV_C_Addresses, SPIRV_C_PhysicalStorageBufferAddresses, SPIRV_C_VariablePointers, SPIRV_C_VariablePointersStorageBuffer]>
   ];
 
   let arguments = (ins
-    SPV_AnyPtr:$base_ptr,
-    SPV_Integer:$element,
-    Variadic<SPV_Integer>:$indices
+    SPIRV_AnyPtr:$base_ptr,
+    SPIRV_Integer:$element,
+    Variadic<SPIRV_Integer>:$indices
   );
 
   let results = (outs
-    SPV_AnyPtr:$result
+    SPIRV_AnyPtr:$result
   );
 
   let builders = [OpBuilder<(ins "Value":$basePtr, "Value":$element, "ValueRange":$indices)>];
 }
 
 // -----
 
-def SPV_StoreOp : SPV_Op<"Store", []> {
+def SPIRV_StoreOp : SPIRV_Op<"Store", []> {
   let summary = "Store through a pointer.";
 
   let description = [{
     Pointer is the pointer to store through.  Its type must be an
     OpTypePointer whose Type operand is the same as the type of Object.
 
     Object is the object to store.
 
let description = [{
     %1 = spirv.FMul ... : f32
     spirv.Store "Function" %0, %1 : f32
     spirv.Store "Function" %0, %1 ["Volatile"] : f32
     spirv.Store "Function" %0, %1 ["Aligned", 4] : f32
     ```
   }];
 
   let arguments = (ins
-    SPV_AnyPtr:$ptr,
-    SPV_Type:$value,
-    OptionalAttr<SPV_MemoryAccessAttr>:$memory_access,
+    SPIRV_AnyPtr:$ptr,
+    SPIRV_Type:$value,
+    OptionalAttr<SPIRV_MemoryAccessAttr>:$memory_access,
     OptionalAttr<I32Attr>:$alignment
   );
 
   let results = (outs);
 
   let builders = [
     OpBuilder<(ins "Value":$ptr, "Value":$value,
       CArg<"ArrayRef<NamedAttribute>", "{}">:$namedAttrs),
     [{
       $_state.addOperands(ptr);
       $_state.addOperands(value);
       $_state.addAttributes(namedAttrs);
     }]>
   ];
 }
 
 // -----
 
-def SPV_VariableOp : SPV_Op<"Variable", []> {
+def SPIRV_VariableOp : SPIRV_Op<"Variable", []> {
   let summary = [{
     Allocate an object in memory, resulting in a pointer to it, which can be
     used with OpLoad and OpStore.
   }];
 
   let description = [{
     Result Type must be an OpTypePointer. Its Type operand is the type of
     object in memory.
let description = [{
     %0 = spirv.Constant ...
 
     %1 = spirv.Variable : !spirv.ptr<f32, Function>
     %2 = spirv.Variable init(%0): !spirv.ptr<f32, Function>
     ```
   }];
 
   let arguments = (ins
-    SPV_StorageClassAttr:$storage_class,
+    SPIRV_StorageClassAttr:$storage_class,
     Optional<AnyType>:$initializer
   );
 
   let results = (outs
-    SPV_AnyPtr:$pointer
+    SPIRV_AnyPtr:$pointer
   );
 }
 
 #endif // MLIR_DIALECT_SPIRV_IR_MEMORY_OPS

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td

 
 #ifndef MLIR_DIALECT_SPIRV_IR_MISC_OPS
 #define MLIR_DIALECT_SPIRV_IR_MISC_OPS
 
 include "mlir/Dialect/SPIRV/IR/SPIRVBase.td"
 
 // -----
 
-def SPV_KHRAssumeTrueOp : SPV_KhrVendorOp<"AssumeTrue", []> {
+def SPIRV_KHRAssumeTrueOp : SPIRV_KhrVendorOp<"AssumeTrue", []> {
   let summary = "TBD";
 
   let description = [{
 
 
     <!-- End of AutoGen section -->
 
     ```
     assumetruekhr-op ::= `spirv.KHR.AssumeTrue` ssa-use
     ```mlir
 
     #### Example:
 
     ```
     spirv.KHR.AssumeTrue %arg
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_0>,
-    MaxVersion<SPV_V_1_6>,
-    Extension<[SPV_KHR_expect_assume]>,
-    Capability<[SPV_C_ExpectAssumeKHR]>
+    MinVersion<SPIRV_V_1_0>,
+    MaxVersion<SPIRV_V_1_6>,
+    Extension<[SPIRV_KHR_expect_assume]>,
+    Capability<[SPIRV_C_ExpectAssumeKHR]>
   ];
 
   let arguments = (ins
-    SPV_Bool:$condition
+    SPIRV_Bool:$condition
   );
 
   let results = (outs);
 
   let hasVerifier = 0;
   let assemblyFormat = "$condition attr-dict";
 }
 
 // -----
 
-def SPV_UndefOp : SPV_Op<"Undef", [NoSideEffect]> {
+def SPIRV_UndefOp : SPIRV_Op<"Undef", [NoSideEffect]> {
   let summary = "Make an intermediate object whose value is undefined.";
 
   let description = [{
     Result Type is the type of object to make.
 
     Each consumption of Result <id> yields an arbitrary, possibly different
     bit pattern or abstract value resulting in possibly different concrete,
     abstract, or opaque values.
let description = [{
     %0 = spirv.Undef : f32
     %1 = spirv.Undef : !spirv.struct<!spirv.array<4 x vector<4xi32>>>
     ```
   }];
 
   let arguments = (ins);
 
   let results = (outs
-    SPV_Type:$result
+    SPIRV_Type:$result
   );
 
   let hasVerifier = 0;
 
   let hasOpcode = 0;
   let autogenSerialization = 0;
 
   let assemblyFormat = "attr-dict `:` type($result)";
 }
 
 // -----
 
 #endif // MLIR_DIALECT_SPIRV_IR_MISC_OPS

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td

 //===-- SPIRVNonUniformOps.td - MLIR SPIR-V NonUniform Ops -*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains non-uniform ops for the SPIR-V dialect. It corresponds to
 // "3.32.24. Non-Uniform Instructions" of the SPIR-V specification.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef MLIR_DIALECT_SPIRV_IR_NON_UNIFORM_OPS
 #define MLIR_DIALECT_SPIRV_IR_NON_UNIFORM_OPS
 
-class SPV_GroupNonUniformArithmeticOp<string mnemonic, Type type,
-      list<Trait> traits = []> : SPV_Op<mnemonic, traits> {
+class SPIRV_GroupNonUniformArithmeticOp<string mnemonic, Type type,
+      list<Trait> traits = []> : SPIRV_Op<mnemonic, traits> {
 
   let arguments = (ins
-    SPV_ScopeAttr:$execution_scope,
-    SPV_GroupOperationAttr:$group_operation,
-    SPV_ScalarOrVectorOf<type>:$value,
-    Optional<SPV_Integer>:$cluster_size
+    SPIRV_ScopeAttr:$execution_scope,
+    SPIRV_GroupOperationAttr:$group_operation,
+    SPIRV_ScalarOrVectorOf<type>:$value,
+    Optional<SPIRV_Integer>:$cluster_size
   );
 
   let results = (outs
-    SPV_ScalarOrVectorOf<type>:$result
+    SPIRV_ScalarOrVectorOf<type>:$result
   );
 }
 
 // -----
 
-def SPV_GroupNonUniformBallotOp : SPV_Op<"GroupNonUniformBallot", []> {
+def SPIRV_GroupNonUniformBallotOp : SPIRV_Op<"GroupNonUniformBallot", []> {
   let summary = [{
     Result is a bitfield value combining the Predicate value from all
     invocations in the group that execute the same dynamic instance of this
     instruction. The bit is set to one if the corresponding invocation is
     active and the Predicate for that invocation evaluated to true;
     otherwise, it is set to zero.
   }];
 
let description = [{
     #### Example:
 
     ```mlir
     %0 = spirv.GroupNonUniformBallot "SubGroup" %predicate : vector<4xi32>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_3>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_GroupNonUniformBallot]>
+    Capability<[SPIRV_C_GroupNonUniformBallot]>
   ];
 
   let arguments = (ins
-    SPV_ScopeAttr:$execution_scope,
-    SPV_Bool:$predicate
+    SPIRV_ScopeAttr:$execution_scope,
+    SPIRV_Bool:$predicate
   );
 
   let results = (outs
-    SPV_IOrUIVec4:$result
+    SPIRV_IOrUIVec4:$result
   );
 
   let assemblyFormat = [{
     $execution_scope $predicate attr-dict `:` type($result)
   }];
 }
 
 // -----
 
-def SPV_GroupNonUniformBroadcastOp : SPV_Op<"GroupNonUniformBroadcast",
+def SPIRV_GroupNonUniformBroadcastOp : SPIRV_Op<"GroupNonUniformBroadcast",
   [NoSideEffect, AllTypesMatch<["value", "result"]>]> {
   let summary = [{
     Result is the Value of the invocation identified by the id Id to all
     active invocations in the group.
   }];
 
   let description = [{
     Result Type  must be a scalar or vector of floating-point type, integer
let description = [{
     %id = ... : i32
     %0 = spirv.GroupNonUniformBroadcast "Subgroup" %scalar_value, %id : f32, i32
     %1 = spirv.GroupNonUniformBroadcast "Workgroup" %vector_value, %id :
       vector<4xf32>, i32
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_3>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_GroupNonUniformBallot]>
+    Capability<[SPIRV_C_GroupNonUniformBallot]>
   ];
 
   let arguments = (ins
-    SPV_ScopeAttr:$execution_scope,
-    SPV_Type:$value,
-    SPV_Integer:$id
+    SPIRV_ScopeAttr:$execution_scope,
+    SPIRV_Type:$value,
+    SPIRV_Integer:$id
   );
 
   let results = (outs
-    SPV_Type:$result
+    SPIRV_Type:$result
   );
 
   let assemblyFormat = [{
     $execution_scope operands attr-dict `:` type($value) `,` type($id)
   }];
 }
 
 // -----
 
-def SPV_GroupNonUniformElectOp : SPV_Op<"GroupNonUniformElect", []> {
+def SPIRV_GroupNonUniformElectOp : SPIRV_Op<"GroupNonUniformElect", []> {
   let summary = [{
     Result is true only in the active invocation with the lowest id in the
     group, otherwise result is false.
   }];
 
   let description = [{
     Result Type must be a Boolean type.
 
let description = [{
     #### Example:
 
     ```mlir
     %0 = spirv.GroupNonUniformElect : i1
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_3>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_GroupNonUniform]>
+    Capability<[SPIRV_C_GroupNonUniform]>
   ];
 
   let arguments = (ins
-    SPV_ScopeAttr:$execution_scope
+    SPIRV_ScopeAttr:$execution_scope
   );
 
   let results = (outs
-    SPV_Bool:$result
+    SPIRV_Bool:$result
   );
 
   let assemblyFormat = "$execution_scope attr-dict `:` type($result)";
 }
 
 // -----
 
-def SPV_GroupNonUniformFAddOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniformFAdd", SPV_Float, []> {
+def SPIRV_GroupNonUniformFAddOp : SPIRV_GroupNonUniformArithmeticOp<"GroupNonUniformFAdd", SPIRV_Float, []> {
   let summary = [{
     A floating point add group operation of all Value operands contributed
     by active invocations in the group.
   }];
 
   let description = [{
     Result Type  must be a scalar or vector of floating-point type.
 
let description = [{
     %scalar = ... : f32
     %vector = ... : vector<4xf32>
     %0 = spirv.GroupNonUniformFAdd "Workgroup" "Reduce" %scalar : f32
     %1 = spirv.GroupNonUniformFAdd "Subgroup" "ClusteredReduce" %vector cluster_size(%four) : vector<4xf32>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_3>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
+    Capability<[SPIRV_C_GroupNonUniformArithmetic, SPIRV_C_GroupNonUniformClustered, SPIRV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 // -----
 
-def SPV_GroupNonUniformFMaxOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniformFMax", SPV_Float, []> {
+def SPIRV_GroupNonUniformFMaxOp : SPIRV_GroupNonUniformArithmeticOp<"GroupNonUniformFMax", SPIRV_Float, []> {
   let summary = [{
     A floating point maximum group operation of all Value operands
     contributed by active invocations in by group.
   }];
 
   let description = [{
     Result Type  must be a scalar or vector of floating-point type.
 
let description = [{
     %scalar = ... : f32
     %vector = ... : vector<4xf32>
     %0 = spirv.GroupNonUniformFMax "Workgroup" "Reduce" %scalar : f32
     %1 = spirv.GroupNonUniformFMax "Subgroup" "ClusteredReduce" %vector cluster_size(%four) : vector<4xf32>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_3>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
+    Capability<[SPIRV_C_GroupNonUniformArithmetic, SPIRV_C_GroupNonUniformClustered, SPIRV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 // -----
 
-def SPV_GroupNonUniformFMinOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniformFMin", SPV_Float, []> {
+def SPIRV_GroupNonUniformFMinOp : SPIRV_GroupNonUniformArithmeticOp<"GroupNonUniformFMin", SPIRV_Float, []> {
   let summary = [{
     A floating point minimum group operation of all Value operands
     contributed by active invocations in the group.
   }];
 
   let description = [{
     Result Type  must be a scalar or vector of floating-point type.
 
let description = [{
     %scalar = ... : f32
     %vector = ... : vector<4xf32>
     %0 = spirv.GroupNonUniformFMin "Workgroup" "Reduce" %scalar : f32
     %1 = spirv.GroupNonUniformFMin "Subgroup" "ClusteredReduce" %vector cluster_size(%four) : vector<4xf32>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_3>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
+    Capability<[SPIRV_C_GroupNonUniformArithmetic, SPIRV_C_GroupNonUniformClustered, SPIRV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 // -----
 
-def SPV_GroupNonUniformFMulOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniformFMul", SPV_Float, []> {
+def SPIRV_GroupNonUniformFMulOp : SPIRV_GroupNonUniformArithmeticOp<"GroupNonUniformFMul", SPIRV_Float, []> {
   let summary = [{
     A floating point multiply group operation of all Value operands
     contributed by active invocations in the group.
   }];
 
   let description = [{
     Result Type  must be a scalar or vector of floating-point type.
 
let description = [{
     %scalar = ... : f32
     %vector = ... : vector<4xf32>
     %0 = spirv.GroupNonUniformFMul "Workgroup" "Reduce" %scalar : f32
     %1 = spirv.GroupNonUniformFMul "Subgroup" "ClusteredReduce" %vector cluster_size(%four) : vector<4xf32>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_3>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
+    Capability<[SPIRV_C_GroupNonUniformArithmetic, SPIRV_C_GroupNonUniformClustered, SPIRV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 // -----
 
-def SPV_GroupNonUniformIAddOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniformIAdd", SPV_Integer, []> {
+def SPIRV_GroupNonUniformIAddOp : SPIRV_GroupNonUniformArithmeticOp<"GroupNonUniformIAdd", SPIRV_Integer, []> {
   let summary = [{
     An integer add group operation of all Value operands contributed by
     active invocations in the group.
   }];
 
   let description = [{
     Result Type  must be a scalar or vector of integer type.
 
let description = [{
     %scalar = ... : i32
     %vector = ... : vector<4xi32>
     %0 = spirv.GroupNonUniformIAdd "Workgroup" "Reduce" %scalar : i32
     %1 = spirv.GroupNonUniformIAdd "Subgroup" "ClusteredReduce" %vector cluster_size(%four) : vector<4xi32>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_3>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
+    Capability<[SPIRV_C_GroupNonUniformArithmetic, SPIRV_C_GroupNonUniformClustered, SPIRV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 // -----
 
-def SPV_GroupNonUniformIMulOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniformIMul", SPV_Integer, []> {
+def SPIRV_GroupNonUniformIMulOp : SPIRV_GroupNonUniformArithmeticOp<"GroupNonUniformIMul", SPIRV_Integer, []> {
   let summary = [{
     An integer multiply group operation of all Value operands contributed by
     active invocations in the group.
   }];
 
   let description = [{
     Result Type  must be a scalar or vector of integer type.
 
let description = [{
     %scalar = ... : i32
     %vector = ... : vector<4xi32>
     %0 = spirv.GroupNonUniformIMul "Workgroup" "Reduce" %scalar : i32
     %1 = spirv.GroupNonUniformIMul "Subgroup" "ClusteredReduce" %vector cluster_size(%four) : vector<4xi32>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_3>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
+    Capability<[SPIRV_C_GroupNonUniformArithmetic, SPIRV_C_GroupNonUniformClustered, SPIRV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 // -----
 
-def SPV_GroupNonUniformSMaxOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniformSMax",
-                                    SPV_Integer,
+def SPIRV_GroupNonUniformSMaxOp : SPIRV_GroupNonUniformArithmeticOp<"GroupNonUniformSMax",
+                                    SPIRV_Integer,
                                     [SignedOp]> {
   let summary = [{
     A signed integer maximum group operation of all Value operands
     contributed by active invocations in the group.
   }];
 
   let description = [{
     Result Type  must be a scalar or vector of integer type.
let description = [{
     %scalar = ... : i32
     %vector = ... : vector<4xi32>
     %0 = spirv.GroupNonUniformSMax "Workgroup" "Reduce" %scalar : i32
     %1 = spirv.GroupNonUniformSMax "Subgroup" "ClusteredReduce" %vector cluster_size(%four) : vector<4xi32>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_3>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
+    Capability<[SPIRV_C_GroupNonUniformArithmetic, SPIRV_C_GroupNonUniformClustered, SPIRV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 // -----
 
-def SPV_GroupNonUniformSMinOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniformSMin",
-                                    SPV_Integer,
+def SPIRV_GroupNonUniformSMinOp : SPIRV_GroupNonUniformArithmeticOp<"GroupNonUniformSMin",
+                                    SPIRV_Integer,
                                     [SignedOp]> {
   let summary = [{
     A signed integer minimum group operation of all Value operands
     contributed by active invocations in the group.
   }];
 
   let description = [{
     Result Type  must be a scalar or vector of integer type.
let description = [{
     %scalar = ... : i32
     %vector = ... : vector<4xi32>
     %0 = spirv.GroupNonUniformSMin "Workgroup" "Reduce" %scalar : i32
     %1 = spirv.GroupNonUniformSMin "Subgroup" "ClusteredReduce" %vector cluster_size(%four) : vector<4xi32>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_3>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
+    Capability<[SPIRV_C_GroupNonUniformArithmetic, SPIRV_C_GroupNonUniformClustered, SPIRV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 // -----
 
-def SPV_GroupNonUniformShuffleOp : SPV_Op<"GroupNonUniformShuffle",
+def SPIRV_GroupNonUniformShuffleOp : SPIRV_Op<"GroupNonUniformShuffle",
     [NoSideEffect, AllTypesMatch<["value", "result"]>]> {
   let summary = [{
     Result is the Value of the invocation identified by the id Id.
   }];
 
   let description = [{
     Result Type  must be a scalar or vector of floating-point type, integer
     type, or Boolean type.
let description = [{
     #### Example:
 
     ```mlir
     %0 = spirv.GroupNonUniformShuffle <Subgroup> %val, %id : f32, i32
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_3>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_GroupNonUniformShuffle]>
+    Capability<[SPIRV_C_GroupNonUniformShuffle]>
   ];
 
   let arguments = (ins
-    SPV_ScopeAttr:$execution_scope,
-    SPV_ScalarOrVector:$value,
-    SPV_Integer:$id
+    SPIRV_ScopeAttr:$execution_scope,
+    SPIRV_ScalarOrVector:$value,
+    SPIRV_Integer:$id
   );
 
   let results = (outs
-    SPV_ScalarOrVector:$result
+    SPIRV_ScalarOrVector:$result
   );
 
   let assemblyFormat = [{
     $execution_scope operands attr-dict `:` type($value) `,` type($id)
   }];
 }
 
 // -----
 
-def SPV_GroupNonUniformShuffleDownOp : SPV_Op<"GroupNonUniformShuffleDown",
+def SPIRV_GroupNonUniformShuffleDownOp : SPIRV_Op<"GroupNonUniformShuffleDown",
     [NoSideEffect, AllTypesMatch<["value", "result"]>]> {
   let summary = [{
     Result is the Value of the invocation identified by the current
     invocation’s id within the group + Delta.
   }];
 
   let description = [{
     Result Type  must be a scalar or vector of floating-point type, integer
let description = [{
     #### Example:
 
     ```mlir
     %0 = spirv.GroupNonUniformShuffleDown <Subgroup> %val, %delta : f32, i32
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_3>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_GroupNonUniformShuffleRelative]>
+    Capability<[SPIRV_C_GroupNonUniformShuffleRelative]>
   ];
 
   let arguments = (ins
-    SPV_ScopeAttr:$execution_scope,
-    SPV_ScalarOrVector:$value,
-    SPV_Integer:$delta
+    SPIRV_ScopeAttr:$execution_scope,
+    SPIRV_ScalarOrVector:$value,
+    SPIRV_Integer:$delta
   );
 
   let results = (outs
-    SPV_Type:$result
+    SPIRV_Type:$result
   );
 
   let assemblyFormat = [{
     $execution_scope operands attr-dict `:` type($value) `,` type($delta)
   }];
 }
 
 // -----
 
-def SPV_GroupNonUniformShuffleUpOp : SPV_Op<"GroupNonUniformShuffleUp",
+def SPIRV_GroupNonUniformShuffleUpOp : SPIRV_Op<"GroupNonUniformShuffleUp",
     [NoSideEffect, AllTypesMatch<["value", "result"]>]> {
   let summary = [{
     Result is the Value of the invocation identified by the current
     invocation’s id within the group - Delta.
   }];
 
   let description = [{
     Result Type  must be a scalar or vector of floating-point type, integer
let description = [{
     #### Example:
 
     ```mlir
     %0 = spirv.GroupNonUniformShuffleUp <Subgroup> %val, %delta : f32, i32
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_3>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_GroupNonUniformShuffleRelative]>
+    Capability<[SPIRV_C_GroupNonUniformShuffleRelative]>
   ];
 
   let arguments = (ins
-    SPV_ScopeAttr:$execution_scope,
-    SPV_ScalarOrVector:$value,
-    SPV_Integer:$delta
+    SPIRV_ScopeAttr:$execution_scope,
+    SPIRV_ScalarOrVector:$value,
+    SPIRV_Integer:$delta
   );
 
   let results = (outs
-    SPV_Type:$result
+    SPIRV_Type:$result
   );
 
   let assemblyFormat = [{
     $execution_scope operands attr-dict `:` type($value) `,` type($delta)
   }];
 }
 
 // -----
 
-def SPV_GroupNonUniformShuffleXorOp : SPV_Op<"GroupNonUniformShuffleXor",
+def SPIRV_GroupNonUniformShuffleXorOp : SPIRV_Op<"GroupNonUniformShuffleXor",
     [NoSideEffect, AllTypesMatch<["value", "result"]>]> {
   let summary = [{
     Result is the Value of the invocation identified by the current
     invocation’s id within the group xor’ed with Mask.
   }];
 
   let description = [{
     Result Type  must be a scalar or vector of floating-point type, integer
let description = [{
     #### Example:
 
     ```mlir
     %0 = spirv.GroupNonUniformShuffleXor <Subgroup> %val, %mask : f32, i32
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_3>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_GroupNonUniformShuffle]>
+    Capability<[SPIRV_C_GroupNonUniformShuffle]>
   ];
 
   let arguments = (ins
-    SPV_ScopeAttr:$execution_scope,
-    SPV_ScalarOrVector:$value,
-    SPV_Integer:$mask
+    SPIRV_ScopeAttr:$execution_scope,
+    SPIRV_ScalarOrVector:$value,
+    SPIRV_Integer:$mask
   );
 
   let results = (outs
-    SPV_Type:$result
+    SPIRV_Type:$result
   );
 
   let assemblyFormat = [{
     $execution_scope operands attr-dict `:` type($value) `,` type($mask)
   }];
 }
 
 // -----
 
-def SPV_GroupNonUniformUMaxOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniformUMax",
-                                    SPV_Integer,
+def SPIRV_GroupNonUniformUMaxOp : SPIRV_GroupNonUniformArithmeticOp<"GroupNonUniformUMax",
+                                    SPIRV_Integer,
                                     [UnsignedOp]> {
   let summary = [{
     An unsigned integer maximum group operation of all Value operands
     contributed by active invocations in the group.
   }];
 
   let description = [{
     Result Type  must be a scalar or vector of integer type, whose
let description = [{
     %scalar = ... : i32
     %vector = ... : vector<4xi32>
     %0 = spirv.GroupNonUniformUMax "Workgroup" "Reduce" %scalar : i32
     %1 = spirv.GroupNonUniformUMax "Subgroup" "ClusteredReduce" %vector cluster_size(%four) : vector<4xi32>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_3>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
+    Capability<[SPIRV_C_GroupNonUniformArithmetic, SPIRV_C_GroupNonUniformClustered, SPIRV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 // -----
 
-def SPV_GroupNonUniformUMinOp : SPV_GroupNonUniformArithmeticOp<"GroupNonUniformUMin",
-                                    SPV_Integer,
+def SPIRV_GroupNonUniformUMinOp : SPIRV_GroupNonUniformArithmeticOp<"GroupNonUniformUMin",
+                                    SPIRV_Integer,
                                     [UnsignedOp]> {
   let summary = [{
     An unsigned integer minimum group operation of all Value operands
     contributed by active invocations in the group.
   }];
 
   let description = [{
     Result Type  must be a scalar or vector of integer type, whose
let description = [{
     %scalar = ... : i32
     %vector = ... : vector<4xi32>
     %0 = spirv.GroupNonUniformUMin "Workgroup" "Reduce" %scalar : i32
     %1 = spirv.GroupNonUniformUMin "Subgroup" "ClusteredReduce" %vector cluster_size(%four) : vector<4xi32>
     ```
   }];
 
   let availability = [
-    MinVersion<SPV_V_1_3>,
-    MaxVersion<SPV_V_1_6>,
+    MinVersion<SPIRV_V_1_3>,
+    MaxVersion<SPIRV_V_1_6>,
     Extension<[]>,
-    Capability<[SPV_C_GroupNonUniformArithmetic, SPV_C_GroupNonUniformClustered, SPV_C_GroupNonUniformPartitionedNV]>
+    Capability<[SPIRV_C_GroupNonUniformArithmetic, SPIRV_C_GroupNonUniformClustered, SPIRV_C_GroupNonUniformPartitionedNV]>
   ];
 }
 
 // -----
 
 #endif // MLIR_DIALECT_SPIRV_IR_NON_UNIFORM_OPS

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVStructureOps.td

 include "mlir/IR/FunctionInterfaces.td"
 include "mlir/IR/OpAsmInterface.td"
 include "mlir/IR/SymbolInterfaces.td"
 include "mlir/Interfaces/CallInterfaces.td"
 include "mlir/Interfaces/SideEffectInterfaces.td"
 
 // -----
 
-def SPV_AddressOfOp : SPV_Op<"mlir.addressof",
+def SPIRV_AddressOfOp : SPIRV_Op<"mlir.addressof",
     [DeclareOpInterfaceMethods<OpAsmOpInterface, ["getAsmResultNames"]>,
      InFunctionScope, NoSideEffect]> {
   let summary = "Get the address of a global variable.";
 
   let description = [{
     Variables in module scope are defined using symbol names. This op generates
     an SSA value that can be used to refer to the symbol within function scope
     for use in ops that expect an SSA value. This operation has no corresponding
let description = [{
     ```
   }];
 
   let arguments = (ins
     FlatSymbolRefAttr:$variable
   );
 
   let results = (outs
-    SPV_AnyPtr:$pointer
+    SPIRV_AnyPtr:$pointer
   );
 
   let hasOpcode = 0;
 
   let autogenSerialization = 0;
 
   let builders = [OpBuilder<(ins "spirv::GlobalVariableOp":$var)>];
 
   let assemblyFormat = "$variable attr-dict `:` type($pointer)";
 }
 
 // -----
 
-def SPV_ConstantOp : SPV_Op<"Constant",
+def SPIRV_ConstantOp : SPIRV_Op<"Constant",
     [ConstantLike,
      DeclareOpInterfaceMethods<OpAsmOpInterface, ["getAsmResultNames"]>,
      NoSideEffect]> {
   let summary = [{
     Declare a new integer-type or floating-point-type scalar constant.
   }];
 
   let description = [{
let description = [{
     TODO: support constant structs
   }];
 
   let arguments = (ins
     AnyAttr:$value
   );
 
   let results = (outs
-    SPV_Type:$constant
+    SPIRV_Type:$constant
   );
 
   let hasFolder = 1;
 
   let extraClassDeclaration = [{
     // Returns true if a constant can be built for the given `type`.
     static bool isBuildableWith(Type type);
 
     // Creates a constant zero/one of the given `type` at the current insertion
     // point of `builder` and returns it.
     static spirv::ConstantOp getZero(Type type, Location loc,
                                      OpBuilder &builder);
     static spirv::ConstantOp getOne(Type type, Location loc,
                                     OpBuilder &builder);
   }];
 
   let hasOpcode = 0;
 
   let autogenSerialization = 0;
 }
 
 // -----
 
-def SPV_EntryPointOp : SPV_Op<"EntryPoint", [InModuleScope]> {
+def SPIRV_EntryPointOp : SPIRV_Op<"EntryPoint", [InModuleScope]> {
   let summary = [{
     Declare an entry point, its execution model, and its interface.
   }];
 
   let description = [{
     Execution Model is the execution model for the entry point and its
     static call tree. See Execution Model.
 
let description = [{
     ```mlir
     spirv.EntryPoint "GLCompute" @foo
     spirv.EntryPoint "Kernel" @foo, @var1, @var2
 
     ```
   }];
 
   let arguments = (ins
-    SPV_ExecutionModelAttr:$execution_model,
+    SPIRV_ExecutionModelAttr:$execution_model,
     FlatSymbolRefAttr:$fn,
     SymbolRefArrayAttr:$interface
   );
 
   let results = (outs);
 
   let autogenSerialization = 0;
 
   let builders = [
     OpBuilder<(ins "spirv::ExecutionModel":$executionModel,
       "spirv::FuncOp":$function, "ArrayRef<Attribute>":$interfaceVars)>];
 }
 
 // -----
 
-def SPV_ExecutionModeOp : SPV_Op<"ExecutionMode", [InModuleScope]> {
+def SPIRV_ExecutionModeOp : SPIRV_Op<"ExecutionMode", [InModuleScope]> {
   let summary = "Declare an execution mode for an entry point.";
 
   let description = [{
     Entry Point must be the Entry Point <id> operand of an OpEntryPoint
     instruction.
 
     Mode is the execution mode. See Execution Mode.
 
let description = [{
     ```mlir
     spirv.ExecutionMode @foo "ContractionOff"
     spirv.ExecutionMode @bar "LocalSizeHint", 3, 4, 5
     ```
   }];
 
   let arguments = (ins
     FlatSymbolRefAttr:$fn,
-    SPV_ExecutionModeAttr:$execution_mode,
+    SPIRV_ExecutionModeAttr:$execution_mode,
     I32ArrayAttr:$values
   );
 
   let results = (outs);
 
   let hasVerifier = 0;
 
   let autogenSerialization = 0;
 
   let builders = [
     OpBuilder<(ins "spirv::FuncOp":$function,
       "spirv::ExecutionMode":$executionMode, "ArrayRef<int32_t>":$params)>];
 }
 
 // -----
 
-def SPV_FuncOp : SPV_Op<"func", [
+def SPIRV_FuncOp : SPIRV_Op<"func", [
     AutomaticAllocationScope, DeclareOpInterfaceMethods<CallableOpInterface>,
     FunctionOpInterface, InModuleScope, IsolatedFromAbove, Symbol
   ]> {
   let summary = "Declare or define a function";
 
   let description = [{
     This op declares or defines a SPIR-V function using one region, which
     contains one or more blocks.
let description = [{
     spirv.func @foo() -> () "None" { ... }
     spirv.func @bar() -> () "Inline|Pure" { ... }
     ```
   }];
 
   let arguments = (ins
     TypeAttrOf<FunctionType>:$function_type,
     StrAttr:$sym_name,
-    SPV_FunctionControlAttr:$function_control
+    SPIRV_FunctionControlAttr:$function_control
   );
 
   let results = (outs);
 
   let regions = (region AnyRegion:$body);
 
   let hasVerifier = 0;
 
let extraClassDeclaration = [{
     /// type and the presence of the (potentially empty) function body.
     /// Ensures SPIR-V specific semantics.
     LogicalResult verifyBody();
   }];
 }
 
 // -----
 
-def SPV_GlobalVariableOp : SPV_Op<"GlobalVariable", [InModuleScope, Symbol]> {
+def SPIRV_GlobalVariableOp : SPIRV_Op<"GlobalVariable", [InModuleScope, Symbol]> {
   let summary = [{
     Allocate an object in memory at module scope. The object is
     referenced using a symbol name.
   }];
 
   let description = [{
     The variable type must be an OpTypePointer. Its type operand is the type of
     object in memory.
let extraClassDeclaration = [{
     ::mlir::spirv::StorageClass storageClass() {
       return this->getType().cast<::mlir::spirv::PointerType>().getStorageClass();
     }
   }];
 }
 
 // -----
 
-def SPV_ModuleOp : SPV_Op<"module",
+def SPIRV_ModuleOp : SPIRV_Op<"module",
     [IsolatedFromAbove, NoRegionArguments, NoTerminator,
      SingleBlock, SymbolTable, Symbol]> {
   let summary = "The top-level op that defines a SPIR-V module";
 
   let description = [{
     This op defines a SPIR-V module using a MLIR region. The region contains
     one block. Module-level operations, including functions definitions,
     are all placed in this block.
let description = [{
     ```
 
     #### Example:
 
     ```mlir
     spirv.module Logical GLSL450  {}
 
     spirv.module Logical Vulkan
-        requires #spirv.vce<v1.0, [Shader], [SPV_KHR_vulkan_memory_model]>
+        requires #spirv.vce<v1.0, [Shader], [SPIRV_KHR_vulkan_memory_model]>
         attributes { some_additional_attr = ... } {
       spirv.func @do_nothing() -> () {
         spirv.Return
       }
     }
     ```
   }];
 
   let arguments = (ins
-    SPV_AddressingModelAttr:$addressing_model,
-    SPV_MemoryModelAttr:$memory_model,
-    OptionalAttr<SPV_VerCapExtAttr>:$vce_triple,
+    SPIRV_AddressingModelAttr:$addressing_model,
+    SPIRV_MemoryModelAttr:$memory_model,
+    OptionalAttr<SPIRV_VerCapExtAttr>:$vce_triple,
     OptionalAttr<StrAttr>:$sym_name
   );
 
   let results = (outs);
 
   let regions = (region AnyRegion);
 
   let builders = [
def SPIRV_ModuleOp : SPIRV_Op<"module",
   }];
 
   let hasVerifier = 0;
   let hasRegionVerifier = 1;
 }
 
 // -----
 
-def SPV_ReferenceOfOp : SPV_Op<"mlir.referenceof", [NoSideEffect]> {
+def SPIRV_ReferenceOfOp : SPIRV_Op<"mlir.referenceof", [NoSideEffect]> {
   let summary = "Reference a specialization constant.";
 
   let description = [{
     Specialization constants in module scope are defined using symbol names.
     This op generates an SSA value that can be used to refer to the symbol
     within function scope for use in ops that expect an SSA value.
     This operation has no corresponding SPIR-V instruction; it's merely used
     for modelling purpose in the SPIR-V dialect. This op's return type is
let description = [{
     TODO Add support for composite specialization constants.
   }];
 
   let arguments = (ins
     FlatSymbolRefAttr:$spec_const
   );
 
   let results = (outs
-    SPV_Type:$reference
+    SPIRV_Type:$reference
   );
 
   let hasOpcode = 0;
 
   let autogenSerialization = 0;
 
   let assemblyFormat = "$spec_const attr-dict `:` type($reference)";
 }
 
 // -----
 
-def SPV_SpecConstantOp : SPV_Op<"SpecConstant", [InModuleScope, Symbol]> {
+def SPIRV_SpecConstantOp : SPIRV_Op<"SpecConstant", [InModuleScope, Symbol]> {
   let summary = [{
     Declare a new integer-type or floating-point-type scalar specialization
     constant.
   }];
 
   let description = [{
     This op declares a SPIR-V scalar specialization constant. SPIR-V has
     multiple constant instructions covering different scalar types:
def SPIRV_SpecConstantOp : SPIRV_Op<"SpecConstant", [InModuleScope, Symbol]> {
 
   let hasOpcode = 0;
 
   let autogenSerialization = 0;
 }
 
 // -----
 
-def SPV_SpecConstantCompositeOp : SPV_Op<"SpecConstantComposite", [
+def SPIRV_SpecConstantCompositeOp : SPIRV_Op<"SpecConstantComposite", [
     InModuleScope, Symbol]> {
   let summary = "Declare a new composite specialization constant.";
 
   let description = [{
     This op declares a SPIR-V composite specialization constant. This covers
     the `OpSpecConstantComposite` SPIR-V instruction. Scalar constants are
     covered by `spirv.SpecConstant`.
 
def SPIRV_SpecConstantCompositeOp : SPIRV_Op<"SpecConstantComposite", [
 
   let hasOpcode = 0;
 
   let autogenSerialization = 0;
 }
 
 // -----
 
-def SPV_SpecConstantOperationOp : SPV_Op<"SpecConstantOperation", [
+def SPIRV_SpecConstantOperationOp : SPIRV_Op<"SpecConstantOperation", [
        NoSideEffect, InFunctionScope,
        SingleBlockImplicitTerminator<"YieldOp">]> {
   let summary = [{
     Declare a new specialization constant that results from doing an operation.
   }];
 
   let description = [{
     This op declares a SPIR-V specialization constant that results from
def SPIRV_SpecConstantOperationOp : SPIRV_Op<"SpecConstantOperation", [
   let autogenSerialization = 0;
 
   let hasVerifier = 0;
   let hasRegionVerifier = 1;
 }
 
 // -----
 
-def SPV_YieldOp : SPV_Op<"mlir.yield", [
+def SPIRV_YieldOp : SPIRV_Op<"mlir.yield", [
     HasParent<"SpecConstantOperationOp">, NoSideEffect, Terminator]> {
   let summary = [{
     Yields the result computed in `spirv.SpecConstantOperation`'s
     region back to the parent op.
   }];
 
   let description = [{
     This op is a special terminator whose only purpose is to terminate
     an `spirv.SpecConstantOperation`'s enclosed region. It accepts a
     single operand produced by the preceeding (and only other) instruction
-    in its parent block (see SPV_SpecConstantOperation for further
+    in its parent block (see SPIRV_SpecConstantOperation for further
     details). This op has no corresponding SPIR-V instruction.
 
     ```
     spirv.mlir.yield ::= `spirv.mlir.yield` ssa-id : spirv-type
     ```
 
     #### Example:
     ```mlir

mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp

matchAndRewrite(vector::ExtractStridedSliceOp extractOp, OpAdaptor adaptor,
     rewriter.replaceOpWithNewOp<spirv::VectorShuffleOp>(
         extractOp, dstType, srcVector, srcVector,
         rewriter.getI32ArrayAttr(indices));
 
     return success();
   }
 };
 
-template <class SPVFMAOp>
+template <class SPIRVFMAOp>
 struct VectorFmaOpConvert final : public OpConversionPattern<vector::FMAOp> {
   using OpConversionPattern::OpConversionPattern;
 
   LogicalResult
   matchAndRewrite(vector::FMAOp fmaOp, OpAdaptor adaptor,
                   ConversionPatternRewriter &rewriter) const override {
     Type dstType = getTypeConverter()->convertType(fmaOp.getType());
     if (!dstType)
       return failure();
-    rewriter.replaceOpWithNewOp<SPVFMAOp>(fmaOp, dstType, adaptor.getLhs(),
+    rewriter.replaceOpWithNewOp<SPIRVFMAOp>(fmaOp, dstType, adaptor.getLhs(),
                                             adaptor.getRhs(), adaptor.getAcc());
     return success();
   }
 };
 
 struct VectorInsertOpConvert final
     : public OpConversionPattern<vector::InsertOp> {
   using OpConversionPattern::OpConversionPattern;
 
matchAndRewrite(vector::InsertStridedSliceOp insertOp, OpAdaptor adaptor,
     rewriter.replaceOpWithNewOp<spirv::VectorShuffleOp>(
         insertOp, dstVector.getType(), dstVector, srcVector,
         rewriter.getI32ArrayAttr(indices));
 
     return success();
   }
 };
 
-template <class SPVFMaxOp, class SPVFMinOp, class SPVUMaxOp, class SPVUMinOp,
-          class SPVSMaxOp, class SPVSMinOp>
+template <class SPIRVFMaxOp, class SPIRVFMinOp, class SPIRVUMaxOp,
+          class SPIRVUMinOp, class SPIRVSMaxOp, class SPIRVSMinOp>
 struct VectorReductionPattern final
     : public OpConversionPattern<vector::ReductionOp> {
   using OpConversionPattern::OpConversionPattern;
 
   LogicalResult
   matchAndRewrite(vector::ReductionOp reduceOp, OpAdaptor adaptor,
                   ConversionPatternRewriter &rewriter) const override {
     Type resultType = typeConverter->convertType(reduceOp.getType());

 #define INT_OR_FLOAT_CASE(kind, fop)                                           \
   case vector::CombiningKind::kind:                                            \
     result = rewriter.create<fop>(loc, resultType, result, next);              \
     break
 
         INT_AND_FLOAT_CASE(ADD, IAddOp, FAddOp);
         INT_AND_FLOAT_CASE(MUL, IMulOp, FMulOp);
 
-        INT_OR_FLOAT_CASE(MAXF, SPVFMaxOp);
-        INT_OR_FLOAT_CASE(MINF, SPVFMinOp);
-        INT_OR_FLOAT_CASE(MINUI, SPVUMinOp);
-        INT_OR_FLOAT_CASE(MINSI, SPVSMinOp);
-        INT_OR_FLOAT_CASE(MAXUI, SPVUMaxOp);
-        INT_OR_FLOAT_CASE(MAXSI, SPVSMaxOp);
+        INT_OR_FLOAT_CASE(MAXF, SPIRVFMaxOp);
+        INT_OR_FLOAT_CASE(MINF, SPIRVFMinOp);
+        INT_OR_FLOAT_CASE(MINUI, SPIRVUMinOp);
+        INT_OR_FLOAT_CASE(MINSI, SPIRVSMinOp);
+        INT_OR_FLOAT_CASE(MAXUI, SPIRVUMaxOp);
+        INT_OR_FLOAT_CASE(MAXSI, SPIRVSMaxOp);
 
       case vector::CombiningKind::AND:
       case vector::CombiningKind::OR:
       case vector::CombiningKind::XOR:
         return rewriter.notifyMatchFailure(reduceOp, "unimplemented");
       }
     }
 

mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.td

 
 include "mlir/IR/PatternBase.td"
 include "mlir/Dialect/SPIRV/IR/SPIRVOps.td"
 
 //===----------------------------------------------------------------------===//
 // spirv.Bitcast
 //===----------------------------------------------------------------------===//
 
-def ConvertChainedBitcast : Pat<(SPV_BitcastOp (SPV_BitcastOp $operand)),
-                                (SPV_BitcastOp $operand)>;
+def ConvertChainedBitcast : Pat<(SPIRV_BitcastOp (SPIRV_BitcastOp $operand)),
+                                (SPIRV_BitcastOp $operand)>;
 
 //===----------------------------------------------------------------------===//
 // spirv.LogicalNot
 //===----------------------------------------------------------------------===//
 
 def ConvertLogicalNotOfIEqual : Pat<
-    (SPV_LogicalNotOp (SPV_IEqualOp $lhs, $rhs)),
-    (SPV_INotEqualOp $lhs, $rhs)>;
+    (SPIRV_LogicalNotOp (SPIRV_IEqualOp $lhs, $rhs)),
+    (SPIRV_INotEqualOp $lhs, $rhs)>;
 
 def ConvertLogicalNotOfINotEqual : Pat<
-    (SPV_LogicalNotOp (SPV_INotEqualOp $lhs, $rhs)),
-    (SPV_IEqualOp $lhs, $rhs)>;
+    (SPIRV_LogicalNotOp (SPIRV_INotEqualOp $lhs, $rhs)),
+    (SPIRV_IEqualOp $lhs, $rhs)>;
 
 def ConvertLogicalNotOfLogicalEqual : Pat<
-    (SPV_LogicalNotOp (SPV_LogicalEqualOp $lhs, $rhs)),
-    (SPV_LogicalNotEqualOp $lhs, $rhs)>;
+    (SPIRV_LogicalNotOp (SPIRV_LogicalEqualOp $lhs, $rhs)),
+    (SPIRV_LogicalNotEqualOp $lhs, $rhs)>;
 
 def ConvertLogicalNotOfLogicalNotEqual : Pat<
-    (SPV_LogicalNotOp (SPV_LogicalNotEqualOp $lhs, $rhs)),
-    (SPV_LogicalEqualOp $lhs, $rhs)>;
+    (SPIRV_LogicalNotOp (SPIRV_LogicalNotEqualOp $lhs, $rhs)),
+    (SPIRV_LogicalEqualOp $lhs, $rhs)>;
 
 //===----------------------------------------------------------------------===//
 // spirv.Select -> spirv.GL.*Clamp
 //===----------------------------------------------------------------------===//
 
 def ValuesAreEqual : Constraint<CPred<"$0 == $1">>;
 
 foreach CmpClampPair = [
-    [SPV_FOrdLessThanOp, SPV_GLFClampOp],
-    [SPV_FOrdLessThanEqualOp, SPV_GLFClampOp],
-    [SPV_SLessThanOp, SPV_GLSClampOp],
-    [SPV_SLessThanEqualOp, SPV_GLSClampOp],
-    [SPV_ULessThanOp, SPV_GLUClampOp],
-    [SPV_ULessThanEqualOp, SPV_GLUClampOp]] in {
+    [SPIRV_FOrdLessThanOp, SPIRV_GLFClampOp],
+    [SPIRV_FOrdLessThanEqualOp, SPIRV_GLFClampOp],
+    [SPIRV_SLessThanOp, SPIRV_GLSClampOp],
+    [SPIRV_SLessThanEqualOp, SPIRV_GLSClampOp],
+    [SPIRV_ULessThanOp, SPIRV_GLUClampOp],
+    [SPIRV_ULessThanEqualOp, SPIRV_GLUClampOp]] in {
 
 // Detect: $min < $input, $input < $max
 def ConvertComparisonIntoClamp1_#CmpClampPair[0] : Pat<
-    (SPV_SelectOp
+    (SPIRV_SelectOp
         (CmpClampPair[0]
-            (SPV_SelectOp:$middle0
+            (SPIRV_SelectOp:$middle0
                 (CmpClampPair[0] $min, $input),
                 $input,
                 $min
             ),
             $max
         ),
         $middle1,
         $max),
     (CmpClampPair[1] $input, $min, $max),
     [(ValuesAreEqual $middle0, $middle1)]>;
 
 // Detect: $input < $min, $max < $input
 def ConvertComparisonIntoClamp2_#CmpClampPair[0] : Pat<
-    (SPV_SelectOp
+    (SPIRV_SelectOp
         (CmpClampPair[0] $max, $input),
         $max,
-        (SPV_SelectOp
+        (SPIRV_SelectOp
             (CmpClampPair[0] $input, $min),
             $min,
             $input
         )),
     (CmpClampPair[1] $input, $min, $max)>;
 }

mlir/lib/Dialect/SPIRV/IR/SPIRVEnums.cpp

 //===----------------------------------------------------------------------===//
 // Availability relationship
 //===----------------------------------------------------------------------===//
 
 ArrayRef<spirv::Extension> spirv::getImpliedExtensions(spirv::Version version) {
   // Note: the following lists are from "Appendix A: Changes" of the spec.
 
 #define V_1_3_IMPLIED_EXTS                                                     \
-  Extension::SPV_KHR_shader_draw_parameters, Extension::SPV_KHR_16bit_storage, \
-      Extension::SPV_KHR_device_group, Extension::SPV_KHR_multiview,           \
-      Extension::SPV_KHR_storage_buffer_storage_class,                         \
-      Extension::SPV_KHR_variable_pointers
+  Extension::SPIRV_KHR_shader_draw_parameters,                                 \
+      Extension::SPIRV_KHR_16bit_storage, Extension::SPIRV_KHR_device_group,   \
+      Extension::SPIRV_KHR_multiview,                                          \
+      Extension::SPIRV_KHR_storage_buffer_storage_class,                       \
+      Extension::SPIRV_KHR_variable_pointers
 
 #define V_1_4_IMPLIED_EXTS                                                     \
-  Extension::SPV_KHR_no_integer_wrap_decoration,                               \
-      Extension::SPV_GOOGLE_decorate_string,                                   \
-      Extension::SPV_GOOGLE_hlsl_functionality1,                               \
-      Extension::SPV_KHR_float_controls
+  Extension::SPIRV_KHR_no_integer_wrap_decoration,                             \
+      Extension::SPIRV_GOOGLE_decorate_string,                                 \
+      Extension::SPIRV_GOOGLE_hlsl_functionality1,                             \
+      Extension::SPIRV_KHR_float_controls
 
 #define V_1_5_IMPLIED_EXTS                                                     \
-  Extension::SPV_KHR_8bit_storage, Extension::SPV_EXT_descriptor_indexing,     \
-      Extension::SPV_EXT_shader_viewport_index_layer,                          \
-      Extension::SPV_EXT_physical_storage_buffer,                              \
-      Extension::SPV_KHR_physical_storage_buffer,                              \
-      Extension::SPV_KHR_vulkan_memory_model
+  Extension::SPIRV_KHR_8bit_storage, Extension::SPIRV_EXT_descriptor_indexing, \
+      Extension::SPIRV_EXT_shader_viewport_index_layer,                        \
+      Extension::SPIRV_EXT_physical_storage_buffer,                            \
+      Extension::SPIRV_KHR_physical_storage_buffer,                            \
+      Extension::SPIRV_KHR_vulkan_memory_model
 
   switch (version) {
   default:
     return {};
   case Version::V_1_3: {
     // The following manual ArrayRef constructor call is to satisfy GCC 5.
     static const Extension exts[] = {V_1_3_IMPLIED_EXTS};
     return ArrayRef<spirv::Extension>(exts, std::size(exts));

mlir/lib/Dialect/SPIRV/IR/SPIRVGLCanonicalization.cpp

 
 namespace {
 #include "SPIRVCanonicalization.inc"
 } // namespace
 
 namespace mlir {
 namespace spirv {
 void populateSPIRVGLCanonicalizationPatterns(RewritePatternSet &results) {
-  results.add<ConvertComparisonIntoClamp1_SPV_FOrdLessThanOp,
-              ConvertComparisonIntoClamp1_SPV_FOrdLessThanEqualOp,
-              ConvertComparisonIntoClamp1_SPV_SLessThanOp,
-              ConvertComparisonIntoClamp1_SPV_SLessThanEqualOp,
-              ConvertComparisonIntoClamp1_SPV_ULessThanOp,
-              ConvertComparisonIntoClamp1_SPV_ULessThanEqualOp,
-              ConvertComparisonIntoClamp2_SPV_FOrdLessThanOp,
-              ConvertComparisonIntoClamp2_SPV_FOrdLessThanEqualOp,
-              ConvertComparisonIntoClamp2_SPV_SLessThanOp,
-              ConvertComparisonIntoClamp2_SPV_SLessThanEqualOp,
-              ConvertComparisonIntoClamp2_SPV_ULessThanOp,
-              ConvertComparisonIntoClamp2_SPV_ULessThanEqualOp>(
+  results.add<ConvertComparisonIntoClamp1_SPIRV_FOrdLessThanOp,
+              ConvertComparisonIntoClamp1_SPIRV_FOrdLessThanEqualOp,
+              ConvertComparisonIntoClamp1_SPIRV_SLessThanOp,
+              ConvertComparisonIntoClamp1_SPIRV_SLessThanEqualOp,
+              ConvertComparisonIntoClamp1_SPIRV_ULessThanOp,
+              ConvertComparisonIntoClamp1_SPIRV_ULessThanEqualOp,
+              ConvertComparisonIntoClamp2_SPIRV_FOrdLessThanOp,
+              ConvertComparisonIntoClamp2_SPIRV_FOrdLessThanEqualOp,
+              ConvertComparisonIntoClamp2_SPIRV_SLessThanOp,
+              ConvertComparisonIntoClamp2_SPIRV_SLessThanEqualOp,
+              ConvertComparisonIntoClamp2_SPIRV_ULessThanOp,
+              ConvertComparisonIntoClamp2_SPIRV_ULessThanEqualOp>(
       results.getContext());
 }
 } // namespace spirv
 } // namespace mlir

mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp

 unsigned CooperativeMatrixNVType::getColumns() const {
   return getImpl()->columns;
 }
 
 void CooperativeMatrixNVType::getExtensions(
     SPIRVType::ExtensionArrayRefVector &extensions,
     Optional<StorageClass> storage) {
   getElementType().cast<SPIRVType>().getExtensions(extensions, storage);
-  static const Extension exts[] = {Extension::SPV_NV_cooperative_matrix};
+  static const Extension exts[] = {Extension::SPIRV_NV_cooperative_matrix};
   ArrayRef<Extension> ref(exts, std::size(exts));
   extensions.push_back(ref);
 }
 
 void CooperativeMatrixNVType::getCapabilities(
     SPIRVType::CapabilityArrayRefVector &capabilities,
     Optional<StorageClass> storage) {
   getElementType().cast<SPIRVType>().getCapabilities(capabilities, storage);

 MatrixLayout JointMatrixINTELType::getMatrixLayout() const {
   return getImpl()->matrixLayout;
 }
 
 void JointMatrixINTELType::getExtensions(
     SPIRVType::ExtensionArrayRefVector &extensions,
     Optional<StorageClass> storage) {
   getElementType().cast<SPIRVType>().getExtensions(extensions, storage);
-  static const Extension exts[] = {Extension::SPV_INTEL_joint_matrix};
+  static const Extension exts[] = {Extension::SPIRV_INTEL_joint_matrix};
   ArrayRef<Extension> ref(exts, std::size(exts));
   extensions.push_back(ref);
 }
 
 void JointMatrixINTELType::getCapabilities(
     SPIRVType::CapabilityArrayRefVector &capabilities,
     Optional<StorageClass> storage) {
   getElementType().cast<SPIRVType>().getCapabilities(capabilities, storage);
bool ScalarType::isValid(IntegerType type) {
   default:
     return false;
   }
 }
 
 void ScalarType::getExtensions(SPIRVType::ExtensionArrayRefVector &extensions,
                                Optional<StorageClass> storage) {
   // 8- or 16-bit integer/floating-point numbers will require extra extensions
-  // to appear in interface storage classes. See SPV_KHR_16bit_storage and
-  // SPV_KHR_8bit_storage for more details.
+  // to appear in interface storage classes. See SPIRV_KHR_16bit_storage and
+  // SPIRV_KHR_8bit_storage for more details.
   if (!storage)
     return;
 
   switch (*storage) {
   case StorageClass::PushConstant:
   case StorageClass::StorageBuffer:
   case StorageClass::Uniform:
     if (getIntOrFloatBitWidth() == 8) {
-      static const Extension exts[] = {Extension::SPV_KHR_8bit_storage};
+      static const Extension exts[] = {Extension::SPIRV_KHR_8bit_storage};
       ArrayRef<Extension> ref(exts, std::size(exts));
       extensions.push_back(ref);
     }
     [[fallthrough]];
   case StorageClass::Input:
   case StorageClass::Output:
     if (getIntOrFloatBitWidth() == 16) {
-      static const Extension exts[] = {Extension::SPV_KHR_16bit_storage};
+      static const Extension exts[] = {Extension::SPIRV_KHR_16bit_storage};
       ArrayRef<Extension> ref(exts, std::size(exts));
       extensions.push_back(ref);
     }
     break;
   default:
     break;
   }
 }
 
 void ScalarType::getCapabilities(
     SPIRVType::CapabilityArrayRefVector &capabilities,
     Optional<StorageClass> storage) {
   unsigned bitwidth = getIntOrFloatBitWidth();
 
   // 8- or 16-bit integer/floating-point numbers will require extra capabilities
-  // to appear in interface storage classes. See SPV_KHR_16bit_storage and
-  // SPV_KHR_8bit_storage for more details.
+  // to appear in interface storage classes. See SPIRV_KHR_16bit_storage and
+  // SPIRV_KHR_8bit_storage for more details.
 
 #define STORAGE_CASE(storage, cap8, cap16)                                     \
   case StorageClass::storage: {                                                \
     if (bitwidth == 8) {                                                       \
       static const Capability caps[] = {Capability::cap8};                     \
       ArrayRef<Capability> ref(caps, std::size(caps));                         \
       capabilities.push_back(ref);                                             \
       return;                                                                  \

mlir/test/Conversion/ArithmeticToSPIRV/arithmetic-to-spirv.mlir

 
 } // end module
 
 // -----
 
 module attributes {
   spirv.target_env = #spirv.target_env<
     #spirv.vce<v1.0, [Shader, Int8, Int16, Int64, Float16, Float64],
-             [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+             [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
 } {
 
 // CHECK-LABEL: @select
 func.func @select(%arg0 : i32, %arg1 : i32) {
   %0 = arith.cmpi sle, %arg0, %arg1 : i32
   // CHECK: spirv.Select
   %1 = arith.select %0, %arg0, %arg1 : i32
   return

mlir/test/Conversion/FuncToSPIRV/types-to-spirv.mlir

 
 //===----------------------------------------------------------------------===//
 // MemRef types
 //===----------------------------------------------------------------------===//
 
 // Check memory spaces.
 module attributes {
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [], [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
 } {
 
 // CHECK-LABEL: func @memref_mem_space
 // CHECK-SAME: StorageBuffer
 // CHECK-SAME: Uniform
 // CHECK-SAME: Workgroup
 // CHECK-SAME: PushConstant
 // CHECK-SAME: Private

 
 } // end module
 
 // -----
 
 // Reject memory spaces.
 module attributes {
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [], [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
 } {
 
 // CHECK-LABEL: func @numeric_memref_mem_space1
 // CHECK-SAME: memref<4xf32>
 // NOEMU-LABEL: func @numeric_memref_mem_space1
 // NOEMU-SAME: memref<4xf32>
 func.func @numeric_memref_mem_space1(%arg0: memref<4xf32>) { return }
 

 // -----
 
 // Check that using non-32-bit scalar types in interface storage classes
 // requires special capability and extension: keep as-is when the capability
 // and extension is available.
 module attributes {
   spirv.target_env = #spirv.target_env<
     #spirv.vce<v1.0, [StoragePushConstant8, StoragePushConstant16, Int64, Float64],
-             [SPV_KHR_8bit_storage, SPV_KHR_16bit_storage]>, #spirv.resource_limits<>>
+             [SPIRV_KHR_8bit_storage, SPIRV_KHR_16bit_storage]>, #spirv.resource_limits<>>
 } {
 
 // CHECK-LABEL: spirv.func @memref_8bit_PushConstant
 // CHECK-SAME: !spirv.ptr<!spirv.struct<(!spirv.array<16 x i8, stride=1> [0])>, PushConstant>
 // NOEMU-LABEL: spirv.func @memref_8bit_PushConstant
 // NOEMU-SAME: !spirv.ptr<!spirv.struct<(!spirv.array<16 x i8, stride=1> [0])>, PushConstant>
 func.func @memref_8bit_PushConstant(%arg0: memref<16xi8, #spirv.storage_class<PushConstant>>) { return }
 

 // -----
 
 // Check that using non-32-bit scalar types in interface storage classes
 // requires special capability and extension: keep as-is when the capability
 // and extension is available.
 module attributes {
   spirv.target_env = #spirv.target_env<
     #spirv.vce<v1.0, [StorageBuffer8BitAccess, StorageBuffer16BitAccess, Int64, Float64],
-             [SPV_KHR_8bit_storage, SPV_KHR_16bit_storage]>, #spirv.resource_limits<>>
+             [SPIRV_KHR_8bit_storage, SPIRV_KHR_16bit_storage]>, #spirv.resource_limits<>>
 } {
 
 // CHECK-LABEL: spirv.func @memref_8bit_StorageBuffer
 // CHECK-SAME: !spirv.ptr<!spirv.struct<(!spirv.array<16 x i8, stride=1> [0])>, StorageBuffer>
 // NOEMU-LABEL: spirv.func @memref_8bit_StorageBuffer
 // NOEMU-SAME: !spirv.ptr<!spirv.struct<(!spirv.array<16 x i8, stride=1> [0])>, StorageBuffer>
 func.func @memref_8bit_StorageBuffer(%arg0: memref<16xi8, #spirv.storage_class<StorageBuffer>>) { return }
 

 // -----
 
 // Check that using non-32-bit scalar types in interface storage classes
 // requires special capability and extension: keep as-is when the capability
 // and extension is available.
 module attributes {
   spirv.target_env = #spirv.target_env<
     #spirv.vce<v1.0, [UniformAndStorageBuffer8BitAccess, StorageUniform16, Int64, Float64],
-             [SPV_KHR_8bit_storage, SPV_KHR_16bit_storage]>, #spirv.resource_limits<>>
+             [SPIRV_KHR_8bit_storage, SPIRV_KHR_16bit_storage]>, #spirv.resource_limits<>>
 } {
 
 // CHECK-LABEL: spirv.func @memref_8bit_Uniform
 // CHECK-SAME: !spirv.ptr<!spirv.struct<(!spirv.array<16 x i8, stride=1> [0])>, Uniform>
 // NOEMU-LABEL: spirv.func @memref_8bit_Uniform
 // NOEMU-SAME: !spirv.ptr<!spirv.struct<(!spirv.array<16 x i8, stride=1> [0])>, Uniform>
 func.func @memref_8bit_Uniform(%arg0: memref<16xi8, #spirv.storage_class<Uniform>>) { return }
 

 
 // -----
 
 // Check that using non-32-bit scalar types in interface storage classes
 // requires special capability and extension: keep as-is when the capability
 // and extension is available.
 module attributes {
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [StorageInputOutput16, Int64, Float64], [SPV_KHR_16bit_storage]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [StorageInputOutput16, Int64, Float64], [SPIRV_KHR_16bit_storage]>, #spirv.resource_limits<>>
 } {
 
 // CHECK-LABEL: spirv.func @memref_16bit_Input
 // CHECK-SAME: !spirv.ptr<!spirv.struct<(!spirv.array<16 x f16>)>, Input>
 // NOEMU-LABEL: spirv.func @memref_16bit_Input
 // NOEMU-SAME: !spirv.ptr<!spirv.struct<(!spirv.array<16 x f16>)>, Input>
 func.func @memref_16bit_Input(%arg3: memref<16xf16, #spirv.storage_class<Input>>) { return }
 

 
 } // end module
 
 // -----
 
 // Check that memref offset and strides affect the array size.
 module attributes {
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [StorageBuffer16BitAccess], [SPV_KHR_16bit_storage]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [StorageBuffer16BitAccess], [SPIRV_KHR_16bit_storage]>, #spirv.resource_limits<>>
 } {
 
 // CHECK-LABEL: spirv.func @memref_offset_strides
 func.func @memref_offset_strides(
 // CHECK-SAME: !spirv.array<64 x f32, stride=4> [0])>, StorageBuffer>
 // CHECK-SAME: !spirv.array<72 x f32, stride=4> [0])>, StorageBuffer>
 // CHECK-SAME: !spirv.array<256 x f32, stride=4> [0])>, StorageBuffer>
 // CHECK-SAME: !spirv.array<64 x f32, stride=4> [0])>, StorageBuffer>

mlir/test/Conversion/GPUToSPIRV/load-store.mlir

 // RUN: mlir-opt -convert-gpu-to-spirv %s -o - | FileCheck %s
 
 module attributes {
   gpu.container_module,
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
 } {
   func.func @load_store(%arg0: memref<12x4xf32, #spirv.storage_class<StorageBuffer>>, %arg1: memref<12x4xf32, #spirv.storage_class<StorageBuffer>>, %arg2: memref<12x4xf32, #spirv.storage_class<StorageBuffer>>) {
     %c0 = arith.constant 0 : index
     %c12 = arith.constant 12 : index
     %0 = arith.subi %c12, %c0 : index
     %c1 = arith.constant 1 : index
     %c0_0 = arith.constant 0 : index
     %c4 = arith.constant 4 : index

mlir/test/Conversion/GPUToVulkan/lower-gpu-launch-vulkan-launch.mlir

 // RUN: mlir-opt %s -convert-gpu-launch-to-vulkan-launch | FileCheck %s
 
 // CHECK: %[[resource:.*]] = memref.alloc() : memref<12xf32>
 // CHECK: %[[index:.*]] = arith.constant 1 : index
 // CHECK: call @vulkanLaunch(%[[index]], %[[index]], %[[index]], %[[resource]]) {spirv_blob = "{{.*}}", spirv_entry_point = "kernel"}
 
 module attributes {gpu.container_module} {
-  spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]> {
+  spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]> {
     spirv.GlobalVariable @kernel_arg_0 bind(0, 0) : !spirv.ptr<!spirv.struct<(!spirv.array<12 x f32, stride=4> [0])>, StorageBuffer>
     spirv.func @kernel() "None" attributes {workgroup_attributions = 0 : i64} {
       %0 = spirv.mlir.addressof @kernel_arg_0 : !spirv.ptr<!spirv.struct<(!spirv.array<12 x f32, stride=4> [0])>, StorageBuffer>
       %2 = spirv.Constant 0 : i32
       %3 = spirv.mlir.addressof @kernel_arg_0 : !spirv.ptr<!spirv.struct<(!spirv.array<12 x f32, stride=4> [0])>, StorageBuffer>
       %4 = spirv.AccessChain %0[%2, %2] : !spirv.ptr<!spirv.struct<(!spirv.array<12 x f32, stride=4> [0])>, StorageBuffer>, i32, i32
       %5 = spirv.Load "StorageBuffer" %4 : f32
       spirv.Return

mlir/test/Conversion/MemRefToSPIRV/alloc.mlir

 // RUN: mlir-opt -split-input-file -convert-memref-to-spirv -canonicalize -verify-diagnostics %s -o - | FileCheck %s
 
 module attributes {
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
   }
 {
   func.func @alloc_dealloc_workgroup_mem(%arg0 : index, %arg1 : index) {
     %0 = memref.alloc() : memref<4x5xf32, #spirv.storage_class<Workgroup>>
     %1 = memref.load %0[%arg0, %arg1] : memref<4x5xf32, #spirv.storage_class<Workgroup>>
     memref.store %1, %0[%arg0, %arg1] : memref<4x5xf32, #spirv.storage_class<Workgroup>>
     memref.dealloc %0 : memref<4x5xf32, #spirv.storage_class<Workgroup>>
     return
   }
 }
 //     CHECK: spirv.GlobalVariable @[[VAR:.+]] : !spirv.ptr<!spirv.struct<(!spirv.array<20 x f32>)>, Workgroup>
 //     CHECK: func @alloc_dealloc_workgroup_mem
 // CHECK-NOT:   memref.alloc
 //     CHECK:   %[[PTR:.+]] = spirv.mlir.addressof @[[VAR]]
 //     CHECK:   %[[LOADPTR:.+]] = spirv.AccessChain %[[PTR]]
 //     CHECK:   %[[VAL:.+]] = spirv.Load "Workgroup" %[[LOADPTR]] : f32
 //     CHECK:   %[[STOREPTR:.+]] = spirv.AccessChain %[[PTR]]
 //     CHECK:   spirv.Store "Workgroup" %[[STOREPTR]], %[[VAL]] : f32
 // CHECK-NOT:   memref.dealloc
 
 // -----
 
 module attributes {
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
   }
 {
   func.func @alloc_dealloc_workgroup_mem(%arg0 : index, %arg1 : index) {
     %0 = memref.alloc() : memref<4x5xi16, #spirv.storage_class<Workgroup>>
     %1 = memref.load %0[%arg0, %arg1] : memref<4x5xi16, #spirv.storage_class<Workgroup>>
     memref.store %1, %0[%arg0, %arg1] : memref<4x5xi16, #spirv.storage_class<Workgroup>>
     memref.dealloc %0 : memref<4x5xi16, #spirv.storage_class<Workgroup>>
     return

 //       CHECK:   %{{.+}} = spirv.AtomicAnd "Workgroup" "AcquireRelease" %[[PTR]], %{{.+}} : !spirv.ptr<i32, Workgroup>
 //       CHECK:   %{{.+}} = spirv.AtomicOr "Workgroup" "AcquireRelease" %[[PTR]], %{{.+}} : !spirv.ptr<i32, Workgroup>
 
 
 // -----
 
 module attributes {
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
   }
 {
   func.func @two_allocs() {
     %0 = memref.alloc() : memref<4x5xf32, #spirv.storage_class<Workgroup>>
     %1 = memref.alloc() : memref<2x3xi32, #spirv.storage_class<Workgroup>>
     return
   }
 }
 
 //  CHECK-DAG: spirv.GlobalVariable @__workgroup_mem__{{[0-9]+}}
 // CHECK-SAME:   !spirv.ptr<!spirv.struct<(!spirv.array<6 x i32>)>, Workgroup>
 //  CHECK-DAG: spirv.GlobalVariable @__workgroup_mem__{{[0-9]+}}
 // CHECK-SAME:   !spirv.ptr<!spirv.struct<(!spirv.array<20 x f32>)>, Workgroup>
 //      CHECK: func @two_allocs()
 
 // -----
 
 module attributes {
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
   }
 {
   func.func @two_allocs_vector() {
     %0 = memref.alloc() : memref<4xvector<4xf32>, #spirv.storage_class<Workgroup>>
     %1 = memref.alloc() : memref<2xvector<2xi32>, #spirv.storage_class<Workgroup>>
     return
   }
 }
 
 //  CHECK-DAG: spirv.GlobalVariable @__workgroup_mem__{{[0-9]+}}
 // CHECK-SAME:   !spirv.ptr<!spirv.struct<(!spirv.array<2 x vector<2xi32>>)>, Workgroup>
 //  CHECK-DAG: spirv.GlobalVariable @__workgroup_mem__{{[0-9]+}}
 // CHECK-SAME:   !spirv.ptr<!spirv.struct<(!spirv.array<4 x vector<4xf32>>)>, Workgroup>
 //      CHECK: func @two_allocs_vector()
 
 
 // -----
 
 module attributes {
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
   }
 {
   // CHECK-LABEL: func @alloc_dynamic_size
   func.func @alloc_dynamic_size(%arg0 : index) -> f32 {
     // CHECK: memref.alloc
     %0 = memref.alloc(%arg0) : memref<4x?xf32, #spirv.storage_class<Workgroup>>
     %1 = memref.load %0[%arg0, %arg0] : memref<4x?xf32, #spirv.storage_class<Workgroup>>
     return %1: f32
   }
 }
 
 // -----
 
 module attributes {
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
   }
 {
   // CHECK-LABEL: func @alloc_unsupported_memory_space
   func.func @alloc_unsupported_memory_space(%arg0: index) -> f32 {
     // CHECK: memref.alloc
     %0 = memref.alloc() : memref<4x5xf32, #spirv.storage_class<StorageBuffer>>
     %1 = memref.load %0[%arg0, %arg0] : memref<4x5xf32, #spirv.storage_class<StorageBuffer>>
     return %1: f32
   }
 }
 
 
 // -----
 
 module attributes {
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
   }
 {
   // CHECK-LABEL: func @dealloc_dynamic_size
   func.func @dealloc_dynamic_size(%arg0 : memref<4x?xf32, #spirv.storage_class<Workgroup>>) {
     // CHECK: memref.dealloc
     memref.dealloc %arg0 : memref<4x?xf32, #spirv.storage_class<Workgroup>>
     return
   }
 }
 
 // -----
 
 module attributes {
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
   }
 {
   // CHECK-LABEL: func @dealloc_unsupported_memory_space
   func.func @dealloc_unsupported_memory_space(%arg0 : memref<4x5xf32, #spirv.storage_class<StorageBuffer>>) {
     // CHECK: memref.dealloc
     memref.dealloc %arg0 : memref<4x5xf32, #spirv.storage_class<StorageBuffer>>
     return
   }
 }

mlir/test/Conversion/MemRefToSPIRV/memref-to-spirv.mlir

 // RUN: mlir-opt -split-input-file -convert-memref-to-spirv="bool-num-bits=8" %s -o - | FileCheck %s
 
 // Check that with proper compute and storage extensions, we don't need to
 // perform special tricks.
 
 module attributes {
   spirv.target_env = #spirv.target_env<
     #spirv.vce<v1.0,
       [
         Shader, Int8, Int16, Int64, Float16, Float64,
         StorageBuffer16BitAccess, StorageUniform16, StoragePushConstant16,
         StorageBuffer8BitAccess, UniformAndStorageBuffer8BitAccess, StoragePushConstant8
       ],
-      [SPV_KHR_16bit_storage, SPV_KHR_8bit_storage, SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+      [SPIRV_KHR_16bit_storage, SPIRV_KHR_8bit_storage, SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
 } {
 
 // CHECK-LABEL: @load_store_zero_rank_float
 func.func @load_store_zero_rank_float(%arg0: memref<f32, #spirv.storage_class<StorageBuffer>>, %arg1: memref<f32, #spirv.storage_class<StorageBuffer>>) {
   //      CHECK: [[ARG0:%.*]] = builtin.unrealized_conversion_cast {{.+}} : memref<f32, #spirv.storage_class<StorageBuffer>> to !spirv.ptr<!spirv.struct<(!spirv.array<1 x f32, stride=4> [0])>, StorageBuffer>
   //      CHECK: [[ARG1:%.*]] = builtin.unrealized_conversion_cast {{.+}} : memref<f32, #spirv.storage_class<StorageBuffer>> to !spirv.ptr<!spirv.struct<(!spirv.array<1 x f32, stride=4> [0])>, StorageBuffer>
   //      CHECK: [[ZERO1:%.*]] = spirv.Constant 0 : i32
   //      CHECK: spirv.AccessChain [[ARG0]][

 
 // -----
 
 // Check that access chain indices are properly adjusted if non-32-bit types are
 // emulated via 32-bit types.
 // TODO: Test i64 types.
 module attributes {
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
 } {
 
 // CHECK-LABEL: @load_i1
 func.func @load_i1(%arg0: memref<i1, #spirv.storage_class<StorageBuffer>>) -> i1 {
   //     CHECK: %[[ZERO:.+]] = spirv.Constant 0 : i32
   //     CHECK: %[[FOUR1:.+]] = spirv.Constant 4 : i32
   //     CHECK: %[[QUOTIENT:.+]] = spirv.SDiv %[[ZERO]], %[[FOUR1]] : i32
   //     CHECK: %[[PTR:.+]] = spirv.AccessChain %{{.+}}[%[[ZERO]], %[[QUOTIENT]]]

 
 // -----
 
 // Check that access chain indices are properly adjusted if non-16/32-bit types
 // are emulated via 32-bit types.
 module attributes {
   spirv.target_env = #spirv.target_env<
     #spirv.vce<v1.0, [Int16, StorageBuffer16BitAccess, Shader],
-    [SPV_KHR_storage_buffer_storage_class, SPV_KHR_16bit_storage]>, #spirv.resource_limits<>>
+    [SPIRV_KHR_storage_buffer_storage_class, SPIRV_KHR_16bit_storage]>, #spirv.resource_limits<>>
 } {
 
 // CHECK-LABEL: @load_i8
 func.func @load_i8(%arg0: memref<i8, #spirv.storage_class<StorageBuffer>>) {
   //     CHECK: %[[ZERO:.+]] = spirv.Constant 0 : i32
   //     CHECK: %[[FOUR1:.+]] = spirv.Constant 4 : i32
   //     CHECK: %[[QUOTIENT:.+]] = spirv.SDiv %[[ZERO]], %[[FOUR1]] : i32
   //     CHECK: %[[PTR:.+]] = spirv.AccessChain %{{.+}}[%[[ZERO]], %[[QUOTIENT]]]

mlir/test/Conversion/SCFToSPIRV/for.mlir

 // RUN: mlir-opt -convert-scf-to-spirv %s -o - | FileCheck %s
 
 module attributes {
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
 } {
 
 func.func @loop_kernel(%arg2 : memref<10xf32, #spirv.storage_class<StorageBuffer>>, %arg3 : memref<10xf32, #spirv.storage_class<StorageBuffer>>) {
   // CHECK: %[[LB:.*]] = spirv.Constant 4 : i32
   %lb = arith.constant 4 : index
   // CHECK: %[[UB:.*]] = spirv.Constant 42 : i32
   %ub = arith.constant 42 : index
   // CHECK: %[[STEP:.*]] = spirv.Constant 2 : i32

mlir/test/Conversion/SCFToSPIRV/if.mlir

 // RUN: mlir-opt -convert-scf-to-spirv %s -o - | FileCheck %s
 
 module attributes {
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
 } {
 
 // CHECK-LABEL: @kernel_simple_selection
 func.func @kernel_simple_selection(%arg2 : memref<10xf32, #spirv.storage_class<StorageBuffer>>, %arg3 : i1) {
   %value = arith.constant 0.0 : f32
   %i = arith.constant 0 : index
 
   // CHECK:       spirv.mlir.selection {

mlir/test/Conversion/SCFToSPIRV/while.mlir

 // RUN: mlir-opt -allow-unregistered-dialect -convert-scf-to-spirv %s -o - | FileCheck %s
 
 module attributes {
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader, Int64], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [Shader, Int64], [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
 } {
 
 // CHECK-LABEL: @while_loop1
 func.func @while_loop1(%arg0: i32, %arg1: i32) -> i32 {
   // CHECK-SAME: (%[[ARG1:.*]]: i32, %[[ARG2:.*]]: i32)
   // CHECK: %[[INITVAR:.*]] = spirv.Constant 2 : i32
   // CHECK: %[[VAR1:.*]] = spirv.Variable : !spirv.ptr<i32, Function>
   // CHECK: spirv.mlir.loop {

mlir/test/Conversion/SPIRVToLLVM/lower-host-to-llvm-calls.mlir

 // RUN: mlir-opt --lower-host-to-llvm %s | FileCheck %s
 
-module attributes {gpu.container_module, spirv.target_env = #spirv.target_env<#spirv.vce<v1.0, [Shader], [SPV_KHR_variable_pointers]>, #spirv.resource_limits<max_compute_workgroup_invocations = 128, max_compute_workgroup_size = [128, 128, 64]>>} {
+module attributes {gpu.container_module, spirv.target_env = #spirv.target_env<#spirv.vce<v1.0, [Shader], [SPIRV_KHR_variable_pointers]>, #spirv.resource_limits<max_compute_workgroup_invocations = 128, max_compute_workgroup_size = [128, 128, 64]>>} {
 
   //       CHECK: llvm.mlir.global linkonce @__spv__foo_bar_arg_0_descriptor_set0_binding0() {addr_space = 0 : i32} : !llvm.struct<(array<6 x i32>)>
   //       CHECK: llvm.func @__spv__foo_bar()
 
   //       CHECK: spirv.module @__spv__foo
   //       CHECK:   spirv.GlobalVariable @bar_arg_0 bind(0, 0) : !spirv.ptr<!spirv.struct<(!spirv.array<6 x i32, stride=4> [0])>, StorageBuffer>
   //       CHECK:   spirv.func @__spv__foo_bar
 
   //       CHECK:   spirv.EntryPoint "GLCompute" @__spv__foo_bar
   //       CHECK:   spirv.ExecutionMode @__spv__foo_bar "LocalSize", 1, 1, 1
 
   // CHECK-LABEL: @main
   //       CHECK:   %[[SRC:.*]] = llvm.extractvalue %{{.*}}[0] : !llvm.struct<(ptr<i32>, ptr<i32>, i64, array<1 x i64>, array<1 x i64>)>
   //  CHECK-NEXT:   %[[DEST:.*]] = llvm.mlir.addressof @__spv__foo_bar_arg_0_descriptor_set0_binding0 : !llvm.ptr<struct<(array<6 x i32>)>>
   //  CHECK-NEXT:   llvm.mlir.constant(false) : i1
   //  CHECK-NEXT:   "llvm.intr.memcpy"(%[[DEST]], %[[SRC]], %[[SIZE:.*]], %{{.*}}) : (!llvm.ptr<struct<(array<6 x i32>)>>, !llvm.ptr<i32>, i64, i1) -> ()
   //  CHECK-NEXT:   llvm.call @__spv__foo_bar() : () -> ()
   //  CHECK-NEXT:   llvm.mlir.constant(false) : i1
   //  CHECK-NEXT:   "llvm.intr.memcpy"(%[[SRC]], %[[DEST]], %[[SIZE]], %{{.*}}) : (!llvm.ptr<i32>, !llvm.ptr<struct<(array<6 x i32>)>>, i64, i1) -> ()
 
-  spirv.module @__spv__foo Logical GLSL450 requires #spirv.vce<v1.0, [Shader], [SPV_KHR_variable_pointers]> {
+  spirv.module @__spv__foo Logical GLSL450 requires #spirv.vce<v1.0, [Shader], [SPIRV_KHR_variable_pointers]> {
     spirv.GlobalVariable @bar_arg_0 bind(0, 0) : !spirv.ptr<!spirv.struct<(!spirv.array<6 x i32, stride=4> [0])>, StorageBuffer>
     spirv.func @bar() "None" attributes {workgroup_attributions = 0 : i64} {
       %0 = spirv.mlir.addressof @bar_arg_0 : !spirv.ptr<!spirv.struct<(!spirv.array<6 x i32, stride=4> [0])>, StorageBuffer>
       spirv.Return
     }
     spirv.EntryPoint "GLCompute" @bar
     spirv.ExecutionMode @bar "LocalSize", 1, 1, 1
   }

mlir/test/Conversion/SPIRVToLLVM/module-ops-to-llvm.mlir

 // RUN: mlir-opt -convert-spirv-to-llvm %s | FileCheck %s
 
 //===----------------------------------------------------------------------===//
 // spirv.module
 //===----------------------------------------------------------------------===//
 
 // CHECK: module
 spirv.module Logical GLSL450 {}
 
 // CHECK: module @foo
 spirv.module @foo Logical GLSL450 {}
 
 // CHECK: module
-spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader], [SPV_KHR_16bit_storage]> {}
+spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader], [SPIRV_KHR_16bit_storage]> {}
 
 // CHECK: module
 spirv.module Logical GLSL450 {
   // CHECK-LABEL: llvm.func @empty()
   spirv.func @empty() -> () "None" {
     // CHECK: llvm.return
     spirv.Return
   }
 }

mlir/test/Dialect/SPIRV/IR/availability.mlir

func.func @module_logical_glsl450() {
   spirv.module Logical GLSL450 { }
   return
 }
 
 // CHECK-LABEL: module_physical_storage_buffer64_vulkan
 func.func @module_physical_storage_buffer64_vulkan() {
   // CHECK: spirv.module min version: v1.0
   // CHECK: spirv.module max version: v1.6
-  // CHECK: spirv.module extensions: [ [SPV_EXT_physical_storage_buffer, SPV_KHR_physical_storage_buffer] [SPV_KHR_vulkan_memory_model] ]
+  // CHECK: spirv.module extensions: [ [SPIRV_EXT_physical_storage_buffer, SPIRV_KHR_physical_storage_buffer] [SPIRV_KHR_vulkan_memory_model] ]
   // CHECK: spirv.module capabilities: [ [PhysicalStorageBufferAddresses] [VulkanMemoryModel] ]
   spirv.module PhysicalStorageBuffer64 Vulkan { }
   return
 }

mlir/test/Dialect/SPIRV/IR/barrier-ops.mlir

 // RUN: mlir-opt -split-input-file -verify-diagnostics %s | FileCheck %s
 
 //===----------------------------------------------------------------------===//
 // spirv.ControlBarrier
 //===----------------------------------------------------------------------===//
 
 func.func @control_barrier_0() -> () {
   // CHECK: spirv.ControlBarrier <Workgroup>, <Device>, <Acquire|UniformMemory>
   spirv.ControlBarrier <Workgroup>, <Device>, <Acquire|UniformMemory>
   return
 }
 
 // -----
 
 func.func @control_barrier_1() -> () {
   // expected-error @+2 {{to be one of}}
-  // expected-error @+1 {{failed to parse SPV_ScopeAttr}}
+  // expected-error @+1 {{failed to parse SPIRV_ScopeAttr}}
   spirv.ControlBarrier <Something>, <Device>, <Acquire|UniformMemory>
   return
 }
 
 
 // -----
 
 //===----------------------------------------------------------------------===//

mlir/test/Dialect/SPIRV/IR/structure-ops.mlir

 // CHECK: spirv.module Logical GLSL450
 spirv.module Logical GLSL450 { }
 
 // Module with a name
 // CHECK: spirv.module @{{.*}} Logical GLSL450
 spirv.module @name Logical GLSL450 { }
 
 // Module with (version, capabilities, extensions) triple
-// CHECK: spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader], [SPV_KHR_16bit_storage]>
-spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader], [SPV_KHR_16bit_storage]> { }
+// CHECK: spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader], [SPIRV_KHR_16bit_storage]>
+spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader], [SPIRV_KHR_16bit_storage]> { }
 
 // Module with additional attributes
 // CHECK: spirv.module Logical GLSL450 attributes {foo = "bar"}
 spirv.module Logical GLSL450 attributes {foo = "bar"} { }
 
 // Module with VCE triple and additional attributes
-// CHECK: spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader], [SPV_KHR_16bit_storage]> attributes {foo = "bar"}
+// CHECK: spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader], [SPIRV_KHR_16bit_storage]> attributes {foo = "bar"}
 spirv.module Logical GLSL450
-  requires #spirv.vce<v1.0, [Shader], [SPV_KHR_16bit_storage]>
+  requires #spirv.vce<v1.0, [Shader], [SPIRV_KHR_16bit_storage]>
   attributes {foo = "bar"} { }
 
 // Module with function
 // CHECK: spirv.module
 spirv.module Logical GLSL450 {
   spirv.func @do_nothing() -> () "None" {
     spirv.Return
   }

mlir/test/Dialect/SPIRV/IR/target-and-abi.mlir

 // expected-error @+1 {{'spirv.entry_point_abi' attribute must be an entry point ABI attribute}}
 func.func @spv_entry_point() attributes {
   spirv.entry_point_abi = 64
 } { return }
 
 // -----
 
 func.func @spv_entry_point() attributes {
-  // expected-error @+2 {{failed to parse SPV_EntryPointABIAttr parameter 'local_size' which is to be a `DenseIntElementsAttr`}}
+  // expected-error @+2 {{failed to parse SPIRV_EntryPointABIAttr parameter 'local_size' which is to be a `DenseIntElementsAttr`}}
   // expected-error @+1 {{invalid kind of attribute specified}}
   spirv.entry_point_abi = #spirv.entry_point_abi<local_size = 64>
 } { return }
 
 // -----
 
 func.func @spv_entry_point() attributes {
   // CHECK: {spirv.entry_point_abi = #spirv.entry_point_abi<local_size = dense<[64, 1, 1]> : vector<3xi32>>}

 // -----
 
 //===----------------------------------------------------------------------===//
 // spirv.target_env
 //===----------------------------------------------------------------------===//
 
 func.func @target_env() attributes {
   // CHECK:      spirv.target_env = #spirv.target_env<
-  // CHECK-SAME:   #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>,
+  // CHECK-SAME:   #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>,
   // CHECK-SAME:   #spirv.resource_limits<max_compute_workgroup_size = [128, 64, 64]>>
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>,
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>,
     #spirv.resource_limits<
       max_compute_workgroup_size = [128, 64, 64]
     >>
 } { return }
 
 // -----
 
 func.func @target_env_vendor_id() attributes {
func.func @target_env_vendor_id_device_type_device_id() attributes {
   spirv.target_env = #spirv.target_env<#spirv.vce<v1.0, [], []>, Qualcomm:IntegratedGPU:0x6040001, #spirv.resource_limits<>>
 } { return }
 
 // -----
 
 func.func @target_env_extra_fields() attributes {
   // expected-error @+3 {{expected '>'}}
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>,
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>,
     #spirv.resource_limits<>,
     more_stuff
   >
 } { return }
 
 // -----
 
 func.func @target_env_cooperative_matrix() attributes{
   // CHECK:      spirv.target_env = #spirv.target_env<
-  // CHECK-SAME:   SPV_NV_cooperative_matrix
+  // CHECK-SAME:   SPIRV_NV_cooperative_matrix
   // CHECK-SAME: #spirv.coop_matrix_props<
   // CHECK-SAME:   m_size = 8, n_size = 8, k_size = 32,
   // CHECK-SAME:   a_type = i8, b_type = i8, c_type = i32,
   // CHECK-SAME:   result_type = i32, scope = <Subgroup>>
   // CHECK-SAME: #spirv.coop_matrix_props<
   // CHECK-SAME:   m_size = 8, n_size = 8, k_size = 16,
   // CHECK-SAME:   a_type = f16, b_type = f16, c_type = f16,
   // CHECK-SAME:   result_type = f16, scope = <Subgroup>>
   spirv.target_env = #spirv.target_env<
-  #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class,
-                            SPV_NV_cooperative_matrix]>,
+  #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class,
+                            SPIRV_NV_cooperative_matrix]>,
   #spirv.resource_limits<
     cooperative_matrix_properties_nv = [#spirv.coop_matrix_props<
       m_size = 8,
       n_size = 8,
       k_size = 32,
       a_type = i8,
       b_type = i8,
       c_type = i32,

 func.func @vce_wrong_extension_type() attributes {
   // expected-error @+1 {{expected valid keyword}}
   vce = #spirv.vce<v1.0, [32: i32], [Shader]>
 } { return }
 
 // -----
 
 func.func @vce_wrong_extension() attributes {
-  // expected-error @+1 {{unknown extension: SPV_Something}}
-  vce = #spirv.vce<v1.0, [Shader], [SPV_Something]>
+  // expected-error @+1 {{unknown extension: SPIRV_Something}}
+  vce = #spirv.vce<v1.0, [Shader], [SPIRV_Something]>
 } { return }
 
 // -----
 
 func.func @vce_wrong_capability() attributes {
   // expected-error @+1 {{unknown capability: Something}}
   vce = #spirv.vce<v1.0, [Something], []>
 } { return }
 
 // -----
 
 func.func @vce() attributes {
-  // CHECK: #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>
-  vce = #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>
+  // CHECK: #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>
+  vce = #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>
 } { return }

mlir/test/Dialect/SPIRV/IR/target-env.mlir

 // AtomicStorage capability.
 
 // spirv.BitReverse is available in all SPIR-V versions under Shader capability.
 
 // spirv.GroupNonUniformBallot is available starting from SPIR-V 1.3 under
 // GroupNonUniform capability.
 
 // spirv.KHR.SubgroupBallot is available under in all SPIR-V versions under
-// SubgroupBallotKHR capability and SPV_KHR_shader_ballot extension.
+// SubgroupBallotKHR capability and SPIRV_KHR_shader_ballot extension.
 
 // The GeometryPointSize capability implies the Geometry capability, which
 // implies the Shader capability.
 
 // PhysicalStorageBuffer64 addressing model is available via extension
-// SPV_EXT_physical_storage_buffer or SPV_KHR_physical_storage_buffer;
+// SPIRV_EXT_physical_storage_buffer or SPIRV_KHR_physical_storage_buffer;
 // both extensions are incorporated into SPIR-V 1.5.
 
-// Vulkan memory model is available via extension SPV_KHR_vulkan_memory_model,
+// Vulkan memory model is available via extension SPIRV_KHR_vulkan_memory_model,
 // which extensions are incorporated into SPIR-V 1.5.
 
 //===----------------------------------------------------------------------===//
 // MaxVersion
 //===----------------------------------------------------------------------===//
 
 // CHECK-LABEL: @cmp_exchange_weak_suitable_version_capabilities
 func.func @cmp_exchange_weak_suitable_version_capabilities(%ptr: !spirv.ptr<i32, Workgroup>, %value: i32, %comparator: i32) -> i32 attributes {

 } {
   // CHECK: test.convert_to_atomic_compare_exchange_weak_op
   %0 = "test.convert_to_atomic_compare_exchange_weak_op"(%ptr, %value, %comparator): (!spirv.ptr<i32, Workgroup>, i32, i32) -> (i32)
   return %0: i32
 }
 
 // CHECK-LABEL: @subgroup_ballot_missing_capability
 func.func @subgroup_ballot_missing_capability(%predicate: i1) -> vector<4xi32> attributes {
-  spirv.target_env = #spirv.target_env<#spirv.vce<v1.4, [], [SPV_KHR_shader_ballot]>, #spirv.resource_limits<>>
+  spirv.target_env = #spirv.target_env<#spirv.vce<v1.4, [], [SPIRV_KHR_shader_ballot]>, #spirv.resource_limits<>>
 } {
   // CHECK: test.convert_to_subgroup_ballot_op
   %0 = "test.convert_to_subgroup_ballot_op"(%predicate): (i1) -> (vector<4xi32>)
   return %0: vector<4xi32>
 }
 
 // CHECK-LABEL: @bit_reverse_directly_implied_capability
 func.func @bit_reverse_directly_implied_capability(%operand: i32) -> i32 attributes {

 }
 
 //===----------------------------------------------------------------------===//
 // Extension
 //===----------------------------------------------------------------------===//
 
 // CHECK-LABEL: @subgroup_ballot_suitable_extension
 func.func @subgroup_ballot_suitable_extension(%predicate: i1) -> vector<4xi32> attributes {
-  spirv.target_env = #spirv.target_env<#spirv.vce<v1.4, [SubgroupBallotKHR], [SPV_KHR_shader_ballot]>, #spirv.resource_limits<>>
+  spirv.target_env = #spirv.target_env<#spirv.vce<v1.4, [SubgroupBallotKHR], [SPIRV_KHR_shader_ballot]>, #spirv.resource_limits<>>
 } {
   // CHECK: spirv.KHR.SubgroupBallot
   %0 = "test.convert_to_subgroup_ballot_op"(%predicate): (i1) -> (vector<4xi32>)
   return %0: vector<4xi32>
 }
 
 // CHECK-LABEL: @subgroup_ballot_missing_extension
 func.func @subgroup_ballot_missing_extension(%predicate: i1) -> vector<4xi32> attributes {
   spirv.target_env = #spirv.target_env<#spirv.vce<v1.4, [SubgroupBallotKHR], []>, #spirv.resource_limits<>>
 } {
   // CHECK: test.convert_to_subgroup_ballot_op
   %0 = "test.convert_to_subgroup_ballot_op"(%predicate): (i1) -> (vector<4xi32>)
   return %0: vector<4xi32>
 }
 
 // CHECK-LABEL: @module_suitable_extension1
 func.func @module_suitable_extension1() attributes {
-  spirv.target_env = #spirv.target_env<#spirv.vce<v1.0, [VulkanMemoryModel, PhysicalStorageBufferAddresses], [SPV_KHR_vulkan_memory_model, SPV_EXT_physical_storage_buffer]>, #spirv.resource_limits<>>
+  spirv.target_env = #spirv.target_env<#spirv.vce<v1.0, [VulkanMemoryModel, PhysicalStorageBufferAddresses], [SPIRV_KHR_vulkan_memory_model, SPIRV_EXT_physical_storage_buffer]>, #spirv.resource_limits<>>
 } {
   // CHECK: spirv.module PhysicalStorageBuffer64 Vulkan
   "test.convert_to_module_op"() : () ->()
   return
 }
 
 // CHECK-LABEL: @module_suitable_extension2
 func.func @module_suitable_extension2() attributes {
-  spirv.target_env = #spirv.target_env<#spirv.vce<v1.0, [VulkanMemoryModel, PhysicalStorageBufferAddresses], [SPV_KHR_vulkan_memory_model, SPV_KHR_physical_storage_buffer]>, #spirv.resource_limits<>>
+  spirv.target_env = #spirv.target_env<#spirv.vce<v1.0, [VulkanMemoryModel, PhysicalStorageBufferAddresses], [SPIRV_KHR_vulkan_memory_model, SPIRV_KHR_physical_storage_buffer]>, #spirv.resource_limits<>>
 } {
   // CHECK: spirv.module PhysicalStorageBuffer64 Vulkan
   "test.convert_to_module_op"() : () -> ()
   return
 }
 
 // CHECK-LABEL: @module_missing_extension_mm
 func.func @module_missing_extension_mm() attributes {
-  spirv.target_env = #spirv.target_env<#spirv.vce<v1.0, [VulkanMemoryModel, PhysicalStorageBufferAddresses], [SPV_KHR_physical_storage_buffer]>, #spirv.resource_limits<>>
+  spirv.target_env = #spirv.target_env<#spirv.vce<v1.0, [VulkanMemoryModel, PhysicalStorageBufferAddresses], [SPIRV_KHR_physical_storage_buffer]>, #spirv.resource_limits<>>
 } {
   // CHECK: test.convert_to_module_op
   "test.convert_to_module_op"() : () -> ()
   return
 }
 
 // CHECK-LABEL: @module_missing_extension_am
 func.func @module_missing_extension_am() attributes {
-  spirv.target_env = #spirv.target_env<#spirv.vce<v1.0, [VulkanMemoryModel, PhysicalStorageBufferAddresses], [SPV_KHR_vulkan_memory_model]>, #spirv.resource_limits<>>
+  spirv.target_env = #spirv.target_env<#spirv.vce<v1.0, [VulkanMemoryModel, PhysicalStorageBufferAddresses], [SPIRV_KHR_vulkan_memory_model]>, #spirv.resource_limits<>>
 } {
   // CHECK: test.convert_to_module_op
   "test.convert_to_module_op"() : () -> ()
   return
 }
 
 // CHECK-LABEL: @module_implied_extension
 func.func @module_implied_extension() attributes {
-  // Version 1.5 implies SPV_KHR_vulkan_memory_model and SPV_KHR_physical_storage_buffer.
+  // Version 1.5 implies SPIRV_KHR_vulkan_memory_model and SPIRV_KHR_physical_storage_buffer.
   spirv.target_env = #spirv.target_env<#spirv.vce<v1.5, [VulkanMemoryModel, PhysicalStorageBufferAddresses], []>, #spirv.resource_limits<>>
 } {
   // CHECK: spirv.module PhysicalStorageBuffer64 Vulkan
   "test.convert_to_module_op"() : () -> ()
   return
 }

mlir/test/Dialect/SPIRV/Linking/ModuleCombiner/basic.mlir

 
 // -----
 
 module {
 spirv.module Logical GLSL450 {
 }
 
 // expected-error @+1 {{input modules differ in addressing model, memory model, and/or VCE triple}}
-spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]> {
+spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]> {
 }
 }
 

mlir/test/Dialect/SPIRV/Transforms/abi-interface.mlir

 // RUN: mlir-opt -spirv-lower-abi-attrs -verify-diagnostics %s -o - | FileCheck %s
 
 module attributes {
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
 } {
 
 // CHECK-LABEL: spirv.module
 spirv.module Logical GLSL450 {
   // CHECK-DAG:    spirv.GlobalVariable [[VAR0:@.*]] bind(0, 0) : !spirv.ptr<!spirv.struct<(f32 [0])>, StorageBuffer>
   // CHECK-DAG:    spirv.GlobalVariable [[VAR1:@.*]] bind(0, 1) : !spirv.ptr<!spirv.struct<(!spirv.array<12 x f32, stride=4> [0])>, StorageBuffer>
   // CHECK:    spirv.func [[FN:@.*]]()
   spirv.func @kernel(

mlir/test/Dialect/SPIRV/Transforms/abi-load-store.mlir

 // RUN: mlir-opt -spirv-lower-abi-attrs -verify-diagnostics %s -o - | FileCheck %s
 
 module attributes {
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
 } {
 
 // CHECK-LABEL: spirv.module
 spirv.module Logical GLSL450 {
   // CHECK-DAG: spirv.GlobalVariable [[WORKGROUPSIZE:@.*]] built_in("WorkgroupSize")
   spirv.GlobalVariable @__builtin_var_WorkgroupSize__ built_in("WorkgroupSize") : !spirv.ptr<vector<3xi32>, Input>
   // CHECK-DAG: spirv.GlobalVariable [[NUMWORKGROUPS:@.*]] built_in("NumWorkgroups")
   spirv.GlobalVariable @__builtin_var_NumWorkgroups__ built_in("NumWorkgroups") : !spirv.ptr<vector<3xi32>, Input>

mlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir

spirv.module Logical GLSL450 attributes {
   spirv.func @iadd(%val : i32) -> i32 "None" {
     %0 = spirv.IAdd %val, %val: i32
     spirv.ReturnValue %0: i32
   }
 }
 
 // Test Physical Storage Buffers are deduced correctly.
 
-// CHECK: spirv.module PhysicalStorageBuffer64 GLSL450 requires #spirv.vce<v1.0, [PhysicalStorageBufferAddresses, Shader], [SPV_EXT_physical_storage_buffer]>
+// CHECK: spirv.module PhysicalStorageBuffer64 GLSL450 requires #spirv.vce<v1.0, [PhysicalStorageBufferAddresses, Shader], [SPIRV_EXT_physical_storage_buffer]>
 spirv.module PhysicalStorageBuffer64 GLSL450 attributes {
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader, PhysicalStorageBufferAddresses], [SPV_EXT_physical_storage_buffer]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [Shader, PhysicalStorageBufferAddresses], [SPIRV_EXT_physical_storage_buffer]>, #spirv.resource_limits<>>
 } {
   spirv.func @physical_ptr(%val : !spirv.ptr<f32, PhysicalStorageBuffer>) "None" {
     spirv.Return
   }
 }
 
 // Test deducing implied capability.
 // AtomicStorage implies Shader.
spirv.module Logical GLSL450 attributes {
   }
 }
 
 //===----------------------------------------------------------------------===//
 // Extension
 //===----------------------------------------------------------------------===//
 
 // Test deducing minimal extensions.
-// spirv.KHR.SubgroupBallot requires the SPV_KHR_shader_ballot extension.
+// spirv.KHR.SubgroupBallot requires the SPIRV_KHR_shader_ballot extension.
 
-// CHECK: requires #spirv.vce<v1.0, [SubgroupBallotKHR, Shader], [SPV_KHR_shader_ballot]>
+// CHECK: requires #spirv.vce<v1.0, [SubgroupBallotKHR, Shader], [SPIRV_KHR_shader_ballot]>
 spirv.module Logical GLSL450 attributes {
   spirv.target_env = #spirv.target_env<
     #spirv.vce<v1.0, [Shader, SubgroupBallotKHR],
-             [SPV_KHR_shader_ballot, SPV_KHR_shader_clock, SPV_KHR_variable_pointers]>, #spirv.resource_limits<>>
+             [SPIRV_KHR_shader_ballot, SPIRV_KHR_shader_clock, SPIRV_KHR_variable_pointers]>, #spirv.resource_limits<>>
 } {
   spirv.func @subgroup_ballot(%predicate : i1) -> vector<4xi32> "None" {
     %0 = spirv.KHR.SubgroupBallot %predicate: vector<4xi32>
     spirv.ReturnValue %0: vector<4xi32>
   }
 }
 
 // Test deducing implied extension.
-// Vulkan memory model requires SPV_KHR_vulkan_memory_model, which is enabled
+// Vulkan memory model requires SPIRV_KHR_vulkan_memory_model, which is enabled
 // implicitly by v1.5.
 
-// CHECK: requires #spirv.vce<v1.0, [VulkanMemoryModel], [SPV_KHR_vulkan_memory_model]>
+// CHECK: requires #spirv.vce<v1.0, [VulkanMemoryModel], [SPIRV_KHR_vulkan_memory_model]>
 spirv.module Logical Vulkan attributes {
   spirv.target_env = #spirv.target_env<
     #spirv.vce<v1.5, [Shader, VulkanMemoryModel], []>, #spirv.resource_limits<>>
 } {
   spirv.func @iadd(%val : i32) -> i32 "None" {
     %0 = spirv.IAdd %val, %val: i32
     spirv.ReturnValue %0: i32
   }
 }
 
 // Test type required extensions
 
 // Using 8-bit integers in interface storage class requires additional
 // extensions and capabilities.
-// CHECK: requires #spirv.vce<v1.0, [StorageBuffer16BitAccess, Shader, Int16], [SPV_KHR_16bit_storage, SPV_KHR_storage_buffer_storage_class]>
+// CHECK: requires #spirv.vce<v1.0, [StorageBuffer16BitAccess, Shader, Int16], [SPIRV_KHR_16bit_storage, SPIRV_KHR_storage_buffer_storage_class]>
 spirv.module Logical GLSL450 attributes {
   spirv.target_env = #spirv.target_env<
     #spirv.vce<v1.3, [Shader, StorageBuffer16BitAccess, Int16], []>, #spirv.resource_limits<>>
 } {
   spirv.func @iadd_storage_buffer(%ptr : !spirv.ptr<i16, StorageBuffer>) -> i16 "None" {
     %0 = spirv.Load "StorageBuffer" %ptr : i16
     %1 = spirv.IAdd %0, %0 : i16
     spirv.ReturnValue %1: i16
   }
 }
 
 // Complicated nested types
 // * Buffer requires ImageBuffer or SampledBuffer.
 // * Rg32f requires StorageImageExtendedFormats.
-// CHECK: requires #spirv.vce<v1.0, [UniformAndStorageBuffer8BitAccess, StorageUniform16, Int64, Shader, ImageBuffer, StorageImageExtendedFormats], [SPV_KHR_8bit_storage, SPV_KHR_16bit_storage]>
+// CHECK: requires #spirv.vce<v1.0, [UniformAndStorageBuffer8BitAccess, StorageUniform16, Int64, Shader, ImageBuffer, StorageImageExtendedFormats], [SPIRV_KHR_8bit_storage, SPIRV_KHR_16bit_storage]>
 spirv.module Logical GLSL450 attributes {
   spirv.target_env = #spirv.target_env<
     #spirv.vce<v1.5, [Shader, UniformAndStorageBuffer8BitAccess, StorageBuffer16BitAccess, StorageUniform16, Int16, Int64, ImageBuffer, StorageImageExtendedFormats], []>,
     #spirv.resource_limits<>>
 } {
   spirv.GlobalVariable @data : !spirv.ptr<!spirv.struct<(i8 [0], f16 [2], i64 [4])>, Uniform>
   spirv.GlobalVariable @img  : !spirv.ptr<!spirv.image<f32, Buffer, NoDepth, NonArrayed, SingleSampled, SamplerUnknown, Rg32f>, UniformConstant>
 }

mlir/test/Target/SPIRV/cooperative-matrix-ops.mlir

 // RUN: mlir-translate -test-spirv-roundtrip -split-input-file %s | FileCheck %s
 
-spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [CooperativeMatrixNV], [SPV_NV_cooperative_matrix]> {
+spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [CooperativeMatrixNV], [SPIRV_NV_cooperative_matrix]> {
   // CHECK-LABEL: @cooperative_matrix_load
   spirv.func @cooperative_matrix_load(%ptr : !spirv.ptr<i32, StorageBuffer>, %stride : i32, %b : i1) "None" {
     // CHECK: {{%.*}} = spirv.NV.CooperativeMatrixLoad {{%.*}}, {{%.*}}, {{%.*}} : !spirv.ptr<i32, StorageBuffer> as !spirv.coopmatrix<16x8xi32, Workgroup>
     %0 = spirv.NV.CooperativeMatrixLoad %ptr, %stride, %b : !spirv.ptr<i32, StorageBuffer> as !spirv.coopmatrix<16x8xi32, Workgroup>
     spirv.Return
   }
 
   // CHECK-LABEL: @cooperative_matrix_load_memaccess

mlir/test/Target/SPIRV/joint-matrix-ops.mlir

 // RUN: mlir-translate -test-spirv-roundtrip -split-input-file %s | FileCheck %s
 
-spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [JointMatrixINTEL], [SPV_INTEL_joint_matrix]> {
+spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [JointMatrixINTEL], [SPIRV_INTEL_joint_matrix]> {
   // CHECK-LABEL: @joint_matrix_load
   spirv.func @joint_matrix_load(%ptr : !spirv.ptr<i32, Workgroup>, %stride : i32) "None" {
     // CHECK: {{%.*}} = spirv.INTEL.JointMatrixLoad <Subgroup> <RowMajor> {{%.*}}, {{%.*}} : (!spirv.ptr<i32, Workgroup>, i32) -> !spirv.jointmatrix<16x8xi32, RowMajor, Workgroup>
     %0 = spirv.INTEL.JointMatrixLoad <Subgroup> <RowMajor> %ptr, %stride : (!spirv.ptr<i32, Workgroup>, i32) -> !spirv.jointmatrix<16x8xi32, RowMajor, Workgroup>
     spirv.Return
   }
 
   // CHECK-LABEL: @joint_matrix_load_memaccess

mlir/test/Target/SPIRV/module.mlir

 // -----
 
 // CHECK: [Shader, Float16]
 spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader, Float16], []> {
 }
 
 // -----
 
-// CHECK: [SPV_KHR_float_controls, SPV_KHR_subgroup_vote]
-spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader], [SPV_KHR_float_controls, SPV_KHR_subgroup_vote]> {
+// CHECK: [SPIRV_KHR_float_controls, SPIRV_KHR_subgroup_vote]
+spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader], [SPIRV_KHR_float_controls, SPIRV_KHR_subgroup_vote]> {
 }
 

mlir/test/mlir-spirv-cpu-runner/double.mlir

 // RUN: mlir-spirv-cpu-runner %s -e main --entry-point-result=void --shared-libs=%mlir_lib_dir/libmlir_runner_utils%shlibext,%mlir_lib_dir/libmlir_test_spirv_cpu_runner_c_wrappers%shlibext
 
 // CHECK: [8,  8,  8,  8,  8,  8]
 module attributes {
   gpu.container_module,
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_variable_pointers]>,
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_variable_pointers]>,
     #spirv.resource_limits<
      max_compute_workgroup_invocations = 128,
      max_compute_workgroup_size = [128, 128, 64]>>
 } {
   gpu.module @kernels {
     gpu.func @double(%arg0 : memref<6xi32>, %arg1 : memref<6xi32>)
       kernel attributes { spirv.entry_point_abi = #spirv.entry_point_abi<local_size = dense<[1, 1, 1]>: vector<3xi32>>} {
       %factor = arith.constant 2 : i32

mlir/test/mlir-spirv-cpu-runner/simple_add.mlir

 // RUN: mlir-spirv-cpu-runner %s -e main --entry-point-result=void --shared-libs=%mlir_lib_dir/libmlir_runner_utils%shlibext,%mlir_lib_dir/libmlir_test_spirv_cpu_runner_c_wrappers%shlibext
 
 // CHECK: [[[7.7,    0,    0], [7.7,    0,    0], [7.7,    0,    0]], [[0,    7.7,    0], [0,    7.7,    0], [0,    7.7,    0]], [[0,    0,    7.7], [0,    0,    7.7], [0,    0,    7.7]]]
 module attributes {
   gpu.container_module,
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class, SPV_KHR_8bit_storage]>,
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class, SPIRV_KHR_8bit_storage]>,
     #spirv.resource_limits<
      max_compute_workgroup_invocations = 128,
      max_compute_workgroup_size = [128, 128, 64]>>
 } {
   gpu.module @kernels {
     gpu.func @sum(%arg0 : memref<3xf32>, %arg1 : memref<3x3xf32>, %arg2 :  memref<3x3x3xf32>)
       kernel attributes { spirv.entry_point_abi = #spirv.entry_point_abi<local_size = dense<[1, 1, 1]>: vector<3xi32>>} {
       %i0 = arith.constant 0 : index

mlir/test/mlir-vulkan-runner/addf.mlir

 // RUN: mlir-vulkan-runner %s --shared-libs=%mlir_lib_dir/libvulkan-runtime-wrappers%shlibext,%mlir_lib_dir/libmlir_runner_utils%shlibext --entry-point-result=void | FileCheck %s
 
 // CHECK: [3.3,  3.3,  3.3,  3.3,  3.3,  3.3,  3.3,  3.3]
 module attributes {
   gpu.container_module,
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
 } {
   gpu.module @kernels {
     gpu.func @kernel_add(%arg0 : memref<8xf32>, %arg1 : memref<8xf32>, %arg2 : memref<8xf32>)
       kernel attributes { spirv.entry_point_abi = #spirv.entry_point_abi<local_size = dense<[1, 1, 1]>: vector<3xi32>>} {
       %0 = gpu.block_id x
       %1 = memref.load %arg0[%0] : memref<8xf32>
       %2 = memref.load %arg1[%0] : memref<8xf32>
       %3 = arith.addf %1, %2 : f32

mlir/test/mlir-vulkan-runner/addi.mlir

 // RUN: mlir-vulkan-runner %s --shared-libs=%mlir_lib_dir/libvulkan-runtime-wrappers%shlibext,%mlir_lib_dir/libmlir_runner_utils%shlibext --entry-point-result=void | FileCheck %s
 
 // CHECK-COUNT-64: [3, 3, 3, 3, 3, 3, 3, 3]
 module attributes {
   gpu.container_module,
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
 } {
   gpu.module @kernels {
     gpu.func @kernel_addi(%arg0 : memref<8xi32>, %arg1 : memref<8x8xi32>, %arg2 : memref<8x8x8xi32>)
       kernel attributes { spirv.entry_point_abi = #spirv.entry_point_abi<local_size = dense<[1, 1, 1]>: vector<3xi32>>} {
       %x = gpu.block_id x
       %y = gpu.block_id y
       %z = gpu.block_id z
       %0 = memref.load %arg0[%x] : memref<8xi32>

mlir/test/mlir-vulkan-runner/addi8.mlir

 // RUN: mlir-vulkan-runner %s --shared-libs=%mlir_lib_dir/libvulkan-runtime-wrappers%shlibext,%mlir_lib_dir/libmlir_runner_utils%shlibext --entry-point-result=void | FileCheck %s
 
 // CHECK-COUNT-64: [3, 3, 3, 3, 3, 3, 3, 3]
 module attributes {
   gpu.container_module,
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class, SPV_KHR_8bit_storage]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class, SPIRV_KHR_8bit_storage]>, #spirv.resource_limits<>>
 } {
   gpu.module @kernels {
     gpu.func @kernel_addi(%arg0 : memref<8xi8>, %arg1 : memref<8x8xi8>, %arg2 : memref<8x8x8xi32>)
       kernel attributes { spirv.entry_point_abi = #spirv.entry_point_abi<local_size = dense<[1, 1, 1]>: vector<3xi32>>} {
       %x = gpu.block_id x
       %y = gpu.block_id y
       %z = gpu.block_id z
       %0 = memref.load %arg0[%x] : memref<8xi8>

mlir/test/mlir-vulkan-runner/mulf.mlir

 // RUN: mlir-vulkan-runner %s --shared-libs=%mlir_lib_dir/libvulkan-runtime-wrappers%shlibext,%mlir_lib_dir/libmlir_runner_utils%shlibext --entry-point-result=void | FileCheck %s
 
 // CHECK-COUNT-4: [6, 6, 6, 6]
 module attributes {
   gpu.container_module,
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
 } {
   gpu.module @kernels {
     gpu.func @kernel_mul(%arg0 : memref<4x4xf32>, %arg1 : memref<4x4xf32>, %arg2 : memref<4x4xf32>)
       kernel attributes { spirv.entry_point_abi = #spirv.entry_point_abi<local_size = dense<[1, 1, 1]>: vector<3xi32>>} {
       %x = gpu.block_id x
       %y = gpu.block_id y
       %1 = memref.load %arg0[%x, %y] : memref<4x4xf32>
       %2 = memref.load %arg1[%x, %y] : memref<4x4xf32>

mlir/test/mlir-vulkan-runner/subf.mlir

 // RUN: mlir-vulkan-runner %s --shared-libs=%mlir_lib_dir/libvulkan-runtime-wrappers%shlibext,%mlir_lib_dir/libmlir_runner_utils%shlibext --entry-point-result=void | FileCheck %s
 
 // CHECK-COUNT-32: [2.2, 2.2, 2.2, 2.2]
 module attributes {
   gpu.container_module,
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, 
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>, 
     #spirv.resource_limits<>>
 } {
   gpu.module @kernels {
     gpu.func @kernel_sub(%arg0 : memref<8x4x4xf32>, %arg1 : memref<4x4xf32>, %arg2 : memref<8x4x4xf32>)
       kernel attributes { spirv.entry_point_abi = #spirv.entry_point_abi<local_size = dense<[1, 1, 1]>: vector<3xi32>>} {
       %x = gpu.block_id x
       %y = gpu.block_id y
       %z = gpu.block_id z

mlir/test/mlir-vulkan-runner/time.mlir

 // RUN: mlir-vulkan-runner %s --shared-libs=%mlir_lib_dir/libvulkan-runtime-wrappers%shlibext,%mlir_lib_dir/libmlir_runner_utils%shlibext --entry-point-result=void | FileCheck %s
 
 // CHECK: Compute shader execution time
 // CHECK: Command buffer submit time
 // CHECK: Wait idle time
 
 module attributes {
   gpu.container_module,
   spirv.target_env = #spirv.target_env<
-    #spirv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
+    #spirv.vce<v1.0, [Shader], [SPIRV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>
 } {
   gpu.module @kernels {
     gpu.func @kernel_add(%arg0 : memref<16384xf32>, %arg1 : memref<16384xf32>, %arg2 : memref<16384xf32>)
       kernel attributes { spirv.entry_point_abi = #spirv.entry_point_abi<local_size = dense<[128, 1, 1]>: vector<3xi32>>} {
       %bid = gpu.block_id x
       %tid = gpu.thread_id x
       %cst = arith.constant 128 : index
       %b = arith.muli %bid, %cst : index

mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp

genEnumDefs("gen-spirv-enum-avail-defs",
                 [](const RecordKeeper &records, raw_ostream &os) {
                   return emitEnumDefs(records, os);
                 });
 
 //===----------------------------------------------------------------------===//
 // Serialization AutoGen
 //===----------------------------------------------------------------------===//
 
-/// Generates code to serialize attributes of a SPV_Op `op` into `os`. The
+/// Generates code to serialize attributes of a SPIRV_Op `op` into `os`. The
 /// generates code extracts the attribute with name `attrName` from
 /// `operandList` of `op`.
 static void emitAttributeSerialization(const Attribute &attr,
                                        ArrayRef<SMLoc> loc, StringRef tabs,
                                        StringRef opVar, StringRef operandList,
                                        StringRef attrName, raw_ostream &os) {
   os << tabs
      << formatv("if (auto attr = {0}->getAttr(\"{1}\")) {{\n", opVar, attrName);
-  if (attr.getAttrDefName() == "SPV_ScopeAttr" ||
-      attr.getAttrDefName() == "SPV_MemorySemanticsAttr" ||
-      attr.getAttrDefName() == "SPV_MatrixLayoutAttr") {
+  if (attr.getAttrDefName() == "SPIRV_ScopeAttr" ||
+      attr.getAttrDefName() == "SPIRV_MemorySemanticsAttr" ||
+      attr.getAttrDefName() == "SPIRV_MatrixLayoutAttr") {
     // These two enums are encoded as <id> to constant values in SPIR-V blob,
     // but we directly use the constant value as attribute in SPIR-V dialect. So
     // need to handle them separately from normal enum attributes.
     EnumAttr baseEnum(attr.getDef().getValueAsDef("enum"));
     os << tabs
        << formatv("  {0}.push_back(prepareConstantInt({1}.getLoc(), "
                   "Builder({1}).getI32IntegerAttr(static_cast<uint32_t>("
                   "attr.cast<{2}::{3}Attr>().getValue()))));\n",
                   operandList, opVar, baseEnum.getCppNamespace(),
                   baseEnum.getEnumClassName());
-  } else if (attr.isSubClassOf("SPV_BitEnumAttr") ||
-             attr.isSubClassOf("SPV_I32EnumAttr")) {
+  } else if (attr.isSubClassOf("SPIRV_BitEnumAttr") ||
+             attr.isSubClassOf("SPIRV_I32EnumAttr")) {
     EnumAttr baseEnum(attr.getDef().getValueAsDef("enum"));
     os << tabs
        << formatv("  {0}.push_back(static_cast<uint32_t>("
                   "attr.cast<{1}::{2}Attr>().getValue()));\n",
                   operandList, baseEnum.getCppNamespace(),
                   baseEnum.getEnumClassName());
   } else if (attr.getAttrDefName() == "I32ArrayAttr") {
     // Serialize all the elements of the array
PrintFatalError(
         loc,
         llvm::Twine(
             "unhandled attribute type in SPIR-V serialization generation : '") +
             attr.getAttrDefName() + llvm::Twine("'"));
   }
   os << tabs << "}\n";
 }
 
-/// Generates code to serialize the operands of a SPV_Op `op` into `os`. The
+/// Generates code to serialize the operands of a SPIRV_Op `op` into `os`. The
 /// generated queries the SSA-ID if operand is a SSA-Value, or serializes the
 /// attributes. The `operands` vector is updated appropriately. `elidedAttrs`
 /// updated as well to include the serialized attributes.
 static void emitArgumentSerialization(const Operator &op, ArrayRef<SMLoc> loc,
                                       StringRef tabs, StringRef opVar,
                                       StringRef operands, StringRef elidedAttrs,
                                       raw_ostream &os) {
   using mlir::tblgen::Argument;
if (argument.is<NamedTypeConstraint *>()) {
           loc, newtabs, opVar, operands, attr->name, os);
       os << newtabs
          << formatv("{0}.push_back(\"{1}\");\n", elidedAttrs, attr->name);
     }
     os << tabs << "}\n";
   }
 }
 
-/// Generates code to serializes the result of SPV_Op `op` into `os`. The
+/// Generates code to serializes the result of SPIRV_Op `op` into `os`. The
 /// generated gets the ID for the type of the result (if any), the SSA-ID of
 /// the result and updates `resultID` with the SSA-ID.
 static void emitResultSerialization(const Operator &op, ArrayRef<SMLoc> loc,
                                     StringRef tabs, StringRef opVar,
                                     StringRef operands, StringRef resultID,
                                     raw_ostream &os) {
   if (op.getNumResults() == 1) {
     StringRef resultTypeID("resultTypeID");
if (op.getNumResults() == 1) {
     os << tabs
        << formatv("valueIDMap[{0}.getResult()] = {1};\n", opVar, resultID);
     os << tabs << formatv("{0}.push_back({1});\n", operands, resultID);
   } else if (op.getNumResults() != 0) {
     PrintFatalError(loc, "SPIR-V ops can only have zero or one result");
   }
 }
 
-/// Generates code to serialize attributes of SPV_Op `op` that become
+/// Generates code to serialize attributes of SPIRV_Op `op` that become
 /// decorations on the `resultID` of the serialized operation `opVar` in the
 /// SPIR-V binary.
 static void emitDecorationSerialization(const Operator &op, StringRef tabs,
                                         StringRef opVar, StringRef elidedAttrs,
                                         StringRef resultID, raw_ostream &os) {
   if (op.getNumResults() == 1) {
     // All non-argument attributes translated into OpDecorate instruction
     os << tabs << formatv("for (auto attr : {0}->getAttrs()) {{\n", opVar);
     os << tabs
        << formatv("  if (llvm::is_contained({0}, attr.getName())) {{",
                   elidedAttrs);
     os << tabs << "    continue;\n";
     os << tabs << "  }\n";
     os << tabs
        << formatv(
               "  if (failed(processDecoration({0}.getLoc(), {1}, attr))) {{\n",
               opVar, resultID);
     os << tabs << "    return failure();\n";
     os << tabs << "  }\n";
     os << tabs << "}\n";
   }
 }
 
-/// Generates code to serialize an SPV_Op `op` into `os`.
+/// Generates code to serialize an SPIRV_Op `op` into `os`.
 static void emitSerializationFunction(const Record *attrClass,
                                       const Record *record, const Operator &op,
                                       raw_ostream &os) {
   // If the record has 'autogenSerialization' set to 0, nothing to do
   if (!record->getValueAsBit("autogenSerialization"))
     return;
 
   StringRef opVar("op"), operands("operands"), elidedAttrs("elidedAttrs"),
       resultID("resultID");
 
   os << formatv(
       "template <> LogicalResult\nSerializer::processOp<{0}>({0} {1}) {{\n",
       op.getQualCppClassName(), opVar);
 
   // Special case for ops without attributes in TableGen definitions
   if (op.getNumAttributes() == 0 && op.getNumVariableLengthOperands() == 0) {
     std::string extInstSet;
     std::string opcode;
-    if (record->isSubClassOf("SPV_ExtInstOp")) {
+    if (record->isSubClassOf("SPIRV_ExtInstOp")) {
       extInstSet =
           formatv("\"{0}\"", record->getValueAsString("extendedInstSetName"));
       opcode = std::to_string(record->getValueAsInt("extendedInstOpcode"));
     } else {
       extInstSet = "\"\"";
       opcode = formatv("static_cast<uint32_t>(spirv::Opcode::{0})",
                        record->getValueAsString("spirvOpName"));
     }
if (op.getNumResults() == 1) {
     emitResultSerialization(op, record->getLoc(), "  ", opVar, operands,
                             resultID, os);
   }
 
   // Process arguments.
   emitArgumentSerialization(op, record->getLoc(), "  ", opVar, operands,
                             elidedAttrs, os);
 
-  if (record->isSubClassOf("SPV_ExtInstOp")) {
+  if (record->isSubClassOf("SPIRV_ExtInstOp")) {
     os << formatv(
         "  (void)encodeExtensionInstruction({0}, \"{1}\", {2}, {3});\n", opVar,
         record->getValueAsString("extendedInstSetName"),
         record->getValueAsInt("extendedInstOpcode"), operands);
   } else {
     // Emit debug info.
     os << formatv("  (void)emitDebugLine(functionBody, {0}.getLoc());\n",
                   opVar);

 /// the operation.
 static void finalizeDispatchSerializationFn(StringRef opVar, raw_ostream &os) {
   os << formatv(
       "  return {0}->emitError(\"unhandled operation serialization\");\n",
       opVar);
   os << "}\n\n";
 }
 
-/// Generates code to deserialize the attribute of a SPV_Op into `os`. The
+/// Generates code to deserialize the attribute of a SPIRV_Op into `os`. The
 /// generated code reads the `words` of the serialized instruction at
 /// position `wordIndex` and adds the deserialized attribute into `attrList`.
 static void emitAttributeDeserialization(const Attribute &attr,
                                          ArrayRef<SMLoc> loc, StringRef tabs,
                                          StringRef attrList, StringRef attrName,
                                          StringRef words, StringRef wordIndex,
                                          raw_ostream &os) {
-  if (attr.getAttrDefName() == "SPV_ScopeAttr" ||
-      attr.getAttrDefName() == "SPV_MemorySemanticsAttr" ||
-      attr.getAttrDefName() == "SPV_MatrixLayoutAttr") {
+  if (attr.getAttrDefName() == "SPIRV_ScopeAttr" ||
+      attr.getAttrDefName() == "SPIRV_MemorySemanticsAttr" ||
+      attr.getAttrDefName() == "SPIRV_MatrixLayoutAttr") {
     // These two enums are encoded as <id> to constant values in SPIR-V blob,
     // but we directly use the constant value as attribute in SPIR-V dialect. So
     // need to handle them separately from normal enum attributes.
     EnumAttr baseEnum(attr.getDef().getValueAsDef("enum"));
     os << tabs
        << formatv("{0}.push_back(opBuilder.getNamedAttr(\"{1}\", "
                   "opBuilder.getAttr<{2}::{3}Attr>(static_cast<{2}::{3}>("
                   "getConstantInt({4}[{5}++]).getValue().getZExtValue()))));\n",
                   attrList, attrName, baseEnum.getCppNamespace(),
                   baseEnum.getEnumClassName(), words, wordIndex);
-  } else if (attr.isSubClassOf("SPV_BitEnumAttr") ||
-             attr.isSubClassOf("SPV_I32EnumAttr")) {
+  } else if (attr.isSubClassOf("SPIRV_BitEnumAttr") ||
+             attr.isSubClassOf("SPIRV_I32EnumAttr")) {
     EnumAttr baseEnum(attr.getDef().getValueAsDef("enum"));
     os << tabs
        << formatv("  {0}.push_back(opBuilder.getNamedAttr(\"{1}\", "
                   "opBuilder.getAttr<{2}::{3}Attr>("
                   "static_cast<{2}::{3}>({4}[{5}++]))));\n",
                   attrList, attrName, baseEnum.getCppNamespace(),
                   baseEnum.getEnumClassName(), words, wordIndex);
   } else if (attr.getAttrDefName() == "I32ArrayAttr") {
static void emitAttributeDeserialization(const Attribute &attr,
   } else {
     PrintFatalError(
         loc, llvm::Twine(
                  "unhandled attribute type in deserialization generation : '") +
                  attr.getAttrDefName() + llvm::Twine("'"));
   }
 }
 
-/// Generates the code to deserialize the result of an SPV_Op `op` into
+/// Generates the code to deserialize the result of an SPIRV_Op `op` into
 /// `os`. The generated code gets the type of the result specified at
 /// `words`[`wordIndex`], the SSA ID for the result at position `wordIndex` + 1
 /// and updates the `resultType` and `valueID` with the parsed type and SSA ID,
 /// respectively.
 static void emitResultDeserialization(const Operator &op, ArrayRef<SMLoc> loc,
                                       StringRef tabs, StringRef words,
                                       StringRef wordIndex,
                                       StringRef resultTypes, StringRef valueID,
if (op.getNumResults() == 1) {
     os << tabs << "  }\n";
     os << tabs << "}\n";
     os << tabs << formatv("{0} = {1}[{2}++];\n", valueID, words, wordIndex);
   } else if (op.getNumResults() != 0) {
     PrintFatalError(loc, "SPIR-V ops can have only zero or one result");
   }
 }
 
-/// Generates the code to deserialize the operands of an SPV_Op `op` into
+/// Generates the code to deserialize the operands of an SPIRV_Op `op` into
 /// `os`. The generated code reads the `words` of the binary instruction, from
 /// position `wordIndex` to the end, and either gets the Value corresponding to
 /// the ID encoded, or deserializes the attributes encoded. The parsed
 /// operand(attribute) is added to the `operands` list or `attributes` list.
 static void emitOperandDeserialization(const Operator &op, ArrayRef<SMLoc> loc,
                                        StringRef tabs, StringRef words,
                                        StringRef wordIndex, StringRef operands,
                                        StringRef attributes, raw_ostream &os) {
if (op.getNumResults() == 1) {
     os << tabs
        << formatv("  auto attrs = decorations[{0}].getAttrs();\n", valueID);
     os << tabs
        << formatv("  {0}.append(attrs.begin(), attrs.end());\n", attributes);
     os << tabs << "}\n";
   }
 }
 
-/// Generates code to deserialize an SPV_Op `op` into `os`.
+/// Generates code to deserialize an SPIRV_Op `op` into `os`.
 static void emitDeserializationFunction(const Record *attrClass,
                                         const Record *record,
                                         const Operator &op, raw_ostream &os) {
   // If the record has 'autogenSerialization' set to 0, nothing to do
   if (!record->getValueAsBit("autogenSerialization"))
     return;
 
   StringRef resultTypes("resultTypes"), valueID("valueID"), words("words"),

 }
 
 static void
 emitExtendedSetDeserializationDispatch(const RecordKeeper &recordKeeper,
                                        raw_ostream &os) {
   StringRef extensionSetName("extensionSetName"),
       instructionID("instructionID"), words("words");
 
-  // First iterate over all ops derived from SPV_ExtensionSetOps to get all
+  // First iterate over all ops derived from SPIRV_ExtensionSetOps to get all
   // extensionSets.
 
   // For each of the extensions a separate raw_string_ostream is used to
   // generate code into. These are then concatenated at the end. Since
   // raw_string_ostream needs a string&, use a vector to store all the string
   // that are captured by reference within raw_string_ostream.
   StringMap<raw_string_ostream> extensionSets;
   std::list<std::string> extensionSetNames;
 
   initExtendedSetDeserializationDispatch(extensionSetName, instructionID, words,
                                          os);
-  auto defs = recordKeeper.getAllDerivedDefinitions("SPV_ExtInstOp");
+  auto defs = recordKeeper.getAllDerivedDefinitions("SPIRV_ExtInstOp");
   for (const auto *def : defs) {
     if (!def->getValueAsBit("autogenSerialization")) {
       continue;
     }
     Operator op(def);
     auto setName = def->getValueAsString("extendedInstSetName");
     if (!extensionSets.count(setName)) {
       extensionSetNames.emplace_back("");
emitExtendedSetDeserializationDispatch(const RecordKeeper &recordKeeper,
 
   os << formatv("  return emitError(unknownLoc, \"unhandled deserialization of "
                 "extended instruction set {0}\");\n",
                 extensionSetName);
   os << "}\n";
 }
 
 /// Emits all the autogenerated serialization/deserializations functions for the
-/// SPV_Ops.
+/// SPIRV_Ops.
 static bool emitSerializationFns(const RecordKeeper &recordKeeper,
                                  raw_ostream &os) {
   llvm::emitSourceFileHeader("SPIR-V Serialization Utilities/Functions", os);
 
   std::string dSerFnString, dDesFnString, serFnString, deserFnString,
       utilsString;
   raw_string_ostream dSerFn(dSerFnString), dDesFn(dDesFnString),
       serFn(serFnString), deserFn(deserFnString);
   Record *attrClass = recordKeeper.getClass("Attr");
 
   // Emit the serialization and deserialization functions simultaneously.
   StringRef opVar("op");
   StringRef opcode("opcode"), words("words");
 
   // Handle the SPIR-V ops.
   initDispatchSerializationFn(opVar, dSerFn);
   initDispatchDeserializationFn(opcode, words, dDesFn);
-  auto defs = recordKeeper.getAllDerivedDefinitions("SPV_Op");
+  auto defs = recordKeeper.getAllDerivedDefinitions("SPIRV_Op");
   for (const auto *def : defs) {
     Operator op(def);
     emitSerializationFunction(attrClass, def, op, serFn);
     emitDeserializationFunction(attrClass, def, op, deserFn);
-    if (def->getValueAsBit("hasOpcode") || def->isSubClassOf("SPV_ExtInstOp")) {
+    if (def->getValueAsBit("hasOpcode") ||
+        def->isSubClassOf("SPIRV_ExtInstOp")) {
       emitSerializationDispatch(op, "  ", opVar, dSerFn);
     }
     if (def->getValueAsBit("hasOpcode")) {
       emitDeserializationDispatch(op, def, "  ", words, dDesFn);
     }
   }
   finalizeDispatchSerializationFn(opVar, dSerFn);
   finalizeDispatchDeserializationFn(opcode, dDesFn);
static void emitAvailabilityImpl(const Operator &srcOp, raw_ostream &os) {
   // First collect all availability classes this op should implement.
   // All availability instances keep information for the generated interface and
   // the instance's specific requirement. Here we remember a random instance so
   // we can get the information regarding the generated interface.
   llvm::StringMap<Availability> availClasses;
   for (const Availability &avail : opAvailabilities)
     availClasses.try_emplace(avail.getClass(), avail);
   for (const NamedAttribute &namedAttr : srcOp.getAttributes()) {
-    if (!namedAttr.attr.isSubClassOf("SPV_BitEnumAttr") &&
-        !namedAttr.attr.isSubClassOf("SPV_I32EnumAttr"))
+    if (!namedAttr.attr.isSubClassOf("SPIRV_BitEnumAttr") &&
+        !namedAttr.attr.isSubClassOf("SPIRV_I32EnumAttr"))
       continue;
     EnumAttr enumAttr(namedAttr.attr.getDef().getValueAsDef("enum"));
 
     for (const EnumAttrCase &enumerant : enumAttr.getAllCases())
       for (const Availability &caseAvail :
            getAvailabilities(enumerant.getDef()))
         availClasses.try_emplace(caseAvail.getClass(), caseAvail);
   }
for (const Availability &avail : opAvailabilities)
            << std::string(
                   tgfmt(avail.getMergeActionCode(),
                         &fctx.addSubst("instance", avail.getMergeInstance())))
            << ";\n  }\n";
       }
 
     // Update with enum attributes' specific availability spec.
     for (const NamedAttribute &namedAttr : srcOp.getAttributes()) {
-      if (!namedAttr.attr.isSubClassOf("SPV_BitEnumAttr") &&
-          !namedAttr.attr.isSubClassOf("SPV_I32EnumAttr"))
+      if (!namedAttr.attr.isSubClassOf("SPIRV_BitEnumAttr") &&
+          !namedAttr.attr.isSubClassOf("SPIRV_I32EnumAttr"))
         continue;
       EnumAttr enumAttr(namedAttr.attr.getDef().getValueAsDef("enum"));
 
       // (enumerant, availability specification) pairs for this availability
       // class.
       SmallVector<std::pair<EnumAttrCase, Availability>, 1> caseSpecs;
 
       // Collect all cases' availability specs.
for (const auto &availClass : availClasses) {
     os << "}\n";
   }
 }
 
 static bool emitAvailabilityImpl(const RecordKeeper &recordKeeper,
                                  raw_ostream &os) {
   llvm::emitSourceFileHeader("SPIR-V Op Availability Implementations", os);
 
-  auto defs = recordKeeper.getAllDerivedDefinitions("SPV_Op");
+  auto defs = recordKeeper.getAllDerivedDefinitions("SPIRV_Op");
   for (const auto *def : defs) {
     Operator op(def);
     emitAvailabilityImpl(op, os);
   }
   return false;
 }
 
 //===----------------------------------------------------------------------===//

 // SPIR-V Capability Implication AutoGen
 //===----------------------------------------------------------------------===//
 
 static bool emitCapabilityImplication(const RecordKeeper &recordKeeper,
                                       raw_ostream &os) {
   llvm::emitSourceFileHeader("SPIR-V Capability Implication", os);
 
   EnumAttr enumAttr(
-      recordKeeper.getDef("SPV_CapabilityAttr")->getValueAsDef("enum"));
+      recordKeeper.getDef("SPIRV_CapabilityAttr")->getValueAsDef("enum"));
 
   os << "ArrayRef<spirv::Capability> "
         "spirv::getDirectImpliedCapabilities(spirv::Capability cap) {\n"
      << "  switch (cap) {\n"
      << "  default: return {};\n";
   for (const EnumAttrCase &enumerant : enumAttr.getAllCases()) {
     const Record &def = enumerant.getDef();
     if (!def.getValue("implies"))

mlir/utils/spirv/gen_spirv_dialect.py

- for_cap: bool value indicating whether this is the availability spec for
       capabilities themselves.
 
   Returns:
     - A `let availability = [...];` string if with availability spec or
       empty string if without availability spec
   """
   assert not (for_op and for_cap), 'cannot set both for_op and for_cap'
 
-  DEFAULT_MIN_VERSION = 'MinVersion<SPV_V_1_0>'
-  DEFAULT_MAX_VERSION = 'MaxVersion<SPV_V_1_6>'
+  DEFAULT_MIN_VERSION = 'MinVersion<SPIRV_V_1_0>'
+  DEFAULT_MAX_VERSION = 'MaxVersion<SPIRV_V_1_6>'
   DEFAULT_CAP = 'Capability<[]>'
   DEFAULT_EXT = 'Extension<[]>'
 
   min_version = enum_case.get('version', '')
   if min_version == 'None':
     min_version = ''
   elif min_version:
-    min_version = 'MinVersion<SPV_V_{}>'.format(min_version.replace('.', '_'))
+    min_version = 'MinVersion<SPIRV_V_{}>'.format(min_version.replace('.', '_'))
   # TODO: delete this once ODS can support dialect-specific content
   # and we can use omission to mean no requirements.
   if for_op and not min_version:
     min_version = DEFAULT_MIN_VERSION
 
   max_version = enum_case.get('lastVersion', '')
   if max_version:
-    max_version = 'MaxVersion<SPV_V_{}>'.format(max_version.replace('.', '_'))
+    max_version = 'MaxVersion<SPIRV_V_{}>'.format(max_version.replace('.', '_'))
   # TODO: delete this once ODS can support dialect-specific content
   # and we can use omission to mean no requirements.
   if for_op and not max_version:
     max_version = DEFAULT_MAX_VERSION
 
   exts = enum_case.get('extensions', [])
   if exts:
     exts = 'Extension<[{}]>'.format(', '.join(sorted(set(exts))))
def get_availability_spec(enum_case, capability_mapping, for_op, for_cap):
   if caps:
     canonicalized_caps = []
     for c in caps:
       if c in capability_mapping:
         canonicalized_caps.append(capability_mapping[c])
       else:
         canonicalized_caps.append(c)
     prefixed_caps = [
-        'SPV_C_{}'.format(c) for c in sorted(set(canonicalized_caps))
+        'SPIRV_C_{}'.format(c) for c in sorted(set(canonicalized_caps))
     ]
     if for_cap:
       # If this is generating the availability for capabilities, we need to
       # put the capability "requirements" in implies field because now
       # the "capabilities" field in the source grammar means so.
       caps = ''
       implies = 'list<I32EnumAttrCase> implies = [{}];'.format(
           ', '.join(prefixed_caps))
     else:
       caps = 'Capability<[{}]>'.format(', '.join(prefixed_caps))
       implies = ''
   # TODO: delete this once ODS can support dialect-specific content
   # and we can use omission to mean no requirements.
   if for_op and not caps:
     caps = DEFAULT_CAP
 
   avail = ''
   # Compose availability spec if any of the requirements is not empty.
-  # For ops, because we have a default in SPV_Op class, omit if the spec
+  # For ops, because we have a default in SPIRV_Op class, omit if the spec
   # is the same.
   if (min_version or max_version or caps or exts) and not (
       for_op and min_version == DEFAULT_MIN_VERSION and
       max_version == DEFAULT_MAX_VERSION and caps == DEFAULT_CAP and
       exts == DEFAULT_EXT):
     joined_spec = ',\n    '.join(
         [e for e in [min_version, max_version, exts, caps] if e])
     avail = '{} availability = [\n    {}\n  ];'.format(
def gen_operand_kind_enum_attr(operand_kind, capability_mapping):
   else:
     kind_cases = [(case['enumerant'], case['value'])
                   for case in operand_kind['enumerants']]
     kind_cases, _ = uniquify_enum_cases(kind_cases)
   max_len = max([len(symbol) for (symbol, _) in kind_cases])
 
   # Generate the definition for each enum case
   case_category = 'I32Bit' if is_bit_enum else 'I32'
-  fmt_str = 'def SPV_{acronym}_{case_name} {colon:>{offset}} '\
+  fmt_str = 'def SPIRV_{acronym}_{case_name} {colon:>{offset}} '\
             '{category}EnumAttrCase{suffix}<"{symbol}"{case_value_part}>{avail}'
   case_defs = []
   for case_pair in kind_cases:
     name = case_pair[0]
     if is_bit_enum:
       value = int(case_pair[1], base=16)
     else:
       value = int(case_pair[1])
case_def = fmt_str.format(
         case_value_part=value,
         avail=' {{\n  {}\n}}'.format(avail) if avail else ';',
         colon=':',
         offset=(max_len + 1 - len(name)))
     case_defs.append(case_def)
   case_defs = '\n'.join(case_defs)
 
   # Generate the list of enum case names
-  fmt_str = 'SPV_{acronym}_{symbol}';
+  fmt_str = 'SPIRV_{acronym}_{symbol}';
   case_names = [fmt_str.format(acronym=kind_acronym,symbol=case[0])
                 for case in kind_cases]
 
   # Split them into sublists and concatenate into multiple lines
   case_names = split_list_into_sublists(case_names)
   case_names = ['{:6}'.format('') + ', '.join(sublist)
                 for sublist in case_names]
   case_names = ',\n'.join(case_names)
 
   # Generate the enum attribute definition
   kind_category = 'Bit' if is_bit_enum else 'I32'
-  enum_attr = '''def SPV_{name}Attr :
-    SPV_{category}EnumAttr<"{name}", "valid SPIR-V {name}", "{snake_name}", [
+  enum_attr = '''def SPIRV_{name}Attr :
+    SPIRV_{category}EnumAttr<"{name}", "valid SPIR-V {name}", "{snake_name}", [
 {cases}
     ]>;'''.format(
           name=kind_name,
           snake_name=snake_casify(kind_name),
           category=kind_category,
           cases=case_names)
   return kind_name, case_defs + '\n\n' + enum_attr
 
 
 def gen_opcode(instructions):
   """ Generates the TableGen definition to map opname to opcode
 
   Returns:
-    - A string containing the TableGen SPV_OpCode definition
+    - A string containing the TableGen SPIRV_OpCode definition
   """
 
   max_len = max([len(inst['opname']) for inst in instructions])
-  def_fmt_str = 'def SPV_OC_{name} {colon:>{offset}} '\
+  def_fmt_str = 'def SPIRV_OC_{name} {colon:>{offset}} '\
             'I32EnumAttrCase<"{name}", {value}>;'
   opcode_defs = [
       def_fmt_str.format(
           name=inst['opname'],
           value=inst['opcode'],
           colon=':',
           offset=(max_len + 1 - len(inst['opname']))) for inst in instructions
   ]
   opcode_str = '\n'.join(opcode_defs)
 
-  decl_fmt_str = 'SPV_OC_{name}'
+  decl_fmt_str = 'SPIRV_OC_{name}'
   opcode_list = [
       decl_fmt_str.format(name=inst['opname']) for inst in instructions
   ]
   opcode_list = split_list_into_sublists(opcode_list)
   opcode_list = [
       '{:6}'.format('') + ', '.join(sublist) for sublist in opcode_list
   ]
   opcode_list = ',\n'.join(opcode_list)
-  enum_attr = 'def SPV_OpcodeAttr :\n'\
-              '    SPV_I32EnumAttr<"{name}", "valid SPIR-V instructions", '\
+  enum_attr = 'def SPIRV_OpcodeAttr :\n'\
+              '    SPIRV_I32EnumAttr<"{name}", "valid SPIR-V instructions", '\
               '"opcode", [\n'\
               '{lst}\n'\
               '    ]>;'.format(name='Opcode', lst=opcode_list)
   return opcode_str + '\n\n' + enum_attr
 
 def map_cap_to_opnames(instructions):
   """Maps capabilities to instructions enabled by those capabilities
 
Arguments:
     - path: the path to SPIRBase.td
     - instructions: a list containing all SPIR-V instructions' grammar
   """
   with open(path, 'r') as f:
     content = f.read()
 
   content = content.split(AUTOGEN_OPCODE_SECTION_MARKER)
 
-  existing_opcodes = [k[11:] for k in re.findall('def SPV_OC_\w+', content[1])]
+  existing_opcodes = [k[11:] for k in re.findall('def SPIRV_OC_\w+', content[1])]
   existing_instructions = list(
           filter(lambda inst: (inst['opname'] in existing_opcodes),
               instructions))
 
   instructions_opnames = [inst['opname'] for inst in instructions]
 
   remaining_opcodes = list(set(instructions_opnames) - set(existing_opcodes))
   remaining_instructions = list(
def update_td_opcodes(path, instructions, filter_list):
 
   with open(path, 'r') as f:
     content = f.read()
 
   content = content.split(AUTOGEN_OPCODE_SECTION_MARKER)
   assert len(content) == 3
 
   # Extend opcode list with existing list
-  existing_opcodes = [k[11:] for k in re.findall('def SPV_OC_\w+', content[1])]
+  existing_opcodes = [k[11:] for k in re.findall('def SPIRV_OC_\w+', content[1])]
   filter_list.extend(existing_opcodes)
   filter_list = list(set(filter_list))
 
   # Generate the opcode for all instructions in SPIR-V
   filter_instrs = list(
       filter(lambda inst: (inst['opname'] in filter_list), instructions))
   # Sort instruction based on opcode
   filter_instrs.sort(key=lambda inst: inst['opcode'])
def update_td_enum_attrs(path, operand_kinds, filter_list):
   with open(path, 'r') as f:
     content = f.read()
 
   content = content.split(AUTOGEN_ENUM_SECTION_MARKER)
   assert len(content) == 3
 
   # Extend filter list with existing enum definitions
   existing_kinds = [
-      k[8:-4] for k in re.findall('def SPV_\w+Attr', content[1])]
+      k[8:-4] for k in re.findall('def SPIRV_\w+Attr', content[1])]
   filter_list.extend(existing_kinds)
 
   capability_mapping = get_capability_mapping(operand_kinds)
 
   # Generate definitions for all enums in filter list
   defs = [
       gen_operand_kind_enum_attr(kind, capability_mapping)
       for kind in operand_kinds
def map_spec_operand_to_ods_argument(operand):
 
   # These instruction "operands" are for encoding the results; they should
   # not be handled here.
   assert kind != 'IdResultType', 'unexpected to handle "IdResultType" kind'
   assert kind != 'IdResult', 'unexpected to handle "IdResult" kind'
 
   if kind == 'IdRef':
     if quantifier == '':
-      arg_type = 'SPV_Type'
+      arg_type = 'SPIRV_Type'
     elif quantifier == '?':
-      arg_type = 'Optional<SPV_Type>'
+      arg_type = 'Optional<SPIRV_Type>'
     else:
-      arg_type = 'Variadic<SPV_Type>'
+      arg_type = 'Variadic<SPIRV_Type>'
   elif kind == 'IdMemorySemantics' or kind == 'IdScope':
     # TODO: Need to further constrain 'IdMemorySemantics'
     # and 'IdScope' given that they should be generated from OpConstant.
     assert quantifier == '', ('unexpected to have optional/variadic memory '
                               'semantics or scope <id>')
-    arg_type = 'SPV_' + kind[2:] + 'Attr'
+    arg_type = 'SPIRV_' + kind[2:] + 'Attr'
   elif kind == 'LiteralInteger':
     if quantifier == '':
       arg_type = 'I32Attr'
     elif quantifier == '?':
       arg_type = 'OptionalAttr<I32Attr>'
     else:
       arg_type = 'OptionalAttr<I32ArrayAttr>'
   elif kind == 'LiteralString' or \
       kind == 'LiteralContextDependentNumber' or \
       kind == 'LiteralExtInstInteger' or \
       kind == 'LiteralSpecConstantOpInteger' or \
       kind == 'PairLiteralIntegerIdRef' or \
       kind == 'PairIdRefLiteralInteger' or \
       kind == 'PairIdRefIdRef':
     assert False, '"{}" kind unimplemented'.format(kind)
   else:
     # The rest are all enum operands that we represent with op attributes.
     assert quantifier != '*', 'unexpected to have variadic enum attribute'
-    arg_type = 'SPV_{}Attr'.format(kind)
+    arg_type = 'SPIRV_{}Attr'.format(kind)
     if quantifier == '?':
       arg_type = 'OptionalAttr<{}>'.format(arg_type)
 
   name = operand.get('name', '')
   name = snake_casify(name) if name else kind.lower()
 
   return '{}:${}'.format(arg_type, name)
 
- existing_info: a dict containing potential manually specified sections for
       this instruction
     - capability_mapping: mapping from duplicated capability symbols to the
                    canonicalized symbol chosen for SPIRVBase.td
 
   Returns:
     - A string containing the TableGen op definition
   """
   if settings.gen_cl_ops:
-    fmt_str = ('def SPV_{opname}Op : '
-               'SPV_{inst_category}<"{opname_src}", {opcode}, <<Insert result type>> > '
+    fmt_str = ('def SPIRV_{opname}Op : '
+               'SPIRV_{inst_category}<"{opname_src}", {opcode}, <<Insert result type>> > '
                '{{\n  let summary = {summary};\n\n  let description = '
                '[{{\n{description}}}];{availability}\n')
   else:
-    fmt_str = ('def SPV_{vendor_name}{opname_src}Op : '
-               'SPV_{inst_category}<"{opname_src}"{category_args}, [{traits}]> '
+    fmt_str = ('def SPIRV_{vendor_name}{opname_src}Op : '
+               'SPIRV_{inst_category}<"{opname_src}"{category_args}, [{traits}]> '
                '{{\n  let summary = {summary};\n\n  let description = '
                '[{{\n{description}}}];{availability}\n')
 
   vendor_name = ''
   inst_category = existing_info.get('inst_category', 'Op')
   if inst_category == 'Op':
     fmt_str +='\n  let arguments = (ins{args});\n\n'\
               '  let results = (outs{results});\n'
def get_op_definition(instruction, opname, doc, existing_info, capability_mapping, settings):
   # Op availability
   avail = get_availability_spec(instruction, capability_mapping, True, False)
   if avail:
     avail = '\n\n  {0}'.format(avail)
 
   # Set op's result
   results = ''
   if len(operands) > 0 and operands[0]['kind'] == 'IdResultType':
-    results = '\n    SPV_Type:$result\n  '
+    results = '\n    SPIRV_Type:$result\n  '
     operands = operands[1:]
   if 'results' in existing_info:
     results = existing_info['results']
 
   # Ignore the operand standing for the result <id>
   if len(operands) > 0 and operands[0]['kind'] == 'IdResult':
     operands = operands[1:]
 
def extract_td_op_info(op_def):
   """Extracts potentially manually specified sections in op's definition.
 
   Arguments: - A string containing the op's TableGen definition
 
   Returns:
     - A dict containing potential manually specified sections
   """
   # Get opname
-  opname = [o[8:-2] for o in re.findall('def SPV_\w+Op', op_def)]
+  opname = [o[8:-2] for o in re.findall('def SPIRV_\w+Op', op_def)]
   assert len(opname) == 1, 'more than one ops in the same section!'
   opname = opname[0]
 
   # Get instruction category
   inst_category = [
-      o[4:] for o in re.findall('SPV_\w+Op',
+      o[4:] for o in re.findall('SPIRV_\w+Op',
                                 op_def.split(':', 1)[1])
   ]
   assert len(inst_category) <= 1, 'more than one ops in the same section!'
   inst_category = inst_category[0] if len(inst_category) == 1 else 'Op'
 
   # Get category_args
   op_tmpl_params, _ = get_string_between_nested(op_def, '<', '>')
   opstringname, rest = get_string_between(op_tmpl_params, '"', '"')