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[RISCV] Merge vmerge.vvm and unmasked intrinsic with VLMAX vector length.
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Authored by fakepaper56 on Aug 13 2022, 8:57 AM.

Details

Summary

The motivation of this patch is to lower the IR pattern
(vp.merge mask, (add x, y), false, vl) to
(PseudoVADD_VV_<LMUL>_MASK false, x, y, mask, vl).

Diff Detail

Event Timeline

fakepaper56 created this revision.Aug 13 2022, 8:57 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 13 2022, 8:57 AM
fakepaper56 requested review of this revision.Aug 13 2022, 8:57 AM
craig.topper added inline comments.Aug 18 2022, 1:07 PM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
2677

This is incorrect if the True opcode can raise a floating point exception. Applying the mask could lose an exception that should occur even if the result is discarded.

I think we need to look up the MayRaiseException property from the MCInstrDesc entry for the opcode. If it is has that properly, we need to check that the hasNoFPExcept bit in the SDNodeFlags is set before doing this combine.

craig.topper added inline comments.Aug 18 2022, 1:09 PM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
2700

We also should be copying the NoFPExcept flag here. Can probably just take the SDNodeFlags from the True node.

fakepaper56 added inline comments.Aug 22 2022, 11:36 PM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
2677

Good point. Thank you find the bug.

Address Craig's comment and rebase.

Make test case more similiar as previous commit.

This revision is now accepted and ready to land.Aug 27 2022, 3:37 PM
This revision was landed with ongoing or failed builds.Aug 28 2022, 8:45 PM
This revision was automatically updated to reflect the committed changes.
luke added a subscriber: luke.Jul 11 2023, 6:56 AM
luke added inline comments.
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
2677

@fakepaper56 @craig.topper is there a reason why we only check for fp exceptions when the VL changes and not the mask too?

evandro removed a subscriber: evandro.Jul 11 2023, 3:06 PM