[RISCV] Fold vector binary operatrion into select with identity constant.

[jacquesguan]

Summary

This patch implements shouldFoldSelectWithIdentityConstant for RISCV. It would try to generate vmerge after the binary instruction and let them folded to maksed instruction later.

[craig.topper]

We've been discussing doing this as a post isel peephole or a DAG combine in D130442. That should have much less impact on the size of the generated isel table.

It might not be a good idea to do this fold without checking that the select is the only user of binary op. If it's not the only user you'll duplicate the binary op and there will be a masked and unmasked version. This can increase register pressure and use more execution resources.

[jacquesguan]

Use DAG combiner instead of pattern.

[jacquesguan]

remove empty line.

[jacquesguan]

In D131551#3713084, @craig.topper wrote:

We've been discussing doing this as a post isel peephole or a DAG combine in D130442. That should have much less impact on the size of the generated isel table.

It might not be a good idea to do this fold without checking that the select is the only user of binary op. If it's not the only user you'll duplicate the binary op and there will be a masked and unmasked version. This can increase register pressure and use more execution resources.

Thanks for your advice, I swtich to the DAG combiner. And I do not support fixed vector in this revision as I have not finished its test cases. I will add anothe revision to make it.

[StephenFan]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8317 ↗

(On Diff #452148)

Is it possible to use a macro definition to reduce code lines?

[jacquesguan]

Address comment.

[jacquesguan]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8317 ↗

(On Diff #452148)

Done.

[jrtc27]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8314 ↗

(On Diff #452362)

Imm isn't that clear, this is really the identity

8357 ↗

(On Diff #452362)

Why the blank line when the others don't have one?

8317 ↗

(On Diff #452148)

Undefine helper macros like this once you're done with them

[jacquesguan]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8314 ↗

(On Diff #452362)

Which word you suggest to use?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

981 ↗

(On Diff #452362)

Why !hasStdExtZbb()?

8347 ↗

(On Diff #452362)

VLMaxSentinel is not to be used in SelectionDAG anymore. Use getRegister(RISCV::X0

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8290 ↗

(On Diff #452362)

std::swap?

8324 ↗

(On Diff #452362)

Some of these operations aren't commutable. If the select is on the LHS of the SUB this transform isn't valid.

8330 ↗

(On Diff #452362)

1 is not an identity value for urem or srem, it would always return 0.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8326 ↗

(On Diff #452362)

1 is also not the identify value for MULHS/MULHU. This returns the high half of the product. MULHU(a, 1) produces 0 since the high product is 0. MULHS(a, 1) is a vector filled with the sigh bit of a.

[jacquesguan]

Address comment.

[jacquesguan]

Remove blank line.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

981 ↗

(On Diff #452362)

if (Subtarget.hasStdExtZbb())
  setTargetDAGCombine({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN});

Because if we have Zbb, we already set ISD::UMIN and ISD::UMAX.

8290 ↗

(On Diff #452362)

Done.

8324 ↗

(On Diff #452362)

Done.

8326 ↗

(On Diff #452362)

Done, I removed MULHS, MULHU, UREM and SREM.

8330 ↗

(On Diff #452362)

Done.

8347 ↗

(On Diff #452362)

Done.

8357 ↗

(On Diff #452362)

Done.

8317 ↗

(On Diff #452148)

Done.

[reames]

Can you land the tests and rebase this change please? Be helpful to see the deltas.

Please also add tests (for only one op flavor is fine) for binop with multiple uses, and other negative edge cases.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8275 ↗

(On Diff #452603)

This isn't protected against illegal types. DAGCombiners can see any types.

My suggestion is to defer this combine until DCI.isAfterLegalizeDAG() which ensure types are legalized and that we don't create _VL operations too early.

8286 ↗

(On Diff #452603)

Imm -> IdentityImm

8293 ↗

(On Diff #452603)

Use TargetLowering::isCommutativeBinOp?

8333 ↗

(On Diff #452603)

Technically you need to truncate the splat_vector input to element size. But maybe all your tests are before type legalization so you don't test any SPLAT_VECTORS where the scalar input is larger than the element type?

8337 ↗

(On Diff #452603)

VMV_V_X_VL is allowed to have scalar values both larger and smaller than the element type.

981 ↗

(On Diff #452362)

It's harmless to do it again and would make the code less confusing.

[jacquesguan]

Address comment.

[jacquesguan]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8275 ↗

(On Diff #452603)

Done.

8286 ↗

(On Diff #452603)

Done.

8293 ↗

(On Diff #452603)

Done.

8333 ↗

(On Diff #452603)

Done.

8337 ↗

(On Diff #452603)

Done.

981 ↗

(On Diff #452362)

Done.

[jacquesguan]

In D131551#3723187, @reames wrote:

Can you land the tests and rebase this change please? Be helpful to see the deltas.

Please also add tests (for only one op flavor is fine) for binop with multiple uses, and other negative edge cases.

Done, I add a pre-commit test in https://reviews.llvm.org/D131950, and the negative test is added in the llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll.

[jacquesguan]

ping.

[craig.topper]

How much does this overlap with implementing RISCVTargetLowering::shouldFoldSelectWithIdentityConstant and letting the generic DAGCombiner do this?

[jacquesguan]

In D131551#3756737, @craig.topper wrote:

How much does this overlap with implementing RISCVTargetLowering::shouldFoldSelectWithIdentityConstant and letting the generic DAGCombiner do this?

Thanks, it should work, but I need https://reviews.llvm.org/D132923 to fold the transformed DAG, could you mind to have a review?

[jacquesguan]

Use RISCVTargetLowering::shouldFoldSelectWithIdentityConstant to make it.

[jacquesguan]

In D131551#3756737, @craig.topper wrote:

How much does this overlap with implementing RISCVTargetLowering::shouldFoldSelectWithIdentityConstant and letting the generic DAGCombiner do this?

Done.

[jacquesguan]

ping.

[craig.topper]

foldSelectWithIdentityConstant handles FP as well, but you have no FP tests. It doesn't look like you did anything to disable FP unless I missed it.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

2220 ↗

(On Diff #461806)

This needs to be rebased.

[jacquesguan]

rebase and add fp test.

[jacquesguan]

In D131551#3869552, @craig.topper wrote:

foldSelectWithIdentityConstant handles FP as well, but you have no FP tests. It doesn't look like you did anything to disable FP unless I missed it.

Done, I add FP cases.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

2220 ↗

(On Diff #461806)

Done.

[jacquesguan]

ping.

[jacquesguan]

ping.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1214 ↗

(On Diff #469486)

This is imprecise for FP which has a different ELEN for Zve64f and Zve32x.

I think you can ignore it for scalable vectors since those elements always have to be supported if we see them. For fixed vectors we should check isTypeLegal.

[jacquesguan]

Address comment.

[jacquesguan]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1214 ↗

(On Diff #469486)

Done, thanks.

[jacquesguan]

ping.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

foreach vti = AllIntegerVectors in {
     def : Pat<(vti.Vector (op vti.RegClass:$rs2,
                               (mul_oneuse (SplatPat XLenVT:$rs1), vti.RegClass:$rd))),
               (!cast<Instruction>(instruction_name#"_VX_" # suffix)
                  vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
                  vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
   }
 }
 
+class VPatBinaryMaskSDNode_VV<SDNode vop,
+                              string instruction_name,
+                              ValueType result_type,
+                              ValueType op_type,
+                              ValueType mask_type,
+                              int sew,
+                              LMULInfo vlmul,
+                              OutPatFrag avl,
+                              VReg op_reg_class,
+                              int imm> :
+    Pat<(result_type (vop (op_type op_reg_class:$rs1),
+                          (op_type (vselect (mask_type V0),
+                                            (op_type op_reg_class:$rs2),
+                                            (riscv_vmv_v_x_vl
+                                                 (op_type undef), imm,
+                                                 (XLenVT srcvalue)))))),
+        (!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX#"_MASK")
+                     op_reg_class:$rs1,
+                     op_reg_class:$rs1,
+                     op_reg_class:$rs2,
+                     (mask_type V0),
+                     avl, sew, TAIL_AGNOSTIC)>;
+
+class VPatBinaryMaskSDNode_XI<SDNode vop,
+                              string instruction_name,
+                              string suffix,
+                              ValueType result_type,
+                              ValueType vop_type,
+                              ValueType mask_type,
+                              int sew,
+                              LMULInfo vlmul,
+                              OutPatFrag avl,
+                              VReg vop_reg_class,
+                              ComplexPattern SplatPatKind,
+                              DAGOperand xop_kind,
+                              int imm> :
+    Pat<(result_type (vop
+                     (vop_type vop_reg_class:$rs1),
+                     (vop_type (vselect (mask_type V0),
+                                        (vop_type (SplatPatKind xop_kind:$rs2)),
+                                        (riscv_vmv_v_x_vl
+                                             (vop_type undef), imm,
+                                             (XLenVT srcvalue)))))),
+        (!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX#"_MASK")
+                     vop_reg_class:$rs1,
+                     vop_reg_class:$rs1,
+                     xop_kind:$rs2,
+                     (mask_type V0),
+                     avl, sew, TAIL_AGNOSTIC)>;
+
+
+multiclass VPatBinaryMaskSDNode_VV_VX<SDNode vop, string instruction_name,
+                                      int imm> {
+  foreach vti = AllIntegerVectors in {
+    def : VPatBinaryMaskSDNode_VV<vop, instruction_name,
+                                  vti.Vector, vti.Vector, vti.Mask,
+                                  vti.Log2SEW, vti.LMul, vti.AVL,
+                                  vti.RegClass, imm>;
+    def : VPatBinaryMaskSDNode_XI<vop, instruction_name, "VX",
+                                  vti.Vector, vti.Vector, vti.Mask,
+                                  vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass,
+                                  SplatPat, GPR, imm>;
+  }
+}
+
+multiclass VPatBinaryMaskSDNode_VV_VX_VI<SDNode vop, string instruction_name,
+                                         int imm, Operand ImmType = simm5>
+    : VPatBinaryMaskSDNode_VV_VX<vop, instruction_name, imm> {
+  foreach vti = AllIntegerVectors in {
+    def : VPatBinaryMaskSDNode_XI<vop, instruction_name, "VI",
+                                  vti.Vector, vti.Vector, vti.Mask,
+                                  vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass,
+                                  !cast<ComplexPattern>(SplatPat#_#ImmType),
+                                  ImmType, imm>;
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // Patterns.
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasVInstructions] in {
 
 // 7.4. Vector Unit-Stride Instructions
 foreach vti = !listconcat(FractionalGroupIntegerVectors,
                           FractionalGroupFloatVectors) in
   defm : VPatUSLoadStoreSDNode<vti.Vector, vti.Log2SEW, vti.LMul,
                                vti.AVL, vti.RegClass>;
 foreach vti = [VI8M1, VI16M1, VI32M1, VI64M1, VF16M1, VF32M1, VF64M1] in
   defm : VPatUSLoadStoreWholeVRSDNode<vti.Vector, vti.Log2SEW, vti.LMul,
                                       vti.RegClass>;
 foreach vti = !listconcat(GroupIntegerVectors, GroupFloatVectors) in
   defm : VPatUSLoadStoreWholeVRSDNode<vti.Vector, vti.Log2SEW, vti.LMul,
                                       vti.RegClass>;
 foreach mti = AllMasks in
   defm : VPatUSLoadStoreMaskSDNode<mti>;
 
 // 12.1. Vector Single-Width Integer Add and Subtract
 defm : VPatBinarySDNode_VV_VX_VI<add, "PseudoVADD">;
+defm : VPatBinaryMaskSDNode_VV_VX_VI<add, "PseudoVADD", 0>;
+
 defm : VPatBinarySDNode_VV_VX<sub, "PseudoVSUB">;
+defm : VPatBinaryMaskSDNode_VV_VX<sub, "PseudoVSUB", 0>;
+
 // Handle VRSUB specially since it's the only integer binary op with reversed
 // pattern operands
 foreach vti = AllIntegerVectors in {
   def : Pat<(sub (vti.Vector (SplatPat GPR:$rs2)),
                  (vti.Vector vti.RegClass:$rs1)),
             (!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX)
                  vti.RegClass:$rs1, GPR:$rs2, vti.AVL, vti.Log2SEW)>;
   def : Pat<(sub (vti.Vector (SplatPat_simm5 simm5:$rs2)),
defm : VPatExtendSDNode_V<[sext],         "PseudoVSEXT", "VF4",
                           AllFractionableVF4IntVectors>;
 defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF8",
                           AllFractionableVF8IntVectors>;
 defm : VPatExtendSDNode_V<[sext],         "PseudoVSEXT", "VF8",
                           AllFractionableVF8IntVectors>;
 
 // 12.5. Vector Bitwise Logical Instructions
 defm : VPatBinarySDNode_VV_VX_VI<and, "PseudoVAND">;
+defm : VPatBinaryMaskSDNode_VV_VX_VI<and, "PseudoVAND", -1>;
 defm : VPatBinarySDNode_VV_VX_VI<or, "PseudoVOR">;
+defm : VPatBinaryMaskSDNode_VV_VX_VI<or, "PseudoVOR", 0>;
 defm : VPatBinarySDNode_VV_VX_VI<xor, "PseudoVXOR">;
+defm : VPatBinaryMaskSDNode_VV_VX_VI<xor, "PseudoVXOR", 0>;
 
 // 12.6. Vector Single-Width Bit Shift Instructions
 defm : VPatBinarySDNode_VV_VX_VI<shl, "PseudoVSLL", uimm5>;
+defm : VPatBinaryMaskSDNode_VV_VX_VI<shl, "PseudoVSLL", 0, uimm5>;
 defm : VPatBinarySDNode_VV_VX_VI<srl, "PseudoVSRL", uimm5>;
+defm : VPatBinaryMaskSDNode_VV_VX_VI<srl, "PseudoVSRL", 0, uimm5>;
 defm : VPatBinarySDNode_VV_VX_VI<sra, "PseudoVSRA", uimm5>;
+defm : VPatBinaryMaskSDNode_VV_VX_VI<sra, "PseudoVSRA", 0, uimm5>;
 
 foreach vti = AllIntegerVectors in {
   // Emit shift by 1 as an add since it might be faster.
   def : Pat<(shl (vti.Vector vti.RegClass:$rs1),
                  (vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), 1, (XLenVT srcvalue)))),
             (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX)
                  vti.RegClass:$rs1, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>;
 
defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSLEU", SETULT,
                                       SplatPat_simm5_plus1_nonzero>;
 defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSGT", SETGE,
                                       SplatPat_simm5_plus1>;
 defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSGTU", SETUGE,
                                       SplatPat_simm5_plus1_nonzero>;
 
 // 12.9. Vector Integer Min/Max Instructions
 defm : VPatBinarySDNode_VV_VX<umin, "PseudoVMINU">;
+defm : VPatBinaryMaskSDNode_VV_VX<umin, "PseudoVMINU", -1>;
 defm : VPatBinarySDNode_VV_VX<smin, "PseudoVMIN">;
 defm : VPatBinarySDNode_VV_VX<umax, "PseudoVMAXU">;
+defm : VPatBinaryMaskSDNode_VV_VX<umax, "PseudoVMAXU", 0>;
 defm : VPatBinarySDNode_VV_VX<smax, "PseudoVMAX">;
 
 // 12.10. Vector Single-Width Integer Multiply Instructions
 defm : VPatBinarySDNode_VV_VX<mul, "PseudoVMUL">;
+defm : VPatBinaryMaskSDNode_VV_VX<mul, "PseudoVMUL", 1>;
 defm : VPatBinarySDNode_VV_VX<mulhs, "PseudoVMULH">;
+defm : VPatBinaryMaskSDNode_VV_VX<mulhs, "PseudoVMULH", 1>;
 defm : VPatBinarySDNode_VV_VX<mulhu, "PseudoVMULHU">;
+defm : VPatBinaryMaskSDNode_VV_VX<mulhu, "PseudoVMULHU", 1>;
 
 // 12.11. Vector Integer Divide Instructions
 defm : VPatBinarySDNode_VV_VX<udiv, "PseudoVDIVU">;
+defm : VPatBinaryMaskSDNode_VV_VX<udiv, "PseudoVDIVU", 1>;
 defm : VPatBinarySDNode_VV_VX<sdiv, "PseudoVDIV">;
+defm : VPatBinaryMaskSDNode_VV_VX<sdiv, "PseudoVDIV", 1>;
 defm : VPatBinarySDNode_VV_VX<urem, "PseudoVREMU">;
+defm : VPatBinaryMaskSDNode_VV_VX<urem, "PseudoVREMU", 1>;
 defm : VPatBinarySDNode_VV_VX<srem, "PseudoVREM">;
+defm : VPatBinaryMaskSDNode_VV_VX<srem, "PseudoVREM", 1>;
 
 // 12.12. Vector Widening Integer Multiply Instructions
 defm : VPatWidenBinarySDNode_VV_VX<mul, sext_oneuse, sext_oneuse,
                                    "PseudoVWMUL">;
 defm : VPatWidenBinarySDNode_VV_VX<mul, zext_oneuse, zext_oneuse,
                                    "PseudoVWMULU">;
 defm : VPatWidenBinarySDNode_VV_VX<mul, anyext_oneuse, anyext_oneuse,
                                    "PseudoVWMULU">;

llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll

 ; RV64-NEXT:    ret
   %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
   %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
   %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %v = add <vscale x 8 x i64> %splat1, %splat2
   ret <vscale x 8 x i64> %v
 }
+
+define <vscale x 8 x i32> @vadd_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vadd_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vadd.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vadd_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vadd_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vadd_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vadd_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vadd.vi v8, v8, 7, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}

llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll

 ; RV64-NEXT:    ret
   %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
   %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
   %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %v = and <vscale x 8 x i64> %splat1, %splat2
   ret <vscale x 8 x i64> %v
 }
+
+define <vscale x 8 x i32> @vand_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vand_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vand.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
+  %allones = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %allones
+  %vc = and <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vand_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vand_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
+  %allones = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %allones
+  %vc = and <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vand_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vand_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vand.vi v8, v8, 7, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
+  %allones = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %allones
+  %vc = and <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}

llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll

 ; RV64-V-NEXT:    vsra.vi v8, v8, 1
 ; RV64-V-NEXT:    vadd.vv v8, v8, v16
 ; RV64-V-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> poison, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
+
+define <vscale x 8 x i32> @vdiv_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vdiv_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vdiv.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
+  %vc = sdiv <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vdiv_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vdiv_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vdiv.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+  %vc = sdiv <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vdiv_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vdiv_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vdiv.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+  %vc = sdiv <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}

llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll

 ; CHECK-NEXT:    vsrl.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %vc = shl <vscale x 8 x i64> %splat, %vb
   %vd = udiv <vscale x 8 x i64> %va, %vc
   ret <vscale x 8 x i64> %vd
 }
+
+define <vscale x 8 x i32> @vdivu_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vdivu_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vdivu.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
+  %vc = udiv <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vdivu_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vdivu_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vdivu.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+  %vc = udiv <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vdivu_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vdivu_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vdivu.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+  %vc = udiv <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}

llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll

 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> poison, i64 -3, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %cmp = icmp ugt <vscale x 8 x i64> %va, %splat
   %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
   ret <vscale x 8 x i64> %vc
 }
 
+define <vscale x 8 x i32> @vmax_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmax_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmaxu.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+  %cmp = icmp ugt <vscale x 8 x i32> %va, %vs
+  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vmax_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmax_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmaxu.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %cmp = icmp ugt <vscale x 8 x i32> %va, %vs
+  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vmax_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmax_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, -3
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmaxu.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 -3, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %cmp = icmp ugt <vscale x 8 x i32> %va, %vs
+  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
+  ret <vscale x 8 x i32> %vc
+}

llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll

 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> poison, i64 -3, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %cmp = icmp ult <vscale x 8 x i64> %va, %splat
   %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
   ret <vscale x 8 x i64> %vc
 }
 
+define <vscale x 8 x i32> @vmin_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmin_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vminu.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
+  %max = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %max
+  %cmp = icmp ult <vscale x 8 x i32> %va, %vs
+  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vmin_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmin_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vminu.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head0 = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
+  %max = shufflevector <vscale x 8 x i32> %head0, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %max
+  %cmp = icmp ult <vscale x 8 x i32> %va, %vs
+  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vmin_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmin_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, -3
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vminu.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head0 = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
+  %max = shufflevector <vscale x 8 x i32> %head0, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 -3, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %max
+  %cmp = icmp ult <vscale x 8 x i32> %va, %vs
+  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
+  ret <vscale x 8 x i32> %vc
+}

llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll

 ; RV64M-NEXT:    ret
   %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
   %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
   %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %v = mul <vscale x 8 x i64> %splat1, %splat2
   ret <vscale x 8 x i64> %v
 }
+
+define <vscale x 8 x i32> @vmul_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmul_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmul.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
+  %vc = mul <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vmul_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmul_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmul.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+  %vc = mul <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vmul_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmul_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmul.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+  %vc = mul <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+

llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll

; CHECK-NEXT:    ret
   %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
   %vd = mul <vscale x 8 x i64> %vb, %vc
   %head2 = insertelement <vscale x 8 x i64> poison, i64 32, i32 0
   %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %ve = lshr <vscale x 8 x i64> %vd, %splat2
   %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %vf
 }
+
+define <vscale x 8 x i32> @vmulh_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmulh_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulh.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %head0 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head0, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
+  %vc = sext <vscale x 8 x i32> %vs to <vscale x 8 x i64>
+  %vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+  %ve = mul <vscale x 8 x i64> %vc, %vd
+  %head1 = insertelement <vscale x 8 x i64> poison, i64 32, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+  %vf = lshr <vscale x 8 x i64> %ve, %splat
+  %vg = trunc <vscale x 8 x i64> %vf to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %vg
+}
+
+define <vscale x 8 x i32> @vmulh_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %x, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmulh_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head0 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head0, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 %x, i32 0
+  %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat1, <vscale x 8 x i32> %one
+  %vb = sext <vscale x 8 x i32> %vs to <vscale x 8 x i64>
+  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+  %vd = mul <vscale x 8 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 8 x i64> poison, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+  %ve = lshr <vscale x 8 x i64> %vd, %splat2
+  %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %vf
+}
+
+define <vscale x 8 x i32> @vmulh_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmulh_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head0 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head0, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat1, <vscale x 8 x i32> %one
+  %vb = sext <vscale x 8 x i32> %vs to <vscale x 8 x i64>
+  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+  %vd = mul <vscale x 8 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 8 x i64> poison, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+  %ve = lshr <vscale x 8 x i64> %vd, %splat2
+  %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %vf
+}

llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll

; RV64-NEXT:    ret
   %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
   %vd = mul <vscale x 8 x i64> %vb, %vc
   %head2 = insertelement <vscale x 8 x i64> poison, i64 32, i32 0
   %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %ve = lshr <vscale x 8 x i64> %vd, %splat2
   %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %vf
 }
+
+define <vscale x 8 x i32> @vmulhu_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmulhu_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulhu.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %head0 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head0, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
+  %vc = zext <vscale x 8 x i32> %vs to <vscale x 8 x i64>
+  %vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+  %ve = mul <vscale x 8 x i64> %vc, %vd
+  %head1 = insertelement <vscale x 8 x i64> poison, i64 32, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+  %vf = lshr <vscale x 8 x i64> %ve, %splat
+  %vg = trunc <vscale x 8 x i64> %vf to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %vg
+}
+
+define <vscale x 8 x i32> @vmulhu_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %x, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmulhu_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head0 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head0, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 %x, i32 0
+  %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat1, <vscale x 8 x i32> %one
+  %vb = zext <vscale x 8 x i32> %vs to <vscale x 8 x i64>
+  %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+  %vd = mul <vscale x 8 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 8 x i64> poison, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+  %ve = lshr <vscale x 8 x i64> %vd, %splat2
+  %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %vf
+}
+
+define <vscale x 8 x i32> @vmulhu_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmulhu_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head0 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head0, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat1, <vscale x 8 x i32> %one
+  %vb = zext <vscale x 8 x i32> %vs to <vscale x 8 x i64>
+  %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+  %vd = mul <vscale x 8 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 8 x i64> poison, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+  %ve = lshr <vscale x 8 x i64> %vd, %splat2
+  %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %vf
+}

llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll

 ; RV64-NEXT:    ret
   %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
   %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
   %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %v = or <vscale x 8 x i64> %splat1, %splat2
   ret <vscale x 8 x i64> %v
 }
+
+define <vscale x 8 x i32> @vor_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vor_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vor.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vor_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vor_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vor.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vor_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vor_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vor.vi v8, v8, 7, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}

llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll

 ; RV64-V-NEXT:    vnmsac.vx v8, a0, v16
 ; RV64-V-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> poison, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 
+
+define <vscale x 8 x i32> @vrem_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vrem_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vrem.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
+  %vc = srem <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vrem_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vrem_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vrem.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+  %vc = srem <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vrem_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vrem_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vrem.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+  %vc = srem <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+

llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll

 ; CHECK-NEXT:    vand.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %vc = shl <vscale x 8 x i64> %splat, %vb
   %vd = urem <vscale x 8 x i64> %va, %vc
   ret <vscale x 8 x i64> %vd
 }
+
+define <vscale x 8 x i32> @vremu_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vremu_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vremu.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
+  %vc = urem <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vremu_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vremu_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vremu.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+  %vc = urem <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vremu_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vremu_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vremu.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+  %vc = urem <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}

llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll

 ; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
 ; CHECK-NEXT:    vadd.vv v8, v8, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> poison, i64 1, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %vc = shl <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
+
+define <vscale x 8 x i32> @vshl_vv_mask_nxv4i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vshl_vv_mask_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsll.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vshl_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vshl_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsll.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vshl_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vshl_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsll.vi v8, v8, 31, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 31, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}

llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll

 ; CHECK-NEXT:    vsra.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> poison, i64 32, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %vc = ashr <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 
+define <vscale x 8 x i32> @vsra_vv_mask_nxv4i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsra_vv_mask_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsra.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+  %vc = ashr <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsra_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsra_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsra.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = ashr <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsra_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsra_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsra.vi v8, v8, 31, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 31, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = ashr <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}

llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll

 ; CHECK-NEXT:    vsrl.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> poison, i64 32, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %vc = lshr <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 
+define <vscale x 8 x i32> @vsrl_vv_mask_nxv4i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsrl_vv_mask_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsrl.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsrl_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsrl_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsrl.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsrl_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsrl_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsrl.vi v8, v8, 31, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 31, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}

llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll

 ; RV64-NEXT:    ret
   %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
   %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
   %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %v = sub <vscale x 8 x i64> %splat1, %splat2
   ret <vscale x 8 x i64> %v
 }
+
+define <vscale x 8 x i32> @vsub_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsub_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsub.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+  %vc = sub <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsub_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsub_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsub.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = sub <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsub_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsub_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsub.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = sub <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}

llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll

 ; RV64-NEXT:    ret
   %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
   %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
   %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
   %v = xor <vscale x 8 x i64> %splat1, %splat2
   ret <vscale x 8 x i64> %v
 }
+
+define <vscale x 8 x i32> @vxor_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vxor_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vxor.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+  %vc = xor <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vxor_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vxor_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = xor <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vxor_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vxor_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = xor <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}