MC: force eager evaluation of relocations in `.debug_info`

[MaskRay]

Summary

Force eager evaluation of symbolic difference on debug_info which is
required to be resolved eagerly for fission as dwo sections may not
contain relocations.

Fixes: #56642

[MaskRay]

This does not fix the incompatibility with RISC-V linker relaxation. This changes DW_AT_high_pc from a length to (pre-DWARF-v4) an address.
The address needs to be relocated as well. The correct approach is to use .debug_addr indirection via DW_FORM_addrx.

This is useful with linker relaxation, though, as it can decrease the number of relocations.

https://maskray.me/blog/2021-03-14-the-dark-side-of-riscv-linker-relaxation#code-addresses I am going to revise some paragraphs about DWARF.

[MaskRay]

Note: with -mno-relax this will increase the number of relocations.

[compnerd]

In D130206#3666984, @MaskRay wrote:

This does not fix the incompatibility with RISC-V linker relaxation. This changes DW_AT_high_pc from a length to (pre-DWARF-v4) an address.

Correct, this is not to fix the incompatibility with relaxation, it is to fix the compatibility with no relaxation and fission.

The address needs to be relocated as well. The correct approach is to use .debug_addr indirection via DW_FORM_addrx.

Interesting, do we have any target currently using that form?

This is useful with linker relaxation, though, as it can decrease the number of relocations.

https://maskray.me/blog/2021-03-14-the-dark-side-of-riscv-linker-relaxation#code-addresses I am going to revise some paragraphs about DWARF.

Yes, this should be able to reduce the number of relocations at the cost of debug info size. However, given that we currently fail to emit the object file this seems like a good tradeoff.

[MaskRay]

In D130206#3669301, @compnerd wrote:

In D130206#3666984, @MaskRay wrote:

This does not fix the incompatibility with RISC-V linker relaxation. This changes DW_AT_high_pc from a length to (pre-DWARF-v4) an address.

Correct, this is not to fix the incompatibility with relaxation, it is to fix the compatibility with no relaxation and fission.

For -mno-relax code, using the length instead of the end address for DW_AT_high_pc leads to fewer relocations in the output.
MC should be able to resolve the pair of R_RISCV_ADD32/R_RISCV_SUB32 to a constant.

With this patch, there will be a relocation which cannot be resolved at assembler time, leading to larger output size.

The address needs to be relocated as well. The correct approach is to use .debug_addr indirection via DW_FORM_addrx.

Interesting, do we have any target currently using that form?

No. As you can see, for -mno-relax, DW_AT_high_pc is a constant which saves more space than using the end address (one relocation) or using a .debug_addr indirection to represent the end address (more expensive),
so it is unimplemented. I think GCC doesn't implement it as well, hence the silent broken output :)

This is useful with linker relaxation, though, as it can decrease the number of relocations.

https://maskray.me/blog/2021-03-14-the-dark-side-of-riscv-linker-relaxation#code-addresses I am going to revise some paragraphs about DWARF.

Yes, this should be able to reduce the number of relocations at the cost of debug info size. However, given that we currently fail to emit the object file this seems like a good tradeoff.

See above.

[MaskRay]

There have been some changes in the relocation area. Is this patch unneeded now?

[MaskRay]

Pretty sure unneeded after https://reviews.llvm.org/D155357 completely fixed the requiresFixups heuristic problem :)

llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp

   assert(End->isDefined() && "Invalid end label");
 
   addLabelAddress(D, dwarf::DW_AT_low_pc, Begin);
-  if (DD->getDwarfVersion() < 4)
+  if (DD->getDwarfVersion() < 4 || Asm->TM.getTargetTriple().isRISCV())
     addLabelAddress(D, dwarf::DW_AT_high_pc, End);
   else
     addLabelDelta(D, dwarf::DW_AT_high_pc, End, Begin);

llvm/test/CodeGen/RISCV/fixups-diff.ll

 }
 
 ; CHECK:      Section {{.*}} .rela.debug_info {
-; CHECK:        0x22 R_RISCV_ADD32 - 0x0
-; CHECK-NEXT:   0x22 R_RISCV_SUB32 - 0x0
-; CHECK:        0x2B R_RISCV_ADD32 - 0x0
-; CHECK-NEXT:   0x2B R_RISCV_SUB32 - 0x0
+; CHECK:        0x22 R_RISCV_32 - 0x0
+; CHECK:        0x2B R_RISCV_32 - 0x0
 ; CHECK:      }
 
 ; CHECK:      Section {{.*}} .rela.eh_frame {

llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll

 
 ; Check that we actually have relocations, otherwise this is kind of pointless.
 ; READOBJ-RELOCS:  Section ({{.*}}) .rela.debug_info {
-; READOBJ-RELOCS:    0x1B R_RISCV_ADD32 - 0x0
-; READOBJ-RELOCS-NEXT:    0x1B R_RISCV_SUB32 - 0x0
+; READOBJ-RELOCS:    0x11 R_RISCV_32 - 0x0
 ; READOBJ-RELOCS:  Section ({{.*}}) .rela.debug_frame {
 ; READOBJ-RELOCS:    0x20 R_RISCV_ADD32 - 0x0
 ; READOBJ-RELOCS-NEXT:    0x20 R_RISCV_SUB32 - 0x0

 ; DWARF-DUMP: DW_AT_name      ("main")
 ; DWARF-DUMP: DW_AT_decl_file ("{{.*}}dwarf-riscv-relocs.c")
 ; DWARF-DUMP: DW_AT_decl_line (1)
-; DWARF-DUMP: DW_AT_type      (0x00000032 "int")
+; DWARF-DUMP: DW_AT_type      (0x0000002c "int")
 ; DWARF-DUMP: DW_AT_name      ("int")
 ; DWARF-DUMP: DW_AT_encoding  (DW_ATE_signed)
 ; DWARF-DUMP: DW_AT_byte_size (0x04)