[RISCV] Add new pass to transform undef to pseudo for vector values.

[BeMg]

Summary

RISC-V vector instruction has register overlapping constraint for certain
instructions, and will cause illegal instruction trap if violated, we use
early clobber to model this constraint, but it can't prevent register allocator
allocated same or overlapped if the input register is undef value, so convert
IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way
to resolve this. Ideally we should model the constraint right, but before we
model the constraint right, it's the approach to prevent that happen.

See also: https://github.com/llvm/llvm-project/issues/50157

[BeMg]

In D129735#3873448, @craig.topper wrote:

In D129735#3873436, @BeMg wrote:

In D129735#3871632, @craig.topper wrote:

Does this patch work for this test case

define internal void @foo() {
loopIR.preheader.i.i:
  %v15 = tail call <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
  %v17 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %v15, i64 0)
  %vs12.i.i.i = add <vscale x 1 x i16> %v15, shufflevector (<vscale x 1 x i16> insertelement (<vscale x 1 x i16> poison, i16 1, i32 0), <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer)
  %v18 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i, i64 0)
  %vs16.i.i.i = add <vscale x 1 x i16> %v15, shufflevector (<vscale x 1 x i16> insertelement (<vscale x 1 x i16> poison, i16 3, i32 0), <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer)
  %v20 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs16.i.i.i, i64 0)
  br label %loopIR3.i.i

loopIR3.i.i:                                      ; preds = %loopIR3.i.i, %loopIR.preheader.i.i
  %v37 = load <vscale x 8 x i8>, ptr addrspace(1) null, align 8
  %v38 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v17, i64 4)
  %v40 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v18, i64 4)
  %v42 = and <vscale x 8 x i8> %v38, %v40
  %v46 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v20, i64 4)
  %v60 = and <vscale x 8 x i8> %v42, %v46
  store <vscale x 8 x i8> %v60, ptr addrspace(1) null, align 4
  br label %loopIR3.i.i
}

declare <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()

declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16>, <vscale x 1 x i16>, i64 immarg) 

declare <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i16>, i64)

This IR doesn't generate the undef+early-clobber situation, so this pass will not work on it.

RA result will not break the early-clobber constraint in current compiler.

Corrsponding MachineInst before RA place below:

********** MACHINEINSTRS **********
# Machine code for function foo: NoPHIs, TracksLiveness, TiedOpsRewritten, TracksDebugUserValues

0B      bb.0.loopIR.preheader.i.i:
          successors: %bb.1(0x80000000); %bb.1(100.00%)

16B       dead %16:gpr = PseudoVSETVLIX0 $x0, 206, implicit-def $vl, implicit-def $vtype
32B       undef %0.sub_vrm1_0:vrm2 = PseudoVID_V_MF4 -1, 4, implicit $vl, implicit $vtype
64B       undef %1.sub_vrm1_0:vrm2 = PseudoVADD_VI_MF4 %0.sub_vrm1_0:vrm2, 1, -1, 4, implicit $vl, implicit $vtype
96B       undef %2.sub_vrm1_0:vrm2 = PseudoVADD_VI_MF4 %0.sub_vrm1_0:vrm2, 3, -1, 4, implicit $vl, implicit $vtype

128B    bb.1.loopIR3.i.i:
        ; predecessors: %bb.0, %bb.1
          successors: %bb.1(0x80000000); %bb.1(100.00%)

160B      %10:vr = VL1RE8_V $x0 :: (load unknown-size from `ptr addrspace(1) null`, align 8, addrspace 1)
176B      dead $x0 = PseudoVSETIVLI 4, 192, implicit-def $vl, implicit-def $vtype
192B      early-clobber %11:vr = PseudoVRGATHEREI16_VV_M1_M2 %10:vr, %0:vrm2, 4, 3, implicit $vl, implicit $vtype
208B      early-clobber %12:vr = PseudoVRGATHEREI16_VV_M1_M2 %10:vr, %1:vrm2, 4, 3, implicit $vl, implicit $vtype
224B      dead %17:gpr = PseudoVSETVLIX0 $x0, 192, implicit-def $vl, implicit-def $vtype
240B      %13:vr = PseudoVAND_VV_M1 %11:vr, %12:vr, -1, 3, implicit $vl, implicit $vtype
256B      dead $x0 = PseudoVSETIVLI 4, 192, implicit-def $vl, implicit-def $vtype
272B      early-clobber %14:vr = PseudoVRGATHEREI16_VV_M1_M2 %10:vr, %2:vrm2, 4, 3, implicit $vl, implicit $vtype
288B      dead %18:gpr = PseudoVSETVLIX0 $x0, 192, implicit-def $vl, implicit-def $vtype
304B      %15:vr = PseudoVAND_VV_M1 %13:vr, %14:vr, -1, 3, implicit $vl, implicit $vtype
320B      VS1R_V %15:vr, $x0 :: (store unknown-size into `ptr addrspace(1) null`, align 4, addrspace 1)
336B      PseudoBR %bb.1

Generated assembly see the note inline.

foo:                                    # @foo
	.cfi_startproc
# %bb.0:                                # %loopIR.preheader.i.i
	vsetvli	a0, zero, e16, mf4, ta, ma
	vid.v	v8
	vadd.vi	v10, v8, 1
	vadd.vi	v12, v8, 3
.LBB0_1:                                # %loopIR3.i.i
                                        # =>This Inner Loop Header: Depth=1
	vl1r.v	v14, (zero)
	vsetivli	zero, 4, e8, m1, ta, ma
	vrgatherei16.vv	v15, v14, v8  <- The v14 here is LMUL=2 so it's v14 and v15. This means writing v15 violated the early clobber constraint.
	vrgatherei16.vv	v16, v14, v10
	vsetvli	a0, zero, e8, m1, ta, ma
	vand.vv	v15, v15, v16
	vsetivli	zero, 4, e8, m1, ta, ma
	vrgatherei16.vv	v16, v14, v12
	vsetvli	a0, zero, e8, m1, ta, ma
	vand.vv	v14, v15, v16
	vs1r.v	v14, (zero)
	j	.LBB0_1
.Lfunc_end0:
	.size	foo, .Lfunc_end0-foo
	.cfi_endproc
                                        # -- End function
	.section	".note.GNU-stack","",@progbits

Is this MIR wrong here? Does %10 should be marked as vrm2?
Compiler treat %11 and %10 as M1, %0 as M2, so i think RA doesn't violated the early clobber constraint.

192B      early-clobber %11:vr = PseudoVRGATHEREI16_VV_M1_M2 %10:vr, %0:vrm2, 4, 3, implicit $vl, implicit $vtype
vrgatherei16.vv	v15, v14, v8 
// %11 -> v15
// %10 -> v14
// %0 -> v8

Compiler Register allocation result:

********** REWRITE VIRTUAL REGISTERS **********
********** Function: foo
********** REGISTER MAP **********
[%0 -> $v8m2] VRM2
[%1 -> $v10m2] VRM2
[%2 -> $v12m2] VRM2
[%10 -> $v14] VR
[%11 -> $v15] VR
[%12 -> $v16] VR
[%13 -> $v15] VR
[%14 -> $v16] VR
[%15 -> $v14] VR
[%16 -> $x10] GPR
[%17 -> $x10] GPR
[%18 -> $x10] GPR

[BeMg]

1. Update the approach that finding the VR super class.

[craig.topper]

In D129735#3873595, @BeMg wrote:

In D129735#3873448, @craig.topper wrote:

In D129735#3873436, @BeMg wrote:

In D129735#3871632, @craig.topper wrote:

Does this patch work for this test case

define internal void @foo() {
loopIR.preheader.i.i:
  %v15 = tail call <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
  %v17 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %v15, i64 0)
  %vs12.i.i.i = add <vscale x 1 x i16> %v15, shufflevector (<vscale x 1 x i16> insertelement (<vscale x 1 x i16> poison, i16 1, i32 0), <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer)
  %v18 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i, i64 0)
  %vs16.i.i.i = add <vscale x 1 x i16> %v15, shufflevector (<vscale x 1 x i16> insertelement (<vscale x 1 x i16> poison, i16 3, i32 0), <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer)
  %v20 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs16.i.i.i, i64 0)
  br label %loopIR3.i.i

loopIR3.i.i:                                      ; preds = %loopIR3.i.i, %loopIR.preheader.i.i
  %v37 = load <vscale x 8 x i8>, ptr addrspace(1) null, align 8
  %v38 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v17, i64 4)
  %v40 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v18, i64 4)
  %v42 = and <vscale x 8 x i8> %v38, %v40
  %v46 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v20, i64 4)
  %v60 = and <vscale x 8 x i8> %v42, %v46
  store <vscale x 8 x i8> %v60, ptr addrspace(1) null, align 4
  br label %loopIR3.i.i
}

declare <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()

declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16>, <vscale x 1 x i16>, i64 immarg) 

declare <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i16>, i64)

This IR doesn't generate the undef+early-clobber situation, so this pass will not work on it.

RA result will not break the early-clobber constraint in current compiler.

Corrsponding MachineInst before RA place below:

********** MACHINEINSTRS **********
# Machine code for function foo: NoPHIs, TracksLiveness, TiedOpsRewritten, TracksDebugUserValues

0B      bb.0.loopIR.preheader.i.i:
          successors: %bb.1(0x80000000); %bb.1(100.00%)

16B       dead %16:gpr = PseudoVSETVLIX0 $x0, 206, implicit-def $vl, implicit-def $vtype
32B       undef %0.sub_vrm1_0:vrm2 = PseudoVID_V_MF4 -1, 4, implicit $vl, implicit $vtype
64B       undef %1.sub_vrm1_0:vrm2 = PseudoVADD_VI_MF4 %0.sub_vrm1_0:vrm2, 1, -1, 4, implicit $vl, implicit $vtype
96B       undef %2.sub_vrm1_0:vrm2 = PseudoVADD_VI_MF4 %0.sub_vrm1_0:vrm2, 3, -1, 4, implicit $vl, implicit $vtype

128B    bb.1.loopIR3.i.i:
        ; predecessors: %bb.0, %bb.1
          successors: %bb.1(0x80000000); %bb.1(100.00%)

160B      %10:vr = VL1RE8_V $x0 :: (load unknown-size from `ptr addrspace(1) null`, align 8, addrspace 1)
176B      dead $x0 = PseudoVSETIVLI 4, 192, implicit-def $vl, implicit-def $vtype
192B      early-clobber %11:vr = PseudoVRGATHEREI16_VV_M1_M2 %10:vr, %0:vrm2, 4, 3, implicit $vl, implicit $vtype
208B      early-clobber %12:vr = PseudoVRGATHEREI16_VV_M1_M2 %10:vr, %1:vrm2, 4, 3, implicit $vl, implicit $vtype
224B      dead %17:gpr = PseudoVSETVLIX0 $x0, 192, implicit-def $vl, implicit-def $vtype
240B      %13:vr = PseudoVAND_VV_M1 %11:vr, %12:vr, -1, 3, implicit $vl, implicit $vtype
256B      dead $x0 = PseudoVSETIVLI 4, 192, implicit-def $vl, implicit-def $vtype
272B      early-clobber %14:vr = PseudoVRGATHEREI16_VV_M1_M2 %10:vr, %2:vrm2, 4, 3, implicit $vl, implicit $vtype
288B      dead %18:gpr = PseudoVSETVLIX0 $x0, 192, implicit-def $vl, implicit-def $vtype
304B      %15:vr = PseudoVAND_VV_M1 %13:vr, %14:vr, -1, 3, implicit $vl, implicit $vtype
320B      VS1R_V %15:vr, $x0 :: (store unknown-size into `ptr addrspace(1) null`, align 4, addrspace 1)
336B      PseudoBR %bb.1

Generated assembly see the note inline.

foo:                                    # @foo
	.cfi_startproc
# %bb.0:                                # %loopIR.preheader.i.i
	vsetvli	a0, zero, e16, mf4, ta, ma
	vid.v	v8
	vadd.vi	v10, v8, 1
	vadd.vi	v12, v8, 3
.LBB0_1:                                # %loopIR3.i.i
                                        # =>This Inner Loop Header: Depth=1
	vl1r.v	v14, (zero)
	vsetivli	zero, 4, e8, m1, ta, ma
	vrgatherei16.vv	v15, v14, v8  <- The v14 here is LMUL=2 so it's v14 and v15. This means writing v15 violated the early clobber constraint.
	vrgatherei16.vv	v16, v14, v10
	vsetvli	a0, zero, e8, m1, ta, ma
	vand.vv	v15, v15, v16
	vsetivli	zero, 4, e8, m1, ta, ma
	vrgatherei16.vv	v16, v14, v12
	vsetvli	a0, zero, e8, m1, ta, ma
	vand.vv	v14, v15, v16
	vs1r.v	v14, (zero)
	j	.LBB0_1
.Lfunc_end0:
	.size	foo, .Lfunc_end0-foo
	.cfi_endproc
                                        # -- End function
	.section	".note.GNU-stack","",@progbits

Is this MIR wrong here? Does %10 should be marked as vrm2?
Compiler treat %11 and %10 as M1, %0 as M2, so i think RA doesn't violated the early clobber constraint.

192B      early-clobber %11:vr = PseudoVRGATHEREI16_VV_M1_M2 %10:vr, %0:vrm2, 4, 3, implicit $vl, implicit $vtype
vrgatherei16.vv	v15, v14, v8 
// %11 -> v15
// %10 -> v14
// %0 -> v8

Compiler Register allocation result:

********** REWRITE VIRTUAL REGISTERS **********
********** Function: foo
********** REGISTER MAP **********
[%0 -> $v8m2] VRM2
[%1 -> $v10m2] VRM2
[%2 -> $v12m2] VRM2
[%10 -> $v14] VR
[%11 -> $v15] VR
[%12 -> $v16] VR
[%13 -> $v15] VR
[%14 -> $v16] VR
[%15 -> $v14] VR
[%16 -> $x10] GPR
[%17 -> $x10] GPR
[%18 -> $x10] GPR

You're right. I mixed up the operand order. I need to go look at this test again. It used to fail. Maybe we fixed it some other way.

[craig.topper]

I remember now. It only miscompiles with -riscv-enable-subreg-liveness

That produces

foo:                                    # @foo
        .cfi_startproc
# %bb.0:                                # %loopIR.preheader.i.i
        vsetvli a0, zero, e16, mf4, ta, ma
        vid.v   v8
        vadd.vi v10, v8, 1
        vadd.vi v12, v8, 3
.LBB0_1:                                # %loopIR3.i.i
                                        # =>This Inner Loop Header: Depth=1
        vl1r.v  v9, (zero)
        vsetivli        zero, 4, e8, m1, ta, ma
        vrgatherei16.vv v11, v9, v8
        vrgatherei16.vv v13, v9, v10
        vsetvli a0, zero, e8, m1, ta, ma
        vand.vv v11, v11, v13
        vsetivli        zero, 4, e8, m1, ta, ma
        vrgatherei16.vv v13, v9, v12 <- this instruction violates the early clobber constraint
        vsetvli a0, zero, e8, m1, ta, ma
        vand.vv v9, v11, v13
        vs1r.v  v9, (zero)
        j       .LBB0_1
.Lfunc_end0:
        .size   foo, .Lfunc_end0-foo
        .cfi_endproc
                                        # -- End function                        
        .section        ".note.GNU-stack","",@progbits

[BeMg]

Replace Insert_subreg with PesudoInit when subreg liveness is enabled.

[BeMg]

In D129735#3875529, @craig.topper wrote:

I remember now. It only miscompiles with -riscv-enable-subreg-liveness

That produces

foo:                                    # @foo
        .cfi_startproc
# %bb.0:                                # %loopIR.preheader.i.i
        vsetvli a0, zero, e16, mf4, ta, ma
        vid.v   v8
        vadd.vi v10, v8, 1
        vadd.vi v12, v8, 3
.LBB0_1:                                # %loopIR3.i.i
                                        # =>This Inner Loop Header: Depth=1
        vl1r.v  v9, (zero)
        vsetivli        zero, 4, e8, m1, ta, ma
        vrgatherei16.vv v11, v9, v8
        vrgatherei16.vv v13, v9, v10
        vsetvli a0, zero, e8, m1, ta, ma
        vand.vv v11, v11, v13
        vsetivli        zero, 4, e8, m1, ta, ma
        vrgatherei16.vv v13, v9, v12 <- this instruction violates the early clobber constraint
        vsetvli a0, zero, e8, m1, ta, ma
        vand.vv v9, v11, v13
        vs1r.v  v9, (zero)
        j       .LBB0_1
.Lfunc_end0:
        .size   foo, .Lfunc_end0-foo
        .cfi_endproc
                                        # -- End function                        
        .section        ".note.GNU-stack","",@progbits

Add one more condtion for subreg-liveness.

The assembly show as below:

        .p2align        2                               # -- Begin function foo
        .type   foo,@function
foo:                                    # @foo
        .cfi_startproc
# %bb.0:                                # %loopIR.preheader.i.i
        vsetvli a0, zero, e16, mf4, ta, ma
        vid.v   v14
        vadd.vi v15, v14, 1
        vadd.vi v16, v14, 3
        vmv1r.v v8, v14
        vmv1r.v v10, v15
        vmv1r.v v12, v16
.LBB0_1:                                # %loopIR3.i.i
                                        # =>This Inner Loop Header: Depth=1
        vl1r.v  v14, (zero)
        vsetivli        zero, 4, e8, m1, ta, ma
        vrgatherei16.vv v15, v14, v8
        vrgatherei16.vv v16, v14, v10
        vsetvli a0, zero, e8, m1, ta, ma
        vand.vv v15, v15, v16
        vsetivli        zero, 4, e8, m1, ta, ma
        vrgatherei16.vv v16, v14, v12
        vsetvli a0, zero, e8, m1, ta, ma
        vand.vv v14, v15, v16
        vs1r.v  v14, (zero)
        j       .LBB0_1
.Lfunc_end0:
        .size   foo, .Lfunc_end0-foo
        .cfi_endproc
                                        # -- End function
        .section        ".note.GNU-stack","",@progbits

[BeMg]

Handle subregister liveness situation

[BeMg]

Avoid infinite loop by DenseMap

[kito-cheng]

llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll

1

Could you add a pre-commit patch for this testcase so that could easier demonstrate what's get fixed?

[kito-cheng]

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

50

SmallPtrSet for Seen

[BeMg]

Change DenseMap into SmallPrtSet

[BeMg]

llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll

1

New patch https://reviews.llvm.org/D137763 for test only and set up the dependency.

Should I remove the testcase in this patch?

[BeMg]

Update testcase

[BeMg]

1. Record PHI node subregister change
2. New INSERT_SUBREG insert before early-clobber instruciton
3. Subreg index computation include PHI node

[BeMg]

Handle Sub-register undef+early-clobber

For sub-registers, there is the same issue. The register allocator will also generate the program that breaks the early-clobber constraint. The reason for this situation is that the partial register used in instruction (with early-clobber flag) is undef. For example:

early-clobber %12:vr = PseudoVRGATHEREI16_VV_M1_M2 %10:vr, %1:vrm2, 4, 3, implicit $vl, implicit $vtype

->

vrgatherei16.vv v13, v9, v12

v12 is selected as VRM2, it will occupy the v12~v13. The register allocator still allocates the v13 for %12:vrm2 due to the v13 is undef for %1:vr in the register allocation stage. This is an example of how an undef subregister breaks the early-clobber constraint in the register allocation stage.

Here we propose an approach to fix this problem. The concept is the same as a normal undef register situation. We define the sub-register with pseudo instruction and remove it in the later pass (after RA).

There are three steps for this approach:

1. Select the def-use chain from implicit_def to the first user with early-clobber constraint
2. Compute the undef sub-register index from collecting information from INSERT_SUBREG and PHI node
3. Insert the PseudoInit and INSERT_SUBREG for undefined sub-register after the last INSERT_SUGREG that updates the sub-register

Here we show the example with the pattern that will trigger undef+early-clobber issue.

Step 1

There are three def-use chains we need to care about in this program.

The pattern will look like

v0 = Implicit_def
…
INSERT_SUBREG | COPY | PHI
…
early-clobber rd = Op vN

Step 2

The INSERT_SUBREG node third operand is subregister index. It shows that this node defines which sub-register in the whole register. We can use the information to construct the sub-register that is undefined.

We use the LaneBitMask for this purpose.

LaneBitmask == 0xC for whole VRM2 register
LaneBitmask == 0x4 for %subreg.sub_vrm1_0 
LaneBitmask == 0x8 for %subreg.sub_vrm1_1

If we get the following def-use chain in step1

%4:vrm2 = Implicit_def
%0:vrm2 = INSERT_SUBREG %4, %subreg.sub_vrm1_0
early-clobber %11:vr = Op %0

0xC is VRM2’s LaneBitMask and 0x4 is already defined by INSERT_SUBREG in the program.

0xC & ~0x4 = 0x8 -> subreg.sub_vrm1_1

In this case, subreg.sub_vrm1_1 is the undefined sub-register before being used by early-clobber instruction.

Step 3

We can define a sub-register by INSERT_SUBREG between the last INSERT_SUBREG and the user with early-clobber. Our goal is to make sure the sub-registers are all defined before being used by early-clobber instruction.

%4:vrm2 = Implicit_def
%0:vrm2 = INSERT_SUBREG %4, %subreg.sub_vrm1_0
early-clobber %11:vr = Op %0

->

%4:vrm2 = Implicit_def
%0:vrm2 = INSERT_SUBREG %4, %subreg.sub_vrm1_0
%21:vr = PseudoRVVInitUndefM1
%22:vrm2 = INSERT_SUBREG %1:vrm2, %21:vr, %subreg.sub_vrm1_1
early-clobber %11:vr = Op %22

PHI in def-use chain

In Step 2, PHI will be seen as another instruction that will change the subregister defined region. The PHINodeLaneBitRecord will record the LaneBitMask from both predecessors, and insert the INSERT_SUBREG with this information.

[BeMg]

Update testcase

[craig.topper]

pseudo is misspelled in the title

[craig.topper]

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

2

pesudo -> pseudo

11

"pesudo" -> "pseudo" in two places

19

pesudo -> pseudo

19

latter -> later

246

Pesudo -> Pseudo

247

regitser -> register

289

Candidata -> Candidate?

llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll

28

Are we treating insert_subreg for segment load tuples the same as inserting a small LMUL into a wider LMUL?

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber-vrm4.mir

118 ↗

(On Diff #478437)

Why is there an PseudoRVVInitUnde pseudo in the IR before the pass runs?

[craig.topper]

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

74

You can pass Register by value

106

origin -> original

111

Can't we do something like

VRRegClass.hasSubClassEq(MRI->getRegClass(R)) ||
VRM2RegClass.hasSubClassEq(MRI->getRegClass(R)) ||
VRM4RegClass.hasSubClassEq(MRI->getRegClass(R)) ||
VRM8RegClass.hasSubClassEq(MRI->getRegClass(R))

why do we need to use getVRLargestSuperClass?

[BeMg]

1. Fix spell
2. Update isVectorRegClass

[BeMg]

1. Rplace PseudoRVVInitUndef with VLE in MIR test
2. Move MIR test into precommit

[BeMg]

llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll

28

This pass doesn't consider segment load as instruction that assign sub-register.

The following Insert_subreg work like put %5:vrm2 into %6:vrm4

%1:vrm4 = IMPLICIT_DEF
%5:vrm2 = PseudoVLE32_V_M2 killed %4, 0, 5 /* e32 */
%6:vrm4 = INSERT_SUBREG %1, %5, %subreg.sub_vrm2_0

Do we should treat vloxseg2ei32 as INSERT_SUBREG in this patch?

[BeMg]

Ping

[craig.topper]

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

172

Why passing Insts by value? That will make a copy but it doesn't look like we need a copy.

182

Why passing Insts by value? That will make a copy but it doesn't look like we need a copy.

183

unsigned -> Register

197

unsigned -> Register

197

Why passing Insts by value? That will make a copy but it doesn't look like we need a copy.

200

unsigned -> Register

299

unsigned -> Register

300

unsigned -> Register

313

createVirtualRegister returns Register not unsigned

317

createVirtualRegister returns Register not unsigned

llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll

28

Nevermind, I didn't realize this test had so many undef and poison operands. I suspect llvm-reduce or bugpoint. I dislike tests with undef/poison operands. It makes things very fragile. It would be legal for DAG combine to delete a large portion of this test.

[craig.topper]

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

279

"the " is unnecessary in this sentence

[craig.topper]

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

28

"is be occupied" -> "is occupied"

[craig.topper]

Is it possible to insert the PseudoRVVInitUndef instructions after we've left SSA and the LiveIntervals have been built. Would that make it easier to find the undef lanes?

[BeMg]

1. unsigned -> Register
2. use const std::vector<MachineInstr *> & instead of call by value

[BeMg]

rebase

[BeMg]

Reuse DetectDeadLanes pass info for undefined subregister

[BeMg]

Move DetectDeadLanes pass change into another patch

[craig.topper]

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

202

Isn't this calculating for the entire function? But handleSubReg is called for individual instructions. So we'll be recomputing information right?

[arsenm]

This could certainly use some new MIR tests. I didn't look super closely but I'm not sure you're correctly handling undef vs. not-undef subreg defs

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

54

DenseMap

91–101

I don't understand the point of this function, getSuperClasses is already sorted by largest. You can just take the first?

106

Could this use the new getPhysRegBaseClass?

108

Don't call getRegClass for each use

142

Reg.isVirtual()

201

unique_ptr

[BeMg]

1. Use unique_ptr for VRegInfo
2. Only run once DetectDeadLanes for each function
3. Remove Seen and PHINodeLaneBitRecord
4. Only call getRegClass once

[BeMg]

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

91–101

When this function take VRNoV0RegClassID as input. the getSuperClasses will return as following order.

AnyRegRegClassID 1
VMRegClassID 20
VRRegClassID 21 <- stop here
...

This patch only want those four RegClass as result.

106

Could this hook use for virtual register? It seem only for physical register but this pass run before register allocation.

202

Yes, you're right. we don't need recompute this info for each instruction. It call only once now.

[BeMg]

Add more subregister testcase

[craig.topper]

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

40

Are there any maps in the code anymore?

llvm/test/CodeGen/RISCV/O3-pipeline.ll

107

If I understand correctly, we're effectively running DetectDeadLanes inside of RISCV init undef pass and then running the real DetectDeadLanes pass which won't do anything because we already did it?

[craig.topper]

llvm/test/CodeGen/RISCV/O3-pipeline.ll

107

Can we run DetectDeadLanes, then run our pass and just use the portion of the DetectDeadLanes that computes the Lane Masks in our pass?

[BeMg]

1. Move init undef pass after DetectDeadLanes
2. Remove <map>

[craig.topper]

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

282

Should this be std::unique_ptr<VRegInfo[]> since it points to an array?

[BeMg]

Update std::unique_ptr<VRegInfo> with std::unique_ptr<VRegInfo[]>

[BeMg]

rebase

[BeMg]

rebase

[BeMg]

rebaseY

[BeMg]

Use D141993 as DetectDeadLane user interface

[craig.topper]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

149

I kind of think we should keep these instructions all the way to RISCVAsmPrinter::emitInstruction. Setting the operands to "undef" says it is ok to change the operands after this pass runs, but its not. RISCVExpandPseudo runs late enough there is probably no pass that will change them. Keeping the pseudo all the way to RISCVAsmPrinter::emitInstruction removes any possibility.

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

88

Can this be

if (RISCV::VRM8RegClass.hasSubClassEq(RC))
  return &RISCV::VRM8RegClass;
if (RISCV::VRM4RegClass.hasSubClassEq(RC))
  return &RISCV::VRM4RegClass;
if (RISCV::VRM2RegClass.hasSubClassEq(RC))
  return &RISCV::VRM2RegClass;
if (RISCV::VRRegClass.hasSubClassEq(RC))
  return &RISCV::VRRegClass;
return RC;

117

return RISCV::PseudoRVVInitUndefM1;

152

Do we need to scan all operands? Can we check if MO is a tied use and find the operand it is tied to check the early clobber?

188

Use defs()?

188

Replace the place with llvm::any_of?

201

Can we scan uses() instead of operands()?

206

I think we wouldn't need this if we only checked uses?

229

Can we put Info.UsedLanes & ~Info.DefinedLanes into a variable? We use that expression twice

232

Lastest isn't a word

[BeMg]

1. Skip undef-init pseudo in ASMEmitter instead of removing it in PseudoExpend pass
2. Update operands with defs() or uses()
3. Fix some typo
4. Use variable to represent Info.UsedLanes & ~Info.DefinedLanes

[BeMg]

Remove removeTempRVVInitUndef declaration

[BeMg]

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

152

0B      bb.0.entry:
16B       LIFETIME_START %stack.0.dst
32B       %1:vr = IMPLICIT_DEF
48B       early-clobber %0:vr = PseudoVRGATHER_VI_M1 killed %1:vr, 0, 0, 5
64B       %2:gpr = ADDI %stack.0.dst, 0
80B       PseudoVSE32_V_M1 killed %0:vr, killed %2:gpr, 0, 5
96B       LIFETIME_END %stack.0.dst
112B      %3:gpr = COPY $x0
128B      $x10 = COPY %3:gpr
144B      PseudoRET implicit $x10

Here we maybe need scan both defs and uses operand, because the early-clobber operand not always exist tied-to operand.

[BeMg]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

149

Skip PseudoRVVInitUndefM1|2|4|8 in RISCVAsmPrinter::emitInstruction and remove undef-init relate function in RISCVExpandPseudo.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

152

Right. I wasn't thinking about that right.

[fmayer]

It seems like this breaks under ASan: https://lab.llvm.org/buildbot/#/builders/5/builds/31529/steps/13/logs/stdio

FAIL: LLVM :: CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll (35389 of 72944)
******************** TEST 'LLVM :: CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll' FAILED ********************
Script:
--
: 'RUN: at line 2';   /b/sanitizer-x86_64-linux-fast/build/llvm_build_asan/bin/llc -mtriple=riscv64 -mattr=+f,+m,+zfh,+experimental-zvfh    -riscv-enable-subreg-liveness=false < /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll | /b/sanitizer-x86_64-linux-fast/build/llvm_build_asan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
: 'RUN: at line 4';   /b/sanitizer-x86_64-linux-fast/build/llvm_build_asan/bin/llc -mtriple=riscv64 -mattr=+f,+m,+zfh,+experimental-zvfh < /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll    -riscv-enable-subreg-liveness=true| /b/sanitizer-x86_64-linux-fast/build/llvm_build_asan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll --check-prefix=SUBREGLIVENESS
--
Exit Code: 2
Command Output (stderr):
--
=================================================================
==924420==ERROR: AddressSanitizer: use-after-poison on address 0x62100002da58 at pc 0x564ad06d209e bp 0x7ffe116375f0 sp 0x7ffe116375e8
READ of size 8 at 0x62100002da58 thread T0
    #0 0x564ad06d209d in operands_begin /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/include/llvm/CodeGen/MachineInstr.h:635:42
    #1 0x564ad06d209d in defs /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/include/llvm/CodeGen/MachineInstr.h:679:23
    #2 0x564ad06d209d in isEarlyClobberMI /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:175:26
    #3 0x564ad06d209d in processBasicBlock /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:250:39
    #4 0x564ad06d209d in (anonymous namespace)::RISCVInitUndef::runOnMachineFunction(llvm::MachineFunction&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:270:16
    #5 0x564ad2aa92d2 in llvm::MachineFunctionPass::runOnFunction(llvm::Function&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/MachineFunctionPass.cpp:91:13
    #6 0x564ad39ba4a3 in llvm::FPPassManager::runOnFunction(llvm::Function&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1430:27
    #7 0x564ad39d4140 in llvm::FPPassManager::runOnModule(llvm::Module&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1476:16
    #8 0x564ad39bc312 in runOnModule /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1545:27
    #9 0x564ad39bc312 in llvm::legacy::PassManagerImpl::run(llvm::Module&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:535:44
    #10 0x564acd741a10 in compileModule /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/tools/llc/llc.cpp:733:8
    #11 0x564acd741a10 in main /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/tools/llc/llc.cpp:420:22
    #12 0x7f2985940d8f  (/lib/x86_64-linux-gnu/libc.so.6+0x29d8f) (BuildId: 69389d485a9793dbe873f0ea2c93e02efaa9aa3d)
    #13 0x7f2985940e3f in __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x29e3f) (BuildId: 69389d485a9793dbe873f0ea2c93e02efaa9aa3d)
    #14 0x564acd66dba4 in _start (/b/sanitizer-x86_64-linux-fast/build/llvm_build_asan/bin/llc+0x7670ba4)
0x62100002da58 is located 2392 bytes inside of 4096-byte region [0x62100002d100,0x62100002e100)
allocated by thread T0 here:
    #0 0x564acd72db32 in operator new(unsigned long, std::align_val_t) /b/sanitizer-x86_64-linux-fast/build/llvm-project/compiler-rt/lib/asan/asan_new_delete.cpp:107:3
    #1 0x564acdc2908d in Allocate /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/include/llvm/Support/AllocatorBase.h:86:12
    #2 0x564acdc2908d in StartNewSlab /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/include/llvm/Support/Allocator.h:339:42
    #3 0x564acdc2908d in llvm::BumpPtrAllocatorImpl<llvm::MallocAllocator, 4096ul, 4096ul, 128ul>::Allocate(unsigned long, llvm::Align) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/include/llvm/Support/Allocator.h:195:5
    #4 0x564ad2a81869 in Allocate /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/include/llvm/Support/Allocator.h:209:12
    #5 0x564ad2a81869 in operator new<llvm::MallocAllocator, 4096UL, 4096UL, 128UL> /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/include/llvm/Support/Allocator.h:443:20
    #6 0x564ad2a81869 in llvm::MachineFunction::init() /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/MachineFunction.cpp:185:15
    #7 0x564ad2b43c17 in llvm::MachineModuleInfo::getOrCreateMachineFunction(llvm::Function&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/MachineModuleInfo.cpp:108:14
    #8 0x564ad2aa8def in llvm::MachineFunctionPass::runOnFunction(llvm::Function&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/MachineFunctionPass.cpp:46:29
    #9 0x564ad39ba4a3 in llvm::FPPassManager::runOnFunction(llvm::Function&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1430:27
    #10 0x564ad39d4140 in llvm::FPPassManager::runOnModule(llvm::Module&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1476:16
    #11 0x564ad39bc312 in runOnModule /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1545:27
    #12 0x564ad39bc312 in llvm::legacy::PassManagerImpl::run(llvm::Module&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:535:44
    #13 0x564acd741a10 in compileModule /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/tools/llc/llc.cpp:733:8
    #14 0x564acd741a10 in main /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/tools/llc/llc.cpp:420:22
    #15 0x7f2985940d8f  (/lib/x86_64-linux-gnu/libc.so.6+0x29d8f) (BuildId: 69389d485a9793dbe873f0ea2c93e02efaa9aa3d)
SUMMARY: AddressSanitizer: use-after-poison /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/include/llvm/CodeGen/MachineInstr.h:635:42 in operands_begin
Shadow bytes around the buggy address:
  0x0c427fffdaf0: 00 f7 00 00 00 00 00 00 00 00 00 f7 00 00 00 00
  0x0c427fffdb00: 00 00 00 00 00 00 00 00 00 00 00 00 f7 00 00 00
  0x0c427fffdb10: 00 00 00 00 00 00 f7 00 00 00 00 00 00 00 00 00
  0x0c427fffdb20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  0x0c427fffdb30: 00 00 00 00 00 00 00 f7 00 00 00 00 00 00 00 00
=>0x0c427fffdb40: 00 f7 00 00 00 00 f7 f7 f7 f7 f7[f7]f7 f7 f7 f7
  0x0c427fffdb50: f7 00 00 00 00 f7 00 00 00 00 00 00 00 00 00 f7
  0x0c427fffdb60: 00 00 00 00 00 00 00 00 f7 00 00 00 00 00 00 00
  0x0c427fffdb70: 00 00 f7 00 00 00 00 00 00 00 00 00 00 00 00 00
  0x0c427fffdb80: 00 00 00 f7 00 00 00 00 00 00 00 00 00 f7 00 00
  0x0c427fffdb90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f7 00
Shadow byte legend (one shadow byte represents 8 application bytes):
  Addressable:           00
  Partially addressable: 01 02 03 04 05 06 07 
  Heap left redzone:       fa
  Freed heap region:       fd
  Stack left redzone:      f1
  Stack mid redzone:       f2
  Stack right redzone:     f3
  Stack after return:      f5
  Stack use after scope:   f8
  Global redzone:          f9
  Global init order:       f6
  Poisoned by user:        f7
  Container overflow:      fc
  Array cookie:            ac
  Intra object redzone:    bb
  ASan internal:           fe
  Left alloca redzone:     ca
  Right alloca redzone:    cb
==924420==ABORTING
FileCheck error: '<stdin>' is empty.
FileCheck command line:  /b/sanitizer-x86_64-linux-fast/build/llvm_build_asan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll --check-prefix=SUBREGLIVENESS
--
********************
Testing:  0.. 10.. 20.. 30.. 40..
FAIL: LLVM :: CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll (35659 of 72944)
******************** TEST 'LLVM :: CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll' FAILED ********************
Script:
--
: 'RUN: at line 2';   /b/sanitizer-x86_64-linux-fast/build/llvm_build_asan/bin/llc -mtriple riscv64 -mattr=+v -riscv-enable-subreg-liveness < /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll  | /b/sanitizer-x86_64-linux-fast/build/llvm_build_asan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
--
Exit Code: 2
Command Output (stderr):
--
=================================================================
==928893==ERROR: AddressSanitizer: use-after-poison on address 0x62100005a980 at pc 0x55a20925a09e bp 0x7ffebd9ed930 sp 0x7ffebd9ed928
READ of size 8 at 0x62100005a980 thread T0
    #0 0x55a20925a09d in operands_begin /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/include/llvm/CodeGen/MachineInstr.h:635:42
    #1 0x55a20925a09d in defs /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/include/llvm/CodeGen/MachineInstr.h:679:23
    #2 0x55a20925a09d in isEarlyClobberMI /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:175:26
    #3 0x55a20925a09d in processBasicBlock /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:250:39
    #4 0x55a20925a09d in (anonymous namespace)::RISCVInitUndef::runOnMachineFunction(llvm::MachineFunction&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:270:16
    #5 0x55a20b6312d2 in llvm::MachineFunctionPass::runOnFunction(llvm::Function&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/MachineFunctionPass.cpp:91:13
    #6 0x55a20c5424a3 in llvm::FPPassManager::runOnFunction(llvm::Function&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1430:27
    #7 0x55a20c55c140 in llvm::FPPassManager::runOnModule(llvm::Module&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1476:16
    #8 0x55a20c544312 in runOnModule /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1545:27
    #9 0x55a20c544312 in llvm::legacy::PassManagerImpl::run(llvm::Module&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:535:44
    #10 0x55a2062c9a10 in compileModule /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/tools/llc/llc.cpp:733:8
    #11 0x55a2062c9a10 in main /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/tools/llc/llc.cpp:420:22
    #12 0x7f2447396d8f  (/lib/x86_64-linux-gnu/libc.so.6+0x29d8f) (BuildId: 69389d485a9793dbe873f0ea2c93e02efaa9aa3d)
    #13 0x7f2447396e3f in __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x29e3f) (BuildId: 69389d485a9793dbe873f0ea2c93e02efaa9aa3d)
    #14 0x55a2061f5ba4 in _start (/b/sanitizer-x86_64-linux-fast/build/llvm_build_asan/bin/llc+0x7670ba4)
0x62100005a980 is located 2176 bytes inside of 4096-byte region [0x62100005a100,0x62100005b100)
allocated by thread T0 here:
    #0 0x55a2062b5b32 in operator new(unsigned long, std::align_val_t) /b/sanitizer-x86_64-linux-fast/build/llvm-project/compiler-rt/lib/asan/asan_new_delete.cpp:107:3
    #1 0x55a2067b108d in Allocate /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/include/llvm/Support/AllocatorBase.h:86:12
    #2 0x55a2067b108d in StartNewSlab /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/include/llvm/Support/Allocator.h:339:42
    #3 0x55a2067b108d in llvm::BumpPtrAllocatorImpl<llvm::MallocAllocator, 4096ul, 4096ul, 128ul>::Allocate(unsigned long, llvm::Align) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/include/llvm/Support/Allocator.h:195:5
    #4 0x55a20b609869 in Allocate /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/include/llvm/Support/Allocator.h:209:12
    #5 0x55a20b609869 in operator new<llvm::MallocAllocator, 4096UL, 4096UL, 128UL> /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/include/llvm/Support/Allocator.h:443:20
    #6 0x55a20b609869 in llvm::MachineFunction::init() /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/MachineFunction.cpp:185:15
    #7 0x55a20b6cbc17 in llvm::MachineModuleInfo::getOrCreateMachineFunction(llvm::Function&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/MachineModuleInfo.cpp:108:14
    #8 0x55a20b630def in llvm::MachineFunctionPass::runOnFunction(llvm::Function&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/CodeGen/MachineFunctionPass.cpp:46:29
    #9 0x55a20c5424a3 in llvm::FPPassManager::runOnFunction(llvm::Function&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1430:27
    #10 0x55a20c55c140 in llvm::FPPassManager::runOnModule(llvm::Module&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1476:16
    #11 0x55a20c544312 in runOnModule /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1545:27
    #12 0x55a20c544312 in llvm::legacy::PassManagerImpl::run(llvm::Module&) /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:535:44
    #13 0x55a2062c9a10 in compileModule /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/tools/llc/llc.cpp:733:8
    #14 0x55a2062c9a10 in main /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/tools/llc/llc.cpp:420:22
    #15 0x7f2447396d8f  (/lib/x86_64-linux-gnu/libc.so.6+0x29d8f) (BuildId: 69389d485a9793dbe873f0ea2c93e02efaa9aa3d)
SUMMARY: AddressSanitizer: use-after-poison /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/include/llvm/CodeGen/MachineInstr.h:635:42 in operands_begin
Shadow bytes around the buggy address:
  0x0c42800034e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  0x0c42800034f0: 00 f7 00 00 00 00 00 00 00 00 00 f7 00 00 00 00
  0x0c4280003500: f7 00 00 00 00 00 00 00 00 00 f7 00 00 00 00 00
  0x0c4280003510: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  0x0c4280003520: 00 00 00 00 00 00 00 00 00 00 00 f7 f7 f7 f7 f7
=>0x0c4280003530:[f7]f7 f7 f7 f7 f7 00 00 00 00 f7 00 00 00 00 00
  0x0c4280003540: 00 00 00 00 f7 00 00 00 00 00 00 00 00 00 00 00
  0x0c4280003550: 00 00 00 00 00 f7 00 00 00 00 00 00 00 00 00 f7
  0x0c4280003560: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  0x0c4280003570: f7 00 00 00 00 00 00 00 00 00 f7 00 00 00 00 f7
  0x0c4280003580: 00 00 00 00 00 00 00 00 00 f7 00 00 00 00 00 00
Shadow byte legend (one shadow byte represents 8 application bytes):
  Addressable:           00
  Partially addressable: 01 02 03 04 05 06 07 
  Heap left redzone:       fa
  Freed heap region:       fd
  Stack left redzone:      f1
  Stack mid redzone:       f2
  Stack right redzone:     f3
  Stack after return:      f5
  Stack use after scope:   f8
  Global redzone:          f9
  Global init order:       f6
  Poisoned by user:        f7
  Container overflow:      fc
  Array cookie:            ac
  Intra object redzone:    bb
  ASan internal:           fe
  Left alloca redzone:     ca
  Right alloca redzone:    cb
==928893==ABORTING
FileCheck error: '<stdin>' is empty.
FileCheck command line:  /b/sanitizer-x86_64-linux-fast/build/llvm_build_asan/bin/FileCheck /b/sanitizer-x86_64-linux-fast/build/llvm-project/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll

[MaskRay]

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

2

RISCVRVVInitUndef.cpp

216

delete blank line

[craig.topper]

Removing my approval until the asan failure is fixed

[BeMg]

1. Update comment
2. Remove blank line
3. Use the old version isEarlyClobberMI

[craig.topper]

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

176

Any idea why the llvm::any_of didn't work?

[jrtc27]

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

176

Because the thing that calls this is erasing from the MBB whilst it iterates over it... so this is the wrong fix and probably doesn't even work either

[BeMg]

1. Restore any_of version isEarlyClobberMI
2. handleImplicitDef will remove ImplicitDef MI, and be use in following for loop body. I think this is the reason it trigger ASan fail.

[craig.topper]

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

176

Do we need [&] here or would [] work?

[BeMg]

1. Rename some variables name (UserMOs -> UseMOs, UseMO -> UserMO)
2. Reorder if statement in processBasicBlock
3. Use [] instead of [&] because the body of the function doesn't use any variables other than DefMO.

[craig.topper]

LGTM

[garthlei]

1.ll24 KBDownload

Illegal instructions "vslideup.vi v8, v8, 5" and "vslideup.vi v8, v8, 2" are generated.

[craig.topper]

In D129735#4640476, @garthlei wrote:

1.ll24 KBDownload

Illegal instructions "vslideup.vi v8, v8, 5" and "vslideup.vi v8, v8, 2" are generated.

Looks like the undef operand is not the passthru operand in this case. It's the value to slide. This pass only fixed the case where the passthru was undef. Can you file a new issue?

llvm/lib/Target/RISCV/CMakeLists.txt

add_llvm_target(RISCVCodeGen
   RISCVLegalizerInfo.cpp
   RISCVMachineFunctionInfo.cpp
   RISCVMacroFusion.cpp
   RISCVMCInstLower.cpp
   RISCVMergeBaseOffset.cpp
   RISCVRedundantCopyElimination.cpp
   RISCVRegisterBankInfo.cpp
   RISCVRegisterInfo.cpp
+  RISCVRVVInitUndef.cpp
   RISCVSExtWRemoval.cpp
   RISCVSubtarget.cpp
   RISCVTargetMachine.cpp
   RISCVTargetObjectFile.cpp
   RISCVTargetTransformInfo.cpp
 
   LINK_COMPONENTS
   Analysis

llvm/lib/Target/RISCV/RISCV.h

 void initializeRISCVExpandAtomicPseudoPass(PassRegistry &);
 
 FunctionPass *createRISCVInsertVSETVLIPass();
 void initializeRISCVInsertVSETVLIPass(PassRegistry &);
 
 FunctionPass *createRISCVRedundantCopyEliminationPass();
 void initializeRISCVRedundantCopyEliminationPass(PassRegistry &);
 
+FunctionPass *createRISCVInitUndefPass();
+void initializeRISCVInitUndefPass(PassRegistry &);
+
 InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &,
                                                     RISCVSubtarget &,
                                                     RISCVRegisterBankInfo &);
 }
 
 #endif

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

public:
   StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
 
 private:
   bool expandMBB(MachineBasicBlock &MBB);
   bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                 MachineBasicBlock::iterator &NextMBBI);
   bool expandCCOp(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                   MachineBasicBlock::iterator &NextMBBI);
+  bool removeTempRVVInitUndef(MachineBasicBlock &MBB,
+                              MachineBasicBlock::iterator MBBI);
   bool expandVSetVL(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
   bool expandVMSET_VMCLR(MachineBasicBlock &MBB,
                          MachineBasicBlock::iterator MBBI, unsigned Opcode);
   bool expandVSPILL(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
   bool expandVRELOAD(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
 };
 
 char RISCVExpandPseudo::ID = 0;
bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
   case RISCV::PseudoVRELOAD3_M2:
   case RISCV::PseudoVRELOAD4_M1:
   case RISCV::PseudoVRELOAD4_M2:
   case RISCV::PseudoVRELOAD5_M1:
   case RISCV::PseudoVRELOAD6_M1:
   case RISCV::PseudoVRELOAD7_M1:
   case RISCV::PseudoVRELOAD8_M1:
     return expandVRELOAD(MBB, MBBI);
+  case RISCV::PseudoRVVInitUndefM1:
+  case RISCV::PseudoRVVInitUndefM2:
+  case RISCV::PseudoRVVInitUndefM4:
+  case RISCV::PseudoRVVInitUndefM8:
+    return removeTempRVVInitUndef(MBB, MBBI);
   }
 
   return false;
 }
 
+bool RISCVExpandPseudo::removeTempRVVInitUndef(
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
+  MachineRegisterInfo *MRI = &(MBB.getParent()->getRegInfo());
+  MachineInstr &MI = *MBBI;
+  Register Reg = MI.getOperand(0).getReg();
+
+  for (MachineOperand &MO : MRI->use_nodbg_operands(Reg))
+    MO.setIsUndef();
+
+  MI.eraseFromParent();
+  return true;
+}
+
 bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MBBI,
                                    MachineBasicBlock::iterator &NextMBBI) {
   assert(MBBI->getOpcode() == RISCV::PseudoCCMOVGPR && "Unexpected opcode");
 
   MachineFunction *MF = MBB.getParent();
   MachineInstr &MI = *MBBI;
   DebugLoc DL = MI.getDebugLoc();

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 
 let Predicates = [IsRV64] in {
 // Select W instructions if only the lower 32-bits of the result are used.
 def : Pat<(binop_allwusers<add> GPR:$rs1, (AddiPair:$rs2)),
           (ADDIW (ADDIW GPR:$rs1, (AddiPairImmLarge AddiPair:$rs2)),
                  (AddiPairImmSmall AddiPair:$rs2))>;
 }
 
+/// Empty pseudo for RISCVInitUndefPass
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 0, isCodeGenOnly = 1 in {
+  def PseudoRVVInitUndefM1     :  Pseudo<(outs VR:$vd), (ins), [], "">;
+  def PseudoRVVInitUndefM2     :  Pseudo<(outs VRM2:$vd), (ins), [], "">;
+  def PseudoRVVInitUndefM4     :  Pseudo<(outs VRM4:$vd), (ins), [], "">;
+  def PseudoRVVInitUndefM8     :  Pseudo<(outs VRM8:$vd), (ins), [], "">;
+}
+
 //===----------------------------------------------------------------------===//
 // Standard extensions
 //===----------------------------------------------------------------------===//
 
 include "RISCVInstrInfoM.td"
 include "RISCVInstrInfoA.td"
 include "RISCVInstrInfoF.td"
 include "RISCVInstrInfoD.td"
 include "RISCVInstrInfoC.td"
 include "RISCVInstrInfoZb.td"
 include "RISCVInstrInfoZk.td"
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZfh.td"
 include "RISCVInstrInfoZicbo.td"

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

+//===- RISCVInitUndef.cpp - Initialize undef vector value to pesudo -------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a function pass that initializes undef vector value to
+// temporary pesudo instruction and remove it in expandpesudo pass to prevent
+// register allocation resulting in a constraint violated result for vector
+// instruction.
+//
+// RISC-V vector instruction has register overlapping constraint for certain
+// instructions, and will cause illegal instruction trap if violated, we use
+// early clobber to model this constraint, but it can't prevent register
+// allocator allocated same or overlapped if the input register is undef value,
+// so convert IMPLICIT_DEF to temporary pesudo instruction and remove it latter
+// could prevent that happen, it's not best way to resolve this, and it might
+// change the order of program or increase the register pressure, so ideally we
+// should model the constraint right, but before we model the constraint right,
+// it's the only way to prevent that happen.
+//
+// When we enable the subregister liveness option, it will also trigger same
+// issue due to the partial of register is undef. If we pesudoinit the whole
+// register, then it will generate redundant COPY instruction. Currently, it
+// will generate INSERT_SUBREG to make sure the whole register is be occupied
+// when program encounter operation that has early-clobber constraint.
+//
+//
+// See also: https://github.com/llvm/llvm-project/issues/50157
+//
+//===----------------------------------------------------------------------===//
+
+#include "RISCV.h"
+#include "RISCVSubtarget.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+using namespace llvm;
+
+#define DEBUG_TYPE "riscv-init-undef"
+#define RISCV_INIT_UNDEF_NAME "RISCV init undef pass"
+
+namespace {
+
+class RISCVInitUndef : public MachineFunctionPass {
+  const TargetInstrInfo *TII;
+  MachineRegisterInfo *MRI;
+  const RISCVSubtarget *ST;
+  const TargetRegisterInfo *TRI;
+  llvm::DenseMap<MachineInstr *, bool> Seen;
+
+public:
+  static char ID;
+
+  RISCVInitUndef() : MachineFunctionPass(ID) {
+    initializeRISCVInitUndefPass(*PassRegistry::getPassRegistry());
+  }
+  bool runOnMachineFunction(MachineFunction &MF) override;
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.setPreservesCFG();
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
+
+  StringRef getPassName() const override { return RISCV_INIT_UNDEF_NAME; }
+
+private:
+  bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
+  bool handleImplicitDef(MachineBasicBlock &MBB,
+                         MachineBasicBlock::iterator &Inst);
+  bool isVectorRegClass(const Register &R);
+  bool handleSubRegister(MachineBasicBlock &MBB,
+                         MachineBasicBlock::iterator &Inst);
+  void findSubRegDefChainNeedToFix(
+      MachineInstr *Curr, std::vector<MachineInstr *> InstrChain,
+      std::vector<std::vector<MachineInstr *>> &Candidates);
+  const TargetRegisterClass *
+  getVRLargestSuperClass(const TargetRegisterClass *RC) const;
+};
+
+} // end anonymous namespace
+
+char RISCVInitUndef::ID = 0;
+
+INITIALIZE_PASS(RISCVInitUndef, DEBUG_TYPE, RISCV_INIT_UNDEF_NAME, false, false)
+
+const TargetRegisterClass *
+RISCVInitUndef::getVRLargestSuperClass(const TargetRegisterClass *RC) const {
+  const TargetRegisterClass *Super = RC;
+  TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
+  do {
+    switch (Super->getID()) {
+    // We only care vector register.
+    case RISCV::VRRegClassID:
+    case RISCV::VRM2RegClassID:
+    case RISCV::VRM4RegClassID:
+    case RISCV::VRM8RegClassID:
+      return Super;
+    }
+    Super = *I++;
+  } while (Super);
+  // If we don't encounter VR then return origin one.
+  return RC;
+}
+
+bool RISCVInitUndef::isVectorRegClass(const Register &R) {
+  unsigned RegClassID = getVRLargestSuperClass(MRI->getRegClass(R))->getID();
+  switch (RegClassID) {
+  case RISCV::VRRegClassID:
+  case RISCV::VRM2RegClassID:
+  case RISCV::VRM4RegClassID:
+  case RISCV::VRM8RegClassID:
+    return true;
+  default:
+    return false;
+  }
+}
+
+static unsigned getUndefInitOpcode(unsigned RegClassID) {
+  unsigned Opcode;
+  switch (RegClassID) {
+  case RISCV::VRRegClassID:
+    Opcode = RISCV::PseudoRVVInitUndefM1;
+    break;
+  case RISCV::VRM2RegClassID:
+    Opcode = RISCV::PseudoRVVInitUndefM2;
+    break;
+  case RISCV::VRM4RegClassID:
+    Opcode = RISCV::PseudoRVVInitUndefM4;
+    break;
+  case RISCV::VRM8RegClassID:
+    Opcode = RISCV::PseudoRVVInitUndefM8;
+    break;
+  default:
+    llvm_unreachable("Unexpected register class.");
+  }
+  return Opcode;
+}
+
+void RISCVInitUndef::findSubRegDefChainNeedToFix(
+    MachineInstr *Curr, std::vector<MachineInstr *> InstrChain,
+    std::vector<std::vector<MachineInstr *>> &Candidates) {
+  unsigned Reg = Curr->getOperand(0).getReg();
+  for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
+    MachineInstr *UserMI = MO.getParent();
+    // Avoid infinite loop
+    if (Seen[UserMI])
+      continue;
+    InstrChain.push_back(UserMI);
+    Seen[UserMI] = true;
+    // If we encounter instruction that using sub-register and
+    // have early-clobber flag, then set it as candidate.
+    for (MachineOperand &UseMO : UserMI->operands()) {
+      if (!UseMO.isReg())
+        continue;
+      if (UseMO.isEarlyClobber()) {
+        Candidates.push_back(InstrChain);
+      }
+    }
+    // If there are other inst define the register, then ignore it due to
+    // register is all defined (for all sub-register).
+    // FIXME: Are there other MachineInstrs could pass the partial defined
+    // register?
+    if (UserMI->getOpcode() == TargetOpcode::INSERT_SUBREG ||
+        UserMI->getOpcode() == TargetOpcode::PHI ||
+        UserMI->getOpcode() == TargetOpcode::COPY)
+      findSubRegDefChainNeedToFix(UserMI, InstrChain, Candidates);
+    InstrChain.pop_back();
+    Seen[UserMI] = false;
+  }
+}
+
+static std::vector<MachineInstr *>
+filterInsertSubRegInst(std::vector<MachineInstr *> Insts) {
+  std::vector<MachineInstr *> rst;
+  for (auto Inst : Insts) {
+    if (Inst->getOpcode() == TargetOpcode::INSERT_SUBREG)
+      rst.push_back(Inst);
+  }
+  return rst;
+}
+
+static MachineOperand *getLastRegUser(std::vector<MachineInstr *> Insts,
+                                      unsigned Reg) {
+  for (size_t i = Insts.size(); i != 0; i--) {
+    for (MachineOperand &UseMO : Insts[i - 1]->operands()) {
+      if (!UseMO.isReg())
+        continue;
+      if (UseMO.getReg() == Reg)
+        return &UseMO;
+    }
+  }
+  LLVM_DEBUG(dbgs() << "Can't find the Inst that using this Register " << Reg
+                    << '\n');
+  return nullptr;
+}
+
+static MachineInstr *
+getLastInsertSubRegInst(std::vector<MachineInstr *> Insts) {
+  MachineInstr *Rst = nullptr;
+  for (auto Inst : Insts) {
+    if (Inst->getOpcode() == TargetOpcode::INSERT_SUBREG)
+      Rst = Inst;
+  }
+  return Rst;
+}
+
+// If Sub-register liveness is enable, then we only need to PesudoInit undef
+// sub-register instead of whole regitser. Otherwise, it will generate redundant
+// COPY. For this purpose, there are some steps to meet this requirement.
+//
+// 1. Find the def-use chain from INSERT_SUBREG.
+//  V0 = Implicit_def
+//  ^ Don't add it to vector due to it will pass from function args
+//  V1 = INSERT_SUBREG V0, SubV0, subreg_index0 V2 = INSERT_SUBREG
+//  V1, SubV1, subreg_index1 V3 = INSERT_SUBREG V2, SubV2, subreg_index2
+//  ...
+//  INSERT_SUBREG || COPY || PHI
+//  ...
+//  VN = INSERT_SUBREG V(N-1), SubV(N-1), subreg_index(N-1)
+//  early-clobber vd = Op VN
+// 2. Compute the which subregister is undef.
+// 3. Insert the more INSERT_SUBREG Node between the
+//    last INSERT_SUBREG and Op with early-clobber constraint.
+//
+// Note: We assume this sub-register def-use will be SSA-form.
+bool RISCVInitUndef::handleSubRegister(MachineBasicBlock &MBB,
+                                       MachineBasicBlock::iterator &Inst) {
+  MachineInstr *CurrInst = &(*Inst);
+
+  Seen.clear();
+  std::vector<std::vector<MachineInstr *>> Candidates;
+  findSubRegDefChainNeedToFix(CurrInst, std::vector<MachineInstr *>(),
+                              Candidates);
+
+  if (Candidates.empty())
+    return false;
+
+  bool Changed = false;
+  unsigned TargetReg = Inst->getOperand(0).getReg();
+  const TargetRegisterClass *TargetRegClass =
+      getVRLargestSuperClass(MRI->getRegClass(TargetReg));
+  for (auto Candidate : Candidates) {
+    LaneBitmask TargetRegLaneMask = TargetRegClass->getLaneMask();
+    LaneBitmask CandidataLaneMask = TargetRegLaneMask;
+
+    // Step 2 Compute the which subregister is undef.
+    for (auto SRDef : filterInsertSubRegInst(Candidate)) {
+      MachineOperand SubRegInd = SRDef->getOperand(3);
+      LaneBitmask SubRegLaneMask =
+          TRI->getSubRegIndexLaneMask(SubRegInd.getImm());
+      CandidataLaneMask = CandidataLaneMask & ~SubRegLaneMask;
+    }
+
+    SmallVector<unsigned> CandidateSubRegIndex;
+    TRI->getCoveringSubRegIndexes(*MRI, TargetRegClass, CandidataLaneMask,
+                                  CandidateSubRegIndex);
+
+    // Step 3 Insert the more INSERT_SUBREG according Step 2 result.
+    MachineInstr *LastInsertSubRegInst = getLastInsertSubRegInst(Candidate);
+    MachineInstr *InsertPoint = LastInsertSubRegInst;
+    unsigned RegOriginUsedbyEC = LastInsertSubRegInst->getOperand(0).getReg();
+    unsigned LastestReg = RegOriginUsedbyEC;
+    // PseudoDef the sub-register until whole target register is fully defined.
+    // It will insert multiple times according to getCoveringSubRegIndexes
+    // result.
+    //
+    // SubV0 = PseudoRVVInitUndef
+    // V1 = INSERT_SUBREG V0, SubV0, subreg_index0
+    //
+    // Then replace the V0 with V1 for early-clobber user.
+    for (auto ind : CandidateSubRegIndex) {
+      Changed = true;
+      const TargetRegisterClass *SubRegClass =
+          getVRLargestSuperClass(TRI->getSubRegisterClass(TargetRegClass, ind));
+      unsigned TmpInitSubReg = MRI->createVirtualRegister(SubRegClass);
+      BuildMI(MBB, Inst, Inst->getDebugLoc(),
+              TII->get(getUndefInitOpcode(SubRegClass->getID())),
+              TmpInitSubReg);
+      unsigned NewReg = MRI->createVirtualRegister(TargetRegClass);
+      MachineInstr *NewInsertSubRegInst =
+          BuildMI(*InsertPoint->getParent(), InsertPoint,
+                  InsertPoint->getDebugLoc(),
+                  TII->get(TargetOpcode::INSERT_SUBREG), NewReg)
+              .addReg(LastestReg)
+              .addReg(TmpInitSubReg)
+              .addImm(ind);
+      // FIXME: Is there better method to insert instruction after another
+      // instruction.
+      InsertPoint->moveBefore(NewInsertSubRegInst);
+      InsertPoint = NewInsertSubRegInst;
+      LastestReg = NewReg;
+    }
+
+    getLastRegUser(Candidate, RegOriginUsedbyEC)->setReg(LastestReg);
+  }
+
+  return Changed;
+}
+
+bool RISCVInitUndef::handleImplicitDef(MachineBasicBlock &MBB,
+                                       MachineBasicBlock::iterator &Inst) {
+  const TargetRegisterInfo &TRI =
+      *MBB.getParent()->getSubtarget().getRegisterInfo();
+
+  assert(Inst->getOpcode() == TargetOpcode::IMPLICIT_DEF);
+
+  unsigned Reg = Inst->getOperand(0).getReg();
+  if (!Register::isVirtualRegister(Reg))
+    return false;
+
+  bool NeedPseudoInit = false;
+  SmallVector<MachineOperand *, 1> UserMOs;
+  for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
+    MachineInstr *UserMI = MO.getParent();
+
+    if (ST->enableSubRegLiveness() &&
+        UserMI->getOpcode() == TargetOpcode::INSERT_SUBREG)
+      return handleSubRegister(MBB, Inst);
+
+    bool HasEarlyClobber = false;
+    bool TiedToDef = false;
+    for (MachineOperand &UseMO : UserMI->operands()) {
+      if (!UseMO.isReg())
+        continue;
+      if (UseMO.isEarlyClobber())
+        HasEarlyClobber = true;
+      if (UseMO.isUse() && UseMO.isTied() &&
+          TRI.regsOverlap(UseMO.getReg(), Reg))
+        TiedToDef = true;
+    }
+    if (HasEarlyClobber && !TiedToDef) {
+      NeedPseudoInit = true;
+      UserMOs.push_back(&MO);
+    }
+  }
+
+  if (!NeedPseudoInit)
+    return false;
+
+  LLVM_DEBUG(
+      dbgs() << "Emitting PseudoRVVInitUndef for implicit vector register "
+             << Reg << '\n');
+
+  unsigned RegClassID = getVRLargestSuperClass(MRI->getRegClass(Reg))->getID();
+  unsigned Opcode = getUndefInitOpcode(RegClassID);
+
+  BuildMI(MBB, Inst, Inst->getDebugLoc(), TII->get(Opcode), Reg);
+
+  Inst = MBB.erase(Inst);
+
+  for (auto MO : UserMOs)
+    MO->setIsUndef(false);
+
+  return true;
+}
+
+bool RISCVInitUndef::processBasicBlock(MachineFunction &MF,
+                                       MachineBasicBlock &MBB) {
+  bool Changed = false;
+  for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
+    MachineInstr &MI = *I;
+    if (MI.isImplicitDef()) {
+      auto DstReg = MI.getOperand(0).getReg();
+      if (isVectorRegClass(DstReg))
+        Changed |= handleImplicitDef(MBB, I);
+    }
+  }
+  return Changed;
+}
+
+bool RISCVInitUndef::runOnMachineFunction(MachineFunction &MF) {
+  ST = &MF.getSubtarget<RISCVSubtarget>();
+  if (!ST->hasVInstructions())
+    return false;
+
+  MRI = &MF.getRegInfo();
+  TII = ST->getInstrInfo();
+  TRI = MRI->getTargetRegisterInfo();
+
+  bool Changed = false;
+  for (MachineBasicBlock &BB : MF)
+    Changed |= processBasicBlock(MF, BB);
+
+  return Changed;
+}
+
+FunctionPass *llvm::createRISCVInitUndefPass() { return new RISCVInitUndef(); }

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
   initializeRISCVMakeCompressibleOptPass(*PR);
   initializeRISCVGatherScatterLoweringPass(*PR);
   initializeRISCVCodeGenPreparePass(*PR);
   initializeRISCVMergeBaseOffsetOptPass(*PR);
   initializeRISCVSExtWRemovalPass(*PR);
   initializeRISCVPreRAExpandPseudoPass(*PR);
   initializeRISCVExpandPseudoPass(*PR);
   initializeRISCVInsertVSETVLIPass(*PR);
+  initializeRISCVInitUndefPass(*PR);
 }
 
 static StringRef computeDataLayout(const Triple &TT) {
   if (TT.isArch64Bit())
     return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
   assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
   return "e-m:e-p:32:32-i64:64-n32-S128";
 }
if (TM->getTargetTriple().getArch() == Triple::riscv64)
     addPass(createRISCVSExtWRemovalPass());
 }
 
 void RISCVPassConfig::addPreRegAlloc() {
   addPass(createRISCVPreRAExpandPseudoPass());
   if (TM->getOptLevel() != CodeGenOpt::None)
     addPass(createRISCVMergeBaseOffsetOptPass());
   addPass(createRISCVInsertVSETVLIPass());
+  if (getOptimizeRegAlloc())
+    addPass(createRISCVInitUndefPass());
 }
 
 void RISCVPassConfig::addPostRegAlloc() {
   if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
     addPass(createRISCVRedundantCopyEliminationPass());
 }
 
 yaml::MachineFunctionInfo *

llvm/test/CodeGen/RISCV/O3-pipeline.ll

 ; CHECK-NEXT:       Remove dead machine instructions
 ; CHECK-NEXT:       Machine Trace Metrics
 ; CHECK-NEXT:       Lazy Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine InstCombiner
 ; RV64-NEXT:        RISCV sext.w Removal
 ; CHECK-NEXT:       RISCV Pre-RA pseudo instruction expansion pass
 ; CHECK-NEXT:       RISCV Merge Base Offset
 ; CHECK-NEXT:       RISCV Insert VSETVLI pass
+; CHECK-NEXT:       RISCV init undef pass
 ; CHECK-NEXT:       Detect Dead Lanes
 ; CHECK-NEXT:       Process Implicit Definitions
 ; CHECK-NEXT:       Remove unreachable machine basic blocks
 ; CHECK-NEXT:       Live Variable Analysis
 ; CHECK-NEXT:       Eliminate PHI nodes for register allocation
 ; CHECK-NEXT:       Two-Address instruction pass
 ; CHECK-NEXT:       MachineDominator Tree Construction
 ; CHECK-NEXT:       Slot index numbering

llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll

 ; CHECK-NEXT:    .cfi_offset ra, -8
 ; CHECK-NEXT:    .cfi_offset s0, -16
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    li a1, 24
 ; CHECK-NEXT:    mul a0, a0, a1
 ; CHECK-NEXT:    sub sp, sp, a0
 ; CHECK-NEXT:    li a0, 55
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT:    vloxseg2ei32.v v8, (a0), v8
+; CHECK-NEXT:    vloxseg2ei32.v v16, (a0), v8
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    slli a0, a0, 3
 ; CHECK-NEXT:    add a0, sp, a0
 ; CHECK-NEXT:    addi a0, a0, 16
 ; CHECK-NEXT:    csrr a1, vlenb
 ; CHECK-NEXT:    slli a1, a1, 2
-; CHECK-NEXT:    vs4r.v v8, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT:    vs4r.v v16, (a0) # Unknown-size Folded Spill
 ; CHECK-NEXT:    add a0, a0, a1
-; CHECK-NEXT:    vs4r.v v12, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT:    vs4r.v v20, (a0) # Unknown-size Folded Spill
 ; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
 ; CHECK-NEXT:    vmclr.m v0
 ; CHECK-NEXT:    li s0, 36
 ; CHECK-NEXT:    vsetvli zero, s0, e16, m4, ta, ma
-; CHECK-NEXT:    vfwadd.vv v8, v8, v8, v0.t
+; CHECK-NEXT:    vfwadd.vv v16, v8, v8, v0.t
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    slli a0, a0, 4
 ; CHECK-NEXT:    add a0, sp, a0
 ; CHECK-NEXT:    addi a0, a0, 16
-; CHECK-NEXT:    vs8r.v v8, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT:    vs8r.v v16, (a0) # Unknown-size Folded Spill
 ; CHECK-NEXT:    call func@plt
 ; CHECK-NEXT:    li a0, 32
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
 ; CHECK-NEXT:    vrgather.vv v4, v8, v8, v0.t
 ; CHECK-NEXT:    vsetvli zero, s0, e16, m4, ta, ma
 ; CHECK-NEXT:    csrr a1, vlenb
 ; CHECK-NEXT:    slli a1, a1, 3
 ; CHECK-NEXT:    add a1, sp, a1

 ; SUBREGLIVENESS-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; SUBREGLIVENESS-NEXT:    .cfi_offset ra, -8
 ; SUBREGLIVENESS-NEXT:    .cfi_offset s0, -16
 ; SUBREGLIVENESS-NEXT:    csrr a0, vlenb
 ; SUBREGLIVENESS-NEXT:    slli a0, a0, 4
 ; SUBREGLIVENESS-NEXT:    sub sp, sp, a0
 ; SUBREGLIVENESS-NEXT:    li a0, 55
 ; SUBREGLIVENESS-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
-; SUBREGLIVENESS-NEXT:    vloxseg2ei32.v v8, (a0), v8
+; SUBREGLIVENESS-NEXT:    vloxseg2ei32.v v16, (a0), v8
 ; SUBREGLIVENESS-NEXT:    csrr a0, vlenb
 ; SUBREGLIVENESS-NEXT:    slli a0, a0, 3
 ; SUBREGLIVENESS-NEXT:    add a0, sp, a0
 ; SUBREGLIVENESS-NEXT:    addi a0, a0, 16
 ; SUBREGLIVENESS-NEXT:    csrr a1, vlenb
 ; SUBREGLIVENESS-NEXT:    slli a1, a1, 2
-; SUBREGLIVENESS-NEXT:    vs4r.v v8, (a0) # Unknown-size Folded Spill
+; SUBREGLIVENESS-NEXT:    vs4r.v v16, (a0) # Unknown-size Folded Spill
 ; SUBREGLIVENESS-NEXT:    add a0, a0, a1
-; SUBREGLIVENESS-NEXT:    vs4r.v v12, (a0) # Unknown-size Folded Spill
+; SUBREGLIVENESS-NEXT:    vs4r.v v20, (a0) # Unknown-size Folded Spill
 ; SUBREGLIVENESS-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
 ; SUBREGLIVENESS-NEXT:    vmclr.m v0
 ; SUBREGLIVENESS-NEXT:    li s0, 36
 ; SUBREGLIVENESS-NEXT:    vsetvli zero, s0, e16, m4, ta, ma
-; SUBREGLIVENESS-NEXT:    vfwadd.vv v8, v8, v8, v0.t
+; SUBREGLIVENESS-NEXT:    vfwadd.vv v16, v8, v8, v0.t
 ; SUBREGLIVENESS-NEXT:    addi a0, sp, 16
-; SUBREGLIVENESS-NEXT:    vs8r.v v8, (a0) # Unknown-size Folded Spill
+; SUBREGLIVENESS-NEXT:    vs8r.v v16, (a0) # Unknown-size Folded Spill
 ; SUBREGLIVENESS-NEXT:    call func@plt
 ; SUBREGLIVENESS-NEXT:    li a0, 32
 ; SUBREGLIVENESS-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
 ; SUBREGLIVENESS-NEXT:    vrgather.vv v16, v8, v8, v0.t
 ; SUBREGLIVENESS-NEXT:    vsetvli zero, s0, e16, m4, ta, ma
 ; SUBREGLIVENESS-NEXT:    csrr a1, vlenb
 ; SUBREGLIVENESS-NEXT:    slli a1, a1, 3
 ; SUBREGLIVENESS-NEXT:    add a1, sp, a1

llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple riscv64 -mattr=+v -riscv-enable-subreg-liveness < %s  | FileCheck %s
+
+define dso_local signext i32 @undef_early_clobber_chain() {
+; CHECK-LABEL: undef_early_clobber_chain:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addi sp, sp, -400
+; CHECK-NEXT:    .cfi_def_cfa_offset 400
+; CHECK-NEXT:    vsetivli zero, 0, e32, m1, ta, ma
+; CHECK-NEXT:    vrgather.vi v9, v8, 0
+; CHECK-NEXT:    mv a0, sp
+; CHECK-NEXT:    vse32.v v9, (a0)
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    addi sp, sp, 400
+; CHECK-NEXT:    ret
+entry:
+  %dst = alloca [100 x float], align 8
+  call void @llvm.lifetime.start.p0(i64 400, ptr nonnull %dst) #4
+  %0 = tail call <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.i64(<vscale x 2 x float> undef, <vscale x 2 x float> undef, i64 0, i64 0)
+  call void @llvm.riscv.vse.nxv2f32.i64(<vscale x 2 x float> %0, ptr nonnull %dst, i64 0)
+  call void @llvm.lifetime.end.p0(i64 400, ptr nonnull %dst) #4
+  ret i32 0
+}
+
+define internal void @SubRegLivenessUndefInPhi(i64 %cond) {
+; CHECK-LABEL: SubRegLivenessUndefInPhi:
+; CHECK:       # %bb.0: # %start
+; CHECK-NEXT:    blez a0, .LBB1_2
+; CHECK-NEXT:  # %bb.1: # %Cond1
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT:    vid.v v8
+; CHECK-NEXT:    vadd.vi v10, v8, 1
+; CHECK-NEXT:    vadd.vi v12, v8, 3
+; CHECK-NEXT:    j .LBB1_3
+; CHECK-NEXT:  .LBB1_2: # %Cond2
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT:    vid.v v12
+; CHECK-NEXT:    csrr a0, vlenb
+; CHECK-NEXT:    srli a0, a0, 3
+; CHECK-NEXT:    add a1, a0, a0
+; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
+; CHECK-NEXT:    vslideup.vx v8, v12, a0
+; CHECK-NEXT:    vsetvli a2, zero, e16, mf4, ta, ma
+; CHECK-NEXT:    vadd.vi v11, v12, 1
+; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
+; CHECK-NEXT:    vslideup.vx v10, v11, a0
+; CHECK-NEXT:    vsetvli a2, zero, e16, mf4, ta, ma
+; CHECK-NEXT:    vadd.vi v13, v12, 3
+; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
+; CHECK-NEXT:    vslideup.vx v12, v13, a0
+; CHECK-NEXT:  .LBB1_3: # %UseSR
+; CHECK-NEXT:    vl1r.v v14, (zero)
+; CHECK-NEXT:    vsetivli zero, 4, e8, m1, ta, ma
+; CHECK-NEXT:    vrgatherei16.vv v15, v14, v8
+; CHECK-NEXT:    vrgatherei16.vv v8, v14, v10
+; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT:    vand.vv v8, v15, v8
+; CHECK-NEXT:    vsetivli zero, 4, e8, m1, ta, ma
+; CHECK-NEXT:    vrgatherei16.vv v9, v14, v12
+; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT:    vand.vv v8, v8, v9
+; CHECK-NEXT:    vs1r.v v8, (zero)
+; CHECK-NEXT:    ret
+start:
+    %0 = icmp sgt i64 %cond, 0
+    br i1 %0, label %Cond1, label %Cond2
+
+Cond1:                             ; preds = %start
+    %v15 = tail call <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
+    %v17 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %v15, i64 0)
+    %vs12.i.i.i = add <vscale x 1 x i16> %v15, shufflevector (<vscale x 1 x i16> insertelement (<vscale x 1 x i16> poison, i16 1, i32 0), <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer)
+    %v18 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i, i64 0)
+    %vs16.i.i.i = add <vscale x 1 x i16> %v15, shufflevector (<vscale x 1 x i16> insertelement (<vscale x 1 x i16> poison, i16 3, i32 0), <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer)
+    %v20 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs16.i.i.i, i64 0)
+    br label %UseSR
+
+Cond2:                           ; preds = %start
+    %v15.2 = tail call <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
+    %v17.2 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %v15.2, i64 1)
+    %vs12.i.i.i.2 = add <vscale x 1 x i16> %v15.2, shufflevector (<vscale x 1 x i16> insertelement (<vscale x 1 x i16> poison, i16 1, i32 0), <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer)
+    %v18.2 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i.2, i64 1)
+    %vs16.i.i.i.2 = add <vscale x 1 x i16> %v15.2, shufflevector (<vscale x 1 x i16> insertelement (<vscale x 1 x i16> poison, i16 3, i32 0), <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer)
+    %v20.2 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs16.i.i.i.2, i64 1)
+    br label %UseSR
+
+UseSR:                                      ; preds = %Cond1, Cond2
+    %v17.3 = phi <vscale x 8 x i16> [ %v17, %Cond1 ], [ %v17.2, %Cond2 ]
+    %v18.3 = phi <vscale x 8 x i16> [ %v18, %Cond1 ], [ %v18.2, %Cond2 ]
+    %v20.3 = phi <vscale x 8 x i16> [ %v20, %Cond1 ], [ %v20.2, %Cond2 ]
+    %v37 = load <vscale x 8 x i8>, ptr addrspace(1) null, align 8
+    %v38 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v17.3, i64 4)
+    %v40 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v18.3, i64 4)
+    %v42 = and <vscale x 8 x i8> %v38, %v40
+    %v46 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v20.3, i64 4)
+    %v60 = and <vscale x 8 x i8> %v42, %v46
+    store <vscale x 8 x i8> %v60, ptr addrspace(1) null, align 4
+    ret void
+}
+
+define internal void @SubRegLivenessUndef() {
+; CHECK-LABEL: SubRegLivenessUndef:
+; CHECK:       # %bb.0: # %loopIR.preheader.i.i
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT:    vid.v v8
+; CHECK-NEXT:    vadd.vi v10, v8, 1
+; CHECK-NEXT:    vadd.vi v12, v8, 3
+; CHECK-NEXT:  .LBB2_1: # %loopIR3.i.i
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    vl1r.v v14, (zero)
+; CHECK-NEXT:    vsetivli zero, 4, e8, m1, ta, ma
+; CHECK-NEXT:    vrgatherei16.vv v15, v14, v8
+; CHECK-NEXT:    vrgatherei16.vv v16, v14, v10
+; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT:    vand.vv v15, v15, v16
+; CHECK-NEXT:    vsetivli zero, 4, e8, m1, ta, ma
+; CHECK-NEXT:    vrgatherei16.vv v16, v14, v12
+; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT:    vand.vv v14, v15, v16
+; CHECK-NEXT:    vs1r.v v14, (zero)
+; CHECK-NEXT:    j .LBB2_1
+loopIR.preheader.i.i:
+  %v15 = tail call <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
+  %v17 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %v15, i64 0)
+  %vs12.i.i.i = add <vscale x 1 x i16> %v15, shufflevector (<vscale x 1 x i16> insertelement (<vscale x 1 x i16> poison, i16 1, i32 0), <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer)
+  %v18 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i, i64 0)
+  %vs16.i.i.i = add <vscale x 1 x i16> %v15, shufflevector (<vscale x 1 x i16> insertelement (<vscale x 1 x i16> poison, i16 3, i32 0), <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer)
+  %v20 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs16.i.i.i, i64 0)
+  br label %loopIR3.i.i
+
+loopIR3.i.i:                                      ; preds = %loopIR3.i.i, %loopIR.preheader.i.i
+  %v37 = load <vscale x 8 x i8>, ptr addrspace(1) null, align 8
+  %v38 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v17, i64 4)
+  %v40 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v18, i64 4)
+  %v42 = and <vscale x 8 x i8> %v38, %v40
+  %v46 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v20, i64 4)
+  %v60 = and <vscale x 8 x i8> %v42, %v46
+  store <vscale x 8 x i8> %v60, ptr addrspace(1) null, align 4
+  br label %loopIR3.i.i
+}
+
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)
+declare <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64) #2
+declare void @llvm.riscv.vse.nxv2f32.i64(<vscale x 2 x float>, ptr nocapture, i64)
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)
+declare <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
+declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16>, <vscale x 1 x i16>, i64 immarg)
+declare <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i16>, i64)

llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll

 ; SUBREG-NEXT:    vmv.v.i v9, 0
 ; SUBREG-NEXT:    vsetivli zero, 4, e8, m1, tu, ma
 ; SUBREG-NEXT:    vmv1r.v v8, v9
 ; SUBREG-NEXT:    vrgatherei16.vv v8, v9, v14
 ; SUBREG-NEXT:  .LBB0_1: # %loopIR3.i.i
 ; SUBREG-NEXT:    # =>This Inner Loop Header: Depth=1
 ; SUBREG-NEXT:    vl1r.v v9, (zero)
 ; SUBREG-NEXT:    vsetivli zero, 4, e8, m1, tu, ma
-; SUBREG-NEXT:    vmv1r.v v11, v12
-; SUBREG-NEXT:    vrgatherei16.vv v11, v9, v10
+; SUBREG-NEXT:    vmv1r.v v13, v12
+; SUBREG-NEXT:    vrgatherei16.vv v13, v9, v10
 ; SUBREG-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
-; SUBREG-NEXT:    vand.vv v9, v8, v11
+; SUBREG-NEXT:    vand.vv v9, v8, v13
 ; SUBREG-NEXT:    vs1r.v v9, (zero)
 ; SUBREG-NEXT:    j .LBB0_1
 loopIR.preheader.i.i:
   %v18 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i, i64 0)
   br label %loopIR3.i.i
 
 loopIR3.i.i:                                      ; preds = %loopIR3.i.i, %loopIR.preheader.i.i
   %v376 = load <vscale x 8 x i8>, ptr addrspace(1) null, align 8