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[RISCV] Disable subregister liveness by default
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Authored by frasercrmck on Jul 13 2022, 8:02 AM.

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craig.topper
reames
rogfer01
kito-cheng

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rGd1a5669f5e44: [RISCV] Disable subregister liveness by default

Summary

We previously enabled subregister liveness by default when compiling
with RVV. This has been shown to cause miscompilations where RVV
register operand constraints are not met. A test was added for this in
D129639 which explains the issue in more detail.

Until this issue is fixed in some way, we should not be enabling
subregister liveness unless the user asks for it.

Diff Detail

Repository: rG LLVM Github Monorepo

Event Timeline

frasercrmck created this revision.Jul 13 2022, 8:02 AM

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frasercrmck requested review of this revision.Jul 13 2022, 8:02 AM

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frasercrmck added a parent revision: D129639: [RISCV] Add a test showing a miscompilation with subreg liveness.Jul 13 2022, 8:03 AM

Harbormaster completed remote builds in B175117: Diff 444262.Jul 13 2022, 8:03 AM

I'm too in favour of disabling subregister liveness until we can model the problematic instructions constraints in a more robust way.

This revision is now accepted and ready to land.Jul 13 2022, 12:50 PM

I agree we should disable this.

Another approach to fix/work-around for this issue: https://reviews.llvm.org/D129735

Personally I would prefer keep sub register liveness enabled by default, that indeed improved code gen quality especially when program contain segment load/store.

As I can see the most root cause is the undef and poison value in the program, ideally that should not appeared in program IMO, so I would prefer to trade some code gen quality about undef/poison value to make sub register liveness still enabled, and buy more time to model the constraint issue right.

I guess I should express that explicitly: I am not intend to block this patch and OK to disable by default unless we have another better way, since apparently the alternative solution https://reviews.llvm.org/D129735 isn't ready.

This revision was landed with ongoing or failed builds.Jul 14 2022, 9:15 AM

Closed by commit rGd1a5669f5e44: [RISCV] Disable subregister liveness by default (authored by frasercrmck). · Explain Why

This revision was automatically updated to reflect the committed changes.

frasercrmck added a commit: rGd1a5669f5e44: [RISCV] Disable subregister liveness by default.

craig.topper mentioned this in D145546: [RISCV] Enable subregister liveness by default.Mar 7 2023, 10:51 PM

BeMg mentioned this in rG365f84039878: [RISCV] Enable subregister liveness by default.Mar 8 2023, 11:15 PM

Revision Contents

Path

Size

llvm/

lib/

Target/

RISCV/

RISCVSubtarget.cpp

8 lines

test/

CodeGen/

RISCV/

rvv/

extract-subvector.ll

18 lines

fixed-vector-segN-load.ll

7 lines

fixed-vector-trunc-vp.ll

12 lines

fixed-vectors-fp-interleave.ll

18 lines

fixed-vectors-int-exttrunc.ll

10 lines

fixed-vectors-int-interleave.ll

18 lines

fixed-vectors-masked-gather.ll

50 lines

fixed-vectors-masked-scatter.ll

50 lines

fixed-vectors-reduction-fp.ll

20 lines

fixed-vectors-reduction-int.ll

16 lines

insert-subvector.ll

4 lines

rv32-spill-zvlsseg.ll

5 lines

rv64-spill-zvlsseg.ll

5 lines

18 lines

2992 lines

4238 lines

258 lines

280 lines

4 lines

924 lines

4 lines

994 lines

258 lines

280 lines

2992 lines

4238 lines

26 lines

vrgatherei16-subreg-liveness.ll

44 lines

vsetvli-insert-crossbb.ll

2 lines

5412 lines

7622 lines

258 lines

280 lines

258 lines

280 lines

5412 lines

7622 lines

12 lines

Diff 444691

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

Show First 20 Lines • Show All 196 Lines • ▼ Show 20 Lines	return PowerOf2Floor(
std::max<unsigned>(std::min<unsigned>(RVVVectorLMULMax, 8), 1));		std::max<unsigned>(std::min<unsigned>(RVVVectorLMULMax, 8), 1));
}		}

bool RISCVSubtarget::useRVVForFixedLengthVectors() const {		bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
return hasVInstructions() && getMinRVVVectorSizeInBits() != 0;		return hasVInstructions() && getMinRVVVectorSizeInBits() != 0;
}		}

bool RISCVSubtarget::enableSubRegLiveness() const {		bool RISCVSubtarget::enableSubRegLiveness() const {
if (EnableSubRegLiveness.getNumOccurrences())		// FIXME: Enable subregister liveness by default for RVV to better handle
		// LMUL>1 and segment load/store.
return EnableSubRegLiveness;		return EnableSubRegLiveness;
// Enable subregister liveness for RVV to better handle LMUL>1 and segment
// load/store.
return hasVInstructions();
}		}

void RISCVSubtarget::getPostRAMutations(		void RISCVSubtarget::getPostRAMutations(
std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {		std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
Mutations.push_back(createRISCVMacroFusionDAGMutation());		Mutations.push_back(createRISCVMacroFusionDAGMutation());
}		}

llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple riscv32 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s \| FileCheck %s			; RUN: llc -mtriple riscv32 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s \| FileCheck %s
	; RUN: llc -mtriple riscv64 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s \| FileCheck %s			; RUN: llc -mtriple riscv64 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s \| FileCheck %s

	define <vscale x 4 x i32> @extract_nxv8i32_nxv4i32_0(<vscale x 8 x i32> %vec) {			define <vscale x 4 x i32> @extract_nxv8i32_nxv4i32_0(<vscale x 8 x i32> %vec) {
	; CHECK-LABEL: extract_nxv8i32_nxv4i32_0:			; CHECK-LABEL: extract_nxv8i32_nxv4i32_0:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 0)			%c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 0)
	ret <vscale x 4 x i32> %c			ret <vscale x 4 x i32> %c
	}			}

	define <vscale x 4 x i32> @extract_nxv8i32_nxv4i32_4(<vscale x 8 x i32> %vec) {			define <vscale x 4 x i32> @extract_nxv8i32_nxv4i32_4(<vscale x 8 x i32> %vec) {
	; CHECK-LABEL: extract_nxv8i32_nxv4i32_4:			; CHECK-LABEL: extract_nxv8i32_nxv4i32_4:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	; CHECK-NEXT: vmv2r.v v8, v10			; CHECK-NEXT: vmv2r.v v8, v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 4)			%c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 4)
	ret <vscale x 4 x i32> %c			ret <vscale x 4 x i32> %c
	}			}

	define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_0(<vscale x 8 x i32> %vec) {			define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_0(<vscale x 8 x i32> %vec) {
	; CHECK-LABEL: extract_nxv8i32_nxv2i32_0:			; CHECK-LABEL: extract_nxv8i32_nxv2i32_0:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 0)			%c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 0)
	ret <vscale x 2 x i32> %c			ret <vscale x 2 x i32> %c
	}			}

	define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_2(<vscale x 8 x i32> %vec) {			define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_2(<vscale x 8 x i32> %vec) {
	; CHECK-LABEL: extract_nxv8i32_nxv2i32_2:			; CHECK-LABEL: extract_nxv8i32_nxv2i32_2:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	Show All 19 Lines
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 6)			%c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 6)
	ret <vscale x 2 x i32> %c			ret <vscale x 2 x i32> %c
	}			}

	define <vscale x 8 x i32> @extract_nxv16i32_nxv8i32_0(<vscale x 16 x i32> %vec) {			define <vscale x 8 x i32> @extract_nxv16i32_nxv8i32_0(<vscale x 16 x i32> %vec) {
	; CHECK-LABEL: extract_nxv16i32_nxv8i32_0:			; CHECK-LABEL: extract_nxv16i32_nxv8i32_0:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%c = call <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)			%c = call <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)
	ret <vscale x 8 x i32> %c			ret <vscale x 8 x i32> %c
	}			}

	define <vscale x 8 x i32> @extract_nxv16i32_nxv8i32_8(<vscale x 16 x i32> %vec) {			define <vscale x 8 x i32> @extract_nxv16i32_nxv8i32_8(<vscale x 16 x i32> %vec) {
	; CHECK-LABEL: extract_nxv16i32_nxv8i32_8:			; CHECK-LABEL: extract_nxv16i32_nxv8i32_8:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	; CHECK-NEXT: vmv4r.v v8, v12			; CHECK-NEXT: vmv4r.v v8, v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%c = call <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8)			%c = call <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8)
	ret <vscale x 8 x i32> %c			ret <vscale x 8 x i32> %c
	}			}

	define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_0(<vscale x 16 x i32> %vec) {			define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_0(<vscale x 16 x i32> %vec) {
	; CHECK-LABEL: extract_nxv16i32_nxv4i32_0:			; CHECK-LABEL: extract_nxv16i32_nxv4i32_0:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)			%c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)
	ret <vscale x 4 x i32> %c			ret <vscale x 4 x i32> %c
	}			}

	define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_4(<vscale x 16 x i32> %vec) {			define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_4(<vscale x 16 x i32> %vec) {
	; CHECK-LABEL: extract_nxv16i32_nxv4i32_4:			; CHECK-LABEL: extract_nxv16i32_nxv4i32_4:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	Show All 19 Lines
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 12)			%c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 12)
	ret <vscale x 4 x i32> %c			ret <vscale x 4 x i32> %c
	}			}

	define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_0(<vscale x 16 x i32> %vec) {			define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_0(<vscale x 16 x i32> %vec) {
	; CHECK-LABEL: extract_nxv16i32_nxv2i32_0:			; CHECK-LABEL: extract_nxv16i32_nxv2i32_0:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8m8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)			%c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)
	ret <vscale x 2 x i32> %c			ret <vscale x 2 x i32> %c
	}			}

	define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_2(<vscale x 16 x i32> %vec) {			define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_2(<vscale x 16 x i32> %vec) {
	; CHECK-LABEL: extract_nxv16i32_nxv2i32_2:			; CHECK-LABEL: extract_nxv16i32_nxv2i32_2:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 14)			%c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 14)
	ret <vscale x 2 x i32> %c			ret <vscale x 2 x i32> %c
	}			}

	define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_0(<vscale x 16 x i32> %vec) {			define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_0(<vscale x 16 x i32> %vec) {
	; CHECK-LABEL: extract_nxv16i32_nxv1i32_0:			; CHECK-LABEL: extract_nxv16i32_nxv1i32_0:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8m8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)			%c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)
	ret <vscale x 1 x i32> %c			ret <vscale x 1 x i32> %c
	}			}

	define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_1(<vscale x 16 x i32> %vec) {			define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_1(<vscale x 16 x i32> %vec) {
	; CHECK-LABEL: extract_nxv16i32_nxv1i32_1:			; CHECK-LABEL: extract_nxv16i32_nxv1i32_1:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> %vec, i64 0)			%c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> %vec, i64 0)
	ret <vscale x 1 x i32> %c			ret <vscale x 1 x i32> %c
	}			}

	define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_0(<vscale x 32 x i8> %vec) {			define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_0(<vscale x 32 x i8> %vec) {
	; CHECK-LABEL: extract_nxv32i8_nxv2i8_0:			; CHECK-LABEL: extract_nxv32i8_nxv2i8_0:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%c = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 0)			%c = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 0)
	ret <vscale x 2 x i8> %c			ret <vscale x 2 x i8> %c
	}			}

	define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_2(<vscale x 32 x i8> %vec) {			define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_2(<vscale x 32 x i8> %vec) {
	; CHECK-LABEL: extract_nxv32i8_nxv2i8_2:			; CHECK-LABEL: extract_nxv32i8_nxv2i8_2:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%c = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, i64 3)			%c = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, i64 3)
	ret <vscale x 1 x i8> %c			ret <vscale x 1 x i8> %c
	}			}

	define <vscale x 2 x half> @extract_nxv2f16_nxv16f16_0(<vscale x 16 x half> %vec) {			define <vscale x 2 x half> @extract_nxv2f16_nxv16f16_0(<vscale x 16 x half> %vec) {
	; CHECK-LABEL: extract_nxv2f16_nxv16f16_0:			; CHECK-LABEL: extract_nxv2f16_nxv16f16_0:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%c = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %vec, i64 0)			%c = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %vec, i64 0)
	ret <vscale x 2 x half> %c			ret <vscale x 2 x half> %c
	}			}

	define <vscale x 2 x half> @extract_nxv2f16_nxv16f16_2(<vscale x 16 x half> %vec) {			define <vscale x 2 x half> @extract_nxv2f16_nxv16f16_2(<vscale x 16 x half> %vec) {
	; CHECK-LABEL: extract_nxv2f16_nxv16f16_2:			; CHECK-LABEL: extract_nxv2f16_nxv16f16_2:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	▲ Show 20 Lines • Show All 106 Lines • ▼ Show 20 Lines
	}			}

	;			;
	; Extract f16 vector that needs widening from one that needs widening.			; Extract f16 vector that needs widening from one that needs widening.
	;			;
	define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_0(<vscale x 12 x half> %in) {			define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_0(<vscale x 12 x half> %in) {
	; CHECK-LABEL: extract_nxv6f16_nxv12f16_0:			; CHECK-LABEL: extract_nxv6f16_nxv12f16_0:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%res = call <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 0)			%res = call <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 0)
	ret <vscale x 6 x half> %res			ret <vscale x 6 x half> %res
	}			}

	define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_6(<vscale x 12 x half> %in) {			define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_6(<vscale x 12 x half> %in) {
	; CHECK-LABEL: extract_nxv6f16_nxv12f16_6:			; CHECK-LABEL: extract_nxv6f16_nxv12f16_6:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	; CHECK-NEXT: csrr a0, vlenb			; CHECK-NEXT: csrr a0, vlenb
	; CHECK-NEXT: srli a0, a0, 2			; CHECK-NEXT: srli a0, a0, 2
	; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu			; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
	; CHECK-NEXT: vslidedown.vx v11, v10, a0			; CHECK-NEXT: vslidedown.vx v14, v10, a0
	; CHECK-NEXT: vslidedown.vx v8, v9, a0			; CHECK-NEXT: vslidedown.vx v12, v9, a0
	; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu			; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
	; CHECK-NEXT: vslideup.vi v9, v11, 0			; CHECK-NEXT: vslideup.vi v13, v14, 0
	; CHECK-NEXT: add a1, a0, a0			; CHECK-NEXT: add a1, a0, a0
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
	; CHECK-NEXT: vslideup.vx v8, v10, a0			; CHECK-NEXT: vslideup.vx v12, v10, a0
				; CHECK-NEXT: vmv2r.v v8, v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%res = call <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 6)			%res = call <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 6)
	ret <vscale x 6 x half> %res			ret <vscale x 6 x half> %res
	}			}

	declare <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half>, i64)			declare <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half>, i64)

	declare <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, i64 %idx)			declare <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, i64 %idx)
	Show All 21 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vector-segN-load.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple riscv64 -mattr=+zve64x -riscv-v-vector-bits-min=128 < %s \			; RUN: llc -mtriple riscv64 -mattr=+zve64x -riscv-v-vector-bits-min=128 < %s \
	; RUN: \| FileCheck %s			; RUN: \| FileCheck %s

	define <8 x i8> @load_factor2(<16 x i8>* %ptr) {			define <8 x i8> @load_factor2(<16 x i8>* %ptr) {
	; CHECK-LABEL: load_factor2:			; CHECK-LABEL: load_factor2:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu			; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg2e8.v v7, (a0)			; CHECK-NEXT: vlseg2e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%1 = bitcast <16 x i8>* %ptr to i8*			%1 = bitcast <16 x i8>* %ptr to i8*
	%2 = call { <8 x i8>, <8 x i8> } @llvm.riscv.seg2.load.v8i8.p0i8.i64(i8* %1, i64 8)			%2 = call { <8 x i8>, <8 x i8> } @llvm.riscv.seg2.load.v8i8.p0i8.i64(i8* %1, i64 8)
	%3 = extractvalue { <8 x i8>, <8 x i8> } %2, 0			%3 = extractvalue { <8 x i8>, <8 x i8> } %2, 0
	%4 = extractvalue { <8 x i8>, <8 x i8> } %2, 1			%4 = extractvalue { <8 x i8>, <8 x i8> } %2, 1
	ret <8 x i8> %4			ret <8 x i8> %4
	}			}

	define <8 x i8> @load_factor3(<24 x i8>* %ptr) {			define <8 x i8> @load_factor3(<24 x i8>* %ptr) {
	; CHECK-LABEL: load_factor3:			; CHECK-LABEL: load_factor3:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu			; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg3e8.v v6, (a0)			; CHECK-NEXT: vlseg3e8.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v6_v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%1 = bitcast <24 x i8>* %ptr to i8*			%1 = bitcast <24 x i8>* %ptr to i8*
	%2 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg3.load.v8i8.p0i8.i64(i8* %1, i64 8)			%2 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg3.load.v8i8.p0i8.i64(i8* %1, i64 8)
	%3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %2, 0			%3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %2, 0
	%4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %2, 1			%4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %2, 1
	%5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %2, 2			%5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %2, 2
	ret <8 x i8> %5			ret <8 x i8> %5
	}			}

	define <8 x i8> @load_factor4(<32 x i8>* %ptr) {			define <8 x i8> @load_factor4(<32 x i8>* %ptr) {
	; CHECK-LABEL: load_factor4:			; CHECK-LABEL: load_factor4:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu			; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg4e8.v v5, (a0)			; CHECK-NEXT: vlseg4e8.v v5, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v5_v6_v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%1 = bitcast <32 x i8>* %ptr to i8*			%1 = bitcast <32 x i8>* %ptr to i8*
	%2 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg4.load.v8i8.p0i8.i64(i8* %1, i64 8)			%2 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg4.load.v8i8.p0i8.i64(i8* %1, i64 8)
	%3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 0			%3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 0
	%4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 1			%4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 1
	%5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 2			%5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 2
	%6 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 3			%6 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 3
	ret <8 x i8> %6			ret <8 x i8> %6
	}			}

	define <8 x i8> @load_factor5(<40 x i8>* %ptr) {			define <8 x i8> @load_factor5(<40 x i8>* %ptr) {
	; CHECK-LABEL: load_factor5:			; CHECK-LABEL: load_factor5:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu			; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg5e8.v v4, (a0)			; CHECK-NEXT: vlseg5e8.v v4, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v4_v5_v6_v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%1 = bitcast <40 x i8>* %ptr to i8*			%1 = bitcast <40 x i8>* %ptr to i8*
	%2 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg5.load.v8i8.p0i8.i64(i8* %1, i64 8)			%2 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg5.load.v8i8.p0i8.i64(i8* %1, i64 8)
	%3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 0			%3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 0
	%4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 1			%4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 1
	%5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 2			%5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 2
	%6 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 3			%6 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 3
	%7 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 4			%7 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 4
	ret <8 x i8> %7			ret <8 x i8> %7
	}			}

	define <8 x i8> @load_factor6(<48 x i8>* %ptr) {			define <8 x i8> @load_factor6(<48 x i8>* %ptr) {
	; CHECK-LABEL: load_factor6:			; CHECK-LABEL: load_factor6:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu			; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg6e8.v v3, (a0)			; CHECK-NEXT: vlseg6e8.v v3, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v3_v4_v5_v6_v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%1 = bitcast <48 x i8>* %ptr to i8*			%1 = bitcast <48 x i8>* %ptr to i8*
	%2 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg6.load.v8i8.p0i8.i64(i8* %1, i64 8)			%2 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg6.load.v8i8.p0i8.i64(i8* %1, i64 8)
	%3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 0			%3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 0
	%4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 1			%4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 1
	%5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 2			%5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 2
	%6 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 3			%6 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 3
	%7 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 4			%7 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 4
	%8 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 5			%8 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 5
	ret <8 x i8> %8			ret <8 x i8> %8
	}			}

	define <8 x i8> @load_factor7(<56 x i8>* %ptr) {			define <8 x i8> @load_factor7(<56 x i8>* %ptr) {
	; CHECK-LABEL: load_factor7:			; CHECK-LABEL: load_factor7:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu			; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg7e8.v v2, (a0)			; CHECK-NEXT: vlseg7e8.v v2, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v2_v3_v4_v5_v6_v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%1 = bitcast <56 x i8>* %ptr to i8*			%1 = bitcast <56 x i8>* %ptr to i8*
	%2 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg7.load.v8i8.p0i8.i64(i8* %1, i64 8)			%2 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg7.load.v8i8.p0i8.i64(i8* %1, i64 8)
	%3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 0			%3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 0
	%4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 1			%4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 1
	%5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 2			%5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 2
	%6 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 3			%6 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 3
	%7 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 4			%7 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 4
	%8 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 5			%8 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 5
	%9 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 6			%9 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 6
	ret <8 x i8> %9			ret <8 x i8> %9
	}			}

	define <8 x i8> @load_factor8(<64 x i8>* %ptr) {			define <8 x i8> @load_factor8(<64 x i8>* %ptr) {
	; CHECK-LABEL: load_factor8:			; CHECK-LABEL: load_factor8:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu			; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg8e8.v v1, (a0)			; CHECK-NEXT: vlseg8e8.v v1, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v1_v2_v3_v4_v5_v6_v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%1 = bitcast <64 x i8>* %ptr to i8*			%1 = bitcast <64 x i8>* %ptr to i8*
	%2 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg8.load.v8i8.p0i8.i64(i8* %1, i64 8)			%2 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg8.load.v8i8.p0i8.i64(i8* %1, i64 8)
	%3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 0			%3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 0
	%4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 1			%4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 1
	%5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 2			%5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 2
	%6 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 3			%6 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 3
	%7 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 4			%7 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 4
	Show All 12 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll

	Show First 20 Lines • Show All 261 Lines • ▼ Show 20 Lines
	; CHECK-NEXT: addi a3, a7, -64			; CHECK-NEXT: addi a3, a7, -64
	; CHECK-NEXT: vslidedown.vi v2, v0, 8			; CHECK-NEXT: vslidedown.vi v2, v0, 8
	; CHECK-NEXT: mv a4, a2			; CHECK-NEXT: mv a4, a2
	; CHECK-NEXT: bltu a7, a3, .LBB16_2			; CHECK-NEXT: bltu a7, a3, .LBB16_2
	; CHECK-NEXT: # %bb.1:			; CHECK-NEXT: # %bb.1:
	; CHECK-NEXT: mv a4, a3			; CHECK-NEXT: mv a4, a3
	; CHECK-NEXT: .LBB16_2:			; CHECK-NEXT: .LBB16_2:
	; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu			; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
	; CHECK-NEXT: vslidedown.vi v28, v2, 4			; CHECK-NEXT: vslidedown.vi v3, v2, 4
	; CHECK-NEXT: addi a6, a4, -32			; CHECK-NEXT: addi a6, a4, -32
	; CHECK-NEXT: addi a3, a1, 640			; CHECK-NEXT: addi a3, a1, 640
	; CHECK-NEXT: mv a5, a2			; CHECK-NEXT: mv a5, a2
	; CHECK-NEXT: bltu a4, a6, .LBB16_4			; CHECK-NEXT: bltu a4, a6, .LBB16_4
	; CHECK-NEXT: # %bb.3:			; CHECK-NEXT: # %bb.3:
	; CHECK-NEXT: mv a5, a6			; CHECK-NEXT: mv a5, a6
	; CHECK-NEXT: .LBB16_4:			; CHECK-NEXT: .LBB16_4:
	; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu			; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
	; CHECK-NEXT: vslidedown.vi v0, v28, 2			; CHECK-NEXT: vslidedown.vi v0, v3, 2
	; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu			; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
	; CHECK-NEXT: vle64.v v16, (a3)			; CHECK-NEXT: vle64.v v16, (a3)
	; CHECK-NEXT: addi t0, a5, -16			; CHECK-NEXT: addi t0, a5, -16
	; CHECK-NEXT: addi a6, a1, 512			; CHECK-NEXT: addi a6, a1, 512
	; CHECK-NEXT: mv a3, a2			; CHECK-NEXT: mv a3, a2
	; CHECK-NEXT: bltu a5, t0, .LBB16_6			; CHECK-NEXT: bltu a5, t0, .LBB16_6
	; CHECK-NEXT: # %bb.5:			; CHECK-NEXT: # %bb.5:
	; CHECK-NEXT: mv a3, t0			; CHECK-NEXT: mv a3, t0
	; CHECK-NEXT: .LBB16_6:			; CHECK-NEXT: .LBB16_6:
	; CHECK-NEXT: vle64.v v8, (a6)			; CHECK-NEXT: vle64.v v8, (a6)
	; CHECK-NEXT: vsetvli zero, a3, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a3, e32, m4, ta, mu
	; CHECK-NEXT: li a3, 16			; CHECK-NEXT: li a3, 16
	; CHECK-NEXT: vncvt.x.x.w v24, v16, v0.t			; CHECK-NEXT: vncvt.x.x.w v24, v16, v0.t
	; CHECK-NEXT: csrr a6, vlenb			; CHECK-NEXT: csrr a6, vlenb
	; CHECK-NEXT: slli a6, a6, 4			; CHECK-NEXT: slli a6, a6, 4
	; CHECK-NEXT: add a6, sp, a6			; CHECK-NEXT: add a6, sp, a6
	; CHECK-NEXT: addi a6, a6, 16			; CHECK-NEXT: addi a6, a6, 16
	; CHECK-NEXT: vs8r.v v24, (a6) # Unknown-size Folded Spill			; CHECK-NEXT: vs8r.v v24, (a6) # Unknown-size Folded Spill
	; CHECK-NEXT: bltu a5, a3, .LBB16_8			; CHECK-NEXT: bltu a5, a3, .LBB16_8
	; CHECK-NEXT: # %bb.7:			; CHECK-NEXT: # %bb.7:
	; CHECK-NEXT: li a5, 16			; CHECK-NEXT: li a5, 16
	; CHECK-NEXT: .LBB16_8:			; CHECK-NEXT: .LBB16_8:
	; CHECK-NEXT: vsetvli zero, a5, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a5, e32, m4, ta, mu
	; CHECK-NEXT: li a5, 64			; CHECK-NEXT: li a5, 64
	; CHECK-NEXT: vmv1r.v v0, v28			; CHECK-NEXT: vmv1r.v v0, v3
	; CHECK-NEXT: vncvt.x.x.w v16, v8, v0.t			; CHECK-NEXT: vncvt.x.x.w v16, v8, v0.t
	; CHECK-NEXT: csrr a6, vlenb			; CHECK-NEXT: csrr a6, vlenb
	; CHECK-NEXT: li t0, 48			; CHECK-NEXT: li t0, 48
	; CHECK-NEXT: mul a6, a6, t0			; CHECK-NEXT: mul a6, a6, t0
	; CHECK-NEXT: add a6, sp, a6			; CHECK-NEXT: add a6, sp, a6
	; CHECK-NEXT: addi a6, a6, 16			; CHECK-NEXT: addi a6, a6, 16
	; CHECK-NEXT: vs8r.v v16, (a6) # Unknown-size Folded Spill			; CHECK-NEXT: vs8r.v v16, (a6) # Unknown-size Folded Spill
	; CHECK-NEXT: bltu a7, a5, .LBB16_10			; CHECK-NEXT: bltu a7, a5, .LBB16_10
	; CHECK-NEXT: # %bb.9:			; CHECK-NEXT: # %bb.9:
	; CHECK-NEXT: li a7, 64			; CHECK-NEXT: li a7, 64
	; CHECK-NEXT: .LBB16_10:			; CHECK-NEXT: .LBB16_10:
	; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu			; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
	; CHECK-NEXT: vslidedown.vi v28, v1, 4			; CHECK-NEXT: vslidedown.vi v3, v1, 4
	; CHECK-NEXT: addi t0, a7, -32			; CHECK-NEXT: addi t0, a7, -32
	; CHECK-NEXT: addi a5, a1, 128			; CHECK-NEXT: addi a5, a1, 128
	; CHECK-NEXT: mv a6, a2			; CHECK-NEXT: mv a6, a2
	; CHECK-NEXT: bltu a7, t0, .LBB16_12			; CHECK-NEXT: bltu a7, t0, .LBB16_12
	; CHECK-NEXT: # %bb.11:			; CHECK-NEXT: # %bb.11:
	; CHECK-NEXT: mv a6, t0			; CHECK-NEXT: mv a6, t0
	; CHECK-NEXT: .LBB16_12:			; CHECK-NEXT: .LBB16_12:
	; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu			; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
	; CHECK-NEXT: vslidedown.vi v0, v28, 2			; CHECK-NEXT: vslidedown.vi v0, v3, 2
	; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu			; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
	; CHECK-NEXT: vle64.v v16, (a5)			; CHECK-NEXT: vle64.v v16, (a5)
	; CHECK-NEXT: addi a5, a6, -16			; CHECK-NEXT: addi a5, a6, -16
	; CHECK-NEXT: mv t0, a2			; CHECK-NEXT: mv t0, a2
	; CHECK-NEXT: bltu a6, a5, .LBB16_14			; CHECK-NEXT: bltu a6, a5, .LBB16_14
	; CHECK-NEXT: # %bb.13:			; CHECK-NEXT: # %bb.13:
	; CHECK-NEXT: mv t0, a5			; CHECK-NEXT: mv t0, a5
	; CHECK-NEXT: .LBB16_14:			; CHECK-NEXT: .LBB16_14:
	; CHECK-NEXT: vle64.v v8, (a1)			; CHECK-NEXT: vle64.v v8, (a1)
	; CHECK-NEXT: li a5, 32			; CHECK-NEXT: li a5, 32
	; CHECK-NEXT: vsetvli zero, t0, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, t0, e32, m4, ta, mu
	; CHECK-NEXT: vncvt.x.x.w v24, v16, v0.t			; CHECK-NEXT: vncvt.x.x.w v24, v16, v0.t
	; CHECK-NEXT: csrr t0, vlenb			; CHECK-NEXT: csrr t0, vlenb
	; CHECK-NEXT: slli t0, t0, 3			; CHECK-NEXT: slli t0, t0, 3
	; CHECK-NEXT: add t0, sp, t0			; CHECK-NEXT: add t0, sp, t0
	; CHECK-NEXT: addi t0, t0, 16			; CHECK-NEXT: addi t0, t0, 16
	; CHECK-NEXT: vs8r.v v24, (t0) # Unknown-size Folded Spill			; CHECK-NEXT: vs8r.v v24, (t0) # Unknown-size Folded Spill
	; CHECK-NEXT: bltu a6, a3, .LBB16_16			; CHECK-NEXT: bltu a6, a3, .LBB16_16
	; CHECK-NEXT: # %bb.15:			; CHECK-NEXT: # %bb.15:
	; CHECK-NEXT: li a6, 16			; CHECK-NEXT: li a6, 16
	; CHECK-NEXT: .LBB16_16:			; CHECK-NEXT: .LBB16_16:
	; CHECK-NEXT: addi t0, a1, 384			; CHECK-NEXT: addi t0, a1, 384
	; CHECK-NEXT: vsetvli zero, a6, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a6, e32, m4, ta, mu
	; CHECK-NEXT: vmv1r.v v0, v28			; CHECK-NEXT: vmv1r.v v0, v3
	; CHECK-NEXT: vncvt.x.x.w v16, v8, v0.t			; CHECK-NEXT: vncvt.x.x.w v16, v8, v0.t
	; CHECK-NEXT: csrr a6, vlenb			; CHECK-NEXT: csrr a6, vlenb
	; CHECK-NEXT: li t1, 40			; CHECK-NEXT: li t1, 40
	; CHECK-NEXT: mul a6, a6, t1			; CHECK-NEXT: mul a6, a6, t1
	; CHECK-NEXT: add a6, sp, a6			; CHECK-NEXT: add a6, sp, a6
	; CHECK-NEXT: addi a6, a6, 16			; CHECK-NEXT: addi a6, a6, 16
	; CHECK-NEXT: vs8r.v v16, (a6) # Unknown-size Folded Spill			; CHECK-NEXT: vs8r.v v16, (a6) # Unknown-size Folded Spill
	; CHECK-NEXT: bltu a4, a5, .LBB16_18			; CHECK-NEXT: bltu a4, a5, .LBB16_18
	▲ Show 20 Lines • Show All 183 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll

	Show All 33 Lines
	}			}

	; One vXf64 test case to very that we don't optimize it.			; One vXf64 test case to very that we don't optimize it.
	; FIXME: Is there better codegen we can do here?			; FIXME: Is there better codegen we can do here?
	define <4 x double> @interleave_v2f64(<2 x double> %x, <2 x double> %y) {			define <4 x double> @interleave_v2f64(<2 x double> %x, <2 x double> %y) {
	; RV32-V128-LABEL: interleave_v2f64:			; RV32-V128-LABEL: interleave_v2f64:
	; RV32-V128: # %bb.0:			; RV32-V128: # %bb.0:
	; RV32-V128-NEXT: vmv1r.v v12, v9			; RV32-V128-NEXT: vmv1r.v v12, v9
				; RV32-V128-NEXT: # kill: def $v8 killed $v8 def $v8m2
	; RV32-V128-NEXT: vsetivli zero, 4, e16, mf2, ta, mu			; RV32-V128-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
	; RV32-V128-NEXT: vid.v v9			; RV32-V128-NEXT: vid.v v10
	; RV32-V128-NEXT: vsrl.vi v9, v9, 1			; RV32-V128-NEXT: vsrl.vi v14, v10, 1
	; RV32-V128-NEXT: vsetvli zero, zero, e64, m2, ta, mu			; RV32-V128-NEXT: vsetvli zero, zero, e64, m2, ta, mu
	; RV32-V128-NEXT: li a0, 10			; RV32-V128-NEXT: li a0, 10
	; RV32-V128-NEXT: vmv.s.x v0, a0			; RV32-V128-NEXT: vmv.s.x v0, a0
	; RV32-V128-NEXT: vrgatherei16.vv v10, v8, v9			; RV32-V128-NEXT: vrgatherei16.vv v10, v8, v14
	; RV32-V128-NEXT: vrgatherei16.vv v10, v12, v9, v0.t			; RV32-V128-NEXT: vrgatherei16.vv v10, v12, v14, v0.t
	; RV32-V128-NEXT: vmv.v.v v8, v10			; RV32-V128-NEXT: vmv.v.v v8, v10
	; RV32-V128-NEXT: ret			; RV32-V128-NEXT: ret
	;			;
	; RV64-V128-LABEL: interleave_v2f64:			; RV64-V128-LABEL: interleave_v2f64:
	; RV64-V128: # %bb.0:			; RV64-V128: # %bb.0:
	; RV64-V128-NEXT: vmv1r.v v12, v9			; RV64-V128-NEXT: vmv1r.v v12, v9
				; RV64-V128-NEXT: # kill: def $v8 killed $v8 def $v8m2
	; RV64-V128-NEXT: vsetivli zero, 4, e64, m2, ta, mu			; RV64-V128-NEXT: vsetivli zero, 4, e64, m2, ta, mu
	; RV64-V128-NEXT: vid.v v10			; RV64-V128-NEXT: vid.v v10
	; RV64-V128-NEXT: vsrl.vi v14, v10, 1			; RV64-V128-NEXT: vsrl.vi v14, v10, 1
	; RV64-V128-NEXT: li a0, 10			; RV64-V128-NEXT: li a0, 10
	; RV64-V128-NEXT: vmv.s.x v0, a0			; RV64-V128-NEXT: vmv.s.x v0, a0
	; RV64-V128-NEXT: vrgather.vv v10, v8, v14			; RV64-V128-NEXT: vrgather.vv v10, v8, v14
	; RV64-V128-NEXT: vrgather.vv v10, v12, v14, v0.t			; RV64-V128-NEXT: vrgather.vv v10, v12, v14, v0.t
	; RV64-V128-NEXT: vmv.v.v v8, v10			; RV64-V128-NEXT: vmv.v.v v8, v10
	▲ Show 20 Lines • Show All 198 Lines • ▼ Show 20 Lines
	; RV32-V128-NEXT: slli a0, a0, 4			; RV32-V128-NEXT: slli a0, a0, 4
	; RV32-V128-NEXT: sub sp, sp, a0			; RV32-V128-NEXT: sub sp, sp, a0
	; RV32-V128-NEXT: lui a0, %hi(.LCPI10_0)			; RV32-V128-NEXT: lui a0, %hi(.LCPI10_0)
	; RV32-V128-NEXT: addi a0, a0, %lo(.LCPI10_0)			; RV32-V128-NEXT: addi a0, a0, %lo(.LCPI10_0)
	; RV32-V128-NEXT: li a1, 32			; RV32-V128-NEXT: li a1, 32
	; RV32-V128-NEXT: vsetvli zero, a1, e32, m8, ta, mu			; RV32-V128-NEXT: vsetvli zero, a1, e32, m8, ta, mu
	; RV32-V128-NEXT: vle32.v v0, (a0)			; RV32-V128-NEXT: vle32.v v0, (a0)
	; RV32-V128-NEXT: vmv8r.v v24, v8			; RV32-V128-NEXT: vmv8r.v v24, v8
	; RV32-V128-NEXT: vrgather.vv v8, v24, v0
	; RV32-V128-NEXT: addi a0, sp, 16			; RV32-V128-NEXT: addi a0, sp, 16
	; RV32-V128-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill			; RV32-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
				; RV32-V128-NEXT: vrgather.vv v8, v24, v0
	; RV32-V128-NEXT: lui a0, %hi(.LCPI10_1)			; RV32-V128-NEXT: lui a0, %hi(.LCPI10_1)
	; RV32-V128-NEXT: addi a0, a0, %lo(.LCPI10_1)			; RV32-V128-NEXT: addi a0, a0, %lo(.LCPI10_1)
	; RV32-V128-NEXT: vle32.v v24, (a0)			; RV32-V128-NEXT: vle32.v v24, (a0)
	; RV32-V128-NEXT: csrr a0, vlenb			; RV32-V128-NEXT: csrr a0, vlenb
	; RV32-V128-NEXT: slli a0, a0, 3			; RV32-V128-NEXT: slli a0, a0, 3
	; RV32-V128-NEXT: add a0, sp, a0			; RV32-V128-NEXT: add a0, sp, a0
	; RV32-V128-NEXT: addi a0, a0, 16			; RV32-V128-NEXT: addi a0, a0, 16
	; RV32-V128-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill			; RV32-V128-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
	Show All 31 Lines
	; RV64-V128-NEXT: slli a0, a0, 4			; RV64-V128-NEXT: slli a0, a0, 4
	; RV64-V128-NEXT: sub sp, sp, a0			; RV64-V128-NEXT: sub sp, sp, a0
	; RV64-V128-NEXT: lui a0, %hi(.LCPI10_0)			; RV64-V128-NEXT: lui a0, %hi(.LCPI10_0)
	; RV64-V128-NEXT: addi a0, a0, %lo(.LCPI10_0)			; RV64-V128-NEXT: addi a0, a0, %lo(.LCPI10_0)
	; RV64-V128-NEXT: li a1, 32			; RV64-V128-NEXT: li a1, 32
	; RV64-V128-NEXT: vsetvli zero, a1, e32, m8, ta, mu			; RV64-V128-NEXT: vsetvli zero, a1, e32, m8, ta, mu
	; RV64-V128-NEXT: vle32.v v0, (a0)			; RV64-V128-NEXT: vle32.v v0, (a0)
	; RV64-V128-NEXT: vmv8r.v v24, v8			; RV64-V128-NEXT: vmv8r.v v24, v8
	; RV64-V128-NEXT: vrgather.vv v8, v24, v0
	; RV64-V128-NEXT: addi a0, sp, 16			; RV64-V128-NEXT: addi a0, sp, 16
	; RV64-V128-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill			; RV64-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
				; RV64-V128-NEXT: vrgather.vv v8, v24, v0
	; RV64-V128-NEXT: lui a0, %hi(.LCPI10_1)			; RV64-V128-NEXT: lui a0, %hi(.LCPI10_1)
	; RV64-V128-NEXT: addi a0, a0, %lo(.LCPI10_1)			; RV64-V128-NEXT: addi a0, a0, %lo(.LCPI10_1)
	; RV64-V128-NEXT: vle32.v v24, (a0)			; RV64-V128-NEXT: vle32.v v24, (a0)
	; RV64-V128-NEXT: csrr a0, vlenb			; RV64-V128-NEXT: csrr a0, vlenb
	; RV64-V128-NEXT: slli a0, a0, 3			; RV64-V128-NEXT: slli a0, a0, 3
	; RV64-V128-NEXT: add a0, sp, a0			; RV64-V128-NEXT: add a0, sp, a0
	; RV64-V128-NEXT: addi a0, a0, 16			; RV64-V128-NEXT: addi a0, a0, 16
	; RV64-V128-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill			; RV64-V128-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
	Show All 38 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll

	Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
	; LMULMAX2-NEXT: vle8.v v8, (a0)			; LMULMAX2-NEXT: vle8.v v8, (a0)
	; LMULMAX2-NEXT: vsetivli zero, 8, e8, m1, ta, mu			; LMULMAX2-NEXT: vsetivli zero, 8, e8, m1, ta, mu
	; LMULMAX2-NEXT: vslidedown.vi v10, v8, 8			; LMULMAX2-NEXT: vslidedown.vi v10, v8, 8
	; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu			; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
	; LMULMAX2-NEXT: vsext.vf4 v12, v10			; LMULMAX2-NEXT: vsext.vf4 v12, v10
	; LMULMAX2-NEXT: vsetivli zero, 16, e8, m2, ta, mu			; LMULMAX2-NEXT: vsetivli zero, 16, e8, m2, ta, mu
	; LMULMAX2-NEXT: vslidedown.vi v10, v8, 16			; LMULMAX2-NEXT: vslidedown.vi v10, v8, 16
	; LMULMAX2-NEXT: vsetivli zero, 8, e8, m1, ta, mu			; LMULMAX2-NEXT: vsetivli zero, 8, e8, m1, ta, mu
	; LMULMAX2-NEXT: vslidedown.vi v9, v10, 8			; LMULMAX2-NEXT: vslidedown.vi v14, v10, 8
	; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu			; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
	; LMULMAX2-NEXT: vsext.vf4 v14, v9			; LMULMAX2-NEXT: vsext.vf4 v16, v14
	; LMULMAX2-NEXT: vsext.vf4 v16, v8			; LMULMAX2-NEXT: vsext.vf4 v14, v8
	; LMULMAX2-NEXT: vsext.vf4 v8, v10			; LMULMAX2-NEXT: vsext.vf4 v8, v10
	; LMULMAX2-NEXT: addi a0, a1, 64			; LMULMAX2-NEXT: addi a0, a1, 64
	; LMULMAX2-NEXT: vse32.v v8, (a0)			; LMULMAX2-NEXT: vse32.v v8, (a0)
	; LMULMAX2-NEXT: vse32.v v16, (a1)			; LMULMAX2-NEXT: vse32.v v14, (a1)
	; LMULMAX2-NEXT: addi a0, a1, 96			; LMULMAX2-NEXT: addi a0, a1, 96
	; LMULMAX2-NEXT: vse32.v v14, (a0)			; LMULMAX2-NEXT: vse32.v v16, (a0)
	; LMULMAX2-NEXT: addi a0, a1, 32			; LMULMAX2-NEXT: addi a0, a1, 32
	; LMULMAX2-NEXT: vse32.v v12, (a0)			; LMULMAX2-NEXT: vse32.v v12, (a0)
	; LMULMAX2-NEXT: ret			; LMULMAX2-NEXT: ret
	;			;
	; LMULMAX1-LABEL: sext_v32i8_v32i32:			; LMULMAX1-LABEL: sext_v32i8_v32i32:
	; LMULMAX1: # %bb.0:			; LMULMAX1: # %bb.0:
	; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu			; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
	; LMULMAX1-NEXT: addi a2, a0, 16			; LMULMAX1-NEXT: addi a2, a0, 16
	▲ Show 20 Lines • Show All 107 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll

	Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
	}			}

	; One vXi64 test case to very that we don't optimize it.			; One vXi64 test case to very that we don't optimize it.
	; FIXME: Is there better codegen we can do here?			; FIXME: Is there better codegen we can do here?
	define <4 x i64> @interleave_v2i64(<2 x i64> %x, <2 x i64> %y) {			define <4 x i64> @interleave_v2i64(<2 x i64> %x, <2 x i64> %y) {
	; RV32-V128-LABEL: interleave_v2i64:			; RV32-V128-LABEL: interleave_v2i64:
	; RV32-V128: # %bb.0:			; RV32-V128: # %bb.0:
	; RV32-V128-NEXT: vmv1r.v v12, v9			; RV32-V128-NEXT: vmv1r.v v12, v9
				; RV32-V128-NEXT: # kill: def $v8 killed $v8 def $v8m2
	; RV32-V128-NEXT: vsetivli zero, 4, e16, mf2, ta, mu			; RV32-V128-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
	; RV32-V128-NEXT: vid.v v9			; RV32-V128-NEXT: vid.v v10
	; RV32-V128-NEXT: vsrl.vi v9, v9, 1			; RV32-V128-NEXT: vsrl.vi v14, v10, 1
	; RV32-V128-NEXT: vsetvli zero, zero, e64, m2, ta, mu			; RV32-V128-NEXT: vsetvli zero, zero, e64, m2, ta, mu
	; RV32-V128-NEXT: li a0, 10			; RV32-V128-NEXT: li a0, 10
	; RV32-V128-NEXT: vmv.s.x v0, a0			; RV32-V128-NEXT: vmv.s.x v0, a0
	; RV32-V128-NEXT: vrgatherei16.vv v10, v8, v9			; RV32-V128-NEXT: vrgatherei16.vv v10, v8, v14
	; RV32-V128-NEXT: vrgatherei16.vv v10, v12, v9, v0.t			; RV32-V128-NEXT: vrgatherei16.vv v10, v12, v14, v0.t
	; RV32-V128-NEXT: vmv.v.v v8, v10			; RV32-V128-NEXT: vmv.v.v v8, v10
	; RV32-V128-NEXT: ret			; RV32-V128-NEXT: ret
	;			;
	; RV64-V128-LABEL: interleave_v2i64:			; RV64-V128-LABEL: interleave_v2i64:
	; RV64-V128: # %bb.0:			; RV64-V128: # %bb.0:
	; RV64-V128-NEXT: vmv1r.v v12, v9			; RV64-V128-NEXT: vmv1r.v v12, v9
				; RV64-V128-NEXT: # kill: def $v8 killed $v8 def $v8m2
	; RV64-V128-NEXT: vsetivli zero, 4, e64, m2, ta, mu			; RV64-V128-NEXT: vsetivli zero, 4, e64, m2, ta, mu
	; RV64-V128-NEXT: vid.v v10			; RV64-V128-NEXT: vid.v v10
	; RV64-V128-NEXT: vsrl.vi v14, v10, 1			; RV64-V128-NEXT: vsrl.vi v14, v10, 1
	; RV64-V128-NEXT: li a0, 10			; RV64-V128-NEXT: li a0, 10
	; RV64-V128-NEXT: vmv.s.x v0, a0			; RV64-V128-NEXT: vmv.s.x v0, a0
	; RV64-V128-NEXT: vrgather.vv v10, v8, v14			; RV64-V128-NEXT: vrgather.vv v10, v8, v14
	; RV64-V128-NEXT: vrgather.vv v10, v12, v14, v0.t			; RV64-V128-NEXT: vrgather.vv v10, v12, v14, v0.t
	; RV64-V128-NEXT: vmv.v.v v8, v10			; RV64-V128-NEXT: vmv.v.v v8, v10
	▲ Show 20 Lines • Show All 291 Lines • ▼ Show 20 Lines
	; RV32-V128-NEXT: slli a0, a0, 4			; RV32-V128-NEXT: slli a0, a0, 4
	; RV32-V128-NEXT: sub sp, sp, a0			; RV32-V128-NEXT: sub sp, sp, a0
	; RV32-V128-NEXT: lui a0, %hi(.LCPI15_0)			; RV32-V128-NEXT: lui a0, %hi(.LCPI15_0)
	; RV32-V128-NEXT: addi a0, a0, %lo(.LCPI15_0)			; RV32-V128-NEXT: addi a0, a0, %lo(.LCPI15_0)
	; RV32-V128-NEXT: li a1, 32			; RV32-V128-NEXT: li a1, 32
	; RV32-V128-NEXT: vsetvli zero, a1, e32, m8, ta, mu			; RV32-V128-NEXT: vsetvli zero, a1, e32, m8, ta, mu
	; RV32-V128-NEXT: vle32.v v0, (a0)			; RV32-V128-NEXT: vle32.v v0, (a0)
	; RV32-V128-NEXT: vmv8r.v v24, v8			; RV32-V128-NEXT: vmv8r.v v24, v8
	; RV32-V128-NEXT: vrgather.vv v8, v24, v0
	; RV32-V128-NEXT: addi a0, sp, 16			; RV32-V128-NEXT: addi a0, sp, 16
	; RV32-V128-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill			; RV32-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
				; RV32-V128-NEXT: vrgather.vv v8, v24, v0
	; RV32-V128-NEXT: lui a0, %hi(.LCPI15_1)			; RV32-V128-NEXT: lui a0, %hi(.LCPI15_1)
	; RV32-V128-NEXT: addi a0, a0, %lo(.LCPI15_1)			; RV32-V128-NEXT: addi a0, a0, %lo(.LCPI15_1)
	; RV32-V128-NEXT: vle32.v v24, (a0)			; RV32-V128-NEXT: vle32.v v24, (a0)
	; RV32-V128-NEXT: csrr a0, vlenb			; RV32-V128-NEXT: csrr a0, vlenb
	; RV32-V128-NEXT: slli a0, a0, 3			; RV32-V128-NEXT: slli a0, a0, 3
	; RV32-V128-NEXT: add a0, sp, a0			; RV32-V128-NEXT: add a0, sp, a0
	; RV32-V128-NEXT: addi a0, a0, 16			; RV32-V128-NEXT: addi a0, a0, 16
	; RV32-V128-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill			; RV32-V128-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
	Show All 31 Lines
	; RV64-V128-NEXT: slli a0, a0, 4			; RV64-V128-NEXT: slli a0, a0, 4
	; RV64-V128-NEXT: sub sp, sp, a0			; RV64-V128-NEXT: sub sp, sp, a0
	; RV64-V128-NEXT: lui a0, %hi(.LCPI15_0)			; RV64-V128-NEXT: lui a0, %hi(.LCPI15_0)
	; RV64-V128-NEXT: addi a0, a0, %lo(.LCPI15_0)			; RV64-V128-NEXT: addi a0, a0, %lo(.LCPI15_0)
	; RV64-V128-NEXT: li a1, 32			; RV64-V128-NEXT: li a1, 32
	; RV64-V128-NEXT: vsetvli zero, a1, e32, m8, ta, mu			; RV64-V128-NEXT: vsetvli zero, a1, e32, m8, ta, mu
	; RV64-V128-NEXT: vle32.v v0, (a0)			; RV64-V128-NEXT: vle32.v v0, (a0)
	; RV64-V128-NEXT: vmv8r.v v24, v8			; RV64-V128-NEXT: vmv8r.v v24, v8
	; RV64-V128-NEXT: vrgather.vv v8, v24, v0
	; RV64-V128-NEXT: addi a0, sp, 16			; RV64-V128-NEXT: addi a0, sp, 16
	; RV64-V128-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill			; RV64-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
				; RV64-V128-NEXT: vrgather.vv v8, v24, v0
	; RV64-V128-NEXT: lui a0, %hi(.LCPI15_1)			; RV64-V128-NEXT: lui a0, %hi(.LCPI15_1)
	; RV64-V128-NEXT: addi a0, a0, %lo(.LCPI15_1)			; RV64-V128-NEXT: addi a0, a0, %lo(.LCPI15_1)
	; RV64-V128-NEXT: vle32.v v24, (a0)			; RV64-V128-NEXT: vle32.v v24, (a0)
	; RV64-V128-NEXT: csrr a0, vlenb			; RV64-V128-NEXT: csrr a0, vlenb
	; RV64-V128-NEXT: slli a0, a0, 3			; RV64-V128-NEXT: slli a0, a0, 3
	; RV64-V128-NEXT: add a0, sp, a0			; RV64-V128-NEXT: add a0, sp, a0
	; RV64-V128-NEXT: addi a0, a0, 16			; RV64-V128-NEXT: addi a0, a0, 16
	; RV64-V128-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill			; RV64-V128-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
	Show All 38 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

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	Show First 20 Lines • Show All 12,813 Lines • ▼ Show 20 Lines
	; RV64ZVE32F-NEXT: vsetivli zero, 13, e8, m2, tu, mu			; RV64ZVE32F-NEXT: vsetivli zero, 13, e8, m2, tu, mu
	; RV64ZVE32F-NEXT: vslideup.vi v10, v14, 12			; RV64ZVE32F-NEXT: vslideup.vi v10, v14, 12
	; RV64ZVE32F-NEXT: .LBB98_21: # %else35			; RV64ZVE32F-NEXT: .LBB98_21: # %else35
	; RV64ZVE32F-NEXT: lui a2, 2			; RV64ZVE32F-NEXT: lui a2, 2
	; RV64ZVE32F-NEXT: and a2, a1, a2			; RV64ZVE32F-NEXT: and a2, a1, a2
	; RV64ZVE32F-NEXT: beqz a2, .LBB98_23			; RV64ZVE32F-NEXT: beqz a2, .LBB98_23
	; RV64ZVE32F-NEXT: # %bb.22: # %cond.load37			; RV64ZVE32F-NEXT: # %bb.22: # %cond.load37
	; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v9, v12, 1			; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 1
	; RV64ZVE32F-NEXT: vmv.x.s a2, v9			; RV64ZVE32F-NEXT: vmv.x.s a2, v13
	; RV64ZVE32F-NEXT: add a2, a0, a2			; RV64ZVE32F-NEXT: add a2, a0, a2
	; RV64ZVE32F-NEXT: lb a2, 0(a2)			; RV64ZVE32F-NEXT: lb a2, 0(a2)
	; RV64ZVE32F-NEXT: li a3, 32			; RV64ZVE32F-NEXT: li a3, 32
	; RV64ZVE32F-NEXT: vsetvli zero, a3, e8, m2, ta, mu			; RV64ZVE32F-NEXT: vsetvli zero, a3, e8, m2, ta, mu
	; RV64ZVE32F-NEXT: vmv.s.x v14, a2			; RV64ZVE32F-NEXT: vmv.s.x v14, a2
	; RV64ZVE32F-NEXT: vsetivli zero, 14, e8, m2, tu, mu			; RV64ZVE32F-NEXT: vsetivli zero, 14, e8, m2, tu, mu
	; RV64ZVE32F-NEXT: vslideup.vi v10, v14, 13			; RV64ZVE32F-NEXT: vslideup.vi v10, v14, 13
	; RV64ZVE32F-NEXT: .LBB98_23: # %else38			; RV64ZVE32F-NEXT: .LBB98_23: # %else38
	; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
	; RV64ZVE32F-NEXT: lui a2, 4			; RV64ZVE32F-NEXT: lui a2, 4
	; RV64ZVE32F-NEXT: and a2, a1, a2			; RV64ZVE32F-NEXT: and a2, a1, a2
	; RV64ZVE32F-NEXT: vslidedown.vi v9, v12, 2			; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 2
	; RV64ZVE32F-NEXT: beqz a2, .LBB98_25			; RV64ZVE32F-NEXT: beqz a2, .LBB98_25
	; RV64ZVE32F-NEXT: # %bb.24: # %cond.load40			; RV64ZVE32F-NEXT: # %bb.24: # %cond.load40
	; RV64ZVE32F-NEXT: vmv.x.s a2, v9			; RV64ZVE32F-NEXT: vmv.x.s a2, v12
	; RV64ZVE32F-NEXT: add a2, a0, a2			; RV64ZVE32F-NEXT: add a2, a0, a2
	; RV64ZVE32F-NEXT: lb a2, 0(a2)			; RV64ZVE32F-NEXT: lb a2, 0(a2)
	; RV64ZVE32F-NEXT: li a3, 32			; RV64ZVE32F-NEXT: li a3, 32
	; RV64ZVE32F-NEXT: vsetvli zero, a3, e8, m2, ta, mu			; RV64ZVE32F-NEXT: vsetvli zero, a3, e8, m2, ta, mu
	; RV64ZVE32F-NEXT: vmv.s.x v12, a2			; RV64ZVE32F-NEXT: vmv.s.x v14, a2
	; RV64ZVE32F-NEXT: vsetivli zero, 15, e8, m2, tu, mu			; RV64ZVE32F-NEXT: vsetivli zero, 15, e8, m2, tu, mu
	; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 14			; RV64ZVE32F-NEXT: vslideup.vi v10, v14, 14
	; RV64ZVE32F-NEXT: .LBB98_25: # %else41			; RV64ZVE32F-NEXT: .LBB98_25: # %else41
	; RV64ZVE32F-NEXT: lui a2, 8			; RV64ZVE32F-NEXT: lui a2, 8
	; RV64ZVE32F-NEXT: and a2, a1, a2			; RV64ZVE32F-NEXT: and a2, a1, a2
	; RV64ZVE32F-NEXT: beqz a2, .LBB98_27			; RV64ZVE32F-NEXT: beqz a2, .LBB98_27
	; RV64ZVE32F-NEXT: # %bb.26: # %cond.load43			; RV64ZVE32F-NEXT: # %bb.26: # %cond.load43
	; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1			; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 1
	; RV64ZVE32F-NEXT: vmv.x.s a2, v9			; RV64ZVE32F-NEXT: vmv.x.s a2, v12
	; RV64ZVE32F-NEXT: add a2, a0, a2			; RV64ZVE32F-NEXT: add a2, a0, a2
	; RV64ZVE32F-NEXT: lb a2, 0(a2)			; RV64ZVE32F-NEXT: lb a2, 0(a2)
	; RV64ZVE32F-NEXT: li a3, 32			; RV64ZVE32F-NEXT: li a3, 32
	; RV64ZVE32F-NEXT: vsetvli zero, a3, e8, m2, ta, mu			; RV64ZVE32F-NEXT: vsetvli zero, a3, e8, m2, ta, mu
	; RV64ZVE32F-NEXT: vmv.s.x v12, a2			; RV64ZVE32F-NEXT: vmv.s.x v12, a2
	; RV64ZVE32F-NEXT: vsetivli zero, 16, e8, m2, tu, mu			; RV64ZVE32F-NEXT: vsetivli zero, 16, e8, m2, tu, mu
	; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 15			; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 15
	; RV64ZVE32F-NEXT: .LBB98_27: # %else44			; RV64ZVE32F-NEXT: .LBB98_27: # %else44
	Show All 11 Lines
	; RV64ZVE32F-NEXT: vsetivli zero, 17, e8, m2, tu, mu			; RV64ZVE32F-NEXT: vsetivli zero, 17, e8, m2, tu, mu
	; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 16			; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 16
	; RV64ZVE32F-NEXT: .LBB98_29: # %else47			; RV64ZVE32F-NEXT: .LBB98_29: # %else47
	; RV64ZVE32F-NEXT: lui a2, 32			; RV64ZVE32F-NEXT: lui a2, 32
	; RV64ZVE32F-NEXT: and a2, a1, a2			; RV64ZVE32F-NEXT: and a2, a1, a2
	; RV64ZVE32F-NEXT: beqz a2, .LBB98_31			; RV64ZVE32F-NEXT: beqz a2, .LBB98_31
	; RV64ZVE32F-NEXT: # %bb.30: # %cond.load49			; RV64ZVE32F-NEXT: # %bb.30: # %cond.load49
	; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1			; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 1
	; RV64ZVE32F-NEXT: vmv.x.s a2, v9			; RV64ZVE32F-NEXT: vmv.x.s a2, v12
	; RV64ZVE32F-NEXT: add a2, a0, a2			; RV64ZVE32F-NEXT: add a2, a0, a2
	; RV64ZVE32F-NEXT: lb a2, 0(a2)			; RV64ZVE32F-NEXT: lb a2, 0(a2)
	; RV64ZVE32F-NEXT: li a3, 32			; RV64ZVE32F-NEXT: li a3, 32
	; RV64ZVE32F-NEXT: vsetvli zero, a3, e8, m2, ta, mu			; RV64ZVE32F-NEXT: vsetvli zero, a3, e8, m2, ta, mu
	; RV64ZVE32F-NEXT: vmv.s.x v12, a2			; RV64ZVE32F-NEXT: vmv.s.x v12, a2
	; RV64ZVE32F-NEXT: vsetivli zero, 18, e8, m2, tu, mu			; RV64ZVE32F-NEXT: vsetivli zero, 18, e8, m2, tu, mu
	; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 17			; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 17
	; RV64ZVE32F-NEXT: .LBB98_31: # %else50			; RV64ZVE32F-NEXT: .LBB98_31: # %else50
	; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
	; RV64ZVE32F-NEXT: lui a2, 64			; RV64ZVE32F-NEXT: lui a2, 64
	; RV64ZVE32F-NEXT: and a2, a1, a2			; RV64ZVE32F-NEXT: and a2, a1, a2
	; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2			; RV64ZVE32F-NEXT: vslidedown.vi v13, v8, 2
	; RV64ZVE32F-NEXT: beqz a2, .LBB98_33			; RV64ZVE32F-NEXT: beqz a2, .LBB98_33
	; RV64ZVE32F-NEXT: # %bb.32: # %cond.load52			; RV64ZVE32F-NEXT: # %bb.32: # %cond.load52
	; RV64ZVE32F-NEXT: vmv.x.s a2, v12			; RV64ZVE32F-NEXT: vmv.x.s a2, v13
	; RV64ZVE32F-NEXT: add a2, a0, a2			; RV64ZVE32F-NEXT: add a2, a0, a2
	; RV64ZVE32F-NEXT: lb a2, 0(a2)			; RV64ZVE32F-NEXT: lb a2, 0(a2)
	; RV64ZVE32F-NEXT: li a3, 32			; RV64ZVE32F-NEXT: li a3, 32
	; RV64ZVE32F-NEXT: vsetvli zero, a3, e8, m2, ta, mu			; RV64ZVE32F-NEXT: vsetvli zero, a3, e8, m2, ta, mu
	; RV64ZVE32F-NEXT: vmv.s.x v14, a2			; RV64ZVE32F-NEXT: vmv.s.x v14, a2
	; RV64ZVE32F-NEXT: vsetivli zero, 19, e8, m2, tu, mu			; RV64ZVE32F-NEXT: vsetivli zero, 19, e8, m2, tu, mu
	; RV64ZVE32F-NEXT: vslideup.vi v10, v14, 18			; RV64ZVE32F-NEXT: vslideup.vi v10, v14, 18
	; RV64ZVE32F-NEXT: .LBB98_33: # %else53			; RV64ZVE32F-NEXT: .LBB98_33: # %else53
	; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
	; RV64ZVE32F-NEXT: lui a2, 128			; RV64ZVE32F-NEXT: lui a2, 128
	; RV64ZVE32F-NEXT: and a2, a1, a2			; RV64ZVE32F-NEXT: and a2, a1, a2
	; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 4			; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
	; RV64ZVE32F-NEXT: beqz a2, .LBB98_35			; RV64ZVE32F-NEXT: beqz a2, .LBB98_35
	; RV64ZVE32F-NEXT: # %bb.34: # %cond.load55			; RV64ZVE32F-NEXT: # %bb.34: # %cond.load55
	; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 1			; RV64ZVE32F-NEXT: vslidedown.vi v13, v13, 1
	; RV64ZVE32F-NEXT: vmv.x.s a2, v12			; RV64ZVE32F-NEXT: vmv.x.s a2, v13
	; RV64ZVE32F-NEXT: add a2, a0, a2			; RV64ZVE32F-NEXT: add a2, a0, a2
	; RV64ZVE32F-NEXT: lb a2, 0(a2)			; RV64ZVE32F-NEXT: lb a2, 0(a2)
	; RV64ZVE32F-NEXT: li a3, 32			; RV64ZVE32F-NEXT: li a3, 32
	; RV64ZVE32F-NEXT: vsetvli zero, a3, e8, m2, ta, mu			; RV64ZVE32F-NEXT: vsetvli zero, a3, e8, m2, ta, mu
	; RV64ZVE32F-NEXT: vmv.s.x v12, a2			; RV64ZVE32F-NEXT: vmv.s.x v14, a2
	; RV64ZVE32F-NEXT: vsetivli zero, 20, e8, m2, tu, mu			; RV64ZVE32F-NEXT: vsetivli zero, 20, e8, m2, tu, mu
	; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 19			; RV64ZVE32F-NEXT: vslideup.vi v10, v14, 19
	; RV64ZVE32F-NEXT: .LBB98_35: # %else56			; RV64ZVE32F-NEXT: .LBB98_35: # %else56
	; RV64ZVE32F-NEXT: lui a2, 256			; RV64ZVE32F-NEXT: lui a2, 256
	; RV64ZVE32F-NEXT: and a2, a1, a2			; RV64ZVE32F-NEXT: and a2, a1, a2
	; RV64ZVE32F-NEXT: beqz a2, .LBB98_37			; RV64ZVE32F-NEXT: beqz a2, .LBB98_37
	; RV64ZVE32F-NEXT: # %bb.36: # %cond.load58			; RV64ZVE32F-NEXT: # %bb.36: # %cond.load58
	; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, mu
	; RV64ZVE32F-NEXT: vmv.x.s a2, v9			; RV64ZVE32F-NEXT: vmv.x.s a2, v12
	; RV64ZVE32F-NEXT: add a2, a0, a2			; RV64ZVE32F-NEXT: add a2, a0, a2
	; RV64ZVE32F-NEXT: lb a2, 0(a2)			; RV64ZVE32F-NEXT: lb a2, 0(a2)
	; RV64ZVE32F-NEXT: li a3, 32			; RV64ZVE32F-NEXT: li a3, 32
	; RV64ZVE32F-NEXT: vsetvli zero, a3, e8, m2, ta, mu			; RV64ZVE32F-NEXT: vsetvli zero, a3, e8, m2, ta, mu
	; RV64ZVE32F-NEXT: vmv.s.x v12, a2			; RV64ZVE32F-NEXT: vmv.s.x v14, a2
	; RV64ZVE32F-NEXT: vsetivli zero, 21, e8, m2, tu, mu			; RV64ZVE32F-NEXT: vsetivli zero, 21, e8, m2, tu, mu
	; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 20			; RV64ZVE32F-NEXT: vslideup.vi v10, v14, 20
	; RV64ZVE32F-NEXT: .LBB98_37: # %else59			; RV64ZVE32F-NEXT: .LBB98_37: # %else59
	; RV64ZVE32F-NEXT: lui a2, 512			; RV64ZVE32F-NEXT: lui a2, 512
	; RV64ZVE32F-NEXT: and a2, a1, a2			; RV64ZVE32F-NEXT: and a2, a1, a2
	; RV64ZVE32F-NEXT: beqz a2, .LBB98_39			; RV64ZVE32F-NEXT: beqz a2, .LBB98_39
	; RV64ZVE32F-NEXT: # %bb.38: # %cond.load61			; RV64ZVE32F-NEXT: # %bb.38: # %cond.load61
	; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v12, v9, 1			; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 1
	; RV64ZVE32F-NEXT: vmv.x.s a2, v12			; RV64ZVE32F-NEXT: vmv.x.s a2, v13
	; RV64ZVE32F-NEXT: add a2, a0, a2			; RV64ZVE32F-NEXT: add a2, a0, a2
	; RV64ZVE32F-NEXT: lb a2, 0(a2)			; RV64ZVE32F-NEXT: lb a2, 0(a2)
	; RV64ZVE32F-NEXT: li a3, 32			; RV64ZVE32F-NEXT: li a3, 32
	; RV64ZVE32F-NEXT: vsetvli zero, a3, e8, m2, ta, mu			; RV64ZVE32F-NEXT: vsetvli zero, a3, e8, m2, ta, mu
	; RV64ZVE32F-NEXT: vmv.s.x v12, a2			; RV64ZVE32F-NEXT: vmv.s.x v14, a2
	; RV64ZVE32F-NEXT: vsetivli zero, 22, e8, m2, tu, mu			; RV64ZVE32F-NEXT: vsetivli zero, 22, e8, m2, tu, mu
	; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 21			; RV64ZVE32F-NEXT: vslideup.vi v10, v14, 21
	; RV64ZVE32F-NEXT: .LBB98_39: # %else62			; RV64ZVE32F-NEXT: .LBB98_39: # %else62
	; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 8			; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 8
	; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
	; RV64ZVE32F-NEXT: lui a2, 1024			; RV64ZVE32F-NEXT: lui a2, 1024
	; RV64ZVE32F-NEXT: and a2, a1, a2			; RV64ZVE32F-NEXT: and a2, a1, a2
	; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 2			; RV64ZVE32F-NEXT: vslidedown.vi v9, v12, 2
	; RV64ZVE32F-NEXT: beqz a2, .LBB98_41			; RV64ZVE32F-NEXT: beqz a2, .LBB98_41
	; RV64ZVE32F-NEXT: # %bb.40: # %cond.load64			; RV64ZVE32F-NEXT: # %bb.40: # %cond.load64
	; RV64ZVE32F-NEXT: vmv.x.s a2, v9			; RV64ZVE32F-NEXT: vmv.x.s a2, v9
	; RV64ZVE32F-NEXT: add a2, a0, a2			; RV64ZVE32F-NEXT: add a2, a0, a2
	; RV64ZVE32F-NEXT: lb a2, 0(a2)			; RV64ZVE32F-NEXT: lb a2, 0(a2)
	; RV64ZVE32F-NEXT: li a3, 32			; RV64ZVE32F-NEXT: li a3, 32
	; RV64ZVE32F-NEXT: vsetvli zero, a3, e8, m2, ta, mu			; RV64ZVE32F-NEXT: vsetvli zero, a3, e8, m2, ta, mu
	; RV64ZVE32F-NEXT: vmv.s.x v12, a2			; RV64ZVE32F-NEXT: vmv.s.x v12, a2
	▲ Show 20 Lines • Show All 207 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

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	Show First 20 Lines • Show All 11,151 Lines • ▼ Show 20 Lines
	; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 12			; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 12
	; RV64ZVE32F-NEXT: vse8.v v14, (a2)			; RV64ZVE32F-NEXT: vse8.v v14, (a2)
	; RV64ZVE32F-NEXT: .LBB92_21: # %else24			; RV64ZVE32F-NEXT: .LBB92_21: # %else24
	; RV64ZVE32F-NEXT: lui a2, 2			; RV64ZVE32F-NEXT: lui a2, 2
	; RV64ZVE32F-NEXT: and a2, a1, a2			; RV64ZVE32F-NEXT: and a2, a1, a2
	; RV64ZVE32F-NEXT: beqz a2, .LBB92_23			; RV64ZVE32F-NEXT: beqz a2, .LBB92_23
	; RV64ZVE32F-NEXT: # %bb.22: # %cond.store25			; RV64ZVE32F-NEXT: # %bb.22: # %cond.store25
	; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v11, v12, 1			; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 1
	; RV64ZVE32F-NEXT: vmv.x.s a2, v11			; RV64ZVE32F-NEXT: vmv.x.s a2, v13
	; RV64ZVE32F-NEXT: add a2, a0, a2			; RV64ZVE32F-NEXT: add a2, a0, a2
	; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 13			; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 13
	; RV64ZVE32F-NEXT: vse8.v v14, (a2)			; RV64ZVE32F-NEXT: vse8.v v14, (a2)
	; RV64ZVE32F-NEXT: .LBB92_23: # %else26			; RV64ZVE32F-NEXT: .LBB92_23: # %else26
	; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
	; RV64ZVE32F-NEXT: lui a2, 4			; RV64ZVE32F-NEXT: lui a2, 4
	; RV64ZVE32F-NEXT: and a2, a1, a2			; RV64ZVE32F-NEXT: and a2, a1, a2
	; RV64ZVE32F-NEXT: vslidedown.vi v11, v12, 2			; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 2
	; RV64ZVE32F-NEXT: beqz a2, .LBB92_25			; RV64ZVE32F-NEXT: beqz a2, .LBB92_25
	; RV64ZVE32F-NEXT: # %bb.24: # %cond.store27			; RV64ZVE32F-NEXT: # %bb.24: # %cond.store27
	; RV64ZVE32F-NEXT: vmv.x.s a2, v11			; RV64ZVE32F-NEXT: vmv.x.s a2, v12
	; RV64ZVE32F-NEXT: add a2, a0, a2			; RV64ZVE32F-NEXT: add a2, a0, a2
	; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 14			; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 14
	; RV64ZVE32F-NEXT: vse8.v v12, (a2)			; RV64ZVE32F-NEXT: vse8.v v14, (a2)
	; RV64ZVE32F-NEXT: .LBB92_25: # %else28			; RV64ZVE32F-NEXT: .LBB92_25: # %else28
	; RV64ZVE32F-NEXT: lui a2, 8			; RV64ZVE32F-NEXT: lui a2, 8
	; RV64ZVE32F-NEXT: and a2, a1, a2			; RV64ZVE32F-NEXT: and a2, a1, a2
	; RV64ZVE32F-NEXT: beqz a2, .LBB92_27			; RV64ZVE32F-NEXT: beqz a2, .LBB92_27
	; RV64ZVE32F-NEXT: # %bb.26: # %cond.store29			; RV64ZVE32F-NEXT: # %bb.26: # %cond.store29
	; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1			; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 1
	; RV64ZVE32F-NEXT: vmv.x.s a2, v11			; RV64ZVE32F-NEXT: vmv.x.s a2, v12
	; RV64ZVE32F-NEXT: add a2, a0, a2			; RV64ZVE32F-NEXT: add a2, a0, a2
	; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 15			; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 15
	; RV64ZVE32F-NEXT: vse8.v v12, (a2)			; RV64ZVE32F-NEXT: vse8.v v12, (a2)
	; RV64ZVE32F-NEXT: .LBB92_27: # %else30			; RV64ZVE32F-NEXT: .LBB92_27: # %else30
	; RV64ZVE32F-NEXT: lui a2, 16			; RV64ZVE32F-NEXT: lui a2, 16
	; RV64ZVE32F-NEXT: and a2, a1, a2			; RV64ZVE32F-NEXT: and a2, a1, a2
	; RV64ZVE32F-NEXT: beqz a2, .LBB92_29			; RV64ZVE32F-NEXT: beqz a2, .LBB92_29
	; RV64ZVE32F-NEXT: # %bb.28: # %cond.store31			; RV64ZVE32F-NEXT: # %bb.28: # %cond.store31
	; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, mu
	; RV64ZVE32F-NEXT: vmv.x.s a2, v10			; RV64ZVE32F-NEXT: vmv.x.s a2, v10
	; RV64ZVE32F-NEXT: add a2, a0, a2			; RV64ZVE32F-NEXT: add a2, a0, a2
	; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 16			; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 16
	; RV64ZVE32F-NEXT: vse8.v v12, (a2)			; RV64ZVE32F-NEXT: vse8.v v12, (a2)
	; RV64ZVE32F-NEXT: .LBB92_29: # %else32			; RV64ZVE32F-NEXT: .LBB92_29: # %else32
	; RV64ZVE32F-NEXT: lui a2, 32			; RV64ZVE32F-NEXT: lui a2, 32
	; RV64ZVE32F-NEXT: and a2, a1, a2			; RV64ZVE32F-NEXT: and a2, a1, a2
	; RV64ZVE32F-NEXT: beqz a2, .LBB92_31			; RV64ZVE32F-NEXT: beqz a2, .LBB92_31
	; RV64ZVE32F-NEXT: # %bb.30: # %cond.store33			; RV64ZVE32F-NEXT: # %bb.30: # %cond.store33
	; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1			; RV64ZVE32F-NEXT: vslidedown.vi v12, v10, 1
	; RV64ZVE32F-NEXT: vmv.x.s a2, v11			; RV64ZVE32F-NEXT: vmv.x.s a2, v12
	; RV64ZVE32F-NEXT: add a2, a0, a2			; RV64ZVE32F-NEXT: add a2, a0, a2
	; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 17			; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 17
	; RV64ZVE32F-NEXT: vse8.v v12, (a2)			; RV64ZVE32F-NEXT: vse8.v v12, (a2)
	; RV64ZVE32F-NEXT: .LBB92_31: # %else34			; RV64ZVE32F-NEXT: .LBB92_31: # %else34
	; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
	; RV64ZVE32F-NEXT: lui a2, 64			; RV64ZVE32F-NEXT: lui a2, 64
	; RV64ZVE32F-NEXT: and a2, a1, a2			; RV64ZVE32F-NEXT: and a2, a1, a2
	; RV64ZVE32F-NEXT: vslidedown.vi v12, v10, 2			; RV64ZVE32F-NEXT: vslidedown.vi v13, v10, 2
	; RV64ZVE32F-NEXT: beqz a2, .LBB92_33			; RV64ZVE32F-NEXT: beqz a2, .LBB92_33
	; RV64ZVE32F-NEXT: # %bb.32: # %cond.store35			; RV64ZVE32F-NEXT: # %bb.32: # %cond.store35
	; RV64ZVE32F-NEXT: vmv.x.s a2, v12			; RV64ZVE32F-NEXT: vmv.x.s a2, v13
	; RV64ZVE32F-NEXT: add a2, a0, a2			; RV64ZVE32F-NEXT: add a2, a0, a2
	; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 18			; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 18
	; RV64ZVE32F-NEXT: vse8.v v14, (a2)			; RV64ZVE32F-NEXT: vse8.v v14, (a2)
	; RV64ZVE32F-NEXT: .LBB92_33: # %else36			; RV64ZVE32F-NEXT: .LBB92_33: # %else36
	; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
	; RV64ZVE32F-NEXT: lui a2, 128			; RV64ZVE32F-NEXT: lui a2, 128
	; RV64ZVE32F-NEXT: and a2, a1, a2			; RV64ZVE32F-NEXT: and a2, a1, a2
	; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 4			; RV64ZVE32F-NEXT: vslidedown.vi v12, v10, 4
	; RV64ZVE32F-NEXT: beqz a2, .LBB92_35			; RV64ZVE32F-NEXT: beqz a2, .LBB92_35
	; RV64ZVE32F-NEXT: # %bb.34: # %cond.store37			; RV64ZVE32F-NEXT: # %bb.34: # %cond.store37
	; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 1			; RV64ZVE32F-NEXT: vslidedown.vi v13, v13, 1
	; RV64ZVE32F-NEXT: vmv.x.s a2, v12			; RV64ZVE32F-NEXT: vmv.x.s a2, v13
	; RV64ZVE32F-NEXT: add a2, a0, a2			; RV64ZVE32F-NEXT: add a2, a0, a2
	; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 19			; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 19
	; RV64ZVE32F-NEXT: vse8.v v12, (a2)			; RV64ZVE32F-NEXT: vse8.v v14, (a2)
	; RV64ZVE32F-NEXT: .LBB92_35: # %else38			; RV64ZVE32F-NEXT: .LBB92_35: # %else38
	; RV64ZVE32F-NEXT: lui a2, 256			; RV64ZVE32F-NEXT: lui a2, 256
	; RV64ZVE32F-NEXT: and a2, a1, a2			; RV64ZVE32F-NEXT: and a2, a1, a2
	; RV64ZVE32F-NEXT: beqz a2, .LBB92_37			; RV64ZVE32F-NEXT: beqz a2, .LBB92_37
	; RV64ZVE32F-NEXT: # %bb.36: # %cond.store39			; RV64ZVE32F-NEXT: # %bb.36: # %cond.store39
	; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, mu
	; RV64ZVE32F-NEXT: vmv.x.s a2, v11			; RV64ZVE32F-NEXT: vmv.x.s a2, v12
	; RV64ZVE32F-NEXT: add a2, a0, a2			; RV64ZVE32F-NEXT: add a2, a0, a2
	; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 20			; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 20
	; RV64ZVE32F-NEXT: vse8.v v12, (a2)			; RV64ZVE32F-NEXT: vse8.v v14, (a2)
	; RV64ZVE32F-NEXT: .LBB92_37: # %else40			; RV64ZVE32F-NEXT: .LBB92_37: # %else40
	; RV64ZVE32F-NEXT: lui a2, 512			; RV64ZVE32F-NEXT: lui a2, 512
	; RV64ZVE32F-NEXT: and a2, a1, a2			; RV64ZVE32F-NEXT: and a2, a1, a2
	; RV64ZVE32F-NEXT: beqz a2, .LBB92_39			; RV64ZVE32F-NEXT: beqz a2, .LBB92_39
	; RV64ZVE32F-NEXT: # %bb.38: # %cond.store41			; RV64ZVE32F-NEXT: # %bb.38: # %cond.store41
	; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v12, v11, 1			; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 1
	; RV64ZVE32F-NEXT: vmv.x.s a2, v12			; RV64ZVE32F-NEXT: vmv.x.s a2, v13
	; RV64ZVE32F-NEXT: add a2, a0, a2			; RV64ZVE32F-NEXT: add a2, a0, a2
	; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 21			; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 21
	; RV64ZVE32F-NEXT: vse8.v v12, (a2)			; RV64ZVE32F-NEXT: vse8.v v14, (a2)
	; RV64ZVE32F-NEXT: .LBB92_39: # %else42			; RV64ZVE32F-NEXT: .LBB92_39: # %else42
	; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 8			; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 8
	; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
	; RV64ZVE32F-NEXT: lui a2, 1024			; RV64ZVE32F-NEXT: lui a2, 1024
	; RV64ZVE32F-NEXT: and a2, a1, a2			; RV64ZVE32F-NEXT: and a2, a1, a2
	; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 2			; RV64ZVE32F-NEXT: vslidedown.vi v11, v12, 2
	; RV64ZVE32F-NEXT: beqz a2, .LBB92_41			; RV64ZVE32F-NEXT: beqz a2, .LBB92_41
	; RV64ZVE32F-NEXT: # %bb.40: # %cond.store43			; RV64ZVE32F-NEXT: # %bb.40: # %cond.store43
	; RV64ZVE32F-NEXT: vmv.x.s a2, v11			; RV64ZVE32F-NEXT: vmv.x.s a2, v11
	; RV64ZVE32F-NEXT: add a2, a0, a2			; RV64ZVE32F-NEXT: add a2, a0, a2
	; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, mu			; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, mu
	; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 22			; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 22
	; RV64ZVE32F-NEXT: vse8.v v12, (a2)			; RV64ZVE32F-NEXT: vse8.v v12, (a2)
	; RV64ZVE32F-NEXT: .LBB92_41: # %else44			; RV64ZVE32F-NEXT: .LBB92_41: # %else44
	▲ Show 20 Lines • Show All 161 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll

	Show First 20 Lines • Show All 741 Lines • ▼ Show 20 Lines
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	; CHECK-NEXT: li a1, 64			; CHECK-NEXT: li a1, 64
	; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
	; CHECK-NEXT: vle16.v v16, (a0)			; CHECK-NEXT: vle16.v v16, (a0)
	; CHECK-NEXT: li a0, 32			; CHECK-NEXT: li a0, 32
	; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu			; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
	; CHECK-NEXT: vslidedown.vx v8, v16, a0			; CHECK-NEXT: vslidedown.vx v8, v16, a0
	; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu			; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
	; CHECK-NEXT: vfmv.s.f v12, fa0			; CHECK-NEXT: vfmv.s.f v24, fa0
	; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
	; CHECK-NEXT: vfwredosum.vs v12, v16, v12			; CHECK-NEXT: vfwredosum.vs v16, v16, v24
	; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu			; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu
	; CHECK-NEXT: vfmv.f.s ft0, v12			; CHECK-NEXT: vfmv.f.s ft0, v16
	; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu			; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
	; CHECK-NEXT: vfmv.s.f v12, ft0			; CHECK-NEXT: vfmv.s.f v16, ft0
	; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
	; CHECK-NEXT: vfwredosum.vs v8, v8, v12			; CHECK-NEXT: vfwredosum.vs v8, v8, v16
	; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu			; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu
	; CHECK-NEXT: vfmv.f.s fa0, v8			; CHECK-NEXT: vfmv.f.s fa0, v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%v = load <64 x half>, <64 x half>* %x			%v = load <64 x half>, <64 x half>* %x
	%e = fpext <64 x half> %v to <64 x float>			%e = fpext <64 x half> %v to <64 x float>
	%red = call float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %e)			%red = call float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %e)
	ret float %red			ret float %red
	}			}
	▲ Show 20 Lines • Show All 423 Lines • ▼ Show 20 Lines
	; CHECK-LABEL: vreduce_ord_fwadd_v32f64:			; CHECK-LABEL: vreduce_ord_fwadd_v32f64:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	; CHECK-NEXT: li a1, 32			; CHECK-NEXT: li a1, 32
	; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
	; CHECK-NEXT: vle32.v v16, (a0)			; CHECK-NEXT: vle32.v v16, (a0)
	; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, mu			; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, mu
	; CHECK-NEXT: vslidedown.vi v8, v16, 16			; CHECK-NEXT: vslidedown.vi v8, v16, 16
	; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu			; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
	; CHECK-NEXT: vfmv.s.f v12, fa0			; CHECK-NEXT: vfmv.s.f v24, fa0
	; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu			; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
	; CHECK-NEXT: vfwredosum.vs v12, v16, v12			; CHECK-NEXT: vfwredosum.vs v16, v16, v24
	; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu			; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu
	; CHECK-NEXT: vfmv.f.s ft0, v12			; CHECK-NEXT: vfmv.f.s ft0, v16
	; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu			; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
	; CHECK-NEXT: vfmv.s.f v12, ft0			; CHECK-NEXT: vfmv.s.f v16, ft0
	; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu			; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
	; CHECK-NEXT: vfwredosum.vs v8, v8, v12			; CHECK-NEXT: vfwredosum.vs v8, v8, v16
	; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu			; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu
	; CHECK-NEXT: vfmv.f.s fa0, v8			; CHECK-NEXT: vfmv.f.s fa0, v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%v = load <32 x float>, <32 x float>* %x			%v = load <32 x float>, <32 x float>* %x
	%e = fpext <32 x float> %v to <32 x double>			%e = fpext <32 x float> %v to <32 x double>
	%red = call double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %e)			%red = call double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %e)
	ret double %red			ret double %red
	}			}
	▲ Show 20 Lines • Show All 624 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll

	Show First 20 Lines • Show All 1,590 Lines • ▼ Show 20 Lines
	; RV32-NEXT: .cfi_def_cfa_offset 16			; RV32-NEXT: .cfi_def_cfa_offset 16
	; RV32-NEXT: csrr a1, vlenb			; RV32-NEXT: csrr a1, vlenb
	; RV32-NEXT: slli a1, a1, 5			; RV32-NEXT: slli a1, a1, 5
	; RV32-NEXT: sub sp, sp, a1			; RV32-NEXT: sub sp, sp, a1
	; RV32-NEXT: addi a1, a0, 128			; RV32-NEXT: addi a1, a0, 128
	; RV32-NEXT: li a2, 32			; RV32-NEXT: li a2, 32
	; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu			; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu
	; RV32-NEXT: vle32.v v8, (a0)			; RV32-NEXT: vle32.v v8, (a0)
				; RV32-NEXT: addi a0, sp, 16
				; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
	; RV32-NEXT: vle32.v v16, (a1)			; RV32-NEXT: vle32.v v16, (a1)
	; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, mu			; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, mu
	; RV32-NEXT: vslidedown.vi v24, v8, 16			; RV32-NEXT: vslidedown.vi v24, v8, 16
	; RV32-NEXT: addi a0, sp, 16
	; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
	; RV32-NEXT: csrr a0, vlenb			; RV32-NEXT: csrr a0, vlenb
	; RV32-NEXT: li a1, 24			; RV32-NEXT: li a1, 24
	; RV32-NEXT: mul a0, a0, a1			; RV32-NEXT: mul a0, a0, a1
	; RV32-NEXT: add a0, sp, a0			; RV32-NEXT: add a0, sp, a0
	; RV32-NEXT: addi a0, a0, 16			; RV32-NEXT: addi a0, a0, 16
	; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill			; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
	; RV32-NEXT: vslidedown.vi v24, v16, 16			; RV32-NEXT: vslidedown.vi v24, v16, 16
	; RV32-NEXT: csrr a0, vlenb			; RV32-NEXT: csrr a0, vlenb
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	; RV64-NEXT: .cfi_def_cfa_offset 16			; RV64-NEXT: .cfi_def_cfa_offset 16
	; RV64-NEXT: csrr a1, vlenb			; RV64-NEXT: csrr a1, vlenb
	; RV64-NEXT: slli a1, a1, 5			; RV64-NEXT: slli a1, a1, 5
	; RV64-NEXT: sub sp, sp, a1			; RV64-NEXT: sub sp, sp, a1
	; RV64-NEXT: addi a1, a0, 128			; RV64-NEXT: addi a1, a0, 128
	; RV64-NEXT: li a2, 32			; RV64-NEXT: li a2, 32
	; RV64-NEXT: vsetvli zero, a2, e32, m8, ta, mu			; RV64-NEXT: vsetvli zero, a2, e32, m8, ta, mu
	; RV64-NEXT: vle32.v v8, (a0)			; RV64-NEXT: vle32.v v8, (a0)
				; RV64-NEXT: addi a0, sp, 16
				; RV64-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
	; RV64-NEXT: vle32.v v16, (a1)			; RV64-NEXT: vle32.v v16, (a1)
	; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, mu			; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, mu
	; RV64-NEXT: vslidedown.vi v24, v8, 16			; RV64-NEXT: vslidedown.vi v24, v8, 16
	; RV64-NEXT: addi a0, sp, 16
	; RV64-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
	; RV64-NEXT: csrr a0, vlenb			; RV64-NEXT: csrr a0, vlenb
	; RV64-NEXT: li a1, 24			; RV64-NEXT: li a1, 24
	; RV64-NEXT: mul a0, a0, a1			; RV64-NEXT: mul a0, a0, a1
	; RV64-NEXT: add a0, sp, a0			; RV64-NEXT: add a0, sp, a0
	; RV64-NEXT: addi a0, a0, 16			; RV64-NEXT: addi a0, a0, 16
	; RV64-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill			; RV64-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
	; RV64-NEXT: vslidedown.vi v24, v16, 16			; RV64-NEXT: vslidedown.vi v24, v16, 16
	; RV64-NEXT: csrr a0, vlenb			; RV64-NEXT: csrr a0, vlenb
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	; RV32-NEXT: .cfi_def_cfa_offset 16			; RV32-NEXT: .cfi_def_cfa_offset 16
	; RV32-NEXT: csrr a1, vlenb			; RV32-NEXT: csrr a1, vlenb
	; RV32-NEXT: slli a1, a1, 5			; RV32-NEXT: slli a1, a1, 5
	; RV32-NEXT: sub sp, sp, a1			; RV32-NEXT: sub sp, sp, a1
	; RV32-NEXT: addi a1, a0, 128			; RV32-NEXT: addi a1, a0, 128
	; RV32-NEXT: li a2, 32			; RV32-NEXT: li a2, 32
	; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu			; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu
	; RV32-NEXT: vle32.v v8, (a0)			; RV32-NEXT: vle32.v v8, (a0)
				; RV32-NEXT: addi a0, sp, 16
				; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
	; RV32-NEXT: vle32.v v16, (a1)			; RV32-NEXT: vle32.v v16, (a1)
	; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, mu			; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, mu
	; RV32-NEXT: vslidedown.vi v24, v8, 16			; RV32-NEXT: vslidedown.vi v24, v8, 16
	; RV32-NEXT: addi a0, sp, 16
	; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
	; RV32-NEXT: csrr a0, vlenb			; RV32-NEXT: csrr a0, vlenb
	; RV32-NEXT: li a1, 24			; RV32-NEXT: li a1, 24
	; RV32-NEXT: mul a0, a0, a1			; RV32-NEXT: mul a0, a0, a1
	; RV32-NEXT: add a0, sp, a0			; RV32-NEXT: add a0, sp, a0
	; RV32-NEXT: addi a0, a0, 16			; RV32-NEXT: addi a0, a0, 16
	; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill			; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
	; RV32-NEXT: vslidedown.vi v24, v16, 16			; RV32-NEXT: vslidedown.vi v24, v16, 16
	; RV32-NEXT: csrr a0, vlenb			; RV32-NEXT: csrr a0, vlenb
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	; RV64-NEXT: .cfi_def_cfa_offset 16			; RV64-NEXT: .cfi_def_cfa_offset 16
	; RV64-NEXT: csrr a1, vlenb			; RV64-NEXT: csrr a1, vlenb
	; RV64-NEXT: slli a1, a1, 5			; RV64-NEXT: slli a1, a1, 5
	; RV64-NEXT: sub sp, sp, a1			; RV64-NEXT: sub sp, sp, a1
	; RV64-NEXT: addi a1, a0, 128			; RV64-NEXT: addi a1, a0, 128
	; RV64-NEXT: li a2, 32			; RV64-NEXT: li a2, 32
	; RV64-NEXT: vsetvli zero, a2, e32, m8, ta, mu			; RV64-NEXT: vsetvli zero, a2, e32, m8, ta, mu
	; RV64-NEXT: vle32.v v8, (a0)			; RV64-NEXT: vle32.v v8, (a0)
				; RV64-NEXT: addi a0, sp, 16
				; RV64-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
	; RV64-NEXT: vle32.v v16, (a1)			; RV64-NEXT: vle32.v v16, (a1)
	; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, mu			; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, mu
	; RV64-NEXT: vslidedown.vi v24, v8, 16			; RV64-NEXT: vslidedown.vi v24, v8, 16
	; RV64-NEXT: addi a0, sp, 16
	; RV64-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
	; RV64-NEXT: csrr a0, vlenb			; RV64-NEXT: csrr a0, vlenb
	; RV64-NEXT: li a1, 24			; RV64-NEXT: li a1, 24
	; RV64-NEXT: mul a0, a0, a1			; RV64-NEXT: mul a0, a0, a1
	; RV64-NEXT: add a0, sp, a0			; RV64-NEXT: add a0, sp, a0
	; RV64-NEXT: addi a0, a0, 16			; RV64-NEXT: addi a0, a0, 16
	; RV64-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill			; RV64-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
	; RV64-NEXT: vslidedown.vi v24, v16, 16			; RV64-NEXT: vslidedown.vi v24, v16, 16
	; RV64-NEXT: csrr a0, vlenb			; RV64-NEXT: csrr a0, vlenb
	▲ Show 20 Lines • Show All 5,750 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll

	Show First 20 Lines • Show All 361 Lines • ▼ Show 20 Lines
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%v = call <vscale x 32 x half> @llvm.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 26)			%v = call <vscale x 32 x half> @llvm.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 26)
	ret <vscale x 32 x half> %v			ret <vscale x 32 x half> %v
	}			}

	define <vscale x 32 x half> @insert_nxv32f16_undef_nxv1f16_0(<vscale x 1 x half> %subvec) {			define <vscale x 32 x half> @insert_nxv32f16_undef_nxv1f16_0(<vscale x 1 x half> %subvec) {
	; CHECK-LABEL: insert_nxv32f16_undef_nxv1f16_0:			; CHECK-LABEL: insert_nxv32f16_undef_nxv1f16_0:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8m8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%v = call <vscale x 32 x half> @llvm.vector.insert.nxv1f16.nxv32f16(<vscale x 32 x half> undef, <vscale x 1 x half> %subvec, i64 0)			%v = call <vscale x 32 x half> @llvm.vector.insert.nxv1f16.nxv32f16(<vscale x 32 x half> undef, <vscale x 1 x half> %subvec, i64 0)
	ret <vscale x 32 x half> %v			ret <vscale x 32 x half> %v
	}			}

	define <vscale x 32 x half> @insert_nxv32f16_undef_nxv1f16_26(<vscale x 1 x half> %subvec) {			define <vscale x 32 x half> @insert_nxv32f16_undef_nxv1f16_26(<vscale x 1 x half> %subvec) {
	; CHECK-LABEL: insert_nxv32f16_undef_nxv1f16_26:			; CHECK-LABEL: insert_nxv32f16_undef_nxv1f16_26:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	; CHECK-NEXT: csrr a0, vlenb			; CHECK-NEXT: csrr a0, vlenb
	; CHECK-NEXT: srli a1, a0, 3			; CHECK-NEXT: srli a1, a0, 3
	; CHECK-NEXT: srli a0, a0, 2			; CHECK-NEXT: srli a0, a0, 2
	; CHECK-NEXT: add a1, a0, a1			; CHECK-NEXT: add a1, a0, a1
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu
	; CHECK-NEXT: vslideup.vx v14, v8, a0			; CHECK-NEXT: vslideup.vx v22, v8, a0
				; CHECK-NEXT: vmv8r.v v8, v16
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%v = call <vscale x 32 x half> @llvm.vector.insert.nxv1f16.nxv32f16(<vscale x 32 x half> undef, <vscale x 1 x half> %subvec, i64 26)			%v = call <vscale x 32 x half> @llvm.vector.insert.nxv1f16.nxv32f16(<vscale x 32 x half> undef, <vscale x 1 x half> %subvec, i64 26)
	ret <vscale x 32 x half> %v			ret <vscale x 32 x half> %v
	}			}

	define <vscale x 32 x i1> @insert_nxv32i1_nxv8i1_0(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv) {			define <vscale x 32 x i1> @insert_nxv32i1_nxv8i1_0(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv) {
	; CHECK-LABEL: insert_nxv32i1_nxv8i1_0:			; CHECK-LABEL: insert_nxv32i1_nxv8i1_0:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	▲ Show 20 Lines • Show All 123 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll

	Show All 40 Lines
	; SPILL-O2-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill			; SPILL-O2-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill
	; SPILL-O2-NEXT: #APP			; SPILL-O2-NEXT: #APP
	; SPILL-O2-NEXT: #NO_APP			; SPILL-O2-NEXT: #NO_APP
	; SPILL-O2-NEXT: addi a0, sp, 16			; SPILL-O2-NEXT: addi a0, sp, 16
	; SPILL-O2-NEXT: csrr a1, vlenb			; SPILL-O2-NEXT: csrr a1, vlenb
	; SPILL-O2-NEXT: vl1r.v v7, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl1r.v v7, (a0) # Unknown-size Folded Reload
	; SPILL-O2-NEXT: add a0, a0, a1			; SPILL-O2-NEXT: add a0, a0, a1
	; SPILL-O2-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
				; SPILL-O2-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; SPILL-O2-NEXT: csrr a0, vlenb			; SPILL-O2-NEXT: csrr a0, vlenb
	; SPILL-O2-NEXT: slli a0, a0, 1			; SPILL-O2-NEXT: slli a0, a0, 1
	; SPILL-O2-NEXT: add sp, sp, a0			; SPILL-O2-NEXT: add sp, sp, a0
	; SPILL-O2-NEXT: addi sp, sp, 16			; SPILL-O2-NEXT: addi sp, sp, 16
	; SPILL-O2-NEXT: ret			; SPILL-O2-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	call void asm sideeffect "",			call void asm sideeffect "",
	Show All 39 Lines
	; SPILL-O2-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill			; SPILL-O2-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill
	; SPILL-O2-NEXT: #APP			; SPILL-O2-NEXT: #APP
	; SPILL-O2-NEXT: #NO_APP			; SPILL-O2-NEXT: #NO_APP
	; SPILL-O2-NEXT: addi a0, sp, 16			; SPILL-O2-NEXT: addi a0, sp, 16
	; SPILL-O2-NEXT: csrr a1, vlenb			; SPILL-O2-NEXT: csrr a1, vlenb
	; SPILL-O2-NEXT: vl1r.v v7, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl1r.v v7, (a0) # Unknown-size Folded Reload
	; SPILL-O2-NEXT: add a0, a0, a1			; SPILL-O2-NEXT: add a0, a0, a1
	; SPILL-O2-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
				; SPILL-O2-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; SPILL-O2-NEXT: csrr a0, vlenb			; SPILL-O2-NEXT: csrr a0, vlenb
	; SPILL-O2-NEXT: slli a0, a0, 1			; SPILL-O2-NEXT: slli a0, a0, 1
	; SPILL-O2-NEXT: add sp, sp, a0			; SPILL-O2-NEXT: add sp, sp, a0
	; SPILL-O2-NEXT: addi sp, sp, 16			; SPILL-O2-NEXT: addi sp, sp, 16
	; SPILL-O2-NEXT: ret			; SPILL-O2-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	call void asm sideeffect "",			call void asm sideeffect "",
	▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
	; SPILL-O2-NEXT: #APP			; SPILL-O2-NEXT: #APP
	; SPILL-O2-NEXT: #NO_APP			; SPILL-O2-NEXT: #NO_APP
	; SPILL-O2-NEXT: addi a0, sp, 16			; SPILL-O2-NEXT: addi a0, sp, 16
	; SPILL-O2-NEXT: csrr a1, vlenb			; SPILL-O2-NEXT: csrr a1, vlenb
	; SPILL-O2-NEXT: slli a1, a1, 1			; SPILL-O2-NEXT: slli a1, a1, 1
	; SPILL-O2-NEXT: vl2r.v v6, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl2r.v v6, (a0) # Unknown-size Folded Reload
	; SPILL-O2-NEXT: add a0, a0, a1			; SPILL-O2-NEXT: add a0, a0, a1
	; SPILL-O2-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload
				; SPILL-O2-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; SPILL-O2-NEXT: csrr a0, vlenb			; SPILL-O2-NEXT: csrr a0, vlenb
	; SPILL-O2-NEXT: slli a0, a0, 2			; SPILL-O2-NEXT: slli a0, a0, 2
	; SPILL-O2-NEXT: add sp, sp, a0			; SPILL-O2-NEXT: add sp, sp, a0
	; SPILL-O2-NEXT: addi sp, sp, 16			; SPILL-O2-NEXT: addi sp, sp, 16
	; SPILL-O2-NEXT: ret			; SPILL-O2-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)
	call void asm sideeffect "",			call void asm sideeffect "",
	▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
	; SPILL-O2-NEXT: #APP			; SPILL-O2-NEXT: #APP
	; SPILL-O2-NEXT: #NO_APP			; SPILL-O2-NEXT: #NO_APP
	; SPILL-O2-NEXT: addi a0, sp, 16			; SPILL-O2-NEXT: addi a0, sp, 16
	; SPILL-O2-NEXT: csrr a1, vlenb			; SPILL-O2-NEXT: csrr a1, vlenb
	; SPILL-O2-NEXT: slli a1, a1, 2			; SPILL-O2-NEXT: slli a1, a1, 2
	; SPILL-O2-NEXT: vl4r.v v4, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl4r.v v4, (a0) # Unknown-size Folded Reload
	; SPILL-O2-NEXT: add a0, a0, a1			; SPILL-O2-NEXT: add a0, a0, a1
	; SPILL-O2-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload
				; SPILL-O2-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; SPILL-O2-NEXT: csrr a0, vlenb			; SPILL-O2-NEXT: csrr a0, vlenb
	; SPILL-O2-NEXT: slli a0, a0, 3			; SPILL-O2-NEXT: slli a0, a0, 3
	; SPILL-O2-NEXT: add sp, sp, a0			; SPILL-O2-NEXT: add sp, sp, a0
	; SPILL-O2-NEXT: addi sp, sp, 16			; SPILL-O2-NEXT: addi sp, sp, 16
	; SPILL-O2-NEXT: ret			; SPILL-O2-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i32 %vl)
	call void asm sideeffect "",			call void asm sideeffect "",
	▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
	; SPILL-O2-NEXT: addi a0, sp, 16			; SPILL-O2-NEXT: addi a0, sp, 16
	; SPILL-O2-NEXT: csrr a1, vlenb			; SPILL-O2-NEXT: csrr a1, vlenb
	; SPILL-O2-NEXT: slli a1, a1, 1			; SPILL-O2-NEXT: slli a1, a1, 1
	; SPILL-O2-NEXT: vl2r.v v6, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl2r.v v6, (a0) # Unknown-size Folded Reload
	; SPILL-O2-NEXT: add a0, a0, a1			; SPILL-O2-NEXT: add a0, a0, a1
	; SPILL-O2-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload
	; SPILL-O2-NEXT: add a0, a0, a1			; SPILL-O2-NEXT: add a0, a0, a1
	; SPILL-O2-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
				; SPILL-O2-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; SPILL-O2-NEXT: csrr a0, vlenb			; SPILL-O2-NEXT: csrr a0, vlenb
	; SPILL-O2-NEXT: li a1, 6			; SPILL-O2-NEXT: li a1, 6
	; SPILL-O2-NEXT: mul a0, a0, a1			; SPILL-O2-NEXT: mul a0, a0, a1
	; SPILL-O2-NEXT: add sp, sp, a0			; SPILL-O2-NEXT: add sp, sp, a0
	; SPILL-O2-NEXT: addi sp, sp, 16			; SPILL-O2-NEXT: addi sp, sp, 16
	; SPILL-O2-NEXT: ret			; SPILL-O2-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)
	Show All 11 Lines

llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll

	Show All 40 Lines
	; SPILL-O2-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill			; SPILL-O2-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill
	; SPILL-O2-NEXT: #APP			; SPILL-O2-NEXT: #APP
	; SPILL-O2-NEXT: #NO_APP			; SPILL-O2-NEXT: #NO_APP
	; SPILL-O2-NEXT: addi a0, sp, 16			; SPILL-O2-NEXT: addi a0, sp, 16
	; SPILL-O2-NEXT: csrr a1, vlenb			; SPILL-O2-NEXT: csrr a1, vlenb
	; SPILL-O2-NEXT: vl1r.v v7, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl1r.v v7, (a0) # Unknown-size Folded Reload
	; SPILL-O2-NEXT: add a0, a0, a1			; SPILL-O2-NEXT: add a0, a0, a1
	; SPILL-O2-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
				; SPILL-O2-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; SPILL-O2-NEXT: csrr a0, vlenb			; SPILL-O2-NEXT: csrr a0, vlenb
	; SPILL-O2-NEXT: slli a0, a0, 1			; SPILL-O2-NEXT: slli a0, a0, 1
	; SPILL-O2-NEXT: add sp, sp, a0			; SPILL-O2-NEXT: add sp, sp, a0
	; SPILL-O2-NEXT: addi sp, sp, 16			; SPILL-O2-NEXT: addi sp, sp, 16
	; SPILL-O2-NEXT: ret			; SPILL-O2-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	call void asm sideeffect "",			call void asm sideeffect "",
	Show All 39 Lines
	; SPILL-O2-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill			; SPILL-O2-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill
	; SPILL-O2-NEXT: #APP			; SPILL-O2-NEXT: #APP
	; SPILL-O2-NEXT: #NO_APP			; SPILL-O2-NEXT: #NO_APP
	; SPILL-O2-NEXT: addi a0, sp, 16			; SPILL-O2-NEXT: addi a0, sp, 16
	; SPILL-O2-NEXT: csrr a1, vlenb			; SPILL-O2-NEXT: csrr a1, vlenb
	; SPILL-O2-NEXT: vl1r.v v7, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl1r.v v7, (a0) # Unknown-size Folded Reload
	; SPILL-O2-NEXT: add a0, a0, a1			; SPILL-O2-NEXT: add a0, a0, a1
	; SPILL-O2-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
				; SPILL-O2-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; SPILL-O2-NEXT: csrr a0, vlenb			; SPILL-O2-NEXT: csrr a0, vlenb
	; SPILL-O2-NEXT: slli a0, a0, 1			; SPILL-O2-NEXT: slli a0, a0, 1
	; SPILL-O2-NEXT: add sp, sp, a0			; SPILL-O2-NEXT: add sp, sp, a0
	; SPILL-O2-NEXT: addi sp, sp, 16			; SPILL-O2-NEXT: addi sp, sp, 16
	; SPILL-O2-NEXT: ret			; SPILL-O2-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	call void asm sideeffect "",			call void asm sideeffect "",
	▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
	; SPILL-O2-NEXT: #APP			; SPILL-O2-NEXT: #APP
	; SPILL-O2-NEXT: #NO_APP			; SPILL-O2-NEXT: #NO_APP
	; SPILL-O2-NEXT: addi a0, sp, 16			; SPILL-O2-NEXT: addi a0, sp, 16
	; SPILL-O2-NEXT: csrr a1, vlenb			; SPILL-O2-NEXT: csrr a1, vlenb
	; SPILL-O2-NEXT: slli a1, a1, 1			; SPILL-O2-NEXT: slli a1, a1, 1
	; SPILL-O2-NEXT: vl2r.v v6, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl2r.v v6, (a0) # Unknown-size Folded Reload
	; SPILL-O2-NEXT: add a0, a0, a1			; SPILL-O2-NEXT: add a0, a0, a1
	; SPILL-O2-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload
				; SPILL-O2-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; SPILL-O2-NEXT: csrr a0, vlenb			; SPILL-O2-NEXT: csrr a0, vlenb
	; SPILL-O2-NEXT: slli a0, a0, 2			; SPILL-O2-NEXT: slli a0, a0, 2
	; SPILL-O2-NEXT: add sp, sp, a0			; SPILL-O2-NEXT: add sp, sp, a0
	; SPILL-O2-NEXT: addi sp, sp, 16			; SPILL-O2-NEXT: addi sp, sp, 16
	; SPILL-O2-NEXT: ret			; SPILL-O2-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)
	call void asm sideeffect "",			call void asm sideeffect "",
	▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
	; SPILL-O2-NEXT: #APP			; SPILL-O2-NEXT: #APP
	; SPILL-O2-NEXT: #NO_APP			; SPILL-O2-NEXT: #NO_APP
	; SPILL-O2-NEXT: addi a0, sp, 16			; SPILL-O2-NEXT: addi a0, sp, 16
	; SPILL-O2-NEXT: csrr a1, vlenb			; SPILL-O2-NEXT: csrr a1, vlenb
	; SPILL-O2-NEXT: slli a1, a1, 2			; SPILL-O2-NEXT: slli a1, a1, 2
	; SPILL-O2-NEXT: vl4r.v v4, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl4r.v v4, (a0) # Unknown-size Folded Reload
	; SPILL-O2-NEXT: add a0, a0, a1			; SPILL-O2-NEXT: add a0, a0, a1
	; SPILL-O2-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload
				; SPILL-O2-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; SPILL-O2-NEXT: csrr a0, vlenb			; SPILL-O2-NEXT: csrr a0, vlenb
	; SPILL-O2-NEXT: slli a0, a0, 3			; SPILL-O2-NEXT: slli a0, a0, 3
	; SPILL-O2-NEXT: add sp, sp, a0			; SPILL-O2-NEXT: add sp, sp, a0
	; SPILL-O2-NEXT: addi sp, sp, 16			; SPILL-O2-NEXT: addi sp, sp, 16
	; SPILL-O2-NEXT: ret			; SPILL-O2-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i64 %vl)
	call void asm sideeffect "",			call void asm sideeffect "",
	▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
	; SPILL-O2-NEXT: addi a0, sp, 16			; SPILL-O2-NEXT: addi a0, sp, 16
	; SPILL-O2-NEXT: csrr a1, vlenb			; SPILL-O2-NEXT: csrr a1, vlenb
	; SPILL-O2-NEXT: slli a1, a1, 1			; SPILL-O2-NEXT: slli a1, a1, 1
	; SPILL-O2-NEXT: vl2r.v v6, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl2r.v v6, (a0) # Unknown-size Folded Reload
	; SPILL-O2-NEXT: add a0, a0, a1			; SPILL-O2-NEXT: add a0, a0, a1
	; SPILL-O2-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload
	; SPILL-O2-NEXT: add a0, a0, a1			; SPILL-O2-NEXT: add a0, a0, a1
	; SPILL-O2-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload			; SPILL-O2-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
				; SPILL-O2-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; SPILL-O2-NEXT: csrr a0, vlenb			; SPILL-O2-NEXT: csrr a0, vlenb
	; SPILL-O2-NEXT: li a1, 6			; SPILL-O2-NEXT: li a1, 6
	; SPILL-O2-NEXT: mul a0, a0, a1			; SPILL-O2-NEXT: mul a0, a0, a1
	; SPILL-O2-NEXT: add sp, sp, a0			; SPILL-O2-NEXT: add sp, sp, a0
	; SPILL-O2-NEXT: addi sp, sp, 16			; SPILL-O2-NEXT: addi sp, sp, 16
	; SPILL-O2-NEXT: ret			; SPILL-O2-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)
	Show All 11 Lines

llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines	; CHECK-NEXT: ret
ret <vscale x 7 x float> %v		ret <vscale x 7 x float> %v
}		}

declare <vscale x 16 x float> @llvm.vp.fptrunc.nxv16f64.nxv16f32(<vscale x 16 x double>, <vscale x 16 x i1>, i32)		declare <vscale x 16 x float> @llvm.vp.fptrunc.nxv16f64.nxv16f32(<vscale x 16 x double>, <vscale x 16 x i1>, i32)

define <vscale x 16 x float> @vfptrunc_nxv16f32_nxv16f64(<vscale x 16 x double> %a, <vscale x 16 x i1> %m, i32 zeroext %vl) {		define <vscale x 16 x float> @vfptrunc_nxv16f32_nxv16f64(<vscale x 16 x double> %a, <vscale x 16 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vfptrunc_nxv16f32_nxv16f64:		; CHECK-LABEL: vfptrunc_nxv16f32_nxv16f64:
; CHECK: # %bb.0:		; CHECK: # %bb.0:
		; CHECK-NEXT: addi sp, sp, -16
		; CHECK-NEXT: .cfi_def_cfa_offset 16
		; CHECK-NEXT: csrr a1, vlenb
		; CHECK-NEXT: slli a1, a1, 3
		; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: vmv1r.v v24, v0		; CHECK-NEXT: vmv1r.v v24, v0
		; CHECK-NEXT: addi a1, sp, 16
		; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: li a2, 0		; CHECK-NEXT: li a2, 0
; CHECK-NEXT: csrr a1, vlenb		; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a4, a1, 3		; CHECK-NEXT: srli a4, a1, 3
; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, mu		; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, mu
; CHECK-NEXT: sub a3, a0, a1		; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vslidedown.vx v0, v0, a4		; CHECK-NEXT: vslidedown.vx v0, v0, a4
; CHECK-NEXT: bltu a0, a3, .LBB7_2		; CHECK-NEXT: bltu a0, a3, .LBB7_2
; CHECK-NEXT: # %bb.1:		; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a3		; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: .LBB7_2:		; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu		; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
; CHECK-NEXT: vfncvt.f.f.w v28, v16, v0.t		; CHECK-NEXT: vfncvt.f.f.w v12, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB7_4		; CHECK-NEXT: bltu a0, a1, .LBB7_4
; CHECK-NEXT: # %bb.3:		; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: mv a0, a1		; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB7_4:		; CHECK-NEXT: .LBB7_4:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu		; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v24		; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vfncvt.f.f.w v24, v8, v0.t		; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vmv8r.v v8, v24		; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
		; CHECK-NEXT: vfncvt.f.f.w v8, v16, v0.t
		; CHECK-NEXT: csrr a0, vlenb
		; CHECK-NEXT: slli a0, a0, 3
		; CHECK-NEXT: add sp, sp, a0
		; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret		; CHECK-NEXT: ret
%v = call <vscale x 16 x float> @llvm.vp.fptrunc.nxv16f64.nxv16f32(<vscale x 16 x double> %a, <vscale x 16 x i1> %m, i32 %vl)		%v = call <vscale x 16 x float> @llvm.vp.fptrunc.nxv16f64.nxv16f32(<vscale x 16 x double> %a, <vscale x 16 x i1> %m, i32 %vl)
ret <vscale x 16 x float> %v		ret <vscale x 16 x float> %v
}		}

declare <vscale x 32 x float> @llvm.vp.fptrunc.nxv32f64.nxv32f32(<vscale x 32 x double>, <vscale x 32 x i1>, i32)		declare <vscale x 32 x float> @llvm.vp.fptrunc.nxv32f64.nxv32f32(<vscale x 32 x double>, <vscale x 32 x i1>, i32)

define <vscale x 32 x float> @vfptrunc_nxv32f32_nxv32f64(<vscale x 32 x double> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {		define <vscale x 32 x float> @vfptrunc_nxv32f32_nxv32f64(<vscale x 32 x double> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
▲ Show 20 Lines • Show All 95 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll

This file has a very large number of changes (2,992 lines). Show File Contents

llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll

This file has a very large number of changes (4,238 lines). Show File Contents

llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \			; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \
	; RUN: -verify-machineinstrs < %s \| FileCheck %s			; RUN: -verify-machineinstrs < %s \| FileCheck %s

	declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16* , i32)			declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16* , i32)
	declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i32, i32)			declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i32, i32)

	define <vscale x 16 x i16> @test_vlseg2_nxv16i16(i16* %base, i32 %vl) {			define <vscale x 16 x i16> @test_vlseg2_nxv16i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv16i16:			; CHECK-LABEL: test_vlseg2_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vlseg2e16.v v4, (a0)			; CHECK-NEXT: vlseg2e16.v v4, (a0)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1			%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
	ret <vscale x 16 x i16> %1			ret <vscale x 16 x i16> %1
	}			}

	define <vscale x 16 x i16> @test_vlseg2_mask_nxv16i16(i16* %base, i32 %vl, <vscale x 16 x i1> %mask) {			define <vscale x 16 x i16> @test_vlseg2_mask_nxv16i16(i16* %base, i32 %vl, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv16i16:			; CHECK-LABEL: test_vlseg2_mask_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vlseg2e16.v v4, (a0)			; CHECK-NEXT: vlseg2e16.v v4, (a0)
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0			%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
	%2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.mask.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.mask.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1			%3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
	ret <vscale x 16 x i16> %3			ret <vscale x 16 x i16> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg2.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg2.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg2.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg2.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i8> @test_vlseg2_nxv1i8(i8* %base, i32 %vl) {			define <vscale x 1 x i8> @test_vlseg2_nxv1i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv1i8:			; CHECK-LABEL: test_vlseg2_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg2e8.v v7, (a0)			; CHECK-NEXT: vlseg2e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg2.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg2.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg2_mask_nxv1i8(i8* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlseg2_mask_nxv1i8(i8* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv1i8:			; CHECK-LABEL: test_vlseg2_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg2e8.v v7, (a0)			; CHECK-NEXT: vlseg2e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg2.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg2.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg2.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg2.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg3.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg3.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg3.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg3.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i8> @test_vlseg3_nxv1i8(i8* %base, i32 %vl) {			define <vscale x 1 x i8> @test_vlseg3_nxv1i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv1i8:			; CHECK-LABEL: test_vlseg3_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg3e8.v v7, (a0)			; CHECK-NEXT: vlseg3e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg3.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg3.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg3_mask_nxv1i8(i8* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlseg3_mask_nxv1i8(i8* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv1i8:			; CHECK-LABEL: test_vlseg3_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg3e8.v v7, (a0)			; CHECK-NEXT: vlseg3e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg3.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg3.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg3.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg3.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg4.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg4.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg4.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg4.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i8> @test_vlseg4_nxv1i8(i8* %base, i32 %vl) {			define <vscale x 1 x i8> @test_vlseg4_nxv1i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv1i8:			; CHECK-LABEL: test_vlseg4_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg4e8.v v7, (a0)			; CHECK-NEXT: vlseg4e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg4.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg4.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg4_mask_nxv1i8(i8* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlseg4_mask_nxv1i8(i8* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv1i8:			; CHECK-LABEL: test_vlseg4_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg4e8.v v7, (a0)			; CHECK-NEXT: vlseg4e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg4.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg4.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg4.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg4.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg5.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg5.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg5.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg5.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i8> @test_vlseg5_nxv1i8(i8* %base, i32 %vl) {			define <vscale x 1 x i8> @test_vlseg5_nxv1i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv1i8:			; CHECK-LABEL: test_vlseg5_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg5e8.v v7, (a0)			; CHECK-NEXT: vlseg5e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg5.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg5.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg5_mask_nxv1i8(i8* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlseg5_mask_nxv1i8(i8* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv1i8:			; CHECK-LABEL: test_vlseg5_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg5e8.v v7, (a0)			; CHECK-NEXT: vlseg5e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg5.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg5.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg5.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg5.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg6.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg6.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg6.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg6.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i8> @test_vlseg6_nxv1i8(i8* %base, i32 %vl) {			define <vscale x 1 x i8> @test_vlseg6_nxv1i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv1i8:			; CHECK-LABEL: test_vlseg6_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg6e8.v v7, (a0)			; CHECK-NEXT: vlseg6e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg6.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg6.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg6_mask_nxv1i8(i8* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlseg6_mask_nxv1i8(i8* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv1i8:			; CHECK-LABEL: test_vlseg6_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg6e8.v v7, (a0)			; CHECK-NEXT: vlseg6e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg6.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg6.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg6.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg6.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg7.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg7.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg7.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg7.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i8> @test_vlseg7_nxv1i8(i8* %base, i32 %vl) {			define <vscale x 1 x i8> @test_vlseg7_nxv1i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv1i8:			; CHECK-LABEL: test_vlseg7_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg7e8.v v7, (a0)			; CHECK-NEXT: vlseg7e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg7.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg7.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg7_mask_nxv1i8(i8* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlseg7_mask_nxv1i8(i8* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv1i8:			; CHECK-LABEL: test_vlseg7_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg7e8.v v7, (a0)			; CHECK-NEXT: vlseg7e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg7.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg7.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg7.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg7.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg8.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg8.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i8> @test_vlseg8_nxv1i8(i8* %base, i32 %vl) {			define <vscale x 1 x i8> @test_vlseg8_nxv1i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv1i8:			; CHECK-LABEL: test_vlseg8_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg8e8.v v7, (a0)			; CHECK-NEXT: vlseg8e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg8.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg8.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg8_mask_nxv1i8(i8* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlseg8_mask_nxv1i8(i8* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv1i8:			; CHECK-LABEL: test_vlseg8_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg8e8.v v7, (a0)			; CHECK-NEXT: vlseg8e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg8.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg8.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg8.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg8.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg2.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i32)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg2.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i32)
	declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg2.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32, i32)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg2.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32, i32)

	define <vscale x 16 x i8> @test_vlseg2_nxv16i8(i8* %base, i32 %vl) {			define <vscale x 16 x i8> @test_vlseg2_nxv16i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv16i8:			; CHECK-LABEL: test_vlseg2_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg2e8.v v6, (a0)			; CHECK-NEXT: vlseg2e8.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg2.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg2.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	define <vscale x 16 x i8> @test_vlseg2_mask_nxv16i8(i8* %base, i32 %vl, <vscale x 16 x i1> %mask) {			define <vscale x 16 x i8> @test_vlseg2_mask_nxv16i8(i8* %base, i32 %vl, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv16i8:			; CHECK-LABEL: test_vlseg2_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg2e8.v v6, (a0)			; CHECK-NEXT: vlseg2e8.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlseg2e8.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e8.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg2.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg2.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
	%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg2.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg2.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1			%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
	ret <vscale x 16 x i8> %3			ret <vscale x 16 x i8> %3
	}			}

	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg3.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i32)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg3.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i32)
	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg3.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32, i32)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg3.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32, i32)

	define <vscale x 16 x i8> @test_vlseg3_nxv16i8(i8* %base, i32 %vl) {			define <vscale x 16 x i8> @test_vlseg3_nxv16i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv16i8:			; CHECK-LABEL: test_vlseg3_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg3e8.v v6, (a0)			; CHECK-NEXT: vlseg3e8.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg3.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg3.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	define <vscale x 16 x i8> @test_vlseg3_mask_nxv16i8(i8* %base, i32 %vl, <vscale x 16 x i1> %mask) {			define <vscale x 16 x i8> @test_vlseg3_mask_nxv16i8(i8* %base, i32 %vl, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv16i8:			; CHECK-LABEL: test_vlseg3_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg3e8.v v6, (a0)			; CHECK-NEXT: vlseg3e8.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlseg3e8.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e8.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg3.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg3.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
	%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg3.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg3.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1			%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
	ret <vscale x 16 x i8> %3			ret <vscale x 16 x i8> %3
	}			}

	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg4.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i32)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg4.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i32)
	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg4.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32, i32)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg4.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32, i32)

	define <vscale x 16 x i8> @test_vlseg4_nxv16i8(i8* %base, i32 %vl) {			define <vscale x 16 x i8> @test_vlseg4_nxv16i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv16i8:			; CHECK-LABEL: test_vlseg4_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg4e8.v v6, (a0)			; CHECK-NEXT: vlseg4e8.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg4.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg4.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	define <vscale x 16 x i8> @test_vlseg4_mask_nxv16i8(i8* %base, i32 %vl, <vscale x 16 x i1> %mask) {			define <vscale x 16 x i8> @test_vlseg4_mask_nxv16i8(i8* %base, i32 %vl, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv16i8:			; CHECK-LABEL: test_vlseg4_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg4e8.v v6, (a0)			; CHECK-NEXT: vlseg4e8.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlseg4e8.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e8.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg4.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg4.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
	%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg4.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg4.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1			%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
	ret <vscale x 16 x i8> %3			ret <vscale x 16 x i8> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i32> @test_vlseg2_nxv2i32(i32* %base, i32 %vl) {			define <vscale x 2 x i32> @test_vlseg2_nxv2i32(i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv2i32:			; CHECK-LABEL: test_vlseg2_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg2e32.v v7, (a0)			; CHECK-NEXT: vlseg2e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg2_mask_nxv2i32(i32* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlseg2_mask_nxv2i32(i32* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv2i32:			; CHECK-LABEL: test_vlseg2_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg2e32.v v7, (a0)			; CHECK-NEXT: vlseg2e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg3.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg3.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg3.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg3.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i32> @test_vlseg3_nxv2i32(i32* %base, i32 %vl) {			define <vscale x 2 x i32> @test_vlseg3_nxv2i32(i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv2i32:			; CHECK-LABEL: test_vlseg3_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg3e32.v v7, (a0)			; CHECK-NEXT: vlseg3e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg3.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg3.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg3_mask_nxv2i32(i32* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlseg3_mask_nxv2i32(i32* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv2i32:			; CHECK-LABEL: test_vlseg3_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg3e32.v v7, (a0)			; CHECK-NEXT: vlseg3e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg3.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg3.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg3.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg3.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg4.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg4.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg4.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg4.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i32> @test_vlseg4_nxv2i32(i32* %base, i32 %vl) {			define <vscale x 2 x i32> @test_vlseg4_nxv2i32(i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv2i32:			; CHECK-LABEL: test_vlseg4_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg4e32.v v7, (a0)			; CHECK-NEXT: vlseg4e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg4.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg4.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg4_mask_nxv2i32(i32* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlseg4_mask_nxv2i32(i32* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv2i32:			; CHECK-LABEL: test_vlseg4_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg4e32.v v7, (a0)			; CHECK-NEXT: vlseg4e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg4.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg4.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg4.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg4.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg5.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg5.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg5.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg5.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i32> @test_vlseg5_nxv2i32(i32* %base, i32 %vl) {			define <vscale x 2 x i32> @test_vlseg5_nxv2i32(i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv2i32:			; CHECK-LABEL: test_vlseg5_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg5e32.v v7, (a0)			; CHECK-NEXT: vlseg5e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg5.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg5.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg5_mask_nxv2i32(i32* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlseg5_mask_nxv2i32(i32* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv2i32:			; CHECK-LABEL: test_vlseg5_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg5e32.v v7, (a0)			; CHECK-NEXT: vlseg5e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg5.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg5.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg5.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg5.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg6.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg6.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg6.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg6.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i32> @test_vlseg6_nxv2i32(i32* %base, i32 %vl) {			define <vscale x 2 x i32> @test_vlseg6_nxv2i32(i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv2i32:			; CHECK-LABEL: test_vlseg6_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg6e32.v v7, (a0)			; CHECK-NEXT: vlseg6e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg6.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg6.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg6_mask_nxv2i32(i32* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlseg6_mask_nxv2i32(i32* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv2i32:			; CHECK-LABEL: test_vlseg6_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg6e32.v v7, (a0)			; CHECK-NEXT: vlseg6e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg6.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg6.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg6.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg6.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg7.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg7.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg7.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg7.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i32> @test_vlseg7_nxv2i32(i32* %base, i32 %vl) {			define <vscale x 2 x i32> @test_vlseg7_nxv2i32(i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv2i32:			; CHECK-LABEL: test_vlseg7_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg7e32.v v7, (a0)			; CHECK-NEXT: vlseg7e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg7.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg7.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg7_mask_nxv2i32(i32* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlseg7_mask_nxv2i32(i32* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv2i32:			; CHECK-LABEL: test_vlseg7_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg7e32.v v7, (a0)			; CHECK-NEXT: vlseg7e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg7.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg7.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg7.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg7.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg8.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg8.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg8.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg8.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i32> @test_vlseg8_nxv2i32(i32* %base, i32 %vl) {			define <vscale x 2 x i32> @test_vlseg8_nxv2i32(i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv2i32:			; CHECK-LABEL: test_vlseg8_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg8e32.v v7, (a0)			; CHECK-NEXT: vlseg8e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg8.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg8.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg8_mask_nxv2i32(i32* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlseg8_mask_nxv2i32(i32* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv2i32:			; CHECK-LABEL: test_vlseg8_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg8e32.v v7, (a0)			; CHECK-NEXT: vlseg8e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg8.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg8.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg8.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg8.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg2.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg2.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg2.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg2.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i16> @test_vlseg2_nxv4i16(i16* %base, i32 %vl) {			define <vscale x 4 x i16> @test_vlseg2_nxv4i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv4i16:			; CHECK-LABEL: test_vlseg2_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg2.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg2.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg2_mask_nxv4i16(i16* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlseg2_mask_nxv4i16(i16* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv4i16:			; CHECK-LABEL: test_vlseg2_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg2.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg2.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg2.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg2.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg3.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg3.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg3.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg3.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i16> @test_vlseg3_nxv4i16(i16* %base, i32 %vl) {			define <vscale x 4 x i16> @test_vlseg3_nxv4i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv4i16:			; CHECK-LABEL: test_vlseg3_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg3.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg3.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg3_mask_nxv4i16(i16* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlseg3_mask_nxv4i16(i16* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv4i16:			; CHECK-LABEL: test_vlseg3_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg3.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg3.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg3.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg3.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg4.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg4.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg4.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg4.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i16> @test_vlseg4_nxv4i16(i16* %base, i32 %vl) {			define <vscale x 4 x i16> @test_vlseg4_nxv4i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv4i16:			; CHECK-LABEL: test_vlseg4_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg4.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg4.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg4_mask_nxv4i16(i16* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlseg4_mask_nxv4i16(i16* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv4i16:			; CHECK-LABEL: test_vlseg4_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg4.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg4.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg4.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg4.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg5.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg5.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg5.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg5.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i16> @test_vlseg5_nxv4i16(i16* %base, i32 %vl) {			define <vscale x 4 x i16> @test_vlseg5_nxv4i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv4i16:			; CHECK-LABEL: test_vlseg5_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg5.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg5.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg5_mask_nxv4i16(i16* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlseg5_mask_nxv4i16(i16* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv4i16:			; CHECK-LABEL: test_vlseg5_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg5.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg5.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg5.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg5.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg6.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg6.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg6.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg6.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i16> @test_vlseg6_nxv4i16(i16* %base, i32 %vl) {			define <vscale x 4 x i16> @test_vlseg6_nxv4i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv4i16:			; CHECK-LABEL: test_vlseg6_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg6.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg6.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg6_mask_nxv4i16(i16* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlseg6_mask_nxv4i16(i16* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv4i16:			; CHECK-LABEL: test_vlseg6_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg6.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg6.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg6.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg6.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg7.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg7.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg7.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg7.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i16> @test_vlseg7_nxv4i16(i16* %base, i32 %vl) {			define <vscale x 4 x i16> @test_vlseg7_nxv4i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv4i16:			; CHECK-LABEL: test_vlseg7_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg7.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg7.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg7_mask_nxv4i16(i16* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlseg7_mask_nxv4i16(i16* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv4i16:			; CHECK-LABEL: test_vlseg7_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg7.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg7.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg7.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg7.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg8.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg8.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg8.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg8.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i16> @test_vlseg8_nxv4i16(i16* %base, i32 %vl) {			define <vscale x 4 x i16> @test_vlseg8_nxv4i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv4i16:			; CHECK-LABEL: test_vlseg8_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg8.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg8.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg8_mask_nxv4i16(i16* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlseg8_mask_nxv4i16(i16* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv4i16:			; CHECK-LABEL: test_vlseg8_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg8.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg8.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg8.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg8.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i32> @test_vlseg2_nxv1i32(i32* %base, i32 %vl) {			define <vscale x 1 x i32> @test_vlseg2_nxv1i32(i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv1i32:			; CHECK-LABEL: test_vlseg2_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg2e32.v v7, (a0)			; CHECK-NEXT: vlseg2e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg2_mask_nxv1i32(i32* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlseg2_mask_nxv1i32(i32* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv1i32:			; CHECK-LABEL: test_vlseg2_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg2e32.v v7, (a0)			; CHECK-NEXT: vlseg2e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i32> @test_vlseg3_nxv1i32(i32* %base, i32 %vl) {			define <vscale x 1 x i32> @test_vlseg3_nxv1i32(i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv1i32:			; CHECK-LABEL: test_vlseg3_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg3e32.v v7, (a0)			; CHECK-NEXT: vlseg3e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg3_mask_nxv1i32(i32* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlseg3_mask_nxv1i32(i32* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv1i32:			; CHECK-LABEL: test_vlseg3_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg3e32.v v7, (a0)			; CHECK-NEXT: vlseg3e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i32> @test_vlseg4_nxv1i32(i32* %base, i32 %vl) {			define <vscale x 1 x i32> @test_vlseg4_nxv1i32(i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv1i32:			; CHECK-LABEL: test_vlseg4_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg4e32.v v7, (a0)			; CHECK-NEXT: vlseg4e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg4_mask_nxv1i32(i32* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlseg4_mask_nxv1i32(i32* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv1i32:			; CHECK-LABEL: test_vlseg4_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg4e32.v v7, (a0)			; CHECK-NEXT: vlseg4e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i32> @test_vlseg5_nxv1i32(i32* %base, i32 %vl) {			define <vscale x 1 x i32> @test_vlseg5_nxv1i32(i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv1i32:			; CHECK-LABEL: test_vlseg5_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg5e32.v v7, (a0)			; CHECK-NEXT: vlseg5e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg5_mask_nxv1i32(i32* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlseg5_mask_nxv1i32(i32* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv1i32:			; CHECK-LABEL: test_vlseg5_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg5e32.v v7, (a0)			; CHECK-NEXT: vlseg5e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i32> @test_vlseg6_nxv1i32(i32* %base, i32 %vl) {			define <vscale x 1 x i32> @test_vlseg6_nxv1i32(i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv1i32:			; CHECK-LABEL: test_vlseg6_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg6e32.v v7, (a0)			; CHECK-NEXT: vlseg6e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg6_mask_nxv1i32(i32* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlseg6_mask_nxv1i32(i32* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv1i32:			; CHECK-LABEL: test_vlseg6_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg6e32.v v7, (a0)			; CHECK-NEXT: vlseg6e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i32> @test_vlseg7_nxv1i32(i32* %base, i32 %vl) {			define <vscale x 1 x i32> @test_vlseg7_nxv1i32(i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv1i32:			; CHECK-LABEL: test_vlseg7_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg7e32.v v7, (a0)			; CHECK-NEXT: vlseg7e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg7_mask_nxv1i32(i32* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlseg7_mask_nxv1i32(i32* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv1i32:			; CHECK-LABEL: test_vlseg7_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg7e32.v v7, (a0)			; CHECK-NEXT: vlseg7e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i32> @test_vlseg8_nxv1i32(i32* %base, i32 %vl) {			define <vscale x 1 x i32> @test_vlseg8_nxv1i32(i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv1i32:			; CHECK-LABEL: test_vlseg8_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg8e32.v v7, (a0)			; CHECK-NEXT: vlseg8e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg8_mask_nxv1i32(i32* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlseg8_mask_nxv1i32(i32* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv1i32:			; CHECK-LABEL: test_vlseg8_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg8e32.v v7, (a0)			; CHECK-NEXT: vlseg8e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg2.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i32)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg2.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i32)
	declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg2.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg2.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i16> @test_vlseg2_nxv8i16(i16* %base, i32 %vl) {			define <vscale x 8 x i16> @test_vlseg2_nxv8i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv8i16:			; CHECK-LABEL: test_vlseg2_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg2e16.v v6, (a0)			; CHECK-NEXT: vlseg2e16.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg2.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg2.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	define <vscale x 8 x i16> @test_vlseg2_mask_nxv8i16(i16* %base, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i16> @test_vlseg2_mask_nxv8i16(i16* %base, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv8i16:			; CHECK-LABEL: test_vlseg2_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg2e16.v v6, (a0)			; CHECK-NEXT: vlseg2e16.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlseg2e16.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e16.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg2.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg2.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
	%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg2.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg2.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1			%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
	ret <vscale x 8 x i16> %3			ret <vscale x 8 x i16> %3
	}			}

	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg3.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i32)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg3.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i32)
	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg3.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg3.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i16> @test_vlseg3_nxv8i16(i16* %base, i32 %vl) {			define <vscale x 8 x i16> @test_vlseg3_nxv8i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv8i16:			; CHECK-LABEL: test_vlseg3_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg3e16.v v6, (a0)			; CHECK-NEXT: vlseg3e16.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg3.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg3.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	define <vscale x 8 x i16> @test_vlseg3_mask_nxv8i16(i16* %base, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i16> @test_vlseg3_mask_nxv8i16(i16* %base, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv8i16:			; CHECK-LABEL: test_vlseg3_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg3e16.v v6, (a0)			; CHECK-NEXT: vlseg3e16.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlseg3e16.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e16.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg3.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg3.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
	%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg3.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg3.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1			%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
	ret <vscale x 8 x i16> %3			ret <vscale x 8 x i16> %3
	}			}

	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg4.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i32)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg4.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i32)
	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg4.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg4.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i16> @test_vlseg4_nxv8i16(i16* %base, i32 %vl) {			define <vscale x 8 x i16> @test_vlseg4_nxv8i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv8i16:			; CHECK-LABEL: test_vlseg4_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg4e16.v v6, (a0)			; CHECK-NEXT: vlseg4e16.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg4.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg4.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	define <vscale x 8 x i16> @test_vlseg4_mask_nxv8i16(i16* %base, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i16> @test_vlseg4_mask_nxv8i16(i16* %base, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv8i16:			; CHECK-LABEL: test_vlseg4_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg4e16.v v6, (a0)			; CHECK-NEXT: vlseg4e16.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlseg4e16.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e16.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg4.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg4.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
	%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg4.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg4.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1			%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
	ret <vscale x 8 x i16> %3			ret <vscale x 8 x i16> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg2.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg2.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg2.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg2.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i8> @test_vlseg2_nxv8i8(i8* %base, i32 %vl) {			define <vscale x 8 x i8> @test_vlseg2_nxv8i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv8i8:			; CHECK-LABEL: test_vlseg2_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg2e8.v v7, (a0)			; CHECK-NEXT: vlseg2e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg2.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg2.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg2_mask_nxv8i8(i8* %base, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlseg2_mask_nxv8i8(i8* %base, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv8i8:			; CHECK-LABEL: test_vlseg2_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg2e8.v v7, (a0)			; CHECK-NEXT: vlseg2e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg2.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg2.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg2.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg2.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg3.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg3.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg3.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg3.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i8> @test_vlseg3_nxv8i8(i8* %base, i32 %vl) {			define <vscale x 8 x i8> @test_vlseg3_nxv8i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv8i8:			; CHECK-LABEL: test_vlseg3_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg3e8.v v7, (a0)			; CHECK-NEXT: vlseg3e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg3.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg3.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg3_mask_nxv8i8(i8* %base, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlseg3_mask_nxv8i8(i8* %base, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv8i8:			; CHECK-LABEL: test_vlseg3_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg3e8.v v7, (a0)			; CHECK-NEXT: vlseg3e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg3.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg3.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg3.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg3.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg4.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg4.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg4.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg4.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i8> @test_vlseg4_nxv8i8(i8* %base, i32 %vl) {			define <vscale x 8 x i8> @test_vlseg4_nxv8i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv8i8:			; CHECK-LABEL: test_vlseg4_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg4e8.v v7, (a0)			; CHECK-NEXT: vlseg4e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg4.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg4.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg4_mask_nxv8i8(i8* %base, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlseg4_mask_nxv8i8(i8* %base, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv8i8:			; CHECK-LABEL: test_vlseg4_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg4e8.v v7, (a0)			; CHECK-NEXT: vlseg4e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg4.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg4.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg4.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg4.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg5.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg5.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg5.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg5.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i8> @test_vlseg5_nxv8i8(i8* %base, i32 %vl) {			define <vscale x 8 x i8> @test_vlseg5_nxv8i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv8i8:			; CHECK-LABEL: test_vlseg5_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg5e8.v v7, (a0)			; CHECK-NEXT: vlseg5e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg5.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg5.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg5_mask_nxv8i8(i8* %base, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlseg5_mask_nxv8i8(i8* %base, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv8i8:			; CHECK-LABEL: test_vlseg5_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg5e8.v v7, (a0)			; CHECK-NEXT: vlseg5e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg5.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg5.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg5.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg5.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg6.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg6.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg6.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg6.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i8> @test_vlseg6_nxv8i8(i8* %base, i32 %vl) {			define <vscale x 8 x i8> @test_vlseg6_nxv8i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv8i8:			; CHECK-LABEL: test_vlseg6_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg6e8.v v7, (a0)			; CHECK-NEXT: vlseg6e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg6.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg6.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg6_mask_nxv8i8(i8* %base, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlseg6_mask_nxv8i8(i8* %base, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv8i8:			; CHECK-LABEL: test_vlseg6_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg6e8.v v7, (a0)			; CHECK-NEXT: vlseg6e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg6.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg6.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg6.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg6.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg7.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg7.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg7.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg7.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i8> @test_vlseg7_nxv8i8(i8* %base, i32 %vl) {			define <vscale x 8 x i8> @test_vlseg7_nxv8i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv8i8:			; CHECK-LABEL: test_vlseg7_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg7e8.v v7, (a0)			; CHECK-NEXT: vlseg7e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg7.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg7.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg7_mask_nxv8i8(i8* %base, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlseg7_mask_nxv8i8(i8* %base, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv8i8:			; CHECK-LABEL: test_vlseg7_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg7e8.v v7, (a0)			; CHECK-NEXT: vlseg7e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg7.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg7.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg7.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg7.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg8.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg8.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i8> @test_vlseg8_nxv8i8(i8* %base, i32 %vl) {			define <vscale x 8 x i8> @test_vlseg8_nxv8i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv8i8:			; CHECK-LABEL: test_vlseg8_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg8e8.v v7, (a0)			; CHECK-NEXT: vlseg8e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg8.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg8.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg8_mask_nxv8i8(i8* %base, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlseg8_mask_nxv8i8(i8* %base, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv8i8:			; CHECK-LABEL: test_vlseg8_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg8e8.v v7, (a0)			; CHECK-NEXT: vlseg8e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg8.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg8.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg8.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg8.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32* , i32)			declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32* , i32)
	declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i32> @test_vlseg2_nxv8i32(i32* %base, i32 %vl) {			define <vscale x 8 x i32> @test_vlseg2_nxv8i32(i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv8i32:			; CHECK-LABEL: test_vlseg2_nxv8i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vlseg2e32.v v4, (a0)			; CHECK-NEXT: vlseg2e32.v v4, (a0)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1			%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
	ret <vscale x 8 x i32> %1			ret <vscale x 8 x i32> %1
	}			}

	define <vscale x 8 x i32> @test_vlseg2_mask_nxv8i32(i32* %base, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i32> @test_vlseg2_mask_nxv8i32(i32* %base, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv8i32:			; CHECK-LABEL: test_vlseg2_mask_nxv8i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vlseg2e32.v v4, (a0)			; CHECK-NEXT: vlseg2e32.v v4, (a0)
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlseg2e32.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e32.v v4, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0			%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
	%2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.mask.nxv8i32(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.mask.nxv8i32(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1			%3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
	ret <vscale x 8 x i32> %3			ret <vscale x 8 x i32> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg2.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg2.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg2.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg2.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i8> @test_vlseg2_nxv4i8(i8* %base, i32 %vl) {			define <vscale x 4 x i8> @test_vlseg2_nxv4i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv4i8:			; CHECK-LABEL: test_vlseg2_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg2e8.v v7, (a0)			; CHECK-NEXT: vlseg2e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg2.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg2.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg2_mask_nxv4i8(i8* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlseg2_mask_nxv4i8(i8* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv4i8:			; CHECK-LABEL: test_vlseg2_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg2e8.v v7, (a0)			; CHECK-NEXT: vlseg2e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg2.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg2.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg2.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg2.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg3.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg3.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg3.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg3.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i8> @test_vlseg3_nxv4i8(i8* %base, i32 %vl) {			define <vscale x 4 x i8> @test_vlseg3_nxv4i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv4i8:			; CHECK-LABEL: test_vlseg3_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg3e8.v v7, (a0)			; CHECK-NEXT: vlseg3e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg3.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg3.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg3_mask_nxv4i8(i8* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlseg3_mask_nxv4i8(i8* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv4i8:			; CHECK-LABEL: test_vlseg3_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg3e8.v v7, (a0)			; CHECK-NEXT: vlseg3e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg3.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg3.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg3.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg3.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg4.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg4.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg4.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg4.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i8> @test_vlseg4_nxv4i8(i8* %base, i32 %vl) {			define <vscale x 4 x i8> @test_vlseg4_nxv4i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv4i8:			; CHECK-LABEL: test_vlseg4_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg4e8.v v7, (a0)			; CHECK-NEXT: vlseg4e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg4.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg4.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg4_mask_nxv4i8(i8* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlseg4_mask_nxv4i8(i8* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv4i8:			; CHECK-LABEL: test_vlseg4_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg4e8.v v7, (a0)			; CHECK-NEXT: vlseg4e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg4.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg4.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg4.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg4.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg5.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg5.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg5.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg5.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i8> @test_vlseg5_nxv4i8(i8* %base, i32 %vl) {			define <vscale x 4 x i8> @test_vlseg5_nxv4i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv4i8:			; CHECK-LABEL: test_vlseg5_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg5e8.v v7, (a0)			; CHECK-NEXT: vlseg5e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg5.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg5.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg5_mask_nxv4i8(i8* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlseg5_mask_nxv4i8(i8* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv4i8:			; CHECK-LABEL: test_vlseg5_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg5e8.v v7, (a0)			; CHECK-NEXT: vlseg5e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg5.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg5.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg5.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg5.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg6.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg6.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg6.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg6.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i8> @test_vlseg6_nxv4i8(i8* %base, i32 %vl) {			define <vscale x 4 x i8> @test_vlseg6_nxv4i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv4i8:			; CHECK-LABEL: test_vlseg6_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg6e8.v v7, (a0)			; CHECK-NEXT: vlseg6e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg6.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg6.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg6_mask_nxv4i8(i8* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlseg6_mask_nxv4i8(i8* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv4i8:			; CHECK-LABEL: test_vlseg6_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg6e8.v v7, (a0)			; CHECK-NEXT: vlseg6e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg6.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg6.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg6.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg6.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg7.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg7.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg7.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg7.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i8> @test_vlseg7_nxv4i8(i8* %base, i32 %vl) {			define <vscale x 4 x i8> @test_vlseg7_nxv4i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv4i8:			; CHECK-LABEL: test_vlseg7_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg7e8.v v7, (a0)			; CHECK-NEXT: vlseg7e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg7.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg7.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg7_mask_nxv4i8(i8* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlseg7_mask_nxv4i8(i8* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv4i8:			; CHECK-LABEL: test_vlseg7_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg7e8.v v7, (a0)			; CHECK-NEXT: vlseg7e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg7.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg7.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg7.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg7.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg8.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg8.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i8> @test_vlseg8_nxv4i8(i8* %base, i32 %vl) {			define <vscale x 4 x i8> @test_vlseg8_nxv4i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv4i8:			; CHECK-LABEL: test_vlseg8_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg8e8.v v7, (a0)			; CHECK-NEXT: vlseg8e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg8.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg8.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg8_mask_nxv4i8(i8* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlseg8_mask_nxv4i8(i8* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv4i8:			; CHECK-LABEL: test_vlseg8_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg8e8.v v7, (a0)			; CHECK-NEXT: vlseg8e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg8.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg8.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg8.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg8.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg2.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg2.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg2.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg2.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i16> @test_vlseg2_nxv1i16(i16* %base, i32 %vl) {			define <vscale x 1 x i16> @test_vlseg2_nxv1i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv1i16:			; CHECK-LABEL: test_vlseg2_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg2.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg2.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg2_mask_nxv1i16(i16* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlseg2_mask_nxv1i16(i16* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv1i16:			; CHECK-LABEL: test_vlseg2_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg2.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg2.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg2.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg2.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg3.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg3.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg3.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg3.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i16> @test_vlseg3_nxv1i16(i16* %base, i32 %vl) {			define <vscale x 1 x i16> @test_vlseg3_nxv1i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv1i16:			; CHECK-LABEL: test_vlseg3_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg3.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg3.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg3_mask_nxv1i16(i16* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlseg3_mask_nxv1i16(i16* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv1i16:			; CHECK-LABEL: test_vlseg3_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg3.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg3.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg3.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg3.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg4.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg4.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg4.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg4.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i16> @test_vlseg4_nxv1i16(i16* %base, i32 %vl) {			define <vscale x 1 x i16> @test_vlseg4_nxv1i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv1i16:			; CHECK-LABEL: test_vlseg4_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg4.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg4.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg4_mask_nxv1i16(i16* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlseg4_mask_nxv1i16(i16* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv1i16:			; CHECK-LABEL: test_vlseg4_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg4.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg4.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg4.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg4.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg5.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg5.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg5.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg5.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i16> @test_vlseg5_nxv1i16(i16* %base, i32 %vl) {			define <vscale x 1 x i16> @test_vlseg5_nxv1i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv1i16:			; CHECK-LABEL: test_vlseg5_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg5.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg5.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg5_mask_nxv1i16(i16* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlseg5_mask_nxv1i16(i16* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv1i16:			; CHECK-LABEL: test_vlseg5_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg5.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg5.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg5.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg5.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg6.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg6.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg6.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg6.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i16> @test_vlseg6_nxv1i16(i16* %base, i32 %vl) {			define <vscale x 1 x i16> @test_vlseg6_nxv1i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv1i16:			; CHECK-LABEL: test_vlseg6_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg6.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg6.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg6_mask_nxv1i16(i16* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlseg6_mask_nxv1i16(i16* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv1i16:			; CHECK-LABEL: test_vlseg6_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg6.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg6.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg6.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg6.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg7.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg7.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg7.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg7.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i16> @test_vlseg7_nxv1i16(i16* %base, i32 %vl) {			define <vscale x 1 x i16> @test_vlseg7_nxv1i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv1i16:			; CHECK-LABEL: test_vlseg7_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg7.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg7.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg7_mask_nxv1i16(i16* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlseg7_mask_nxv1i16(i16* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv1i16:			; CHECK-LABEL: test_vlseg7_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg7.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg7.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg7.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg7.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg8.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg8.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg8.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg8.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i16> @test_vlseg8_nxv1i16(i16* %base, i32 %vl) {			define <vscale x 1 x i16> @test_vlseg8_nxv1i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv1i16:			; CHECK-LABEL: test_vlseg8_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg8.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg8.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg8_mask_nxv1i16(i16* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlseg8_mask_nxv1i16(i16* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv1i16:			; CHECK-LABEL: test_vlseg8_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg8.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg8.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg8.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg8.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlseg2.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8* , i32)			declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlseg2.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8* , i32)
	declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlseg2.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i1>, i32, i32)			declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlseg2.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i1>, i32, i32)

	define <vscale x 32 x i8> @test_vlseg2_nxv32i8(i8* %base, i32 %vl) {			define <vscale x 32 x i8> @test_vlseg2_nxv32i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv32i8:			; CHECK-LABEL: test_vlseg2_nxv32i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
	; CHECK-NEXT: vlseg2e8.v v4, (a0)			; CHECK-NEXT: vlseg2e8.v v4, (a0)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlseg2.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlseg2.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1			%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
	ret <vscale x 32 x i8> %1			ret <vscale x 32 x i8> %1
	}			}

	define <vscale x 32 x i8> @test_vlseg2_mask_nxv32i8(i8* %base, i32 %vl, <vscale x 32 x i1> %mask) {			define <vscale x 32 x i8> @test_vlseg2_mask_nxv32i8(i8* %base, i32 %vl, <vscale x 32 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv32i8:			; CHECK-LABEL: test_vlseg2_mask_nxv32i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
	; CHECK-NEXT: vlseg2e8.v v4, (a0)			; CHECK-NEXT: vlseg2e8.v v4, (a0)
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlseg2e8.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e8.v v4, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlseg2.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlseg2.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0			%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
	%2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlseg2.mask.nxv32i8(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 32 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlseg2.mask.nxv32i8(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 32 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1			%3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
	ret <vscale x 32 x i8> %3			ret <vscale x 32 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg2.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg2.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg2.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg2.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i8> @test_vlseg2_nxv2i8(i8* %base, i32 %vl) {			define <vscale x 2 x i8> @test_vlseg2_nxv2i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv2i8:			; CHECK-LABEL: test_vlseg2_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg2e8.v v7, (a0)			; CHECK-NEXT: vlseg2e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg2.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg2.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg2_mask_nxv2i8(i8* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlseg2_mask_nxv2i8(i8* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv2i8:			; CHECK-LABEL: test_vlseg2_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg2e8.v v7, (a0)			; CHECK-NEXT: vlseg2e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg2.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg2.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg2.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg2.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg3.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg3.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg3.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg3.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i8> @test_vlseg3_nxv2i8(i8* %base, i32 %vl) {			define <vscale x 2 x i8> @test_vlseg3_nxv2i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv2i8:			; CHECK-LABEL: test_vlseg3_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg3e8.v v7, (a0)			; CHECK-NEXT: vlseg3e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg3.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg3.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg3_mask_nxv2i8(i8* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlseg3_mask_nxv2i8(i8* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv2i8:			; CHECK-LABEL: test_vlseg3_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg3e8.v v7, (a0)			; CHECK-NEXT: vlseg3e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg3.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg3.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg3.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg3.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg4.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg4.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg4.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg4.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i8> @test_vlseg4_nxv2i8(i8* %base, i32 %vl) {			define <vscale x 2 x i8> @test_vlseg4_nxv2i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv2i8:			; CHECK-LABEL: test_vlseg4_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg4e8.v v7, (a0)			; CHECK-NEXT: vlseg4e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg4.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg4.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg4_mask_nxv2i8(i8* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlseg4_mask_nxv2i8(i8* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv2i8:			; CHECK-LABEL: test_vlseg4_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg4e8.v v7, (a0)			; CHECK-NEXT: vlseg4e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg4.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg4.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg4.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg4.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg5.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg5.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg5.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg5.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i8> @test_vlseg5_nxv2i8(i8* %base, i32 %vl) {			define <vscale x 2 x i8> @test_vlseg5_nxv2i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv2i8:			; CHECK-LABEL: test_vlseg5_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg5e8.v v7, (a0)			; CHECK-NEXT: vlseg5e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg5.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg5.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg5_mask_nxv2i8(i8* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlseg5_mask_nxv2i8(i8* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv2i8:			; CHECK-LABEL: test_vlseg5_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg5e8.v v7, (a0)			; CHECK-NEXT: vlseg5e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg5.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg5.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg5.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg5.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg6.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg6.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg6.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg6.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i8> @test_vlseg6_nxv2i8(i8* %base, i32 %vl) {			define <vscale x 2 x i8> @test_vlseg6_nxv2i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv2i8:			; CHECK-LABEL: test_vlseg6_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg6e8.v v7, (a0)			; CHECK-NEXT: vlseg6e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg6.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg6.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg6_mask_nxv2i8(i8* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlseg6_mask_nxv2i8(i8* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv2i8:			; CHECK-LABEL: test_vlseg6_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg6e8.v v7, (a0)			; CHECK-NEXT: vlseg6e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg6.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg6.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg6.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg6.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg7.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg7.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg7.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg7.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i8> @test_vlseg7_nxv2i8(i8* %base, i32 %vl) {			define <vscale x 2 x i8> @test_vlseg7_nxv2i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv2i8:			; CHECK-LABEL: test_vlseg7_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg7e8.v v7, (a0)			; CHECK-NEXT: vlseg7e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg7.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg7.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg7_mask_nxv2i8(i8* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlseg7_mask_nxv2i8(i8* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv2i8:			; CHECK-LABEL: test_vlseg7_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg7e8.v v7, (a0)			; CHECK-NEXT: vlseg7e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg7.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg7.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg7.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg7.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg8.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg8.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i8> @test_vlseg8_nxv2i8(i8* %base, i32 %vl) {			define <vscale x 2 x i8> @test_vlseg8_nxv2i8(i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv2i8:			; CHECK-LABEL: test_vlseg8_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg8e8.v v7, (a0)			; CHECK-NEXT: vlseg8e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg8.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg8.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg8_mask_nxv2i8(i8* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlseg8_mask_nxv2i8(i8* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv2i8:			; CHECK-LABEL: test_vlseg8_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg8e8.v v7, (a0)			; CHECK-NEXT: vlseg8e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg8.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg8.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg8.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg8.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg2.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg2.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg2.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg2.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i16> @test_vlseg2_nxv2i16(i16* %base, i32 %vl) {			define <vscale x 2 x i16> @test_vlseg2_nxv2i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv2i16:			; CHECK-LABEL: test_vlseg2_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg2.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg2.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg2_mask_nxv2i16(i16* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlseg2_mask_nxv2i16(i16* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv2i16:			; CHECK-LABEL: test_vlseg2_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg2.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg2.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg2.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg2.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg3.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg3.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg3.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg3.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i16> @test_vlseg3_nxv2i16(i16* %base, i32 %vl) {			define <vscale x 2 x i16> @test_vlseg3_nxv2i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv2i16:			; CHECK-LABEL: test_vlseg3_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg3.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg3.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg3_mask_nxv2i16(i16* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlseg3_mask_nxv2i16(i16* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv2i16:			; CHECK-LABEL: test_vlseg3_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg3.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg3.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg3.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg3.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg4.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg4.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg4.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg4.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i16> @test_vlseg4_nxv2i16(i16* %base, i32 %vl) {			define <vscale x 2 x i16> @test_vlseg4_nxv2i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv2i16:			; CHECK-LABEL: test_vlseg4_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg4.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg4.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg4_mask_nxv2i16(i16* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlseg4_mask_nxv2i16(i16* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv2i16:			; CHECK-LABEL: test_vlseg4_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg4.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg4.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg4.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg4.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg5.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg5.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg5.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg5.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i16> @test_vlseg5_nxv2i16(i16* %base, i32 %vl) {			define <vscale x 2 x i16> @test_vlseg5_nxv2i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv2i16:			; CHECK-LABEL: test_vlseg5_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg5.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg5.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg5_mask_nxv2i16(i16* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlseg5_mask_nxv2i16(i16* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv2i16:			; CHECK-LABEL: test_vlseg5_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg5.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg5.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg5.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg5.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg6.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg6.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg6.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg6.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i16> @test_vlseg6_nxv2i16(i16* %base, i32 %vl) {			define <vscale x 2 x i16> @test_vlseg6_nxv2i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv2i16:			; CHECK-LABEL: test_vlseg6_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg6.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg6.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg6_mask_nxv2i16(i16* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlseg6_mask_nxv2i16(i16* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv2i16:			; CHECK-LABEL: test_vlseg6_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg6.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg6.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg6.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg6.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg7.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg7.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg7.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg7.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i16> @test_vlseg7_nxv2i16(i16* %base, i32 %vl) {			define <vscale x 2 x i16> @test_vlseg7_nxv2i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv2i16:			; CHECK-LABEL: test_vlseg7_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg7.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg7.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg7_mask_nxv2i16(i16* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlseg7_mask_nxv2i16(i16* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv2i16:			; CHECK-LABEL: test_vlseg7_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg7.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg7.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg7.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg7.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg8.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg8.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg8.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg8.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i16> @test_vlseg8_nxv2i16(i16* %base, i32 %vl) {			define <vscale x 2 x i16> @test_vlseg8_nxv2i16(i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv2i16:			; CHECK-LABEL: test_vlseg8_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg8.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg8.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg8_mask_nxv2i16(i16* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlseg8_mask_nxv2i16(i16* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv2i16:			; CHECK-LABEL: test_vlseg8_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg8.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg8.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg8.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg8.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i32)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i32)
	declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i32> @test_vlseg2_nxv4i32(i32* %base, i32 %vl) {			define <vscale x 4 x i32> @test_vlseg2_nxv4i32(i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv4i32:			; CHECK-LABEL: test_vlseg2_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg2e32.v v6, (a0)			; CHECK-NEXT: vlseg2e32.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	define <vscale x 4 x i32> @test_vlseg2_mask_nxv4i32(i32* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i32> @test_vlseg2_mask_nxv4i32(i32* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv4i32:			; CHECK-LABEL: test_vlseg2_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg2e32.v v6, (a0)			; CHECK-NEXT: vlseg2e32.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlseg2e32.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e32.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
	%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1			%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
	ret <vscale x 4 x i32> %3			ret <vscale x 4 x i32> %3
	}			}

	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i32)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i32)
	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i32> @test_vlseg3_nxv4i32(i32* %base, i32 %vl) {			define <vscale x 4 x i32> @test_vlseg3_nxv4i32(i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv4i32:			; CHECK-LABEL: test_vlseg3_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg3e32.v v6, (a0)			; CHECK-NEXT: vlseg3e32.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	define <vscale x 4 x i32> @test_vlseg3_mask_nxv4i32(i32* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i32> @test_vlseg3_mask_nxv4i32(i32* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv4i32:			; CHECK-LABEL: test_vlseg3_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg3e32.v v6, (a0)			; CHECK-NEXT: vlseg3e32.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlseg3e32.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e32.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
	%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1			%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
	ret <vscale x 4 x i32> %3			ret <vscale x 4 x i32> %3
	}			}

	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg4.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i32)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg4.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i32)
	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg4.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg4.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i32> @test_vlseg4_nxv4i32(i32* %base, i32 %vl) {			define <vscale x 4 x i32> @test_vlseg4_nxv4i32(i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv4i32:			; CHECK-LABEL: test_vlseg4_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg4e32.v v6, (a0)			; CHECK-NEXT: vlseg4e32.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg4.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg4.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	define <vscale x 4 x i32> @test_vlseg4_mask_nxv4i32(i32* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i32> @test_vlseg4_mask_nxv4i32(i32* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv4i32:			; CHECK-LABEL: test_vlseg4_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg4e32.v v6, (a0)			; CHECK-NEXT: vlseg4e32.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlseg4e32.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e32.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg4.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg4.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
	%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg4.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg4.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1			%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
	ret <vscale x 4 x i32> %3			ret <vscale x 4 x i32> %3
	}			}

	declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlseg2.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half* , i32)			declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlseg2.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half* , i32)
	declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlseg2.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i1>, i32, i32)			declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlseg2.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i1>, i32, i32)

	define <vscale x 16 x half> @test_vlseg2_nxv16f16(half* %base, i32 %vl) {			define <vscale x 16 x half> @test_vlseg2_nxv16f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv16f16:			; CHECK-LABEL: test_vlseg2_nxv16f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vlseg2e16.v v4, (a0)			; CHECK-NEXT: vlseg2e16.v v4, (a0)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlseg2.nxv16f16(<vscale x 16 x half> undef, <vscale x 16 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlseg2.nxv16f16(<vscale x 16 x half> undef, <vscale x 16 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1			%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
	ret <vscale x 16 x half> %1			ret <vscale x 16 x half> %1
	}			}

	define <vscale x 16 x half> @test_vlseg2_mask_nxv16f16(half* %base, i32 %vl, <vscale x 16 x i1> %mask) {			define <vscale x 16 x half> @test_vlseg2_mask_nxv16f16(half* %base, i32 %vl, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv16f16:			; CHECK-LABEL: test_vlseg2_mask_nxv16f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vlseg2e16.v v4, (a0)			; CHECK-NEXT: vlseg2e16.v v4, (a0)
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlseg2.nxv16f16(<vscale x 16 x half> undef, <vscale x 16 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlseg2.nxv16f16(<vscale x 16 x half> undef, <vscale x 16 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0			%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
	%2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlseg2.mask.nxv16f16(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlseg2.mask.nxv16f16(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1			%3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
	ret <vscale x 16 x half> %3			ret <vscale x 16 x half> %3
	}			}

	declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlseg2.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double* , i32)			declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlseg2.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double* , i32)
	declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlseg2.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlseg2.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x double> @test_vlseg2_nxv4f64(double* %base, i32 %vl) {			define <vscale x 4 x double> @test_vlseg2_nxv4f64(double* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv4f64:			; CHECK-LABEL: test_vlseg2_nxv4f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
	; CHECK-NEXT: vlseg2e64.v v4, (a0)			; CHECK-NEXT: vlseg2e64.v v4, (a0)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlseg2.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlseg2.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1			%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
	ret <vscale x 4 x double> %1			ret <vscale x 4 x double> %1
	}			}

	define <vscale x 4 x double> @test_vlseg2_mask_nxv4f64(double* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x double> @test_vlseg2_mask_nxv4f64(double* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv4f64:			; CHECK-LABEL: test_vlseg2_mask_nxv4f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
	; CHECK-NEXT: vlseg2e64.v v4, (a0)			; CHECK-NEXT: vlseg2e64.v v4, (a0)
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlseg2e64.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e64.v v4, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlseg2.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlseg2.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0			%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
	%2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlseg2.mask.nxv4f64(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlseg2.mask.nxv4f64(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1			%3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
	ret <vscale x 4 x double> %3			ret <vscale x 4 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg2.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg2.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
	declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg2.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg2.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x double> @test_vlseg2_nxv1f64(double* %base, i32 %vl) {			define <vscale x 1 x double> @test_vlseg2_nxv1f64(double* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv1f64:			; CHECK-LABEL: test_vlseg2_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg2e64.v v7, (a0)			; CHECK-NEXT: vlseg2e64.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg2.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg2.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg2_mask_nxv1f64(double* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlseg2_mask_nxv1f64(double* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv1f64:			; CHECK-LABEL: test_vlseg2_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg2e64.v v7, (a0)			; CHECK-NEXT: vlseg2e64.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e64.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e64.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg2.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg2.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg2.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg2.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg3.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg3.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg3.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg3.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x double> @test_vlseg3_nxv1f64(double* %base, i32 %vl) {			define <vscale x 1 x double> @test_vlseg3_nxv1f64(double* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv1f64:			; CHECK-LABEL: test_vlseg3_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg3e64.v v7, (a0)			; CHECK-NEXT: vlseg3e64.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg3.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg3.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg3_mask_nxv1f64(double* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlseg3_mask_nxv1f64(double* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv1f64:			; CHECK-LABEL: test_vlseg3_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg3e64.v v7, (a0)			; CHECK-NEXT: vlseg3e64.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e64.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e64.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg3.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg3.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg3.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg3.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg4.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg4.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg4.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg4.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x double> @test_vlseg4_nxv1f64(double* %base, i32 %vl) {			define <vscale x 1 x double> @test_vlseg4_nxv1f64(double* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv1f64:			; CHECK-LABEL: test_vlseg4_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg4e64.v v7, (a0)			; CHECK-NEXT: vlseg4e64.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg4.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg4.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg4_mask_nxv1f64(double* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlseg4_mask_nxv1f64(double* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv1f64:			; CHECK-LABEL: test_vlseg4_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg4e64.v v7, (a0)			; CHECK-NEXT: vlseg4e64.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e64.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e64.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg4.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg4.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg4.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg4.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg5.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg5.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg5.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg5.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x double> @test_vlseg5_nxv1f64(double* %base, i32 %vl) {			define <vscale x 1 x double> @test_vlseg5_nxv1f64(double* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv1f64:			; CHECK-LABEL: test_vlseg5_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg5e64.v v7, (a0)			; CHECK-NEXT: vlseg5e64.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg5.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg5.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg5_mask_nxv1f64(double* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlseg5_mask_nxv1f64(double* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv1f64:			; CHECK-LABEL: test_vlseg5_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg5e64.v v7, (a0)			; CHECK-NEXT: vlseg5e64.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e64.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e64.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg5.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg5.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg5.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg5.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg6.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg6.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg6.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg6.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x double> @test_vlseg6_nxv1f64(double* %base, i32 %vl) {			define <vscale x 1 x double> @test_vlseg6_nxv1f64(double* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv1f64:			; CHECK-LABEL: test_vlseg6_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg6e64.v v7, (a0)			; CHECK-NEXT: vlseg6e64.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg6.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg6.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg6_mask_nxv1f64(double* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlseg6_mask_nxv1f64(double* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv1f64:			; CHECK-LABEL: test_vlseg6_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg6e64.v v7, (a0)			; CHECK-NEXT: vlseg6e64.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e64.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e64.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg6.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg6.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg6.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg6.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg7.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg7.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg7.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg7.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x double> @test_vlseg7_nxv1f64(double* %base, i32 %vl) {			define <vscale x 1 x double> @test_vlseg7_nxv1f64(double* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv1f64:			; CHECK-LABEL: test_vlseg7_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg7e64.v v7, (a0)			; CHECK-NEXT: vlseg7e64.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg7.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg7.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg7_mask_nxv1f64(double* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlseg7_mask_nxv1f64(double* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv1f64:			; CHECK-LABEL: test_vlseg7_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg7e64.v v7, (a0)			; CHECK-NEXT: vlseg7e64.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e64.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e64.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg7.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg7.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg7.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg7.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg8.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg8.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg8.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg8.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x double> @test_vlseg8_nxv1f64(double* %base, i32 %vl) {			define <vscale x 1 x double> @test_vlseg8_nxv1f64(double* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv1f64:			; CHECK-LABEL: test_vlseg8_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg8e64.v v7, (a0)			; CHECK-NEXT: vlseg8e64.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg8.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg8.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg8_mask_nxv1f64(double* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlseg8_mask_nxv1f64(double* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv1f64:			; CHECK-LABEL: test_vlseg8_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg8e64.v v7, (a0)			; CHECK-NEXT: vlseg8e64.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e64.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e64.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg8.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg8.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg8.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg8.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg2.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg2.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
	declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg2.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg2.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x float> @test_vlseg2_nxv2f32(float* %base, i32 %vl) {			define <vscale x 2 x float> @test_vlseg2_nxv2f32(float* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv2f32:			; CHECK-LABEL: test_vlseg2_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg2e32.v v7, (a0)			; CHECK-NEXT: vlseg2e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg2.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg2.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg2_mask_nxv2f32(float* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlseg2_mask_nxv2f32(float* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv2f32:			; CHECK-LABEL: test_vlseg2_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg2e32.v v7, (a0)			; CHECK-NEXT: vlseg2e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg2.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg2.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg2.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg2.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg3.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg3.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg3.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg3.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x float> @test_vlseg3_nxv2f32(float* %base, i32 %vl) {			define <vscale x 2 x float> @test_vlseg3_nxv2f32(float* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv2f32:			; CHECK-LABEL: test_vlseg3_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg3e32.v v7, (a0)			; CHECK-NEXT: vlseg3e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg3.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg3.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg3_mask_nxv2f32(float* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlseg3_mask_nxv2f32(float* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv2f32:			; CHECK-LABEL: test_vlseg3_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg3e32.v v7, (a0)			; CHECK-NEXT: vlseg3e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg3.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg3.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg3.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg3.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg4.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg4.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg4.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg4.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x float> @test_vlseg4_nxv2f32(float* %base, i32 %vl) {			define <vscale x 2 x float> @test_vlseg4_nxv2f32(float* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv2f32:			; CHECK-LABEL: test_vlseg4_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg4e32.v v7, (a0)			; CHECK-NEXT: vlseg4e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg4.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg4.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg4_mask_nxv2f32(float* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlseg4_mask_nxv2f32(float* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv2f32:			; CHECK-LABEL: test_vlseg4_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg4e32.v v7, (a0)			; CHECK-NEXT: vlseg4e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg4.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg4.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg4.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg4.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg5.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg5.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg5.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg5.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x float> @test_vlseg5_nxv2f32(float* %base, i32 %vl) {			define <vscale x 2 x float> @test_vlseg5_nxv2f32(float* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv2f32:			; CHECK-LABEL: test_vlseg5_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg5e32.v v7, (a0)			; CHECK-NEXT: vlseg5e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg5.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg5.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg5_mask_nxv2f32(float* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlseg5_mask_nxv2f32(float* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv2f32:			; CHECK-LABEL: test_vlseg5_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg5e32.v v7, (a0)			; CHECK-NEXT: vlseg5e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg5.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg5.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg5.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg5.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg6.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg6.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg6.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg6.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x float> @test_vlseg6_nxv2f32(float* %base, i32 %vl) {			define <vscale x 2 x float> @test_vlseg6_nxv2f32(float* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv2f32:			; CHECK-LABEL: test_vlseg6_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg6e32.v v7, (a0)			; CHECK-NEXT: vlseg6e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg6.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg6.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg6_mask_nxv2f32(float* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlseg6_mask_nxv2f32(float* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv2f32:			; CHECK-LABEL: test_vlseg6_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg6e32.v v7, (a0)			; CHECK-NEXT: vlseg6e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg6.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg6.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg6.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg6.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg7.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg7.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg7.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg7.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x float> @test_vlseg7_nxv2f32(float* %base, i32 %vl) {			define <vscale x 2 x float> @test_vlseg7_nxv2f32(float* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv2f32:			; CHECK-LABEL: test_vlseg7_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg7e32.v v7, (a0)			; CHECK-NEXT: vlseg7e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg7.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg7.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg7_mask_nxv2f32(float* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlseg7_mask_nxv2f32(float* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv2f32:			; CHECK-LABEL: test_vlseg7_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg7e32.v v7, (a0)			; CHECK-NEXT: vlseg7e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg7.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg7.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg7.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg7.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg8.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg8.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg8.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg8.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x float> @test_vlseg8_nxv2f32(float* %base, i32 %vl) {			define <vscale x 2 x float> @test_vlseg8_nxv2f32(float* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv2f32:			; CHECK-LABEL: test_vlseg8_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg8e32.v v7, (a0)			; CHECK-NEXT: vlseg8e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg8.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg8.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg8_mask_nxv2f32(float* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlseg8_mask_nxv2f32(float* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv2f32:			; CHECK-LABEL: test_vlseg8_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg8e32.v v7, (a0)			; CHECK-NEXT: vlseg8e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg8.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg8.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg8.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg8.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg2.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg2.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
	declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg2.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg2.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x half> @test_vlseg2_nxv1f16(half* %base, i32 %vl) {			define <vscale x 1 x half> @test_vlseg2_nxv1f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv1f16:			; CHECK-LABEL: test_vlseg2_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg2.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg2.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg2_mask_nxv1f16(half* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlseg2_mask_nxv1f16(half* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv1f16:			; CHECK-LABEL: test_vlseg2_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg2.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg2.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg2.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg2.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg3.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg3.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg3.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg3.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x half> @test_vlseg3_nxv1f16(half* %base, i32 %vl) {			define <vscale x 1 x half> @test_vlseg3_nxv1f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv1f16:			; CHECK-LABEL: test_vlseg3_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg3.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg3.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg3_mask_nxv1f16(half* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlseg3_mask_nxv1f16(half* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv1f16:			; CHECK-LABEL: test_vlseg3_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg3.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg3.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg3.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg3.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg4.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg4.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg4.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg4.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x half> @test_vlseg4_nxv1f16(half* %base, i32 %vl) {			define <vscale x 1 x half> @test_vlseg4_nxv1f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv1f16:			; CHECK-LABEL: test_vlseg4_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg4.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg4.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg4_mask_nxv1f16(half* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlseg4_mask_nxv1f16(half* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv1f16:			; CHECK-LABEL: test_vlseg4_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg4.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg4.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg4.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg4.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg5.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg5.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg5.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg5.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x half> @test_vlseg5_nxv1f16(half* %base, i32 %vl) {			define <vscale x 1 x half> @test_vlseg5_nxv1f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv1f16:			; CHECK-LABEL: test_vlseg5_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg5.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg5.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg5_mask_nxv1f16(half* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlseg5_mask_nxv1f16(half* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv1f16:			; CHECK-LABEL: test_vlseg5_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg5.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg5.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg5.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg5.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg6.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg6.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg6.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg6.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x half> @test_vlseg6_nxv1f16(half* %base, i32 %vl) {			define <vscale x 1 x half> @test_vlseg6_nxv1f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv1f16:			; CHECK-LABEL: test_vlseg6_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg6.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg6.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg6_mask_nxv1f16(half* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlseg6_mask_nxv1f16(half* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv1f16:			; CHECK-LABEL: test_vlseg6_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg6.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg6.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg6.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg6.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg7.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg7.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg7.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg7.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x half> @test_vlseg7_nxv1f16(half* %base, i32 %vl) {			define <vscale x 1 x half> @test_vlseg7_nxv1f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv1f16:			; CHECK-LABEL: test_vlseg7_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg7.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg7.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg7_mask_nxv1f16(half* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlseg7_mask_nxv1f16(half* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv1f16:			; CHECK-LABEL: test_vlseg7_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg7.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg7.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg7.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg7.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg8.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg8.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg8.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg8.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x half> @test_vlseg8_nxv1f16(half* %base, i32 %vl) {			define <vscale x 1 x half> @test_vlseg8_nxv1f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv1f16:			; CHECK-LABEL: test_vlseg8_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg8.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg8.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg8_mask_nxv1f16(half* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlseg8_mask_nxv1f16(half* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv1f16:			; CHECK-LABEL: test_vlseg8_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg8.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg8.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg8.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg8.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg2.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg2.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
	declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg2.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg2.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x float> @test_vlseg2_nxv1f32(float* %base, i32 %vl) {			define <vscale x 1 x float> @test_vlseg2_nxv1f32(float* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv1f32:			; CHECK-LABEL: test_vlseg2_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg2e32.v v7, (a0)			; CHECK-NEXT: vlseg2e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg2.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg2.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg2_mask_nxv1f32(float* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlseg2_mask_nxv1f32(float* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv1f32:			; CHECK-LABEL: test_vlseg2_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg2e32.v v7, (a0)			; CHECK-NEXT: vlseg2e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg2.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg2.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg2.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg2.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg3.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg3.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg3.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg3.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x float> @test_vlseg3_nxv1f32(float* %base, i32 %vl) {			define <vscale x 1 x float> @test_vlseg3_nxv1f32(float* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv1f32:			; CHECK-LABEL: test_vlseg3_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg3e32.v v7, (a0)			; CHECK-NEXT: vlseg3e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg3.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg3.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg3_mask_nxv1f32(float* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlseg3_mask_nxv1f32(float* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv1f32:			; CHECK-LABEL: test_vlseg3_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg3e32.v v7, (a0)			; CHECK-NEXT: vlseg3e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg3.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg3.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg3.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg3.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg4.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg4.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg4.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg4.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x float> @test_vlseg4_nxv1f32(float* %base, i32 %vl) {			define <vscale x 1 x float> @test_vlseg4_nxv1f32(float* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv1f32:			; CHECK-LABEL: test_vlseg4_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg4e32.v v7, (a0)			; CHECK-NEXT: vlseg4e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg4.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg4.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg4_mask_nxv1f32(float* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlseg4_mask_nxv1f32(float* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv1f32:			; CHECK-LABEL: test_vlseg4_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg4e32.v v7, (a0)			; CHECK-NEXT: vlseg4e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg4.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg4.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg4.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg4.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg5.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg5.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg5.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg5.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x float> @test_vlseg5_nxv1f32(float* %base, i32 %vl) {			define <vscale x 1 x float> @test_vlseg5_nxv1f32(float* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv1f32:			; CHECK-LABEL: test_vlseg5_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg5e32.v v7, (a0)			; CHECK-NEXT: vlseg5e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg5.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg5.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg5_mask_nxv1f32(float* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlseg5_mask_nxv1f32(float* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv1f32:			; CHECK-LABEL: test_vlseg5_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg5e32.v v7, (a0)			; CHECK-NEXT: vlseg5e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg5.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg5.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg5.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg5.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg6.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg6.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg6.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg6.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x float> @test_vlseg6_nxv1f32(float* %base, i32 %vl) {			define <vscale x 1 x float> @test_vlseg6_nxv1f32(float* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv1f32:			; CHECK-LABEL: test_vlseg6_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg6e32.v v7, (a0)			; CHECK-NEXT: vlseg6e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg6.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg6.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg6_mask_nxv1f32(float* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlseg6_mask_nxv1f32(float* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv1f32:			; CHECK-LABEL: test_vlseg6_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg6e32.v v7, (a0)			; CHECK-NEXT: vlseg6e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg6.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg6.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg6.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg6.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg7.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg7.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg7.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg7.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x float> @test_vlseg7_nxv1f32(float* %base, i32 %vl) {			define <vscale x 1 x float> @test_vlseg7_nxv1f32(float* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv1f32:			; CHECK-LABEL: test_vlseg7_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg7e32.v v7, (a0)			; CHECK-NEXT: vlseg7e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg7.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg7.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg7_mask_nxv1f32(float* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlseg7_mask_nxv1f32(float* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv1f32:			; CHECK-LABEL: test_vlseg7_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg7e32.v v7, (a0)			; CHECK-NEXT: vlseg7e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg7.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg7.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg7.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg7.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg8.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg8.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg8.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg8.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x float> @test_vlseg8_nxv1f32(float* %base, i32 %vl) {			define <vscale x 1 x float> @test_vlseg8_nxv1f32(float* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv1f32:			; CHECK-LABEL: test_vlseg8_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg8e32.v v7, (a0)			; CHECK-NEXT: vlseg8e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg8.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg8.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg8_mask_nxv1f32(float* %base, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlseg8_mask_nxv1f32(float* %base, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv1f32:			; CHECK-LABEL: test_vlseg8_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg8e32.v v7, (a0)			; CHECK-NEXT: vlseg8e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg8.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg8.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg8.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg8.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg2.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half* , i32)			declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg2.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half* , i32)
	declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg2.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg2.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x half> @test_vlseg2_nxv8f16(half* %base, i32 %vl) {			define <vscale x 8 x half> @test_vlseg2_nxv8f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv8f16:			; CHECK-LABEL: test_vlseg2_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg2e16.v v6, (a0)			; CHECK-NEXT: vlseg2e16.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg2.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg2.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	define <vscale x 8 x half> @test_vlseg2_mask_nxv8f16(half* %base, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x half> @test_vlseg2_mask_nxv8f16(half* %base, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv8f16:			; CHECK-LABEL: test_vlseg2_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg2e16.v v6, (a0)			; CHECK-NEXT: vlseg2e16.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlseg2e16.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e16.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg2.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg2.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
	%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg2.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg2.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1			%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
	ret <vscale x 8 x half> %3			ret <vscale x 8 x half> %3
	}			}

	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg3.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i32)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg3.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i32)
	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg3.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg3.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x half> @test_vlseg3_nxv8f16(half* %base, i32 %vl) {			define <vscale x 8 x half> @test_vlseg3_nxv8f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv8f16:			; CHECK-LABEL: test_vlseg3_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg3e16.v v6, (a0)			; CHECK-NEXT: vlseg3e16.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg3.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg3.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	define <vscale x 8 x half> @test_vlseg3_mask_nxv8f16(half* %base, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x half> @test_vlseg3_mask_nxv8f16(half* %base, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv8f16:			; CHECK-LABEL: test_vlseg3_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg3e16.v v6, (a0)			; CHECK-NEXT: vlseg3e16.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlseg3e16.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e16.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg3.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg3.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
	%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg3.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg3.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1			%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
	ret <vscale x 8 x half> %3			ret <vscale x 8 x half> %3
	}			}

	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg4.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i32)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg4.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i32)
	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg4.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg4.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x half> @test_vlseg4_nxv8f16(half* %base, i32 %vl) {			define <vscale x 8 x half> @test_vlseg4_nxv8f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv8f16:			; CHECK-LABEL: test_vlseg4_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg4e16.v v6, (a0)			; CHECK-NEXT: vlseg4e16.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg4.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg4.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	define <vscale x 8 x half> @test_vlseg4_mask_nxv8f16(half* %base, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x half> @test_vlseg4_mask_nxv8f16(half* %base, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv8f16:			; CHECK-LABEL: test_vlseg4_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg4e16.v v6, (a0)			; CHECK-NEXT: vlseg4e16.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlseg4e16.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e16.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg4.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg4.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
	%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg4.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg4.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1			%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
	ret <vscale x 8 x half> %3			ret <vscale x 8 x half> %3
	}			}

	declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlseg2.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float* , i32)			declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlseg2.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float* , i32)
	declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlseg2.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlseg2.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x float> @test_vlseg2_nxv8f32(float* %base, i32 %vl) {			define <vscale x 8 x float> @test_vlseg2_nxv8f32(float* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv8f32:			; CHECK-LABEL: test_vlseg2_nxv8f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vlseg2e32.v v4, (a0)			; CHECK-NEXT: vlseg2e32.v v4, (a0)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlseg2.nxv8f32(<vscale x 8 x float> undef, <vscale x 8 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlseg2.nxv8f32(<vscale x 8 x float> undef, <vscale x 8 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1			%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
	ret <vscale x 8 x float> %1			ret <vscale x 8 x float> %1
	}			}

	define <vscale x 8 x float> @test_vlseg2_mask_nxv8f32(float* %base, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x float> @test_vlseg2_mask_nxv8f32(float* %base, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv8f32:			; CHECK-LABEL: test_vlseg2_mask_nxv8f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vlseg2e32.v v4, (a0)			; CHECK-NEXT: vlseg2e32.v v4, (a0)
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlseg2e32.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e32.v v4, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlseg2.nxv8f32(<vscale x 8 x float> undef, <vscale x 8 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlseg2.nxv8f32(<vscale x 8 x float> undef, <vscale x 8 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0			%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
	%2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlseg2.mask.nxv8f32(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlseg2.mask.nxv8f32(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1			%3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
	ret <vscale x 8 x float> %3			ret <vscale x 8 x float> %3
	}			}

	declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg2.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double* , i32)			declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg2.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double* , i32)
	declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg2.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg2.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x double> @test_vlseg2_nxv2f64(double* %base, i32 %vl) {			define <vscale x 2 x double> @test_vlseg2_nxv2f64(double* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv2f64:			; CHECK-LABEL: test_vlseg2_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg2e64.v v6, (a0)			; CHECK-NEXT: vlseg2e64.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg2.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg2.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	define <vscale x 2 x double> @test_vlseg2_mask_nxv2f64(double* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x double> @test_vlseg2_mask_nxv2f64(double* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv2f64:			; CHECK-LABEL: test_vlseg2_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg2e64.v v6, (a0)			; CHECK-NEXT: vlseg2e64.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlseg2e64.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e64.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg2.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg2.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
	%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg2.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg2.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1			%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
	ret <vscale x 2 x double> %3			ret <vscale x 2 x double> %3
	}			}

	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg3.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i32)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg3.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i32)
	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg3.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg3.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x double> @test_vlseg3_nxv2f64(double* %base, i32 %vl) {			define <vscale x 2 x double> @test_vlseg3_nxv2f64(double* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv2f64:			; CHECK-LABEL: test_vlseg3_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg3e64.v v6, (a0)			; CHECK-NEXT: vlseg3e64.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg3.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg3.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	define <vscale x 2 x double> @test_vlseg3_mask_nxv2f64(double* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x double> @test_vlseg3_mask_nxv2f64(double* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv2f64:			; CHECK-LABEL: test_vlseg3_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg3e64.v v6, (a0)			; CHECK-NEXT: vlseg3e64.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlseg3e64.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e64.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg3.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg3.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
	%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg3.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg3.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1			%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
	ret <vscale x 2 x double> %3			ret <vscale x 2 x double> %3
	}			}

	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg4.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i32)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg4.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i32)
	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg4.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg4.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x double> @test_vlseg4_nxv2f64(double* %base, i32 %vl) {			define <vscale x 2 x double> @test_vlseg4_nxv2f64(double* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv2f64:			; CHECK-LABEL: test_vlseg4_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg4e64.v v6, (a0)			; CHECK-NEXT: vlseg4e64.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg4.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg4.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	define <vscale x 2 x double> @test_vlseg4_mask_nxv2f64(double* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x double> @test_vlseg4_mask_nxv2f64(double* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv2f64:			; CHECK-LABEL: test_vlseg4_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg4e64.v v6, (a0)			; CHECK-NEXT: vlseg4e64.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlseg4e64.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e64.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg4.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg4.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
	%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg4.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg4.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1			%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
	ret <vscale x 2 x double> %3			ret <vscale x 2 x double> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg2.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg2.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
	declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg2.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg2.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x half> @test_vlseg2_nxv4f16(half* %base, i32 %vl) {			define <vscale x 4 x half> @test_vlseg2_nxv4f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv4f16:			; CHECK-LABEL: test_vlseg2_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg2.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg2.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg2_mask_nxv4f16(half* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlseg2_mask_nxv4f16(half* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv4f16:			; CHECK-LABEL: test_vlseg2_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg2.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg2.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg2.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg2.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg3.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg3.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg3.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg3.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x half> @test_vlseg3_nxv4f16(half* %base, i32 %vl) {			define <vscale x 4 x half> @test_vlseg3_nxv4f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv4f16:			; CHECK-LABEL: test_vlseg3_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg3.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg3.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg3_mask_nxv4f16(half* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlseg3_mask_nxv4f16(half* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv4f16:			; CHECK-LABEL: test_vlseg3_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg3.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg3.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg3.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg3.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg4.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg4.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg4.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg4.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x half> @test_vlseg4_nxv4f16(half* %base, i32 %vl) {			define <vscale x 4 x half> @test_vlseg4_nxv4f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv4f16:			; CHECK-LABEL: test_vlseg4_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg4.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg4.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg4_mask_nxv4f16(half* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlseg4_mask_nxv4f16(half* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv4f16:			; CHECK-LABEL: test_vlseg4_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg4.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg4.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg4.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg4.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg5.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg5.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg5.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg5.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x half> @test_vlseg5_nxv4f16(half* %base, i32 %vl) {			define <vscale x 4 x half> @test_vlseg5_nxv4f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv4f16:			; CHECK-LABEL: test_vlseg5_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg5.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg5.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg5_mask_nxv4f16(half* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlseg5_mask_nxv4f16(half* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv4f16:			; CHECK-LABEL: test_vlseg5_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg5.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg5.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg5.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg5.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg6.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg6.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg6.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg6.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x half> @test_vlseg6_nxv4f16(half* %base, i32 %vl) {			define <vscale x 4 x half> @test_vlseg6_nxv4f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv4f16:			; CHECK-LABEL: test_vlseg6_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg6.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg6.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg6_mask_nxv4f16(half* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlseg6_mask_nxv4f16(half* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv4f16:			; CHECK-LABEL: test_vlseg6_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg6.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg6.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg6.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg6.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg7.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg7.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg7.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg7.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x half> @test_vlseg7_nxv4f16(half* %base, i32 %vl) {			define <vscale x 4 x half> @test_vlseg7_nxv4f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv4f16:			; CHECK-LABEL: test_vlseg7_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg7.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg7.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg7_mask_nxv4f16(half* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlseg7_mask_nxv4f16(half* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv4f16:			; CHECK-LABEL: test_vlseg7_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg7.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg7.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg7.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg7.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg8.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg8.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg8.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg8.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x half> @test_vlseg8_nxv4f16(half* %base, i32 %vl) {			define <vscale x 4 x half> @test_vlseg8_nxv4f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv4f16:			; CHECK-LABEL: test_vlseg8_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg8.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg8.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg8_mask_nxv4f16(half* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlseg8_mask_nxv4f16(half* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv4f16:			; CHECK-LABEL: test_vlseg8_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg8.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg8.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg8.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg8.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg2.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg2.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
	declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg2.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg2.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x half> @test_vlseg2_nxv2f16(half* %base, i32 %vl) {			define <vscale x 2 x half> @test_vlseg2_nxv2f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv2f16:			; CHECK-LABEL: test_vlseg2_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg2.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg2.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg2_mask_nxv2f16(half* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlseg2_mask_nxv2f16(half* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv2f16:			; CHECK-LABEL: test_vlseg2_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg2.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg2.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg2.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg2.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg3.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg3.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg3.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg3.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x half> @test_vlseg3_nxv2f16(half* %base, i32 %vl) {			define <vscale x 2 x half> @test_vlseg3_nxv2f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv2f16:			; CHECK-LABEL: test_vlseg3_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg3.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg3.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg3_mask_nxv2f16(half* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlseg3_mask_nxv2f16(half* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv2f16:			; CHECK-LABEL: test_vlseg3_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg3.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg3.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg3.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg3.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg4.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg4.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg4.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg4.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x half> @test_vlseg4_nxv2f16(half* %base, i32 %vl) {			define <vscale x 2 x half> @test_vlseg4_nxv2f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv2f16:			; CHECK-LABEL: test_vlseg4_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg4.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg4.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg4_mask_nxv2f16(half* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlseg4_mask_nxv2f16(half* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv2f16:			; CHECK-LABEL: test_vlseg4_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg4.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg4.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg4.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg4.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg5.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg5.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg5.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg5.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x half> @test_vlseg5_nxv2f16(half* %base, i32 %vl) {			define <vscale x 2 x half> @test_vlseg5_nxv2f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv2f16:			; CHECK-LABEL: test_vlseg5_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg5.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg5.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg5_mask_nxv2f16(half* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlseg5_mask_nxv2f16(half* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv2f16:			; CHECK-LABEL: test_vlseg5_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg5.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg5.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg5.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg5.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg6.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg6.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg6.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg6.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x half> @test_vlseg6_nxv2f16(half* %base, i32 %vl) {			define <vscale x 2 x half> @test_vlseg6_nxv2f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv2f16:			; CHECK-LABEL: test_vlseg6_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg6.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg6.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg6_mask_nxv2f16(half* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlseg6_mask_nxv2f16(half* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv2f16:			; CHECK-LABEL: test_vlseg6_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg6.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg6.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg6.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg6.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg7.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg7.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg7.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg7.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x half> @test_vlseg7_nxv2f16(half* %base, i32 %vl) {			define <vscale x 2 x half> @test_vlseg7_nxv2f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv2f16:			; CHECK-LABEL: test_vlseg7_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg7.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg7.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg7_mask_nxv2f16(half* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlseg7_mask_nxv2f16(half* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv2f16:			; CHECK-LABEL: test_vlseg7_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg7.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg7.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg7.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg7.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg8.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg8.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg8.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg8.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x half> @test_vlseg8_nxv2f16(half* %base, i32 %vl) {			define <vscale x 2 x half> @test_vlseg8_nxv2f16(half* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv2f16:			; CHECK-LABEL: test_vlseg8_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg8.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg8.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg8_mask_nxv2f16(half* %base, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlseg8_mask_nxv2f16(half* %base, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv2f16:			; CHECK-LABEL: test_vlseg8_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg8.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg8.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg8.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg8.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg2.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float* , i32)			declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg2.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float* , i32)
	declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg2.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg2.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x float> @test_vlseg2_nxv4f32(float* %base, i32 %vl) {			define <vscale x 4 x float> @test_vlseg2_nxv4f32(float* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv4f32:			; CHECK-LABEL: test_vlseg2_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg2e32.v v6, (a0)			; CHECK-NEXT: vlseg2e32.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg2.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg2.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	define <vscale x 4 x float> @test_vlseg2_mask_nxv4f32(float* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x float> @test_vlseg2_mask_nxv4f32(float* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv4f32:			; CHECK-LABEL: test_vlseg2_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg2e32.v v6, (a0)			; CHECK-NEXT: vlseg2e32.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlseg2e32.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e32.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg2.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg2.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
	%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg2.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg2.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1			%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
	ret <vscale x 4 x float> %3			ret <vscale x 4 x float> %3
	}			}

	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg3.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i32)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg3.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i32)
	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg3.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg3.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x float> @test_vlseg3_nxv4f32(float* %base, i32 %vl) {			define <vscale x 4 x float> @test_vlseg3_nxv4f32(float* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv4f32:			; CHECK-LABEL: test_vlseg3_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg3e32.v v6, (a0)			; CHECK-NEXT: vlseg3e32.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg3.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg3.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	define <vscale x 4 x float> @test_vlseg3_mask_nxv4f32(float* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x float> @test_vlseg3_mask_nxv4f32(float* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv4f32:			; CHECK-LABEL: test_vlseg3_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg3e32.v v6, (a0)			; CHECK-NEXT: vlseg3e32.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlseg3e32.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e32.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg3.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg3.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
	%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg3.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg3.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1			%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
	ret <vscale x 4 x float> %3			ret <vscale x 4 x float> %3
	}			}

	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg4.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i32)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg4.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i32)
	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg4.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg4.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x float> @test_vlseg4_nxv4f32(float* %base, i32 %vl) {			define <vscale x 4 x float> @test_vlseg4_nxv4f32(float* %base, i32 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv4f32:			; CHECK-LABEL: test_vlseg4_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg4e32.v v6, (a0)			; CHECK-NEXT: vlseg4e32.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg4.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg4.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	define <vscale x 4 x float> @test_vlseg4_mask_nxv4f32(float* %base, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x float> @test_vlseg4_mask_nxv4f32(float* %base, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv4f32:			; CHECK-LABEL: test_vlseg4_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg4e32.v v6, (a0)			; CHECK-NEXT: vlseg4e32.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlseg4e32.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e32.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg4.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg4.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
	%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg4.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg4.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1			%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
	ret <vscale x 4 x float> %3			ret <vscale x 4 x float> %3
	}			}

llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \			; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \
	; RUN: -verify-machineinstrs < %s \| FileCheck %s			; RUN: -verify-machineinstrs < %s \| FileCheck %s

	declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16* , i64)			declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16* , i64)
	declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i64, i64)			declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i64, i64)

	define <vscale x 16 x i16> @test_vlseg2_nxv16i16(i16* %base, i64 %vl) {			define <vscale x 16 x i16> @test_vlseg2_nxv16i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv16i16:			; CHECK-LABEL: test_vlseg2_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vlseg2e16.v v4, (a0)			; CHECK-NEXT: vlseg2e16.v v4, (a0)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1			%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
	ret <vscale x 16 x i16> %1			ret <vscale x 16 x i16> %1
	}			}

	define <vscale x 16 x i16> @test_vlseg2_mask_nxv16i16(i16* %base, i64 %vl, <vscale x 16 x i1> %mask) {			define <vscale x 16 x i16> @test_vlseg2_mask_nxv16i16(i16* %base, i64 %vl, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv16i16:			; CHECK-LABEL: test_vlseg2_mask_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vlseg2e16.v v4, (a0)			; CHECK-NEXT: vlseg2e16.v v4, (a0)
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0			%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
	%2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.mask.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.mask.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1			%3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
	ret <vscale x 16 x i16> %3			ret <vscale x 16 x i16> %3
	}			}

	declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i64)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i64)
	declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i32> @test_vlseg2_nxv4i32(i32* %base, i64 %vl) {			define <vscale x 4 x i32> @test_vlseg2_nxv4i32(i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv4i32:			; CHECK-LABEL: test_vlseg2_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg2e32.v v6, (a0)			; CHECK-NEXT: vlseg2e32.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	define <vscale x 4 x i32> @test_vlseg2_mask_nxv4i32(i32* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i32> @test_vlseg2_mask_nxv4i32(i32* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv4i32:			; CHECK-LABEL: test_vlseg2_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg2e32.v v6, (a0)			; CHECK-NEXT: vlseg2e32.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlseg2e32.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e32.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
	%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1			%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
	ret <vscale x 4 x i32> %3			ret <vscale x 4 x i32> %3
	}			}

	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i64)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i64)
	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i32> @test_vlseg3_nxv4i32(i32* %base, i64 %vl) {			define <vscale x 4 x i32> @test_vlseg3_nxv4i32(i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv4i32:			; CHECK-LABEL: test_vlseg3_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg3e32.v v6, (a0)			; CHECK-NEXT: vlseg3e32.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	define <vscale x 4 x i32> @test_vlseg3_mask_nxv4i32(i32* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i32> @test_vlseg3_mask_nxv4i32(i32* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv4i32:			; CHECK-LABEL: test_vlseg3_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg3e32.v v6, (a0)			; CHECK-NEXT: vlseg3e32.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlseg3e32.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e32.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
	%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1			%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
	ret <vscale x 4 x i32> %3			ret <vscale x 4 x i32> %3
	}			}

	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg4.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i64)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg4.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i64)
	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg4.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg4.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i32> @test_vlseg4_nxv4i32(i32* %base, i64 %vl) {			define <vscale x 4 x i32> @test_vlseg4_nxv4i32(i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv4i32:			; CHECK-LABEL: test_vlseg4_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg4e32.v v6, (a0)			; CHECK-NEXT: vlseg4e32.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg4.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg4.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	define <vscale x 4 x i32> @test_vlseg4_mask_nxv4i32(i32* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i32> @test_vlseg4_mask_nxv4i32(i32* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv4i32:			; CHECK-LABEL: test_vlseg4_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg4e32.v v6, (a0)			; CHECK-NEXT: vlseg4e32.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlseg4e32.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e32.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg4.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg4.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
	%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg4.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg4.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1			%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
	ret <vscale x 4 x i32> %3			ret <vscale x 4 x i32> %3
	}			}

	declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg2.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i64)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg2.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i64)
	declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg2.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64, i64)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg2.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64, i64)

	define <vscale x 16 x i8> @test_vlseg2_nxv16i8(i8* %base, i64 %vl) {			define <vscale x 16 x i8> @test_vlseg2_nxv16i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv16i8:			; CHECK-LABEL: test_vlseg2_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg2e8.v v6, (a0)			; CHECK-NEXT: vlseg2e8.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg2.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg2.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	define <vscale x 16 x i8> @test_vlseg2_mask_nxv16i8(i8* %base, i64 %vl, <vscale x 16 x i1> %mask) {			define <vscale x 16 x i8> @test_vlseg2_mask_nxv16i8(i8* %base, i64 %vl, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv16i8:			; CHECK-LABEL: test_vlseg2_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg2e8.v v6, (a0)			; CHECK-NEXT: vlseg2e8.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlseg2e8.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e8.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg2.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg2.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
	%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg2.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg2.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1			%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
	ret <vscale x 16 x i8> %3			ret <vscale x 16 x i8> %3
	}			}

	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg3.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i64)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg3.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i64)
	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg3.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64, i64)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg3.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64, i64)

	define <vscale x 16 x i8> @test_vlseg3_nxv16i8(i8* %base, i64 %vl) {			define <vscale x 16 x i8> @test_vlseg3_nxv16i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv16i8:			; CHECK-LABEL: test_vlseg3_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg3e8.v v6, (a0)			; CHECK-NEXT: vlseg3e8.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg3.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg3.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	define <vscale x 16 x i8> @test_vlseg3_mask_nxv16i8(i8* %base, i64 %vl, <vscale x 16 x i1> %mask) {			define <vscale x 16 x i8> @test_vlseg3_mask_nxv16i8(i8* %base, i64 %vl, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv16i8:			; CHECK-LABEL: test_vlseg3_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg3e8.v v6, (a0)			; CHECK-NEXT: vlseg3e8.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlseg3e8.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e8.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg3.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg3.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
	%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg3.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg3.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1			%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
	ret <vscale x 16 x i8> %3			ret <vscale x 16 x i8> %3
	}			}

	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg4.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i64)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg4.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i64)
	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg4.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64, i64)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg4.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64, i64)

	define <vscale x 16 x i8> @test_vlseg4_nxv16i8(i8* %base, i64 %vl) {			define <vscale x 16 x i8> @test_vlseg4_nxv16i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv16i8:			; CHECK-LABEL: test_vlseg4_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg4e8.v v6, (a0)			; CHECK-NEXT: vlseg4e8.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg4.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg4.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	define <vscale x 16 x i8> @test_vlseg4_mask_nxv16i8(i8* %base, i64 %vl, <vscale x 16 x i1> %mask) {			define <vscale x 16 x i8> @test_vlseg4_mask_nxv16i8(i8* %base, i64 %vl, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv16i8:			; CHECK-LABEL: test_vlseg4_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg4e8.v v6, (a0)			; CHECK-NEXT: vlseg4e8.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlseg4e8.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e8.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg4.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg4.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
	%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg4.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlseg4.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1			%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
	ret <vscale x 16 x i8> %3			ret <vscale x 16 x i8> %3
	}			}

	declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg2.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg2.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
	declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg2.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg2.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i64> @test_vlseg2_nxv1i64(i64* %base, i64 %vl) {			define <vscale x 1 x i64> @test_vlseg2_nxv1i64(i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv1i64:			; CHECK-LABEL: test_vlseg2_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg2e64.v v7, (a0)			; CHECK-NEXT: vlseg2e64.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg2.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg2.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	define <vscale x 1 x i64> @test_vlseg2_mask_nxv1i64(i64* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i64> @test_vlseg2_mask_nxv1i64(i64* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv1i64:			; CHECK-LABEL: test_vlseg2_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg2e64.v v7, (a0)			; CHECK-NEXT: vlseg2e64.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e64.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e64.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg2.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg2.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
	%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg2.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg2.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1			%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
	ret <vscale x 1 x i64> %3			ret <vscale x 1 x i64> %3
	}			}

	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg3.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg3.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg3.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg3.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i64> @test_vlseg3_nxv1i64(i64* %base, i64 %vl) {			define <vscale x 1 x i64> @test_vlseg3_nxv1i64(i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv1i64:			; CHECK-LABEL: test_vlseg3_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg3e64.v v7, (a0)			; CHECK-NEXT: vlseg3e64.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg3.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg3.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	define <vscale x 1 x i64> @test_vlseg3_mask_nxv1i64(i64* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i64> @test_vlseg3_mask_nxv1i64(i64* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv1i64:			; CHECK-LABEL: test_vlseg3_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg3e64.v v7, (a0)			; CHECK-NEXT: vlseg3e64.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e64.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e64.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg3.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg3.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
	%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg3.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg3.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1			%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
	ret <vscale x 1 x i64> %3			ret <vscale x 1 x i64> %3
	}			}

	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg4.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg4.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg4.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg4.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i64> @test_vlseg4_nxv1i64(i64* %base, i64 %vl) {			define <vscale x 1 x i64> @test_vlseg4_nxv1i64(i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv1i64:			; CHECK-LABEL: test_vlseg4_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg4e64.v v7, (a0)			; CHECK-NEXT: vlseg4e64.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg4.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg4.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	define <vscale x 1 x i64> @test_vlseg4_mask_nxv1i64(i64* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i64> @test_vlseg4_mask_nxv1i64(i64* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv1i64:			; CHECK-LABEL: test_vlseg4_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg4e64.v v7, (a0)			; CHECK-NEXT: vlseg4e64.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e64.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e64.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg4.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg4.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
	%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg4.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg4.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1			%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
	ret <vscale x 1 x i64> %3			ret <vscale x 1 x i64> %3
	}			}

	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg5.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg5.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg5.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg5.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i64> @test_vlseg5_nxv1i64(i64* %base, i64 %vl) {			define <vscale x 1 x i64> @test_vlseg5_nxv1i64(i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv1i64:			; CHECK-LABEL: test_vlseg5_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg5e64.v v7, (a0)			; CHECK-NEXT: vlseg5e64.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg5.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg5.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	define <vscale x 1 x i64> @test_vlseg5_mask_nxv1i64(i64* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i64> @test_vlseg5_mask_nxv1i64(i64* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv1i64:			; CHECK-LABEL: test_vlseg5_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg5e64.v v7, (a0)			; CHECK-NEXT: vlseg5e64.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e64.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e64.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg5.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg5.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
	%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg5.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg5.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1			%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
	ret <vscale x 1 x i64> %3			ret <vscale x 1 x i64> %3
	}			}

	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg6.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg6.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg6.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg6.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i64> @test_vlseg6_nxv1i64(i64* %base, i64 %vl) {			define <vscale x 1 x i64> @test_vlseg6_nxv1i64(i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv1i64:			; CHECK-LABEL: test_vlseg6_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg6e64.v v7, (a0)			; CHECK-NEXT: vlseg6e64.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg6.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg6.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	define <vscale x 1 x i64> @test_vlseg6_mask_nxv1i64(i64* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i64> @test_vlseg6_mask_nxv1i64(i64* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv1i64:			; CHECK-LABEL: test_vlseg6_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg6e64.v v7, (a0)			; CHECK-NEXT: vlseg6e64.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e64.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e64.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg6.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg6.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
	%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg6.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg6.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1			%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
	ret <vscale x 1 x i64> %3			ret <vscale x 1 x i64> %3
	}			}

	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg7.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg7.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg7.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg7.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i64> @test_vlseg7_nxv1i64(i64* %base, i64 %vl) {			define <vscale x 1 x i64> @test_vlseg7_nxv1i64(i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv1i64:			; CHECK-LABEL: test_vlseg7_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg7e64.v v7, (a0)			; CHECK-NEXT: vlseg7e64.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg7.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg7.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	define <vscale x 1 x i64> @test_vlseg7_mask_nxv1i64(i64* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i64> @test_vlseg7_mask_nxv1i64(i64* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv1i64:			; CHECK-LABEL: test_vlseg7_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg7e64.v v7, (a0)			; CHECK-NEXT: vlseg7e64.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e64.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e64.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg7.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg7.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
	%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg7.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg7.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1			%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
	ret <vscale x 1 x i64> %3			ret <vscale x 1 x i64> %3
	}			}

	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg8.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg8.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg8.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg8.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i64> @test_vlseg8_nxv1i64(i64* %base, i64 %vl) {			define <vscale x 1 x i64> @test_vlseg8_nxv1i64(i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv1i64:			; CHECK-LABEL: test_vlseg8_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg8e64.v v7, (a0)			; CHECK-NEXT: vlseg8e64.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg8.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef ,<vscale x 1 x i64> undef ,<vscale x 1 x i64> undef, <vscale x 1 x i64> undef ,<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg8.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef ,<vscale x 1 x i64> undef ,<vscale x 1 x i64> undef, <vscale x 1 x i64> undef ,<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	define <vscale x 1 x i64> @test_vlseg8_mask_nxv1i64(i64* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i64> @test_vlseg8_mask_nxv1i64(i64* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv1i64:			; CHECK-LABEL: test_vlseg8_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg8e64.v v7, (a0)			; CHECK-NEXT: vlseg8e64.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e64.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e64.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg8.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef ,<vscale x 1 x i64> undef ,<vscale x 1 x i64> undef, <vscale x 1 x i64> undef ,<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg8.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef ,<vscale x 1 x i64> undef ,<vscale x 1 x i64> undef, <vscale x 1 x i64> undef ,<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
	%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg8.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlseg8.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1			%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
	ret <vscale x 1 x i64> %3			ret <vscale x 1 x i64> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i32> @test_vlseg2_nxv1i32(i32* %base, i64 %vl) {			define <vscale x 1 x i32> @test_vlseg2_nxv1i32(i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv1i32:			; CHECK-LABEL: test_vlseg2_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg2e32.v v7, (a0)			; CHECK-NEXT: vlseg2e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg2_mask_nxv1i32(i32* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlseg2_mask_nxv1i32(i32* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv1i32:			; CHECK-LABEL: test_vlseg2_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg2e32.v v7, (a0)			; CHECK-NEXT: vlseg2e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i32> @test_vlseg3_nxv1i32(i32* %base, i64 %vl) {			define <vscale x 1 x i32> @test_vlseg3_nxv1i32(i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv1i32:			; CHECK-LABEL: test_vlseg3_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg3e32.v v7, (a0)			; CHECK-NEXT: vlseg3e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg3_mask_nxv1i32(i32* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlseg3_mask_nxv1i32(i32* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv1i32:			; CHECK-LABEL: test_vlseg3_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg3e32.v v7, (a0)			; CHECK-NEXT: vlseg3e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg3.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i32> @test_vlseg4_nxv1i32(i32* %base, i64 %vl) {			define <vscale x 1 x i32> @test_vlseg4_nxv1i32(i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv1i32:			; CHECK-LABEL: test_vlseg4_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg4e32.v v7, (a0)			; CHECK-NEXT: vlseg4e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg4_mask_nxv1i32(i32* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlseg4_mask_nxv1i32(i32* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv1i32:			; CHECK-LABEL: test_vlseg4_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg4e32.v v7, (a0)			; CHECK-NEXT: vlseg4e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg4.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i32> @test_vlseg5_nxv1i32(i32* %base, i64 %vl) {			define <vscale x 1 x i32> @test_vlseg5_nxv1i32(i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv1i32:			; CHECK-LABEL: test_vlseg5_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg5e32.v v7, (a0)			; CHECK-NEXT: vlseg5e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg5_mask_nxv1i32(i32* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlseg5_mask_nxv1i32(i32* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv1i32:			; CHECK-LABEL: test_vlseg5_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg5e32.v v7, (a0)			; CHECK-NEXT: vlseg5e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg5.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i32> @test_vlseg6_nxv1i32(i32* %base, i64 %vl) {			define <vscale x 1 x i32> @test_vlseg6_nxv1i32(i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv1i32:			; CHECK-LABEL: test_vlseg6_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg6e32.v v7, (a0)			; CHECK-NEXT: vlseg6e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg6_mask_nxv1i32(i32* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlseg6_mask_nxv1i32(i32* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv1i32:			; CHECK-LABEL: test_vlseg6_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg6e32.v v7, (a0)			; CHECK-NEXT: vlseg6e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg6.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i32> @test_vlseg7_nxv1i32(i32* %base, i64 %vl) {			define <vscale x 1 x i32> @test_vlseg7_nxv1i32(i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv1i32:			; CHECK-LABEL: test_vlseg7_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg7e32.v v7, (a0)			; CHECK-NEXT: vlseg7e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg7_mask_nxv1i32(i32* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlseg7_mask_nxv1i32(i32* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv1i32:			; CHECK-LABEL: test_vlseg7_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg7e32.v v7, (a0)			; CHECK-NEXT: vlseg7e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg7.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i32> @test_vlseg8_nxv1i32(i32* %base, i64 %vl) {			define <vscale x 1 x i32> @test_vlseg8_nxv1i32(i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv1i32:			; CHECK-LABEL: test_vlseg8_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg8e32.v v7, (a0)			; CHECK-NEXT: vlseg8e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg8_mask_nxv1i32(i32* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlseg8_mask_nxv1i32(i32* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv1i32:			; CHECK-LABEL: test_vlseg8_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg8e32.v v7, (a0)			; CHECK-NEXT: vlseg8e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg8.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg2.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i64)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg2.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i64)
	declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg2.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg2.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i16> @test_vlseg2_nxv8i16(i16* %base, i64 %vl) {			define <vscale x 8 x i16> @test_vlseg2_nxv8i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv8i16:			; CHECK-LABEL: test_vlseg2_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg2e16.v v6, (a0)			; CHECK-NEXT: vlseg2e16.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg2.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg2.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	define <vscale x 8 x i16> @test_vlseg2_mask_nxv8i16(i16* %base, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i16> @test_vlseg2_mask_nxv8i16(i16* %base, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv8i16:			; CHECK-LABEL: test_vlseg2_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg2e16.v v6, (a0)			; CHECK-NEXT: vlseg2e16.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlseg2e16.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e16.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg2.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg2.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
	%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg2.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg2.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1			%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
	ret <vscale x 8 x i16> %3			ret <vscale x 8 x i16> %3
	}			}

	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg3.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i64)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg3.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i64)
	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg3.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg3.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i16> @test_vlseg3_nxv8i16(i16* %base, i64 %vl) {			define <vscale x 8 x i16> @test_vlseg3_nxv8i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv8i16:			; CHECK-LABEL: test_vlseg3_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg3e16.v v6, (a0)			; CHECK-NEXT: vlseg3e16.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg3.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg3.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	define <vscale x 8 x i16> @test_vlseg3_mask_nxv8i16(i16* %base, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i16> @test_vlseg3_mask_nxv8i16(i16* %base, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv8i16:			; CHECK-LABEL: test_vlseg3_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg3e16.v v6, (a0)			; CHECK-NEXT: vlseg3e16.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlseg3e16.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e16.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg3.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg3.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
	%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg3.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg3.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1			%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
	ret <vscale x 8 x i16> %3			ret <vscale x 8 x i16> %3
	}			}

	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg4.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i64)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg4.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i64)
	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg4.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg4.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i16> @test_vlseg4_nxv8i16(i16* %base, i64 %vl) {			define <vscale x 8 x i16> @test_vlseg4_nxv8i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv8i16:			; CHECK-LABEL: test_vlseg4_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg4e16.v v6, (a0)			; CHECK-NEXT: vlseg4e16.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg4.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg4.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	define <vscale x 8 x i16> @test_vlseg4_mask_nxv8i16(i16* %base, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i16> @test_vlseg4_mask_nxv8i16(i16* %base, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv8i16:			; CHECK-LABEL: test_vlseg4_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg4e16.v v6, (a0)			; CHECK-NEXT: vlseg4e16.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlseg4e16.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e16.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg4.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg4.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
	%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg4.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlseg4.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1			%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
	ret <vscale x 8 x i16> %3			ret <vscale x 8 x i16> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg2.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg2.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg2.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg2.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i8> @test_vlseg2_nxv4i8(i8* %base, i64 %vl) {			define <vscale x 4 x i8> @test_vlseg2_nxv4i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv4i8:			; CHECK-LABEL: test_vlseg2_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg2e8.v v7, (a0)			; CHECK-NEXT: vlseg2e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg2.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg2.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg2_mask_nxv4i8(i8* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlseg2_mask_nxv4i8(i8* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv4i8:			; CHECK-LABEL: test_vlseg2_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg2e8.v v7, (a0)			; CHECK-NEXT: vlseg2e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg2.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg2.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg2.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg2.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg3.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg3.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg3.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg3.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i8> @test_vlseg3_nxv4i8(i8* %base, i64 %vl) {			define <vscale x 4 x i8> @test_vlseg3_nxv4i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv4i8:			; CHECK-LABEL: test_vlseg3_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg3e8.v v7, (a0)			; CHECK-NEXT: vlseg3e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg3.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg3.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg3_mask_nxv4i8(i8* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlseg3_mask_nxv4i8(i8* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv4i8:			; CHECK-LABEL: test_vlseg3_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg3e8.v v7, (a0)			; CHECK-NEXT: vlseg3e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg3.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg3.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg3.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg3.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg4.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg4.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg4.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg4.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i8> @test_vlseg4_nxv4i8(i8* %base, i64 %vl) {			define <vscale x 4 x i8> @test_vlseg4_nxv4i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv4i8:			; CHECK-LABEL: test_vlseg4_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg4e8.v v7, (a0)			; CHECK-NEXT: vlseg4e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg4.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg4.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg4_mask_nxv4i8(i8* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlseg4_mask_nxv4i8(i8* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv4i8:			; CHECK-LABEL: test_vlseg4_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg4e8.v v7, (a0)			; CHECK-NEXT: vlseg4e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg4.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg4.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg4.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg4.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg5.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg5.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg5.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg5.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i8> @test_vlseg5_nxv4i8(i8* %base, i64 %vl) {			define <vscale x 4 x i8> @test_vlseg5_nxv4i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv4i8:			; CHECK-LABEL: test_vlseg5_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg5e8.v v7, (a0)			; CHECK-NEXT: vlseg5e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg5.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg5.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg5_mask_nxv4i8(i8* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlseg5_mask_nxv4i8(i8* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv4i8:			; CHECK-LABEL: test_vlseg5_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg5e8.v v7, (a0)			; CHECK-NEXT: vlseg5e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg5.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg5.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg5.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg5.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg6.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg6.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg6.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg6.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i8> @test_vlseg6_nxv4i8(i8* %base, i64 %vl) {			define <vscale x 4 x i8> @test_vlseg6_nxv4i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv4i8:			; CHECK-LABEL: test_vlseg6_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg6e8.v v7, (a0)			; CHECK-NEXT: vlseg6e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg6.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg6.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg6_mask_nxv4i8(i8* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlseg6_mask_nxv4i8(i8* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv4i8:			; CHECK-LABEL: test_vlseg6_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg6e8.v v7, (a0)			; CHECK-NEXT: vlseg6e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg6.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg6.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg6.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg6.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg7.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg7.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg7.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg7.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i8> @test_vlseg7_nxv4i8(i8* %base, i64 %vl) {			define <vscale x 4 x i8> @test_vlseg7_nxv4i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv4i8:			; CHECK-LABEL: test_vlseg7_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg7e8.v v7, (a0)			; CHECK-NEXT: vlseg7e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg7.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg7.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg7_mask_nxv4i8(i8* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlseg7_mask_nxv4i8(i8* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv4i8:			; CHECK-LABEL: test_vlseg7_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg7e8.v v7, (a0)			; CHECK-NEXT: vlseg7e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg7.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg7.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg7.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg7.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg8.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg8.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i8> @test_vlseg8_nxv4i8(i8* %base, i64 %vl) {			define <vscale x 4 x i8> @test_vlseg8_nxv4i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv4i8:			; CHECK-LABEL: test_vlseg8_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg8e8.v v7, (a0)			; CHECK-NEXT: vlseg8e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg8.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg8.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg8_mask_nxv4i8(i8* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlseg8_mask_nxv4i8(i8* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv4i8:			; CHECK-LABEL: test_vlseg8_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg8e8.v v7, (a0)			; CHECK-NEXT: vlseg8e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg8.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg8.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg8.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlseg8.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg2.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg2.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg2.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg2.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i16> @test_vlseg2_nxv1i16(i16* %base, i64 %vl) {			define <vscale x 1 x i16> @test_vlseg2_nxv1i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv1i16:			; CHECK-LABEL: test_vlseg2_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg2.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg2.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg2_mask_nxv1i16(i16* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlseg2_mask_nxv1i16(i16* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv1i16:			; CHECK-LABEL: test_vlseg2_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg2.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg2.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg2.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg2.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg3.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg3.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg3.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg3.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i16> @test_vlseg3_nxv1i16(i16* %base, i64 %vl) {			define <vscale x 1 x i16> @test_vlseg3_nxv1i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv1i16:			; CHECK-LABEL: test_vlseg3_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg3.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg3.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg3_mask_nxv1i16(i16* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlseg3_mask_nxv1i16(i16* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv1i16:			; CHECK-LABEL: test_vlseg3_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg3.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg3.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg3.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg3.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg4.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg4.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg4.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg4.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i16> @test_vlseg4_nxv1i16(i16* %base, i64 %vl) {			define <vscale x 1 x i16> @test_vlseg4_nxv1i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv1i16:			; CHECK-LABEL: test_vlseg4_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg4.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg4.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg4_mask_nxv1i16(i16* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlseg4_mask_nxv1i16(i16* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv1i16:			; CHECK-LABEL: test_vlseg4_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg4.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg4.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg4.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg4.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg5.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg5.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg5.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg5.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i16> @test_vlseg5_nxv1i16(i16* %base, i64 %vl) {			define <vscale x 1 x i16> @test_vlseg5_nxv1i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv1i16:			; CHECK-LABEL: test_vlseg5_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg5.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg5.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg5_mask_nxv1i16(i16* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlseg5_mask_nxv1i16(i16* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv1i16:			; CHECK-LABEL: test_vlseg5_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg5.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg5.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg5.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg5.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg6.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg6.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg6.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg6.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i16> @test_vlseg6_nxv1i16(i16* %base, i64 %vl) {			define <vscale x 1 x i16> @test_vlseg6_nxv1i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv1i16:			; CHECK-LABEL: test_vlseg6_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg6.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg6.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg6_mask_nxv1i16(i16* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlseg6_mask_nxv1i16(i16* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv1i16:			; CHECK-LABEL: test_vlseg6_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg6.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg6.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg6.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg6.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg7.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg7.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg7.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg7.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i16> @test_vlseg7_nxv1i16(i16* %base, i64 %vl) {			define <vscale x 1 x i16> @test_vlseg7_nxv1i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv1i16:			; CHECK-LABEL: test_vlseg7_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg7.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg7.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg7_mask_nxv1i16(i16* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlseg7_mask_nxv1i16(i16* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv1i16:			; CHECK-LABEL: test_vlseg7_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg7.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg7.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg7.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg7.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg8.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg8.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg8.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg8.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i16> @test_vlseg8_nxv1i16(i16* %base, i64 %vl) {			define <vscale x 1 x i16> @test_vlseg8_nxv1i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv1i16:			; CHECK-LABEL: test_vlseg8_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg8.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg8.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg8_mask_nxv1i16(i16* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlseg8_mask_nxv1i16(i16* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv1i16:			; CHECK-LABEL: test_vlseg8_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg8.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg8.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg8.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlseg8.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i32> @test_vlseg2_nxv2i32(i32* %base, i64 %vl) {			define <vscale x 2 x i32> @test_vlseg2_nxv2i32(i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv2i32:			; CHECK-LABEL: test_vlseg2_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg2e32.v v7, (a0)			; CHECK-NEXT: vlseg2e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg2_mask_nxv2i32(i32* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlseg2_mask_nxv2i32(i32* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv2i32:			; CHECK-LABEL: test_vlseg2_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg2e32.v v7, (a0)			; CHECK-NEXT: vlseg2e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg3.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg3.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg3.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg3.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i32> @test_vlseg3_nxv2i32(i32* %base, i64 %vl) {			define <vscale x 2 x i32> @test_vlseg3_nxv2i32(i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv2i32:			; CHECK-LABEL: test_vlseg3_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg3e32.v v7, (a0)			; CHECK-NEXT: vlseg3e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg3.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg3.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg3_mask_nxv2i32(i32* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlseg3_mask_nxv2i32(i32* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv2i32:			; CHECK-LABEL: test_vlseg3_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg3e32.v v7, (a0)			; CHECK-NEXT: vlseg3e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg3.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg3.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg3.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg3.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg4.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg4.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg4.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg4.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i32> @test_vlseg4_nxv2i32(i32* %base, i64 %vl) {			define <vscale x 2 x i32> @test_vlseg4_nxv2i32(i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv2i32:			; CHECK-LABEL: test_vlseg4_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg4e32.v v7, (a0)			; CHECK-NEXT: vlseg4e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg4.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg4.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg4_mask_nxv2i32(i32* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlseg4_mask_nxv2i32(i32* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv2i32:			; CHECK-LABEL: test_vlseg4_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg4e32.v v7, (a0)			; CHECK-NEXT: vlseg4e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg4.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg4.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg4.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg4.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg5.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg5.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg5.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg5.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i32> @test_vlseg5_nxv2i32(i32* %base, i64 %vl) {			define <vscale x 2 x i32> @test_vlseg5_nxv2i32(i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv2i32:			; CHECK-LABEL: test_vlseg5_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg5e32.v v7, (a0)			; CHECK-NEXT: vlseg5e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg5.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg5.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg5_mask_nxv2i32(i32* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlseg5_mask_nxv2i32(i32* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv2i32:			; CHECK-LABEL: test_vlseg5_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg5e32.v v7, (a0)			; CHECK-NEXT: vlseg5e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg5.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg5.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg5.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg5.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg6.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg6.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg6.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg6.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i32> @test_vlseg6_nxv2i32(i32* %base, i64 %vl) {			define <vscale x 2 x i32> @test_vlseg6_nxv2i32(i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv2i32:			; CHECK-LABEL: test_vlseg6_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg6e32.v v7, (a0)			; CHECK-NEXT: vlseg6e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg6.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg6.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg6_mask_nxv2i32(i32* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlseg6_mask_nxv2i32(i32* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv2i32:			; CHECK-LABEL: test_vlseg6_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg6e32.v v7, (a0)			; CHECK-NEXT: vlseg6e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg6.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg6.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg6.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg6.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg7.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg7.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg7.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg7.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i32> @test_vlseg7_nxv2i32(i32* %base, i64 %vl) {			define <vscale x 2 x i32> @test_vlseg7_nxv2i32(i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv2i32:			; CHECK-LABEL: test_vlseg7_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg7e32.v v7, (a0)			; CHECK-NEXT: vlseg7e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg7.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg7.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg7_mask_nxv2i32(i32* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlseg7_mask_nxv2i32(i32* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv2i32:			; CHECK-LABEL: test_vlseg7_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg7e32.v v7, (a0)			; CHECK-NEXT: vlseg7e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg7.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg7.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg7.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg7.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg8.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg8.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg8.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg8.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i32> @test_vlseg8_nxv2i32(i32* %base, i64 %vl) {			define <vscale x 2 x i32> @test_vlseg8_nxv2i32(i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv2i32:			; CHECK-LABEL: test_vlseg8_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg8e32.v v7, (a0)			; CHECK-NEXT: vlseg8e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg8.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg8.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg8_mask_nxv2i32(i32* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlseg8_mask_nxv2i32(i32* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv2i32:			; CHECK-LABEL: test_vlseg8_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg8e32.v v7, (a0)			; CHECK-NEXT: vlseg8e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg8.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg8.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg8.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg8.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg2.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg2.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg2.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg2.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i8> @test_vlseg2_nxv8i8(i8* %base, i64 %vl) {			define <vscale x 8 x i8> @test_vlseg2_nxv8i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv8i8:			; CHECK-LABEL: test_vlseg2_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg2e8.v v7, (a0)			; CHECK-NEXT: vlseg2e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg2.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg2.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg2_mask_nxv8i8(i8* %base, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlseg2_mask_nxv8i8(i8* %base, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv8i8:			; CHECK-LABEL: test_vlseg2_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg2e8.v v7, (a0)			; CHECK-NEXT: vlseg2e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg2.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg2.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg2.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg2.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg3.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg3.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg3.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg3.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i8> @test_vlseg3_nxv8i8(i8* %base, i64 %vl) {			define <vscale x 8 x i8> @test_vlseg3_nxv8i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv8i8:			; CHECK-LABEL: test_vlseg3_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg3e8.v v7, (a0)			; CHECK-NEXT: vlseg3e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg3.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg3.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg3_mask_nxv8i8(i8* %base, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlseg3_mask_nxv8i8(i8* %base, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv8i8:			; CHECK-LABEL: test_vlseg3_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg3e8.v v7, (a0)			; CHECK-NEXT: vlseg3e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg3.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg3.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg3.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg3.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg4.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg4.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg4.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg4.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i8> @test_vlseg4_nxv8i8(i8* %base, i64 %vl) {			define <vscale x 8 x i8> @test_vlseg4_nxv8i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv8i8:			; CHECK-LABEL: test_vlseg4_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg4e8.v v7, (a0)			; CHECK-NEXT: vlseg4e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg4.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg4.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg4_mask_nxv8i8(i8* %base, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlseg4_mask_nxv8i8(i8* %base, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv8i8:			; CHECK-LABEL: test_vlseg4_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg4e8.v v7, (a0)			; CHECK-NEXT: vlseg4e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg4.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg4.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg4.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg4.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg5.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg5.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg5.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg5.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i8> @test_vlseg5_nxv8i8(i8* %base, i64 %vl) {			define <vscale x 8 x i8> @test_vlseg5_nxv8i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv8i8:			; CHECK-LABEL: test_vlseg5_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg5e8.v v7, (a0)			; CHECK-NEXT: vlseg5e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg5.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg5.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg5_mask_nxv8i8(i8* %base, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlseg5_mask_nxv8i8(i8* %base, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv8i8:			; CHECK-LABEL: test_vlseg5_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg5e8.v v7, (a0)			; CHECK-NEXT: vlseg5e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg5.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg5.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg5.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg5.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg6.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg6.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg6.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg6.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i8> @test_vlseg6_nxv8i8(i8* %base, i64 %vl) {			define <vscale x 8 x i8> @test_vlseg6_nxv8i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv8i8:			; CHECK-LABEL: test_vlseg6_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg6e8.v v7, (a0)			; CHECK-NEXT: vlseg6e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg6.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg6.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg6_mask_nxv8i8(i8* %base, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlseg6_mask_nxv8i8(i8* %base, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv8i8:			; CHECK-LABEL: test_vlseg6_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg6e8.v v7, (a0)			; CHECK-NEXT: vlseg6e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg6.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg6.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg6.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg6.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg7.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg7.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg7.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg7.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i8> @test_vlseg7_nxv8i8(i8* %base, i64 %vl) {			define <vscale x 8 x i8> @test_vlseg7_nxv8i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv8i8:			; CHECK-LABEL: test_vlseg7_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg7e8.v v7, (a0)			; CHECK-NEXT: vlseg7e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg7.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg7.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg7_mask_nxv8i8(i8* %base, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlseg7_mask_nxv8i8(i8* %base, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv8i8:			; CHECK-LABEL: test_vlseg7_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg7e8.v v7, (a0)			; CHECK-NEXT: vlseg7e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg7.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg7.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg7.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg7.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg8.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg8.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i8> @test_vlseg8_nxv8i8(i8* %base, i64 %vl) {			define <vscale x 8 x i8> @test_vlseg8_nxv8i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv8i8:			; CHECK-LABEL: test_vlseg8_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg8e8.v v7, (a0)			; CHECK-NEXT: vlseg8e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg8.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg8.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg8_mask_nxv8i8(i8* %base, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlseg8_mask_nxv8i8(i8* %base, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv8i8:			; CHECK-LABEL: test_vlseg8_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg8e8.v v7, (a0)			; CHECK-NEXT: vlseg8e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg8.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg8.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg8.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlseg8.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlseg2.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64* , i64)			declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlseg2.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64* , i64)
	declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlseg2.mask.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlseg2.mask.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i64> @test_vlseg2_nxv4i64(i64* %base, i64 %vl) {			define <vscale x 4 x i64> @test_vlseg2_nxv4i64(i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv4i64:			; CHECK-LABEL: test_vlseg2_nxv4i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
	; CHECK-NEXT: vlseg2e64.v v4, (a0)			; CHECK-NEXT: vlseg2e64.v v4, (a0)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlseg2.nxv4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlseg2.nxv4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1			%1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
	ret <vscale x 4 x i64> %1			ret <vscale x 4 x i64> %1
	}			}

	define <vscale x 4 x i64> @test_vlseg2_mask_nxv4i64(i64* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i64> @test_vlseg2_mask_nxv4i64(i64* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv4i64:			; CHECK-LABEL: test_vlseg2_mask_nxv4i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
	; CHECK-NEXT: vlseg2e64.v v4, (a0)			; CHECK-NEXT: vlseg2e64.v v4, (a0)
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlseg2e64.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e64.v v4, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlseg2.nxv4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlseg2.nxv4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0			%1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
	%2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlseg2.mask.nxv4i64(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlseg2.mask.nxv4i64(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1			%3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
	ret <vscale x 4 x i64> %3			ret <vscale x 4 x i64> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg2.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg2.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg2.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg2.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i16> @test_vlseg2_nxv4i16(i16* %base, i64 %vl) {			define <vscale x 4 x i16> @test_vlseg2_nxv4i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv4i16:			; CHECK-LABEL: test_vlseg2_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg2.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg2.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg2_mask_nxv4i16(i16* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlseg2_mask_nxv4i16(i16* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv4i16:			; CHECK-LABEL: test_vlseg2_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg2.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg2.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg2.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg2.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg3.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg3.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg3.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg3.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i16> @test_vlseg3_nxv4i16(i16* %base, i64 %vl) {			define <vscale x 4 x i16> @test_vlseg3_nxv4i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv4i16:			; CHECK-LABEL: test_vlseg3_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg3.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg3.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg3_mask_nxv4i16(i16* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlseg3_mask_nxv4i16(i16* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv4i16:			; CHECK-LABEL: test_vlseg3_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg3.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg3.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg3.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg3.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg4.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg4.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg4.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg4.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i16> @test_vlseg4_nxv4i16(i16* %base, i64 %vl) {			define <vscale x 4 x i16> @test_vlseg4_nxv4i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv4i16:			; CHECK-LABEL: test_vlseg4_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg4.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg4.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg4_mask_nxv4i16(i16* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlseg4_mask_nxv4i16(i16* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv4i16:			; CHECK-LABEL: test_vlseg4_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg4.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg4.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg4.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg4.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg5.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg5.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg5.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg5.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i16> @test_vlseg5_nxv4i16(i16* %base, i64 %vl) {			define <vscale x 4 x i16> @test_vlseg5_nxv4i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv4i16:			; CHECK-LABEL: test_vlseg5_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg5.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg5.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg5_mask_nxv4i16(i16* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlseg5_mask_nxv4i16(i16* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv4i16:			; CHECK-LABEL: test_vlseg5_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg5.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg5.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg5.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg5.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg6.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg6.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg6.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg6.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i16> @test_vlseg6_nxv4i16(i16* %base, i64 %vl) {			define <vscale x 4 x i16> @test_vlseg6_nxv4i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv4i16:			; CHECK-LABEL: test_vlseg6_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg6.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg6.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg6_mask_nxv4i16(i16* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlseg6_mask_nxv4i16(i16* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv4i16:			; CHECK-LABEL: test_vlseg6_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg6.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg6.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg6.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg6.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg7.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg7.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg7.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg7.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i16> @test_vlseg7_nxv4i16(i16* %base, i64 %vl) {			define <vscale x 4 x i16> @test_vlseg7_nxv4i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv4i16:			; CHECK-LABEL: test_vlseg7_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg7.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg7.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg7_mask_nxv4i16(i16* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlseg7_mask_nxv4i16(i16* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv4i16:			; CHECK-LABEL: test_vlseg7_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg7.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg7.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg7.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg7.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg8.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg8.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg8.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg8.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i16> @test_vlseg8_nxv4i16(i16* %base, i64 %vl) {			define <vscale x 4 x i16> @test_vlseg8_nxv4i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv4i16:			; CHECK-LABEL: test_vlseg8_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg8.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg8.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg8_mask_nxv4i16(i16* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlseg8_mask_nxv4i16(i16* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv4i16:			; CHECK-LABEL: test_vlseg8_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg8.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg8.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg8.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlseg8.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg2.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg2.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg2.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg2.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i8> @test_vlseg2_nxv1i8(i8* %base, i64 %vl) {			define <vscale x 1 x i8> @test_vlseg2_nxv1i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv1i8:			; CHECK-LABEL: test_vlseg2_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg2e8.v v7, (a0)			; CHECK-NEXT: vlseg2e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg2.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg2.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg2_mask_nxv1i8(i8* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlseg2_mask_nxv1i8(i8* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv1i8:			; CHECK-LABEL: test_vlseg2_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg2e8.v v7, (a0)			; CHECK-NEXT: vlseg2e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg2.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg2.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg2.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg2.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg3.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg3.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg3.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg3.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i8> @test_vlseg3_nxv1i8(i8* %base, i64 %vl) {			define <vscale x 1 x i8> @test_vlseg3_nxv1i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv1i8:			; CHECK-LABEL: test_vlseg3_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg3e8.v v7, (a0)			; CHECK-NEXT: vlseg3e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg3.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg3.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg3_mask_nxv1i8(i8* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlseg3_mask_nxv1i8(i8* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv1i8:			; CHECK-LABEL: test_vlseg3_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg3e8.v v7, (a0)			; CHECK-NEXT: vlseg3e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg3.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg3.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg3.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg3.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg4.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg4.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg4.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg4.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i8> @test_vlseg4_nxv1i8(i8* %base, i64 %vl) {			define <vscale x 1 x i8> @test_vlseg4_nxv1i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv1i8:			; CHECK-LABEL: test_vlseg4_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg4e8.v v7, (a0)			; CHECK-NEXT: vlseg4e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg4.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg4.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg4_mask_nxv1i8(i8* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlseg4_mask_nxv1i8(i8* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv1i8:			; CHECK-LABEL: test_vlseg4_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg4e8.v v7, (a0)			; CHECK-NEXT: vlseg4e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg4.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg4.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg4.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg4.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg5.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg5.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg5.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg5.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i8> @test_vlseg5_nxv1i8(i8* %base, i64 %vl) {			define <vscale x 1 x i8> @test_vlseg5_nxv1i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv1i8:			; CHECK-LABEL: test_vlseg5_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg5e8.v v7, (a0)			; CHECK-NEXT: vlseg5e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg5.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg5.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg5_mask_nxv1i8(i8* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlseg5_mask_nxv1i8(i8* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv1i8:			; CHECK-LABEL: test_vlseg5_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg5e8.v v7, (a0)			; CHECK-NEXT: vlseg5e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg5.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg5.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg5.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg5.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg6.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg6.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg6.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg6.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i8> @test_vlseg6_nxv1i8(i8* %base, i64 %vl) {			define <vscale x 1 x i8> @test_vlseg6_nxv1i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv1i8:			; CHECK-LABEL: test_vlseg6_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg6e8.v v7, (a0)			; CHECK-NEXT: vlseg6e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg6.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg6.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg6_mask_nxv1i8(i8* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlseg6_mask_nxv1i8(i8* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv1i8:			; CHECK-LABEL: test_vlseg6_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg6e8.v v7, (a0)			; CHECK-NEXT: vlseg6e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg6.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg6.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg6.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg6.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg7.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg7.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg7.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg7.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i8> @test_vlseg7_nxv1i8(i8* %base, i64 %vl) {			define <vscale x 1 x i8> @test_vlseg7_nxv1i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv1i8:			; CHECK-LABEL: test_vlseg7_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg7e8.v v7, (a0)			; CHECK-NEXT: vlseg7e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg7.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg7.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg7_mask_nxv1i8(i8* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlseg7_mask_nxv1i8(i8* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv1i8:			; CHECK-LABEL: test_vlseg7_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg7e8.v v7, (a0)			; CHECK-NEXT: vlseg7e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg7.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg7.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg7.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg7.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg8.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg8.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i8> @test_vlseg8_nxv1i8(i8* %base, i64 %vl) {			define <vscale x 1 x i8> @test_vlseg8_nxv1i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv1i8:			; CHECK-LABEL: test_vlseg8_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg8e8.v v7, (a0)			; CHECK-NEXT: vlseg8e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg8.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg8.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg8_mask_nxv1i8(i8* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlseg8_mask_nxv1i8(i8* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv1i8:			; CHECK-LABEL: test_vlseg8_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg8e8.v v7, (a0)			; CHECK-NEXT: vlseg8e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg8.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg8.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg8.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlseg8.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg2.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg2.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg2.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg2.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i8> @test_vlseg2_nxv2i8(i8* %base, i64 %vl) {			define <vscale x 2 x i8> @test_vlseg2_nxv2i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv2i8:			; CHECK-LABEL: test_vlseg2_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg2e8.v v7, (a0)			; CHECK-NEXT: vlseg2e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg2.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg2.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg2_mask_nxv2i8(i8* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlseg2_mask_nxv2i8(i8* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv2i8:			; CHECK-LABEL: test_vlseg2_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg2e8.v v7, (a0)			; CHECK-NEXT: vlseg2e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg2.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg2.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg2.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg2.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg3.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg3.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg3.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg3.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i8> @test_vlseg3_nxv2i8(i8* %base, i64 %vl) {			define <vscale x 2 x i8> @test_vlseg3_nxv2i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv2i8:			; CHECK-LABEL: test_vlseg3_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg3e8.v v7, (a0)			; CHECK-NEXT: vlseg3e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg3.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg3.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg3_mask_nxv2i8(i8* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlseg3_mask_nxv2i8(i8* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv2i8:			; CHECK-LABEL: test_vlseg3_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg3e8.v v7, (a0)			; CHECK-NEXT: vlseg3e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg3.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg3.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg3.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg3.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg4.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg4.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg4.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg4.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i8> @test_vlseg4_nxv2i8(i8* %base, i64 %vl) {			define <vscale x 2 x i8> @test_vlseg4_nxv2i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv2i8:			; CHECK-LABEL: test_vlseg4_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg4e8.v v7, (a0)			; CHECK-NEXT: vlseg4e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg4.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg4.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg4_mask_nxv2i8(i8* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlseg4_mask_nxv2i8(i8* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv2i8:			; CHECK-LABEL: test_vlseg4_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg4e8.v v7, (a0)			; CHECK-NEXT: vlseg4e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg4.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg4.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg4.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg4.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg5.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg5.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg5.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg5.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i8> @test_vlseg5_nxv2i8(i8* %base, i64 %vl) {			define <vscale x 2 x i8> @test_vlseg5_nxv2i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv2i8:			; CHECK-LABEL: test_vlseg5_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg5e8.v v7, (a0)			; CHECK-NEXT: vlseg5e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg5.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg5.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg5_mask_nxv2i8(i8* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlseg5_mask_nxv2i8(i8* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv2i8:			; CHECK-LABEL: test_vlseg5_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg5e8.v v7, (a0)			; CHECK-NEXT: vlseg5e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg5.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg5.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg5.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg5.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg6.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg6.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg6.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg6.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i8> @test_vlseg6_nxv2i8(i8* %base, i64 %vl) {			define <vscale x 2 x i8> @test_vlseg6_nxv2i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv2i8:			; CHECK-LABEL: test_vlseg6_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg6e8.v v7, (a0)			; CHECK-NEXT: vlseg6e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg6.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg6.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg6_mask_nxv2i8(i8* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlseg6_mask_nxv2i8(i8* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv2i8:			; CHECK-LABEL: test_vlseg6_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg6e8.v v7, (a0)			; CHECK-NEXT: vlseg6e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg6.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg6.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg6.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg6.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg7.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg7.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg7.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg7.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i8> @test_vlseg7_nxv2i8(i8* %base, i64 %vl) {			define <vscale x 2 x i8> @test_vlseg7_nxv2i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv2i8:			; CHECK-LABEL: test_vlseg7_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg7e8.v v7, (a0)			; CHECK-NEXT: vlseg7e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg7.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg7.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg7_mask_nxv2i8(i8* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlseg7_mask_nxv2i8(i8* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv2i8:			; CHECK-LABEL: test_vlseg7_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg7e8.v v7, (a0)			; CHECK-NEXT: vlseg7e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg7.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg7.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg7.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg7.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg8.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg8.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i8> @test_vlseg8_nxv2i8(i8* %base, i64 %vl) {			define <vscale x 2 x i8> @test_vlseg8_nxv2i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv2i8:			; CHECK-LABEL: test_vlseg8_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg8e8.v v7, (a0)			; CHECK-NEXT: vlseg8e8.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg8.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg8.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg8_mask_nxv2i8(i8* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlseg8_mask_nxv2i8(i8* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv2i8:			; CHECK-LABEL: test_vlseg8_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg8e8.v v7, (a0)			; CHECK-NEXT: vlseg8e8.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg8.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg8.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg8.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlseg8.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32* , i64)			declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32* , i64)
	declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i32> @test_vlseg2_nxv8i32(i32* %base, i64 %vl) {			define <vscale x 8 x i32> @test_vlseg2_nxv8i32(i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv8i32:			; CHECK-LABEL: test_vlseg2_nxv8i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vlseg2e32.v v4, (a0)			; CHECK-NEXT: vlseg2e32.v v4, (a0)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1			%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
	ret <vscale x 8 x i32> %1			ret <vscale x 8 x i32> %1
	}			}

	define <vscale x 8 x i32> @test_vlseg2_mask_nxv8i32(i32* %base, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i32> @test_vlseg2_mask_nxv8i32(i32* %base, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv8i32:			; CHECK-LABEL: test_vlseg2_mask_nxv8i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vlseg2e32.v v4, (a0)			; CHECK-NEXT: vlseg2e32.v v4, (a0)
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlseg2e32.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e32.v v4, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0			%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
	%2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.mask.nxv8i32(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.mask.nxv8i32(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1			%3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
	ret <vscale x 8 x i32> %3			ret <vscale x 8 x i32> %3
	}			}

	declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlseg2.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8* , i64)			declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlseg2.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8* , i64)
	declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlseg2.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i1>, i64, i64)			declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlseg2.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i1>, i64, i64)

	define <vscale x 32 x i8> @test_vlseg2_nxv32i8(i8* %base, i64 %vl) {			define <vscale x 32 x i8> @test_vlseg2_nxv32i8(i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv32i8:			; CHECK-LABEL: test_vlseg2_nxv32i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
	; CHECK-NEXT: vlseg2e8.v v4, (a0)			; CHECK-NEXT: vlseg2e8.v v4, (a0)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlseg2.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlseg2.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1			%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
	ret <vscale x 32 x i8> %1			ret <vscale x 32 x i8> %1
	}			}

	define <vscale x 32 x i8> @test_vlseg2_mask_nxv32i8(i8* %base, i64 %vl, <vscale x 32 x i1> %mask) {			define <vscale x 32 x i8> @test_vlseg2_mask_nxv32i8(i8* %base, i64 %vl, <vscale x 32 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv32i8:			; CHECK-LABEL: test_vlseg2_mask_nxv32i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
	; CHECK-NEXT: vlseg2e8.v v4, (a0)			; CHECK-NEXT: vlseg2e8.v v4, (a0)
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlseg2e8.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e8.v v4, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlseg2.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlseg2.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0			%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
	%2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlseg2.mask.nxv32i8(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 32 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlseg2.mask.nxv32i8(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, <vscale x 32 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1			%3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
	ret <vscale x 32 x i8> %3			ret <vscale x 32 x i8> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg2.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg2.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg2.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg2.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i16> @test_vlseg2_nxv2i16(i16* %base, i64 %vl) {			define <vscale x 2 x i16> @test_vlseg2_nxv2i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv2i16:			; CHECK-LABEL: test_vlseg2_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg2.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg2.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg2_mask_nxv2i16(i16* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlseg2_mask_nxv2i16(i16* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv2i16:			; CHECK-LABEL: test_vlseg2_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg2.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg2.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg2.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg2.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg3.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg3.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg3.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg3.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i16> @test_vlseg3_nxv2i16(i16* %base, i64 %vl) {			define <vscale x 2 x i16> @test_vlseg3_nxv2i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv2i16:			; CHECK-LABEL: test_vlseg3_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg3.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg3.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg3_mask_nxv2i16(i16* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlseg3_mask_nxv2i16(i16* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv2i16:			; CHECK-LABEL: test_vlseg3_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg3.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg3.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg3.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg3.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg4.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg4.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg4.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg4.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i16> @test_vlseg4_nxv2i16(i16* %base, i64 %vl) {			define <vscale x 2 x i16> @test_vlseg4_nxv2i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv2i16:			; CHECK-LABEL: test_vlseg4_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg4.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg4.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg4_mask_nxv2i16(i16* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlseg4_mask_nxv2i16(i16* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv2i16:			; CHECK-LABEL: test_vlseg4_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg4.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg4.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg4.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg4.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg5.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg5.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg5.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg5.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i16> @test_vlseg5_nxv2i16(i16* %base, i64 %vl) {			define <vscale x 2 x i16> @test_vlseg5_nxv2i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv2i16:			; CHECK-LABEL: test_vlseg5_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg5.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg5.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg5_mask_nxv2i16(i16* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlseg5_mask_nxv2i16(i16* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv2i16:			; CHECK-LABEL: test_vlseg5_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg5.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg5.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg5.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg5.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg6.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg6.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg6.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg6.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i16> @test_vlseg6_nxv2i16(i16* %base, i64 %vl) {			define <vscale x 2 x i16> @test_vlseg6_nxv2i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv2i16:			; CHECK-LABEL: test_vlseg6_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg6.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg6.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg6_mask_nxv2i16(i16* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlseg6_mask_nxv2i16(i16* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv2i16:			; CHECK-LABEL: test_vlseg6_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg6.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg6.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg6.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg6.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg7.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg7.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg7.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg7.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i16> @test_vlseg7_nxv2i16(i16* %base, i64 %vl) {			define <vscale x 2 x i16> @test_vlseg7_nxv2i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv2i16:			; CHECK-LABEL: test_vlseg7_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg7.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg7.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg7_mask_nxv2i16(i16* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlseg7_mask_nxv2i16(i16* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv2i16:			; CHECK-LABEL: test_vlseg7_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg7.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg7.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg7.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg7.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg8.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg8.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg8.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg8.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i16> @test_vlseg8_nxv2i16(i16* %base, i64 %vl) {			define <vscale x 2 x i16> @test_vlseg8_nxv2i16(i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv2i16:			; CHECK-LABEL: test_vlseg8_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg8.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg8.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg8_mask_nxv2i16(i16* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlseg8_mask_nxv2i16(i16* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv2i16:			; CHECK-LABEL: test_vlseg8_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg8.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg8.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg8.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlseg8.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg2.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64* , i64)			declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg2.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64* , i64)
	declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg2.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg2.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i64> @test_vlseg2_nxv2i64(i64* %base, i64 %vl) {			define <vscale x 2 x i64> @test_vlseg2_nxv2i64(i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv2i64:			; CHECK-LABEL: test_vlseg2_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg2e64.v v6, (a0)			; CHECK-NEXT: vlseg2e64.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg2.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg2.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1			%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
	ret <vscale x 2 x i64> %1			ret <vscale x 2 x i64> %1
	}			}

	define <vscale x 2 x i64> @test_vlseg2_mask_nxv2i64(i64* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i64> @test_vlseg2_mask_nxv2i64(i64* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv2i64:			; CHECK-LABEL: test_vlseg2_mask_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg2e64.v v6, (a0)			; CHECK-NEXT: vlseg2e64.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlseg2e64.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e64.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg2.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg2.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0			%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
	%2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg2.mask.nxv2i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg2.mask.nxv2i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1			%3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
	ret <vscale x 2 x i64> %3			ret <vscale x 2 x i64> %3
	}			}

	declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg3.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64* , i64)			declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg3.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64* , i64)
	declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg3.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg3.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i64> @test_vlseg3_nxv2i64(i64* %base, i64 %vl) {			define <vscale x 2 x i64> @test_vlseg3_nxv2i64(i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv2i64:			; CHECK-LABEL: test_vlseg3_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg3e64.v v6, (a0)			; CHECK-NEXT: vlseg3e64.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg3.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg3.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1			%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
	ret <vscale x 2 x i64> %1			ret <vscale x 2 x i64> %1
	}			}

	define <vscale x 2 x i64> @test_vlseg3_mask_nxv2i64(i64* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i64> @test_vlseg3_mask_nxv2i64(i64* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv2i64:			; CHECK-LABEL: test_vlseg3_mask_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg3e64.v v6, (a0)			; CHECK-NEXT: vlseg3e64.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlseg3e64.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e64.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg3.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg3.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0			%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
	%2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg3.mask.nxv2i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg3.mask.nxv2i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1			%3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
	ret <vscale x 2 x i64> %3			ret <vscale x 2 x i64> %3
	}			}

	declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg4.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64* , i64)			declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg4.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64* , i64)
	declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg4.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg4.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i64> @test_vlseg4_nxv2i64(i64* %base, i64 %vl) {			define <vscale x 2 x i64> @test_vlseg4_nxv2i64(i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv2i64:			; CHECK-LABEL: test_vlseg4_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg4e64.v v6, (a0)			; CHECK-NEXT: vlseg4e64.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg4.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg4.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1			%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
	ret <vscale x 2 x i64> %1			ret <vscale x 2 x i64> %1
	}			}

	define <vscale x 2 x i64> @test_vlseg4_mask_nxv2i64(i64* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i64> @test_vlseg4_mask_nxv2i64(i64* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv2i64:			; CHECK-LABEL: test_vlseg4_mask_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg4e64.v v6, (a0)			; CHECK-NEXT: vlseg4e64.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlseg4e64.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e64.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg4.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg4.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0			%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
	%2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg4.mask.nxv2i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlseg4.mask.nxv2i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1			%3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
	ret <vscale x 2 x i64> %3			ret <vscale x 2 x i64> %3
	}			}

	declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlseg2.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half* , i64)			declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlseg2.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half* , i64)
	declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlseg2.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i1>, i64, i64)			declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlseg2.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i1>, i64, i64)

	define <vscale x 16 x half> @test_vlseg2_nxv16f16(half* %base, i64 %vl) {			define <vscale x 16 x half> @test_vlseg2_nxv16f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv16f16:			; CHECK-LABEL: test_vlseg2_nxv16f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vlseg2e16.v v4, (a0)			; CHECK-NEXT: vlseg2e16.v v4, (a0)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlseg2.nxv16f16(<vscale x 16 x half> undef, <vscale x 16 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlseg2.nxv16f16(<vscale x 16 x half> undef, <vscale x 16 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1			%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
	ret <vscale x 16 x half> %1			ret <vscale x 16 x half> %1
	}			}

	define <vscale x 16 x half> @test_vlseg2_mask_nxv16f16(half* %base, i64 %vl, <vscale x 16 x i1> %mask) {			define <vscale x 16 x half> @test_vlseg2_mask_nxv16f16(half* %base, i64 %vl, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv16f16:			; CHECK-LABEL: test_vlseg2_mask_nxv16f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vlseg2e16.v v4, (a0)			; CHECK-NEXT: vlseg2e16.v v4, (a0)
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlseg2.nxv16f16(<vscale x 16 x half> undef, <vscale x 16 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlseg2.nxv16f16(<vscale x 16 x half> undef, <vscale x 16 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0			%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
	%2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlseg2.mask.nxv16f16(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlseg2.mask.nxv16f16(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1			%3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
	ret <vscale x 16 x half> %3			ret <vscale x 16 x half> %3
	}			}

	declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlseg2.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double* , i64)			declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlseg2.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double* , i64)
	declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlseg2.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlseg2.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x double> @test_vlseg2_nxv4f64(double* %base, i64 %vl) {			define <vscale x 4 x double> @test_vlseg2_nxv4f64(double* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv4f64:			; CHECK-LABEL: test_vlseg2_nxv4f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
	; CHECK-NEXT: vlseg2e64.v v4, (a0)			; CHECK-NEXT: vlseg2e64.v v4, (a0)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlseg2.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlseg2.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1			%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
	ret <vscale x 4 x double> %1			ret <vscale x 4 x double> %1
	}			}

	define <vscale x 4 x double> @test_vlseg2_mask_nxv4f64(double* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x double> @test_vlseg2_mask_nxv4f64(double* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv4f64:			; CHECK-LABEL: test_vlseg2_mask_nxv4f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
	; CHECK-NEXT: vlseg2e64.v v4, (a0)			; CHECK-NEXT: vlseg2e64.v v4, (a0)
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlseg2e64.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e64.v v4, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlseg2.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlseg2.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0			%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
	%2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlseg2.mask.nxv4f64(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlseg2.mask.nxv4f64(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1			%3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
	ret <vscale x 4 x double> %3			ret <vscale x 4 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg2.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg2.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
	declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg2.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg2.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x double> @test_vlseg2_nxv1f64(double* %base, i64 %vl) {			define <vscale x 1 x double> @test_vlseg2_nxv1f64(double* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv1f64:			; CHECK-LABEL: test_vlseg2_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg2e64.v v7, (a0)			; CHECK-NEXT: vlseg2e64.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg2.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg2.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg2_mask_nxv1f64(double* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlseg2_mask_nxv1f64(double* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv1f64:			; CHECK-LABEL: test_vlseg2_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg2e64.v v7, (a0)			; CHECK-NEXT: vlseg2e64.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e64.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e64.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg2.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg2.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg2.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg2.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg3.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg3.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg3.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg3.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x double> @test_vlseg3_nxv1f64(double* %base, i64 %vl) {			define <vscale x 1 x double> @test_vlseg3_nxv1f64(double* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv1f64:			; CHECK-LABEL: test_vlseg3_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg3e64.v v7, (a0)			; CHECK-NEXT: vlseg3e64.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg3.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg3.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg3_mask_nxv1f64(double* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlseg3_mask_nxv1f64(double* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv1f64:			; CHECK-LABEL: test_vlseg3_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg3e64.v v7, (a0)			; CHECK-NEXT: vlseg3e64.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e64.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e64.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg3.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg3.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg3.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg3.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg4.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg4.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg4.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg4.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x double> @test_vlseg4_nxv1f64(double* %base, i64 %vl) {			define <vscale x 1 x double> @test_vlseg4_nxv1f64(double* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv1f64:			; CHECK-LABEL: test_vlseg4_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg4e64.v v7, (a0)			; CHECK-NEXT: vlseg4e64.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg4.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg4.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg4_mask_nxv1f64(double* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlseg4_mask_nxv1f64(double* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv1f64:			; CHECK-LABEL: test_vlseg4_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg4e64.v v7, (a0)			; CHECK-NEXT: vlseg4e64.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e64.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e64.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg4.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg4.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg4.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg4.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg5.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg5.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg5.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg5.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x double> @test_vlseg5_nxv1f64(double* %base, i64 %vl) {			define <vscale x 1 x double> @test_vlseg5_nxv1f64(double* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv1f64:			; CHECK-LABEL: test_vlseg5_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg5e64.v v7, (a0)			; CHECK-NEXT: vlseg5e64.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg5.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg5.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg5_mask_nxv1f64(double* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlseg5_mask_nxv1f64(double* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv1f64:			; CHECK-LABEL: test_vlseg5_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg5e64.v v7, (a0)			; CHECK-NEXT: vlseg5e64.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e64.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e64.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg5.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg5.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg5.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg5.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg6.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg6.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg6.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg6.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x double> @test_vlseg6_nxv1f64(double* %base, i64 %vl) {			define <vscale x 1 x double> @test_vlseg6_nxv1f64(double* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv1f64:			; CHECK-LABEL: test_vlseg6_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg6e64.v v7, (a0)			; CHECK-NEXT: vlseg6e64.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg6.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg6.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg6_mask_nxv1f64(double* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlseg6_mask_nxv1f64(double* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv1f64:			; CHECK-LABEL: test_vlseg6_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg6e64.v v7, (a0)			; CHECK-NEXT: vlseg6e64.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e64.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e64.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg6.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg6.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg6.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg6.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg7.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg7.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg7.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg7.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x double> @test_vlseg7_nxv1f64(double* %base, i64 %vl) {			define <vscale x 1 x double> @test_vlseg7_nxv1f64(double* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv1f64:			; CHECK-LABEL: test_vlseg7_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg7e64.v v7, (a0)			; CHECK-NEXT: vlseg7e64.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg7.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg7.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg7_mask_nxv1f64(double* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlseg7_mask_nxv1f64(double* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv1f64:			; CHECK-LABEL: test_vlseg7_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg7e64.v v7, (a0)			; CHECK-NEXT: vlseg7e64.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e64.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e64.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg7.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg7.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg7.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg7.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg8.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg8.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg8.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg8.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x double> @test_vlseg8_nxv1f64(double* %base, i64 %vl) {			define <vscale x 1 x double> @test_vlseg8_nxv1f64(double* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv1f64:			; CHECK-LABEL: test_vlseg8_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg8e64.v v7, (a0)			; CHECK-NEXT: vlseg8e64.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg8.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg8.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg8_mask_nxv1f64(double* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlseg8_mask_nxv1f64(double* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv1f64:			; CHECK-LABEL: test_vlseg8_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg8e64.v v7, (a0)			; CHECK-NEXT: vlseg8e64.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e64.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e64.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg8.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg8.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg8.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlseg8.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg2.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg2.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
	declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg2.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg2.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x float> @test_vlseg2_nxv2f32(float* %base, i64 %vl) {			define <vscale x 2 x float> @test_vlseg2_nxv2f32(float* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv2f32:			; CHECK-LABEL: test_vlseg2_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg2e32.v v7, (a0)			; CHECK-NEXT: vlseg2e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg2.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg2.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg2_mask_nxv2f32(float* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlseg2_mask_nxv2f32(float* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv2f32:			; CHECK-LABEL: test_vlseg2_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg2e32.v v7, (a0)			; CHECK-NEXT: vlseg2e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg2.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg2.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg2.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg2.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg3.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg3.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg3.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg3.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x float> @test_vlseg3_nxv2f32(float* %base, i64 %vl) {			define <vscale x 2 x float> @test_vlseg3_nxv2f32(float* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv2f32:			; CHECK-LABEL: test_vlseg3_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg3e32.v v7, (a0)			; CHECK-NEXT: vlseg3e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg3.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg3.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg3_mask_nxv2f32(float* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlseg3_mask_nxv2f32(float* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv2f32:			; CHECK-LABEL: test_vlseg3_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg3e32.v v7, (a0)			; CHECK-NEXT: vlseg3e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg3.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg3.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg3.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg3.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg4.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg4.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg4.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg4.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x float> @test_vlseg4_nxv2f32(float* %base, i64 %vl) {			define <vscale x 2 x float> @test_vlseg4_nxv2f32(float* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv2f32:			; CHECK-LABEL: test_vlseg4_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg4e32.v v7, (a0)			; CHECK-NEXT: vlseg4e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg4.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg4.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg4_mask_nxv2f32(float* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlseg4_mask_nxv2f32(float* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv2f32:			; CHECK-LABEL: test_vlseg4_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg4e32.v v7, (a0)			; CHECK-NEXT: vlseg4e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg4.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg4.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg4.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg4.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg5.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg5.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg5.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg5.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x float> @test_vlseg5_nxv2f32(float* %base, i64 %vl) {			define <vscale x 2 x float> @test_vlseg5_nxv2f32(float* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv2f32:			; CHECK-LABEL: test_vlseg5_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg5e32.v v7, (a0)			; CHECK-NEXT: vlseg5e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg5.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg5.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg5_mask_nxv2f32(float* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlseg5_mask_nxv2f32(float* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv2f32:			; CHECK-LABEL: test_vlseg5_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg5e32.v v7, (a0)			; CHECK-NEXT: vlseg5e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg5.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg5.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg5.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg5.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg6.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg6.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg6.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg6.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x float> @test_vlseg6_nxv2f32(float* %base, i64 %vl) {			define <vscale x 2 x float> @test_vlseg6_nxv2f32(float* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv2f32:			; CHECK-LABEL: test_vlseg6_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg6e32.v v7, (a0)			; CHECK-NEXT: vlseg6e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg6.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg6.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg6_mask_nxv2f32(float* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlseg6_mask_nxv2f32(float* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv2f32:			; CHECK-LABEL: test_vlseg6_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg6e32.v v7, (a0)			; CHECK-NEXT: vlseg6e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg6.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg6.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg6.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg6.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg7.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg7.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg7.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg7.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x float> @test_vlseg7_nxv2f32(float* %base, i64 %vl) {			define <vscale x 2 x float> @test_vlseg7_nxv2f32(float* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv2f32:			; CHECK-LABEL: test_vlseg7_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg7e32.v v7, (a0)			; CHECK-NEXT: vlseg7e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg7.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg7.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg7_mask_nxv2f32(float* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlseg7_mask_nxv2f32(float* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv2f32:			; CHECK-LABEL: test_vlseg7_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg7e32.v v7, (a0)			; CHECK-NEXT: vlseg7e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg7.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg7.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg7.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg7.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg8.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg8.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg8.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg8.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x float> @test_vlseg8_nxv2f32(float* %base, i64 %vl) {			define <vscale x 2 x float> @test_vlseg8_nxv2f32(float* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv2f32:			; CHECK-LABEL: test_vlseg8_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg8e32.v v7, (a0)			; CHECK-NEXT: vlseg8e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg8.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg8.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg8_mask_nxv2f32(float* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlseg8_mask_nxv2f32(float* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv2f32:			; CHECK-LABEL: test_vlseg8_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg8e32.v v7, (a0)			; CHECK-NEXT: vlseg8e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg8.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg8.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg8.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlseg8.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg2.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg2.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
	declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg2.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg2.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x half> @test_vlseg2_nxv1f16(half* %base, i64 %vl) {			define <vscale x 1 x half> @test_vlseg2_nxv1f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv1f16:			; CHECK-LABEL: test_vlseg2_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg2.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg2.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg2_mask_nxv1f16(half* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlseg2_mask_nxv1f16(half* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv1f16:			; CHECK-LABEL: test_vlseg2_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg2.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg2.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg2.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg2.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg3.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg3.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg3.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg3.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x half> @test_vlseg3_nxv1f16(half* %base, i64 %vl) {			define <vscale x 1 x half> @test_vlseg3_nxv1f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv1f16:			; CHECK-LABEL: test_vlseg3_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg3.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg3.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg3_mask_nxv1f16(half* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlseg3_mask_nxv1f16(half* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv1f16:			; CHECK-LABEL: test_vlseg3_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg3.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg3.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg3.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg3.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg4.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg4.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg4.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg4.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x half> @test_vlseg4_nxv1f16(half* %base, i64 %vl) {			define <vscale x 1 x half> @test_vlseg4_nxv1f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv1f16:			; CHECK-LABEL: test_vlseg4_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg4.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg4.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg4_mask_nxv1f16(half* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlseg4_mask_nxv1f16(half* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv1f16:			; CHECK-LABEL: test_vlseg4_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg4.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg4.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg4.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg4.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg5.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg5.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg5.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg5.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x half> @test_vlseg5_nxv1f16(half* %base, i64 %vl) {			define <vscale x 1 x half> @test_vlseg5_nxv1f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv1f16:			; CHECK-LABEL: test_vlseg5_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg5.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg5.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg5_mask_nxv1f16(half* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlseg5_mask_nxv1f16(half* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv1f16:			; CHECK-LABEL: test_vlseg5_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg5.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg5.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg5.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg5.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg6.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg6.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg6.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg6.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x half> @test_vlseg6_nxv1f16(half* %base, i64 %vl) {			define <vscale x 1 x half> @test_vlseg6_nxv1f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv1f16:			; CHECK-LABEL: test_vlseg6_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg6.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg6.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg6_mask_nxv1f16(half* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlseg6_mask_nxv1f16(half* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv1f16:			; CHECK-LABEL: test_vlseg6_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg6.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg6.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg6.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg6.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg7.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg7.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg7.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg7.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x half> @test_vlseg7_nxv1f16(half* %base, i64 %vl) {			define <vscale x 1 x half> @test_vlseg7_nxv1f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv1f16:			; CHECK-LABEL: test_vlseg7_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg7.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg7.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg7_mask_nxv1f16(half* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlseg7_mask_nxv1f16(half* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv1f16:			; CHECK-LABEL: test_vlseg7_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg7.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg7.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg7.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg7.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg8.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg8.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg8.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg8.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x half> @test_vlseg8_nxv1f16(half* %base, i64 %vl) {			define <vscale x 1 x half> @test_vlseg8_nxv1f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv1f16:			; CHECK-LABEL: test_vlseg8_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg8.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg8.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg8_mask_nxv1f16(half* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlseg8_mask_nxv1f16(half* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv1f16:			; CHECK-LABEL: test_vlseg8_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg8.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg8.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg8.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlseg8.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg2.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg2.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
	declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg2.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg2.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x float> @test_vlseg2_nxv1f32(float* %base, i64 %vl) {			define <vscale x 1 x float> @test_vlseg2_nxv1f32(float* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv1f32:			; CHECK-LABEL: test_vlseg2_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg2e32.v v7, (a0)			; CHECK-NEXT: vlseg2e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg2.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg2.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg2_mask_nxv1f32(float* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlseg2_mask_nxv1f32(float* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv1f32:			; CHECK-LABEL: test_vlseg2_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg2e32.v v7, (a0)			; CHECK-NEXT: vlseg2e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg2.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg2.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg2.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg2.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg3.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg3.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg3.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg3.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x float> @test_vlseg3_nxv1f32(float* %base, i64 %vl) {			define <vscale x 1 x float> @test_vlseg3_nxv1f32(float* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv1f32:			; CHECK-LABEL: test_vlseg3_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg3e32.v v7, (a0)			; CHECK-NEXT: vlseg3e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg3.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg3.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg3_mask_nxv1f32(float* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlseg3_mask_nxv1f32(float* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv1f32:			; CHECK-LABEL: test_vlseg3_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg3e32.v v7, (a0)			; CHECK-NEXT: vlseg3e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg3.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg3.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg3.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg3.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg4.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg4.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg4.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg4.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x float> @test_vlseg4_nxv1f32(float* %base, i64 %vl) {			define <vscale x 1 x float> @test_vlseg4_nxv1f32(float* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv1f32:			; CHECK-LABEL: test_vlseg4_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg4e32.v v7, (a0)			; CHECK-NEXT: vlseg4e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg4.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg4.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg4_mask_nxv1f32(float* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlseg4_mask_nxv1f32(float* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv1f32:			; CHECK-LABEL: test_vlseg4_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg4e32.v v7, (a0)			; CHECK-NEXT: vlseg4e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg4.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg4.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg4.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg4.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg5.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg5.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg5.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg5.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x float> @test_vlseg5_nxv1f32(float* %base, i64 %vl) {			define <vscale x 1 x float> @test_vlseg5_nxv1f32(float* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv1f32:			; CHECK-LABEL: test_vlseg5_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg5e32.v v7, (a0)			; CHECK-NEXT: vlseg5e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg5.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg5.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg5_mask_nxv1f32(float* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlseg5_mask_nxv1f32(float* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv1f32:			; CHECK-LABEL: test_vlseg5_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg5e32.v v7, (a0)			; CHECK-NEXT: vlseg5e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg5.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg5.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg5.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg5.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg6.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg6.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg6.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg6.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x float> @test_vlseg6_nxv1f32(float* %base, i64 %vl) {			define <vscale x 1 x float> @test_vlseg6_nxv1f32(float* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv1f32:			; CHECK-LABEL: test_vlseg6_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg6e32.v v7, (a0)			; CHECK-NEXT: vlseg6e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg6.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg6.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg6_mask_nxv1f32(float* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlseg6_mask_nxv1f32(float* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv1f32:			; CHECK-LABEL: test_vlseg6_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg6e32.v v7, (a0)			; CHECK-NEXT: vlseg6e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg6.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg6.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg6.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg6.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg7.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg7.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg7.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg7.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x float> @test_vlseg7_nxv1f32(float* %base, i64 %vl) {			define <vscale x 1 x float> @test_vlseg7_nxv1f32(float* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv1f32:			; CHECK-LABEL: test_vlseg7_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg7e32.v v7, (a0)			; CHECK-NEXT: vlseg7e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg7.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg7.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg7_mask_nxv1f32(float* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlseg7_mask_nxv1f32(float* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv1f32:			; CHECK-LABEL: test_vlseg7_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg7e32.v v7, (a0)			; CHECK-NEXT: vlseg7e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg7.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg7.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg7.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg7.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg8.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg8.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg8.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg8.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x float> @test_vlseg8_nxv1f32(float* %base, i64 %vl) {			define <vscale x 1 x float> @test_vlseg8_nxv1f32(float* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv1f32:			; CHECK-LABEL: test_vlseg8_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg8e32.v v7, (a0)			; CHECK-NEXT: vlseg8e32.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg8.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg8.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg8_mask_nxv1f32(float* %base, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlseg8_mask_nxv1f32(float* %base, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv1f32:			; CHECK-LABEL: test_vlseg8_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg8e32.v v7, (a0)			; CHECK-NEXT: vlseg8e32.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg8.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg8.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg8.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlseg8.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg2.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half* , i64)			declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg2.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half* , i64)
	declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg2.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg2.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x half> @test_vlseg2_nxv8f16(half* %base, i64 %vl) {			define <vscale x 8 x half> @test_vlseg2_nxv8f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv8f16:			; CHECK-LABEL: test_vlseg2_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg2e16.v v6, (a0)			; CHECK-NEXT: vlseg2e16.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg2.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg2.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	define <vscale x 8 x half> @test_vlseg2_mask_nxv8f16(half* %base, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x half> @test_vlseg2_mask_nxv8f16(half* %base, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv8f16:			; CHECK-LABEL: test_vlseg2_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg2e16.v v6, (a0)			; CHECK-NEXT: vlseg2e16.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlseg2e16.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e16.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg2.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg2.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
	%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg2.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg2.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1			%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
	ret <vscale x 8 x half> %3			ret <vscale x 8 x half> %3
	}			}

	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg3.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i64)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg3.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i64)
	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg3.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg3.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x half> @test_vlseg3_nxv8f16(half* %base, i64 %vl) {			define <vscale x 8 x half> @test_vlseg3_nxv8f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv8f16:			; CHECK-LABEL: test_vlseg3_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg3e16.v v6, (a0)			; CHECK-NEXT: vlseg3e16.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg3.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg3.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	define <vscale x 8 x half> @test_vlseg3_mask_nxv8f16(half* %base, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x half> @test_vlseg3_mask_nxv8f16(half* %base, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv8f16:			; CHECK-LABEL: test_vlseg3_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg3e16.v v6, (a0)			; CHECK-NEXT: vlseg3e16.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlseg3e16.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e16.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg3.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg3.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
	%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg3.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg3.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1			%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
	ret <vscale x 8 x half> %3			ret <vscale x 8 x half> %3
	}			}

	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg4.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i64)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg4.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i64)
	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg4.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg4.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x half> @test_vlseg4_nxv8f16(half* %base, i64 %vl) {			define <vscale x 8 x half> @test_vlseg4_nxv8f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv8f16:			; CHECK-LABEL: test_vlseg4_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg4e16.v v6, (a0)			; CHECK-NEXT: vlseg4e16.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg4.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg4.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	define <vscale x 8 x half> @test_vlseg4_mask_nxv8f16(half* %base, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x half> @test_vlseg4_mask_nxv8f16(half* %base, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv8f16:			; CHECK-LABEL: test_vlseg4_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg4e16.v v6, (a0)			; CHECK-NEXT: vlseg4e16.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlseg4e16.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e16.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg4.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg4.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
	%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg4.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlseg4.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1			%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
	ret <vscale x 8 x half> %3			ret <vscale x 8 x half> %3
	}			}

	declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlseg2.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float* , i64)			declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlseg2.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float* , i64)
	declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlseg2.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlseg2.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x float> @test_vlseg2_nxv8f32(float* %base, i64 %vl) {			define <vscale x 8 x float> @test_vlseg2_nxv8f32(float* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv8f32:			; CHECK-LABEL: test_vlseg2_nxv8f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vlseg2e32.v v4, (a0)			; CHECK-NEXT: vlseg2e32.v v4, (a0)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlseg2.nxv8f32(<vscale x 8 x float> undef, <vscale x 8 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlseg2.nxv8f32(<vscale x 8 x float> undef, <vscale x 8 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1			%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
	ret <vscale x 8 x float> %1			ret <vscale x 8 x float> %1
	}			}

	define <vscale x 8 x float> @test_vlseg2_mask_nxv8f32(float* %base, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x float> @test_vlseg2_mask_nxv8f32(float* %base, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv8f32:			; CHECK-LABEL: test_vlseg2_mask_nxv8f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vlseg2e32.v v4, (a0)			; CHECK-NEXT: vlseg2e32.v v4, (a0)
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlseg2e32.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e32.v v4, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlseg2.nxv8f32(<vscale x 8 x float> undef, <vscale x 8 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlseg2.nxv8f32(<vscale x 8 x float> undef, <vscale x 8 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0			%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
	%2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlseg2.mask.nxv8f32(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlseg2.mask.nxv8f32(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1			%3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
	ret <vscale x 8 x float> %3			ret <vscale x 8 x float> %3
	}			}

	declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg2.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double* , i64)			declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg2.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double* , i64)
	declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg2.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg2.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x double> @test_vlseg2_nxv2f64(double* %base, i64 %vl) {			define <vscale x 2 x double> @test_vlseg2_nxv2f64(double* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv2f64:			; CHECK-LABEL: test_vlseg2_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg2e64.v v6, (a0)			; CHECK-NEXT: vlseg2e64.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg2.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg2.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	define <vscale x 2 x double> @test_vlseg2_mask_nxv2f64(double* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x double> @test_vlseg2_mask_nxv2f64(double* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv2f64:			; CHECK-LABEL: test_vlseg2_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg2e64.v v6, (a0)			; CHECK-NEXT: vlseg2e64.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlseg2e64.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e64.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg2.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg2.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
	%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg2.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg2.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1			%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
	ret <vscale x 2 x double> %3			ret <vscale x 2 x double> %3
	}			}

	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg3.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i64)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg3.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i64)
	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg3.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg3.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x double> @test_vlseg3_nxv2f64(double* %base, i64 %vl) {			define <vscale x 2 x double> @test_vlseg3_nxv2f64(double* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv2f64:			; CHECK-LABEL: test_vlseg3_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg3e64.v v6, (a0)			; CHECK-NEXT: vlseg3e64.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg3.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg3.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	define <vscale x 2 x double> @test_vlseg3_mask_nxv2f64(double* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x double> @test_vlseg3_mask_nxv2f64(double* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv2f64:			; CHECK-LABEL: test_vlseg3_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg3e64.v v6, (a0)			; CHECK-NEXT: vlseg3e64.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlseg3e64.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e64.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg3.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg3.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
	%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg3.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg3.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1			%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
	ret <vscale x 2 x double> %3			ret <vscale x 2 x double> %3
	}			}

	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg4.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i64)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg4.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i64)
	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg4.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg4.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x double> @test_vlseg4_nxv2f64(double* %base, i64 %vl) {			define <vscale x 2 x double> @test_vlseg4_nxv2f64(double* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv2f64:			; CHECK-LABEL: test_vlseg4_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg4e64.v v6, (a0)			; CHECK-NEXT: vlseg4e64.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg4.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg4.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	define <vscale x 2 x double> @test_vlseg4_mask_nxv2f64(double* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x double> @test_vlseg4_mask_nxv2f64(double* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv2f64:			; CHECK-LABEL: test_vlseg4_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg4e64.v v6, (a0)			; CHECK-NEXT: vlseg4e64.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlseg4e64.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e64.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg4.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg4.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
	%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg4.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlseg4.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1			%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
	ret <vscale x 2 x double> %3			ret <vscale x 2 x double> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg2.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg2.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
	declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg2.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg2.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x half> @test_vlseg2_nxv4f16(half* %base, i64 %vl) {			define <vscale x 4 x half> @test_vlseg2_nxv4f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv4f16:			; CHECK-LABEL: test_vlseg2_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg2.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg2.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg2_mask_nxv4f16(half* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlseg2_mask_nxv4f16(half* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv4f16:			; CHECK-LABEL: test_vlseg2_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg2.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg2.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg2.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg2.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg3.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg3.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg3.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg3.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x half> @test_vlseg3_nxv4f16(half* %base, i64 %vl) {			define <vscale x 4 x half> @test_vlseg3_nxv4f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv4f16:			; CHECK-LABEL: test_vlseg3_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg3.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg3.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg3_mask_nxv4f16(half* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlseg3_mask_nxv4f16(half* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv4f16:			; CHECK-LABEL: test_vlseg3_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg3.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg3.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg3.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg3.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg4.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg4.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg4.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg4.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x half> @test_vlseg4_nxv4f16(half* %base, i64 %vl) {			define <vscale x 4 x half> @test_vlseg4_nxv4f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv4f16:			; CHECK-LABEL: test_vlseg4_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg4.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg4.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg4_mask_nxv4f16(half* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlseg4_mask_nxv4f16(half* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv4f16:			; CHECK-LABEL: test_vlseg4_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg4.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg4.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg4.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg4.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg5.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg5.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg5.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg5.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x half> @test_vlseg5_nxv4f16(half* %base, i64 %vl) {			define <vscale x 4 x half> @test_vlseg5_nxv4f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv4f16:			; CHECK-LABEL: test_vlseg5_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg5.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg5.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg5_mask_nxv4f16(half* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlseg5_mask_nxv4f16(half* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv4f16:			; CHECK-LABEL: test_vlseg5_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg5.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg5.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg5.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg5.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg6.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg6.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg6.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg6.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x half> @test_vlseg6_nxv4f16(half* %base, i64 %vl) {			define <vscale x 4 x half> @test_vlseg6_nxv4f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv4f16:			; CHECK-LABEL: test_vlseg6_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg6.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg6.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg6_mask_nxv4f16(half* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlseg6_mask_nxv4f16(half* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv4f16:			; CHECK-LABEL: test_vlseg6_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg6.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg6.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg6.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg6.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg7.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg7.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg7.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg7.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x half> @test_vlseg7_nxv4f16(half* %base, i64 %vl) {			define <vscale x 4 x half> @test_vlseg7_nxv4f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv4f16:			; CHECK-LABEL: test_vlseg7_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg7.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg7.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg7_mask_nxv4f16(half* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlseg7_mask_nxv4f16(half* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv4f16:			; CHECK-LABEL: test_vlseg7_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg7.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg7.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg7.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg7.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg8.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg8.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg8.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg8.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x half> @test_vlseg8_nxv4f16(half* %base, i64 %vl) {			define <vscale x 4 x half> @test_vlseg8_nxv4f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv4f16:			; CHECK-LABEL: test_vlseg8_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg8.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg8.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg8_mask_nxv4f16(half* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlseg8_mask_nxv4f16(half* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv4f16:			; CHECK-LABEL: test_vlseg8_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg8.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg8.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg8.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlseg8.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg2.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg2.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
	declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg2.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg2.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x half> @test_vlseg2_nxv2f16(half* %base, i64 %vl) {			define <vscale x 2 x half> @test_vlseg2_nxv2f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv2f16:			; CHECK-LABEL: test_vlseg2_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg2.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg2.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg2_mask_nxv2f16(half* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlseg2_mask_nxv2f16(half* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv2f16:			; CHECK-LABEL: test_vlseg2_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg2e16.v v7, (a0)			; CHECK-NEXT: vlseg2e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg2.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg2.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg2.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg2.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg3.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg3.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg3.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg3.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x half> @test_vlseg3_nxv2f16(half* %base, i64 %vl) {			define <vscale x 2 x half> @test_vlseg3_nxv2f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv2f16:			; CHECK-LABEL: test_vlseg3_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg3.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg3.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg3_mask_nxv2f16(half* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlseg3_mask_nxv2f16(half* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv2f16:			; CHECK-LABEL: test_vlseg3_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg3e16.v v7, (a0)			; CHECK-NEXT: vlseg3e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg3.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg3.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg3.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg3.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg4.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg4.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg4.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg4.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x half> @test_vlseg4_nxv2f16(half* %base, i64 %vl) {			define <vscale x 2 x half> @test_vlseg4_nxv2f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv2f16:			; CHECK-LABEL: test_vlseg4_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg4.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg4.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg4_mask_nxv2f16(half* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlseg4_mask_nxv2f16(half* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv2f16:			; CHECK-LABEL: test_vlseg4_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg4e16.v v7, (a0)			; CHECK-NEXT: vlseg4e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg4.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg4.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg4.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg4.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg5.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg5.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg5.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg5.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x half> @test_vlseg5_nxv2f16(half* %base, i64 %vl) {			define <vscale x 2 x half> @test_vlseg5_nxv2f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg5_nxv2f16:			; CHECK-LABEL: test_vlseg5_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg5.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg5.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg5_mask_nxv2f16(half* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlseg5_mask_nxv2f16(half* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg5_mask_nxv2f16:			; CHECK-LABEL: test_vlseg5_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg5e16.v v7, (a0)			; CHECK-NEXT: vlseg5e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg5.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg5.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg5.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg5.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg6.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg6.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg6.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg6.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x half> @test_vlseg6_nxv2f16(half* %base, i64 %vl) {			define <vscale x 2 x half> @test_vlseg6_nxv2f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg6_nxv2f16:			; CHECK-LABEL: test_vlseg6_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg6.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg6.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg6_mask_nxv2f16(half* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlseg6_mask_nxv2f16(half* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg6_mask_nxv2f16:			; CHECK-LABEL: test_vlseg6_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg6e16.v v7, (a0)			; CHECK-NEXT: vlseg6e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg6.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg6.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg6.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg6.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg7.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg7.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg7.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg7.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x half> @test_vlseg7_nxv2f16(half* %base, i64 %vl) {			define <vscale x 2 x half> @test_vlseg7_nxv2f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg7_nxv2f16:			; CHECK-LABEL: test_vlseg7_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg7.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg7.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg7_mask_nxv2f16(half* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlseg7_mask_nxv2f16(half* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg7_mask_nxv2f16:			; CHECK-LABEL: test_vlseg7_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg7e16.v v7, (a0)			; CHECK-NEXT: vlseg7e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg7.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg7.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg7.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg7.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg8.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg8.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg8.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg8.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x half> @test_vlseg8_nxv2f16(half* %base, i64 %vl) {			define <vscale x 2 x half> @test_vlseg8_nxv2f16(half* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg8_nxv2f16:			; CHECK-LABEL: test_vlseg8_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg8.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg8.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg8_mask_nxv2f16(half* %base, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlseg8_mask_nxv2f16(half* %base, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlseg8_mask_nxv2f16:			; CHECK-LABEL: test_vlseg8_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg8e16.v v7, (a0)			; CHECK-NEXT: vlseg8e16.v v7, (a0)
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg8.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg8.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg8.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlseg8.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg2.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float* , i64)			declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg2.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float* , i64)
	declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg2.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg2.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x float> @test_vlseg2_nxv4f32(float* %base, i64 %vl) {			define <vscale x 4 x float> @test_vlseg2_nxv4f32(float* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg2_nxv4f32:			; CHECK-LABEL: test_vlseg2_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg2e32.v v6, (a0)			; CHECK-NEXT: vlseg2e32.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg2.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg2.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	define <vscale x 4 x float> @test_vlseg2_mask_nxv4f32(float* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x float> @test_vlseg2_mask_nxv4f32(float* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv4f32:			; CHECK-LABEL: test_vlseg2_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg2e32.v v6, (a0)			; CHECK-NEXT: vlseg2e32.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlseg2e32.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e32.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg2.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg2.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
	%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg2.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg2.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1			%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
	ret <vscale x 4 x float> %3			ret <vscale x 4 x float> %3
	}			}

	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg3.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i64)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg3.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i64)
	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg3.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg3.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x float> @test_vlseg3_nxv4f32(float* %base, i64 %vl) {			define <vscale x 4 x float> @test_vlseg3_nxv4f32(float* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg3_nxv4f32:			; CHECK-LABEL: test_vlseg3_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg3e32.v v6, (a0)			; CHECK-NEXT: vlseg3e32.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg3.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg3.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	define <vscale x 4 x float> @test_vlseg3_mask_nxv4f32(float* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x float> @test_vlseg3_mask_nxv4f32(float* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg3_mask_nxv4f32:			; CHECK-LABEL: test_vlseg3_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg3e32.v v6, (a0)			; CHECK-NEXT: vlseg3e32.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlseg3e32.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e32.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg3.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg3.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
	%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg3.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg3.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1			%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
	ret <vscale x 4 x float> %3			ret <vscale x 4 x float> %3
	}			}

	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg4.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i64)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg4.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i64)
	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg4.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg4.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x float> @test_vlseg4_nxv4f32(float* %base, i64 %vl) {			define <vscale x 4 x float> @test_vlseg4_nxv4f32(float* %base, i64 %vl) {
	; CHECK-LABEL: test_vlseg4_nxv4f32:			; CHECK-LABEL: test_vlseg4_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg4e32.v v6, (a0)			; CHECK-NEXT: vlseg4e32.v v6, (a0)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg4.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg4.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	define <vscale x 4 x float> @test_vlseg4_mask_nxv4f32(float* %base, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x float> @test_vlseg4_mask_nxv4f32(float* %base, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlseg4_mask_nxv4f32:			; CHECK-LABEL: test_vlseg4_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg4e32.v v6, (a0)			; CHECK-NEXT: vlseg4e32.v v6, (a0)
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlseg4e32.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e32.v v6, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg4.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg4.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
	%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg4.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlseg4.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1			%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
	ret <vscale x 4 x float> %3			ret <vscale x 4 x float> %3
	}			}

llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll

Show All 17 Lines	entry:
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 2		%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 2
store i32 %1, i32* %outvl		store i32 %1, i32* %outvl
ret void		ret void
}		}

define void @test_vlseg2ff_mask_dead_value(<vscale x 16 x i16> %val, i16* %base, i32 %vl, <vscale x 16 x i1> %mask, i32* %outvl) {		define void @test_vlseg2ff_mask_dead_value(<vscale x 16 x i16> %val, i16* %base, i32 %vl, <vscale x 16 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_dead_value:		; CHECK-LABEL: test_vlseg2ff_mask_dead_value:
; CHECK: # %bb.0: # %entry		; CHECK: # %bb.0: # %entry
		; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v12, v8		; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu		; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vlseg2e16ff.v v8, (a0), v0.t		; CHECK-NEXT: vlseg2e16ff.v v8, (a0), v0.t
; CHECK-NEXT: csrr a0, vl		; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)		; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret		; CHECK-NEXT: ret
entry:		entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)		%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 2		%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 2
store i32 %1, i32* %outvl		store i32 %1, i32* %outvl
ret void		ret void
}		}

define <vscale x 16 x i16> @test_vlseg2ff_dead_vl(i16* %base, i32 %vl) {		define <vscale x 16 x i16> @test_vlseg2ff_dead_vl(i16* %base, i32 %vl) {
; CHECK-LABEL: test_vlseg2ff_dead_vl:		; CHECK-LABEL: test_vlseg2ff_dead_vl:
; CHECK: # %bb.0: # %entry		; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu		; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0)		; CHECK-NEXT: vlseg2e16ff.v v4, (a0)
		; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret		; CHECK-NEXT: ret
entry:		entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i32 %vl)		%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 1		%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 1
ret <vscale x 16 x i16> %1		ret <vscale x 16 x i16> %1
}		}

define <vscale x 16 x i16> @test_vlseg2ff_mask_dead_vl(<vscale x 16 x i16> %val, i16* %base, i32 %vl, <vscale x 16 x i1> %mask) {		define <vscale x 16 x i16> @test_vlseg2ff_mask_dead_vl(<vscale x 16 x i16> %val, i16* %base, i32 %vl, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vlseg2ff_mask_dead_vl:		; CHECK-LABEL: test_vlseg2ff_mask_dead_vl:
; CHECK: # %bb.0: # %entry		; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv4r.v v4, v8		; CHECK-NEXT: vmv4r.v v4, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu		; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t		; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t
		; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret		; CHECK-NEXT: ret
entry:		entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)		%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 1		%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 1
ret <vscale x 16 x i16> %1		ret <vscale x 16 x i16> %1
}		}

define void @test_vlseg2ff_dead_all(i16* %base, i32 %vl) {		define void @test_vlseg2ff_dead_all(i16* %base, i32 %vl) {
; CHECK-LABEL: test_vlseg2ff_dead_all:		; CHECK-LABEL: test_vlseg2ff_dead_all:
; CHECK: # %bb.0: # %entry		; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu		; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vlseg2e16ff.v v8, (a0)		; CHECK-NEXT: vlseg2e16ff.v v8, (a0)
; CHECK-NEXT: ret		; CHECK-NEXT: ret
entry:		entry:
tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i32 %vl)		tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i32 %vl)
ret void		ret void
}		}

define void @test_vlseg2ff_mask_dead_all(<vscale x 16 x i16> %val, i16* %base, i32 %vl, <vscale x 16 x i1> %mask) {		define void @test_vlseg2ff_mask_dead_all(<vscale x 16 x i16> %val, i16* %base, i32 %vl, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vlseg2ff_mask_dead_all:		; CHECK-LABEL: test_vlseg2ff_mask_dead_all:
; CHECK: # %bb.0: # %entry		; CHECK: # %bb.0: # %entry
		; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v12, v8		; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu		; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vlseg2e16ff.v v8, (a0), v0.t		; CHECK-NEXT: vlseg2e16ff.v v8, (a0), v0.t
; CHECK-NEXT: ret		; CHECK-NEXT: ret
entry:		entry:
tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)		tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
ret void		ret void
}		}

llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \			; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \
	; RUN: -verify-machineinstrs < %s \| FileCheck %s			; RUN: -verify-machineinstrs < %s \| FileCheck %s

	declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16* , i32)			declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16* , i32)
	declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i32, i32)			declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i32, i32)

	define <vscale x 16 x i16> @test_vlseg2ff_nxv16i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 16 x i16> @test_vlseg2ff_nxv16i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv16i16:			; CHECK-LABEL: test_vlseg2ff_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v4, (a0)			; CHECK-NEXT: vlseg2e16ff.v v4, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 2			%2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 16 x i16> %1			ret <vscale x 16 x i16> %1
	}			}

	define <vscale x 16 x i16> @test_vlseg2ff_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i32 %vl, <vscale x 16 x i1> %mask, i32* %outvl) {			define <vscale x 16 x i16> @test_vlseg2ff_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i32 %vl, <vscale x 16 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv16i16:			; CHECK-LABEL: test_vlseg2ff_mask_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv4r.v v4, v8			; CHECK-NEXT: vmv4r.v v4, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 2			%2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 16 x i16> %1			ret <vscale x 16 x i16> %1
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg2ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg2ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i8> @test_vlseg2ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x i8> @test_vlseg2ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv1i8:			; CHECK-LABEL: test_vlseg2ff_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v7, (a0)			; CHECK-NEXT: vlseg2e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg2ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg2ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 2			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg2ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x i8> @test_vlseg2ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv1i8:			; CHECK-LABEL: test_vlseg2ff_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 2			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg3ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg3ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i8> @test_vlseg3ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x i8> @test_vlseg3ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv1i8:			; CHECK-LABEL: test_vlseg3ff_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg3e8ff.v v7, (a0)			; CHECK-NEXT: vlseg3e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg3ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg3ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 3			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg3ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x i8> @test_vlseg3ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv1i8:			; CHECK-LABEL: test_vlseg3ff_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 3			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg4ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg4ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i8> @test_vlseg4ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x i8> @test_vlseg4ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv1i8:			; CHECK-LABEL: test_vlseg4ff_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg4e8ff.v v7, (a0)			; CHECK-NEXT: vlseg4e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg4ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg4ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 4			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg4ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x i8> @test_vlseg4ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv1i8:			; CHECK-LABEL: test_vlseg4ff_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 4			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg5ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg5ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i8> @test_vlseg5ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x i8> @test_vlseg5ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv1i8:			; CHECK-LABEL: test_vlseg5ff_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg5e8ff.v v7, (a0)			; CHECK-NEXT: vlseg5e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg5ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg5ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 5			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg5ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x i8> @test_vlseg5ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv1i8:			; CHECK-LABEL: test_vlseg5ff_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 5			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg6ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg6ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i8> @test_vlseg6ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x i8> @test_vlseg6ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv1i8:			; CHECK-LABEL: test_vlseg6ff_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg6e8ff.v v7, (a0)			; CHECK-NEXT: vlseg6e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg6ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg6ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 6			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg6ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x i8> @test_vlseg6ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv1i8:			; CHECK-LABEL: test_vlseg6ff_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 6			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg7ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg7ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i8> @test_vlseg7ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x i8> @test_vlseg7ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv1i8:			; CHECK-LABEL: test_vlseg7ff_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg7e8ff.v v7, (a0)			; CHECK-NEXT: vlseg7e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg7ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg7ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 7			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg7ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x i8> @test_vlseg7ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv1i8:			; CHECK-LABEL: test_vlseg7ff_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 7			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg8ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg8ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i8> @test_vlseg8ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x i8> @test_vlseg8ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv1i8:			; CHECK-LABEL: test_vlseg8ff_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg8e8ff.v v7, (a0)			; CHECK-NEXT: vlseg8e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg8ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg8ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 8			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg8ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x i8> @test_vlseg8ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv1i8:			; CHECK-LABEL: test_vlseg8ff_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 8			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	declare {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg2ff.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i32)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg2ff.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i32)
	declare {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32, i32)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32, i32)

	define <vscale x 16 x i8> @test_vlseg2ff_nxv16i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 16 x i8> @test_vlseg2ff_nxv16i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv16i8:			; CHECK-LABEL: test_vlseg2ff_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v6, (a0)			; CHECK-NEXT: vlseg2e8ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg2ff.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg2ff.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 2			%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	define <vscale x 16 x i8> @test_vlseg2ff_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %vl, <vscale x 16 x i1> %mask, i32* %outvl) {			define <vscale x 16 x i8> @test_vlseg2ff_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %vl, <vscale x 16 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv16i8:			; CHECK-LABEL: test_vlseg2ff_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e8ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 2			%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg3ff.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i32)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg3ff.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i32)
	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32, i32)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32, i32)

	define <vscale x 16 x i8> @test_vlseg3ff_nxv16i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 16 x i8> @test_vlseg3ff_nxv16i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv16i8:			; CHECK-LABEL: test_vlseg3ff_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg3e8ff.v v6, (a0)			; CHECK-NEXT: vlseg3e8ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg3ff.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg3ff.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 3			%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	define <vscale x 16 x i8> @test_vlseg3ff_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %vl, <vscale x 16 x i1> %mask, i32* %outvl) {			define <vscale x 16 x i8> @test_vlseg3ff_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %vl, <vscale x 16 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv16i8:			; CHECK-LABEL: test_vlseg3ff_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg3e8ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e8ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 3			%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg4ff.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i32)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg4ff.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i32)
	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32, i32)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32, i32)

	define <vscale x 16 x i8> @test_vlseg4ff_nxv16i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 16 x i8> @test_vlseg4ff_nxv16i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv16i8:			; CHECK-LABEL: test_vlseg4ff_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg4e8ff.v v6, (a0)			; CHECK-NEXT: vlseg4e8ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg4ff.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg4ff.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 4			%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	define <vscale x 16 x i8> @test_vlseg4ff_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %vl, <vscale x 16 x i1> %mask, i32* %outvl) {			define <vscale x 16 x i8> @test_vlseg4ff_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %vl, <vscale x 16 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv16i8:			; CHECK-LABEL: test_vlseg4ff_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg4e8ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e8ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 4			%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg2ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg2ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i32> @test_vlseg2ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x i32> @test_vlseg2ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv2i32:			; CHECK-LABEL: test_vlseg2ff_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v7, (a0)			; CHECK-NEXT: vlseg2e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg2ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg2ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 2			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg2ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x i32> @test_vlseg2ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv2i32:			; CHECK-LABEL: test_vlseg2ff_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 2			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg3ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg3ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg3ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg3ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i32> @test_vlseg3ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x i32> @test_vlseg3ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv2i32:			; CHECK-LABEL: test_vlseg3ff_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v7, (a0)			; CHECK-NEXT: vlseg3e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg3ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg3ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 3			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg3ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x i32> @test_vlseg3ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv2i32:			; CHECK-LABEL: test_vlseg3ff_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg3ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg3ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 3			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg4ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg4ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg4ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg4ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i32> @test_vlseg4ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x i32> @test_vlseg4ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv2i32:			; CHECK-LABEL: test_vlseg4ff_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v7, (a0)			; CHECK-NEXT: vlseg4e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg4ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg4ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 4			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg4ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x i32> @test_vlseg4ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv2i32:			; CHECK-LABEL: test_vlseg4ff_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg4ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg4ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 4			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg5ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg5ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg5ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg5ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i32> @test_vlseg5ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x i32> @test_vlseg5ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv2i32:			; CHECK-LABEL: test_vlseg5ff_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg5e32ff.v v7, (a0)			; CHECK-NEXT: vlseg5e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg5ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg5ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 5			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg5ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x i32> @test_vlseg5ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv2i32:			; CHECK-LABEL: test_vlseg5ff_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg5ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg5ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 5			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg6ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg6ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg6ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg6ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i32> @test_vlseg6ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x i32> @test_vlseg6ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv2i32:			; CHECK-LABEL: test_vlseg6ff_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg6e32ff.v v7, (a0)			; CHECK-NEXT: vlseg6e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg6ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg6ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 6			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg6ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x i32> @test_vlseg6ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv2i32:			; CHECK-LABEL: test_vlseg6ff_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg6ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg6ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 6			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg7ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg7ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg7ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg7ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i32> @test_vlseg7ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x i32> @test_vlseg7ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv2i32:			; CHECK-LABEL: test_vlseg7ff_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg7e32ff.v v7, (a0)			; CHECK-NEXT: vlseg7e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg7ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg7ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 7			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg7ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x i32> @test_vlseg7ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv2i32:			; CHECK-LABEL: test_vlseg7ff_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg7ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg7ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 7			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg8ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg8ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg8ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg8ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i32> @test_vlseg8ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x i32> @test_vlseg8ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv2i32:			; CHECK-LABEL: test_vlseg8ff_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg8e32ff.v v7, (a0)			; CHECK-NEXT: vlseg8e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg8ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg8ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 8			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg8ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x i32> @test_vlseg8ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv2i32:			; CHECK-LABEL: test_vlseg8ff_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg8ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg8ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 8			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg2ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg2ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i16> @test_vlseg2ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x i16> @test_vlseg2ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv4i16:			; CHECK-LABEL: test_vlseg2ff_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0)			; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg2ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg2ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 2			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg2ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x i16> @test_vlseg2ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv4i16:			; CHECK-LABEL: test_vlseg2ff_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 2			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg3ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg3ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i16> @test_vlseg3ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x i16> @test_vlseg3ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv4i16:			; CHECK-LABEL: test_vlseg3ff_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0)			; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg3ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg3ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 3			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg3ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x i16> @test_vlseg3ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv4i16:			; CHECK-LABEL: test_vlseg3ff_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 3			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg4ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg4ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i16> @test_vlseg4ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x i16> @test_vlseg4ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv4i16:			; CHECK-LABEL: test_vlseg4ff_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0)			; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg4ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg4ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 4			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg4ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x i16> @test_vlseg4ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv4i16:			; CHECK-LABEL: test_vlseg4ff_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 4			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg5ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg5ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg5ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg5ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i16> @test_vlseg5ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x i16> @test_vlseg5ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv4i16:			; CHECK-LABEL: test_vlseg5ff_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0)			; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg5ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg5ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 5			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg5ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x i16> @test_vlseg5ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv4i16:			; CHECK-LABEL: test_vlseg5ff_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg5ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg5ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 5			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg6ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg6ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg6ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg6ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i16> @test_vlseg6ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x i16> @test_vlseg6ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv4i16:			; CHECK-LABEL: test_vlseg6ff_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0)			; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg6ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg6ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 6			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg6ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x i16> @test_vlseg6ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv4i16:			; CHECK-LABEL: test_vlseg6ff_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg6ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg6ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 6			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg7ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg7ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg7ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg7ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i16> @test_vlseg7ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x i16> @test_vlseg7ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv4i16:			; CHECK-LABEL: test_vlseg7ff_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0)			; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg7ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg7ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 7			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg7ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x i16> @test_vlseg7ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv4i16:			; CHECK-LABEL: test_vlseg7ff_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg7ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg7ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 7			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg8ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg8ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg8ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg8ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i16> @test_vlseg8ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x i16> @test_vlseg8ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv4i16:			; CHECK-LABEL: test_vlseg8ff_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0)			; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg8ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg8ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 8			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg8ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x i16> @test_vlseg8ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv4i16:			; CHECK-LABEL: test_vlseg8ff_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg8ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg8ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 8			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg2ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg2ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i32> @test_vlseg2ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x i32> @test_vlseg2ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv1i32:			; CHECK-LABEL: test_vlseg2ff_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v7, (a0)			; CHECK-NEXT: vlseg2e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg2ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg2ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 2			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg2ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x i32> @test_vlseg2ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv1i32:			; CHECK-LABEL: test_vlseg2ff_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 2			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg3ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg3ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg3ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg3ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i32> @test_vlseg3ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x i32> @test_vlseg3ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv1i32:			; CHECK-LABEL: test_vlseg3ff_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v7, (a0)			; CHECK-NEXT: vlseg3e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg3ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg3ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 3			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg3ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x i32> @test_vlseg3ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv1i32:			; CHECK-LABEL: test_vlseg3ff_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg3ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg3ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 3			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg4ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg4ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg4ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg4ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i32> @test_vlseg4ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x i32> @test_vlseg4ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv1i32:			; CHECK-LABEL: test_vlseg4ff_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v7, (a0)			; CHECK-NEXT: vlseg4e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg4ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg4ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 4			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg4ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x i32> @test_vlseg4ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv1i32:			; CHECK-LABEL: test_vlseg4ff_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg4ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg4ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 4			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg5ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg5ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg5ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg5ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i32> @test_vlseg5ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x i32> @test_vlseg5ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv1i32:			; CHECK-LABEL: test_vlseg5ff_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg5e32ff.v v7, (a0)			; CHECK-NEXT: vlseg5e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg5ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg5ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 5			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg5ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x i32> @test_vlseg5ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv1i32:			; CHECK-LABEL: test_vlseg5ff_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg5ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg5ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 5			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg6ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg6ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg6ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg6ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i32> @test_vlseg6ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x i32> @test_vlseg6ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv1i32:			; CHECK-LABEL: test_vlseg6ff_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg6e32ff.v v7, (a0)			; CHECK-NEXT: vlseg6e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg6ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg6ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 6			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg6ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x i32> @test_vlseg6ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv1i32:			; CHECK-LABEL: test_vlseg6ff_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg6ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg6ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 6			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg7ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg7ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg7ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg7ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i32> @test_vlseg7ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x i32> @test_vlseg7ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv1i32:			; CHECK-LABEL: test_vlseg7ff_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg7e32ff.v v7, (a0)			; CHECK-NEXT: vlseg7e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg7ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg7ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 7			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg7ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x i32> @test_vlseg7ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv1i32:			; CHECK-LABEL: test_vlseg7ff_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg7ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg7ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 7			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg8ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg8ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg8ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg8ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i32> @test_vlseg8ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x i32> @test_vlseg8ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv1i32:			; CHECK-LABEL: test_vlseg8ff_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg8e32ff.v v7, (a0)			; CHECK-NEXT: vlseg8e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg8ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg8ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 8			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg8ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x i32> @test_vlseg8ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv1i32:			; CHECK-LABEL: test_vlseg8ff_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg8ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg8ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 8			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	declare {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg2ff.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i32)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg2ff.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i32)
	declare {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i16> @test_vlseg2ff_nxv8i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 8 x i16> @test_vlseg2ff_nxv8i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv8i16:			; CHECK-LABEL: test_vlseg2ff_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v6, (a0)			; CHECK-NEXT: vlseg2e16ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg2ff.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg2ff.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 2			%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	define <vscale x 8 x i16> @test_vlseg2ff_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {			define <vscale x 8 x i16> @test_vlseg2ff_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv8i16:			; CHECK-LABEL: test_vlseg2ff_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e16ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 2			%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg3ff.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i32)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg3ff.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i32)
	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i16> @test_vlseg3ff_nxv8i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 8 x i16> @test_vlseg3ff_nxv8i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv8i16:			; CHECK-LABEL: test_vlseg3ff_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v6, (a0)			; CHECK-NEXT: vlseg3e16ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg3ff.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg3ff.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 3			%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	define <vscale x 8 x i16> @test_vlseg3ff_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {			define <vscale x 8 x i16> @test_vlseg3ff_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv8i16:			; CHECK-LABEL: test_vlseg3ff_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e16ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 3			%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg4ff.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i32)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg4ff.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i32)
	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i16> @test_vlseg4ff_nxv8i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 8 x i16> @test_vlseg4ff_nxv8i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv8i16:			; CHECK-LABEL: test_vlseg4ff_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v6, (a0)			; CHECK-NEXT: vlseg4e16ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg4ff.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg4ff.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 4			%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	define <vscale x 8 x i16> @test_vlseg4ff_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {			define <vscale x 8 x i16> @test_vlseg4ff_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv8i16:			; CHECK-LABEL: test_vlseg4ff_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e16ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 4			%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg2ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg2ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i8> @test_vlseg2ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 8 x i8> @test_vlseg2ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv8i8:			; CHECK-LABEL: test_vlseg2ff_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v7, (a0)			; CHECK-NEXT: vlseg2e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg2ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg2ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 2			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg2ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {			define <vscale x 8 x i8> @test_vlseg2ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv8i8:			; CHECK-LABEL: test_vlseg2ff_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 2			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg3ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg3ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i8> @test_vlseg3ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 8 x i8> @test_vlseg3ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv8i8:			; CHECK-LABEL: test_vlseg3ff_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg3e8ff.v v7, (a0)			; CHECK-NEXT: vlseg3e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg3ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg3ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 3			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg3ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {			define <vscale x 8 x i8> @test_vlseg3ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv8i8:			; CHECK-LABEL: test_vlseg3ff_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 3			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg4ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg4ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i8> @test_vlseg4ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 8 x i8> @test_vlseg4ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv8i8:			; CHECK-LABEL: test_vlseg4ff_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg4e8ff.v v7, (a0)			; CHECK-NEXT: vlseg4e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg4ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg4ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 4			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg4ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {			define <vscale x 8 x i8> @test_vlseg4ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv8i8:			; CHECK-LABEL: test_vlseg4ff_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 4			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg5ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg5ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i8> @test_vlseg5ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 8 x i8> @test_vlseg5ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv8i8:			; CHECK-LABEL: test_vlseg5ff_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg5e8ff.v v7, (a0)			; CHECK-NEXT: vlseg5e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg5ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg5ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 5			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg5ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {			define <vscale x 8 x i8> @test_vlseg5ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv8i8:			; CHECK-LABEL: test_vlseg5ff_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 5			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg6ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg6ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i8> @test_vlseg6ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 8 x i8> @test_vlseg6ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv8i8:			; CHECK-LABEL: test_vlseg6ff_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg6e8ff.v v7, (a0)			; CHECK-NEXT: vlseg6e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg6ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg6ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 6			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg6ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {			define <vscale x 8 x i8> @test_vlseg6ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv8i8:			; CHECK-LABEL: test_vlseg6ff_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 6			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg7ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg7ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i8> @test_vlseg7ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 8 x i8> @test_vlseg7ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv8i8:			; CHECK-LABEL: test_vlseg7ff_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg7e8ff.v v7, (a0)			; CHECK-NEXT: vlseg7e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg7ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg7ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 7			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg7ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {			define <vscale x 8 x i8> @test_vlseg7ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv8i8:			; CHECK-LABEL: test_vlseg7ff_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 7			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg8ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg8ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i8> @test_vlseg8ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 8 x i8> @test_vlseg8ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv8i8:			; CHECK-LABEL: test_vlseg8ff_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg8e8ff.v v7, (a0)			; CHECK-NEXT: vlseg8e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg8ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg8ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 8			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg8ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {			define <vscale x 8 x i8> @test_vlseg8ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv8i8:			; CHECK-LABEL: test_vlseg8ff_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 8			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	declare {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} @llvm.riscv.vlseg2ff.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32* , i32)			declare {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} @llvm.riscv.vlseg2ff.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32* , i32)
	declare {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i32> @test_vlseg2ff_nxv8i32(i32* %base, i32 %vl, i32* %outvl) {			define <vscale x 8 x i32> @test_vlseg2ff_nxv8i32(i32* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv8i32:			; CHECK-LABEL: test_vlseg2ff_nxv8i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v4, (a0)			; CHECK-NEXT: vlseg2e32ff.v v4, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} @llvm.riscv.vlseg2ff.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} @llvm.riscv.vlseg2ff.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} %0, 2			%2 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i32> %1			ret <vscale x 8 x i32> %1
	}			}

	define <vscale x 8 x i32> @test_vlseg2ff_mask_nxv8i32(<vscale x 8 x i32> %val, i32* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {			define <vscale x 8 x i32> @test_vlseg2ff_mask_nxv8i32(<vscale x 8 x i32> %val, i32* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv8i32:			; CHECK-LABEL: test_vlseg2ff_mask_nxv8i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv4r.v v4, v8			; CHECK-NEXT: vmv4r.v v4, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e32ff.v v4, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} %0, 2			%2 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x i32> %1			ret <vscale x 8 x i32> %1
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg2ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg2ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i8> @test_vlseg2ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x i8> @test_vlseg2ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv4i8:			; CHECK-LABEL: test_vlseg2ff_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v7, (a0)			; CHECK-NEXT: vlseg2e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg2ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg2ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 2			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg2ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x i8> @test_vlseg2ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv4i8:			; CHECK-LABEL: test_vlseg2ff_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 2			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg3ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg3ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i8> @test_vlseg3ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x i8> @test_vlseg3ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv4i8:			; CHECK-LABEL: test_vlseg3ff_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg3e8ff.v v7, (a0)			; CHECK-NEXT: vlseg3e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg3ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg3ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 3			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg3ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x i8> @test_vlseg3ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv4i8:			; CHECK-LABEL: test_vlseg3ff_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 3			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg4ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg4ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i8> @test_vlseg4ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x i8> @test_vlseg4ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv4i8:			; CHECK-LABEL: test_vlseg4ff_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg4e8ff.v v7, (a0)			; CHECK-NEXT: vlseg4e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg4ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg4ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 4			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg4ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x i8> @test_vlseg4ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv4i8:			; CHECK-LABEL: test_vlseg4ff_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 4			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg5ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg5ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i8> @test_vlseg5ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x i8> @test_vlseg5ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv4i8:			; CHECK-LABEL: test_vlseg5ff_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg5e8ff.v v7, (a0)			; CHECK-NEXT: vlseg5e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg5ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg5ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 5			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg5ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x i8> @test_vlseg5ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv4i8:			; CHECK-LABEL: test_vlseg5ff_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 5			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg6ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg6ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i8> @test_vlseg6ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x i8> @test_vlseg6ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv4i8:			; CHECK-LABEL: test_vlseg6ff_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg6e8ff.v v7, (a0)			; CHECK-NEXT: vlseg6e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg6ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg6ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 6			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg6ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x i8> @test_vlseg6ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv4i8:			; CHECK-LABEL: test_vlseg6ff_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 6			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg7ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg7ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i8> @test_vlseg7ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x i8> @test_vlseg7ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv4i8:			; CHECK-LABEL: test_vlseg7ff_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg7e8ff.v v7, (a0)			; CHECK-NEXT: vlseg7e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg7ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg7ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 7			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg7ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x i8> @test_vlseg7ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv4i8:			; CHECK-LABEL: test_vlseg7ff_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 7			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg8ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg8ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i8> @test_vlseg8ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x i8> @test_vlseg8ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv4i8:			; CHECK-LABEL: test_vlseg8ff_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg8e8ff.v v7, (a0)			; CHECK-NEXT: vlseg8e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg8ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg8ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 8			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg8ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x i8> @test_vlseg8ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv4i8:			; CHECK-LABEL: test_vlseg8ff_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 8			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg2ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg2ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i16> @test_vlseg2ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x i16> @test_vlseg2ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv1i16:			; CHECK-LABEL: test_vlseg2ff_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0)			; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg2ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg2ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 2			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg2ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x i16> @test_vlseg2ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv1i16:			; CHECK-LABEL: test_vlseg2ff_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 2			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg3ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg3ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i16> @test_vlseg3ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x i16> @test_vlseg3ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv1i16:			; CHECK-LABEL: test_vlseg3ff_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0)			; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg3ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg3ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 3			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg3ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x i16> @test_vlseg3ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv1i16:			; CHECK-LABEL: test_vlseg3ff_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 3			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg4ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg4ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i16> @test_vlseg4ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x i16> @test_vlseg4ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv1i16:			; CHECK-LABEL: test_vlseg4ff_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0)			; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg4ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg4ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 4			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg4ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x i16> @test_vlseg4ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv1i16:			; CHECK-LABEL: test_vlseg4ff_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 4			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg5ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg5ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg5ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg5ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i16> @test_vlseg5ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x i16> @test_vlseg5ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv1i16:			; CHECK-LABEL: test_vlseg5ff_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0)			; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg5ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg5ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 5			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg5ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x i16> @test_vlseg5ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv1i16:			; CHECK-LABEL: test_vlseg5ff_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg5ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg5ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 5			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg6ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg6ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg6ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg6ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i16> @test_vlseg6ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x i16> @test_vlseg6ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv1i16:			; CHECK-LABEL: test_vlseg6ff_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0)			; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg6ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg6ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 6			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg6ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x i16> @test_vlseg6ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv1i16:			; CHECK-LABEL: test_vlseg6ff_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg6ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg6ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 6			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg7ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg7ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg7ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg7ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i16> @test_vlseg7ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x i16> @test_vlseg7ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv1i16:			; CHECK-LABEL: test_vlseg7ff_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0)			; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg7ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg7ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 7			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg7ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x i16> @test_vlseg7ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv1i16:			; CHECK-LABEL: test_vlseg7ff_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg7ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg7ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 7			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg8ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg8ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg8ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg8ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i16> @test_vlseg8ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x i16> @test_vlseg8ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv1i16:			; CHECK-LABEL: test_vlseg8ff_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0)			; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg8ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg8ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 8			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg8ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x i16> @test_vlseg8ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv1i16:			; CHECK-LABEL: test_vlseg8ff_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg8ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg8ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 8			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	declare {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} @llvm.riscv.vlseg2ff.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8* , i32)			declare {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} @llvm.riscv.vlseg2ff.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8* , i32)
	declare {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i1>, i32, i32)			declare {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i1>, i32, i32)

	define <vscale x 32 x i8> @test_vlseg2ff_nxv32i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 32 x i8> @test_vlseg2ff_nxv32i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv32i8:			; CHECK-LABEL: test_vlseg2ff_nxv32i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v4, (a0)			; CHECK-NEXT: vlseg2e8ff.v v4, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} @llvm.riscv.vlseg2ff.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} @llvm.riscv.vlseg2ff.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} %0, 2			%2 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 32 x i8> %1			ret <vscale x 32 x i8> %1
	}			}

	define <vscale x 32 x i8> @test_vlseg2ff_mask_nxv32i8(<vscale x 32 x i8> %val, i8* %base, i32 %vl, <vscale x 32 x i1> %mask, i32* %outvl) {			define <vscale x 32 x i8> @test_vlseg2ff_mask_nxv32i8(<vscale x 32 x i8> %val, i8* %base, i32 %vl, <vscale x 32 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv32i8:			; CHECK-LABEL: test_vlseg2ff_mask_nxv32i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv4r.v v4, v8			; CHECK-NEXT: vmv4r.v v4, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e8ff.v v4, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} %0, 2			%2 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 32 x i8> %1			ret <vscale x 32 x i8> %1
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg2ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg2ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i8> @test_vlseg2ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x i8> @test_vlseg2ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv2i8:			; CHECK-LABEL: test_vlseg2ff_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v7, (a0)			; CHECK-NEXT: vlseg2e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg2ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg2ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 2			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg2ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x i8> @test_vlseg2ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv2i8:			; CHECK-LABEL: test_vlseg2ff_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 2			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg3ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg3ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i8> @test_vlseg3ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x i8> @test_vlseg3ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv2i8:			; CHECK-LABEL: test_vlseg3ff_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg3e8ff.v v7, (a0)			; CHECK-NEXT: vlseg3e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg3ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg3ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 3			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg3ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x i8> @test_vlseg3ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv2i8:			; CHECK-LABEL: test_vlseg3ff_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 3			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg4ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg4ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i8> @test_vlseg4ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x i8> @test_vlseg4ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv2i8:			; CHECK-LABEL: test_vlseg4ff_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg4e8ff.v v7, (a0)			; CHECK-NEXT: vlseg4e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg4ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg4ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 4			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg4ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x i8> @test_vlseg4ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv2i8:			; CHECK-LABEL: test_vlseg4ff_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 4			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg5ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg5ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i8> @test_vlseg5ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x i8> @test_vlseg5ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv2i8:			; CHECK-LABEL: test_vlseg5ff_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg5e8ff.v v7, (a0)			; CHECK-NEXT: vlseg5e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg5ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg5ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 5			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg5ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x i8> @test_vlseg5ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv2i8:			; CHECK-LABEL: test_vlseg5ff_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 5			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg6ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg6ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i8> @test_vlseg6ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x i8> @test_vlseg6ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv2i8:			; CHECK-LABEL: test_vlseg6ff_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg6e8ff.v v7, (a0)			; CHECK-NEXT: vlseg6e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg6ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg6ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 6			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg6ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x i8> @test_vlseg6ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv2i8:			; CHECK-LABEL: test_vlseg6ff_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 6			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg7ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg7ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i8> @test_vlseg7ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x i8> @test_vlseg7ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv2i8:			; CHECK-LABEL: test_vlseg7ff_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg7e8ff.v v7, (a0)			; CHECK-NEXT: vlseg7e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg7ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg7ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 7			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg7ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x i8> @test_vlseg7ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv2i8:			; CHECK-LABEL: test_vlseg7ff_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 7			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg8ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg8ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i8> @test_vlseg8ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x i8> @test_vlseg8ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv2i8:			; CHECK-LABEL: test_vlseg8ff_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg8e8ff.v v7, (a0)			; CHECK-NEXT: vlseg8e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg8ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg8ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 8			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg8ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x i8> @test_vlseg8ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv2i8:			; CHECK-LABEL: test_vlseg8ff_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 8			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg2ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg2ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i16> @test_vlseg2ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x i16> @test_vlseg2ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv2i16:			; CHECK-LABEL: test_vlseg2ff_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0)			; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg2ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg2ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 2			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg2ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x i16> @test_vlseg2ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv2i16:			; CHECK-LABEL: test_vlseg2ff_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 2			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg3ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg3ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i16> @test_vlseg3ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x i16> @test_vlseg3ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv2i16:			; CHECK-LABEL: test_vlseg3ff_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0)			; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg3ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg3ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 3			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg3ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x i16> @test_vlseg3ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv2i16:			; CHECK-LABEL: test_vlseg3ff_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 3			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg4ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg4ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i16> @test_vlseg4ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x i16> @test_vlseg4ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv2i16:			; CHECK-LABEL: test_vlseg4ff_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0)			; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg4ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg4ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 4			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg4ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x i16> @test_vlseg4ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv2i16:			; CHECK-LABEL: test_vlseg4ff_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 4			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg5ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg5ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg5ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg5ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i16> @test_vlseg5ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x i16> @test_vlseg5ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv2i16:			; CHECK-LABEL: test_vlseg5ff_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0)			; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg5ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg5ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 5			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg5ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x i16> @test_vlseg5ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv2i16:			; CHECK-LABEL: test_vlseg5ff_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg5ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg5ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 5			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg6ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg6ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg6ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg6ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i16> @test_vlseg6ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x i16> @test_vlseg6ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv2i16:			; CHECK-LABEL: test_vlseg6ff_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0)			; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg6ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg6ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 6			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg6ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x i16> @test_vlseg6ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv2i16:			; CHECK-LABEL: test_vlseg6ff_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg6ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg6ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 6			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg7ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg7ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg7ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg7ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i16> @test_vlseg7ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x i16> @test_vlseg7ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv2i16:			; CHECK-LABEL: test_vlseg7ff_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0)			; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg7ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg7ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 7			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg7ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x i16> @test_vlseg7ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv2i16:			; CHECK-LABEL: test_vlseg7ff_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg7ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg7ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 7			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg8ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg8ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg8ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg8ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i16> @test_vlseg8ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x i16> @test_vlseg8ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv2i16:			; CHECK-LABEL: test_vlseg8ff_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0)			; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg8ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg8ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 8			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg8ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x i16> @test_vlseg8ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv2i16:			; CHECK-LABEL: test_vlseg8ff_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg8ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg8ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 8			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	declare {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg2ff.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i32)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg2ff.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i32)
	declare {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i32> @test_vlseg2ff_nxv4i32(i32* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x i32> @test_vlseg2ff_nxv4i32(i32* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv4i32:			; CHECK-LABEL: test_vlseg2ff_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v6, (a0)			; CHECK-NEXT: vlseg2e32ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg2ff.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg2ff.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 2			%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	define <vscale x 4 x i32> @test_vlseg2ff_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x i32> @test_vlseg2ff_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv4i32:			; CHECK-LABEL: test_vlseg2ff_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e32ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 2			%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg3ff.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i32)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg3ff.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i32)
	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg3ff.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg3ff.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i32> @test_vlseg3ff_nxv4i32(i32* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x i32> @test_vlseg3ff_nxv4i32(i32* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv4i32:			; CHECK-LABEL: test_vlseg3ff_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v6, (a0)			; CHECK-NEXT: vlseg3e32ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg3ff.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg3ff.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 3			%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	define <vscale x 4 x i32> @test_vlseg3ff_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x i32> @test_vlseg3ff_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv4i32:			; CHECK-LABEL: test_vlseg3ff_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e32ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg3ff.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg3ff.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 3			%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg4ff.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i32)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg4ff.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i32)
	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg4ff.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg4ff.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i32> @test_vlseg4ff_nxv4i32(i32* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x i32> @test_vlseg4ff_nxv4i32(i32* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv4i32:			; CHECK-LABEL: test_vlseg4ff_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v6, (a0)			; CHECK-NEXT: vlseg4e32ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg4ff.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg4ff.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 4			%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	define <vscale x 4 x i32> @test_vlseg4ff_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x i32> @test_vlseg4ff_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv4i32:			; CHECK-LABEL: test_vlseg4ff_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e32ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg4ff.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg4ff.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 4			%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	declare {<vscale x 16 x half>,<vscale x 16 x half>, i32} @llvm.riscv.vlseg2ff.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half* , i32)			declare {<vscale x 16 x half>,<vscale x 16 x half>, i32} @llvm.riscv.vlseg2ff.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half* , i32)
	declare {<vscale x 16 x half>,<vscale x 16 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i1>, i32, i32)			declare {<vscale x 16 x half>,<vscale x 16 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i1>, i32, i32)

	define <vscale x 16 x half> @test_vlseg2ff_nxv16f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 16 x half> @test_vlseg2ff_nxv16f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv16f16:			; CHECK-LABEL: test_vlseg2ff_nxv16f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v4, (a0)			; CHECK-NEXT: vlseg2e16ff.v v4, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>, i32} @llvm.riscv.vlseg2ff.nxv16f16(<vscale x 16 x half> undef, <vscale x 16 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>, i32} @llvm.riscv.vlseg2ff.nxv16f16(<vscale x 16 x half> undef, <vscale x 16 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i32} %0, 2			%2 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 16 x half> %1			ret <vscale x 16 x half> %1
	}			}

	define <vscale x 16 x half> @test_vlseg2ff_mask_nxv16f16(<vscale x 16 x half> %val, half* %base, i32 %vl, <vscale x 16 x i1> %mask, i32* %outvl) {			define <vscale x 16 x half> @test_vlseg2ff_mask_nxv16f16(<vscale x 16 x half> %val, half* %base, i32 %vl, <vscale x 16 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv16f16:			; CHECK-LABEL: test_vlseg2ff_mask_nxv16f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv4r.v v4, v8			; CHECK-NEXT: vmv4r.v v4, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i32} %0, 2			%2 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 16 x half> %1			ret <vscale x 16 x half> %1
	}			}

	declare {<vscale x 4 x double>,<vscale x 4 x double>, i32} @llvm.riscv.vlseg2ff.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double* , i32)			declare {<vscale x 4 x double>,<vscale x 4 x double>, i32} @llvm.riscv.vlseg2ff.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double* , i32)
	declare {<vscale x 4 x double>,<vscale x 4 x double>, i32} @llvm.riscv.vlseg2ff.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x double>,<vscale x 4 x double>, i32} @llvm.riscv.vlseg2ff.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x double> @test_vlseg2ff_nxv4f64(double* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x double> @test_vlseg2ff_nxv4f64(double* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv4f64:			; CHECK-LABEL: test_vlseg2ff_nxv4f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
	; CHECK-NEXT: vlseg2e64ff.v v4, (a0)			; CHECK-NEXT: vlseg2e64ff.v v4, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>, i32} @llvm.riscv.vlseg2ff.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>, i32} @llvm.riscv.vlseg2ff.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i32} %0, 2			%2 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x double> %1			ret <vscale x 4 x double> %1
	}			}

	define <vscale x 4 x double> @test_vlseg2ff_mask_nxv4f64(<vscale x 4 x double> %val, double* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x double> @test_vlseg2ff_mask_nxv4f64(<vscale x 4 x double> %val, double* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv4f64:			; CHECK-LABEL: test_vlseg2ff_mask_nxv4f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv4r.v v4, v8			; CHECK-NEXT: vmv4r.v v4, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
	; CHECK-NEXT: vlseg2e64ff.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e64ff.v v4, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>, i32} @llvm.riscv.vlseg2ff.mask.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>, i32} @llvm.riscv.vlseg2ff.mask.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i32} %0, 2			%2 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x double> %1			ret <vscale x 4 x double> %1
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg2ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg2ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
	declare {<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg2ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg2ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x double> @test_vlseg2ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x double> @test_vlseg2ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv1f64:			; CHECK-LABEL: test_vlseg2ff_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg2e64ff.v v7, (a0)			; CHECK-NEXT: vlseg2e64ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg2ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg2ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 2			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg2ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x double> @test_vlseg2ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv1f64:			; CHECK-LABEL: test_vlseg2ff_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg2e64ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e64ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg2ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg2ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 2			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg3ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg3ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg3ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg3ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x double> @test_vlseg3ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x double> @test_vlseg3ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv1f64:			; CHECK-LABEL: test_vlseg3ff_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg3e64ff.v v7, (a0)			; CHECK-NEXT: vlseg3e64ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg3ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg3ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 3			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg3ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x double> @test_vlseg3ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv1f64:			; CHECK-LABEL: test_vlseg3ff_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg3e64ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e64ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg3ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg3ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 3			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg4ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg4ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg4ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg4ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x double> @test_vlseg4ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x double> @test_vlseg4ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv1f64:			; CHECK-LABEL: test_vlseg4ff_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg4e64ff.v v7, (a0)			; CHECK-NEXT: vlseg4e64ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg4ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg4ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 4			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg4ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x double> @test_vlseg4ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv1f64:			; CHECK-LABEL: test_vlseg4ff_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg4e64ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e64ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg4ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg4ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 4			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg5ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg5ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg5ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg5ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x double> @test_vlseg5ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x double> @test_vlseg5ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv1f64:			; CHECK-LABEL: test_vlseg5ff_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg5e64ff.v v7, (a0)			; CHECK-NEXT: vlseg5e64ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg5ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg5ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 5			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg5ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x double> @test_vlseg5ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv1f64:			; CHECK-LABEL: test_vlseg5ff_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg5e64ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e64ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg5ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg5ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 5			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg6ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg6ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg6ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg6ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x double> @test_vlseg6ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x double> @test_vlseg6ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv1f64:			; CHECK-LABEL: test_vlseg6ff_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg6e64ff.v v7, (a0)			; CHECK-NEXT: vlseg6e64ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg6ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg6ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 6			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg6ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x double> @test_vlseg6ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv1f64:			; CHECK-LABEL: test_vlseg6ff_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg6e64ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e64ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg6ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg6ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 6			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg7ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg7ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg7ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg7ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x double> @test_vlseg7ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x double> @test_vlseg7ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv1f64:			; CHECK-LABEL: test_vlseg7ff_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg7e64ff.v v7, (a0)			; CHECK-NEXT: vlseg7e64ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg7ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg7ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 7			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg7ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x double> @test_vlseg7ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv1f64:			; CHECK-LABEL: test_vlseg7ff_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg7e64ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e64ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg7ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg7ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 7			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg8ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg8ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg8ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg8ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x double> @test_vlseg8ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x double> @test_vlseg8ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv1f64:			; CHECK-LABEL: test_vlseg8ff_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg8e64ff.v v7, (a0)			; CHECK-NEXT: vlseg8e64ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg8ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg8ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 8			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg8ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x double> @test_vlseg8ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv1f64:			; CHECK-LABEL: test_vlseg8ff_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg8e64ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e64ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg8ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg8ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 8			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg2ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg2ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
	declare {<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x float> @test_vlseg2ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x float> @test_vlseg2ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv2f32:			; CHECK-LABEL: test_vlseg2ff_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v7, (a0)			; CHECK-NEXT: vlseg2e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg2ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg2ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 2			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg2ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x float> @test_vlseg2ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv2f32:			; CHECK-LABEL: test_vlseg2ff_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 2			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg3ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg3ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg3ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg3ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x float> @test_vlseg3ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x float> @test_vlseg3ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv2f32:			; CHECK-LABEL: test_vlseg3ff_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v7, (a0)			; CHECK-NEXT: vlseg3e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg3ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg3ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 3			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg3ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x float> @test_vlseg3ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv2f32:			; CHECK-LABEL: test_vlseg3ff_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg3ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg3ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 3			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg4ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg4ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg4ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg4ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x float> @test_vlseg4ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x float> @test_vlseg4ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv2f32:			; CHECK-LABEL: test_vlseg4ff_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v7, (a0)			; CHECK-NEXT: vlseg4e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg4ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg4ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 4			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg4ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x float> @test_vlseg4ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv2f32:			; CHECK-LABEL: test_vlseg4ff_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg4ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg4ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 4			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg5ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg5ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg5ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg5ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x float> @test_vlseg5ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x float> @test_vlseg5ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv2f32:			; CHECK-LABEL: test_vlseg5ff_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg5e32ff.v v7, (a0)			; CHECK-NEXT: vlseg5e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg5ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg5ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 5			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg5ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x float> @test_vlseg5ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv2f32:			; CHECK-LABEL: test_vlseg5ff_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg5ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg5ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 5			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg6ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg6ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg6ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg6ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x float> @test_vlseg6ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x float> @test_vlseg6ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv2f32:			; CHECK-LABEL: test_vlseg6ff_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg6e32ff.v v7, (a0)			; CHECK-NEXT: vlseg6e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg6ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg6ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 6			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg6ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x float> @test_vlseg6ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv2f32:			; CHECK-LABEL: test_vlseg6ff_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg6ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg6ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 6			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg7ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg7ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg7ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg7ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x float> @test_vlseg7ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x float> @test_vlseg7ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv2f32:			; CHECK-LABEL: test_vlseg7ff_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg7e32ff.v v7, (a0)			; CHECK-NEXT: vlseg7e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg7ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg7ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 7			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg7ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x float> @test_vlseg7ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv2f32:			; CHECK-LABEL: test_vlseg7ff_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg7ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg7ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 7			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg8ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg8ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg8ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg8ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x float> @test_vlseg8ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x float> @test_vlseg8ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv2f32:			; CHECK-LABEL: test_vlseg8ff_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg8e32ff.v v7, (a0)			; CHECK-NEXT: vlseg8e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg8ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg8ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 8			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg8ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x float> @test_vlseg8ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv2f32:			; CHECK-LABEL: test_vlseg8ff_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg8ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg8ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 8			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg2ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg2ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
	declare {<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x half> @test_vlseg2ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x half> @test_vlseg2ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv1f16:			; CHECK-LABEL: test_vlseg2ff_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0)			; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg2ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg2ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 2			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg2ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x half> @test_vlseg2ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv1f16:			; CHECK-LABEL: test_vlseg2ff_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 2			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg3ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg3ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x half> @test_vlseg3ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x half> @test_vlseg3ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv1f16:			; CHECK-LABEL: test_vlseg3ff_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0)			; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg3ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg3ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 3			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg3ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x half> @test_vlseg3ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv1f16:			; CHECK-LABEL: test_vlseg3ff_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 3			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg4ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg4ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x half> @test_vlseg4ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x half> @test_vlseg4ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv1f16:			; CHECK-LABEL: test_vlseg4ff_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0)			; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg4ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg4ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 4			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg4ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x half> @test_vlseg4ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv1f16:			; CHECK-LABEL: test_vlseg4ff_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 4			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg5ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg5ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg5ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg5ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x half> @test_vlseg5ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x half> @test_vlseg5ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv1f16:			; CHECK-LABEL: test_vlseg5ff_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0)			; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg5ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg5ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 5			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg5ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x half> @test_vlseg5ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv1f16:			; CHECK-LABEL: test_vlseg5ff_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg5ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg5ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 5			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg6ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg6ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg6ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg6ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x half> @test_vlseg6ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x half> @test_vlseg6ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv1f16:			; CHECK-LABEL: test_vlseg6ff_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0)			; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg6ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg6ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 6			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg6ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x half> @test_vlseg6ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv1f16:			; CHECK-LABEL: test_vlseg6ff_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg6ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg6ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 6			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg7ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg7ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg7ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg7ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x half> @test_vlseg7ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x half> @test_vlseg7ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv1f16:			; CHECK-LABEL: test_vlseg7ff_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0)			; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg7ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg7ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 7			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg7ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x half> @test_vlseg7ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv1f16:			; CHECK-LABEL: test_vlseg7ff_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg7ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg7ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 7			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg8ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg8ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg8ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg8ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x half> @test_vlseg8ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x half> @test_vlseg8ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv1f16:			; CHECK-LABEL: test_vlseg8ff_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0)			; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg8ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg8ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 8			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg8ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x half> @test_vlseg8ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv1f16:			; CHECK-LABEL: test_vlseg8ff_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg8ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg8ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 8			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg2ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg2ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
	declare {<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x float> @test_vlseg2ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x float> @test_vlseg2ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv1f32:			; CHECK-LABEL: test_vlseg2ff_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v7, (a0)			; CHECK-NEXT: vlseg2e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg2ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg2ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 2			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg2ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x float> @test_vlseg2ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv1f32:			; CHECK-LABEL: test_vlseg2ff_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 2			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg3ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg3ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg3ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg3ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x float> @test_vlseg3ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x float> @test_vlseg3ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv1f32:			; CHECK-LABEL: test_vlseg3ff_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v7, (a0)			; CHECK-NEXT: vlseg3e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg3ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg3ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 3			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg3ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x float> @test_vlseg3ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv1f32:			; CHECK-LABEL: test_vlseg3ff_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg3ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg3ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 3			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg4ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg4ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg4ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg4ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x float> @test_vlseg4ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x float> @test_vlseg4ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv1f32:			; CHECK-LABEL: test_vlseg4ff_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v7, (a0)			; CHECK-NEXT: vlseg4e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg4ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg4ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 4			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg4ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x float> @test_vlseg4ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv1f32:			; CHECK-LABEL: test_vlseg4ff_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg4ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg4ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 4			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg5ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg5ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg5ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg5ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x float> @test_vlseg5ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x float> @test_vlseg5ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv1f32:			; CHECK-LABEL: test_vlseg5ff_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg5e32ff.v v7, (a0)			; CHECK-NEXT: vlseg5e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg5ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg5ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 5			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg5ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x float> @test_vlseg5ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv1f32:			; CHECK-LABEL: test_vlseg5ff_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg5ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg5ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 5			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg6ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg6ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg6ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg6ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x float> @test_vlseg6ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x float> @test_vlseg6ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv1f32:			; CHECK-LABEL: test_vlseg6ff_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg6e32ff.v v7, (a0)			; CHECK-NEXT: vlseg6e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg6ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg6ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 6			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg6ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x float> @test_vlseg6ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv1f32:			; CHECK-LABEL: test_vlseg6ff_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg6ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg6ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 6			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg7ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg7ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg7ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg7ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x float> @test_vlseg7ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x float> @test_vlseg7ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv1f32:			; CHECK-LABEL: test_vlseg7ff_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg7e32ff.v v7, (a0)			; CHECK-NEXT: vlseg7e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg7ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg7ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 7			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg7ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x float> @test_vlseg7ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv1f32:			; CHECK-LABEL: test_vlseg7ff_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg7ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg7ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 7			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg8ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg8ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg8ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg8ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x float> @test_vlseg8ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) {			define <vscale x 1 x float> @test_vlseg8ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv1f32:			; CHECK-LABEL: test_vlseg8ff_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg8e32ff.v v7, (a0)			; CHECK-NEXT: vlseg8e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg8ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg8ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 8			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg8ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {			define <vscale x 1 x float> @test_vlseg8ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv1f32:			; CHECK-LABEL: test_vlseg8ff_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg8ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg8ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 8			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	declare {<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg2ff.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half* , i32)			declare {<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg2ff.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half* , i32)
	declare {<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x half> @test_vlseg2ff_nxv8f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 8 x half> @test_vlseg2ff_nxv8f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv8f16:			; CHECK-LABEL: test_vlseg2ff_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v6, (a0)			; CHECK-NEXT: vlseg2e16ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg2ff.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg2ff.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 2			%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	define <vscale x 8 x half> @test_vlseg2ff_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {			define <vscale x 8 x half> @test_vlseg2ff_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv8f16:			; CHECK-LABEL: test_vlseg2ff_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e16ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 2			%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg3ff.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i32)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg3ff.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i32)
	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x half> @test_vlseg3ff_nxv8f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 8 x half> @test_vlseg3ff_nxv8f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv8f16:			; CHECK-LABEL: test_vlseg3ff_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v6, (a0)			; CHECK-NEXT: vlseg3e16ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg3ff.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg3ff.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 3			%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	define <vscale x 8 x half> @test_vlseg3ff_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {			define <vscale x 8 x half> @test_vlseg3ff_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv8f16:			; CHECK-LABEL: test_vlseg3ff_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e16ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 3			%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg4ff.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i32)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg4ff.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i32)
	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x half> @test_vlseg4ff_nxv8f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 8 x half> @test_vlseg4ff_nxv8f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv8f16:			; CHECK-LABEL: test_vlseg4ff_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v6, (a0)			; CHECK-NEXT: vlseg4e16ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg4ff.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg4ff.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 4			%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	define <vscale x 8 x half> @test_vlseg4ff_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {			define <vscale x 8 x half> @test_vlseg4ff_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv8f16:			; CHECK-LABEL: test_vlseg4ff_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e16ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 4			%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	declare {<vscale x 8 x float>,<vscale x 8 x float>, i32} @llvm.riscv.vlseg2ff.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float* , i32)			declare {<vscale x 8 x float>,<vscale x 8 x float>, i32} @llvm.riscv.vlseg2ff.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float* , i32)
	declare {<vscale x 8 x float>,<vscale x 8 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x float>,<vscale x 8 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x float> @test_vlseg2ff_nxv8f32(float* %base, i32 %vl, i32* %outvl) {			define <vscale x 8 x float> @test_vlseg2ff_nxv8f32(float* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv8f32:			; CHECK-LABEL: test_vlseg2ff_nxv8f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v4, (a0)			; CHECK-NEXT: vlseg2e32ff.v v4, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>, i32} @llvm.riscv.vlseg2ff.nxv8f32(<vscale x 8 x float> undef, <vscale x 8 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>, i32} @llvm.riscv.vlseg2ff.nxv8f32(<vscale x 8 x float> undef, <vscale x 8 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i32} %0, 2			%2 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x float> %1			ret <vscale x 8 x float> %1
	}			}

	define <vscale x 8 x float> @test_vlseg2ff_mask_nxv8f32(<vscale x 8 x float> %val, float* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {			define <vscale x 8 x float> @test_vlseg2ff_mask_nxv8f32(<vscale x 8 x float> %val, float* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv8f32:			; CHECK-LABEL: test_vlseg2ff_mask_nxv8f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv4r.v v4, v8			; CHECK-NEXT: vmv4r.v v4, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e32ff.v v4, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i32} %0, 2			%2 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 8 x float> %1			ret <vscale x 8 x float> %1
	}			}

	declare {<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg2ff.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double* , i32)			declare {<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg2ff.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double* , i32)
	declare {<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg2ff.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg2ff.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x double> @test_vlseg2ff_nxv2f64(double* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x double> @test_vlseg2ff_nxv2f64(double* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv2f64:			; CHECK-LABEL: test_vlseg2ff_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg2e64ff.v v6, (a0)			; CHECK-NEXT: vlseg2e64ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg2ff.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg2ff.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 2			%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	define <vscale x 2 x double> @test_vlseg2ff_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x double> @test_vlseg2ff_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv2f64:			; CHECK-LABEL: test_vlseg2ff_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg2e64ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e64ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg2ff.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg2ff.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 2			%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg3ff.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i32)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg3ff.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i32)
	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg3ff.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg3ff.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x double> @test_vlseg3ff_nxv2f64(double* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x double> @test_vlseg3ff_nxv2f64(double* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv2f64:			; CHECK-LABEL: test_vlseg3ff_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg3e64ff.v v6, (a0)			; CHECK-NEXT: vlseg3e64ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg3ff.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg3ff.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 3			%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	define <vscale x 2 x double> @test_vlseg3ff_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x double> @test_vlseg3ff_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv2f64:			; CHECK-LABEL: test_vlseg3ff_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg3e64ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e64ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg3ff.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg3ff.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 3			%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg4ff.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i32)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg4ff.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i32)
	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg4ff.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg4ff.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x double> @test_vlseg4ff_nxv2f64(double* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x double> @test_vlseg4ff_nxv2f64(double* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv2f64:			; CHECK-LABEL: test_vlseg4ff_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg4e64ff.v v6, (a0)			; CHECK-NEXT: vlseg4e64ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg4ff.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg4ff.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 4			%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	define <vscale x 2 x double> @test_vlseg4ff_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x double> @test_vlseg4ff_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv2f64:			; CHECK-LABEL: test_vlseg4ff_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg4e64ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e64ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg4ff.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg4ff.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 4			%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg2ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg2ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
	declare {<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x half> @test_vlseg2ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x half> @test_vlseg2ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv4f16:			; CHECK-LABEL: test_vlseg2ff_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0)			; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg2ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg2ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 2			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg2ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x half> @test_vlseg2ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv4f16:			; CHECK-LABEL: test_vlseg2ff_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 2			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg3ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg3ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x half> @test_vlseg3ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x half> @test_vlseg3ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv4f16:			; CHECK-LABEL: test_vlseg3ff_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0)			; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg3ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg3ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 3			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg3ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x half> @test_vlseg3ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv4f16:			; CHECK-LABEL: test_vlseg3ff_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 3			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg4ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg4ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x half> @test_vlseg4ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x half> @test_vlseg4ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv4f16:			; CHECK-LABEL: test_vlseg4ff_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0)			; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg4ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg4ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 4			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg4ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x half> @test_vlseg4ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv4f16:			; CHECK-LABEL: test_vlseg4ff_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 4			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg5ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg5ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg5ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg5ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x half> @test_vlseg5ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x half> @test_vlseg5ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv4f16:			; CHECK-LABEL: test_vlseg5ff_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0)			; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg5ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg5ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 5			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg5ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x half> @test_vlseg5ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv4f16:			; CHECK-LABEL: test_vlseg5ff_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg5ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg5ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 5			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg6ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg6ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg6ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg6ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x half> @test_vlseg6ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x half> @test_vlseg6ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv4f16:			; CHECK-LABEL: test_vlseg6ff_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0)			; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg6ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg6ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 6			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg6ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x half> @test_vlseg6ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv4f16:			; CHECK-LABEL: test_vlseg6ff_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg6ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg6ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 6			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg7ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg7ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg7ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg7ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x half> @test_vlseg7ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x half> @test_vlseg7ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv4f16:			; CHECK-LABEL: test_vlseg7ff_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0)			; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg7ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg7ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 7			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg7ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x half> @test_vlseg7ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv4f16:			; CHECK-LABEL: test_vlseg7ff_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg7ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg7ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 7			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg8ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg8ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg8ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg8ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x half> @test_vlseg8ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x half> @test_vlseg8ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv4f16:			; CHECK-LABEL: test_vlseg8ff_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0)			; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg8ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg8ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 8			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg8ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x half> @test_vlseg8ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv4f16:			; CHECK-LABEL: test_vlseg8ff_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg8ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg8ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 8			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg2ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg2ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
	declare {<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x half> @test_vlseg2ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x half> @test_vlseg2ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv2f16:			; CHECK-LABEL: test_vlseg2ff_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0)			; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg2ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg2ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 2			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg2ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x half> @test_vlseg2ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv2f16:			; CHECK-LABEL: test_vlseg2ff_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 2			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg3ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg3ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x half> @test_vlseg3ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x half> @test_vlseg3ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv2f16:			; CHECK-LABEL: test_vlseg3ff_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0)			; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg3ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg3ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 3			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg3ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x half> @test_vlseg3ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv2f16:			; CHECK-LABEL: test_vlseg3ff_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 3			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg4ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg4ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x half> @test_vlseg4ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x half> @test_vlseg4ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv2f16:			; CHECK-LABEL: test_vlseg4ff_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0)			; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg4ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg4ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 4			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg4ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x half> @test_vlseg4ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv2f16:			; CHECK-LABEL: test_vlseg4ff_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 4			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg5ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg5ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg5ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg5ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x half> @test_vlseg5ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x half> @test_vlseg5ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv2f16:			; CHECK-LABEL: test_vlseg5ff_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0)			; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg5ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg5ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 5			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg5ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x half> @test_vlseg5ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv2f16:			; CHECK-LABEL: test_vlseg5ff_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg5ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg5ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 5			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 5
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg6ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg6ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg6ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg6ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x half> @test_vlseg6ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x half> @test_vlseg6ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv2f16:			; CHECK-LABEL: test_vlseg6ff_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0)			; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg6ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg6ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 6			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg6ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x half> @test_vlseg6ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv2f16:			; CHECK-LABEL: test_vlseg6ff_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg6ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg6ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 6			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 6
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg7ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg7ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg7ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg7ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x half> @test_vlseg7ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x half> @test_vlseg7ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv2f16:			; CHECK-LABEL: test_vlseg7ff_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0)			; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg7ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg7ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 7			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg7ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x half> @test_vlseg7ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv2f16:			; CHECK-LABEL: test_vlseg7ff_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg7ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg7ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 7			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 7
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg8ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg8ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg8ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg8ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x half> @test_vlseg8ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) {			define <vscale x 2 x half> @test_vlseg8ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv2f16:			; CHECK-LABEL: test_vlseg8ff_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0)			; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg8ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg8ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 8			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg8ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {			define <vscale x 2 x half> @test_vlseg8ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv2f16:			; CHECK-LABEL: test_vlseg8ff_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg8ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg8ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 8			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 8
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	declare {<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg2ff.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float* , i32)			declare {<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg2ff.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float* , i32)
	declare {<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x float> @test_vlseg2ff_nxv4f32(float* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x float> @test_vlseg2ff_nxv4f32(float* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv4f32:			; CHECK-LABEL: test_vlseg2ff_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v6, (a0)			; CHECK-NEXT: vlseg2e32ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg2ff.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg2ff.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 2			%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	define <vscale x 4 x float> @test_vlseg2ff_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x float> @test_vlseg2ff_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv4f32:			; CHECK-LABEL: test_vlseg2ff_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e32ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 2			%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 2
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg3ff.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i32)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg3ff.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i32)
	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg3ff.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg3ff.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x float> @test_vlseg3ff_nxv4f32(float* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x float> @test_vlseg3ff_nxv4f32(float* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv4f32:			; CHECK-LABEL: test_vlseg3ff_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v6, (a0)			; CHECK-NEXT: vlseg3e32ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg3ff.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg3ff.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 3			%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	define <vscale x 4 x float> @test_vlseg3ff_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x float> @test_vlseg3ff_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv4f32:			; CHECK-LABEL: test_vlseg3ff_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e32ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg3ff.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg3ff.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 3			%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 3
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg4ff.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i32)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg4ff.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i32)
	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg4ff.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg4ff.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x float> @test_vlseg4ff_nxv4f32(float* %base, i32 %vl, i32* %outvl) {			define <vscale x 4 x float> @test_vlseg4ff_nxv4f32(float* %base, i32 %vl, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv4f32:			; CHECK-LABEL: test_vlseg4ff_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v6, (a0)			; CHECK-NEXT: vlseg4e32ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg4ff.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg4ff.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 4			%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	define <vscale x 4 x float> @test_vlseg4ff_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {			define <vscale x 4 x float> @test_vlseg4ff_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv4f32:			; CHECK-LABEL: test_vlseg4ff_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e32ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sw a0, 0(a2)			; CHECK-NEXT: sw a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg4ff.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg4ff.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 1
	%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 4			%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 4
	store i32 %2, i32* %outvl			store i32 %2, i32* %outvl
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll

Show All 17 Lines	entry:
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2		%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2
store i64 %1, i64* %outvl		store i64 %1, i64* %outvl
ret void		ret void
}		}

define void @test_vlseg2ff_mask_dead_value(<vscale x 16 x i16> %val, i16* %base, i64 %vl, <vscale x 16 x i1> %mask, i64* %outvl) {		define void @test_vlseg2ff_mask_dead_value(<vscale x 16 x i16> %val, i16* %base, i64 %vl, <vscale x 16 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_dead_value:		; CHECK-LABEL: test_vlseg2ff_mask_dead_value:
; CHECK: # %bb.0: # %entry		; CHECK: # %bb.0: # %entry
		; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v12, v8		; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu		; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vlseg2e16ff.v v8, (a0), v0.t		; CHECK-NEXT: vlseg2e16ff.v v8, (a0), v0.t
; CHECK-NEXT: csrr a0, vl		; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)		; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret		; CHECK-NEXT: ret
entry:		entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)		%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2		%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2
store i64 %1, i64* %outvl		store i64 %1, i64* %outvl
ret void		ret void
}		}

define <vscale x 16 x i16> @test_vlseg2ff_dead_vl(i16* %base, i64 %vl) {		define <vscale x 16 x i16> @test_vlseg2ff_dead_vl(i16* %base, i64 %vl) {
; CHECK-LABEL: test_vlseg2ff_dead_vl:		; CHECK-LABEL: test_vlseg2ff_dead_vl:
; CHECK: # %bb.0: # %entry		; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu		; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0)		; CHECK-NEXT: vlseg2e16ff.v v4, (a0)
		; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret		; CHECK-NEXT: ret
entry:		entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i64 %vl)		%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1		%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1
ret <vscale x 16 x i16> %1		ret <vscale x 16 x i16> %1
}		}

define <vscale x 16 x i16> @test_vlseg2ff_mask_dead_vl(<vscale x 16 x i16> %val, i16* %base, i64 %vl, <vscale x 16 x i1> %mask) {		define <vscale x 16 x i16> @test_vlseg2ff_mask_dead_vl(<vscale x 16 x i16> %val, i16* %base, i64 %vl, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vlseg2ff_mask_dead_vl:		; CHECK-LABEL: test_vlseg2ff_mask_dead_vl:
; CHECK: # %bb.0: # %entry		; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv4r.v v4, v8		; CHECK-NEXT: vmv4r.v v4, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu		; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t		; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t
		; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret		; CHECK-NEXT: ret
entry:		entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)		%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1		%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1
ret <vscale x 16 x i16> %1		ret <vscale x 16 x i16> %1
}		}

define void @test_vlseg2ff_dead_all(i16* %base, i64 %vl) {		define void @test_vlseg2ff_dead_all(i16* %base, i64 %vl) {
; CHECK-LABEL: test_vlseg2ff_dead_all:		; CHECK-LABEL: test_vlseg2ff_dead_all:
; CHECK: # %bb.0: # %entry		; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu		; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vlseg2e16ff.v v8, (a0)		; CHECK-NEXT: vlseg2e16ff.v v8, (a0)
; CHECK-NEXT: ret		; CHECK-NEXT: ret
entry:		entry:
tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i64 %vl)		tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i64 %vl)
ret void		ret void
}		}

define void @test_vlseg2ff_mask_dead_all(<vscale x 16 x i16> %val, i16* %base, i64 %vl, <vscale x 16 x i1> %mask) {		define void @test_vlseg2ff_mask_dead_all(<vscale x 16 x i16> %val, i16* %base, i64 %vl, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vlseg2ff_mask_dead_all:		; CHECK-LABEL: test_vlseg2ff_mask_dead_all:
; CHECK: # %bb.0: # %entry		; CHECK: # %bb.0: # %entry
		; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v12, v8		; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu		; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vlseg2e16ff.v v8, (a0), v0.t		; CHECK-NEXT: vlseg2e16ff.v v8, (a0), v0.t
; CHECK-NEXT: ret		; CHECK-NEXT: ret
entry:		entry:
tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)		tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)
ret void		ret void
}		}

llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \			; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \
	; RUN: -verify-machineinstrs < %s \| FileCheck %s			; RUN: -verify-machineinstrs < %s \| FileCheck %s

	declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16* , i64)			declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16* , i64)
	declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i64, i64)			declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i64, i64)

	define <vscale x 16 x i16> @test_vlseg2ff_nxv16i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 16 x i16> @test_vlseg2ff_nxv16i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv16i16:			; CHECK-LABEL: test_vlseg2ff_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v4, (a0)			; CHECK-NEXT: vlseg2e16ff.v v4, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2			%2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 16 x i16> %1			ret <vscale x 16 x i16> %1
	}			}

	define <vscale x 16 x i16> @test_vlseg2ff_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i64 %vl, <vscale x 16 x i1> %mask, i64* %outvl) {			define <vscale x 16 x i16> @test_vlseg2ff_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i64 %vl, <vscale x 16 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv16i16:			; CHECK-LABEL: test_vlseg2ff_mask_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv4r.v v4, v8			; CHECK-NEXT: vmv4r.v v4, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2			%2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 16 x i16> %1			ret <vscale x 16 x i16> %1
	}			}

	declare {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg2ff.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i64)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg2ff.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i64)
	declare {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i32> @test_vlseg2ff_nxv4i32(i32* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x i32> @test_vlseg2ff_nxv4i32(i32* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv4i32:			; CHECK-LABEL: test_vlseg2ff_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v6, (a0)			; CHECK-NEXT: vlseg2e32ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg2ff.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg2ff.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 2			%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	define <vscale x 4 x i32> @test_vlseg2ff_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x i32> @test_vlseg2ff_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv4i32:			; CHECK-LABEL: test_vlseg2ff_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e32ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 2			%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg3ff.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i64)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg3ff.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i64)
	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg3ff.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg3ff.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i32> @test_vlseg3ff_nxv4i32(i32* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x i32> @test_vlseg3ff_nxv4i32(i32* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv4i32:			; CHECK-LABEL: test_vlseg3ff_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v6, (a0)			; CHECK-NEXT: vlseg3e32ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg3ff.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg3ff.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 3			%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	define <vscale x 4 x i32> @test_vlseg3ff_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x i32> @test_vlseg3ff_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv4i32:			; CHECK-LABEL: test_vlseg3ff_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e32ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg3ff.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg3ff.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 3			%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg4ff.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i64)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg4ff.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i64)
	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg4ff.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg4ff.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i32> @test_vlseg4ff_nxv4i32(i32* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x i32> @test_vlseg4ff_nxv4i32(i32* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv4i32:			; CHECK-LABEL: test_vlseg4ff_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v6, (a0)			; CHECK-NEXT: vlseg4e32ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg4ff.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg4ff.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 4			%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	define <vscale x 4 x i32> @test_vlseg4ff_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x i32> @test_vlseg4ff_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv4i32:			; CHECK-LABEL: test_vlseg4ff_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e32ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg4ff.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg4ff.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 4			%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	declare {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg2ff.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i64)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg2ff.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i64)
	declare {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64, i64)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64, i64)

	define <vscale x 16 x i8> @test_vlseg2ff_nxv16i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 16 x i8> @test_vlseg2ff_nxv16i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv16i8:			; CHECK-LABEL: test_vlseg2ff_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v6, (a0)			; CHECK-NEXT: vlseg2e8ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg2ff.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg2ff.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 2			%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	define <vscale x 16 x i8> @test_vlseg2ff_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %vl, <vscale x 16 x i1> %mask, i64* %outvl) {			define <vscale x 16 x i8> @test_vlseg2ff_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %vl, <vscale x 16 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv16i8:			; CHECK-LABEL: test_vlseg2ff_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e8ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 2			%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg3ff.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i64)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg3ff.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i64)
	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64, i64)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64, i64)

	define <vscale x 16 x i8> @test_vlseg3ff_nxv16i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 16 x i8> @test_vlseg3ff_nxv16i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv16i8:			; CHECK-LABEL: test_vlseg3ff_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg3e8ff.v v6, (a0)			; CHECK-NEXT: vlseg3e8ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg3ff.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg3ff.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 3			%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	define <vscale x 16 x i8> @test_vlseg3ff_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %vl, <vscale x 16 x i1> %mask, i64* %outvl) {			define <vscale x 16 x i8> @test_vlseg3ff_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %vl, <vscale x 16 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv16i8:			; CHECK-LABEL: test_vlseg3ff_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg3e8ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e8ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 3			%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg4ff.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i64)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg4ff.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i64)
	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64, i64)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64, i64)

	define <vscale x 16 x i8> @test_vlseg4ff_nxv16i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 16 x i8> @test_vlseg4ff_nxv16i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv16i8:			; CHECK-LABEL: test_vlseg4ff_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg4e8ff.v v6, (a0)			; CHECK-NEXT: vlseg4e8ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg4ff.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg4ff.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 4			%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	define <vscale x 16 x i8> @test_vlseg4ff_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %vl, <vscale x 16 x i1> %mask, i64* %outvl) {			define <vscale x 16 x i8> @test_vlseg4ff_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %vl, <vscale x 16 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv16i8:			; CHECK-LABEL: test_vlseg4ff_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vlseg4e8ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e8ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 4			%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	declare {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg2ff.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg2ff.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
	declare {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i64> @test_vlseg2ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i64> @test_vlseg2ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv1i64:			; CHECK-LABEL: test_vlseg2ff_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg2e64ff.v v7, (a0)			; CHECK-NEXT: vlseg2e64ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg2ff.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg2ff.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 2			%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	define <vscale x 1 x i64> @test_vlseg2ff_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i64> @test_vlseg2ff_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv1i64:			; CHECK-LABEL: test_vlseg2ff_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg2e64ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e64ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 2			%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg3ff.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg3ff.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i64> @test_vlseg3ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i64> @test_vlseg3ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv1i64:			; CHECK-LABEL: test_vlseg3ff_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg3e64ff.v v7, (a0)			; CHECK-NEXT: vlseg3e64ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg3ff.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg3ff.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 3			%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	define <vscale x 1 x i64> @test_vlseg3ff_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i64> @test_vlseg3ff_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv1i64:			; CHECK-LABEL: test_vlseg3ff_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg3e64ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e64ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 3			%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg4ff.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg4ff.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i64> @test_vlseg4ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i64> @test_vlseg4ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv1i64:			; CHECK-LABEL: test_vlseg4ff_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg4e64ff.v v7, (a0)			; CHECK-NEXT: vlseg4e64ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg4ff.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg4ff.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 4			%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	define <vscale x 1 x i64> @test_vlseg4ff_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i64> @test_vlseg4ff_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv1i64:			; CHECK-LABEL: test_vlseg4ff_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg4e64ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e64ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 4			%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg5ff.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg5ff.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i64> @test_vlseg5ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i64> @test_vlseg5ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv1i64:			; CHECK-LABEL: test_vlseg5ff_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg5e64ff.v v7, (a0)			; CHECK-NEXT: vlseg5e64ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg5ff.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg5ff.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 5			%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	define <vscale x 1 x i64> @test_vlseg5ff_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i64> @test_vlseg5ff_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv1i64:			; CHECK-LABEL: test_vlseg5ff_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg5e64ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e64ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 5			%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg6ff.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg6ff.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i64> @test_vlseg6ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i64> @test_vlseg6ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv1i64:			; CHECK-LABEL: test_vlseg6ff_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg6e64ff.v v7, (a0)			; CHECK-NEXT: vlseg6e64ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg6ff.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg6ff.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 6			%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	define <vscale x 1 x i64> @test_vlseg6ff_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i64> @test_vlseg6ff_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv1i64:			; CHECK-LABEL: test_vlseg6ff_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg6e64ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e64ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 6			%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg7ff.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg7ff.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i64> @test_vlseg7ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i64> @test_vlseg7ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv1i64:			; CHECK-LABEL: test_vlseg7ff_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg7e64ff.v v7, (a0)			; CHECK-NEXT: vlseg7e64ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg7ff.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg7ff.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 7			%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	define <vscale x 1 x i64> @test_vlseg7ff_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i64> @test_vlseg7ff_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv1i64:			; CHECK-LABEL: test_vlseg7ff_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg7e64ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e64ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 7			%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg8ff.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg8ff.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i64> @test_vlseg8ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i64> @test_vlseg8ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv1i64:			; CHECK-LABEL: test_vlseg8ff_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg8e64ff.v v7, (a0)			; CHECK-NEXT: vlseg8e64ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg8ff.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef ,<vscale x 1 x i64> undef ,<vscale x 1 x i64> undef, <vscale x 1 x i64> undef ,<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg8ff.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef ,<vscale x 1 x i64> undef ,<vscale x 1 x i64> undef, <vscale x 1 x i64> undef ,<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 8			%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	define <vscale x 1 x i64> @test_vlseg8ff_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i64> @test_vlseg8ff_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv1i64:			; CHECK-LABEL: test_vlseg8ff_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg8e64ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e64ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 8			%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg2ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg2ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i32> @test_vlseg2ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i32> @test_vlseg2ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv1i32:			; CHECK-LABEL: test_vlseg2ff_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v7, (a0)			; CHECK-NEXT: vlseg2e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg2ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg2ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 2			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg2ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i32> @test_vlseg2ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv1i32:			; CHECK-LABEL: test_vlseg2ff_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 2			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg3ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg3ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i32> @test_vlseg3ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i32> @test_vlseg3ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv1i32:			; CHECK-LABEL: test_vlseg3ff_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v7, (a0)			; CHECK-NEXT: vlseg3e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg3ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg3ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 3			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg3ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i32> @test_vlseg3ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv1i32:			; CHECK-LABEL: test_vlseg3ff_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 3			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg4ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg4ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i32> @test_vlseg4ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i32> @test_vlseg4ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv1i32:			; CHECK-LABEL: test_vlseg4ff_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v7, (a0)			; CHECK-NEXT: vlseg4e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg4ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg4ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 4			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg4ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i32> @test_vlseg4ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv1i32:			; CHECK-LABEL: test_vlseg4ff_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 4			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg5ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg5ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i32> @test_vlseg5ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i32> @test_vlseg5ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv1i32:			; CHECK-LABEL: test_vlseg5ff_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg5e32ff.v v7, (a0)			; CHECK-NEXT: vlseg5e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg5ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg5ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 5			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg5ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i32> @test_vlseg5ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv1i32:			; CHECK-LABEL: test_vlseg5ff_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 5			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg6ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg6ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i32> @test_vlseg6ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i32> @test_vlseg6ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv1i32:			; CHECK-LABEL: test_vlseg6ff_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg6e32ff.v v7, (a0)			; CHECK-NEXT: vlseg6e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg6ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg6ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 6			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg6ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i32> @test_vlseg6ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv1i32:			; CHECK-LABEL: test_vlseg6ff_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 6			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg7ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg7ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i32> @test_vlseg7ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i32> @test_vlseg7ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv1i32:			; CHECK-LABEL: test_vlseg7ff_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg7e32ff.v v7, (a0)			; CHECK-NEXT: vlseg7e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg7ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg7ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 7			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg7ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i32> @test_vlseg7ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv1i32:			; CHECK-LABEL: test_vlseg7ff_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 7			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg8ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg8ff.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i32> @test_vlseg8ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i32> @test_vlseg8ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv1i32:			; CHECK-LABEL: test_vlseg8ff_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg8e32ff.v v7, (a0)			; CHECK-NEXT: vlseg8e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg8ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg8ff.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 8			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlseg8ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i32> @test_vlseg8ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv1i32:			; CHECK-LABEL: test_vlseg8ff_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 8			%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	declare {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg2ff.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i64)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg2ff.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i64)
	declare {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i16> @test_vlseg2ff_nxv8i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 8 x i16> @test_vlseg2ff_nxv8i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv8i16:			; CHECK-LABEL: test_vlseg2ff_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v6, (a0)			; CHECK-NEXT: vlseg2e16ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg2ff.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg2ff.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 2			%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	define <vscale x 8 x i16> @test_vlseg2ff_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {			define <vscale x 8 x i16> @test_vlseg2ff_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv8i16:			; CHECK-LABEL: test_vlseg2ff_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e16ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 2			%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg3ff.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i64)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg3ff.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i64)
	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i16> @test_vlseg3ff_nxv8i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 8 x i16> @test_vlseg3ff_nxv8i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv8i16:			; CHECK-LABEL: test_vlseg3ff_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v6, (a0)			; CHECK-NEXT: vlseg3e16ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg3ff.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg3ff.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 3			%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	define <vscale x 8 x i16> @test_vlseg3ff_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {			define <vscale x 8 x i16> @test_vlseg3ff_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv8i16:			; CHECK-LABEL: test_vlseg3ff_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e16ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 3			%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg4ff.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i64)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg4ff.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i64)
	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i16> @test_vlseg4ff_nxv8i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 8 x i16> @test_vlseg4ff_nxv8i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv8i16:			; CHECK-LABEL: test_vlseg4ff_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v6, (a0)			; CHECK-NEXT: vlseg4e16ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg4ff.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg4ff.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 4			%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	define <vscale x 8 x i16> @test_vlseg4ff_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {			define <vscale x 8 x i16> @test_vlseg4ff_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv8i16:			; CHECK-LABEL: test_vlseg4ff_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e16ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 4			%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg2ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg2ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i8> @test_vlseg2ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x i8> @test_vlseg2ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv4i8:			; CHECK-LABEL: test_vlseg2ff_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v7, (a0)			; CHECK-NEXT: vlseg2e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg2ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg2ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 2			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg2ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x i8> @test_vlseg2ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv4i8:			; CHECK-LABEL: test_vlseg2ff_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 2			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg3ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg3ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i8> @test_vlseg3ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x i8> @test_vlseg3ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv4i8:			; CHECK-LABEL: test_vlseg3ff_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg3e8ff.v v7, (a0)			; CHECK-NEXT: vlseg3e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg3ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg3ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 3			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg3ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x i8> @test_vlseg3ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv4i8:			; CHECK-LABEL: test_vlseg3ff_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 3			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg4ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg4ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i8> @test_vlseg4ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x i8> @test_vlseg4ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv4i8:			; CHECK-LABEL: test_vlseg4ff_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg4e8ff.v v7, (a0)			; CHECK-NEXT: vlseg4e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg4ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg4ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 4			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg4ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x i8> @test_vlseg4ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv4i8:			; CHECK-LABEL: test_vlseg4ff_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 4			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg5ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg5ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i8> @test_vlseg5ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x i8> @test_vlseg5ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv4i8:			; CHECK-LABEL: test_vlseg5ff_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg5e8ff.v v7, (a0)			; CHECK-NEXT: vlseg5e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg5ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg5ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 5			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg5ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x i8> @test_vlseg5ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv4i8:			; CHECK-LABEL: test_vlseg5ff_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 5			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg6ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg6ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i8> @test_vlseg6ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x i8> @test_vlseg6ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv4i8:			; CHECK-LABEL: test_vlseg6ff_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg6e8ff.v v7, (a0)			; CHECK-NEXT: vlseg6e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg6ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg6ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 6			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg6ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x i8> @test_vlseg6ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv4i8:			; CHECK-LABEL: test_vlseg6ff_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 6			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg7ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg7ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i8> @test_vlseg7ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x i8> @test_vlseg7ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv4i8:			; CHECK-LABEL: test_vlseg7ff_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg7e8ff.v v7, (a0)			; CHECK-NEXT: vlseg7e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg7ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg7ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 7			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg7ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x i8> @test_vlseg7ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv4i8:			; CHECK-LABEL: test_vlseg7ff_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 7			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg8ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg8ff.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i8> @test_vlseg8ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x i8> @test_vlseg8ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv4i8:			; CHECK-LABEL: test_vlseg8ff_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg8e8ff.v v7, (a0)			; CHECK-NEXT: vlseg8e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg8ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg8ff.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 8			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlseg8ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x i8> @test_vlseg8ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv4i8:			; CHECK-LABEL: test_vlseg8ff_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 8			%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg2ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg2ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i16> @test_vlseg2ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i16> @test_vlseg2ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv1i16:			; CHECK-LABEL: test_vlseg2ff_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0)			; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg2ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg2ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 2			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg2ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i16> @test_vlseg2ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv1i16:			; CHECK-LABEL: test_vlseg2ff_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 2			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg3ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg3ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i16> @test_vlseg3ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i16> @test_vlseg3ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv1i16:			; CHECK-LABEL: test_vlseg3ff_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0)			; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg3ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg3ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 3			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg3ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i16> @test_vlseg3ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv1i16:			; CHECK-LABEL: test_vlseg3ff_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 3			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg4ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg4ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i16> @test_vlseg4ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i16> @test_vlseg4ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv1i16:			; CHECK-LABEL: test_vlseg4ff_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0)			; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg4ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg4ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 4			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg4ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i16> @test_vlseg4ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv1i16:			; CHECK-LABEL: test_vlseg4ff_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 4			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg5ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg5ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i16> @test_vlseg5ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i16> @test_vlseg5ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv1i16:			; CHECK-LABEL: test_vlseg5ff_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0)			; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg5ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg5ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 5			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg5ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i16> @test_vlseg5ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv1i16:			; CHECK-LABEL: test_vlseg5ff_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 5			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg6ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg6ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i16> @test_vlseg6ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i16> @test_vlseg6ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv1i16:			; CHECK-LABEL: test_vlseg6ff_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0)			; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg6ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg6ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 6			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg6ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i16> @test_vlseg6ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv1i16:			; CHECK-LABEL: test_vlseg6ff_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 6			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg7ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg7ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i16> @test_vlseg7ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i16> @test_vlseg7ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv1i16:			; CHECK-LABEL: test_vlseg7ff_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0)			; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg7ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg7ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 7			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg7ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i16> @test_vlseg7ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv1i16:			; CHECK-LABEL: test_vlseg7ff_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 7			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg8ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg8ff.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i16> @test_vlseg8ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i16> @test_vlseg8ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv1i16:			; CHECK-LABEL: test_vlseg8ff_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0)			; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg8ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg8ff.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 8			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlseg8ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i16> @test_vlseg8ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv1i16:			; CHECK-LABEL: test_vlseg8ff_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 8			%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg2ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg2ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i32> @test_vlseg2ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i32> @test_vlseg2ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv2i32:			; CHECK-LABEL: test_vlseg2ff_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v7, (a0)			; CHECK-NEXT: vlseg2e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg2ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg2ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 2			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg2ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i32> @test_vlseg2ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv2i32:			; CHECK-LABEL: test_vlseg2ff_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 2			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg3ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg3ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i32> @test_vlseg3ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i32> @test_vlseg3ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv2i32:			; CHECK-LABEL: test_vlseg3ff_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v7, (a0)			; CHECK-NEXT: vlseg3e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg3ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg3ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 3			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg3ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i32> @test_vlseg3ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv2i32:			; CHECK-LABEL: test_vlseg3ff_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 3			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg4ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg4ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i32> @test_vlseg4ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i32> @test_vlseg4ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv2i32:			; CHECK-LABEL: test_vlseg4ff_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v7, (a0)			; CHECK-NEXT: vlseg4e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg4ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg4ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 4			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg4ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i32> @test_vlseg4ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv2i32:			; CHECK-LABEL: test_vlseg4ff_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 4			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg5ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg5ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg5ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg5ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i32> @test_vlseg5ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i32> @test_vlseg5ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv2i32:			; CHECK-LABEL: test_vlseg5ff_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg5e32ff.v v7, (a0)			; CHECK-NEXT: vlseg5e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg5ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg5ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 5			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg5ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i32> @test_vlseg5ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv2i32:			; CHECK-LABEL: test_vlseg5ff_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg5ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg5ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 5			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg6ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg6ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg6ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg6ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i32> @test_vlseg6ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i32> @test_vlseg6ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv2i32:			; CHECK-LABEL: test_vlseg6ff_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg6e32ff.v v7, (a0)			; CHECK-NEXT: vlseg6e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg6ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg6ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 6			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg6ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i32> @test_vlseg6ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv2i32:			; CHECK-LABEL: test_vlseg6ff_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg6ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg6ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 6			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg7ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg7ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg7ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg7ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i32> @test_vlseg7ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i32> @test_vlseg7ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv2i32:			; CHECK-LABEL: test_vlseg7ff_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg7e32ff.v v7, (a0)			; CHECK-NEXT: vlseg7e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg7ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg7ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 7			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg7ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i32> @test_vlseg7ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv2i32:			; CHECK-LABEL: test_vlseg7ff_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg7ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg7ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 7			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg8ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg8ff.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg8ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg8ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i32> @test_vlseg8ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i32> @test_vlseg8ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv2i32:			; CHECK-LABEL: test_vlseg8ff_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg8e32ff.v v7, (a0)			; CHECK-NEXT: vlseg8e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg8ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg8ff.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 8			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlseg8ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i32> @test_vlseg8ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv2i32:			; CHECK-LABEL: test_vlseg8ff_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg8ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg8ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 8			%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg2ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg2ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i8> @test_vlseg2ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 8 x i8> @test_vlseg2ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv8i8:			; CHECK-LABEL: test_vlseg2ff_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v7, (a0)			; CHECK-NEXT: vlseg2e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg2ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg2ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 2			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg2ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {			define <vscale x 8 x i8> @test_vlseg2ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv8i8:			; CHECK-LABEL: test_vlseg2ff_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 2			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg3ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg3ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i8> @test_vlseg3ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 8 x i8> @test_vlseg3ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv8i8:			; CHECK-LABEL: test_vlseg3ff_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg3e8ff.v v7, (a0)			; CHECK-NEXT: vlseg3e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg3ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg3ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 3			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg3ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {			define <vscale x 8 x i8> @test_vlseg3ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv8i8:			; CHECK-LABEL: test_vlseg3ff_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 3			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg4ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg4ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i8> @test_vlseg4ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 8 x i8> @test_vlseg4ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv8i8:			; CHECK-LABEL: test_vlseg4ff_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg4e8ff.v v7, (a0)			; CHECK-NEXT: vlseg4e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg4ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg4ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 4			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg4ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {			define <vscale x 8 x i8> @test_vlseg4ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv8i8:			; CHECK-LABEL: test_vlseg4ff_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 4			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg5ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg5ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i8> @test_vlseg5ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 8 x i8> @test_vlseg5ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv8i8:			; CHECK-LABEL: test_vlseg5ff_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg5e8ff.v v7, (a0)			; CHECK-NEXT: vlseg5e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg5ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg5ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 5			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg5ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {			define <vscale x 8 x i8> @test_vlseg5ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv8i8:			; CHECK-LABEL: test_vlseg5ff_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 5			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg6ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg6ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i8> @test_vlseg6ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 8 x i8> @test_vlseg6ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv8i8:			; CHECK-LABEL: test_vlseg6ff_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg6e8ff.v v7, (a0)			; CHECK-NEXT: vlseg6e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg6ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg6ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 6			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg6ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {			define <vscale x 8 x i8> @test_vlseg6ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv8i8:			; CHECK-LABEL: test_vlseg6ff_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 6			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg7ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg7ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i8> @test_vlseg7ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 8 x i8> @test_vlseg7ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv8i8:			; CHECK-LABEL: test_vlseg7ff_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg7e8ff.v v7, (a0)			; CHECK-NEXT: vlseg7e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg7ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg7ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 7			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg7ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {			define <vscale x 8 x i8> @test_vlseg7ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv8i8:			; CHECK-LABEL: test_vlseg7ff_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 7			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg8ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg8ff.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i8> @test_vlseg8ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 8 x i8> @test_vlseg8ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv8i8:			; CHECK-LABEL: test_vlseg8ff_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg8e8ff.v v7, (a0)			; CHECK-NEXT: vlseg8e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg8ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg8ff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 8			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlseg8ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {			define <vscale x 8 x i8> @test_vlseg8ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv8i8:			; CHECK-LABEL: test_vlseg8ff_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 8			%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	declare {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} @llvm.riscv.vlseg2ff.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64* , i64)			declare {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} @llvm.riscv.vlseg2ff.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64* , i64)
	declare {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i64> @test_vlseg2ff_nxv4i64(i64* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x i64> @test_vlseg2ff_nxv4i64(i64* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv4i64:			; CHECK-LABEL: test_vlseg2ff_nxv4i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
	; CHECK-NEXT: vlseg2e64ff.v v4, (a0)			; CHECK-NEXT: vlseg2e64ff.v v4, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} @llvm.riscv.vlseg2ff.nxv4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} @llvm.riscv.vlseg2ff.nxv4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} %0, 2			%2 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i64> %1			ret <vscale x 4 x i64> %1
	}			}

	define <vscale x 4 x i64> @test_vlseg2ff_mask_nxv4i64(<vscale x 4 x i64> %val, i64* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x i64> @test_vlseg2ff_mask_nxv4i64(<vscale x 4 x i64> %val, i64* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv4i64:			; CHECK-LABEL: test_vlseg2ff_mask_nxv4i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv4r.v v4, v8			; CHECK-NEXT: vmv4r.v v4, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
	; CHECK-NEXT: vlseg2e64ff.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e64ff.v v4, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} %0, 2			%2 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i64> %1			ret <vscale x 4 x i64> %1
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg2ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg2ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i16> @test_vlseg2ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x i16> @test_vlseg2ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv4i16:			; CHECK-LABEL: test_vlseg2ff_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0)			; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg2ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg2ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 2			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg2ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x i16> @test_vlseg2ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv4i16:			; CHECK-LABEL: test_vlseg2ff_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 2			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg3ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg3ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i16> @test_vlseg3ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x i16> @test_vlseg3ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv4i16:			; CHECK-LABEL: test_vlseg3ff_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0)			; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg3ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg3ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 3			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg3ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x i16> @test_vlseg3ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv4i16:			; CHECK-LABEL: test_vlseg3ff_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 3			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg4ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg4ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i16> @test_vlseg4ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x i16> @test_vlseg4ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv4i16:			; CHECK-LABEL: test_vlseg4ff_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0)			; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg4ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg4ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 4			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg4ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x i16> @test_vlseg4ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv4i16:			; CHECK-LABEL: test_vlseg4ff_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 4			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg5ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg5ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg5ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg5ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i16> @test_vlseg5ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x i16> @test_vlseg5ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv4i16:			; CHECK-LABEL: test_vlseg5ff_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0)			; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg5ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg5ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 5			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg5ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x i16> @test_vlseg5ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv4i16:			; CHECK-LABEL: test_vlseg5ff_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg5ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg5ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 5			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg6ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg6ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg6ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg6ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i16> @test_vlseg6ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x i16> @test_vlseg6ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv4i16:			; CHECK-LABEL: test_vlseg6ff_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0)			; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg6ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg6ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 6			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg6ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x i16> @test_vlseg6ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv4i16:			; CHECK-LABEL: test_vlseg6ff_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg6ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg6ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 6			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg7ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg7ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg7ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg7ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i16> @test_vlseg7ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x i16> @test_vlseg7ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv4i16:			; CHECK-LABEL: test_vlseg7ff_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0)			; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg7ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg7ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 7			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg7ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x i16> @test_vlseg7ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv4i16:			; CHECK-LABEL: test_vlseg7ff_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg7ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg7ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 7			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg8ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg8ff.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg8ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg8ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i16> @test_vlseg8ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x i16> @test_vlseg8ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv4i16:			; CHECK-LABEL: test_vlseg8ff_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0)			; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg8ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg8ff.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 8			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlseg8ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x i16> @test_vlseg8ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv4i16:			; CHECK-LABEL: test_vlseg8ff_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg8ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg8ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 8			%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg2ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg2ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i8> @test_vlseg2ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i8> @test_vlseg2ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv1i8:			; CHECK-LABEL: test_vlseg2ff_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v7, (a0)			; CHECK-NEXT: vlseg2e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg2ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg2ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 2			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg2ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i8> @test_vlseg2ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv1i8:			; CHECK-LABEL: test_vlseg2ff_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 2			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg3ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg3ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i8> @test_vlseg3ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i8> @test_vlseg3ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv1i8:			; CHECK-LABEL: test_vlseg3ff_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg3e8ff.v v7, (a0)			; CHECK-NEXT: vlseg3e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg3ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg3ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 3			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg3ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i8> @test_vlseg3ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv1i8:			; CHECK-LABEL: test_vlseg3ff_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 3			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg4ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg4ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i8> @test_vlseg4ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i8> @test_vlseg4ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv1i8:			; CHECK-LABEL: test_vlseg4ff_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg4e8ff.v v7, (a0)			; CHECK-NEXT: vlseg4e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg4ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg4ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 4			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg4ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i8> @test_vlseg4ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv1i8:			; CHECK-LABEL: test_vlseg4ff_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 4			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg5ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg5ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i8> @test_vlseg5ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i8> @test_vlseg5ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv1i8:			; CHECK-LABEL: test_vlseg5ff_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg5e8ff.v v7, (a0)			; CHECK-NEXT: vlseg5e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg5ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg5ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 5			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg5ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i8> @test_vlseg5ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv1i8:			; CHECK-LABEL: test_vlseg5ff_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 5			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg6ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg6ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i8> @test_vlseg6ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i8> @test_vlseg6ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv1i8:			; CHECK-LABEL: test_vlseg6ff_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg6e8ff.v v7, (a0)			; CHECK-NEXT: vlseg6e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg6ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg6ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 6			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg6ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i8> @test_vlseg6ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv1i8:			; CHECK-LABEL: test_vlseg6ff_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 6			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg7ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg7ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i8> @test_vlseg7ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i8> @test_vlseg7ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv1i8:			; CHECK-LABEL: test_vlseg7ff_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg7e8ff.v v7, (a0)			; CHECK-NEXT: vlseg7e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg7ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg7ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 7			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg7ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i8> @test_vlseg7ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv1i8:			; CHECK-LABEL: test_vlseg7ff_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 7			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg8ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg8ff.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i8> @test_vlseg8ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x i8> @test_vlseg8ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv1i8:			; CHECK-LABEL: test_vlseg8ff_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg8e8ff.v v7, (a0)			; CHECK-NEXT: vlseg8e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg8ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg8ff.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 8			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlseg8ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x i8> @test_vlseg8ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv1i8:			; CHECK-LABEL: test_vlseg8ff_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 8			%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg2ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg2ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i8> @test_vlseg2ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i8> @test_vlseg2ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv2i8:			; CHECK-LABEL: test_vlseg2ff_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v7, (a0)			; CHECK-NEXT: vlseg2e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg2ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg2ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 2			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg2ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i8> @test_vlseg2ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv2i8:			; CHECK-LABEL: test_vlseg2ff_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 2			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg3ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg3ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i8> @test_vlseg3ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i8> @test_vlseg3ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv2i8:			; CHECK-LABEL: test_vlseg3ff_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg3e8ff.v v7, (a0)			; CHECK-NEXT: vlseg3e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg3ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg3ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 3			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg3ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i8> @test_vlseg3ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv2i8:			; CHECK-LABEL: test_vlseg3ff_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 3			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg4ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg4ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i8> @test_vlseg4ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i8> @test_vlseg4ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv2i8:			; CHECK-LABEL: test_vlseg4ff_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg4e8ff.v v7, (a0)			; CHECK-NEXT: vlseg4e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg4ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg4ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 4			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg4ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i8> @test_vlseg4ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv2i8:			; CHECK-LABEL: test_vlseg4ff_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 4			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg5ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg5ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i8> @test_vlseg5ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i8> @test_vlseg5ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv2i8:			; CHECK-LABEL: test_vlseg5ff_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg5e8ff.v v7, (a0)			; CHECK-NEXT: vlseg5e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg5ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg5ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 5			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg5ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i8> @test_vlseg5ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv2i8:			; CHECK-LABEL: test_vlseg5ff_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 5			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg6ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg6ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i8> @test_vlseg6ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i8> @test_vlseg6ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv2i8:			; CHECK-LABEL: test_vlseg6ff_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg6e8ff.v v7, (a0)			; CHECK-NEXT: vlseg6e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg6ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg6ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 6			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg6ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i8> @test_vlseg6ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv2i8:			; CHECK-LABEL: test_vlseg6ff_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 6			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg7ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg7ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i8> @test_vlseg7ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i8> @test_vlseg7ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv2i8:			; CHECK-LABEL: test_vlseg7ff_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg7e8ff.v v7, (a0)			; CHECK-NEXT: vlseg7e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg7ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg7ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 7			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg7ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i8> @test_vlseg7ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv2i8:			; CHECK-LABEL: test_vlseg7ff_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 7			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg8ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg8ff.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i8> @test_vlseg8ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i8> @test_vlseg8ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv2i8:			; CHECK-LABEL: test_vlseg8ff_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg8e8ff.v v7, (a0)			; CHECK-NEXT: vlseg8e8ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg8ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg8ff.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 8			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlseg8ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i8> @test_vlseg8ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv2i8:			; CHECK-LABEL: test_vlseg8ff_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 8			%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	declare {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} @llvm.riscv.vlseg2ff.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32* , i64)			declare {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} @llvm.riscv.vlseg2ff.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32* , i64)
	declare {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i32> @test_vlseg2ff_nxv8i32(i32* %base, i64 %vl, i64* %outvl) {			define <vscale x 8 x i32> @test_vlseg2ff_nxv8i32(i32* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv8i32:			; CHECK-LABEL: test_vlseg2ff_nxv8i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v4, (a0)			; CHECK-NEXT: vlseg2e32ff.v v4, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} @llvm.riscv.vlseg2ff.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i64 %vl)			%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} @llvm.riscv.vlseg2ff.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} %0, 2			%2 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i32> %1			ret <vscale x 8 x i32> %1
	}			}

	define <vscale x 8 x i32> @test_vlseg2ff_mask_nxv8i32(<vscale x 8 x i32> %val, i32* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {			define <vscale x 8 x i32> @test_vlseg2ff_mask_nxv8i32(<vscale x 8 x i32> %val, i32* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv8i32:			; CHECK-LABEL: test_vlseg2ff_mask_nxv8i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv4r.v v4, v8			; CHECK-NEXT: vmv4r.v v4, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e32ff.v v4, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} %0, 2			%2 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x i32> %1			ret <vscale x 8 x i32> %1
	}			}

	declare {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} @llvm.riscv.vlseg2ff.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8* , i64)			declare {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} @llvm.riscv.vlseg2ff.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8* , i64)
	declare {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i1>, i64, i64)			declare {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i1>, i64, i64)

	define <vscale x 32 x i8> @test_vlseg2ff_nxv32i8(i8* %base, i64 %vl, i64* %outvl) {			define <vscale x 32 x i8> @test_vlseg2ff_nxv32i8(i8* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv32i8:			; CHECK-LABEL: test_vlseg2ff_nxv32i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v4, (a0)			; CHECK-NEXT: vlseg2e8ff.v v4, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} @llvm.riscv.vlseg2ff.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i8> undef, i8* %base, i64 %vl)			%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} @llvm.riscv.vlseg2ff.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i8> undef, i8* %base, i64 %vl)
	%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} %0, 2			%2 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 32 x i8> %1			ret <vscale x 32 x i8> %1
	}			}

	define <vscale x 32 x i8> @test_vlseg2ff_mask_nxv32i8(<vscale x 32 x i8> %val, i8* %base, i64 %vl, <vscale x 32 x i1> %mask, i64* %outvl) {			define <vscale x 32 x i8> @test_vlseg2ff_mask_nxv32i8(<vscale x 32 x i8> %val, i8* %base, i64 %vl, <vscale x 32 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv32i8:			; CHECK-LABEL: test_vlseg2ff_mask_nxv32i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv4r.v v4, v8			; CHECK-NEXT: vmv4r.v v4, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
	; CHECK-NEXT: vlseg2e8ff.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e8ff.v v4, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} %0, 1			%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} %0, 1
	%2 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} %0, 2			%2 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 32 x i8> %1			ret <vscale x 32 x i8> %1
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg2ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg2ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i16> @test_vlseg2ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i16> @test_vlseg2ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv2i16:			; CHECK-LABEL: test_vlseg2ff_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0)			; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg2ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg2ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 2			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg2ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i16> @test_vlseg2ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv2i16:			; CHECK-LABEL: test_vlseg2ff_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 2			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg3ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg3ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i16> @test_vlseg3ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i16> @test_vlseg3ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv2i16:			; CHECK-LABEL: test_vlseg3ff_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0)			; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg3ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg3ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 3			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg3ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i16> @test_vlseg3ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv2i16:			; CHECK-LABEL: test_vlseg3ff_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 3			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg4ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg4ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i16> @test_vlseg4ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i16> @test_vlseg4ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv2i16:			; CHECK-LABEL: test_vlseg4ff_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0)			; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg4ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg4ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 4			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg4ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i16> @test_vlseg4ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv2i16:			; CHECK-LABEL: test_vlseg4ff_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 4			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg5ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg5ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg5ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg5ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i16> @test_vlseg5ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i16> @test_vlseg5ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv2i16:			; CHECK-LABEL: test_vlseg5ff_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0)			; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg5ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg5ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 5			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg5ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i16> @test_vlseg5ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv2i16:			; CHECK-LABEL: test_vlseg5ff_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg5ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg5ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 5			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg6ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg6ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg6ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg6ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i16> @test_vlseg6ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i16> @test_vlseg6ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv2i16:			; CHECK-LABEL: test_vlseg6ff_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0)			; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg6ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg6ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 6			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg6ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i16> @test_vlseg6ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv2i16:			; CHECK-LABEL: test_vlseg6ff_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg6ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg6ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 6			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg7ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg7ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg7ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg7ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i16> @test_vlseg7ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i16> @test_vlseg7ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv2i16:			; CHECK-LABEL: test_vlseg7ff_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0)			; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg7ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg7ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 7			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg7ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i16> @test_vlseg7ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv2i16:			; CHECK-LABEL: test_vlseg7ff_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg7ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg7ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 7			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg8ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg8ff.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg8ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg8ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i16> @test_vlseg8ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i16> @test_vlseg8ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv2i16:			; CHECK-LABEL: test_vlseg8ff_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0)			; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg8ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg8ff.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 8			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlseg8ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i16> @test_vlseg8ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv2i16:			; CHECK-LABEL: test_vlseg8ff_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg8ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg8ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 8			%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	declare {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg2ff.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64* , i64)			declare {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg2ff.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64* , i64)
	declare {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i64> @test_vlseg2ff_nxv2i64(i64* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i64> @test_vlseg2ff_nxv2i64(i64* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv2i64:			; CHECK-LABEL: test_vlseg2ff_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg2e64ff.v v6, (a0)			; CHECK-NEXT: vlseg2e64ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg2ff.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg2ff.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 2			%2 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i64> %1			ret <vscale x 2 x i64> %1
	}			}

	define <vscale x 2 x i64> @test_vlseg2ff_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i64> @test_vlseg2ff_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv2i64:			; CHECK-LABEL: test_vlseg2ff_mask_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg2e64ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e64ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 2			%2 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i64> %1			ret <vscale x 2 x i64> %1
	}			}

	declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg3ff.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64* , i64)			declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg3ff.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64* , i64)
	declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i64> @test_vlseg3ff_nxv2i64(i64* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i64> @test_vlseg3ff_nxv2i64(i64* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv2i64:			; CHECK-LABEL: test_vlseg3ff_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg3e64ff.v v6, (a0)			; CHECK-NEXT: vlseg3e64ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg3ff.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg3ff.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 3			%2 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i64> %1			ret <vscale x 2 x i64> %1
	}			}

	define <vscale x 2 x i64> @test_vlseg3ff_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i64> @test_vlseg3ff_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv2i64:			; CHECK-LABEL: test_vlseg3ff_mask_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg3e64ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e64ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 3			%2 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i64> %1			ret <vscale x 2 x i64> %1
	}			}

	declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg4ff.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64* , i64)			declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg4ff.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64* , i64)
	declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i64> @test_vlseg4ff_nxv2i64(i64* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x i64> @test_vlseg4ff_nxv2i64(i64* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv2i64:			; CHECK-LABEL: test_vlseg4ff_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg4e64ff.v v6, (a0)			; CHECK-NEXT: vlseg4e64ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg4ff.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %vl)			%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg4ff.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 4			%2 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i64> %1			ret <vscale x 2 x i64> %1
	}			}

	define <vscale x 2 x i64> @test_vlseg4ff_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x i64> @test_vlseg4ff_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv2i64:			; CHECK-LABEL: test_vlseg4ff_mask_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg4e64ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e64ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 4			%2 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x i64> %1			ret <vscale x 2 x i64> %1
	}			}

	declare {<vscale x 16 x half>,<vscale x 16 x half>, i64} @llvm.riscv.vlseg2ff.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half* , i64)			declare {<vscale x 16 x half>,<vscale x 16 x half>, i64} @llvm.riscv.vlseg2ff.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half* , i64)
	declare {<vscale x 16 x half>,<vscale x 16 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i1>, i64, i64)			declare {<vscale x 16 x half>,<vscale x 16 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i1>, i64, i64)

	define <vscale x 16 x half> @test_vlseg2ff_nxv16f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 16 x half> @test_vlseg2ff_nxv16f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv16f16:			; CHECK-LABEL: test_vlseg2ff_nxv16f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v4, (a0)			; CHECK-NEXT: vlseg2e16ff.v v4, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>, i64} @llvm.riscv.vlseg2ff.nxv16f16(<vscale x 16 x half> undef, <vscale x 16 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>, i64} @llvm.riscv.vlseg2ff.nxv16f16(<vscale x 16 x half> undef, <vscale x 16 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i64} %0, 2			%2 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 16 x half> %1			ret <vscale x 16 x half> %1
	}			}

	define <vscale x 16 x half> @test_vlseg2ff_mask_nxv16f16(<vscale x 16 x half> %val, half* %base, i64 %vl, <vscale x 16 x i1> %mask, i64* %outvl) {			define <vscale x 16 x half> @test_vlseg2ff_mask_nxv16f16(<vscale x 16 x half> %val, half* %base, i64 %vl, <vscale x 16 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv16f16:			; CHECK-LABEL: test_vlseg2ff_mask_nxv16f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv4r.v v4, v8			; CHECK-NEXT: vmv4r.v v4, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i64} %0, 2			%2 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 16 x half> %1			ret <vscale x 16 x half> %1
	}			}

	declare {<vscale x 4 x double>,<vscale x 4 x double>, i64} @llvm.riscv.vlseg2ff.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double* , i64)			declare {<vscale x 4 x double>,<vscale x 4 x double>, i64} @llvm.riscv.vlseg2ff.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double* , i64)
	declare {<vscale x 4 x double>,<vscale x 4 x double>, i64} @llvm.riscv.vlseg2ff.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x double>,<vscale x 4 x double>, i64} @llvm.riscv.vlseg2ff.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x double> @test_vlseg2ff_nxv4f64(double* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x double> @test_vlseg2ff_nxv4f64(double* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv4f64:			; CHECK-LABEL: test_vlseg2ff_nxv4f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
	; CHECK-NEXT: vlseg2e64ff.v v4, (a0)			; CHECK-NEXT: vlseg2e64ff.v v4, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>, i64} @llvm.riscv.vlseg2ff.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>, i64} @llvm.riscv.vlseg2ff.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i64} %0, 2			%2 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x double> %1			ret <vscale x 4 x double> %1
	}			}

	define <vscale x 4 x double> @test_vlseg2ff_mask_nxv4f64(<vscale x 4 x double> %val, double* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x double> @test_vlseg2ff_mask_nxv4f64(<vscale x 4 x double> %val, double* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv4f64:			; CHECK-LABEL: test_vlseg2ff_mask_nxv4f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv4r.v v4, v8			; CHECK-NEXT: vmv4r.v v4, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
	; CHECK-NEXT: vlseg2e64ff.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e64ff.v v4, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>, i64} @llvm.riscv.vlseg2ff.mask.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>, i64} @llvm.riscv.vlseg2ff.mask.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i64} %0, 2			%2 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x double> %1			ret <vscale x 4 x double> %1
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg2ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg2ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
	declare {<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg2ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg2ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x double> @test_vlseg2ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x double> @test_vlseg2ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv1f64:			; CHECK-LABEL: test_vlseg2ff_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg2e64ff.v v7, (a0)			; CHECK-NEXT: vlseg2e64ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg2ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg2ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 2			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg2ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x double> @test_vlseg2ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv1f64:			; CHECK-LABEL: test_vlseg2ff_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg2e64ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e64ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg2ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg2ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 2			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg3ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg3ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg3ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg3ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x double> @test_vlseg3ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x double> @test_vlseg3ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv1f64:			; CHECK-LABEL: test_vlseg3ff_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg3e64ff.v v7, (a0)			; CHECK-NEXT: vlseg3e64ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg3ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg3ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 3			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg3ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x double> @test_vlseg3ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv1f64:			; CHECK-LABEL: test_vlseg3ff_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg3e64ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e64ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg3ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg3ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 3			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg4ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg4ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg4ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg4ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x double> @test_vlseg4ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x double> @test_vlseg4ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv1f64:			; CHECK-LABEL: test_vlseg4ff_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg4e64ff.v v7, (a0)			; CHECK-NEXT: vlseg4e64ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg4ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg4ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 4			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg4ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x double> @test_vlseg4ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv1f64:			; CHECK-LABEL: test_vlseg4ff_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg4e64ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e64ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg4ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg4ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 4			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg5ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg5ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg5ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg5ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x double> @test_vlseg5ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x double> @test_vlseg5ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv1f64:			; CHECK-LABEL: test_vlseg5ff_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg5e64ff.v v7, (a0)			; CHECK-NEXT: vlseg5e64ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg5ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg5ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 5			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg5ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x double> @test_vlseg5ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv1f64:			; CHECK-LABEL: test_vlseg5ff_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg5e64ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e64ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg5ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg5ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 5			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg6ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg6ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg6ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg6ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x double> @test_vlseg6ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x double> @test_vlseg6ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv1f64:			; CHECK-LABEL: test_vlseg6ff_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg6e64ff.v v7, (a0)			; CHECK-NEXT: vlseg6e64ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg6ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg6ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 6			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg6ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x double> @test_vlseg6ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv1f64:			; CHECK-LABEL: test_vlseg6ff_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg6e64ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e64ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg6ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg6ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 6			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg7ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg7ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg7ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg7ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x double> @test_vlseg7ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x double> @test_vlseg7ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv1f64:			; CHECK-LABEL: test_vlseg7ff_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg7e64ff.v v7, (a0)			; CHECK-NEXT: vlseg7e64ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg7ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg7ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 7			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg7ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x double> @test_vlseg7ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv1f64:			; CHECK-LABEL: test_vlseg7ff_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg7e64ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e64ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg7ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg7ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 7			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg8ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg8ff.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg8ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg8ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x double> @test_vlseg8ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x double> @test_vlseg8ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv1f64:			; CHECK-LABEL: test_vlseg8ff_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg8e64ff.v v7, (a0)			; CHECK-NEXT: vlseg8e64ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg8ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg8ff.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 8			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlseg8ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x double> @test_vlseg8ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv1f64:			; CHECK-LABEL: test_vlseg8ff_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vlseg8e64ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e64ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg8ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg8ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 8			%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg2ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg2ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
	declare {<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x float> @test_vlseg2ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x float> @test_vlseg2ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv2f32:			; CHECK-LABEL: test_vlseg2ff_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v7, (a0)			; CHECK-NEXT: vlseg2e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg2ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg2ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 2			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg2ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x float> @test_vlseg2ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv2f32:			; CHECK-LABEL: test_vlseg2ff_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 2			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg3ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg3ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg3ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg3ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x float> @test_vlseg3ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x float> @test_vlseg3ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv2f32:			; CHECK-LABEL: test_vlseg3ff_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v7, (a0)			; CHECK-NEXT: vlseg3e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg3ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg3ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 3			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg3ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x float> @test_vlseg3ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv2f32:			; CHECK-LABEL: test_vlseg3ff_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg3ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg3ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 3			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg4ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg4ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg4ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg4ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x float> @test_vlseg4ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x float> @test_vlseg4ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv2f32:			; CHECK-LABEL: test_vlseg4ff_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v7, (a0)			; CHECK-NEXT: vlseg4e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg4ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg4ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 4			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg4ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x float> @test_vlseg4ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv2f32:			; CHECK-LABEL: test_vlseg4ff_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg4ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg4ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 4			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg5ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg5ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg5ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg5ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x float> @test_vlseg5ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x float> @test_vlseg5ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv2f32:			; CHECK-LABEL: test_vlseg5ff_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg5e32ff.v v7, (a0)			; CHECK-NEXT: vlseg5e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg5ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg5ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 5			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg5ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x float> @test_vlseg5ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv2f32:			; CHECK-LABEL: test_vlseg5ff_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg5ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg5ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 5			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg6ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg6ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg6ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg6ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x float> @test_vlseg6ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x float> @test_vlseg6ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv2f32:			; CHECK-LABEL: test_vlseg6ff_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg6e32ff.v v7, (a0)			; CHECK-NEXT: vlseg6e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg6ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg6ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 6			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg6ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x float> @test_vlseg6ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv2f32:			; CHECK-LABEL: test_vlseg6ff_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg6ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg6ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 6			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg7ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg7ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg7ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg7ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x float> @test_vlseg7ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x float> @test_vlseg7ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv2f32:			; CHECK-LABEL: test_vlseg7ff_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg7e32ff.v v7, (a0)			; CHECK-NEXT: vlseg7e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg7ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg7ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 7			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg7ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x float> @test_vlseg7ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv2f32:			; CHECK-LABEL: test_vlseg7ff_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg7ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg7ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 7			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg8ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg8ff.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg8ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg8ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x float> @test_vlseg8ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x float> @test_vlseg8ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv2f32:			; CHECK-LABEL: test_vlseg8ff_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg8e32ff.v v7, (a0)			; CHECK-NEXT: vlseg8e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg8ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg8ff.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 8			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlseg8ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x float> @test_vlseg8ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv2f32:			; CHECK-LABEL: test_vlseg8ff_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg8ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg8ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 8			%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg2ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg2ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
	declare {<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x half> @test_vlseg2ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x half> @test_vlseg2ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv1f16:			; CHECK-LABEL: test_vlseg2ff_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0)			; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg2ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg2ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 2			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg2ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x half> @test_vlseg2ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv1f16:			; CHECK-LABEL: test_vlseg2ff_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 2			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg3ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg3ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x half> @test_vlseg3ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x half> @test_vlseg3ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv1f16:			; CHECK-LABEL: test_vlseg3ff_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0)			; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg3ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg3ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 3			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg3ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x half> @test_vlseg3ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv1f16:			; CHECK-LABEL: test_vlseg3ff_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 3			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg4ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg4ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x half> @test_vlseg4ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x half> @test_vlseg4ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv1f16:			; CHECK-LABEL: test_vlseg4ff_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0)			; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg4ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg4ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 4			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg4ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x half> @test_vlseg4ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv1f16:			; CHECK-LABEL: test_vlseg4ff_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 4			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg5ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg5ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg5ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg5ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x half> @test_vlseg5ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x half> @test_vlseg5ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv1f16:			; CHECK-LABEL: test_vlseg5ff_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0)			; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg5ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg5ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 5			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg5ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x half> @test_vlseg5ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv1f16:			; CHECK-LABEL: test_vlseg5ff_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg5ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg5ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 5			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg6ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg6ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg6ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg6ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x half> @test_vlseg6ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x half> @test_vlseg6ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv1f16:			; CHECK-LABEL: test_vlseg6ff_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0)			; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg6ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg6ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 6			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg6ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x half> @test_vlseg6ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv1f16:			; CHECK-LABEL: test_vlseg6ff_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg6ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg6ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 6			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg7ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg7ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg7ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg7ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x half> @test_vlseg7ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x half> @test_vlseg7ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv1f16:			; CHECK-LABEL: test_vlseg7ff_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0)			; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg7ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg7ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 7			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg7ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x half> @test_vlseg7ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv1f16:			; CHECK-LABEL: test_vlseg7ff_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg7ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg7ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 7			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg8ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg8ff.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg8ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg8ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x half> @test_vlseg8ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x half> @test_vlseg8ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv1f16:			; CHECK-LABEL: test_vlseg8ff_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0)			; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg8ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg8ff.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 8			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlseg8ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x half> @test_vlseg8ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv1f16:			; CHECK-LABEL: test_vlseg8ff_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg8ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg8ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 8			%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg2ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg2ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
	declare {<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x float> @test_vlseg2ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x float> @test_vlseg2ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv1f32:			; CHECK-LABEL: test_vlseg2ff_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v7, (a0)			; CHECK-NEXT: vlseg2e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg2ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg2ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 2			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg2ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x float> @test_vlseg2ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv1f32:			; CHECK-LABEL: test_vlseg2ff_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 2			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg3ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg3ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg3ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg3ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x float> @test_vlseg3ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x float> @test_vlseg3ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv1f32:			; CHECK-LABEL: test_vlseg3ff_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v7, (a0)			; CHECK-NEXT: vlseg3e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg3ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg3ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 3			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg3ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x float> @test_vlseg3ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv1f32:			; CHECK-LABEL: test_vlseg3ff_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg3ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg3ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 3			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg4ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg4ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg4ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg4ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x float> @test_vlseg4ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x float> @test_vlseg4ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv1f32:			; CHECK-LABEL: test_vlseg4ff_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v7, (a0)			; CHECK-NEXT: vlseg4e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg4ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg4ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 4			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg4ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x float> @test_vlseg4ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv1f32:			; CHECK-LABEL: test_vlseg4ff_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg4ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg4ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 4			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg5ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg5ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg5ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg5ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x float> @test_vlseg5ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x float> @test_vlseg5ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv1f32:			; CHECK-LABEL: test_vlseg5ff_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg5e32ff.v v7, (a0)			; CHECK-NEXT: vlseg5e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg5ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg5ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 5			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg5ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x float> @test_vlseg5ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv1f32:			; CHECK-LABEL: test_vlseg5ff_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg5ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg5ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 5			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg6ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg6ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg6ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg6ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x float> @test_vlseg6ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x float> @test_vlseg6ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv1f32:			; CHECK-LABEL: test_vlseg6ff_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg6e32ff.v v7, (a0)			; CHECK-NEXT: vlseg6e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg6ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg6ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 6			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg6ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x float> @test_vlseg6ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv1f32:			; CHECK-LABEL: test_vlseg6ff_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg6ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg6ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 6			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg7ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg7ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg7ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg7ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x float> @test_vlseg7ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x float> @test_vlseg7ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv1f32:			; CHECK-LABEL: test_vlseg7ff_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg7e32ff.v v7, (a0)			; CHECK-NEXT: vlseg7e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg7ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg7ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 7			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg7ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x float> @test_vlseg7ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv1f32:			; CHECK-LABEL: test_vlseg7ff_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg7ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg7ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 7			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg8ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg8ff.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg8ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg8ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x float> @test_vlseg8ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) {			define <vscale x 1 x float> @test_vlseg8ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv1f32:			; CHECK-LABEL: test_vlseg8ff_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg8e32ff.v v7, (a0)			; CHECK-NEXT: vlseg8e32ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg8ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg8ff.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 8			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlseg8ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {			define <vscale x 1 x float> @test_vlseg8ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv1f32:			; CHECK-LABEL: test_vlseg8ff_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg8ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg8ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 8			%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	declare {<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg2ff.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half* , i64)			declare {<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg2ff.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half* , i64)
	declare {<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x half> @test_vlseg2ff_nxv8f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 8 x half> @test_vlseg2ff_nxv8f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv8f16:			; CHECK-LABEL: test_vlseg2ff_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v6, (a0)			; CHECK-NEXT: vlseg2e16ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg2ff.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg2ff.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 2			%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	define <vscale x 8 x half> @test_vlseg2ff_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {			define <vscale x 8 x half> @test_vlseg2ff_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv8f16:			; CHECK-LABEL: test_vlseg2ff_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e16ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 2			%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg3ff.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i64)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg3ff.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i64)
	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x half> @test_vlseg3ff_nxv8f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 8 x half> @test_vlseg3ff_nxv8f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv8f16:			; CHECK-LABEL: test_vlseg3ff_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v6, (a0)			; CHECK-NEXT: vlseg3e16ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg3ff.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg3ff.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 3			%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	define <vscale x 8 x half> @test_vlseg3ff_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {			define <vscale x 8 x half> @test_vlseg3ff_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv8f16:			; CHECK-LABEL: test_vlseg3ff_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e16ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 3			%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg4ff.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i64)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg4ff.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i64)
	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x half> @test_vlseg4ff_nxv8f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 8 x half> @test_vlseg4ff_nxv8f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv8f16:			; CHECK-LABEL: test_vlseg4ff_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v6, (a0)			; CHECK-NEXT: vlseg4e16ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg4ff.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg4ff.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 4			%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	define <vscale x 8 x half> @test_vlseg4ff_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {			define <vscale x 8 x half> @test_vlseg4ff_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv8f16:			; CHECK-LABEL: test_vlseg4ff_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e16ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 4			%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	declare {<vscale x 8 x float>,<vscale x 8 x float>, i64} @llvm.riscv.vlseg2ff.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float* , i64)			declare {<vscale x 8 x float>,<vscale x 8 x float>, i64} @llvm.riscv.vlseg2ff.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float* , i64)
	declare {<vscale x 8 x float>,<vscale x 8 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x float>,<vscale x 8 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x float> @test_vlseg2ff_nxv8f32(float* %base, i64 %vl, i64* %outvl) {			define <vscale x 8 x float> @test_vlseg2ff_nxv8f32(float* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv8f32:			; CHECK-LABEL: test_vlseg2ff_nxv8f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v4, (a0)			; CHECK-NEXT: vlseg2e32ff.v v4, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>, i64} @llvm.riscv.vlseg2ff.nxv8f32(<vscale x 8 x float> undef, <vscale x 8 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>, i64} @llvm.riscv.vlseg2ff.nxv8f32(<vscale x 8 x float> undef, <vscale x 8 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i64} %0, 2			%2 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x float> %1			ret <vscale x 8 x float> %1
	}			}

	define <vscale x 8 x float> @test_vlseg2ff_mask_nxv8f32(<vscale x 8 x float> %val, float* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {			define <vscale x 8 x float> @test_vlseg2ff_mask_nxv8f32(<vscale x 8 x float> %val, float* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv8f32:			; CHECK-LABEL: test_vlseg2ff_mask_nxv8f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv4r.v v4, v8			; CHECK-NEXT: vmv4r.v v4, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e32ff.v v4, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i64} %0, 2			%2 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 8 x float> %1			ret <vscale x 8 x float> %1
	}			}

	declare {<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg2ff.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double* , i64)			declare {<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg2ff.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double* , i64)
	declare {<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg2ff.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg2ff.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x double> @test_vlseg2ff_nxv2f64(double* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x double> @test_vlseg2ff_nxv2f64(double* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv2f64:			; CHECK-LABEL: test_vlseg2ff_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg2e64ff.v v6, (a0)			; CHECK-NEXT: vlseg2e64ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg2ff.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg2ff.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 2			%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	define <vscale x 2 x double> @test_vlseg2ff_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x double> @test_vlseg2ff_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv2f64:			; CHECK-LABEL: test_vlseg2ff_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg2e64ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e64ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg2ff.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg2ff.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 2			%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg3ff.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i64)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg3ff.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i64)
	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg3ff.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg3ff.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x double> @test_vlseg3ff_nxv2f64(double* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x double> @test_vlseg3ff_nxv2f64(double* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv2f64:			; CHECK-LABEL: test_vlseg3ff_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg3e64ff.v v6, (a0)			; CHECK-NEXT: vlseg3e64ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg3ff.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg3ff.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 3			%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	define <vscale x 2 x double> @test_vlseg3ff_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x double> @test_vlseg3ff_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv2f64:			; CHECK-LABEL: test_vlseg3ff_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg3e64ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e64ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg3ff.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg3ff.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 3			%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg4ff.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i64)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg4ff.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i64)
	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg4ff.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg4ff.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x double> @test_vlseg4ff_nxv2f64(double* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x double> @test_vlseg4ff_nxv2f64(double* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv2f64:			; CHECK-LABEL: test_vlseg4ff_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg4e64ff.v v6, (a0)			; CHECK-NEXT: vlseg4e64ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg4ff.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg4ff.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 4			%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	define <vscale x 2 x double> @test_vlseg4ff_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x double> @test_vlseg4ff_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv2f64:			; CHECK-LABEL: test_vlseg4ff_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vlseg4e64ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e64ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg4ff.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg4ff.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 4			%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg2ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg2ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
	declare {<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x half> @test_vlseg2ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x half> @test_vlseg2ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv4f16:			; CHECK-LABEL: test_vlseg2ff_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0)			; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg2ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg2ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 2			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg2ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x half> @test_vlseg2ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv4f16:			; CHECK-LABEL: test_vlseg2ff_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 2			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg3ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg3ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x half> @test_vlseg3ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x half> @test_vlseg3ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv4f16:			; CHECK-LABEL: test_vlseg3ff_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0)			; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg3ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg3ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 3			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg3ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x half> @test_vlseg3ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv4f16:			; CHECK-LABEL: test_vlseg3ff_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 3			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg4ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg4ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x half> @test_vlseg4ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x half> @test_vlseg4ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv4f16:			; CHECK-LABEL: test_vlseg4ff_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0)			; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg4ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg4ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 4			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg4ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x half> @test_vlseg4ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv4f16:			; CHECK-LABEL: test_vlseg4ff_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 4			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg5ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg5ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg5ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg5ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x half> @test_vlseg5ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x half> @test_vlseg5ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv4f16:			; CHECK-LABEL: test_vlseg5ff_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0)			; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg5ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg5ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 5			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg5ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x half> @test_vlseg5ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv4f16:			; CHECK-LABEL: test_vlseg5ff_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg5ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg5ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 5			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg6ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg6ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg6ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg6ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x half> @test_vlseg6ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x half> @test_vlseg6ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv4f16:			; CHECK-LABEL: test_vlseg6ff_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0)			; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg6ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg6ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 6			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg6ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x half> @test_vlseg6ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv4f16:			; CHECK-LABEL: test_vlseg6ff_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg6ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg6ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 6			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg7ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg7ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg7ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg7ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x half> @test_vlseg7ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x half> @test_vlseg7ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv4f16:			; CHECK-LABEL: test_vlseg7ff_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0)			; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg7ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg7ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 7			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg7ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x half> @test_vlseg7ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv4f16:			; CHECK-LABEL: test_vlseg7ff_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg7ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg7ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 7			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg8ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg8ff.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg8ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg8ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x half> @test_vlseg8ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x half> @test_vlseg8ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv4f16:			; CHECK-LABEL: test_vlseg8ff_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0)			; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg8ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg8ff.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 8			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlseg8ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x half> @test_vlseg8ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv4f16:			; CHECK-LABEL: test_vlseg8ff_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg8ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg8ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 8			%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg2ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg2ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
	declare {<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x half> @test_vlseg2ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x half> @test_vlseg2ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv2f16:			; CHECK-LABEL: test_vlseg2ff_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0)			; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg2ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg2ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 2			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg2ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x half> @test_vlseg2ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv2f16:			; CHECK-LABEL: test_vlseg2ff_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 2			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg3ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg3ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x half> @test_vlseg3ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x half> @test_vlseg3ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv2f16:			; CHECK-LABEL: test_vlseg3ff_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0)			; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg3ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg3ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 3			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg3ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x half> @test_vlseg3ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv2f16:			; CHECK-LABEL: test_vlseg3ff_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 3			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg4ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg4ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x half> @test_vlseg4ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x half> @test_vlseg4ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv2f16:			; CHECK-LABEL: test_vlseg4ff_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0)			; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg4ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg4ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 4			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg4ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x half> @test_vlseg4ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv2f16:			; CHECK-LABEL: test_vlseg4ff_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 4			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg5ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg5ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg5ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg5ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x half> @test_vlseg5ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x half> @test_vlseg5ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_nxv2f16:			; CHECK-LABEL: test_vlseg5ff_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0)			; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg5ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg5ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 5			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg5ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x half> @test_vlseg5ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg5ff_mask_nxv2f16:			; CHECK-LABEL: test_vlseg5ff_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg5ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg5ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 5			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 5
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg6ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg6ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg6ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg6ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x half> @test_vlseg6ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x half> @test_vlseg6ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_nxv2f16:			; CHECK-LABEL: test_vlseg6ff_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0)			; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg6ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg6ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 6			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg6ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x half> @test_vlseg6ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg6ff_mask_nxv2f16:			; CHECK-LABEL: test_vlseg6ff_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg6ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg6ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 6			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 6
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg7ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg7ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg7ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg7ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x half> @test_vlseg7ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x half> @test_vlseg7ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_nxv2f16:			; CHECK-LABEL: test_vlseg7ff_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0)			; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg7ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg7ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 7			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg7ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x half> @test_vlseg7ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg7ff_mask_nxv2f16:			; CHECK-LABEL: test_vlseg7ff_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg7ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg7ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 7			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 7
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg8ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg8ff.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg8ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg8ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x half> @test_vlseg8ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) {			define <vscale x 2 x half> @test_vlseg8ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_nxv2f16:			; CHECK-LABEL: test_vlseg8ff_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0)			; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg8ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg8ff.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 8			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlseg8ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {			define <vscale x 2 x half> @test_vlseg8ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg8ff_mask_nxv2f16:			; CHECK-LABEL: test_vlseg8ff_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv1r.v v7, v8			; CHECK-NEXT: vmv1r.v v7, v8
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t			; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg8ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg8ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
	%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 8			%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 8
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	declare {<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg2ff.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float* , i64)			declare {<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg2ff.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float* , i64)
	declare {<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x float> @test_vlseg2ff_nxv4f32(float* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x float> @test_vlseg2ff_nxv4f32(float* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv4f32:			; CHECK-LABEL: test_vlseg2ff_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v6, (a0)			; CHECK-NEXT: vlseg2e32ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg2ff.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg2ff.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 2			%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	define <vscale x 4 x float> @test_vlseg2ff_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x float> @test_vlseg2ff_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv4f32:			; CHECK-LABEL: test_vlseg2ff_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg2e32ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg2e32ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 2			%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg3ff.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i64)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg3ff.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i64)
	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg3ff.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg3ff.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x float> @test_vlseg3ff_nxv4f32(float* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x float> @test_vlseg3ff_nxv4f32(float* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_nxv4f32:			; CHECK-LABEL: test_vlseg3ff_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v6, (a0)			; CHECK-NEXT: vlseg3e32ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg3ff.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg3ff.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 3			%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	define <vscale x 4 x float> @test_vlseg3ff_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x float> @test_vlseg3ff_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg3ff_mask_nxv4f32:			; CHECK-LABEL: test_vlseg3ff_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg3e32ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg3e32ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg3ff.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg3ff.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 3			%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 3
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg4ff.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i64)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg4ff.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i64)
	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg4ff.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg4ff.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x float> @test_vlseg4ff_nxv4f32(float* %base, i64 %vl, i64* %outvl) {			define <vscale x 4 x float> @test_vlseg4ff_nxv4f32(float* %base, i64 %vl, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_nxv4f32:			; CHECK-LABEL: test_vlseg4ff_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v6, (a0)			; CHECK-NEXT: vlseg4e32ff.v v6, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg4ff.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg4ff.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 4			%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	define <vscale x 4 x float> @test_vlseg4ff_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {			define <vscale x 4 x float> @test_vlseg4ff_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg4ff_mask_nxv4f32:			; CHECK-LABEL: test_vlseg4ff_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv2r.v v6, v8			; CHECK-NEXT: vmv2r.v v6, v8
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vlseg4e32ff.v v6, (a0), v0.t			; CHECK-NEXT: vlseg4e32ff.v v6, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a2)			; CHECK-NEXT: sd a0, 0(a2)
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg4ff.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg4ff.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 1
	%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 4			%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 4
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \			; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \
	; RUN: -verify-machineinstrs < %s \| FileCheck %s			; RUN: -verify-machineinstrs < %s \| FileCheck %s

	declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i32, i32)			declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i32, i32)
	declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i32, <vscale x 16 x i1>, i32, i32)			declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i32, <vscale x 16 x i1>, i32, i32)

	define <vscale x 16 x i16> @test_vlsseg2_nxv16i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 16 x i16> @test_vlsseg2_nxv16i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv16i16:			; CHECK-LABEL: test_vlsseg2_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1			%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
	ret <vscale x 16 x i16> %1			ret <vscale x 16 x i16> %1
	}			}

	define <vscale x 16 x i16> @test_vlsseg2_mask_nxv16i16(i16* %base, i32 %offset, i32 %vl, <vscale x 16 x i1> %mask) {			define <vscale x 16 x i16> @test_vlsseg2_mask_nxv16i16(i16* %base, i32 %offset, i32 %vl, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv16i16:			; CHECK-LABEL: test_vlsseg2_mask_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0			%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
	%2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.mask.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.mask.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1			%3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
	ret <vscale x 16 x i16> %3			ret <vscale x 16 x i16> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i8> @test_vlsseg2_nxv1i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x i8> @test_vlsseg2_nxv1i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv1i8:			; CHECK-LABEL: test_vlsseg2_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlsseg2_mask_nxv1i8(i8* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlsseg2_mask_nxv1i8(i8* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv1i8:			; CHECK-LABEL: test_vlsseg2_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i8> @test_vlsseg3_nxv1i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x i8> @test_vlsseg3_nxv1i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv1i8:			; CHECK-LABEL: test_vlsseg3_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlsseg3_mask_nxv1i8(i8* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlsseg3_mask_nxv1i8(i8* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv1i8:			; CHECK-LABEL: test_vlsseg3_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i8> @test_vlsseg4_nxv1i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x i8> @test_vlsseg4_nxv1i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv1i8:			; CHECK-LABEL: test_vlsseg4_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlsseg4_mask_nxv1i8(i8* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlsseg4_mask_nxv1i8(i8* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv1i8:			; CHECK-LABEL: test_vlsseg4_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i8> @test_vlsseg5_nxv1i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x i8> @test_vlsseg5_nxv1i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv1i8:			; CHECK-LABEL: test_vlsseg5_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlsseg5_mask_nxv1i8(i8* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlsseg5_mask_nxv1i8(i8* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv1i8:			; CHECK-LABEL: test_vlsseg5_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i8> @test_vlsseg6_nxv1i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x i8> @test_vlsseg6_nxv1i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv1i8:			; CHECK-LABEL: test_vlsseg6_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlsseg6_mask_nxv1i8(i8* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlsseg6_mask_nxv1i8(i8* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv1i8:			; CHECK-LABEL: test_vlsseg6_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i8> @test_vlsseg7_nxv1i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x i8> @test_vlsseg7_nxv1i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv1i8:			; CHECK-LABEL: test_vlsseg7_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlsseg7_mask_nxv1i8(i8* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlsseg7_mask_nxv1i8(i8* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv1i8:			; CHECK-LABEL: test_vlsseg7_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i8> @test_vlsseg8_nxv1i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x i8> @test_vlsseg8_nxv1i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv1i8:			; CHECK-LABEL: test_vlsseg8_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlsseg8_mask_nxv1i8(i8* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlsseg8_mask_nxv1i8(i8* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv1i8:			; CHECK-LABEL: test_vlsseg8_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, i32)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, i32)
	declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, <vscale x 16 x i1>, i32, i32)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, <vscale x 16 x i1>, i32, i32)

	define <vscale x 16 x i8> @test_vlsseg2_nxv16i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 16 x i8> @test_vlsseg2_nxv16i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv16i8:			; CHECK-LABEL: test_vlsseg2_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	define <vscale x 16 x i8> @test_vlsseg2_mask_nxv16i8(i8* %base, i32 %offset, i32 %vl, <vscale x 16 x i1> %mask) {			define <vscale x 16 x i8> @test_vlsseg2_mask_nxv16i8(i8* %base, i32 %offset, i32 %vl, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv16i8:			; CHECK-LABEL: test_vlsseg2_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
	%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1			%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
	ret <vscale x 16 x i8> %3			ret <vscale x 16 x i8> %3
	}			}

	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, i32)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, i32)
	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, <vscale x 16 x i1>, i32, i32)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, <vscale x 16 x i1>, i32, i32)

	define <vscale x 16 x i8> @test_vlsseg3_nxv16i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 16 x i8> @test_vlsseg3_nxv16i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv16i8:			; CHECK-LABEL: test_vlsseg3_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	define <vscale x 16 x i8> @test_vlsseg3_mask_nxv16i8(i8* %base, i32 %offset, i32 %vl, <vscale x 16 x i1> %mask) {			define <vscale x 16 x i8> @test_vlsseg3_mask_nxv16i8(i8* %base, i32 %offset, i32 %vl, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv16i8:			; CHECK-LABEL: test_vlsseg3_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
	%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1			%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
	ret <vscale x 16 x i8> %3			ret <vscale x 16 x i8> %3
	}			}

	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, i32)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, i32)
	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, <vscale x 16 x i1>, i32, i32)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, <vscale x 16 x i1>, i32, i32)

	define <vscale x 16 x i8> @test_vlsseg4_nxv16i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 16 x i8> @test_vlsseg4_nxv16i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv16i8:			; CHECK-LABEL: test_vlsseg4_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	define <vscale x 16 x i8> @test_vlsseg4_mask_nxv16i8(i8* %base, i32 %offset, i32 %vl, <vscale x 16 x i1> %mask) {			define <vscale x 16 x i8> @test_vlsseg4_mask_nxv16i8(i8* %base, i32 %offset, i32 %vl, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv16i8:			; CHECK-LABEL: test_vlsseg4_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
	%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1			%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
	ret <vscale x 16 x i8> %3			ret <vscale x 16 x i8> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i32> @test_vlsseg2_nxv2i32(i32* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x i32> @test_vlsseg2_nxv2i32(i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv2i32:			; CHECK-LABEL: test_vlsseg2_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlsseg2_mask_nxv2i32(i32* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlsseg2_mask_nxv2i32(i32* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv2i32:			; CHECK-LABEL: test_vlsseg2_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i32> @test_vlsseg3_nxv2i32(i32* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x i32> @test_vlsseg3_nxv2i32(i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv2i32:			; CHECK-LABEL: test_vlsseg3_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlsseg3_mask_nxv2i32(i32* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlsseg3_mask_nxv2i32(i32* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv2i32:			; CHECK-LABEL: test_vlsseg3_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i32> @test_vlsseg4_nxv2i32(i32* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x i32> @test_vlsseg4_nxv2i32(i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv2i32:			; CHECK-LABEL: test_vlsseg4_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlsseg4_mask_nxv2i32(i32* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlsseg4_mask_nxv2i32(i32* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv2i32:			; CHECK-LABEL: test_vlsseg4_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i32> @test_vlsseg5_nxv2i32(i32* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x i32> @test_vlsseg5_nxv2i32(i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv2i32:			; CHECK-LABEL: test_vlsseg5_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlsseg5_mask_nxv2i32(i32* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlsseg5_mask_nxv2i32(i32* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv2i32:			; CHECK-LABEL: test_vlsseg5_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i32> @test_vlsseg6_nxv2i32(i32* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x i32> @test_vlsseg6_nxv2i32(i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv2i32:			; CHECK-LABEL: test_vlsseg6_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlsseg6_mask_nxv2i32(i32* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlsseg6_mask_nxv2i32(i32* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv2i32:			; CHECK-LABEL: test_vlsseg6_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i32> @test_vlsseg7_nxv2i32(i32* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x i32> @test_vlsseg7_nxv2i32(i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv2i32:			; CHECK-LABEL: test_vlsseg7_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlsseg7_mask_nxv2i32(i32* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlsseg7_mask_nxv2i32(i32* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv2i32:			; CHECK-LABEL: test_vlsseg7_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i32> @test_vlsseg8_nxv2i32(i32* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x i32> @test_vlsseg8_nxv2i32(i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv2i32:			; CHECK-LABEL: test_vlsseg8_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlsseg8_mask_nxv2i32(i32* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlsseg8_mask_nxv2i32(i32* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv2i32:			; CHECK-LABEL: test_vlsseg8_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i16> @test_vlsseg2_nxv4i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x i16> @test_vlsseg2_nxv4i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv4i16:			; CHECK-LABEL: test_vlsseg2_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlsseg2_mask_nxv4i16(i16* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlsseg2_mask_nxv4i16(i16* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv4i16:			; CHECK-LABEL: test_vlsseg2_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i16> @test_vlsseg3_nxv4i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x i16> @test_vlsseg3_nxv4i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv4i16:			; CHECK-LABEL: test_vlsseg3_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlsseg3_mask_nxv4i16(i16* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlsseg3_mask_nxv4i16(i16* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv4i16:			; CHECK-LABEL: test_vlsseg3_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i16> @test_vlsseg4_nxv4i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x i16> @test_vlsseg4_nxv4i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv4i16:			; CHECK-LABEL: test_vlsseg4_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlsseg4_mask_nxv4i16(i16* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlsseg4_mask_nxv4i16(i16* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv4i16:			; CHECK-LABEL: test_vlsseg4_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i16> @test_vlsseg5_nxv4i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x i16> @test_vlsseg5_nxv4i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv4i16:			; CHECK-LABEL: test_vlsseg5_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlsseg5_mask_nxv4i16(i16* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlsseg5_mask_nxv4i16(i16* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv4i16:			; CHECK-LABEL: test_vlsseg5_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i16> @test_vlsseg6_nxv4i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x i16> @test_vlsseg6_nxv4i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv4i16:			; CHECK-LABEL: test_vlsseg6_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlsseg6_mask_nxv4i16(i16* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlsseg6_mask_nxv4i16(i16* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv4i16:			; CHECK-LABEL: test_vlsseg6_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i16> @test_vlsseg7_nxv4i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x i16> @test_vlsseg7_nxv4i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv4i16:			; CHECK-LABEL: test_vlsseg7_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlsseg7_mask_nxv4i16(i16* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlsseg7_mask_nxv4i16(i16* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv4i16:			; CHECK-LABEL: test_vlsseg7_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i16> @test_vlsseg8_nxv4i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x i16> @test_vlsseg8_nxv4i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv4i16:			; CHECK-LABEL: test_vlsseg8_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlsseg8_mask_nxv4i16(i16* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlsseg8_mask_nxv4i16(i16* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv4i16:			; CHECK-LABEL: test_vlsseg8_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i32> @test_vlsseg2_nxv1i32(i32* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x i32> @test_vlsseg2_nxv1i32(i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv1i32:			; CHECK-LABEL: test_vlsseg2_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlsseg2_mask_nxv1i32(i32* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlsseg2_mask_nxv1i32(i32* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv1i32:			; CHECK-LABEL: test_vlsseg2_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i32> @test_vlsseg3_nxv1i32(i32* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x i32> @test_vlsseg3_nxv1i32(i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv1i32:			; CHECK-LABEL: test_vlsseg3_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlsseg3_mask_nxv1i32(i32* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlsseg3_mask_nxv1i32(i32* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv1i32:			; CHECK-LABEL: test_vlsseg3_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i32> @test_vlsseg4_nxv1i32(i32* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x i32> @test_vlsseg4_nxv1i32(i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv1i32:			; CHECK-LABEL: test_vlsseg4_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlsseg4_mask_nxv1i32(i32* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlsseg4_mask_nxv1i32(i32* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv1i32:			; CHECK-LABEL: test_vlsseg4_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i32> @test_vlsseg5_nxv1i32(i32* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x i32> @test_vlsseg5_nxv1i32(i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv1i32:			; CHECK-LABEL: test_vlsseg5_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlsseg5_mask_nxv1i32(i32* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlsseg5_mask_nxv1i32(i32* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv1i32:			; CHECK-LABEL: test_vlsseg5_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i32> @test_vlsseg6_nxv1i32(i32* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x i32> @test_vlsseg6_nxv1i32(i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv1i32:			; CHECK-LABEL: test_vlsseg6_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlsseg6_mask_nxv1i32(i32* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlsseg6_mask_nxv1i32(i32* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv1i32:			; CHECK-LABEL: test_vlsseg6_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i32> @test_vlsseg7_nxv1i32(i32* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x i32> @test_vlsseg7_nxv1i32(i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv1i32:			; CHECK-LABEL: test_vlsseg7_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlsseg7_mask_nxv1i32(i32* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlsseg7_mask_nxv1i32(i32* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv1i32:			; CHECK-LABEL: test_vlsseg7_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i32> @test_vlsseg8_nxv1i32(i32* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x i32> @test_vlsseg8_nxv1i32(i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv1i32:			; CHECK-LABEL: test_vlsseg8_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlsseg8_mask_nxv1i32(i32* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlsseg8_mask_nxv1i32(i32* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv1i32:			; CHECK-LABEL: test_vlsseg8_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg2.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, i32)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg2.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, i32)
	declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg2.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg2.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i16> @test_vlsseg2_nxv8i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 8 x i16> @test_vlsseg2_nxv8i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv8i16:			; CHECK-LABEL: test_vlsseg2_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg2.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg2.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	define <vscale x 8 x i16> @test_vlsseg2_mask_nxv8i16(i16* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i16> @test_vlsseg2_mask_nxv8i16(i16* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv8i16:			; CHECK-LABEL: test_vlsseg2_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg2.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg2.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
	%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg2.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg2.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1			%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
	ret <vscale x 8 x i16> %3			ret <vscale x 8 x i16> %3
	}			}

	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg3.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, i32)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg3.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, i32)
	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg3.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg3.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i16> @test_vlsseg3_nxv8i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 8 x i16> @test_vlsseg3_nxv8i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv8i16:			; CHECK-LABEL: test_vlsseg3_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg3.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg3.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	define <vscale x 8 x i16> @test_vlsseg3_mask_nxv8i16(i16* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i16> @test_vlsseg3_mask_nxv8i16(i16* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv8i16:			; CHECK-LABEL: test_vlsseg3_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg3.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg3.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
	%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg3.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg3.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1			%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
	ret <vscale x 8 x i16> %3			ret <vscale x 8 x i16> %3
	}			}

	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg4.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, i32)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg4.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, i32)
	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg4.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg4.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i16> @test_vlsseg4_nxv8i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 8 x i16> @test_vlsseg4_nxv8i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv8i16:			; CHECK-LABEL: test_vlsseg4_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg4.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg4.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	define <vscale x 8 x i16> @test_vlsseg4_mask_nxv8i16(i16* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i16> @test_vlsseg4_mask_nxv8i16(i16* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv8i16:			; CHECK-LABEL: test_vlsseg4_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg4.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg4.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
	%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg4.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg4.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1			%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
	ret <vscale x 8 x i16> %3			ret <vscale x 8 x i16> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg2.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg2.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg2.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg2.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i8> @test_vlsseg2_nxv8i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 8 x i8> @test_vlsseg2_nxv8i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv8i8:			; CHECK-LABEL: test_vlsseg2_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg2.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg2.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlsseg2_mask_nxv8i8(i8* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlsseg2_mask_nxv8i8(i8* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv8i8:			; CHECK-LABEL: test_vlsseg2_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg2.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg2.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg2.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg2.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg3.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg3.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg3.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg3.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i8> @test_vlsseg3_nxv8i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 8 x i8> @test_vlsseg3_nxv8i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv8i8:			; CHECK-LABEL: test_vlsseg3_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg3.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg3.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlsseg3_mask_nxv8i8(i8* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlsseg3_mask_nxv8i8(i8* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv8i8:			; CHECK-LABEL: test_vlsseg3_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg3.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg3.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg3.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg3.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg4.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg4.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg4.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg4.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i8> @test_vlsseg4_nxv8i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 8 x i8> @test_vlsseg4_nxv8i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv8i8:			; CHECK-LABEL: test_vlsseg4_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg4.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg4.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlsseg4_mask_nxv8i8(i8* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlsseg4_mask_nxv8i8(i8* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv8i8:			; CHECK-LABEL: test_vlsseg4_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg4.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg4.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg4.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg4.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg5.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg5.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg5.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg5.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i8> @test_vlsseg5_nxv8i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 8 x i8> @test_vlsseg5_nxv8i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv8i8:			; CHECK-LABEL: test_vlsseg5_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg5.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg5.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlsseg5_mask_nxv8i8(i8* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlsseg5_mask_nxv8i8(i8* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv8i8:			; CHECK-LABEL: test_vlsseg5_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg5.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg5.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg5.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg5.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg6.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg6.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg6.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg6.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i8> @test_vlsseg6_nxv8i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 8 x i8> @test_vlsseg6_nxv8i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv8i8:			; CHECK-LABEL: test_vlsseg6_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg6.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg6.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlsseg6_mask_nxv8i8(i8* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlsseg6_mask_nxv8i8(i8* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv8i8:			; CHECK-LABEL: test_vlsseg6_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg6.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg6.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg6.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg6.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg7.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg7.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg7.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg7.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i8> @test_vlsseg7_nxv8i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 8 x i8> @test_vlsseg7_nxv8i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv8i8:			; CHECK-LABEL: test_vlsseg7_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg7.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg7.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlsseg7_mask_nxv8i8(i8* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlsseg7_mask_nxv8i8(i8* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv8i8:			; CHECK-LABEL: test_vlsseg7_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg7.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg7.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg7.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg7.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg8.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg8.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i8> @test_vlsseg8_nxv8i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 8 x i8> @test_vlsseg8_nxv8i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv8i8:			; CHECK-LABEL: test_vlsseg8_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg8.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg8.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlsseg8_mask_nxv8i8(i8* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlsseg8_mask_nxv8i8(i8* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv8i8:			; CHECK-LABEL: test_vlsseg8_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg8.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg8.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg8.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg8.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlsseg2.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, i32, i32)			declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlsseg2.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, i32, i32)
	declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlsseg2.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, i32, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlsseg2.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, i32, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x i32> @test_vlsseg2_nxv8i32(i32* %base, i32 %offset, i32 %vl) {			define <vscale x 8 x i32> @test_vlsseg2_nxv8i32(i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv8i32:			; CHECK-LABEL: test_vlsseg2_nxv8i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlsseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlsseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1			%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
	ret <vscale x 8 x i32> %1			ret <vscale x 8 x i32> %1
	}			}

	define <vscale x 8 x i32> @test_vlsseg2_mask_nxv8i32(i32* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i32> @test_vlsseg2_mask_nxv8i32(i32* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv8i32:			; CHECK-LABEL: test_vlsseg2_mask_nxv8i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlsseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlsseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0			%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
	%2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlsseg2.mask.nxv8i32(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlsseg2.mask.nxv8i32(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1			%3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
	ret <vscale x 8 x i32> %3			ret <vscale x 8 x i32> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg2.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg2.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg2.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg2.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i8> @test_vlsseg2_nxv4i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x i8> @test_vlsseg2_nxv4i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv4i8:			; CHECK-LABEL: test_vlsseg2_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg2.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg2.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlsseg2_mask_nxv4i8(i8* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlsseg2_mask_nxv4i8(i8* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv4i8:			; CHECK-LABEL: test_vlsseg2_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg2.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg2.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg2.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg2.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg3.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg3.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg3.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg3.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i8> @test_vlsseg3_nxv4i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x i8> @test_vlsseg3_nxv4i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv4i8:			; CHECK-LABEL: test_vlsseg3_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg3.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg3.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlsseg3_mask_nxv4i8(i8* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlsseg3_mask_nxv4i8(i8* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv4i8:			; CHECK-LABEL: test_vlsseg3_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg3.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg3.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg3.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg3.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg4.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg4.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg4.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg4.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i8> @test_vlsseg4_nxv4i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x i8> @test_vlsseg4_nxv4i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv4i8:			; CHECK-LABEL: test_vlsseg4_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg4.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg4.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlsseg4_mask_nxv4i8(i8* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlsseg4_mask_nxv4i8(i8* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv4i8:			; CHECK-LABEL: test_vlsseg4_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg4.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg4.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg4.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg4.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg5.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg5.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg5.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg5.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i8> @test_vlsseg5_nxv4i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x i8> @test_vlsseg5_nxv4i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv4i8:			; CHECK-LABEL: test_vlsseg5_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg5.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg5.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlsseg5_mask_nxv4i8(i8* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlsseg5_mask_nxv4i8(i8* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv4i8:			; CHECK-LABEL: test_vlsseg5_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg5.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg5.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg5.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg5.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg6.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg6.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg6.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg6.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i8> @test_vlsseg6_nxv4i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x i8> @test_vlsseg6_nxv4i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv4i8:			; CHECK-LABEL: test_vlsseg6_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg6.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg6.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlsseg6_mask_nxv4i8(i8* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlsseg6_mask_nxv4i8(i8* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv4i8:			; CHECK-LABEL: test_vlsseg6_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg6.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg6.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg6.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg6.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg7.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg7.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg7.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg7.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i8> @test_vlsseg7_nxv4i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x i8> @test_vlsseg7_nxv4i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv4i8:			; CHECK-LABEL: test_vlsseg7_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg7.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg7.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlsseg7_mask_nxv4i8(i8* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlsseg7_mask_nxv4i8(i8* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv4i8:			; CHECK-LABEL: test_vlsseg7_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg7.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg7.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg7.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg7.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg8.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg8.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i8> @test_vlsseg8_nxv4i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x i8> @test_vlsseg8_nxv4i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv4i8:			; CHECK-LABEL: test_vlsseg8_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg8.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg8.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlsseg8_mask_nxv4i8(i8* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlsseg8_mask_nxv4i8(i8* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv4i8:			; CHECK-LABEL: test_vlsseg8_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg8.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg8.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg8.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg8.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg2.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg2.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg2.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg2.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i16> @test_vlsseg2_nxv1i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x i16> @test_vlsseg2_nxv1i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv1i16:			; CHECK-LABEL: test_vlsseg2_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg2.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg2.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlsseg2_mask_nxv1i16(i16* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlsseg2_mask_nxv1i16(i16* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv1i16:			; CHECK-LABEL: test_vlsseg2_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg2.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg2.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg2.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg2.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg3.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg3.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg3.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg3.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i16> @test_vlsseg3_nxv1i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x i16> @test_vlsseg3_nxv1i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv1i16:			; CHECK-LABEL: test_vlsseg3_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg3.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg3.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlsseg3_mask_nxv1i16(i16* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlsseg3_mask_nxv1i16(i16* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv1i16:			; CHECK-LABEL: test_vlsseg3_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg3.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg3.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg3.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg3.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg4.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg4.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg4.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg4.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i16> @test_vlsseg4_nxv1i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x i16> @test_vlsseg4_nxv1i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv1i16:			; CHECK-LABEL: test_vlsseg4_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg4.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg4.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlsseg4_mask_nxv1i16(i16* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlsseg4_mask_nxv1i16(i16* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv1i16:			; CHECK-LABEL: test_vlsseg4_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg4.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg4.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg4.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg4.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg5.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg5.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg5.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg5.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i16> @test_vlsseg5_nxv1i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x i16> @test_vlsseg5_nxv1i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv1i16:			; CHECK-LABEL: test_vlsseg5_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg5.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg5.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlsseg5_mask_nxv1i16(i16* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlsseg5_mask_nxv1i16(i16* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv1i16:			; CHECK-LABEL: test_vlsseg5_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg5.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg5.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg5.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg5.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg6.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg6.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg6.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg6.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i16> @test_vlsseg6_nxv1i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x i16> @test_vlsseg6_nxv1i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv1i16:			; CHECK-LABEL: test_vlsseg6_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg6.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg6.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlsseg6_mask_nxv1i16(i16* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlsseg6_mask_nxv1i16(i16* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv1i16:			; CHECK-LABEL: test_vlsseg6_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg6.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg6.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg6.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg6.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg7.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg7.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg7.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg7.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i16> @test_vlsseg7_nxv1i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x i16> @test_vlsseg7_nxv1i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv1i16:			; CHECK-LABEL: test_vlsseg7_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg7.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg7.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlsseg7_mask_nxv1i16(i16* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlsseg7_mask_nxv1i16(i16* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv1i16:			; CHECK-LABEL: test_vlsseg7_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg7.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg7.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg7.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg7.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg8.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg8.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg8.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg8.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x i16> @test_vlsseg8_nxv1i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x i16> @test_vlsseg8_nxv1i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv1i16:			; CHECK-LABEL: test_vlsseg8_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg8.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg8.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlsseg8_mask_nxv1i16(i16* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlsseg8_mask_nxv1i16(i16* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv1i16:			; CHECK-LABEL: test_vlsseg8_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg8.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg8.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg8.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg8.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlsseg2.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, i32, i32)			declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlsseg2.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, i32, i32)
	declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlsseg2.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, i32, <vscale x 32 x i1>, i32, i32)			declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlsseg2.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, i32, <vscale x 32 x i1>, i32, i32)

	define <vscale x 32 x i8> @test_vlsseg2_nxv32i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 32 x i8> @test_vlsseg2_nxv32i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv32i8:			; CHECK-LABEL: test_vlsseg2_nxv32i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlsseg2.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlsseg2.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1			%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
	ret <vscale x 32 x i8> %1			ret <vscale x 32 x i8> %1
	}			}

	define <vscale x 32 x i8> @test_vlsseg2_mask_nxv32i8(i8* %base, i32 %offset, i32 %vl, <vscale x 32 x i1> %mask) {			define <vscale x 32 x i8> @test_vlsseg2_mask_nxv32i8(i8* %base, i32 %offset, i32 %vl, <vscale x 32 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv32i8:			; CHECK-LABEL: test_vlsseg2_mask_nxv32i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlsseg2.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlsseg2.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0			%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
	%2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlsseg2.mask.nxv32i8(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, i32 %offset, <vscale x 32 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlsseg2.mask.nxv32i8(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, i32 %offset, <vscale x 32 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1			%3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
	ret <vscale x 32 x i8> %3			ret <vscale x 32 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg2.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg2.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg2.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg2.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i8> @test_vlsseg2_nxv2i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x i8> @test_vlsseg2_nxv2i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv2i8:			; CHECK-LABEL: test_vlsseg2_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg2.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg2.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlsseg2_mask_nxv2i8(i8* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlsseg2_mask_nxv2i8(i8* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv2i8:			; CHECK-LABEL: test_vlsseg2_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg2.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg2.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg2.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg2.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg3.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg3.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg3.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg3.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i8> @test_vlsseg3_nxv2i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x i8> @test_vlsseg3_nxv2i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv2i8:			; CHECK-LABEL: test_vlsseg3_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg3.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg3.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlsseg3_mask_nxv2i8(i8* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlsseg3_mask_nxv2i8(i8* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv2i8:			; CHECK-LABEL: test_vlsseg3_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg3.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg3.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg3.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg3.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg4.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg4.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg4.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg4.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i8> @test_vlsseg4_nxv2i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x i8> @test_vlsseg4_nxv2i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv2i8:			; CHECK-LABEL: test_vlsseg4_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg4.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg4.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlsseg4_mask_nxv2i8(i8* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlsseg4_mask_nxv2i8(i8* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv2i8:			; CHECK-LABEL: test_vlsseg4_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg4.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg4.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg4.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg4.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg5.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg5.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg5.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg5.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i8> @test_vlsseg5_nxv2i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x i8> @test_vlsseg5_nxv2i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv2i8:			; CHECK-LABEL: test_vlsseg5_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg5.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg5.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlsseg5_mask_nxv2i8(i8* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlsseg5_mask_nxv2i8(i8* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv2i8:			; CHECK-LABEL: test_vlsseg5_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg5.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg5.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg5.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg5.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg6.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg6.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg6.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg6.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i8> @test_vlsseg6_nxv2i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x i8> @test_vlsseg6_nxv2i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv2i8:			; CHECK-LABEL: test_vlsseg6_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg6.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg6.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlsseg6_mask_nxv2i8(i8* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlsseg6_mask_nxv2i8(i8* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv2i8:			; CHECK-LABEL: test_vlsseg6_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg6.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg6.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg6.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg6.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg7.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg7.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg7.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg7.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i8> @test_vlsseg7_nxv2i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x i8> @test_vlsseg7_nxv2i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv2i8:			; CHECK-LABEL: test_vlsseg7_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg7.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg7.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlsseg7_mask_nxv2i8(i8* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlsseg7_mask_nxv2i8(i8* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv2i8:			; CHECK-LABEL: test_vlsseg7_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg7.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg7.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg7.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg7.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg8.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg8.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i8> @test_vlsseg8_nxv2i8(i8* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x i8> @test_vlsseg8_nxv2i8(i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv2i8:			; CHECK-LABEL: test_vlsseg8_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg8.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg8.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlsseg8_mask_nxv2i8(i8* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlsseg8_mask_nxv2i8(i8* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv2i8:			; CHECK-LABEL: test_vlsseg8_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg8.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg8.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg8.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg8.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg2.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg2.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg2.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg2.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i16> @test_vlsseg2_nxv2i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x i16> @test_vlsseg2_nxv2i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv2i16:			; CHECK-LABEL: test_vlsseg2_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg2.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg2.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlsseg2_mask_nxv2i16(i16* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlsseg2_mask_nxv2i16(i16* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv2i16:			; CHECK-LABEL: test_vlsseg2_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg2.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg2.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg2.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg2.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg3.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg3.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg3.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg3.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i16> @test_vlsseg3_nxv2i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x i16> @test_vlsseg3_nxv2i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv2i16:			; CHECK-LABEL: test_vlsseg3_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg3.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg3.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlsseg3_mask_nxv2i16(i16* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlsseg3_mask_nxv2i16(i16* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv2i16:			; CHECK-LABEL: test_vlsseg3_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg3.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg3.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg3.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg3.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg4.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg4.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg4.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg4.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i16> @test_vlsseg4_nxv2i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x i16> @test_vlsseg4_nxv2i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv2i16:			; CHECK-LABEL: test_vlsseg4_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg4.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg4.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlsseg4_mask_nxv2i16(i16* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlsseg4_mask_nxv2i16(i16* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv2i16:			; CHECK-LABEL: test_vlsseg4_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg4.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg4.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg4.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg4.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg5.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg5.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg5.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg5.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i16> @test_vlsseg5_nxv2i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x i16> @test_vlsseg5_nxv2i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv2i16:			; CHECK-LABEL: test_vlsseg5_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg5.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg5.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlsseg5_mask_nxv2i16(i16* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlsseg5_mask_nxv2i16(i16* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv2i16:			; CHECK-LABEL: test_vlsseg5_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg5.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg5.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg5.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg5.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg6.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg6.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg6.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg6.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i16> @test_vlsseg6_nxv2i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x i16> @test_vlsseg6_nxv2i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv2i16:			; CHECK-LABEL: test_vlsseg6_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg6.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg6.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlsseg6_mask_nxv2i16(i16* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlsseg6_mask_nxv2i16(i16* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv2i16:			; CHECK-LABEL: test_vlsseg6_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg6.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg6.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg6.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg6.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg7.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg7.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg7.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg7.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i16> @test_vlsseg7_nxv2i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x i16> @test_vlsseg7_nxv2i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv2i16:			; CHECK-LABEL: test_vlsseg7_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg7.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg7.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlsseg7_mask_nxv2i16(i16* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlsseg7_mask_nxv2i16(i16* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv2i16:			; CHECK-LABEL: test_vlsseg7_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg7.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg7.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg7.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg7.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg8.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg8.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg8.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg8.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x i16> @test_vlsseg8_nxv2i16(i16* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x i16> @test_vlsseg8_nxv2i16(i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv2i16:			; CHECK-LABEL: test_vlsseg8_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg8.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg8.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlsseg8_mask_nxv2i16(i16* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlsseg8_mask_nxv2i16(i16* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv2i16:			; CHECK-LABEL: test_vlsseg8_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg8.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg8.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg8.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg8.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg2.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, i32)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg2.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, i32)
	declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg2.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg2.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i32> @test_vlsseg2_nxv4i32(i32* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x i32> @test_vlsseg2_nxv4i32(i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv4i32:			; CHECK-LABEL: test_vlsseg2_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	define <vscale x 4 x i32> @test_vlsseg2_mask_nxv4i32(i32* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i32> @test_vlsseg2_mask_nxv4i32(i32* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv4i32:			; CHECK-LABEL: test_vlsseg2_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
	%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg2.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg2.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1			%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
	ret <vscale x 4 x i32> %3			ret <vscale x 4 x i32> %3
	}			}

	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg3.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, i32)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg3.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, i32)
	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg3.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg3.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i32> @test_vlsseg3_nxv4i32(i32* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x i32> @test_vlsseg3_nxv4i32(i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv4i32:			; CHECK-LABEL: test_vlsseg3_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	define <vscale x 4 x i32> @test_vlsseg3_mask_nxv4i32(i32* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i32> @test_vlsseg3_mask_nxv4i32(i32* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv4i32:			; CHECK-LABEL: test_vlsseg3_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
	%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg3.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg3.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1			%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
	ret <vscale x 4 x i32> %3			ret <vscale x 4 x i32> %3
	}			}

	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg4.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, i32)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg4.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, i32)
	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg4.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg4.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x i32> @test_vlsseg4_nxv4i32(i32* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x i32> @test_vlsseg4_nxv4i32(i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv4i32:			; CHECK-LABEL: test_vlsseg4_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg4.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg4.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	define <vscale x 4 x i32> @test_vlsseg4_mask_nxv4i32(i32* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i32> @test_vlsseg4_mask_nxv4i32(i32* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv4i32:			; CHECK-LABEL: test_vlsseg4_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg4.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg4.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
	%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg4.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg4.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1			%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
	ret <vscale x 4 x i32> %3			ret <vscale x 4 x i32> %3
	}			}

	declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlsseg2.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, i32, i32)			declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlsseg2.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, i32, i32)
	declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlsseg2.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, i32, <vscale x 16 x i1>, i32, i32)			declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlsseg2.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, i32, <vscale x 16 x i1>, i32, i32)

	define <vscale x 16 x half> @test_vlsseg2_nxv16f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 16 x half> @test_vlsseg2_nxv16f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv16f16:			; CHECK-LABEL: test_vlsseg2_nxv16f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlsseg2.nxv16f16(<vscale x 16 x half> undef, <vscale x 16 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlsseg2.nxv16f16(<vscale x 16 x half> undef, <vscale x 16 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1			%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
	ret <vscale x 16 x half> %1			ret <vscale x 16 x half> %1
	}			}

	define <vscale x 16 x half> @test_vlsseg2_mask_nxv16f16(half* %base, i32 %offset, i32 %vl, <vscale x 16 x i1> %mask) {			define <vscale x 16 x half> @test_vlsseg2_mask_nxv16f16(half* %base, i32 %offset, i32 %vl, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv16f16:			; CHECK-LABEL: test_vlsseg2_mask_nxv16f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlsseg2.nxv16f16(<vscale x 16 x half> undef, <vscale x 16 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlsseg2.nxv16f16(<vscale x 16 x half> undef, <vscale x 16 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0			%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
	%2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlsseg2.mask.nxv16f16(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlsseg2.mask.nxv16f16(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1			%3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
	ret <vscale x 16 x half> %3			ret <vscale x 16 x half> %3
	}			}

	declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlsseg2.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, i32, i32)			declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlsseg2.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, i32, i32)
	declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlsseg2.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlsseg2.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x double> @test_vlsseg2_nxv4f64(double* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x double> @test_vlsseg2_nxv4f64(double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv4f64:			; CHECK-LABEL: test_vlsseg2_nxv4f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
	; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlsseg2.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlsseg2.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1			%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
	ret <vscale x 4 x double> %1			ret <vscale x 4 x double> %1
	}			}

	define <vscale x 4 x double> @test_vlsseg2_mask_nxv4f64(double* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x double> @test_vlsseg2_mask_nxv4f64(double* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv4f64:			; CHECK-LABEL: test_vlsseg2_mask_nxv4f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
	; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlsseg2.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlsseg2.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0			%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
	%2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlsseg2.mask.nxv4f64(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlsseg2.mask.nxv4f64(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1			%3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
	ret <vscale x 4 x double> %3			ret <vscale x 4 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg2.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg2.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)
	declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg2.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg2.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x double> @test_vlsseg2_nxv1f64(double* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x double> @test_vlsseg2_nxv1f64(double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv1f64:			; CHECK-LABEL: test_vlsseg2_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg2.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg2.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlsseg2_mask_nxv1f64(double* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlsseg2_mask_nxv1f64(double* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv1f64:			; CHECK-LABEL: test_vlsseg2_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg2.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg2.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg2.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg2.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg3.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg3.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg3.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg3.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x double> @test_vlsseg3_nxv1f64(double* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x double> @test_vlsseg3_nxv1f64(double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv1f64:			; CHECK-LABEL: test_vlsseg3_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg3.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg3.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlsseg3_mask_nxv1f64(double* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlsseg3_mask_nxv1f64(double* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv1f64:			; CHECK-LABEL: test_vlsseg3_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg3.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg3.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg3.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg3.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg4.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg4.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg4.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg4.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x double> @test_vlsseg4_nxv1f64(double* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x double> @test_vlsseg4_nxv1f64(double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv1f64:			; CHECK-LABEL: test_vlsseg4_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg4.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg4.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlsseg4_mask_nxv1f64(double* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlsseg4_mask_nxv1f64(double* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv1f64:			; CHECK-LABEL: test_vlsseg4_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg4.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg4.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg4.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg4.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg5.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg5.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg5.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg5.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x double> @test_vlsseg5_nxv1f64(double* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x double> @test_vlsseg5_nxv1f64(double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv1f64:			; CHECK-LABEL: test_vlsseg5_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg5.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg5.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlsseg5_mask_nxv1f64(double* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlsseg5_mask_nxv1f64(double* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv1f64:			; CHECK-LABEL: test_vlsseg5_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg5.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg5.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg5.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg5.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg6.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg6.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg6.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg6.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x double> @test_vlsseg6_nxv1f64(double* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x double> @test_vlsseg6_nxv1f64(double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv1f64:			; CHECK-LABEL: test_vlsseg6_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg6.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg6.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlsseg6_mask_nxv1f64(double* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlsseg6_mask_nxv1f64(double* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv1f64:			; CHECK-LABEL: test_vlsseg6_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg6.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg6.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg6.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg6.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg7.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg7.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg7.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg7.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x double> @test_vlsseg7_nxv1f64(double* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x double> @test_vlsseg7_nxv1f64(double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv1f64:			; CHECK-LABEL: test_vlsseg7_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg7.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg7.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlsseg7_mask_nxv1f64(double* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlsseg7_mask_nxv1f64(double* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv1f64:			; CHECK-LABEL: test_vlsseg7_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg7.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg7.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg7.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg7.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg8.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg8.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg8.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg8.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x double> @test_vlsseg8_nxv1f64(double* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x double> @test_vlsseg8_nxv1f64(double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv1f64:			; CHECK-LABEL: test_vlsseg8_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg8.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg8.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlsseg8_mask_nxv1f64(double* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlsseg8_mask_nxv1f64(double* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv1f64:			; CHECK-LABEL: test_vlsseg8_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg8.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg8.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg8.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg8.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg2.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg2.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)
	declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg2.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg2.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x float> @test_vlsseg2_nxv2f32(float* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x float> @test_vlsseg2_nxv2f32(float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv2f32:			; CHECK-LABEL: test_vlsseg2_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg2.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg2.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlsseg2_mask_nxv2f32(float* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlsseg2_mask_nxv2f32(float* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv2f32:			; CHECK-LABEL: test_vlsseg2_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg2.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg2.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg2.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg2.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg3.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg3.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg3.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg3.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x float> @test_vlsseg3_nxv2f32(float* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x float> @test_vlsseg3_nxv2f32(float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv2f32:			; CHECK-LABEL: test_vlsseg3_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg3.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg3.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlsseg3_mask_nxv2f32(float* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlsseg3_mask_nxv2f32(float* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv2f32:			; CHECK-LABEL: test_vlsseg3_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg3.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg3.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg3.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg3.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg4.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg4.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg4.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg4.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x float> @test_vlsseg4_nxv2f32(float* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x float> @test_vlsseg4_nxv2f32(float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv2f32:			; CHECK-LABEL: test_vlsseg4_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg4.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg4.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlsseg4_mask_nxv2f32(float* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlsseg4_mask_nxv2f32(float* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv2f32:			; CHECK-LABEL: test_vlsseg4_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg4.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg4.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg4.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg4.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg5.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg5.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg5.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg5.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x float> @test_vlsseg5_nxv2f32(float* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x float> @test_vlsseg5_nxv2f32(float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv2f32:			; CHECK-LABEL: test_vlsseg5_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg5.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg5.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlsseg5_mask_nxv2f32(float* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlsseg5_mask_nxv2f32(float* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv2f32:			; CHECK-LABEL: test_vlsseg5_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg5.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg5.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg5.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg5.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg6.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg6.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg6.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg6.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x float> @test_vlsseg6_nxv2f32(float* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x float> @test_vlsseg6_nxv2f32(float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv2f32:			; CHECK-LABEL: test_vlsseg6_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg6.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg6.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlsseg6_mask_nxv2f32(float* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlsseg6_mask_nxv2f32(float* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv2f32:			; CHECK-LABEL: test_vlsseg6_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg6.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg6.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg6.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg6.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg7.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg7.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg7.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg7.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x float> @test_vlsseg7_nxv2f32(float* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x float> @test_vlsseg7_nxv2f32(float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv2f32:			; CHECK-LABEL: test_vlsseg7_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg7.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg7.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlsseg7_mask_nxv2f32(float* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlsseg7_mask_nxv2f32(float* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv2f32:			; CHECK-LABEL: test_vlsseg7_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg7.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg7.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg7.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg7.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg8.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg8.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg8.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg8.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x float> @test_vlsseg8_nxv2f32(float* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x float> @test_vlsseg8_nxv2f32(float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv2f32:			; CHECK-LABEL: test_vlsseg8_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg8.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg8.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlsseg8_mask_nxv2f32(float* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlsseg8_mask_nxv2f32(float* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv2f32:			; CHECK-LABEL: test_vlsseg8_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg8.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg8.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg8.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg8.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg2.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg2.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)
	declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg2.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg2.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x half> @test_vlsseg2_nxv1f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x half> @test_vlsseg2_nxv1f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv1f16:			; CHECK-LABEL: test_vlsseg2_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg2.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg2.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlsseg2_mask_nxv1f16(half* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlsseg2_mask_nxv1f16(half* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv1f16:			; CHECK-LABEL: test_vlsseg2_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg2.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg2.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg2.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg2.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg3.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg3.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg3.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg3.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x half> @test_vlsseg3_nxv1f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x half> @test_vlsseg3_nxv1f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv1f16:			; CHECK-LABEL: test_vlsseg3_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg3.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg3.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlsseg3_mask_nxv1f16(half* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlsseg3_mask_nxv1f16(half* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv1f16:			; CHECK-LABEL: test_vlsseg3_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg3.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg3.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg3.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg3.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg4.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg4.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg4.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg4.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x half> @test_vlsseg4_nxv1f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x half> @test_vlsseg4_nxv1f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv1f16:			; CHECK-LABEL: test_vlsseg4_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg4.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg4.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlsseg4_mask_nxv1f16(half* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlsseg4_mask_nxv1f16(half* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv1f16:			; CHECK-LABEL: test_vlsseg4_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg4.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg4.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg4.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg4.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg5.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg5.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg5.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg5.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x half> @test_vlsseg5_nxv1f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x half> @test_vlsseg5_nxv1f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv1f16:			; CHECK-LABEL: test_vlsseg5_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg5.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg5.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlsseg5_mask_nxv1f16(half* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlsseg5_mask_nxv1f16(half* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv1f16:			; CHECK-LABEL: test_vlsseg5_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg5.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg5.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg5.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg5.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg6.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg6.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg6.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg6.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x half> @test_vlsseg6_nxv1f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x half> @test_vlsseg6_nxv1f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv1f16:			; CHECK-LABEL: test_vlsseg6_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg6.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg6.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlsseg6_mask_nxv1f16(half* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlsseg6_mask_nxv1f16(half* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv1f16:			; CHECK-LABEL: test_vlsseg6_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg6.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg6.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg6.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg6.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg7.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg7.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg7.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg7.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x half> @test_vlsseg7_nxv1f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x half> @test_vlsseg7_nxv1f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv1f16:			; CHECK-LABEL: test_vlsseg7_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg7.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg7.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlsseg7_mask_nxv1f16(half* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlsseg7_mask_nxv1f16(half* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv1f16:			; CHECK-LABEL: test_vlsseg7_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg7.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg7.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg7.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg7.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg8.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg8.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg8.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg8.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x half> @test_vlsseg8_nxv1f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x half> @test_vlsseg8_nxv1f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv1f16:			; CHECK-LABEL: test_vlsseg8_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg8.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg8.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlsseg8_mask_nxv1f16(half* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlsseg8_mask_nxv1f16(half* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv1f16:			; CHECK-LABEL: test_vlsseg8_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg8.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg8.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg8.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg8.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg2.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg2.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)
	declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg2.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg2.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x float> @test_vlsseg2_nxv1f32(float* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x float> @test_vlsseg2_nxv1f32(float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv1f32:			; CHECK-LABEL: test_vlsseg2_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg2.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg2.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlsseg2_mask_nxv1f32(float* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlsseg2_mask_nxv1f32(float* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv1f32:			; CHECK-LABEL: test_vlsseg2_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg2.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg2.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg2.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg2.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg3.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg3.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg3.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg3.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x float> @test_vlsseg3_nxv1f32(float* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x float> @test_vlsseg3_nxv1f32(float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv1f32:			; CHECK-LABEL: test_vlsseg3_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg3.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg3.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlsseg3_mask_nxv1f32(float* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlsseg3_mask_nxv1f32(float* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv1f32:			; CHECK-LABEL: test_vlsseg3_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg3.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg3.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg3.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg3.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg4.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg4.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg4.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg4.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x float> @test_vlsseg4_nxv1f32(float* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x float> @test_vlsseg4_nxv1f32(float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv1f32:			; CHECK-LABEL: test_vlsseg4_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg4.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg4.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlsseg4_mask_nxv1f32(float* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlsseg4_mask_nxv1f32(float* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv1f32:			; CHECK-LABEL: test_vlsseg4_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg4.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg4.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg4.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg4.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg5.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg5.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg5.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg5.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x float> @test_vlsseg5_nxv1f32(float* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x float> @test_vlsseg5_nxv1f32(float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv1f32:			; CHECK-LABEL: test_vlsseg5_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg5.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg5.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlsseg5_mask_nxv1f32(float* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlsseg5_mask_nxv1f32(float* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv1f32:			; CHECK-LABEL: test_vlsseg5_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg5.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg5.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg5.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg5.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg6.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg6.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg6.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg6.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x float> @test_vlsseg6_nxv1f32(float* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x float> @test_vlsseg6_nxv1f32(float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv1f32:			; CHECK-LABEL: test_vlsseg6_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg6.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg6.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlsseg6_mask_nxv1f32(float* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlsseg6_mask_nxv1f32(float* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv1f32:			; CHECK-LABEL: test_vlsseg6_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg6.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg6.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg6.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg6.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg7.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg7.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg7.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg7.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x float> @test_vlsseg7_nxv1f32(float* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x float> @test_vlsseg7_nxv1f32(float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv1f32:			; CHECK-LABEL: test_vlsseg7_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg7.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg7.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlsseg7_mask_nxv1f32(float* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlsseg7_mask_nxv1f32(float* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv1f32:			; CHECK-LABEL: test_vlsseg7_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg7.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg7.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg7.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg7.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg8.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg8.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg8.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32, i32)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg8.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32, i32)

	define <vscale x 1 x float> @test_vlsseg8_nxv1f32(float* %base, i32 %offset, i32 %vl) {			define <vscale x 1 x float> @test_vlsseg8_nxv1f32(float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv1f32:			; CHECK-LABEL: test_vlsseg8_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg8.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg8.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlsseg8_mask_nxv1f32(float* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlsseg8_mask_nxv1f32(float* %base, i32 %offset, i32 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv1f32:			; CHECK-LABEL: test_vlsseg8_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg8.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg8.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg8.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg8.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg2.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, i32)			declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg2.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, i32)
	declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg2.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg2.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x half> @test_vlsseg2_nxv8f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 8 x half> @test_vlsseg2_nxv8f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv8f16:			; CHECK-LABEL: test_vlsseg2_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg2.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg2.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	define <vscale x 8 x half> @test_vlsseg2_mask_nxv8f16(half* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x half> @test_vlsseg2_mask_nxv8f16(half* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv8f16:			; CHECK-LABEL: test_vlsseg2_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg2.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg2.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
	%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg2.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg2.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1			%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
	ret <vscale x 8 x half> %3			ret <vscale x 8 x half> %3
	}			}

	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg3.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, i32)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg3.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, i32)
	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg3.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg3.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x half> @test_vlsseg3_nxv8f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 8 x half> @test_vlsseg3_nxv8f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv8f16:			; CHECK-LABEL: test_vlsseg3_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg3.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg3.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	define <vscale x 8 x half> @test_vlsseg3_mask_nxv8f16(half* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x half> @test_vlsseg3_mask_nxv8f16(half* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv8f16:			; CHECK-LABEL: test_vlsseg3_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg3.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg3.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
	%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg3.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg3.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1			%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
	ret <vscale x 8 x half> %3			ret <vscale x 8 x half> %3
	}			}

	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg4.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, i32)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg4.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, i32)
	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg4.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg4.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x half> @test_vlsseg4_nxv8f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 8 x half> @test_vlsseg4_nxv8f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv8f16:			; CHECK-LABEL: test_vlsseg4_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg4.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg4.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	define <vscale x 8 x half> @test_vlsseg4_mask_nxv8f16(half* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x half> @test_vlsseg4_mask_nxv8f16(half* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv8f16:			; CHECK-LABEL: test_vlsseg4_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg4.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg4.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
	%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg4.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg4.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1			%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
	ret <vscale x 8 x half> %3			ret <vscale x 8 x half> %3
	}			}

	declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlsseg2.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, i32, i32)			declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlsseg2.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, i32, i32)
	declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlsseg2.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, i32, <vscale x 8 x i1>, i32, i32)			declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlsseg2.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, i32, <vscale x 8 x i1>, i32, i32)

	define <vscale x 8 x float> @test_vlsseg2_nxv8f32(float* %base, i32 %offset, i32 %vl) {			define <vscale x 8 x float> @test_vlsseg2_nxv8f32(float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv8f32:			; CHECK-LABEL: test_vlsseg2_nxv8f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlsseg2.nxv8f32(<vscale x 8 x float> undef, <vscale x 8 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlsseg2.nxv8f32(<vscale x 8 x float> undef, <vscale x 8 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1			%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
	ret <vscale x 8 x float> %1			ret <vscale x 8 x float> %1
	}			}

	define <vscale x 8 x float> @test_vlsseg2_mask_nxv8f32(float* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x float> @test_vlsseg2_mask_nxv8f32(float* %base, i32 %offset, i32 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv8f32:			; CHECK-LABEL: test_vlsseg2_mask_nxv8f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlsseg2.nxv8f32(<vscale x 8 x float> undef, <vscale x 8 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlsseg2.nxv8f32(<vscale x 8 x float> undef, <vscale x 8 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0			%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
	%2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlsseg2.mask.nxv8f32(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlsseg2.mask.nxv8f32(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1			%3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
	ret <vscale x 8 x float> %3			ret <vscale x 8 x float> %3
	}			}

	declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg2.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, i32)			declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg2.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, i32)
	declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg2.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg2.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x double> @test_vlsseg2_nxv2f64(double* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x double> @test_vlsseg2_nxv2f64(double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv2f64:			; CHECK-LABEL: test_vlsseg2_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg2.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg2.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	define <vscale x 2 x double> @test_vlsseg2_mask_nxv2f64(double* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x double> @test_vlsseg2_mask_nxv2f64(double* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv2f64:			; CHECK-LABEL: test_vlsseg2_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg2.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg2.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
	%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg2.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg2.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1			%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
	ret <vscale x 2 x double> %3			ret <vscale x 2 x double> %3
	}			}

	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg3.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, i32)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg3.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, i32)
	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg3.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg3.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x double> @test_vlsseg3_nxv2f64(double* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x double> @test_vlsseg3_nxv2f64(double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv2f64:			; CHECK-LABEL: test_vlsseg3_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg3.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg3.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	define <vscale x 2 x double> @test_vlsseg3_mask_nxv2f64(double* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x double> @test_vlsseg3_mask_nxv2f64(double* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv2f64:			; CHECK-LABEL: test_vlsseg3_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg3.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg3.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
	%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg3.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg3.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1			%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
	ret <vscale x 2 x double> %3			ret <vscale x 2 x double> %3
	}			}

	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg4.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, i32)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg4.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, i32)
	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg4.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg4.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x double> @test_vlsseg4_nxv2f64(double* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x double> @test_vlsseg4_nxv2f64(double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv2f64:			; CHECK-LABEL: test_vlsseg4_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg4.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg4.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	define <vscale x 2 x double> @test_vlsseg4_mask_nxv2f64(double* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x double> @test_vlsseg4_mask_nxv2f64(double* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv2f64:			; CHECK-LABEL: test_vlsseg4_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg4.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg4.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
	%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg4.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg4.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1			%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
	ret <vscale x 2 x double> %3			ret <vscale x 2 x double> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg2.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg2.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)
	declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg2.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg2.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x half> @test_vlsseg2_nxv4f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x half> @test_vlsseg2_nxv4f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv4f16:			; CHECK-LABEL: test_vlsseg2_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg2.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg2.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlsseg2_mask_nxv4f16(half* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlsseg2_mask_nxv4f16(half* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv4f16:			; CHECK-LABEL: test_vlsseg2_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg2.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg2.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg2.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg2.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg3.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg3.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg3.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg3.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x half> @test_vlsseg3_nxv4f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x half> @test_vlsseg3_nxv4f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv4f16:			; CHECK-LABEL: test_vlsseg3_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg3.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg3.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlsseg3_mask_nxv4f16(half* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlsseg3_mask_nxv4f16(half* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv4f16:			; CHECK-LABEL: test_vlsseg3_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg3.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg3.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg3.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg3.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg4.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg4.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg4.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg4.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x half> @test_vlsseg4_nxv4f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x half> @test_vlsseg4_nxv4f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv4f16:			; CHECK-LABEL: test_vlsseg4_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg4.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg4.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlsseg4_mask_nxv4f16(half* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlsseg4_mask_nxv4f16(half* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv4f16:			; CHECK-LABEL: test_vlsseg4_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg4.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg4.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg4.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg4.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg5.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg5.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg5.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg5.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x half> @test_vlsseg5_nxv4f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x half> @test_vlsseg5_nxv4f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv4f16:			; CHECK-LABEL: test_vlsseg5_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg5.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg5.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlsseg5_mask_nxv4f16(half* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlsseg5_mask_nxv4f16(half* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv4f16:			; CHECK-LABEL: test_vlsseg5_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg5.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg5.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg5.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg5.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg6.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg6.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg6.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg6.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x half> @test_vlsseg6_nxv4f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x half> @test_vlsseg6_nxv4f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv4f16:			; CHECK-LABEL: test_vlsseg6_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg6.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg6.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlsseg6_mask_nxv4f16(half* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlsseg6_mask_nxv4f16(half* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv4f16:			; CHECK-LABEL: test_vlsseg6_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg6.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg6.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg6.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg6.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg7.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg7.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg7.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg7.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x half> @test_vlsseg7_nxv4f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x half> @test_vlsseg7_nxv4f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv4f16:			; CHECK-LABEL: test_vlsseg7_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg7.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg7.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlsseg7_mask_nxv4f16(half* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlsseg7_mask_nxv4f16(half* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv4f16:			; CHECK-LABEL: test_vlsseg7_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg7.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg7.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg7.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg7.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg8.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg8.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg8.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg8.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x half> @test_vlsseg8_nxv4f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x half> @test_vlsseg8_nxv4f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv4f16:			; CHECK-LABEL: test_vlsseg8_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg8.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg8.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlsseg8_mask_nxv4f16(half* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlsseg8_mask_nxv4f16(half* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv4f16:			; CHECK-LABEL: test_vlsseg8_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg8.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg8.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg8.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg8.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg2.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg2.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)
	declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg2.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg2.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x half> @test_vlsseg2_nxv2f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x half> @test_vlsseg2_nxv2f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv2f16:			; CHECK-LABEL: test_vlsseg2_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg2.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg2.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlsseg2_mask_nxv2f16(half* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlsseg2_mask_nxv2f16(half* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv2f16:			; CHECK-LABEL: test_vlsseg2_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg2.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg2.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg2.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg2.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg3.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg3.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg3.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg3.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x half> @test_vlsseg3_nxv2f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x half> @test_vlsseg3_nxv2f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv2f16:			; CHECK-LABEL: test_vlsseg3_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg3.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg3.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlsseg3_mask_nxv2f16(half* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlsseg3_mask_nxv2f16(half* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv2f16:			; CHECK-LABEL: test_vlsseg3_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg3.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg3.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg3.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg3.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg4.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg4.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg4.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg4.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x half> @test_vlsseg4_nxv2f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x half> @test_vlsseg4_nxv2f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv2f16:			; CHECK-LABEL: test_vlsseg4_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg4.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg4.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlsseg4_mask_nxv2f16(half* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlsseg4_mask_nxv2f16(half* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv2f16:			; CHECK-LABEL: test_vlsseg4_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg4.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg4.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg4.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg4.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg5.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg5.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg5.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg5.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x half> @test_vlsseg5_nxv2f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x half> @test_vlsseg5_nxv2f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv2f16:			; CHECK-LABEL: test_vlsseg5_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg5.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg5.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlsseg5_mask_nxv2f16(half* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlsseg5_mask_nxv2f16(half* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv2f16:			; CHECK-LABEL: test_vlsseg5_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg5.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg5.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg5.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg5.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg6.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg6.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg6.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg6.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x half> @test_vlsseg6_nxv2f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x half> @test_vlsseg6_nxv2f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv2f16:			; CHECK-LABEL: test_vlsseg6_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg6.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg6.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlsseg6_mask_nxv2f16(half* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlsseg6_mask_nxv2f16(half* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv2f16:			; CHECK-LABEL: test_vlsseg6_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg6.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg6.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg6.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg6.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg7.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg7.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg7.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg7.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x half> @test_vlsseg7_nxv2f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x half> @test_vlsseg7_nxv2f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv2f16:			; CHECK-LABEL: test_vlsseg7_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg7.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg7.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlsseg7_mask_nxv2f16(half* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlsseg7_mask_nxv2f16(half* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv2f16:			; CHECK-LABEL: test_vlsseg7_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg7.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg7.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg7.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg7.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg8.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg8.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg8.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32, i32)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg8.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32, i32)

	define <vscale x 2 x half> @test_vlsseg8_nxv2f16(half* %base, i32 %offset, i32 %vl) {			define <vscale x 2 x half> @test_vlsseg8_nxv2f16(half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv2f16:			; CHECK-LABEL: test_vlsseg8_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg8.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg8.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlsseg8_mask_nxv2f16(half* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlsseg8_mask_nxv2f16(half* %base, i32 %offset, i32 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv2f16:			; CHECK-LABEL: test_vlsseg8_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg8.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg8.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg8.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg8.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg2.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, i32)			declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg2.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, i32)
	declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg2.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg2.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x float> @test_vlsseg2_nxv4f32(float* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x float> @test_vlsseg2_nxv4f32(float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv4f32:			; CHECK-LABEL: test_vlsseg2_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg2.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg2.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	define <vscale x 4 x float> @test_vlsseg2_mask_nxv4f32(float* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x float> @test_vlsseg2_mask_nxv4f32(float* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv4f32:			; CHECK-LABEL: test_vlsseg2_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg2.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg2.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
	%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg2.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg2.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1			%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
	ret <vscale x 4 x float> %3			ret <vscale x 4 x float> %3
	}			}

	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg3.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, i32)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg3.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, i32)
	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg3.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg3.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x float> @test_vlsseg3_nxv4f32(float* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x float> @test_vlsseg3_nxv4f32(float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv4f32:			; CHECK-LABEL: test_vlsseg3_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg3.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg3.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	define <vscale x 4 x float> @test_vlsseg3_mask_nxv4f32(float* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x float> @test_vlsseg3_mask_nxv4f32(float* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv4f32:			; CHECK-LABEL: test_vlsseg3_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg3.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg3.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
	%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg3.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg3.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1			%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
	ret <vscale x 4 x float> %3			ret <vscale x 4 x float> %3
	}			}

	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg4.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, i32)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg4.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, i32)
	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg4.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, <vscale x 4 x i1>, i32, i32)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg4.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, <vscale x 4 x i1>, i32, i32)

	define <vscale x 4 x float> @test_vlsseg4_nxv4f32(float* %base, i32 %offset, i32 %vl) {			define <vscale x 4 x float> @test_vlsseg4_nxv4f32(float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv4f32:			; CHECK-LABEL: test_vlsseg4_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg4.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg4.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	define <vscale x 4 x float> @test_vlsseg4_mask_nxv4f32(float* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x float> @test_vlsseg4_mask_nxv4f32(float* %base, i32 %offset, i32 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv4f32:			; CHECK-LABEL: test_vlsseg4_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg4.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %offset, i32 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg4.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i32 %offset, i32 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
	%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg4.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)			%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg4.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl, i32 1)
	%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1			%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
	ret <vscale x 4 x float> %3			ret <vscale x 4 x float> %3
	}			}

llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \			; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \
	; RUN: -verify-machineinstrs < %s \| FileCheck %s			; RUN: -verify-machineinstrs < %s \| FileCheck %s

	declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, i64)			declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, i64)
	declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, <vscale x 16 x i1>, i64, i64)			declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, <vscale x 16 x i1>, i64, i64)

	define <vscale x 16 x i16> @test_vlsseg2_nxv16i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 16 x i16> @test_vlsseg2_nxv16i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv16i16:			; CHECK-LABEL: test_vlsseg2_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1			%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 1
	ret <vscale x 16 x i16> %1			ret <vscale x 16 x i16> %1
	}			}

	define <vscale x 16 x i16> @test_vlsseg2_mask_nxv16i16(i16* %base, i64 %offset, i64 %vl, <vscale x 16 x i1> %mask) {			define <vscale x 16 x i16> @test_vlsseg2_mask_nxv16i16(i16* %base, i64 %offset, i64 %vl, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv16i16:			; CHECK-LABEL: test_vlsseg2_mask_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0			%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
	%2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.mask.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.mask.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1			%3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
	ret <vscale x 16 x i16> %3			ret <vscale x 16 x i16> %3
	}			}

	declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg2.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, i64)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg2.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, i64)
	declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg2.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg2.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i32> @test_vlsseg2_nxv4i32(i32* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x i32> @test_vlsseg2_nxv4i32(i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv4i32:			; CHECK-LABEL: test_vlsseg2_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	define <vscale x 4 x i32> @test_vlsseg2_mask_nxv4i32(i32* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i32> @test_vlsseg2_mask_nxv4i32(i32* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv4i32:			; CHECK-LABEL: test_vlsseg2_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
	%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg2.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg2.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1			%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
	ret <vscale x 4 x i32> %3			ret <vscale x 4 x i32> %3
	}			}

	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg3.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, i64)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg3.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, i64)
	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg3.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg3.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i32> @test_vlsseg3_nxv4i32(i32* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x i32> @test_vlsseg3_nxv4i32(i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv4i32:			; CHECK-LABEL: test_vlsseg3_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	define <vscale x 4 x i32> @test_vlsseg3_mask_nxv4i32(i32* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i32> @test_vlsseg3_mask_nxv4i32(i32* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv4i32:			; CHECK-LABEL: test_vlsseg3_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
	%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg3.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg3.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1			%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
	ret <vscale x 4 x i32> %3			ret <vscale x 4 x i32> %3
	}			}

	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg4.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, i64)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg4.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, i64)
	declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg4.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg4.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i32> @test_vlsseg4_nxv4i32(i32* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x i32> @test_vlsseg4_nxv4i32(i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv4i32:			; CHECK-LABEL: test_vlsseg4_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg4.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg4.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 1
	ret <vscale x 4 x i32> %1			ret <vscale x 4 x i32> %1
	}			}

	define <vscale x 4 x i32> @test_vlsseg4_mask_nxv4i32(i32* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i32> @test_vlsseg4_mask_nxv4i32(i32* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv4i32:			; CHECK-LABEL: test_vlsseg4_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg4.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg4.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0			%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %0, 0
	%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg4.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlsseg4.mask.nxv4i32(<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1,<vscale x 4 x i32> %1, i32* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1			%3 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} %2, 1
	ret <vscale x 4 x i32> %3			ret <vscale x 4 x i32> %3
	}			}

	declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, i64)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, i64)
	declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, <vscale x 16 x i1>, i64, i64)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, <vscale x 16 x i1>, i64, i64)

	define <vscale x 16 x i8> @test_vlsseg2_nxv16i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 16 x i8> @test_vlsseg2_nxv16i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv16i8:			; CHECK-LABEL: test_vlsseg2_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	define <vscale x 16 x i8> @test_vlsseg2_mask_nxv16i8(i8* %base, i64 %offset, i64 %vl, <vscale x 16 x i1> %mask) {			define <vscale x 16 x i8> @test_vlsseg2_mask_nxv16i8(i8* %base, i64 %offset, i64 %vl, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv16i8:			; CHECK-LABEL: test_vlsseg2_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
	%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg2.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1			%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
	ret <vscale x 16 x i8> %3			ret <vscale x 16 x i8> %3
	}			}

	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, i64)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, i64)
	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, <vscale x 16 x i1>, i64, i64)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, <vscale x 16 x i1>, i64, i64)

	define <vscale x 16 x i8> @test_vlsseg3_nxv16i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 16 x i8> @test_vlsseg3_nxv16i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv16i8:			; CHECK-LABEL: test_vlsseg3_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	define <vscale x 16 x i8> @test_vlsseg3_mask_nxv16i8(i8* %base, i64 %offset, i64 %vl, <vscale x 16 x i1> %mask) {			define <vscale x 16 x i8> @test_vlsseg3_mask_nxv16i8(i8* %base, i64 %offset, i64 %vl, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv16i8:			; CHECK-LABEL: test_vlsseg3_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
	%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg3.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1			%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
	ret <vscale x 16 x i8> %3			ret <vscale x 16 x i8> %3
	}			}

	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, i64)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, i64)
	declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, <vscale x 16 x i1>, i64, i64)			declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, <vscale x 16 x i1>, i64, i64)

	define <vscale x 16 x i8> @test_vlsseg4_nxv16i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 16 x i8> @test_vlsseg4_nxv16i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv16i8:			; CHECK-LABEL: test_vlsseg4_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 1
	ret <vscale x 16 x i8> %1			ret <vscale x 16 x i8> %1
	}			}

	define <vscale x 16 x i8> @test_vlsseg4_mask_nxv16i8(i8* %base, i64 %offset, i64 %vl, <vscale x 16 x i1> %mask) {			define <vscale x 16 x i8> @test_vlsseg4_mask_nxv16i8(i8* %base, i64 %offset, i64 %vl, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv16i8:			; CHECK-LABEL: test_vlsseg4_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0			%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %0, 0
	%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} @llvm.riscv.vlsseg4.mask.nxv16i8(<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1,<vscale x 16 x i8> %1, i8* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1			%3 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>} %2, 1
	ret <vscale x 16 x i8> %3			ret <vscale x 16 x i8> %3
	}			}

	declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg2.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg2.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)
	declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg2.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg2.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i64> @test_vlsseg2_nxv1i64(i64* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i64> @test_vlsseg2_nxv1i64(i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv1i64:			; CHECK-LABEL: test_vlsseg2_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg2.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg2.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	define <vscale x 1 x i64> @test_vlsseg2_mask_nxv1i64(i64* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i64> @test_vlsseg2_mask_nxv1i64(i64* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv1i64:			; CHECK-LABEL: test_vlsseg2_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg2.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg2.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
	%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg2.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg2.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1			%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
	ret <vscale x 1 x i64> %3			ret <vscale x 1 x i64> %3
	}			}

	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg3.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg3.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)
	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg3.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg3.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i64> @test_vlsseg3_nxv1i64(i64* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i64> @test_vlsseg3_nxv1i64(i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv1i64:			; CHECK-LABEL: test_vlsseg3_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg3.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg3.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	define <vscale x 1 x i64> @test_vlsseg3_mask_nxv1i64(i64* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i64> @test_vlsseg3_mask_nxv1i64(i64* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv1i64:			; CHECK-LABEL: test_vlsseg3_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg3.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg3.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
	%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg3.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg3.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1			%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
	ret <vscale x 1 x i64> %3			ret <vscale x 1 x i64> %3
	}			}

	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg4.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg4.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)
	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg4.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg4.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i64> @test_vlsseg4_nxv1i64(i64* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i64> @test_vlsseg4_nxv1i64(i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv1i64:			; CHECK-LABEL: test_vlsseg4_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg4.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg4.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	define <vscale x 1 x i64> @test_vlsseg4_mask_nxv1i64(i64* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i64> @test_vlsseg4_mask_nxv1i64(i64* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv1i64:			; CHECK-LABEL: test_vlsseg4_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg4.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg4.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
	%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg4.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg4.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1			%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
	ret <vscale x 1 x i64> %3			ret <vscale x 1 x i64> %3
	}			}

	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg5.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg5.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)
	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg5.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg5.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i64> @test_vlsseg5_nxv1i64(i64* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i64> @test_vlsseg5_nxv1i64(i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv1i64:			; CHECK-LABEL: test_vlsseg5_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg5.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg5.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	define <vscale x 1 x i64> @test_vlsseg5_mask_nxv1i64(i64* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i64> @test_vlsseg5_mask_nxv1i64(i64* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv1i64:			; CHECK-LABEL: test_vlsseg5_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg5.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg5.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
	%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg5.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg5.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1			%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
	ret <vscale x 1 x i64> %3			ret <vscale x 1 x i64> %3
	}			}

	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg6.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg6.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)
	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg6.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg6.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i64> @test_vlsseg6_nxv1i64(i64* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i64> @test_vlsseg6_nxv1i64(i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv1i64:			; CHECK-LABEL: test_vlsseg6_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg6.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg6.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	define <vscale x 1 x i64> @test_vlsseg6_mask_nxv1i64(i64* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i64> @test_vlsseg6_mask_nxv1i64(i64* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv1i64:			; CHECK-LABEL: test_vlsseg6_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg6.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg6.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
	%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg6.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg6.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1			%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
	ret <vscale x 1 x i64> %3			ret <vscale x 1 x i64> %3
	}			}

	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg7.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg7.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)
	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg7.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg7.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i64> @test_vlsseg7_nxv1i64(i64* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i64> @test_vlsseg7_nxv1i64(i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv1i64:			; CHECK-LABEL: test_vlsseg7_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg7.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg7.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	define <vscale x 1 x i64> @test_vlsseg7_mask_nxv1i64(i64* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i64> @test_vlsseg7_mask_nxv1i64(i64* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv1i64:			; CHECK-LABEL: test_vlsseg7_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg7.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg7.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
	%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg7.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg7.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1			%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
	ret <vscale x 1 x i64> %3			ret <vscale x 1 x i64> %3
	}			}

	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg8.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg8.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)
	declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg8.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg8.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i64> @test_vlsseg8_nxv1i64(i64* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i64> @test_vlsseg8_nxv1i64(i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv1i64:			; CHECK-LABEL: test_vlsseg8_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg8.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef ,<vscale x 1 x i64> undef ,<vscale x 1 x i64> undef, <vscale x 1 x i64> undef ,<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg8.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef ,<vscale x 1 x i64> undef ,<vscale x 1 x i64> undef, <vscale x 1 x i64> undef ,<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 1
	ret <vscale x 1 x i64> %1			ret <vscale x 1 x i64> %1
	}			}

	define <vscale x 1 x i64> @test_vlsseg8_mask_nxv1i64(i64* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i64> @test_vlsseg8_mask_nxv1i64(i64* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv1i64:			; CHECK-LABEL: test_vlsseg8_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg8.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef ,<vscale x 1 x i64> undef ,<vscale x 1 x i64> undef, <vscale x 1 x i64> undef ,<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg8.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> undef ,<vscale x 1 x i64> undef ,<vscale x 1 x i64> undef, <vscale x 1 x i64> undef ,<vscale x 1 x i64> undef, <vscale x 1 x i64> undef, <vscale x 1 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0			%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %0, 0
	%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg8.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} @llvm.riscv.vlsseg8.mask.nxv1i64(<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1,<vscale x 1 x i64> %1, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1			%3 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>} %2, 1
	ret <vscale x 1 x i64> %3			ret <vscale x 1 x i64> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i32> @test_vlsseg2_nxv1i32(i32* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i32> @test_vlsseg2_nxv1i32(i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv1i32:			; CHECK-LABEL: test_vlsseg2_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlsseg2_mask_nxv1i32(i32* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlsseg2_mask_nxv1i32(i32* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv1i32:			; CHECK-LABEL: test_vlsseg2_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg2.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i32> @test_vlsseg3_nxv1i32(i32* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i32> @test_vlsseg3_nxv1i32(i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv1i32:			; CHECK-LABEL: test_vlsseg3_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlsseg3_mask_nxv1i32(i32* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlsseg3_mask_nxv1i32(i32* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv1i32:			; CHECK-LABEL: test_vlsseg3_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg3.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i32> @test_vlsseg4_nxv1i32(i32* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i32> @test_vlsseg4_nxv1i32(i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv1i32:			; CHECK-LABEL: test_vlsseg4_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlsseg4_mask_nxv1i32(i32* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlsseg4_mask_nxv1i32(i32* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv1i32:			; CHECK-LABEL: test_vlsseg4_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg4.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i32> @test_vlsseg5_nxv1i32(i32* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i32> @test_vlsseg5_nxv1i32(i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv1i32:			; CHECK-LABEL: test_vlsseg5_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlsseg5_mask_nxv1i32(i32* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlsseg5_mask_nxv1i32(i32* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv1i32:			; CHECK-LABEL: test_vlsseg5_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg5.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i32> @test_vlsseg6_nxv1i32(i32* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i32> @test_vlsseg6_nxv1i32(i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv1i32:			; CHECK-LABEL: test_vlsseg6_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlsseg6_mask_nxv1i32(i32* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlsseg6_mask_nxv1i32(i32* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv1i32:			; CHECK-LABEL: test_vlsseg6_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg6.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i32> @test_vlsseg7_nxv1i32(i32* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i32> @test_vlsseg7_nxv1i32(i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv1i32:			; CHECK-LABEL: test_vlsseg7_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlsseg7_mask_nxv1i32(i32* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlsseg7_mask_nxv1i32(i32* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv1i32:			; CHECK-LABEL: test_vlsseg7_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg7.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)
	declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i32> @test_vlsseg8_nxv1i32(i32* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i32> @test_vlsseg8_nxv1i32(i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv1i32:			; CHECK-LABEL: test_vlsseg8_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 1
	ret <vscale x 1 x i32> %1			ret <vscale x 1 x i32> %1
	}			}

	define <vscale x 1 x i32> @test_vlsseg8_mask_nxv1i32(i32* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i32> @test_vlsseg8_mask_nxv1i32(i32* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv1i32:			; CHECK-LABEL: test_vlsseg8_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef ,<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, <vscale x 1 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0			%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %0, 0
	%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlsseg8.mask.nxv1i32(<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1,<vscale x 1 x i32> %1, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1			%3 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>} %2, 1
	ret <vscale x 1 x i32> %3			ret <vscale x 1 x i32> %3
	}			}

	declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg2.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, i64)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg2.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, i64)
	declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg2.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg2.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i16> @test_vlsseg2_nxv8i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 8 x i16> @test_vlsseg2_nxv8i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv8i16:			; CHECK-LABEL: test_vlsseg2_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg2.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg2.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	define <vscale x 8 x i16> @test_vlsseg2_mask_nxv8i16(i16* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i16> @test_vlsseg2_mask_nxv8i16(i16* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv8i16:			; CHECK-LABEL: test_vlsseg2_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg2.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg2.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
	%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg2.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg2.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1			%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
	ret <vscale x 8 x i16> %3			ret <vscale x 8 x i16> %3
	}			}

	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg3.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, i64)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg3.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, i64)
	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg3.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg3.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i16> @test_vlsseg3_nxv8i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 8 x i16> @test_vlsseg3_nxv8i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv8i16:			; CHECK-LABEL: test_vlsseg3_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg3.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg3.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	define <vscale x 8 x i16> @test_vlsseg3_mask_nxv8i16(i16* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i16> @test_vlsseg3_mask_nxv8i16(i16* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv8i16:			; CHECK-LABEL: test_vlsseg3_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg3.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg3.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
	%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg3.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg3.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1			%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
	ret <vscale x 8 x i16> %3			ret <vscale x 8 x i16> %3
	}			}

	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg4.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, i64)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg4.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, i64)
	declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg4.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg4.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i16> @test_vlsseg4_nxv8i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 8 x i16> @test_vlsseg4_nxv8i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv8i16:			; CHECK-LABEL: test_vlsseg4_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg4.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg4.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 1
	ret <vscale x 8 x i16> %1			ret <vscale x 8 x i16> %1
	}			}

	define <vscale x 8 x i16> @test_vlsseg4_mask_nxv8i16(i16* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i16> @test_vlsseg4_mask_nxv8i16(i16* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv8i16:			; CHECK-LABEL: test_vlsseg4_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg4.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg4.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, <vscale x 8 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0			%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %0, 0
	%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg4.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} @llvm.riscv.vlsseg4.mask.nxv8i16(<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1,<vscale x 8 x i16> %1, i16* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1			%3 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>} %2, 1
	ret <vscale x 8 x i16> %3			ret <vscale x 8 x i16> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg2.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg2.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg2.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg2.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i8> @test_vlsseg2_nxv4i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x i8> @test_vlsseg2_nxv4i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv4i8:			; CHECK-LABEL: test_vlsseg2_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg2.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg2.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlsseg2_mask_nxv4i8(i8* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlsseg2_mask_nxv4i8(i8* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv4i8:			; CHECK-LABEL: test_vlsseg2_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg2.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg2.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg2.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg2.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg3.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg3.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg3.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg3.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i8> @test_vlsseg3_nxv4i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x i8> @test_vlsseg3_nxv4i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv4i8:			; CHECK-LABEL: test_vlsseg3_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg3.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg3.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlsseg3_mask_nxv4i8(i8* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlsseg3_mask_nxv4i8(i8* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv4i8:			; CHECK-LABEL: test_vlsseg3_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg3.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg3.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg3.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg3.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg4.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg4.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg4.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg4.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i8> @test_vlsseg4_nxv4i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x i8> @test_vlsseg4_nxv4i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv4i8:			; CHECK-LABEL: test_vlsseg4_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg4.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg4.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlsseg4_mask_nxv4i8(i8* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlsseg4_mask_nxv4i8(i8* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv4i8:			; CHECK-LABEL: test_vlsseg4_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg4.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg4.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg4.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg4.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg5.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg5.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg5.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg5.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i8> @test_vlsseg5_nxv4i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x i8> @test_vlsseg5_nxv4i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv4i8:			; CHECK-LABEL: test_vlsseg5_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg5.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg5.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlsseg5_mask_nxv4i8(i8* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlsseg5_mask_nxv4i8(i8* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv4i8:			; CHECK-LABEL: test_vlsseg5_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg5.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg5.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg5.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg5.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg6.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg6.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg6.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg6.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i8> @test_vlsseg6_nxv4i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x i8> @test_vlsseg6_nxv4i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv4i8:			; CHECK-LABEL: test_vlsseg6_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg6.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg6.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlsseg6_mask_nxv4i8(i8* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlsseg6_mask_nxv4i8(i8* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv4i8:			; CHECK-LABEL: test_vlsseg6_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg6.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg6.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg6.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg6.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg7.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg7.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg7.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg7.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i8> @test_vlsseg7_nxv4i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x i8> @test_vlsseg7_nxv4i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv4i8:			; CHECK-LABEL: test_vlsseg7_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg7.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg7.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlsseg7_mask_nxv4i8(i8* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlsseg7_mask_nxv4i8(i8* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv4i8:			; CHECK-LABEL: test_vlsseg7_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg7.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg7.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg7.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg7.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)
	declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg8.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg8.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i8> @test_vlsseg8_nxv4i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x i8> @test_vlsseg8_nxv4i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv4i8:			; CHECK-LABEL: test_vlsseg8_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg8.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg8.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 1
	ret <vscale x 4 x i8> %1			ret <vscale x 4 x i8> %1
	}			}

	define <vscale x 4 x i8> @test_vlsseg8_mask_nxv4i8(i8* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i8> @test_vlsseg8_mask_nxv4i8(i8* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv4i8:			; CHECK-LABEL: test_vlsseg8_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg8.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg8.nxv4i8(<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef ,<vscale x 4 x i8> undef, <vscale x 4 x i8> undef, <vscale x 4 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0			%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %0, 0
	%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg8.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} @llvm.riscv.vlsseg8.mask.nxv4i8(<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1,<vscale x 4 x i8> %1, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1			%3 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>} %2, 1
	ret <vscale x 4 x i8> %3			ret <vscale x 4 x i8> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg2.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg2.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg2.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg2.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i16> @test_vlsseg2_nxv1i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i16> @test_vlsseg2_nxv1i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv1i16:			; CHECK-LABEL: test_vlsseg2_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg2.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg2.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlsseg2_mask_nxv1i16(i16* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlsseg2_mask_nxv1i16(i16* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv1i16:			; CHECK-LABEL: test_vlsseg2_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg2.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg2.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg2.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg2.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg3.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg3.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg3.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg3.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i16> @test_vlsseg3_nxv1i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i16> @test_vlsseg3_nxv1i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv1i16:			; CHECK-LABEL: test_vlsseg3_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg3.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg3.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlsseg3_mask_nxv1i16(i16* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlsseg3_mask_nxv1i16(i16* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv1i16:			; CHECK-LABEL: test_vlsseg3_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg3.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg3.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg3.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg3.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg4.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg4.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg4.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg4.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i16> @test_vlsseg4_nxv1i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i16> @test_vlsseg4_nxv1i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv1i16:			; CHECK-LABEL: test_vlsseg4_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg4.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg4.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlsseg4_mask_nxv1i16(i16* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlsseg4_mask_nxv1i16(i16* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv1i16:			; CHECK-LABEL: test_vlsseg4_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg4.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg4.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg4.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg4.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg5.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg5.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg5.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg5.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i16> @test_vlsseg5_nxv1i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i16> @test_vlsseg5_nxv1i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv1i16:			; CHECK-LABEL: test_vlsseg5_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg5.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg5.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlsseg5_mask_nxv1i16(i16* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlsseg5_mask_nxv1i16(i16* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv1i16:			; CHECK-LABEL: test_vlsseg5_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg5.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg5.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg5.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg5.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg6.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg6.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg6.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg6.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i16> @test_vlsseg6_nxv1i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i16> @test_vlsseg6_nxv1i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv1i16:			; CHECK-LABEL: test_vlsseg6_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg6.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg6.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlsseg6_mask_nxv1i16(i16* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlsseg6_mask_nxv1i16(i16* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv1i16:			; CHECK-LABEL: test_vlsseg6_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg6.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg6.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg6.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg6.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg7.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg7.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg7.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg7.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i16> @test_vlsseg7_nxv1i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i16> @test_vlsseg7_nxv1i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv1i16:			; CHECK-LABEL: test_vlsseg7_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg7.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg7.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlsseg7_mask_nxv1i16(i16* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlsseg7_mask_nxv1i16(i16* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv1i16:			; CHECK-LABEL: test_vlsseg7_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg7.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg7.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg7.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg7.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg8.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg8.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)
	declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg8.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg8.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i16> @test_vlsseg8_nxv1i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i16> @test_vlsseg8_nxv1i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv1i16:			; CHECK-LABEL: test_vlsseg8_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg8.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg8.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 1
	ret <vscale x 1 x i16> %1			ret <vscale x 1 x i16> %1
	}			}

	define <vscale x 1 x i16> @test_vlsseg8_mask_nxv1i16(i16* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i16> @test_vlsseg8_mask_nxv1i16(i16* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv1i16:			; CHECK-LABEL: test_vlsseg8_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg8.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg8.nxv1i16(<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef ,<vscale x 1 x i16> undef, <vscale x 1 x i16> undef, <vscale x 1 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0			%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %0, 0
	%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg8.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} @llvm.riscv.vlsseg8.mask.nxv1i16(<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1,<vscale x 1 x i16> %1, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1			%3 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>} %2, 1
	ret <vscale x 1 x i16> %3			ret <vscale x 1 x i16> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i32> @test_vlsseg2_nxv2i32(i32* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i32> @test_vlsseg2_nxv2i32(i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv2i32:			; CHECK-LABEL: test_vlsseg2_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlsseg2_mask_nxv2i32(i32* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlsseg2_mask_nxv2i32(i32* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv2i32:			; CHECK-LABEL: test_vlsseg2_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg2.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i32> @test_vlsseg3_nxv2i32(i32* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i32> @test_vlsseg3_nxv2i32(i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv2i32:			; CHECK-LABEL: test_vlsseg3_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlsseg3_mask_nxv2i32(i32* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlsseg3_mask_nxv2i32(i32* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv2i32:			; CHECK-LABEL: test_vlsseg3_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg3.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i32> @test_vlsseg4_nxv2i32(i32* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i32> @test_vlsseg4_nxv2i32(i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv2i32:			; CHECK-LABEL: test_vlsseg4_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlsseg4_mask_nxv2i32(i32* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlsseg4_mask_nxv2i32(i32* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv2i32:			; CHECK-LABEL: test_vlsseg4_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg4.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i32> @test_vlsseg5_nxv2i32(i32* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i32> @test_vlsseg5_nxv2i32(i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv2i32:			; CHECK-LABEL: test_vlsseg5_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlsseg5_mask_nxv2i32(i32* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlsseg5_mask_nxv2i32(i32* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv2i32:			; CHECK-LABEL: test_vlsseg5_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg5.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i32> @test_vlsseg6_nxv2i32(i32* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i32> @test_vlsseg6_nxv2i32(i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv2i32:			; CHECK-LABEL: test_vlsseg6_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlsseg6_mask_nxv2i32(i32* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlsseg6_mask_nxv2i32(i32* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv2i32:			; CHECK-LABEL: test_vlsseg6_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg6.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i32> @test_vlsseg7_nxv2i32(i32* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i32> @test_vlsseg7_nxv2i32(i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv2i32:			; CHECK-LABEL: test_vlsseg7_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlsseg7_mask_nxv2i32(i32* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlsseg7_mask_nxv2i32(i32* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv2i32:			; CHECK-LABEL: test_vlsseg7_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg7.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)
	declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i32> @test_vlsseg8_nxv2i32(i32* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i32> @test_vlsseg8_nxv2i32(i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv2i32:			; CHECK-LABEL: test_vlsseg8_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 1
	ret <vscale x 2 x i32> %1			ret <vscale x 2 x i32> %1
	}			}

	define <vscale x 2 x i32> @test_vlsseg8_mask_nxv2i32(i32* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i32> @test_vlsseg8_mask_nxv2i32(i32* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv2i32:			; CHECK-LABEL: test_vlsseg8_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef ,<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, <vscale x 2 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0			%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %0, 0
	%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlsseg8.mask.nxv2i32(<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1,<vscale x 2 x i32> %1, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1			%3 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>} %2, 1
	ret <vscale x 2 x i32> %3			ret <vscale x 2 x i32> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg2.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg2.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg2.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg2.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i8> @test_vlsseg2_nxv8i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 8 x i8> @test_vlsseg2_nxv8i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv8i8:			; CHECK-LABEL: test_vlsseg2_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg2.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg2.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlsseg2_mask_nxv8i8(i8* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlsseg2_mask_nxv8i8(i8* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv8i8:			; CHECK-LABEL: test_vlsseg2_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg2.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg2.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg2.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg2.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg3.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg3.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg3.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg3.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i8> @test_vlsseg3_nxv8i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 8 x i8> @test_vlsseg3_nxv8i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv8i8:			; CHECK-LABEL: test_vlsseg3_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg3.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg3.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlsseg3_mask_nxv8i8(i8* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlsseg3_mask_nxv8i8(i8* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv8i8:			; CHECK-LABEL: test_vlsseg3_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg3.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg3.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg3.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg3.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg4.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg4.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg4.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg4.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i8> @test_vlsseg4_nxv8i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 8 x i8> @test_vlsseg4_nxv8i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv8i8:			; CHECK-LABEL: test_vlsseg4_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg4.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg4.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlsseg4_mask_nxv8i8(i8* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlsseg4_mask_nxv8i8(i8* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv8i8:			; CHECK-LABEL: test_vlsseg4_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg4.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg4.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg4.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg4.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg5.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg5.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg5.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg5.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i8> @test_vlsseg5_nxv8i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 8 x i8> @test_vlsseg5_nxv8i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv8i8:			; CHECK-LABEL: test_vlsseg5_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg5.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg5.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlsseg5_mask_nxv8i8(i8* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlsseg5_mask_nxv8i8(i8* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv8i8:			; CHECK-LABEL: test_vlsseg5_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg5.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg5.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg5.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg5.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg6.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg6.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg6.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg6.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i8> @test_vlsseg6_nxv8i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 8 x i8> @test_vlsseg6_nxv8i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv8i8:			; CHECK-LABEL: test_vlsseg6_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg6.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg6.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlsseg6_mask_nxv8i8(i8* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlsseg6_mask_nxv8i8(i8* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv8i8:			; CHECK-LABEL: test_vlsseg6_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg6.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg6.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg6.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg6.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg7.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg7.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg7.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg7.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i8> @test_vlsseg7_nxv8i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 8 x i8> @test_vlsseg7_nxv8i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv8i8:			; CHECK-LABEL: test_vlsseg7_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg7.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg7.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlsseg7_mask_nxv8i8(i8* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlsseg7_mask_nxv8i8(i8* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv8i8:			; CHECK-LABEL: test_vlsseg7_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg7.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg7.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg7.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg7.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)
	declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg8.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg8.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i8> @test_vlsseg8_nxv8i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 8 x i8> @test_vlsseg8_nxv8i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv8i8:			; CHECK-LABEL: test_vlsseg8_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg8.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg8.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 1
	ret <vscale x 8 x i8> %1			ret <vscale x 8 x i8> %1
	}			}

	define <vscale x 8 x i8> @test_vlsseg8_mask_nxv8i8(i8* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i8> @test_vlsseg8_mask_nxv8i8(i8* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv8i8:			; CHECK-LABEL: test_vlsseg8_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg8.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg8.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef ,<vscale x 8 x i8> undef, <vscale x 8 x i8> undef, <vscale x 8 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0			%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %0, 0
	%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg8.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} @llvm.riscv.vlsseg8.mask.nxv8i8(<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1,<vscale x 8 x i8> %1, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1			%3 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>} %2, 1
	ret <vscale x 8 x i8> %3			ret <vscale x 8 x i8> %3
	}			}

	declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlsseg2.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, i64, i64)			declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlsseg2.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, i64, i64)
	declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlsseg2.mask.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlsseg2.mask.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i64> @test_vlsseg2_nxv4i64(i64* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x i64> @test_vlsseg2_nxv4i64(i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv4i64:			; CHECK-LABEL: test_vlsseg2_nxv4i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
	; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlsseg2.nxv4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlsseg2.nxv4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1			%1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 1
	ret <vscale x 4 x i64> %1			ret <vscale x 4 x i64> %1
	}			}

	define <vscale x 4 x i64> @test_vlsseg2_mask_nxv4i64(i64* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i64> @test_vlsseg2_mask_nxv4i64(i64* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv4i64:			; CHECK-LABEL: test_vlsseg2_mask_nxv4i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
	; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlsseg2.nxv4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlsseg2.nxv4i64(<vscale x 4 x i64> undef, <vscale x 4 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0			%1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %0, 0
	%2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlsseg2.mask.nxv4i64(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>} @llvm.riscv.vlsseg2.mask.nxv4i64(<vscale x 4 x i64> %1,<vscale x 4 x i64> %1, i64* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1			%3 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>} %2, 1
	ret <vscale x 4 x i64> %3			ret <vscale x 4 x i64> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i16> @test_vlsseg2_nxv4i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x i16> @test_vlsseg2_nxv4i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv4i16:			; CHECK-LABEL: test_vlsseg2_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlsseg2_mask_nxv4i16(i16* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlsseg2_mask_nxv4i16(i16* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv4i16:			; CHECK-LABEL: test_vlsseg2_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg2.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i16> @test_vlsseg3_nxv4i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x i16> @test_vlsseg3_nxv4i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv4i16:			; CHECK-LABEL: test_vlsseg3_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlsseg3_mask_nxv4i16(i16* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlsseg3_mask_nxv4i16(i16* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv4i16:			; CHECK-LABEL: test_vlsseg3_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg3.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i16> @test_vlsseg4_nxv4i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x i16> @test_vlsseg4_nxv4i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv4i16:			; CHECK-LABEL: test_vlsseg4_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlsseg4_mask_nxv4i16(i16* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlsseg4_mask_nxv4i16(i16* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv4i16:			; CHECK-LABEL: test_vlsseg4_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg4.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i16> @test_vlsseg5_nxv4i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x i16> @test_vlsseg5_nxv4i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv4i16:			; CHECK-LABEL: test_vlsseg5_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlsseg5_mask_nxv4i16(i16* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlsseg5_mask_nxv4i16(i16* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv4i16:			; CHECK-LABEL: test_vlsseg5_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg5.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i16> @test_vlsseg6_nxv4i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x i16> @test_vlsseg6_nxv4i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv4i16:			; CHECK-LABEL: test_vlsseg6_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlsseg6_mask_nxv4i16(i16* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlsseg6_mask_nxv4i16(i16* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv4i16:			; CHECK-LABEL: test_vlsseg6_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg6.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i16> @test_vlsseg7_nxv4i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x i16> @test_vlsseg7_nxv4i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv4i16:			; CHECK-LABEL: test_vlsseg7_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlsseg7_mask_nxv4i16(i16* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlsseg7_mask_nxv4i16(i16* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv4i16:			; CHECK-LABEL: test_vlsseg7_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg7.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)
	declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x i16> @test_vlsseg8_nxv4i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x i16> @test_vlsseg8_nxv4i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv4i16:			; CHECK-LABEL: test_vlsseg8_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 1
	ret <vscale x 4 x i16> %1			ret <vscale x 4 x i16> %1
	}			}

	define <vscale x 4 x i16> @test_vlsseg8_mask_nxv4i16(i16* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x i16> @test_vlsseg8_mask_nxv4i16(i16* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv4i16:			; CHECK-LABEL: test_vlsseg8_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.nxv4i16(<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef ,<vscale x 4 x i16> undef, <vscale x 4 x i16> undef, <vscale x 4 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0			%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %0, 0
	%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} @llvm.riscv.vlsseg8.mask.nxv4i16(<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1,<vscale x 4 x i16> %1, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1			%3 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>} %2, 1
	ret <vscale x 4 x i16> %3			ret <vscale x 4 x i16> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i8> @test_vlsseg2_nxv1i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i8> @test_vlsseg2_nxv1i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv1i8:			; CHECK-LABEL: test_vlsseg2_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlsseg2_mask_nxv1i8(i8* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlsseg2_mask_nxv1i8(i8* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv1i8:			; CHECK-LABEL: test_vlsseg2_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg2.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i8> @test_vlsseg3_nxv1i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i8> @test_vlsseg3_nxv1i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv1i8:			; CHECK-LABEL: test_vlsseg3_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlsseg3_mask_nxv1i8(i8* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlsseg3_mask_nxv1i8(i8* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv1i8:			; CHECK-LABEL: test_vlsseg3_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg3.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i8> @test_vlsseg4_nxv1i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i8> @test_vlsseg4_nxv1i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv1i8:			; CHECK-LABEL: test_vlsseg4_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlsseg4_mask_nxv1i8(i8* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlsseg4_mask_nxv1i8(i8* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv1i8:			; CHECK-LABEL: test_vlsseg4_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg4.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i8> @test_vlsseg5_nxv1i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i8> @test_vlsseg5_nxv1i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv1i8:			; CHECK-LABEL: test_vlsseg5_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlsseg5_mask_nxv1i8(i8* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlsseg5_mask_nxv1i8(i8* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv1i8:			; CHECK-LABEL: test_vlsseg5_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg5.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i8> @test_vlsseg6_nxv1i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i8> @test_vlsseg6_nxv1i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv1i8:			; CHECK-LABEL: test_vlsseg6_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlsseg6_mask_nxv1i8(i8* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlsseg6_mask_nxv1i8(i8* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv1i8:			; CHECK-LABEL: test_vlsseg6_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg6.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i8> @test_vlsseg7_nxv1i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i8> @test_vlsseg7_nxv1i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv1i8:			; CHECK-LABEL: test_vlsseg7_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlsseg7_mask_nxv1i8(i8* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlsseg7_mask_nxv1i8(i8* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv1i8:			; CHECK-LABEL: test_vlsseg7_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg7.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)
	declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x i8> @test_vlsseg8_nxv1i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x i8> @test_vlsseg8_nxv1i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv1i8:			; CHECK-LABEL: test_vlsseg8_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 1
	ret <vscale x 1 x i8> %1			ret <vscale x 1 x i8> %1
	}			}

	define <vscale x 1 x i8> @test_vlsseg8_mask_nxv1i8(i8* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x i8> @test_vlsseg8_mask_nxv1i8(i8* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv1i8:			; CHECK-LABEL: test_vlsseg8_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef ,<vscale x 1 x i8> undef, <vscale x 1 x i8> undef, <vscale x 1 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0			%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %0, 0
	%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} @llvm.riscv.vlsseg8.mask.nxv1i8(<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1,<vscale x 1 x i8> %1, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1			%3 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>} %2, 1
	ret <vscale x 1 x i8> %3			ret <vscale x 1 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg2.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg2.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg2.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg2.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i8> @test_vlsseg2_nxv2i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i8> @test_vlsseg2_nxv2i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv2i8:			; CHECK-LABEL: test_vlsseg2_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg2.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg2.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlsseg2_mask_nxv2i8(i8* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlsseg2_mask_nxv2i8(i8* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv2i8:			; CHECK-LABEL: test_vlsseg2_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg2.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg2.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg2.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg2.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg3.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg3.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg3.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg3.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i8> @test_vlsseg3_nxv2i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i8> @test_vlsseg3_nxv2i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv2i8:			; CHECK-LABEL: test_vlsseg3_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg3.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg3.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlsseg3_mask_nxv2i8(i8* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlsseg3_mask_nxv2i8(i8* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv2i8:			; CHECK-LABEL: test_vlsseg3_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg3.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg3.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg3.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg3.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg4.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg4.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg4.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg4.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i8> @test_vlsseg4_nxv2i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i8> @test_vlsseg4_nxv2i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv2i8:			; CHECK-LABEL: test_vlsseg4_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg4.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg4.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlsseg4_mask_nxv2i8(i8* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlsseg4_mask_nxv2i8(i8* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv2i8:			; CHECK-LABEL: test_vlsseg4_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg4.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg4.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg4.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg4.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg5.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg5.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg5.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg5.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i8> @test_vlsseg5_nxv2i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i8> @test_vlsseg5_nxv2i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv2i8:			; CHECK-LABEL: test_vlsseg5_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg5.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg5.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlsseg5_mask_nxv2i8(i8* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlsseg5_mask_nxv2i8(i8* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv2i8:			; CHECK-LABEL: test_vlsseg5_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg5.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg5.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg5.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg5.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg6.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg6.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg6.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg6.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i8> @test_vlsseg6_nxv2i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i8> @test_vlsseg6_nxv2i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv2i8:			; CHECK-LABEL: test_vlsseg6_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg6.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg6.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlsseg6_mask_nxv2i8(i8* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlsseg6_mask_nxv2i8(i8* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv2i8:			; CHECK-LABEL: test_vlsseg6_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg6.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg6.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg6.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg6.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg7.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg7.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg7.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg7.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i8> @test_vlsseg7_nxv2i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i8> @test_vlsseg7_nxv2i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv2i8:			; CHECK-LABEL: test_vlsseg7_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg7.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg7.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlsseg7_mask_nxv2i8(i8* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlsseg7_mask_nxv2i8(i8* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv2i8:			; CHECK-LABEL: test_vlsseg7_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg7.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg7.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg7.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg7.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)
	declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg8.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg8.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i8> @test_vlsseg8_nxv2i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i8> @test_vlsseg8_nxv2i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv2i8:			; CHECK-LABEL: test_vlsseg8_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg8.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg8.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 1
	ret <vscale x 2 x i8> %1			ret <vscale x 2 x i8> %1
	}			}

	define <vscale x 2 x i8> @test_vlsseg8_mask_nxv2i8(i8* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i8> @test_vlsseg8_mask_nxv2i8(i8* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv2i8:			; CHECK-LABEL: test_vlsseg8_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg8.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg8.nxv2i8(<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef ,<vscale x 2 x i8> undef, <vscale x 2 x i8> undef, <vscale x 2 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0			%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %0, 0
	%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg8.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} @llvm.riscv.vlsseg8.mask.nxv2i8(<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1,<vscale x 2 x i8> %1, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1			%3 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>} %2, 1
	ret <vscale x 2 x i8> %3			ret <vscale x 2 x i8> %3
	}			}

	declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlsseg2.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, i64, i64)			declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlsseg2.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, i64, i64)
	declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlsseg2.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, i64, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlsseg2.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, i64, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x i32> @test_vlsseg2_nxv8i32(i32* %base, i64 %offset, i64 %vl) {			define <vscale x 8 x i32> @test_vlsseg2_nxv8i32(i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv8i32:			; CHECK-LABEL: test_vlsseg2_nxv8i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlsseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlsseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1			%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 1
	ret <vscale x 8 x i32> %1			ret <vscale x 8 x i32> %1
	}			}

	define <vscale x 8 x i32> @test_vlsseg2_mask_nxv8i32(i32* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x i32> @test_vlsseg2_mask_nxv8i32(i32* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv8i32:			; CHECK-LABEL: test_vlsseg2_mask_nxv8i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlsseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlsseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, i32* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0			%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %0, 0
	%2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlsseg2.mask.nxv8i32(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlsseg2.mask.nxv8i32(<vscale x 8 x i32> %1,<vscale x 8 x i32> %1, i32* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1			%3 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>} %2, 1
	ret <vscale x 8 x i32> %3			ret <vscale x 8 x i32> %3
	}			}

	declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlsseg2.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, i64, i64)			declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlsseg2.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, i64, i64)
	declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlsseg2.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, i64, <vscale x 32 x i1>, i64, i64)			declare {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlsseg2.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, i64, <vscale x 32 x i1>, i64, i64)

	define <vscale x 32 x i8> @test_vlsseg2_nxv32i8(i8* %base, i64 %offset, i64 %vl) {			define <vscale x 32 x i8> @test_vlsseg2_nxv32i8(i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv32i8:			; CHECK-LABEL: test_vlsseg2_nxv32i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlsseg2.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlsseg2.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1			%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 1
	ret <vscale x 32 x i8> %1			ret <vscale x 32 x i8> %1
	}			}

	define <vscale x 32 x i8> @test_vlsseg2_mask_nxv32i8(i8* %base, i64 %offset, i64 %vl, <vscale x 32 x i1> %mask) {			define <vscale x 32 x i8> @test_vlsseg2_mask_nxv32i8(i8* %base, i64 %offset, i64 %vl, <vscale x 32 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv32i8:			; CHECK-LABEL: test_vlsseg2_mask_nxv32i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
	; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlsseg2.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i8> undef, i8* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlsseg2.nxv32i8(<vscale x 32 x i8> undef, <vscale x 32 x i8> undef, i8* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0			%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %0, 0
	%2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlsseg2.mask.nxv32i8(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, i64 %offset, <vscale x 32 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>} @llvm.riscv.vlsseg2.mask.nxv32i8(<vscale x 32 x i8> %1,<vscale x 32 x i8> %1, i8* %base, i64 %offset, <vscale x 32 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1			%3 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>} %2, 1
	ret <vscale x 32 x i8> %3			ret <vscale x 32 x i8> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg2.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg2.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg2.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg2.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i16> @test_vlsseg2_nxv2i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i16> @test_vlsseg2_nxv2i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv2i16:			; CHECK-LABEL: test_vlsseg2_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg2.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg2.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlsseg2_mask_nxv2i16(i16* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlsseg2_mask_nxv2i16(i16* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv2i16:			; CHECK-LABEL: test_vlsseg2_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg2.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg2.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg2.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg2.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg3.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg3.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg3.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg3.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i16> @test_vlsseg3_nxv2i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i16> @test_vlsseg3_nxv2i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv2i16:			; CHECK-LABEL: test_vlsseg3_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg3.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg3.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlsseg3_mask_nxv2i16(i16* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlsseg3_mask_nxv2i16(i16* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv2i16:			; CHECK-LABEL: test_vlsseg3_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg3.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg3.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg3.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg3.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg4.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg4.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg4.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg4.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i16> @test_vlsseg4_nxv2i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i16> @test_vlsseg4_nxv2i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv2i16:			; CHECK-LABEL: test_vlsseg4_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg4.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg4.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlsseg4_mask_nxv2i16(i16* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlsseg4_mask_nxv2i16(i16* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv2i16:			; CHECK-LABEL: test_vlsseg4_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg4.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg4.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg4.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg4.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg5.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg5.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg5.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg5.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i16> @test_vlsseg5_nxv2i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i16> @test_vlsseg5_nxv2i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv2i16:			; CHECK-LABEL: test_vlsseg5_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg5.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg5.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlsseg5_mask_nxv2i16(i16* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlsseg5_mask_nxv2i16(i16* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv2i16:			; CHECK-LABEL: test_vlsseg5_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg5.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg5.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg5.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg5.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg6.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg6.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg6.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg6.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i16> @test_vlsseg6_nxv2i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i16> @test_vlsseg6_nxv2i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv2i16:			; CHECK-LABEL: test_vlsseg6_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg6.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg6.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlsseg6_mask_nxv2i16(i16* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlsseg6_mask_nxv2i16(i16* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv2i16:			; CHECK-LABEL: test_vlsseg6_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg6.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg6.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg6.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg6.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg7.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg7.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg7.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg7.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i16> @test_vlsseg7_nxv2i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i16> @test_vlsseg7_nxv2i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv2i16:			; CHECK-LABEL: test_vlsseg7_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg7.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg7.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlsseg7_mask_nxv2i16(i16* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlsseg7_mask_nxv2i16(i16* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv2i16:			; CHECK-LABEL: test_vlsseg7_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg7.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg7.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg7.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg7.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg8.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg8.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)
	declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg8.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg8.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i16> @test_vlsseg8_nxv2i16(i16* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i16> @test_vlsseg8_nxv2i16(i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv2i16:			; CHECK-LABEL: test_vlsseg8_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg8.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg8.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 1
	ret <vscale x 2 x i16> %1			ret <vscale x 2 x i16> %1
	}			}

	define <vscale x 2 x i16> @test_vlsseg8_mask_nxv2i16(i16* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i16> @test_vlsseg8_mask_nxv2i16(i16* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv2i16:			; CHECK-LABEL: test_vlsseg8_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg8.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg8.nxv2i16(<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef ,<vscale x 2 x i16> undef, <vscale x 2 x i16> undef, <vscale x 2 x i16> undef, i16* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0			%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %0, 0
	%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg8.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} @llvm.riscv.vlsseg8.mask.nxv2i16(<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1,<vscale x 2 x i16> %1, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1			%3 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>} %2, 1
	ret <vscale x 2 x i16> %3			ret <vscale x 2 x i16> %3
	}			}

	declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg2.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, i64)			declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg2.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, i64)
	declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg2.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg2.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i64> @test_vlsseg2_nxv2i64(i64* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i64> @test_vlsseg2_nxv2i64(i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv2i64:			; CHECK-LABEL: test_vlsseg2_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg2.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg2.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1			%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
	ret <vscale x 2 x i64> %1			ret <vscale x 2 x i64> %1
	}			}

	define <vscale x 2 x i64> @test_vlsseg2_mask_nxv2i64(i64* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i64> @test_vlsseg2_mask_nxv2i64(i64* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv2i64:			; CHECK-LABEL: test_vlsseg2_mask_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg2.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg2.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0			%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
	%2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg2.mask.nxv2i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg2.mask.nxv2i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1			%3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
	ret <vscale x 2 x i64> %3			ret <vscale x 2 x i64> %3
	}			}

	declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg3.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, i64)			declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg3.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, i64)
	declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg3.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg3.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i64> @test_vlsseg3_nxv2i64(i64* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i64> @test_vlsseg3_nxv2i64(i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv2i64:			; CHECK-LABEL: test_vlsseg3_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg3.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg3.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1			%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
	ret <vscale x 2 x i64> %1			ret <vscale x 2 x i64> %1
	}			}

	define <vscale x 2 x i64> @test_vlsseg3_mask_nxv2i64(i64* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i64> @test_vlsseg3_mask_nxv2i64(i64* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv2i64:			; CHECK-LABEL: test_vlsseg3_mask_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg3.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg3.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0			%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
	%2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg3.mask.nxv2i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg3.mask.nxv2i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1			%3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
	ret <vscale x 2 x i64> %3			ret <vscale x 2 x i64> %3
	}			}

	declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg4.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, i64)			declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg4.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, i64)
	declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg4.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg4.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x i64> @test_vlsseg4_nxv2i64(i64* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x i64> @test_vlsseg4_nxv2i64(i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv2i64:			; CHECK-LABEL: test_vlsseg4_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg4.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg4.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1			%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 1
	ret <vscale x 2 x i64> %1			ret <vscale x 2 x i64> %1
	}			}

	define <vscale x 2 x i64> @test_vlsseg4_mask_nxv2i64(i64* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x i64> @test_vlsseg4_mask_nxv2i64(i64* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv2i64:			; CHECK-LABEL: test_vlsseg4_mask_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg4.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg4.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, <vscale x 2 x i64> undef, i64* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0			%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %0, 0
	%2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg4.mask.nxv2i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} @llvm.riscv.vlsseg4.mask.nxv2i64(<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1,<vscale x 2 x i64> %1, i64* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1			%3 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>} %2, 1
	ret <vscale x 2 x i64> %3			ret <vscale x 2 x i64> %3
	}			}

	declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlsseg2.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, i64, i64)			declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlsseg2.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, i64, i64)
	declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlsseg2.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, i64, <vscale x 16 x i1>, i64, i64)			declare {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlsseg2.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, i64, <vscale x 16 x i1>, i64, i64)

	define <vscale x 16 x half> @test_vlsseg2_nxv16f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 16 x half> @test_vlsseg2_nxv16f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv16f16:			; CHECK-LABEL: test_vlsseg2_nxv16f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlsseg2.nxv16f16(<vscale x 16 x half> undef, <vscale x 16 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlsseg2.nxv16f16(<vscale x 16 x half> undef, <vscale x 16 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1			%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 1
	ret <vscale x 16 x half> %1			ret <vscale x 16 x half> %1
	}			}

	define <vscale x 16 x half> @test_vlsseg2_mask_nxv16f16(half* %base, i64 %offset, i64 %vl, <vscale x 16 x i1> %mask) {			define <vscale x 16 x half> @test_vlsseg2_mask_nxv16f16(half* %base, i64 %offset, i64 %vl, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv16f16:			; CHECK-LABEL: test_vlsseg2_mask_nxv16f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlsseg2.nxv16f16(<vscale x 16 x half> undef, <vscale x 16 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlsseg2.nxv16f16(<vscale x 16 x half> undef, <vscale x 16 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0			%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %0, 0
	%2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlsseg2.mask.nxv16f16(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 16 x half>,<vscale x 16 x half>} @llvm.riscv.vlsseg2.mask.nxv16f16(<vscale x 16 x half> %1,<vscale x 16 x half> %1, half* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1			%3 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>} %2, 1
	ret <vscale x 16 x half> %3			ret <vscale x 16 x half> %3
	}			}

	declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlsseg2.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, i64, i64)			declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlsseg2.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, i64, i64)
	declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlsseg2.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlsseg2.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x double> @test_vlsseg2_nxv4f64(double* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x double> @test_vlsseg2_nxv4f64(double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv4f64:			; CHECK-LABEL: test_vlsseg2_nxv4f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
	; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlsseg2.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlsseg2.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1			%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 1
	ret <vscale x 4 x double> %1			ret <vscale x 4 x double> %1
	}			}

	define <vscale x 4 x double> @test_vlsseg2_mask_nxv4f64(double* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x double> @test_vlsseg2_mask_nxv4f64(double* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv4f64:			; CHECK-LABEL: test_vlsseg2_mask_nxv4f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
	; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlsseg2.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlsseg2.nxv4f64(<vscale x 4 x double> undef, <vscale x 4 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0			%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %0, 0
	%2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlsseg2.mask.nxv4f64(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x double>,<vscale x 4 x double>} @llvm.riscv.vlsseg2.mask.nxv4f64(<vscale x 4 x double> %1,<vscale x 4 x double> %1, double* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1			%3 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>} %2, 1
	ret <vscale x 4 x double> %3			ret <vscale x 4 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg2.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg2.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)
	declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg2.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg2.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x double> @test_vlsseg2_nxv1f64(double* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x double> @test_vlsseg2_nxv1f64(double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv1f64:			; CHECK-LABEL: test_vlsseg2_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg2.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg2.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlsseg2_mask_nxv1f64(double* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlsseg2_mask_nxv1f64(double* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv1f64:			; CHECK-LABEL: test_vlsseg2_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg2.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg2.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg2.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg2.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg3.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg3.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg3.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg3.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x double> @test_vlsseg3_nxv1f64(double* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x double> @test_vlsseg3_nxv1f64(double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv1f64:			; CHECK-LABEL: test_vlsseg3_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg3.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg3.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlsseg3_mask_nxv1f64(double* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlsseg3_mask_nxv1f64(double* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv1f64:			; CHECK-LABEL: test_vlsseg3_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg3.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg3.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg3.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg3.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg4.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg4.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg4.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg4.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x double> @test_vlsseg4_nxv1f64(double* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x double> @test_vlsseg4_nxv1f64(double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv1f64:			; CHECK-LABEL: test_vlsseg4_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg4.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg4.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlsseg4_mask_nxv1f64(double* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlsseg4_mask_nxv1f64(double* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv1f64:			; CHECK-LABEL: test_vlsseg4_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg4.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg4.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg4.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg4.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg5.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg5.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg5.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg5.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x double> @test_vlsseg5_nxv1f64(double* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x double> @test_vlsseg5_nxv1f64(double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv1f64:			; CHECK-LABEL: test_vlsseg5_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg5.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg5.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlsseg5_mask_nxv1f64(double* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlsseg5_mask_nxv1f64(double* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv1f64:			; CHECK-LABEL: test_vlsseg5_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg5.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg5.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg5.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg5.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg6.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg6.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg6.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg6.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x double> @test_vlsseg6_nxv1f64(double* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x double> @test_vlsseg6_nxv1f64(double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv1f64:			; CHECK-LABEL: test_vlsseg6_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg6.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg6.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlsseg6_mask_nxv1f64(double* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlsseg6_mask_nxv1f64(double* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv1f64:			; CHECK-LABEL: test_vlsseg6_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg6.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg6.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg6.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg6.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg7.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg7.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg7.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg7.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x double> @test_vlsseg7_nxv1f64(double* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x double> @test_vlsseg7_nxv1f64(double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv1f64:			; CHECK-LABEL: test_vlsseg7_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg7.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg7.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlsseg7_mask_nxv1f64(double* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlsseg7_mask_nxv1f64(double* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv1f64:			; CHECK-LABEL: test_vlsseg7_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg7.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg7.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg7.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg7.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg8.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg8.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)
	declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg8.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg8.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x double> @test_vlsseg8_nxv1f64(double* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x double> @test_vlsseg8_nxv1f64(double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv1f64:			; CHECK-LABEL: test_vlsseg8_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg8.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg8.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 1
	ret <vscale x 1 x double> %1			ret <vscale x 1 x double> %1
	}			}

	define <vscale x 1 x double> @test_vlsseg8_mask_nxv1f64(double* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x double> @test_vlsseg8_mask_nxv1f64(double* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv1f64:			; CHECK-LABEL: test_vlsseg8_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg8.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg8.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef ,<vscale x 1 x double> undef, <vscale x 1 x double> undef, <vscale x 1 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0			%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %0, 0
	%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg8.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} @llvm.riscv.vlsseg8.mask.nxv1f64(<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1,<vscale x 1 x double> %1, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1			%3 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>} %2, 1
	ret <vscale x 1 x double> %3			ret <vscale x 1 x double> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg2.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg2.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)
	declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg2.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg2.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x float> @test_vlsseg2_nxv2f32(float* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x float> @test_vlsseg2_nxv2f32(float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv2f32:			; CHECK-LABEL: test_vlsseg2_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg2.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg2.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlsseg2_mask_nxv2f32(float* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlsseg2_mask_nxv2f32(float* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv2f32:			; CHECK-LABEL: test_vlsseg2_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg2.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg2.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg2.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg2.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg3.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg3.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg3.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg3.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x float> @test_vlsseg3_nxv2f32(float* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x float> @test_vlsseg3_nxv2f32(float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv2f32:			; CHECK-LABEL: test_vlsseg3_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg3.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg3.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlsseg3_mask_nxv2f32(float* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlsseg3_mask_nxv2f32(float* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv2f32:			; CHECK-LABEL: test_vlsseg3_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg3.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg3.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg3.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg3.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg4.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg4.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg4.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg4.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x float> @test_vlsseg4_nxv2f32(float* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x float> @test_vlsseg4_nxv2f32(float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv2f32:			; CHECK-LABEL: test_vlsseg4_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg4.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg4.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlsseg4_mask_nxv2f32(float* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlsseg4_mask_nxv2f32(float* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv2f32:			; CHECK-LABEL: test_vlsseg4_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg4.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg4.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg4.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg4.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg5.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg5.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg5.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg5.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x float> @test_vlsseg5_nxv2f32(float* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x float> @test_vlsseg5_nxv2f32(float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv2f32:			; CHECK-LABEL: test_vlsseg5_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg5.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg5.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlsseg5_mask_nxv2f32(float* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlsseg5_mask_nxv2f32(float* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv2f32:			; CHECK-LABEL: test_vlsseg5_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg5.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg5.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg5.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg5.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg6.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg6.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg6.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg6.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x float> @test_vlsseg6_nxv2f32(float* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x float> @test_vlsseg6_nxv2f32(float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv2f32:			; CHECK-LABEL: test_vlsseg6_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg6.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg6.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlsseg6_mask_nxv2f32(float* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlsseg6_mask_nxv2f32(float* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv2f32:			; CHECK-LABEL: test_vlsseg6_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg6.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg6.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg6.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg6.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg7.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg7.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg7.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg7.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x float> @test_vlsseg7_nxv2f32(float* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x float> @test_vlsseg7_nxv2f32(float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv2f32:			; CHECK-LABEL: test_vlsseg7_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg7.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg7.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlsseg7_mask_nxv2f32(float* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlsseg7_mask_nxv2f32(float* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv2f32:			; CHECK-LABEL: test_vlsseg7_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg7.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg7.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg7.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg7.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg8.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg8.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)
	declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg8.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg8.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x float> @test_vlsseg8_nxv2f32(float* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x float> @test_vlsseg8_nxv2f32(float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv2f32:			; CHECK-LABEL: test_vlsseg8_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg8.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg8.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 1
	ret <vscale x 2 x float> %1			ret <vscale x 2 x float> %1
	}			}

	define <vscale x 2 x float> @test_vlsseg8_mask_nxv2f32(float* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x float> @test_vlsseg8_mask_nxv2f32(float* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv2f32:			; CHECK-LABEL: test_vlsseg8_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg8.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg8.nxv2f32(<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef ,<vscale x 2 x float> undef, <vscale x 2 x float> undef, <vscale x 2 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0			%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %0, 0
	%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg8.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} @llvm.riscv.vlsseg8.mask.nxv2f32(<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1,<vscale x 2 x float> %1, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1			%3 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>} %2, 1
	ret <vscale x 2 x float> %3			ret <vscale x 2 x float> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg2.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg2.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)
	declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg2.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg2.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x half> @test_vlsseg2_nxv1f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x half> @test_vlsseg2_nxv1f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv1f16:			; CHECK-LABEL: test_vlsseg2_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg2.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg2.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlsseg2_mask_nxv1f16(half* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlsseg2_mask_nxv1f16(half* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv1f16:			; CHECK-LABEL: test_vlsseg2_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg2.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg2.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg2.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg2.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg3.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg3.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg3.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg3.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x half> @test_vlsseg3_nxv1f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x half> @test_vlsseg3_nxv1f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv1f16:			; CHECK-LABEL: test_vlsseg3_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg3.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg3.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlsseg3_mask_nxv1f16(half* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlsseg3_mask_nxv1f16(half* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv1f16:			; CHECK-LABEL: test_vlsseg3_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg3.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg3.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg3.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg3.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg4.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg4.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg4.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg4.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x half> @test_vlsseg4_nxv1f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x half> @test_vlsseg4_nxv1f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv1f16:			; CHECK-LABEL: test_vlsseg4_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg4.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg4.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlsseg4_mask_nxv1f16(half* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlsseg4_mask_nxv1f16(half* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv1f16:			; CHECK-LABEL: test_vlsseg4_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg4.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg4.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg4.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg4.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg5.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg5.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg5.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg5.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x half> @test_vlsseg5_nxv1f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x half> @test_vlsseg5_nxv1f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv1f16:			; CHECK-LABEL: test_vlsseg5_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg5.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg5.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlsseg5_mask_nxv1f16(half* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlsseg5_mask_nxv1f16(half* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv1f16:			; CHECK-LABEL: test_vlsseg5_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg5.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg5.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg5.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg5.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg6.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg6.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg6.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg6.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x half> @test_vlsseg6_nxv1f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x half> @test_vlsseg6_nxv1f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv1f16:			; CHECK-LABEL: test_vlsseg6_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg6.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg6.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlsseg6_mask_nxv1f16(half* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlsseg6_mask_nxv1f16(half* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv1f16:			; CHECK-LABEL: test_vlsseg6_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg6.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg6.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg6.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg6.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg7.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg7.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg7.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg7.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x half> @test_vlsseg7_nxv1f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x half> @test_vlsseg7_nxv1f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv1f16:			; CHECK-LABEL: test_vlsseg7_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg7.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg7.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlsseg7_mask_nxv1f16(half* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlsseg7_mask_nxv1f16(half* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv1f16:			; CHECK-LABEL: test_vlsseg7_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg7.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg7.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg7.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg7.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg8.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg8.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)
	declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg8.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg8.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x half> @test_vlsseg8_nxv1f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x half> @test_vlsseg8_nxv1f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv1f16:			; CHECK-LABEL: test_vlsseg8_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg8.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg8.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 1
	ret <vscale x 1 x half> %1			ret <vscale x 1 x half> %1
	}			}

	define <vscale x 1 x half> @test_vlsseg8_mask_nxv1f16(half* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x half> @test_vlsseg8_mask_nxv1f16(half* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv1f16:			; CHECK-LABEL: test_vlsseg8_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg8.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg8.nxv1f16(<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef ,<vscale x 1 x half> undef, <vscale x 1 x half> undef, <vscale x 1 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0			%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %0, 0
	%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg8.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} @llvm.riscv.vlsseg8.mask.nxv1f16(<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1,<vscale x 1 x half> %1, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1			%3 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>} %2, 1
	ret <vscale x 1 x half> %3			ret <vscale x 1 x half> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg2.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg2.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)
	declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg2.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg2.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x float> @test_vlsseg2_nxv1f32(float* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x float> @test_vlsseg2_nxv1f32(float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv1f32:			; CHECK-LABEL: test_vlsseg2_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg2.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg2.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlsseg2_mask_nxv1f32(float* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlsseg2_mask_nxv1f32(float* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv1f32:			; CHECK-LABEL: test_vlsseg2_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg2.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg2.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg2.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg2.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg3.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg3.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg3.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg3.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x float> @test_vlsseg3_nxv1f32(float* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x float> @test_vlsseg3_nxv1f32(float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv1f32:			; CHECK-LABEL: test_vlsseg3_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg3.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg3.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlsseg3_mask_nxv1f32(float* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlsseg3_mask_nxv1f32(float* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv1f32:			; CHECK-LABEL: test_vlsseg3_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg3.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg3.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg3.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg3.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg4.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg4.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg4.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg4.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x float> @test_vlsseg4_nxv1f32(float* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x float> @test_vlsseg4_nxv1f32(float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv1f32:			; CHECK-LABEL: test_vlsseg4_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg4.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg4.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlsseg4_mask_nxv1f32(float* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlsseg4_mask_nxv1f32(float* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv1f32:			; CHECK-LABEL: test_vlsseg4_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg4.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg4.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg4.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg4.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg5.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg5.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg5.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg5.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x float> @test_vlsseg5_nxv1f32(float* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x float> @test_vlsseg5_nxv1f32(float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv1f32:			; CHECK-LABEL: test_vlsseg5_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg5.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg5.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlsseg5_mask_nxv1f32(float* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlsseg5_mask_nxv1f32(float* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv1f32:			; CHECK-LABEL: test_vlsseg5_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg5.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg5.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg5.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg5.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg6.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg6.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg6.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg6.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x float> @test_vlsseg6_nxv1f32(float* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x float> @test_vlsseg6_nxv1f32(float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv1f32:			; CHECK-LABEL: test_vlsseg6_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg6.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg6.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlsseg6_mask_nxv1f32(float* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlsseg6_mask_nxv1f32(float* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv1f32:			; CHECK-LABEL: test_vlsseg6_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg6.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg6.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg6.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg6.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg7.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg7.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg7.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg7.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x float> @test_vlsseg7_nxv1f32(float* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x float> @test_vlsseg7_nxv1f32(float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv1f32:			; CHECK-LABEL: test_vlsseg7_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg7.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg7.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlsseg7_mask_nxv1f32(float* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlsseg7_mask_nxv1f32(float* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv1f32:			; CHECK-LABEL: test_vlsseg7_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg7.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg7.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg7.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg7.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg8.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg8.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)
	declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg8.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64, i64)			declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg8.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64, i64)

	define <vscale x 1 x float> @test_vlsseg8_nxv1f32(float* %base, i64 %offset, i64 %vl) {			define <vscale x 1 x float> @test_vlsseg8_nxv1f32(float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv1f32:			; CHECK-LABEL: test_vlsseg8_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg8.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg8.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 1
	ret <vscale x 1 x float> %1			ret <vscale x 1 x float> %1
	}			}

	define <vscale x 1 x float> @test_vlsseg8_mask_nxv1f32(float* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {			define <vscale x 1 x float> @test_vlsseg8_mask_nxv1f32(float* %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv1f32:			; CHECK-LABEL: test_vlsseg8_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg8.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg8.nxv1f32(<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef ,<vscale x 1 x float> undef, <vscale x 1 x float> undef, <vscale x 1 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0			%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %0, 0
	%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg8.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} @llvm.riscv.vlsseg8.mask.nxv1f32(<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1,<vscale x 1 x float> %1, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1			%3 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>} %2, 1
	ret <vscale x 1 x float> %3			ret <vscale x 1 x float> %3
	}			}

	declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg2.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, i64)			declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg2.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, i64)
	declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg2.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg2.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x half> @test_vlsseg2_nxv8f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 8 x half> @test_vlsseg2_nxv8f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv8f16:			; CHECK-LABEL: test_vlsseg2_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg2.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg2.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	define <vscale x 8 x half> @test_vlsseg2_mask_nxv8f16(half* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x half> @test_vlsseg2_mask_nxv8f16(half* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv8f16:			; CHECK-LABEL: test_vlsseg2_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg2.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg2.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
	%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg2.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg2.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1			%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
	ret <vscale x 8 x half> %3			ret <vscale x 8 x half> %3
	}			}

	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg3.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, i64)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg3.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, i64)
	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg3.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg3.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x half> @test_vlsseg3_nxv8f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 8 x half> @test_vlsseg3_nxv8f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv8f16:			; CHECK-LABEL: test_vlsseg3_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg3.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg3.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	define <vscale x 8 x half> @test_vlsseg3_mask_nxv8f16(half* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x half> @test_vlsseg3_mask_nxv8f16(half* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv8f16:			; CHECK-LABEL: test_vlsseg3_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg3.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg3.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
	%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg3.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg3.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1			%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
	ret <vscale x 8 x half> %3			ret <vscale x 8 x half> %3
	}			}

	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg4.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, i64)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg4.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, i64)
	declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg4.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg4.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x half> @test_vlsseg4_nxv8f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 8 x half> @test_vlsseg4_nxv8f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv8f16:			; CHECK-LABEL: test_vlsseg4_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg4.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg4.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 1
	ret <vscale x 8 x half> %1			ret <vscale x 8 x half> %1
	}			}

	define <vscale x 8 x half> @test_vlsseg4_mask_nxv8f16(half* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x half> @test_vlsseg4_mask_nxv8f16(half* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv8f16:			; CHECK-LABEL: test_vlsseg4_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg4.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg4.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, <vscale x 8 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0			%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %0, 0
	%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg4.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} @llvm.riscv.vlsseg4.mask.nxv8f16(<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1,<vscale x 8 x half> %1, half* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1			%3 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>} %2, 1
	ret <vscale x 8 x half> %3			ret <vscale x 8 x half> %3
	}			}

	declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlsseg2.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, i64, i64)			declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlsseg2.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, i64, i64)
	declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlsseg2.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, i64, <vscale x 8 x i1>, i64, i64)			declare {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlsseg2.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, i64, <vscale x 8 x i1>, i64, i64)

	define <vscale x 8 x float> @test_vlsseg2_nxv8f32(float* %base, i64 %offset, i64 %vl) {			define <vscale x 8 x float> @test_vlsseg2_nxv8f32(float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv8f32:			; CHECK-LABEL: test_vlsseg2_nxv8f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlsseg2.nxv8f32(<vscale x 8 x float> undef, <vscale x 8 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlsseg2.nxv8f32(<vscale x 8 x float> undef, <vscale x 8 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1			%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 1
	ret <vscale x 8 x float> %1			ret <vscale x 8 x float> %1
	}			}

	define <vscale x 8 x float> @test_vlsseg2_mask_nxv8f32(float* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {			define <vscale x 8 x float> @test_vlsseg2_mask_nxv8f32(float* %base, i64 %offset, i64 %vl, <vscale x 8 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv8f32:			; CHECK-LABEL: test_vlsseg2_mask_nxv8f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlsseg2.nxv8f32(<vscale x 8 x float> undef, <vscale x 8 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlsseg2.nxv8f32(<vscale x 8 x float> undef, <vscale x 8 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0			%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %0, 0
	%2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlsseg2.mask.nxv8f32(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 8 x float>,<vscale x 8 x float>} @llvm.riscv.vlsseg2.mask.nxv8f32(<vscale x 8 x float> %1,<vscale x 8 x float> %1, float* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1			%3 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>} %2, 1
	ret <vscale x 8 x float> %3			ret <vscale x 8 x float> %3
	}			}

	declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg2.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, i64)			declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg2.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, i64)
	declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg2.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg2.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x double> @test_vlsseg2_nxv2f64(double* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x double> @test_vlsseg2_nxv2f64(double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv2f64:			; CHECK-LABEL: test_vlsseg2_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg2.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg2.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	define <vscale x 2 x double> @test_vlsseg2_mask_nxv2f64(double* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x double> @test_vlsseg2_mask_nxv2f64(double* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv2f64:			; CHECK-LABEL: test_vlsseg2_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg2.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg2.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
	%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg2.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg2.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1			%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
	ret <vscale x 2 x double> %3			ret <vscale x 2 x double> %3
	}			}

	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg3.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, i64)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg3.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, i64)
	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg3.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg3.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x double> @test_vlsseg3_nxv2f64(double* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x double> @test_vlsseg3_nxv2f64(double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv2f64:			; CHECK-LABEL: test_vlsseg3_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg3.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg3.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	define <vscale x 2 x double> @test_vlsseg3_mask_nxv2f64(double* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x double> @test_vlsseg3_mask_nxv2f64(double* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv2f64:			; CHECK-LABEL: test_vlsseg3_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg3.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg3.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
	%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg3.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg3.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1			%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
	ret <vscale x 2 x double> %3			ret <vscale x 2 x double> %3
	}			}

	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg4.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, i64)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg4.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, i64)
	declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg4.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg4.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x double> @test_vlsseg4_nxv2f64(double* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x double> @test_vlsseg4_nxv2f64(double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv2f64:			; CHECK-LABEL: test_vlsseg4_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg4.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg4.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 1
	ret <vscale x 2 x double> %1			ret <vscale x 2 x double> %1
	}			}

	define <vscale x 2 x double> @test_vlsseg4_mask_nxv2f64(double* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x double> @test_vlsseg4_mask_nxv2f64(double* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv2f64:			; CHECK-LABEL: test_vlsseg4_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg4.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg4.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, <vscale x 2 x double> undef, double* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0			%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %0, 0
	%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg4.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} @llvm.riscv.vlsseg4.mask.nxv2f64(<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1,<vscale x 2 x double> %1, double* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1			%3 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>} %2, 1
	ret <vscale x 2 x double> %3			ret <vscale x 2 x double> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg2.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg2.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)
	declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg2.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg2.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x half> @test_vlsseg2_nxv4f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x half> @test_vlsseg2_nxv4f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv4f16:			; CHECK-LABEL: test_vlsseg2_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg2.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg2.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlsseg2_mask_nxv4f16(half* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlsseg2_mask_nxv4f16(half* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv4f16:			; CHECK-LABEL: test_vlsseg2_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg2.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg2.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg2.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg2.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg3.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg3.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg3.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg3.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x half> @test_vlsseg3_nxv4f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x half> @test_vlsseg3_nxv4f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv4f16:			; CHECK-LABEL: test_vlsseg3_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg3.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg3.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlsseg3_mask_nxv4f16(half* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlsseg3_mask_nxv4f16(half* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv4f16:			; CHECK-LABEL: test_vlsseg3_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg3.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg3.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg3.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg3.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg4.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg4.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg4.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg4.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x half> @test_vlsseg4_nxv4f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x half> @test_vlsseg4_nxv4f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv4f16:			; CHECK-LABEL: test_vlsseg4_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg4.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg4.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlsseg4_mask_nxv4f16(half* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlsseg4_mask_nxv4f16(half* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv4f16:			; CHECK-LABEL: test_vlsseg4_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg4.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg4.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg4.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg4.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg5.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg5.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg5.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg5.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x half> @test_vlsseg5_nxv4f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x half> @test_vlsseg5_nxv4f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv4f16:			; CHECK-LABEL: test_vlsseg5_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg5.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg5.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlsseg5_mask_nxv4f16(half* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlsseg5_mask_nxv4f16(half* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv4f16:			; CHECK-LABEL: test_vlsseg5_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg5.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg5.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg5.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg5.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg6.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg6.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg6.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg6.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x half> @test_vlsseg6_nxv4f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x half> @test_vlsseg6_nxv4f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv4f16:			; CHECK-LABEL: test_vlsseg6_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg6.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg6.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlsseg6_mask_nxv4f16(half* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlsseg6_mask_nxv4f16(half* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv4f16:			; CHECK-LABEL: test_vlsseg6_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg6.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg6.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg6.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg6.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg7.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg7.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg7.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg7.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x half> @test_vlsseg7_nxv4f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x half> @test_vlsseg7_nxv4f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv4f16:			; CHECK-LABEL: test_vlsseg7_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg7.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg7.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlsseg7_mask_nxv4f16(half* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlsseg7_mask_nxv4f16(half* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv4f16:			; CHECK-LABEL: test_vlsseg7_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg7.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg7.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg7.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg7.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg8.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg8.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)
	declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg8.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg8.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x half> @test_vlsseg8_nxv4f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x half> @test_vlsseg8_nxv4f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv4f16:			; CHECK-LABEL: test_vlsseg8_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg8.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg8.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 1
	ret <vscale x 4 x half> %1			ret <vscale x 4 x half> %1
	}			}

	define <vscale x 4 x half> @test_vlsseg8_mask_nxv4f16(half* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x half> @test_vlsseg8_mask_nxv4f16(half* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv4f16:			; CHECK-LABEL: test_vlsseg8_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg8.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg8.nxv4f16(<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef ,<vscale x 4 x half> undef, <vscale x 4 x half> undef, <vscale x 4 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0			%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %0, 0
	%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg8.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} @llvm.riscv.vlsseg8.mask.nxv4f16(<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1,<vscale x 4 x half> %1, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1			%3 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>} %2, 1
	ret <vscale x 4 x half> %3			ret <vscale x 4 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg2.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg2.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)
	declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg2.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg2.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x half> @test_vlsseg2_nxv2f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x half> @test_vlsseg2_nxv2f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv2f16:			; CHECK-LABEL: test_vlsseg2_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg2.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg2.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlsseg2_mask_nxv2f16(half* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlsseg2_mask_nxv2f16(half* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv2f16:			; CHECK-LABEL: test_vlsseg2_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg2.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg2.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg2.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg2.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg3.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg3.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg3.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg3.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x half> @test_vlsseg3_nxv2f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x half> @test_vlsseg3_nxv2f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv2f16:			; CHECK-LABEL: test_vlsseg3_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg3.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg3.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlsseg3_mask_nxv2f16(half* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlsseg3_mask_nxv2f16(half* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv2f16:			; CHECK-LABEL: test_vlsseg3_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg3.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg3.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg3.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg3.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg4.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg4.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg4.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg4.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x half> @test_vlsseg4_nxv2f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x half> @test_vlsseg4_nxv2f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv2f16:			; CHECK-LABEL: test_vlsseg4_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg4.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg4.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlsseg4_mask_nxv2f16(half* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlsseg4_mask_nxv2f16(half* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv2f16:			; CHECK-LABEL: test_vlsseg4_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg4.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg4.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg4.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg4.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg5.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg5.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg5.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg5.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x half> @test_vlsseg5_nxv2f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x half> @test_vlsseg5_nxv2f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg5_nxv2f16:			; CHECK-LABEL: test_vlsseg5_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg5.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg5.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlsseg5_mask_nxv2f16(half* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlsseg5_mask_nxv2f16(half* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg5_mask_nxv2f16:			; CHECK-LABEL: test_vlsseg5_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg5.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg5.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg5.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg5.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg6.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg6.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg6.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg6.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x half> @test_vlsseg6_nxv2f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x half> @test_vlsseg6_nxv2f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg6_nxv2f16:			; CHECK-LABEL: test_vlsseg6_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg6.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg6.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlsseg6_mask_nxv2f16(half* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlsseg6_mask_nxv2f16(half* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg6_mask_nxv2f16:			; CHECK-LABEL: test_vlsseg6_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg6.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg6.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg6.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg6.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg7.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg7.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg7.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg7.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x half> @test_vlsseg7_nxv2f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x half> @test_vlsseg7_nxv2f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg7_nxv2f16:			; CHECK-LABEL: test_vlsseg7_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg7.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg7.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlsseg7_mask_nxv2f16(half* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlsseg7_mask_nxv2f16(half* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg7_mask_nxv2f16:			; CHECK-LABEL: test_vlsseg7_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg7.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg7.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg7.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg7.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg8.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg8.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)
	declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg8.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64, i64)			declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg8.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64, i64)

	define <vscale x 2 x half> @test_vlsseg8_nxv2f16(half* %base, i64 %offset, i64 %vl) {			define <vscale x 2 x half> @test_vlsseg8_nxv2f16(half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg8_nxv2f16:			; CHECK-LABEL: test_vlsseg8_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg8.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg8.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 1
	ret <vscale x 2 x half> %1			ret <vscale x 2 x half> %1
	}			}

	define <vscale x 2 x half> @test_vlsseg8_mask_nxv2f16(half* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {			define <vscale x 2 x half> @test_vlsseg8_mask_nxv2f16(half* %base, i64 %offset, i64 %vl, <vscale x 2 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg8_mask_nxv2f16:			; CHECK-LABEL: test_vlsseg8_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1
	; CHECK-NEXT: vmv1r.v v8, v7			; CHECK-NEXT: vmv1r.v v8, v7
	; CHECK-NEXT: vmv1r.v v9, v7			; CHECK-NEXT: vmv1r.v v9, v7
	; CHECK-NEXT: vmv1r.v v10, v7			; CHECK-NEXT: vmv1r.v v10, v7
	; CHECK-NEXT: vmv1r.v v11, v7			; CHECK-NEXT: vmv1r.v v11, v7
	; CHECK-NEXT: vmv1r.v v12, v7			; CHECK-NEXT: vmv1r.v v12, v7
	; CHECK-NEXT: vmv1r.v v13, v7			; CHECK-NEXT: vmv1r.v v13, v7
	; CHECK-NEXT: vmv1r.v v14, v7			; CHECK-NEXT: vmv1r.v v14, v7
	; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t			; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg8.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg8.nxv2f16(<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef ,<vscale x 2 x half> undef, <vscale x 2 x half> undef, <vscale x 2 x half> undef, half* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0			%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %0, 0
	%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg8.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} @llvm.riscv.vlsseg8.mask.nxv2f16(<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1,<vscale x 2 x half> %1, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1			%3 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>} %2, 1
	ret <vscale x 2 x half> %3			ret <vscale x 2 x half> %3
	}			}

	declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg2.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, i64)			declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg2.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, i64)
	declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg2.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg2.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x float> @test_vlsseg2_nxv4f32(float* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x float> @test_vlsseg2_nxv4f32(float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg2_nxv4f32:			; CHECK-LABEL: test_vlsseg2_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg2.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg2.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	define <vscale x 4 x float> @test_vlsseg2_mask_nxv4f32(float* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x float> @test_vlsseg2_mask_nxv4f32(float* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv4f32:			; CHECK-LABEL: test_vlsseg2_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg2.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg2.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
	%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg2.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg2.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1			%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
	ret <vscale x 4 x float> %3			ret <vscale x 4 x float> %3
	}			}

	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg3.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, i64)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg3.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, i64)
	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg3.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg3.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x float> @test_vlsseg3_nxv4f32(float* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x float> @test_vlsseg3_nxv4f32(float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg3_nxv4f32:			; CHECK-LABEL: test_vlsseg3_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg3.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg3.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	define <vscale x 4 x float> @test_vlsseg3_mask_nxv4f32(float* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x float> @test_vlsseg3_mask_nxv4f32(float* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg3_mask_nxv4f32:			; CHECK-LABEL: test_vlsseg3_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg3.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg3.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
	%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg3.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg3.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1			%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
	ret <vscale x 4 x float> %3			ret <vscale x 4 x float> %3
	}			}

	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg4.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, i64)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg4.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, i64)
	declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg4.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, <vscale x 4 x i1>, i64, i64)			declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg4.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, <vscale x 4 x i1>, i64, i64)

	define <vscale x 4 x float> @test_vlsseg4_nxv4f32(float* %base, i64 %offset, i64 %vl) {			define <vscale x 4 x float> @test_vlsseg4_nxv4f32(float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vlsseg4_nxv4f32:			; CHECK-LABEL: test_vlsseg4_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg4.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg4.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 1
	ret <vscale x 4 x float> %1			ret <vscale x 4 x float> %1
	}			}

	define <vscale x 4 x float> @test_vlsseg4_mask_nxv4f32(float* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {			define <vscale x 4 x float> @test_vlsseg4_mask_nxv4f32(float* %base, i64 %offset, i64 %vl, <vscale x 4 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg4_mask_nxv4f32:			; CHECK-LABEL: test_vlsseg4_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1			; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1
	; CHECK-NEXT: vmv2r.v v8, v6			; CHECK-NEXT: vmv2r.v v8, v6
	; CHECK-NEXT: vmv2r.v v10, v6			; CHECK-NEXT: vmv2r.v v10, v6
	; CHECK-NEXT: vmv2r.v v12, v6			; CHECK-NEXT: vmv2r.v v12, v6
	; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1, v0.t			; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg4.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %offset, i64 %vl)			%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg4.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, <vscale x 4 x float> undef, float* %base, i64 %offset, i64 %vl)
	%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0			%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %0, 0
	%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg4.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)			%2 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} @llvm.riscv.vlsseg4.mask.nxv4f32(<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1,<vscale x 4 x float> %1, float* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl, i64 1)
	%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1			%3 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>} %2, 1
	ret <vscale x 4 x float> %3			ret <vscale x 4 x float> %3
	}			}

llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll

This file has a very large number of changes (2,992 lines). Show File Contents

llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll

This file has a very large number of changes (4,238 lines). Show File Contents

llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

	Show First 20 Lines • Show All 263 Lines • ▼ Show 20 Lines
	; RV32-NEXT: slli a2, a2, 1			; RV32-NEXT: slli a2, a2, 1
	; RV32-NEXT: sub a4, a1, a2			; RV32-NEXT: sub a4, a1, a2
	; RV32-NEXT: vslidedown.vx v0, v0, a5			; RV32-NEXT: vslidedown.vx v0, v0, a5
	; RV32-NEXT: bltu a1, a4, .LBB12_2			; RV32-NEXT: bltu a1, a4, .LBB12_2
	; RV32-NEXT: # %bb.1:			; RV32-NEXT: # %bb.1:
	; RV32-NEXT: mv a3, a4			; RV32-NEXT: mv a3, a4
	; RV32-NEXT: .LBB12_2:			; RV32-NEXT: .LBB12_2:
	; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, mu			; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, mu
	; RV32-NEXT: vsext.vf4 v16, v10			; RV32-NEXT: vsext.vf4 v24, v10
	; RV32-NEXT: vsetvli zero, a3, e8, m2, ta, mu			; RV32-NEXT: vsetvli zero, a3, e8, m2, ta, mu
	; RV32-NEXT: vluxei32.v v10, (a0), v16, v0.t			; RV32-NEXT: vluxei32.v v18, (a0), v24, v0.t
	; RV32-NEXT: bltu a1, a2, .LBB12_4			; RV32-NEXT: bltu a1, a2, .LBB12_4
	; RV32-NEXT: # %bb.3:			; RV32-NEXT: # %bb.3:
	; RV32-NEXT: mv a1, a2			; RV32-NEXT: mv a1, a2
	; RV32-NEXT: .LBB12_4:			; RV32-NEXT: .LBB12_4:
	; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, mu			; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, mu
	; RV32-NEXT: vsext.vf4 v16, v8			; RV32-NEXT: vsext.vf4 v24, v8
	; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; RV32-NEXT: vmv1r.v v0, v12			; RV32-NEXT: vmv1r.v v0, v12
	; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t			; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
				; RV32-NEXT: vmv4r.v v8, v16
	; RV32-NEXT: ret			; RV32-NEXT: ret
	;			;
	; RV64-LABEL: vpgather_baseidx_nxv32i8:			; RV64-LABEL: vpgather_baseidx_nxv32i8:
	; RV64: # %bb.0:			; RV64: # %bb.0:
	; RV64-NEXT: csrr a3, vlenb			; RV64-NEXT: csrr a3, vlenb
	; RV64-NEXT: slli a5, a3, 1			; RV64-NEXT: slli a5, a3, 1
	; RV64-NEXT: sub a6, a1, a5			; RV64-NEXT: sub a6, a1, a5
	; RV64-NEXT: vmv1r.v v12, v0			; RV64-NEXT: vmv1r.v v12, v0
	Show All 11 Lines
	; RV64-NEXT: .LBB12_4:			; RV64-NEXT: .LBB12_4:
	; RV64-NEXT: srli a6, a3, 2			; RV64-NEXT: srli a6, a3, 2
	; RV64-NEXT: vsetvli t0, zero, e8, mf2, ta, mu			; RV64-NEXT: vsetvli t0, zero, e8, mf2, ta, mu
	; RV64-NEXT: vslidedown.vx v13, v12, a6			; RV64-NEXT: vslidedown.vx v13, v12, a6
	; RV64-NEXT: srli a6, a3, 3			; RV64-NEXT: srli a6, a3, 3
	; RV64-NEXT: vsetvli t0, zero, e8, mf4, ta, mu			; RV64-NEXT: vsetvli t0, zero, e8, mf4, ta, mu
	; RV64-NEXT: vslidedown.vx v0, v13, a6			; RV64-NEXT: vslidedown.vx v0, v13, a6
	; RV64-NEXT: vsetvli t0, zero, e64, m8, ta, mu			; RV64-NEXT: vsetvli t0, zero, e64, m8, ta, mu
	; RV64-NEXT: vsext.vf8 v16, v11			; RV64-NEXT: vsext.vf8 v24, v11
	; RV64-NEXT: vsetvli zero, a7, e8, m1, ta, mu			; RV64-NEXT: vsetvli zero, a7, e8, m1, ta, mu
	; RV64-NEXT: vluxei64.v v11, (a0), v16, v0.t			; RV64-NEXT: vluxei64.v v19, (a0), v24, v0.t
	; RV64-NEXT: bltu a1, a5, .LBB12_6			; RV64-NEXT: bltu a1, a5, .LBB12_6
	; RV64-NEXT: # %bb.5:			; RV64-NEXT: # %bb.5:
	; RV64-NEXT: mv a1, a5			; RV64-NEXT: mv a1, a5
	; RV64-NEXT: .LBB12_6:			; RV64-NEXT: .LBB12_6:
	; RV64-NEXT: sub a5, a1, a3			; RV64-NEXT: sub a5, a1, a3
	; RV64-NEXT: bltu a1, a5, .LBB12_8			; RV64-NEXT: bltu a1, a5, .LBB12_8
	; RV64-NEXT: # %bb.7:			; RV64-NEXT: # %bb.7:
	; RV64-NEXT: mv a4, a5			; RV64-NEXT: mv a4, a5
	; RV64-NEXT: .LBB12_8:			; RV64-NEXT: .LBB12_8:
	; RV64-NEXT: vsetvli a5, zero, e8, mf4, ta, mu			; RV64-NEXT: vsetvli a5, zero, e8, mf4, ta, mu
	; RV64-NEXT: vslidedown.vx v0, v12, a6			; RV64-NEXT: vslidedown.vx v0, v12, a6
	; RV64-NEXT: vsetvli a5, zero, e64, m8, ta, mu			; RV64-NEXT: vsetvli a5, zero, e64, m8, ta, mu
	; RV64-NEXT: vsext.vf8 v16, v9			; RV64-NEXT: vsext.vf8 v24, v9
	; RV64-NEXT: vsetvli zero, a4, e8, m1, ta, mu			; RV64-NEXT: vsetvli zero, a4, e8, m1, ta, mu
	; RV64-NEXT: vluxei64.v v9, (a0), v16, v0.t			; RV64-NEXT: vluxei64.v v17, (a0), v24, v0.t
	; RV64-NEXT: bltu a1, a3, .LBB12_10			; RV64-NEXT: bltu a1, a3, .LBB12_10
	; RV64-NEXT: # %bb.9:			; RV64-NEXT: # %bb.9:
	; RV64-NEXT: mv a1, a3			; RV64-NEXT: mv a1, a3
	; RV64-NEXT: .LBB12_10:			; RV64-NEXT: .LBB12_10:
	; RV64-NEXT: vsetvli a4, zero, e64, m8, ta, mu			; RV64-NEXT: vsetvli a4, zero, e64, m8, ta, mu
	; RV64-NEXT: vsext.vf8 v16, v8			; RV64-NEXT: vsext.vf8 v24, v8
	; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; RV64-NEXT: vmv1r.v v0, v12			; RV64-NEXT: vmv1r.v v0, v12
	; RV64-NEXT: vluxei64.v v8, (a0), v16, v0.t			; RV64-NEXT: vluxei64.v v16, (a0), v24, v0.t
	; RV64-NEXT: bltu a2, a3, .LBB12_12			; RV64-NEXT: bltu a2, a3, .LBB12_12
	; RV64-NEXT: # %bb.11:			; RV64-NEXT: # %bb.11:
	; RV64-NEXT: mv a2, a3			; RV64-NEXT: mv a2, a3
	; RV64-NEXT: .LBB12_12:			; RV64-NEXT: .LBB12_12:
	; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu			; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
	; RV64-NEXT: vsext.vf8 v16, v10			; RV64-NEXT: vsext.vf8 v24, v10
	; RV64-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; RV64-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; RV64-NEXT: vmv1r.v v0, v13			; RV64-NEXT: vmv1r.v v0, v13
	; RV64-NEXT: vluxei64.v v10, (a0), v16, v0.t			; RV64-NEXT: vluxei64.v v18, (a0), v24, v0.t
				; RV64-NEXT: vmv4r.v v8, v16
	; RV64-NEXT: ret			; RV64-NEXT: ret
	%ptrs = getelementptr inbounds i8, i8* %base, <vscale x 32 x i8> %idxs			%ptrs = getelementptr inbounds i8, i8* %base, <vscale x 32 x i8> %idxs
	%v = call <vscale x 32 x i8> @llvm.vp.gather.nxv32i8.nxv32p0i8(<vscale x 32 x i8*> %ptrs, <vscale x 32 x i1> %m, i32 %evl)			%v = call <vscale x 32 x i8> @llvm.vp.gather.nxv32i8.nxv32p0i8(<vscale x 32 x i8*> %ptrs, <vscale x 32 x i1> %m, i32 %evl)
	ret <vscale x 32 x i8> %v			ret <vscale x 32 x i8> %v
	}			}

	declare <vscale x 1 x i16> @llvm.vp.gather.nxv1i16.nxv1p0i16(<vscale x 1 x i16*>, <vscale x 1 x i1>, i32)			declare <vscale x 1 x i16> @llvm.vp.gather.nxv1i16.nxv1p0i16(<vscale x 1 x i16*>, <vscale x 1 x i1>, i32)

	▲ Show 20 Lines • Show All 2,236 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \| FileCheck %s			; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \| FileCheck %s --check-prefix NOSUBREG
	; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s -riscv-enable-subreg-liveness=false \| FileCheck %s --check-prefix NOSUBREG			; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s -riscv-enable-subreg-liveness=true \| FileCheck %s --check-prefix SUBREG

	; This test checks that vrgatherei16 instructions are correctly			; This test checks that vrgatherei16 instructions are correctly
	; register-allocated. The LMUL=1 destination register groups may not overlap			; register-allocated. The LMUL=1 destination register groups may not overlap
	; with the EMUL=2 source vector register groups.			; with the EMUL=2 source vector register groups.

	; FIXME: enabling subregister liveness results in incorrect register			; FIXME: enabling subregister liveness results in incorrect register
	; allocation!			; allocation!

	define internal void @foo(<vscale x 1 x i16> %v15, <vscale x 1 x i16> %0, <vscale x 1 x i16> %vs12.i.i.i, <vscale x 1 x i16> %1, <vscale x 8 x i8> %v37) {			define internal void @foo(<vscale x 1 x i16> %v15, <vscale x 1 x i16> %0, <vscale x 1 x i16> %vs12.i.i.i, <vscale x 1 x i16> %1, <vscale x 8 x i8> %v37) {
	; CHECK-LABEL: foo:
	; CHECK: # %bb.0: # %loopIR.preheader.i.i
	; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
	; CHECK-NEXT: vmv.v.i v14, 0
	; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
	; CHECK-NEXT: vmv.v.i v9, 0
	; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, mu
	; CHECK-NEXT: vmv1r.v v8, v9
	; CHECK-NEXT: vrgatherei16.vv v8, v9, v14
	; CHECK-NEXT: .LBB0_1: # %loopIR3.i.i
	; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
	; CHECK-NEXT: vl1r.v v9, (zero)
	; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, mu
	; CHECK-NEXT: vmv1r.v v11, v12
	; CHECK-NEXT: vrgatherei16.vv v11, v9, v10
	; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
	; CHECK-NEXT: vand.vv v9, v8, v11
	; CHECK-NEXT: vs1r.v v9, (zero)
	; CHECK-NEXT: j .LBB0_1
	;
	; NOSUBREG-LABEL: foo:			; NOSUBREG-LABEL: foo:
	; NOSUBREG: # %bb.0: # %loopIR.preheader.i.i			; NOSUBREG: # %bb.0: # %loopIR.preheader.i.i
	; NOSUBREG-NEXT: # kill: def $v10 killed $v10 def $v10m2			; NOSUBREG-NEXT: # kill: def $v10 killed $v10 def $v10m2
	; NOSUBREG-NEXT: vsetvli a0, zero, e16, m2, ta, mu			; NOSUBREG-NEXT: vsetvli a0, zero, e16, m2, ta, mu
	; NOSUBREG-NEXT: vmv.v.i v14, 0			; NOSUBREG-NEXT: vmv.v.i v14, 0
	; NOSUBREG-NEXT: vsetvli zero, zero, e8, m1, ta, mu			; NOSUBREG-NEXT: vsetvli zero, zero, e8, m1, ta, mu
	; NOSUBREG-NEXT: vmv.v.i v9, 0			; NOSUBREG-NEXT: vmv.v.i v9, 0
	; NOSUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, mu			; NOSUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, mu
	; NOSUBREG-NEXT: vmv1r.v v8, v9			; NOSUBREG-NEXT: vmv1r.v v8, v9
	; NOSUBREG-NEXT: vrgatherei16.vv v8, v9, v14			; NOSUBREG-NEXT: vrgatherei16.vv v8, v9, v14
	; NOSUBREG-NEXT: .LBB0_1: # %loopIR3.i.i			; NOSUBREG-NEXT: .LBB0_1: # %loopIR3.i.i
	; NOSUBREG-NEXT: # =>This Inner Loop Header: Depth=1			; NOSUBREG-NEXT: # =>This Inner Loop Header: Depth=1
	; NOSUBREG-NEXT: vl1r.v v9, (zero)			; NOSUBREG-NEXT: vl1r.v v9, (zero)
	; NOSUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, mu			; NOSUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, mu
	; NOSUBREG-NEXT: vmv1r.v v13, v12			; NOSUBREG-NEXT: vmv1r.v v13, v12
	; NOSUBREG-NEXT: vrgatherei16.vv v13, v9, v10			; NOSUBREG-NEXT: vrgatherei16.vv v13, v9, v10
	; NOSUBREG-NEXT: vsetvli a0, zero, e8, m1, ta, mu			; NOSUBREG-NEXT: vsetvli a0, zero, e8, m1, ta, mu
	; NOSUBREG-NEXT: vand.vv v9, v8, v13			; NOSUBREG-NEXT: vand.vv v9, v8, v13
	; NOSUBREG-NEXT: vs1r.v v9, (zero)			; NOSUBREG-NEXT: vs1r.v v9, (zero)
	; NOSUBREG-NEXT: j .LBB0_1			; NOSUBREG-NEXT: j .LBB0_1
				;
				; SUBREG-LABEL: foo:
				; SUBREG: # %bb.0: # %loopIR.preheader.i.i
				; SUBREG-NEXT: vsetvli a0, zero, e16, m2, ta, mu
				; SUBREG-NEXT: vmv.v.i v14, 0
				; SUBREG-NEXT: vsetvli zero, zero, e8, m1, ta, mu
				; SUBREG-NEXT: vmv.v.i v9, 0
				; SUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, mu
				; SUBREG-NEXT: vmv1r.v v8, v9
				; SUBREG-NEXT: vrgatherei16.vv v8, v9, v14
				; SUBREG-NEXT: .LBB0_1: # %loopIR3.i.i
				; SUBREG-NEXT: # =>This Inner Loop Header: Depth=1
				; SUBREG-NEXT: vl1r.v v9, (zero)
				; SUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, mu
				; SUBREG-NEXT: vmv1r.v v11, v12
				; SUBREG-NEXT: vrgatherei16.vv v11, v9, v10
				; SUBREG-NEXT: vsetvli a0, zero, e8, m1, ta, mu
				; SUBREG-NEXT: vand.vv v9, v8, v11
				; SUBREG-NEXT: vs1r.v v9, (zero)
				; SUBREG-NEXT: j .LBB0_1
	loopIR.preheader.i.i:			loopIR.preheader.i.i:
	%v18 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i, i64 0)			%v18 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i, i64 0)
	br label %loopIR3.i.i			br label %loopIR3.i.i

	loopIR3.i.i: ; preds = %loopIR3.i.i, %loopIR.preheader.i.i			loopIR3.i.i: ; preds = %loopIR3.i.i, %loopIR.preheader.i.i
	%v376 = load <vscale x 8 x i8>, ptr addrspace(1) null, align 8			%v376 = load <vscale x 8 x i8>, ptr addrspace(1) null, align 8
	%v38 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> zeroinitializer, <vscale x 8 x i8> zeroinitializer, <vscale x 8 x i16> zeroinitializer, i64 4)			%v38 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> zeroinitializer, <vscale x 8 x i8> zeroinitializer, <vscale x 8 x i16> zeroinitializer, i64 4)
	%v40 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> %v37, <vscale x 8 x i8> %v376, <vscale x 8 x i16> %v18, i64 4)			%v40 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> %v37, <vscale x 8 x i8> %v376, <vscale x 8 x i16> %v18, i64 4)
	Show All 13 Lines

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

	Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
	define <vscale x 1 x double> @test3(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {			define <vscale x 1 x double> @test3(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
	; CHECK-LABEL: test3:			; CHECK-LABEL: test3:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: beqz a1, .LBB2_2			; CHECK-NEXT: beqz a1, .LBB2_2
	; CHECK-NEXT: # %bb.1: # %if.then			; CHECK-NEXT: # %bb.1: # %if.then
	; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, mu			; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, mu
	; CHECK-NEXT: vfadd.vv v9, v8, v9			; CHECK-NEXT: vfadd.vv v9, v8, v9
	; CHECK-NEXT: vfmul.vv v8, v9, v8			; CHECK-NEXT: vfmul.vv v8, v9, v8
	; CHECK-NEXT: # implicit-def: $x10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	; CHECK-NEXT: .LBB2_2: # %if.else			; CHECK-NEXT: .LBB2_2: # %if.else
	; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, mu			; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, mu
	; CHECK-NEXT: vfsub.vv v9, v8, v9			; CHECK-NEXT: vfsub.vv v9, v8, v9
	; CHECK-NEXT: vfmul.vv v8, v9, v8			; CHECK-NEXT: vfmul.vv v8, v9, v8
	; CHECK-NEXT: # implicit-def: $x10
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%tobool = icmp eq i8 %cond, 0			%tobool = icmp eq i8 %cond, 0
	br i1 %tobool, label %if.else, label %if.then			br i1 %tobool, label %if.else, label %if.then

	if.then: ; preds = %entry			if.then: ; preds = %entry
	%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)			%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
	%1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0)			%1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> undef, <vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0)
	▲ Show 20 Lines • Show All 859 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll

This file has a very large number of changes (5,412 lines). Show File Contents

llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll

This file has a very large number of changes (7,622 lines). Show File Contents

llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \			; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \
	; RUN: -verify-machineinstrs < %s \| FileCheck %s			; RUN: -verify-machineinstrs < %s \| FileCheck %s

	declare void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i32)

	define void @test_vsseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv16i16:			; CHECK-LABEL: test_vsseg2_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0)			; CHECK-NEXT: vsseg2e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv16i16:			; CHECK-LABEL: test_vsseg2_mask_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg2.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)

	define void @test_vsseg2_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg2_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv1i8:			; CHECK-LABEL: test_vsseg2_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0)			; CHECK-NEXT: vsseg2e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv1i8:			; CHECK-LABEL: test_vsseg2_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg3.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg3.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg3.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)

	define void @test_vsseg3_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg3_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv1i8:			; CHECK-LABEL: test_vsseg3_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg3e8.v v8, (a0)			; CHECK-NEXT: vsseg3e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg3.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg3_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv1i8:			; CHECK-LABEL: test_vsseg3_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg4.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg4.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg4.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)

	define void @test_vsseg4_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg4_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv1i8:			; CHECK-LABEL: test_vsseg4_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg4e8.v v8, (a0)			; CHECK-NEXT: vsseg4e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg4.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg4_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv1i8:			; CHECK-LABEL: test_vsseg4_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg5.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg5.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg5.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)

	define void @test_vsseg5_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg5_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv1i8:			; CHECK-LABEL: test_vsseg5_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg5e8.v v8, (a0)			; CHECK-NEXT: vsseg5e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg5.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg5_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv1i8:			; CHECK-LABEL: test_vsseg5_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg6.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg6.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg6.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)

	define void @test_vsseg6_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg6_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv1i8:			; CHECK-LABEL: test_vsseg6_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg6e8.v v8, (a0)			; CHECK-NEXT: vsseg6e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg6.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg6_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv1i8:			; CHECK-LABEL: test_vsseg6_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg7.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg7.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg7.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)

	define void @test_vsseg7_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg7_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv1i8:			; CHECK-LABEL: test_vsseg7_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg7e8.v v8, (a0)			; CHECK-NEXT: vsseg7e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg7.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg7_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv1i8:			; CHECK-LABEL: test_vsseg7_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg8.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg8.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)

	define void @test_vsseg8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv1i8:			; CHECK-LABEL: test_vsseg8_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg8e8.v v8, (a0)			; CHECK-NEXT: vsseg8e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg8_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv1i8:			; CHECK-LABEL: test_vsseg8_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg2.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32)

	define void @test_vsseg2_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg2_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv16i8:			; CHECK-LABEL: test_vsseg2_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0)			; CHECK-NEXT: vsseg2e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv16i8:			; CHECK-LABEL: test_vsseg2_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg3.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg3.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32)			declare void @llvm.riscv.vsseg3.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32)

	define void @test_vsseg3_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg3_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv16i8:			; CHECK-LABEL: test_vsseg3_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vsseg3e8.v v8, (a0)			; CHECK-NEXT: vsseg3e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg3.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl) {			define void @test_vsseg3_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv16i8:			; CHECK-LABEL: test_vsseg3_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg4.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg4.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32)			declare void @llvm.riscv.vsseg4.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32)

	define void @test_vsseg4_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg4_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv16i8:			; CHECK-LABEL: test_vsseg4_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vsseg4e8.v v8, (a0)			; CHECK-NEXT: vsseg4e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg4.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl) {			define void @test_vsseg4_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv16i8:			; CHECK-LABEL: test_vsseg4_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)			declare void @llvm.riscv.vsseg2.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)

	define void @test_vsseg2_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl) {			define void @test_vsseg2_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv2i32:			; CHECK-LABEL: test_vsseg2_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0)			; CHECK-NEXT: vsseg2e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv2i32:			; CHECK-LABEL: test_vsseg2_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)			declare void @llvm.riscv.vsseg3.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
	declare void @llvm.riscv.vsseg3.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg3.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)

	define void @test_vsseg3_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl) {			define void @test_vsseg3_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv2i32:			; CHECK-LABEL: test_vsseg3_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0)			; CHECK-NEXT: vsseg3e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %vl)			tail call void @llvm.riscv.vsseg3.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg3_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv2i32:			; CHECK-LABEL: test_vsseg3_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)			declare void @llvm.riscv.vsseg4.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
	declare void @llvm.riscv.vsseg4.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg4.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)

	define void @test_vsseg4_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl) {			define void @test_vsseg4_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv2i32:			; CHECK-LABEL: test_vsseg4_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0)			; CHECK-NEXT: vsseg4e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %vl)			tail call void @llvm.riscv.vsseg4.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg4_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv2i32:			; CHECK-LABEL: test_vsseg4_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)			declare void @llvm.riscv.vsseg5.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
	declare void @llvm.riscv.vsseg5.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg5.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)

	define void @test_vsseg5_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl) {			define void @test_vsseg5_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv2i32:			; CHECK-LABEL: test_vsseg5_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg5e32.v v8, (a0)			; CHECK-NEXT: vsseg5e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %vl)			tail call void @llvm.riscv.vsseg5.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg5_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv2i32:			; CHECK-LABEL: test_vsseg5_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)			declare void @llvm.riscv.vsseg6.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
	declare void @llvm.riscv.vsseg6.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg6.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)

	define void @test_vsseg6_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl) {			define void @test_vsseg6_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv2i32:			; CHECK-LABEL: test_vsseg6_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg6e32.v v8, (a0)			; CHECK-NEXT: vsseg6e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %vl)			tail call void @llvm.riscv.vsseg6.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg6_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv2i32:			; CHECK-LABEL: test_vsseg6_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)			declare void @llvm.riscv.vsseg7.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
	declare void @llvm.riscv.vsseg7.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg7.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)

	define void @test_vsseg7_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl) {			define void @test_vsseg7_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv2i32:			; CHECK-LABEL: test_vsseg7_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg7e32.v v8, (a0)			; CHECK-NEXT: vsseg7e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %vl)			tail call void @llvm.riscv.vsseg7.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg7_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv2i32:			; CHECK-LABEL: test_vsseg7_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)			declare void @llvm.riscv.vsseg8.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i32)
	declare void @llvm.riscv.vsseg8.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg8.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)

	define void @test_vsseg8_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl) {			define void @test_vsseg8_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv2i32:			; CHECK-LABEL: test_vsseg8_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg8e32.v v8, (a0)			; CHECK-NEXT: vsseg8e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %vl)			tail call void @llvm.riscv.vsseg8.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg8_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv2i32:			; CHECK-LABEL: test_vsseg8_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg2.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)

	define void @test_vsseg2_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg2_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv4i16:			; CHECK-LABEL: test_vsseg2_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0)			; CHECK-NEXT: vsseg2e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv4i16:			; CHECK-LABEL: test_vsseg2_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg3.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg3.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg3.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)

	define void @test_vsseg3_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg3_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv4i16:			; CHECK-LABEL: test_vsseg3_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0)			; CHECK-NEXT: vsseg3e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg3.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg3_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv4i16:			; CHECK-LABEL: test_vsseg3_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg4.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg4.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg4.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)

	define void @test_vsseg4_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg4_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv4i16:			; CHECK-LABEL: test_vsseg4_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0)			; CHECK-NEXT: vsseg4e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg4.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg4_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv4i16:			; CHECK-LABEL: test_vsseg4_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg5.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg5.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg5.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)

	define void @test_vsseg5_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg5_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv4i16:			; CHECK-LABEL: test_vsseg5_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0)			; CHECK-NEXT: vsseg5e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg5.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg5_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv4i16:			; CHECK-LABEL: test_vsseg5_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg6.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg6.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg6.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)

	define void @test_vsseg6_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg6_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv4i16:			; CHECK-LABEL: test_vsseg6_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0)			; CHECK-NEXT: vsseg6e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg6.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg6_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv4i16:			; CHECK-LABEL: test_vsseg6_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg7.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg7.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg7.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)

	define void @test_vsseg7_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg7_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv4i16:			; CHECK-LABEL: test_vsseg7_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0)			; CHECK-NEXT: vsseg7e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg7.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg7_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv4i16:			; CHECK-LABEL: test_vsseg7_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg8.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg8.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg8.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)

	define void @test_vsseg8_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg8_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv4i16:			; CHECK-LABEL: test_vsseg8_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0)			; CHECK-NEXT: vsseg8e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg8.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg8_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv4i16:			; CHECK-LABEL: test_vsseg8_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)			declare void @llvm.riscv.vsseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)

	define void @test_vsseg2_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl) {			define void @test_vsseg2_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv1i32:			; CHECK-LABEL: test_vsseg2_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0)			; CHECK-NEXT: vsseg2e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv1i32:			; CHECK-LABEL: test_vsseg2_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)			declare void @llvm.riscv.vsseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
	declare void @llvm.riscv.vsseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)

	define void @test_vsseg3_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl) {			define void @test_vsseg3_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv1i32:			; CHECK-LABEL: test_vsseg3_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0)			; CHECK-NEXT: vsseg3e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %vl)			tail call void @llvm.riscv.vsseg3.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg3_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv1i32:			; CHECK-LABEL: test_vsseg3_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)			declare void @llvm.riscv.vsseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
	declare void @llvm.riscv.vsseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)

	define void @test_vsseg4_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl) {			define void @test_vsseg4_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv1i32:			; CHECK-LABEL: test_vsseg4_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0)			; CHECK-NEXT: vsseg4e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %vl)			tail call void @llvm.riscv.vsseg4.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg4_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv1i32:			; CHECK-LABEL: test_vsseg4_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)			declare void @llvm.riscv.vsseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
	declare void @llvm.riscv.vsseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)

	define void @test_vsseg5_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl) {			define void @test_vsseg5_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv1i32:			; CHECK-LABEL: test_vsseg5_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg5e32.v v8, (a0)			; CHECK-NEXT: vsseg5e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %vl)			tail call void @llvm.riscv.vsseg5.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg5_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv1i32:			; CHECK-LABEL: test_vsseg5_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)			declare void @llvm.riscv.vsseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
	declare void @llvm.riscv.vsseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)

	define void @test_vsseg6_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl) {			define void @test_vsseg6_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv1i32:			; CHECK-LABEL: test_vsseg6_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg6e32.v v8, (a0)			; CHECK-NEXT: vsseg6e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %vl)			tail call void @llvm.riscv.vsseg6.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg6_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv1i32:			; CHECK-LABEL: test_vsseg6_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)			declare void @llvm.riscv.vsseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
	declare void @llvm.riscv.vsseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)

	define void @test_vsseg7_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl) {			define void @test_vsseg7_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv1i32:			; CHECK-LABEL: test_vsseg7_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg7e32.v v8, (a0)			; CHECK-NEXT: vsseg7e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %vl)			tail call void @llvm.riscv.vsseg7.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg7_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv1i32:			; CHECK-LABEL: test_vsseg7_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)			declare void @llvm.riscv.vsseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i32)
	declare void @llvm.riscv.vsseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)

	define void @test_vsseg8_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl) {			define void @test_vsseg8_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv1i32:			; CHECK-LABEL: test_vsseg8_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg8e32.v v8, (a0)			; CHECK-NEXT: vsseg8e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %vl)			tail call void @llvm.riscv.vsseg8.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg8_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv1i32:			; CHECK-LABEL: test_vsseg8_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg2.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32)

	define void @test_vsseg2_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg2_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv8i16:			; CHECK-LABEL: test_vsseg2_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0)			; CHECK-NEXT: vsseg2e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv8i16:			; CHECK-LABEL: test_vsseg2_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg3.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg3.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vsseg3.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32)

	define void @test_vsseg3_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg3_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv8i16:			; CHECK-LABEL: test_vsseg3_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0)			; CHECK-NEXT: vsseg3e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg3.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vsseg3_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv8i16:			; CHECK-LABEL: test_vsseg3_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg4.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg4.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vsseg4.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32)

	define void @test_vsseg4_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg4_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv8i16:			; CHECK-LABEL: test_vsseg4_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0)			; CHECK-NEXT: vsseg4e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg4.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vsseg4_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv8i16:			; CHECK-LABEL: test_vsseg4_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg2.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)

	define void @test_vsseg2_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg2_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv8i8:			; CHECK-LABEL: test_vsseg2_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0)			; CHECK-NEXT: vsseg2e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv8i8:			; CHECK-LABEL: test_vsseg2_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg3.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg3.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vsseg3.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)

	define void @test_vsseg3_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg3_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv8i8:			; CHECK-LABEL: test_vsseg3_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg3e8.v v8, (a0)			; CHECK-NEXT: vsseg3e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg3.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vsseg3_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv8i8:			; CHECK-LABEL: test_vsseg3_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg4.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg4.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vsseg4.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)

	define void @test_vsseg4_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg4_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv8i8:			; CHECK-LABEL: test_vsseg4_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg4e8.v v8, (a0)			; CHECK-NEXT: vsseg4e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg4.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vsseg4_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv8i8:			; CHECK-LABEL: test_vsseg4_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg5.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg5.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vsseg5.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)

	define void @test_vsseg5_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg5_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv8i8:			; CHECK-LABEL: test_vsseg5_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg5e8.v v8, (a0)			; CHECK-NEXT: vsseg5e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg5.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vsseg5_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv8i8:			; CHECK-LABEL: test_vsseg5_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg6.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg6.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vsseg6.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)

	define void @test_vsseg6_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg6_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv8i8:			; CHECK-LABEL: test_vsseg6_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg6e8.v v8, (a0)			; CHECK-NEXT: vsseg6e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg6.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vsseg6_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv8i8:			; CHECK-LABEL: test_vsseg6_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg7.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg7.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vsseg7.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)

	define void @test_vsseg7_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg7_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv8i8:			; CHECK-LABEL: test_vsseg7_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg7e8.v v8, (a0)			; CHECK-NEXT: vsseg7e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg7.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vsseg7_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv8i8:			; CHECK-LABEL: test_vsseg7_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg8.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vsseg8.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)

	define void @test_vsseg8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv8i8:			; CHECK-LABEL: test_vsseg8_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg8e8.v v8, (a0)			; CHECK-NEXT: vsseg8e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vsseg8_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv8i8:			; CHECK-LABEL: test_vsseg8_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32* , i32)			declare void @llvm.riscv.vsseg2.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i1>, i32)

	define void @test_vsseg2_nxv8i32(<vscale x 8 x i32> %val, i32* %base, i32 %vl) {			define void @test_vsseg2_nxv8i32(<vscale x 8 x i32> %val, i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv8i32:			; CHECK-LABEL: test_vsseg2_nxv8i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0)			; CHECK-NEXT: vsseg2e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv8i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv8i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv8i32:			; CHECK-LABEL: test_vsseg2_mask_nxv8i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg2.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)

	define void @test_vsseg2_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg2_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv4i8:			; CHECK-LABEL: test_vsseg2_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0)			; CHECK-NEXT: vsseg2e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv4i8:			; CHECK-LABEL: test_vsseg2_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg3.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg3.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg3.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)

	define void @test_vsseg3_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg3_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv4i8:			; CHECK-LABEL: test_vsseg3_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg3e8.v v8, (a0)			; CHECK-NEXT: vsseg3e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg3.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg3_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv4i8:			; CHECK-LABEL: test_vsseg3_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg4.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg4.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg4.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)

	define void @test_vsseg4_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg4_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv4i8:			; CHECK-LABEL: test_vsseg4_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg4e8.v v8, (a0)			; CHECK-NEXT: vsseg4e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg4.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg4_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv4i8:			; CHECK-LABEL: test_vsseg4_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg5.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg5.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg5.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)

	define void @test_vsseg5_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg5_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv4i8:			; CHECK-LABEL: test_vsseg5_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg5e8.v v8, (a0)			; CHECK-NEXT: vsseg5e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg5.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg5_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv4i8:			; CHECK-LABEL: test_vsseg5_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg6.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg6.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg6.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)

	define void @test_vsseg6_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg6_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv4i8:			; CHECK-LABEL: test_vsseg6_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg6e8.v v8, (a0)			; CHECK-NEXT: vsseg6e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg6.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg6_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv4i8:			; CHECK-LABEL: test_vsseg6_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg7.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg7.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg7.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)

	define void @test_vsseg7_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg7_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv4i8:			; CHECK-LABEL: test_vsseg7_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg7e8.v v8, (a0)			; CHECK-NEXT: vsseg7e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg7.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg7_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv4i8:			; CHECK-LABEL: test_vsseg7_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg8.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg8.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)

	define void @test_vsseg8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv4i8:			; CHECK-LABEL: test_vsseg8_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg8e8.v v8, (a0)			; CHECK-NEXT: vsseg8e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg8_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv4i8:			; CHECK-LABEL: test_vsseg8_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg2.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)

	define void @test_vsseg2_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg2_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv1i16:			; CHECK-LABEL: test_vsseg2_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0)			; CHECK-NEXT: vsseg2e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv1i16:			; CHECK-LABEL: test_vsseg2_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg3.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg3.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg3.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)

	define void @test_vsseg3_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg3_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv1i16:			; CHECK-LABEL: test_vsseg3_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0)			; CHECK-NEXT: vsseg3e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg3.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg3_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv1i16:			; CHECK-LABEL: test_vsseg3_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg4.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg4.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg4.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)

	define void @test_vsseg4_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg4_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv1i16:			; CHECK-LABEL: test_vsseg4_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0)			; CHECK-NEXT: vsseg4e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg4.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg4_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv1i16:			; CHECK-LABEL: test_vsseg4_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg5.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg5.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg5.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)

	define void @test_vsseg5_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg5_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv1i16:			; CHECK-LABEL: test_vsseg5_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0)			; CHECK-NEXT: vsseg5e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg5.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg5_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv1i16:			; CHECK-LABEL: test_vsseg5_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg6.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg6.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg6.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)

	define void @test_vsseg6_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg6_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv1i16:			; CHECK-LABEL: test_vsseg6_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0)			; CHECK-NEXT: vsseg6e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg6.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg6_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv1i16:			; CHECK-LABEL: test_vsseg6_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg7.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg7.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg7.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)

	define void @test_vsseg7_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg7_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv1i16:			; CHECK-LABEL: test_vsseg7_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0)			; CHECK-NEXT: vsseg7e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg7.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg7_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv1i16:			; CHECK-LABEL: test_vsseg7_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg8.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg8.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg8.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)

	define void @test_vsseg8_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg8_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv1i16:			; CHECK-LABEL: test_vsseg8_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0)			; CHECK-NEXT: vsseg8e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg8.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg8_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv1i16:			; CHECK-LABEL: test_vsseg8_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg2.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i1>, i32)

	define void @test_vsseg2_nxv32i8(<vscale x 32 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg2_nxv32i8(<vscale x 32 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv32i8:			; CHECK-LABEL: test_vsseg2_nxv32i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0)			; CHECK-NEXT: vsseg2e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv32i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv32i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv32i8:			; CHECK-LABEL: test_vsseg2_mask_nxv32i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg2.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)

	define void @test_vsseg2_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg2_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv2i8:			; CHECK-LABEL: test_vsseg2_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0)			; CHECK-NEXT: vsseg2e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv2i8:			; CHECK-LABEL: test_vsseg2_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg3.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg3.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg3.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)

	define void @test_vsseg3_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg3_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv2i8:			; CHECK-LABEL: test_vsseg3_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg3e8.v v8, (a0)			; CHECK-NEXT: vsseg3e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg3.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg3_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv2i8:			; CHECK-LABEL: test_vsseg3_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg4.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg4.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg4.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)

	define void @test_vsseg4_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg4_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv2i8:			; CHECK-LABEL: test_vsseg4_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg4e8.v v8, (a0)			; CHECK-NEXT: vsseg4e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg4.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg4_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv2i8:			; CHECK-LABEL: test_vsseg4_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg5.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg5.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg5.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)

	define void @test_vsseg5_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg5_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv2i8:			; CHECK-LABEL: test_vsseg5_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg5e8.v v8, (a0)			; CHECK-NEXT: vsseg5e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg5.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg5_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv2i8:			; CHECK-LABEL: test_vsseg5_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg6.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg6.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg6.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)

	define void @test_vsseg6_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg6_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv2i8:			; CHECK-LABEL: test_vsseg6_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg6e8.v v8, (a0)			; CHECK-NEXT: vsseg6e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg6.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg6_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv2i8:			; CHECK-LABEL: test_vsseg6_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg7.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg7.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg7.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)

	define void @test_vsseg7_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg7_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv2i8:			; CHECK-LABEL: test_vsseg7_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg7e8.v v8, (a0)			; CHECK-NEXT: vsseg7e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg7.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg7_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv2i8:			; CHECK-LABEL: test_vsseg7_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)			declare void @llvm.riscv.vsseg8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i32)
	declare void @llvm.riscv.vsseg8.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg8.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)

	define void @test_vsseg8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl) {			define void @test_vsseg8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv2i8:			; CHECK-LABEL: test_vsseg8_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg8e8.v v8, (a0)			; CHECK-NEXT: vsseg8e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %vl)			tail call void @llvm.riscv.vsseg8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg8_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv2i8:			; CHECK-LABEL: test_vsseg8_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg2.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)

	define void @test_vsseg2_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg2_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv2i16:			; CHECK-LABEL: test_vsseg2_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0)			; CHECK-NEXT: vsseg2e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv2i16:			; CHECK-LABEL: test_vsseg2_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg3.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg3.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg3.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)

	define void @test_vsseg3_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg3_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv2i16:			; CHECK-LABEL: test_vsseg3_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0)			; CHECK-NEXT: vsseg3e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg3.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg3_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv2i16:			; CHECK-LABEL: test_vsseg3_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg4.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg4.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg4.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)

	define void @test_vsseg4_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg4_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv2i16:			; CHECK-LABEL: test_vsseg4_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0)			; CHECK-NEXT: vsseg4e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg4.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg4_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv2i16:			; CHECK-LABEL: test_vsseg4_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg5.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg5.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg5.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)

	define void @test_vsseg5_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg5_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv2i16:			; CHECK-LABEL: test_vsseg5_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0)			; CHECK-NEXT: vsseg5e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg5.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg5_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv2i16:			; CHECK-LABEL: test_vsseg5_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg6.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg6.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg6.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)

	define void @test_vsseg6_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg6_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv2i16:			; CHECK-LABEL: test_vsseg6_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0)			; CHECK-NEXT: vsseg6e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg6.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg6_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv2i16:			; CHECK-LABEL: test_vsseg6_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg7.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg7.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg7.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)

	define void @test_vsseg7_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg7_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv2i16:			; CHECK-LABEL: test_vsseg7_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0)			; CHECK-NEXT: vsseg7e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg7.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg7_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv2i16:			; CHECK-LABEL: test_vsseg7_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)			declare void @llvm.riscv.vsseg8.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i32)
	declare void @llvm.riscv.vsseg8.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg8.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)

	define void @test_vsseg8_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl) {			define void @test_vsseg8_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv2i16:			; CHECK-LABEL: test_vsseg8_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0)			; CHECK-NEXT: vsseg8e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %vl)			tail call void @llvm.riscv.vsseg8.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg8_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv2i16:			; CHECK-LABEL: test_vsseg8_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i32)			declare void @llvm.riscv.vsseg2.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32)

	define void @test_vsseg2_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %vl) {			define void @test_vsseg2_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv4i32:			; CHECK-LABEL: test_vsseg2_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0)			; CHECK-NEXT: vsseg2e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv4i32:			; CHECK-LABEL: test_vsseg2_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i32)			declare void @llvm.riscv.vsseg3.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i32)
	declare void @llvm.riscv.vsseg3.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg3.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32)

	define void @test_vsseg3_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %vl) {			define void @test_vsseg3_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv4i32:			; CHECK-LABEL: test_vsseg3_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0)			; CHECK-NEXT: vsseg3e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i32 %vl)			tail call void @llvm.riscv.vsseg3.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg3_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv4i32:			; CHECK-LABEL: test_vsseg3_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i32)			declare void @llvm.riscv.vsseg4.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i32)
	declare void @llvm.riscv.vsseg4.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg4.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32)

	define void @test_vsseg4_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %vl) {			define void @test_vsseg4_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv4i32:			; CHECK-LABEL: test_vsseg4_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0)			; CHECK-NEXT: vsseg4e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i32 %vl)			tail call void @llvm.riscv.vsseg4.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg4_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv4i32:			; CHECK-LABEL: test_vsseg4_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half* , i32)			declare void @llvm.riscv.vsseg2.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i1>, i32)

	define void @test_vsseg2_nxv16f16(<vscale x 16 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg2_nxv16f16(<vscale x 16 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv16f16:			; CHECK-LABEL: test_vsseg2_nxv16f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0)			; CHECK-NEXT: vsseg2e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv16f16(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv16f16(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv16f16:			; CHECK-LABEL: test_vsseg2_mask_nxv16f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double* , i32)			declare void @llvm.riscv.vsseg2.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i1>, i32)

	define void @test_vsseg2_nxv4f64(<vscale x 4 x double> %val, double* %base, i32 %vl) {			define void @test_vsseg2_nxv4f64(<vscale x 4 x double> %val, double* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv4f64:			; CHECK-LABEL: test_vsseg2_nxv4f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
	; CHECK-NEXT: vsseg2e64.v v8, (a0)			; CHECK-NEXT: vsseg2e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv4f64(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv4f64(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv4f64:			; CHECK-LABEL: test_vsseg2_mask_nxv4f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
	; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)			declare void @llvm.riscv.vsseg2.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)

	define void @test_vsseg2_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl) {			define void @test_vsseg2_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv1f64:			; CHECK-LABEL: test_vsseg2_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg2e64.v v8, (a0)			; CHECK-NEXT: vsseg2e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv1f64:			; CHECK-LABEL: test_vsseg2_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)			declare void @llvm.riscv.vsseg3.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
	declare void @llvm.riscv.vsseg3.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg3.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)

	define void @test_vsseg3_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl) {			define void @test_vsseg3_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv1f64:			; CHECK-LABEL: test_vsseg3_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg3e64.v v8, (a0)			; CHECK-NEXT: vsseg3e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %vl)			tail call void @llvm.riscv.vsseg3.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg3_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv1f64:			; CHECK-LABEL: test_vsseg3_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg3e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)			declare void @llvm.riscv.vsseg4.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
	declare void @llvm.riscv.vsseg4.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg4.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)

	define void @test_vsseg4_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl) {			define void @test_vsseg4_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv1f64:			; CHECK-LABEL: test_vsseg4_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg4e64.v v8, (a0)			; CHECK-NEXT: vsseg4e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %vl)			tail call void @llvm.riscv.vsseg4.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg4_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv1f64:			; CHECK-LABEL: test_vsseg4_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg4e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)			declare void @llvm.riscv.vsseg5.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
	declare void @llvm.riscv.vsseg5.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg5.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)

	define void @test_vsseg5_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl) {			define void @test_vsseg5_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv1f64:			; CHECK-LABEL: test_vsseg5_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg5e64.v v8, (a0)			; CHECK-NEXT: vsseg5e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %vl)			tail call void @llvm.riscv.vsseg5.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg5_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv1f64:			; CHECK-LABEL: test_vsseg5_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg5e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)			declare void @llvm.riscv.vsseg6.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
	declare void @llvm.riscv.vsseg6.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg6.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)

	define void @test_vsseg6_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl) {			define void @test_vsseg6_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv1f64:			; CHECK-LABEL: test_vsseg6_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg6e64.v v8, (a0)			; CHECK-NEXT: vsseg6e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %vl)			tail call void @llvm.riscv.vsseg6.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg6_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv1f64:			; CHECK-LABEL: test_vsseg6_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg6e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)			declare void @llvm.riscv.vsseg7.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
	declare void @llvm.riscv.vsseg7.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg7.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)

	define void @test_vsseg7_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl) {			define void @test_vsseg7_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv1f64:			; CHECK-LABEL: test_vsseg7_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg7e64.v v8, (a0)			; CHECK-NEXT: vsseg7e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %vl)			tail call void @llvm.riscv.vsseg7.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg7_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv1f64:			; CHECK-LABEL: test_vsseg7_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg7e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)			declare void @llvm.riscv.vsseg8.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i32)
	declare void @llvm.riscv.vsseg8.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg8.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)

	define void @test_vsseg8_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl) {			define void @test_vsseg8_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv1f64:			; CHECK-LABEL: test_vsseg8_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg8e64.v v8, (a0)			; CHECK-NEXT: vsseg8e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %vl)			tail call void @llvm.riscv.vsseg8.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg8_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv1f64:			; CHECK-LABEL: test_vsseg8_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg8e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)			declare void @llvm.riscv.vsseg2.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)

	define void @test_vsseg2_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl) {			define void @test_vsseg2_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv2f32:			; CHECK-LABEL: test_vsseg2_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0)			; CHECK-NEXT: vsseg2e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv2f32:			; CHECK-LABEL: test_vsseg2_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)			declare void @llvm.riscv.vsseg3.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
	declare void @llvm.riscv.vsseg3.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg3.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)

	define void @test_vsseg3_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl) {			define void @test_vsseg3_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv2f32:			; CHECK-LABEL: test_vsseg3_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0)			; CHECK-NEXT: vsseg3e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %vl)			tail call void @llvm.riscv.vsseg3.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg3_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv2f32:			; CHECK-LABEL: test_vsseg3_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)			declare void @llvm.riscv.vsseg4.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
	declare void @llvm.riscv.vsseg4.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg4.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)

	define void @test_vsseg4_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl) {			define void @test_vsseg4_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv2f32:			; CHECK-LABEL: test_vsseg4_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0)			; CHECK-NEXT: vsseg4e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %vl)			tail call void @llvm.riscv.vsseg4.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg4_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv2f32:			; CHECK-LABEL: test_vsseg4_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)			declare void @llvm.riscv.vsseg5.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
	declare void @llvm.riscv.vsseg5.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg5.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)

	define void @test_vsseg5_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl) {			define void @test_vsseg5_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv2f32:			; CHECK-LABEL: test_vsseg5_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg5e32.v v8, (a0)			; CHECK-NEXT: vsseg5e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %vl)			tail call void @llvm.riscv.vsseg5.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg5_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv2f32:			; CHECK-LABEL: test_vsseg5_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)			declare void @llvm.riscv.vsseg6.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
	declare void @llvm.riscv.vsseg6.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg6.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)

	define void @test_vsseg6_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl) {			define void @test_vsseg6_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv2f32:			; CHECK-LABEL: test_vsseg6_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg6e32.v v8, (a0)			; CHECK-NEXT: vsseg6e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %vl)			tail call void @llvm.riscv.vsseg6.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg6_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv2f32:			; CHECK-LABEL: test_vsseg6_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)			declare void @llvm.riscv.vsseg7.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
	declare void @llvm.riscv.vsseg7.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg7.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)

	define void @test_vsseg7_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl) {			define void @test_vsseg7_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv2f32:			; CHECK-LABEL: test_vsseg7_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg7e32.v v8, (a0)			; CHECK-NEXT: vsseg7e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %vl)			tail call void @llvm.riscv.vsseg7.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg7_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv2f32:			; CHECK-LABEL: test_vsseg7_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)			declare void @llvm.riscv.vsseg8.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i32)
	declare void @llvm.riscv.vsseg8.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg8.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)

	define void @test_vsseg8_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl) {			define void @test_vsseg8_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv2f32:			; CHECK-LABEL: test_vsseg8_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg8e32.v v8, (a0)			; CHECK-NEXT: vsseg8e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %vl)			tail call void @llvm.riscv.vsseg8.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg8_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv2f32:			; CHECK-LABEL: test_vsseg8_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)			declare void @llvm.riscv.vsseg2.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)

	define void @test_vsseg2_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg2_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv1f16:			; CHECK-LABEL: test_vsseg2_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0)			; CHECK-NEXT: vsseg2e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv1f16:			; CHECK-LABEL: test_vsseg2_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)			declare void @llvm.riscv.vsseg3.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
	declare void @llvm.riscv.vsseg3.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg3.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)

	define void @test_vsseg3_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg3_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv1f16:			; CHECK-LABEL: test_vsseg3_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0)			; CHECK-NEXT: vsseg3e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg3.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg3_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv1f16:			; CHECK-LABEL: test_vsseg3_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)			declare void @llvm.riscv.vsseg4.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
	declare void @llvm.riscv.vsseg4.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg4.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)

	define void @test_vsseg4_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg4_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv1f16:			; CHECK-LABEL: test_vsseg4_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0)			; CHECK-NEXT: vsseg4e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg4.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg4_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv1f16:			; CHECK-LABEL: test_vsseg4_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)			declare void @llvm.riscv.vsseg5.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
	declare void @llvm.riscv.vsseg5.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg5.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)

	define void @test_vsseg5_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg5_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv1f16:			; CHECK-LABEL: test_vsseg5_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0)			; CHECK-NEXT: vsseg5e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg5.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg5_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv1f16:			; CHECK-LABEL: test_vsseg5_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)			declare void @llvm.riscv.vsseg6.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
	declare void @llvm.riscv.vsseg6.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg6.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)

	define void @test_vsseg6_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg6_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv1f16:			; CHECK-LABEL: test_vsseg6_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0)			; CHECK-NEXT: vsseg6e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg6.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg6_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv1f16:			; CHECK-LABEL: test_vsseg6_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)			declare void @llvm.riscv.vsseg7.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
	declare void @llvm.riscv.vsseg7.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg7.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)

	define void @test_vsseg7_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg7_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv1f16:			; CHECK-LABEL: test_vsseg7_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0)			; CHECK-NEXT: vsseg7e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg7.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg7_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv1f16:			; CHECK-LABEL: test_vsseg7_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)			declare void @llvm.riscv.vsseg8.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i32)
	declare void @llvm.riscv.vsseg8.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg8.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)

	define void @test_vsseg8_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg8_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv1f16:			; CHECK-LABEL: test_vsseg8_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0)			; CHECK-NEXT: vsseg8e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg8.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg8_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv1f16:			; CHECK-LABEL: test_vsseg8_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)			declare void @llvm.riscv.vsseg2.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)

	define void @test_vsseg2_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl) {			define void @test_vsseg2_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv1f32:			; CHECK-LABEL: test_vsseg2_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0)			; CHECK-NEXT: vsseg2e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv1f32:			; CHECK-LABEL: test_vsseg2_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)			declare void @llvm.riscv.vsseg3.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
	declare void @llvm.riscv.vsseg3.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg3.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)

	define void @test_vsseg3_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl) {			define void @test_vsseg3_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv1f32:			; CHECK-LABEL: test_vsseg3_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0)			; CHECK-NEXT: vsseg3e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %vl)			tail call void @llvm.riscv.vsseg3.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg3_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv1f32:			; CHECK-LABEL: test_vsseg3_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)			declare void @llvm.riscv.vsseg4.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
	declare void @llvm.riscv.vsseg4.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg4.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)

	define void @test_vsseg4_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl) {			define void @test_vsseg4_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv1f32:			; CHECK-LABEL: test_vsseg4_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0)			; CHECK-NEXT: vsseg4e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %vl)			tail call void @llvm.riscv.vsseg4.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg4_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv1f32:			; CHECK-LABEL: test_vsseg4_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)			declare void @llvm.riscv.vsseg5.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
	declare void @llvm.riscv.vsseg5.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg5.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)

	define void @test_vsseg5_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl) {			define void @test_vsseg5_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv1f32:			; CHECK-LABEL: test_vsseg5_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg5e32.v v8, (a0)			; CHECK-NEXT: vsseg5e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %vl)			tail call void @llvm.riscv.vsseg5.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg5_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv1f32:			; CHECK-LABEL: test_vsseg5_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)			declare void @llvm.riscv.vsseg6.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
	declare void @llvm.riscv.vsseg6.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg6.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)

	define void @test_vsseg6_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl) {			define void @test_vsseg6_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv1f32:			; CHECK-LABEL: test_vsseg6_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg6e32.v v8, (a0)			; CHECK-NEXT: vsseg6e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %vl)			tail call void @llvm.riscv.vsseg6.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg6_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv1f32:			; CHECK-LABEL: test_vsseg6_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)			declare void @llvm.riscv.vsseg7.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
	declare void @llvm.riscv.vsseg7.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg7.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)

	define void @test_vsseg7_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl) {			define void @test_vsseg7_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv1f32:			; CHECK-LABEL: test_vsseg7_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg7e32.v v8, (a0)			; CHECK-NEXT: vsseg7e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %vl)			tail call void @llvm.riscv.vsseg7.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg7_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv1f32:			; CHECK-LABEL: test_vsseg7_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)			declare void @llvm.riscv.vsseg8.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i32)
	declare void @llvm.riscv.vsseg8.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vsseg8.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)

	define void @test_vsseg8_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl) {			define void @test_vsseg8_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv1f32:			; CHECK-LABEL: test_vsseg8_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg8e32.v v8, (a0)			; CHECK-NEXT: vsseg8e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %vl)			tail call void @llvm.riscv.vsseg8.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vsseg8_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv1f32:			; CHECK-LABEL: test_vsseg8_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half* , i32)			declare void @llvm.riscv.vsseg2.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32)

	define void @test_vsseg2_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg2_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv8f16:			; CHECK-LABEL: test_vsseg2_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0)			; CHECK-NEXT: vsseg2e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv8f16:			; CHECK-LABEL: test_vsseg2_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i32)			declare void @llvm.riscv.vsseg3.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i32)
	declare void @llvm.riscv.vsseg3.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vsseg3.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32)

	define void @test_vsseg3_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg3_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv8f16:			; CHECK-LABEL: test_vsseg3_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0)			; CHECK-NEXT: vsseg3e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg3.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vsseg3_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv8f16:			; CHECK-LABEL: test_vsseg3_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i32)			declare void @llvm.riscv.vsseg4.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i32)
	declare void @llvm.riscv.vsseg4.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vsseg4.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32)

	define void @test_vsseg4_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg4_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv8f16:			; CHECK-LABEL: test_vsseg4_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0)			; CHECK-NEXT: vsseg4e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg4.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vsseg4_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv8f16:			; CHECK-LABEL: test_vsseg4_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float* , i32)			declare void @llvm.riscv.vsseg2.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i1>, i32)

	define void @test_vsseg2_nxv8f32(<vscale x 8 x float> %val, float* %base, i32 %vl) {			define void @test_vsseg2_nxv8f32(<vscale x 8 x float> %val, float* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv8f32:			; CHECK-LABEL: test_vsseg2_nxv8f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0)			; CHECK-NEXT: vsseg2e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv8f32(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv8f32(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv8f32:			; CHECK-LABEL: test_vsseg2_mask_nxv8f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double* , i32)			declare void @llvm.riscv.vsseg2.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32)

	define void @test_vsseg2_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %vl) {			define void @test_vsseg2_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv2f64:			; CHECK-LABEL: test_vsseg2_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vsseg2e64.v v8, (a0)			; CHECK-NEXT: vsseg2e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv2f64:			; CHECK-LABEL: test_vsseg2_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i32)			declare void @llvm.riscv.vsseg3.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i32)
	declare void @llvm.riscv.vsseg3.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg3.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32)

	define void @test_vsseg3_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %vl) {			define void @test_vsseg3_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv2f64:			; CHECK-LABEL: test_vsseg3_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vsseg3e64.v v8, (a0)			; CHECK-NEXT: vsseg3e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i32 %vl)			tail call void @llvm.riscv.vsseg3.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg3_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv2f64:			; CHECK-LABEL: test_vsseg3_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vsseg3e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i32)			declare void @llvm.riscv.vsseg4.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i32)
	declare void @llvm.riscv.vsseg4.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg4.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32)

	define void @test_vsseg4_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %vl) {			define void @test_vsseg4_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv2f64:			; CHECK-LABEL: test_vsseg4_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vsseg4e64.v v8, (a0)			; CHECK-NEXT: vsseg4e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i32 %vl)			tail call void @llvm.riscv.vsseg4.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg4_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv2f64:			; CHECK-LABEL: test_vsseg4_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vsseg4e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)			declare void @llvm.riscv.vsseg2.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)

	define void @test_vsseg2_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg2_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv4f16:			; CHECK-LABEL: test_vsseg2_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0)			; CHECK-NEXT: vsseg2e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv4f16:			; CHECK-LABEL: test_vsseg2_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)			declare void @llvm.riscv.vsseg3.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
	declare void @llvm.riscv.vsseg3.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg3.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)

	define void @test_vsseg3_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg3_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv4f16:			; CHECK-LABEL: test_vsseg3_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0)			; CHECK-NEXT: vsseg3e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg3.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg3_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv4f16:			; CHECK-LABEL: test_vsseg3_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)			declare void @llvm.riscv.vsseg4.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
	declare void @llvm.riscv.vsseg4.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg4.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)

	define void @test_vsseg4_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg4_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv4f16:			; CHECK-LABEL: test_vsseg4_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0)			; CHECK-NEXT: vsseg4e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg4.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg4_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv4f16:			; CHECK-LABEL: test_vsseg4_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)			declare void @llvm.riscv.vsseg5.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
	declare void @llvm.riscv.vsseg5.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg5.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)

	define void @test_vsseg5_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg5_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv4f16:			; CHECK-LABEL: test_vsseg5_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0)			; CHECK-NEXT: vsseg5e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg5.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg5_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv4f16:			; CHECK-LABEL: test_vsseg5_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)			declare void @llvm.riscv.vsseg6.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
	declare void @llvm.riscv.vsseg6.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg6.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)

	define void @test_vsseg6_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg6_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv4f16:			; CHECK-LABEL: test_vsseg6_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0)			; CHECK-NEXT: vsseg6e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg6.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg6_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv4f16:			; CHECK-LABEL: test_vsseg6_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)			declare void @llvm.riscv.vsseg7.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
	declare void @llvm.riscv.vsseg7.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg7.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)

	define void @test_vsseg7_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg7_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv4f16:			; CHECK-LABEL: test_vsseg7_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0)			; CHECK-NEXT: vsseg7e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg7.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg7_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv4f16:			; CHECK-LABEL: test_vsseg7_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)			declare void @llvm.riscv.vsseg8.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i32)
	declare void @llvm.riscv.vsseg8.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg8.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)

	define void @test_vsseg8_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg8_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv4f16:			; CHECK-LABEL: test_vsseg8_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0)			; CHECK-NEXT: vsseg8e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg8.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg8_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv4f16:			; CHECK-LABEL: test_vsseg8_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)			declare void @llvm.riscv.vsseg2.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)

	define void @test_vsseg2_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg2_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv2f16:			; CHECK-LABEL: test_vsseg2_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0)			; CHECK-NEXT: vsseg2e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv2f16:			; CHECK-LABEL: test_vsseg2_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)			declare void @llvm.riscv.vsseg3.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
	declare void @llvm.riscv.vsseg3.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg3.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)

	define void @test_vsseg3_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg3_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv2f16:			; CHECK-LABEL: test_vsseg3_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0)			; CHECK-NEXT: vsseg3e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg3.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg3_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv2f16:			; CHECK-LABEL: test_vsseg3_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)			declare void @llvm.riscv.vsseg4.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
	declare void @llvm.riscv.vsseg4.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg4.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)

	define void @test_vsseg4_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg4_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv2f16:			; CHECK-LABEL: test_vsseg4_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0)			; CHECK-NEXT: vsseg4e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg4.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg4_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv2f16:			; CHECK-LABEL: test_vsseg4_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)			declare void @llvm.riscv.vsseg5.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
	declare void @llvm.riscv.vsseg5.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg5.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)

	define void @test_vsseg5_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg5_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv2f16:			; CHECK-LABEL: test_vsseg5_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0)			; CHECK-NEXT: vsseg5e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg5.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg5_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv2f16:			; CHECK-LABEL: test_vsseg5_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)			declare void @llvm.riscv.vsseg6.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
	declare void @llvm.riscv.vsseg6.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg6.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)

	define void @test_vsseg6_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg6_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv2f16:			; CHECK-LABEL: test_vsseg6_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0)			; CHECK-NEXT: vsseg6e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg6.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg6_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv2f16:			; CHECK-LABEL: test_vsseg6_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)			declare void @llvm.riscv.vsseg7.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
	declare void @llvm.riscv.vsseg7.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg7.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)

	define void @test_vsseg7_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg7_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv2f16:			; CHECK-LABEL: test_vsseg7_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0)			; CHECK-NEXT: vsseg7e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg7.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg7_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv2f16:			; CHECK-LABEL: test_vsseg7_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)			declare void @llvm.riscv.vsseg8.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i32)
	declare void @llvm.riscv.vsseg8.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vsseg8.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)

	define void @test_vsseg8_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl) {			define void @test_vsseg8_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv2f16:			; CHECK-LABEL: test_vsseg8_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0)			; CHECK-NEXT: vsseg8e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %vl)			tail call void @llvm.riscv.vsseg8.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vsseg8_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv2f16:			; CHECK-LABEL: test_vsseg8_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float* , i32)			declare void @llvm.riscv.vsseg2.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float* , i32)
	declare void @llvm.riscv.vsseg2.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg2.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32)

	define void @test_vsseg2_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %vl) {			define void @test_vsseg2_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv4f32:			; CHECK-LABEL: test_vsseg2_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0)			; CHECK-NEXT: vsseg2e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i32 %vl)			tail call void @llvm.riscv.vsseg2.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg2_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv4f32:			; CHECK-LABEL: test_vsseg2_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i32)			declare void @llvm.riscv.vsseg3.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i32)
	declare void @llvm.riscv.vsseg3.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg3.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32)

	define void @test_vsseg3_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %vl) {			define void @test_vsseg3_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv4f32:			; CHECK-LABEL: test_vsseg3_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0)			; CHECK-NEXT: vsseg3e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i32 %vl)			tail call void @llvm.riscv.vsseg3.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg3_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv4f32:			; CHECK-LABEL: test_vsseg3_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i32)			declare void @llvm.riscv.vsseg4.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i32)
	declare void @llvm.riscv.vsseg4.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vsseg4.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32)

	define void @test_vsseg4_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %vl) {			define void @test_vsseg4_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv4f32:			; CHECK-LABEL: test_vsseg4_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0)			; CHECK-NEXT: vsseg4e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i32 %vl)			tail call void @llvm.riscv.vsseg4.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vsseg4_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv4f32:			; CHECK-LABEL: test_vsseg4_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \			; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \
	; RUN: -verify-machineinstrs < %s \| FileCheck %s			; RUN: -verify-machineinstrs < %s \| FileCheck %s

	declare void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i64)

	define void @test_vsseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv16i16:			; CHECK-LABEL: test_vsseg2_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0)			; CHECK-NEXT: vsseg2e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv16i16:			; CHECK-LABEL: test_vsseg2_mask_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i64)			declare void @llvm.riscv.vsseg2.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64)

	define void @test_vsseg2_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %vl) {			define void @test_vsseg2_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv4i32:			; CHECK-LABEL: test_vsseg2_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0)			; CHECK-NEXT: vsseg2e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv4i32:			; CHECK-LABEL: test_vsseg2_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i64)			declare void @llvm.riscv.vsseg3.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64)

	define void @test_vsseg3_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %vl) {			define void @test_vsseg3_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv4i32:			; CHECK-LABEL: test_vsseg3_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0)			; CHECK-NEXT: vsseg3e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv4i32:			; CHECK-LABEL: test_vsseg3_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i64)			declare void @llvm.riscv.vsseg4.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64)

	define void @test_vsseg4_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %vl) {			define void @test_vsseg4_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv4i32:			; CHECK-LABEL: test_vsseg4_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0)			; CHECK-NEXT: vsseg4e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv4i32:			; CHECK-LABEL: test_vsseg4_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg2.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64)

	define void @test_vsseg2_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg2_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv16i8:			; CHECK-LABEL: test_vsseg2_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0)			; CHECK-NEXT: vsseg2e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv16i8:			; CHECK-LABEL: test_vsseg2_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg3.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64)

	define void @test_vsseg3_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg3_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv16i8:			; CHECK-LABEL: test_vsseg3_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vsseg3e8.v v8, (a0)			; CHECK-NEXT: vsseg3e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv16i8:			; CHECK-LABEL: test_vsseg3_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg4.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64)

	define void @test_vsseg4_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg4_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv16i8:			; CHECK-LABEL: test_vsseg4_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vsseg4e8.v v8, (a0)			; CHECK-NEXT: vsseg4e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv16i8:			; CHECK-LABEL: test_vsseg4_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
	; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)			declare void @llvm.riscv.vsseg2.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)

	define void @test_vsseg2_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl) {			define void @test_vsseg2_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv1i64:			; CHECK-LABEL: test_vsseg2_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg2e64.v v8, (a0)			; CHECK-NEXT: vsseg2e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv1i64:			; CHECK-LABEL: test_vsseg2_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)			declare void @llvm.riscv.vsseg3.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)

	define void @test_vsseg3_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl) {			define void @test_vsseg3_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv1i64:			; CHECK-LABEL: test_vsseg3_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg3e64.v v8, (a0)			; CHECK-NEXT: vsseg3e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv1i64:			; CHECK-LABEL: test_vsseg3_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg3e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)			declare void @llvm.riscv.vsseg4.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)

	define void @test_vsseg4_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl) {			define void @test_vsseg4_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv1i64:			; CHECK-LABEL: test_vsseg4_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg4e64.v v8, (a0)			; CHECK-NEXT: vsseg4e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv1i64:			; CHECK-LABEL: test_vsseg4_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg4e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)			declare void @llvm.riscv.vsseg5.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
	declare void @llvm.riscv.vsseg5.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg5.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)

	define void @test_vsseg5_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl) {			define void @test_vsseg5_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv1i64:			; CHECK-LABEL: test_vsseg5_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg5e64.v v8, (a0)			; CHECK-NEXT: vsseg5e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %vl)			tail call void @llvm.riscv.vsseg5.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg5_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv1i64:			; CHECK-LABEL: test_vsseg5_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg5e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)			declare void @llvm.riscv.vsseg6.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
	declare void @llvm.riscv.vsseg6.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg6.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)

	define void @test_vsseg6_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl) {			define void @test_vsseg6_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv1i64:			; CHECK-LABEL: test_vsseg6_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg6e64.v v8, (a0)			; CHECK-NEXT: vsseg6e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %vl)			tail call void @llvm.riscv.vsseg6.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg6_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv1i64:			; CHECK-LABEL: test_vsseg6_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg6e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)			declare void @llvm.riscv.vsseg7.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
	declare void @llvm.riscv.vsseg7.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg7.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)

	define void @test_vsseg7_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl) {			define void @test_vsseg7_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv1i64:			; CHECK-LABEL: test_vsseg7_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg7e64.v v8, (a0)			; CHECK-NEXT: vsseg7e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %vl)			tail call void @llvm.riscv.vsseg7.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg7_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv1i64:			; CHECK-LABEL: test_vsseg7_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg7e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)			declare void @llvm.riscv.vsseg8.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64* , i64)
	declare void @llvm.riscv.vsseg8.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg8.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)

	define void @test_vsseg8_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl) {			define void @test_vsseg8_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv1i64:			; CHECK-LABEL: test_vsseg8_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg8e64.v v8, (a0)			; CHECK-NEXT: vsseg8e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %vl)			tail call void @llvm.riscv.vsseg8.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg8_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv1i64:			; CHECK-LABEL: test_vsseg8_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg8e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)			declare void @llvm.riscv.vsseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)

	define void @test_vsseg2_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl) {			define void @test_vsseg2_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv1i32:			; CHECK-LABEL: test_vsseg2_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0)			; CHECK-NEXT: vsseg2e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv1i32:			; CHECK-LABEL: test_vsseg2_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)			declare void @llvm.riscv.vsseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)

	define void @test_vsseg3_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl) {			define void @test_vsseg3_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv1i32:			; CHECK-LABEL: test_vsseg3_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0)			; CHECK-NEXT: vsseg3e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv1i32:			; CHECK-LABEL: test_vsseg3_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)			declare void @llvm.riscv.vsseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)

	define void @test_vsseg4_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl) {			define void @test_vsseg4_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv1i32:			; CHECK-LABEL: test_vsseg4_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0)			; CHECK-NEXT: vsseg4e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv1i32:			; CHECK-LABEL: test_vsseg4_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)			declare void @llvm.riscv.vsseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
	declare void @llvm.riscv.vsseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)

	define void @test_vsseg5_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl) {			define void @test_vsseg5_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv1i32:			; CHECK-LABEL: test_vsseg5_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg5e32.v v8, (a0)			; CHECK-NEXT: vsseg5e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %vl)			tail call void @llvm.riscv.vsseg5.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg5_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv1i32:			; CHECK-LABEL: test_vsseg5_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)			declare void @llvm.riscv.vsseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
	declare void @llvm.riscv.vsseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)

	define void @test_vsseg6_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl) {			define void @test_vsseg6_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv1i32:			; CHECK-LABEL: test_vsseg6_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg6e32.v v8, (a0)			; CHECK-NEXT: vsseg6e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %vl)			tail call void @llvm.riscv.vsseg6.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg6_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv1i32:			; CHECK-LABEL: test_vsseg6_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)			declare void @llvm.riscv.vsseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
	declare void @llvm.riscv.vsseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)

	define void @test_vsseg7_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl) {			define void @test_vsseg7_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv1i32:			; CHECK-LABEL: test_vsseg7_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg7e32.v v8, (a0)			; CHECK-NEXT: vsseg7e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %vl)			tail call void @llvm.riscv.vsseg7.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg7_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv1i32:			; CHECK-LABEL: test_vsseg7_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)			declare void @llvm.riscv.vsseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32* , i64)
	declare void @llvm.riscv.vsseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)

	define void @test_vsseg8_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl) {			define void @test_vsseg8_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv1i32:			; CHECK-LABEL: test_vsseg8_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg8e32.v v8, (a0)			; CHECK-NEXT: vsseg8e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %vl)			tail call void @llvm.riscv.vsseg8.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg8_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv1i32:			; CHECK-LABEL: test_vsseg8_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg2.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64)

	define void @test_vsseg2_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg2_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv8i16:			; CHECK-LABEL: test_vsseg2_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0)			; CHECK-NEXT: vsseg2e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv8i16:			; CHECK-LABEL: test_vsseg2_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg3.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64)

	define void @test_vsseg3_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg3_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv8i16:			; CHECK-LABEL: test_vsseg3_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0)			; CHECK-NEXT: vsseg3e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv8i16:			; CHECK-LABEL: test_vsseg3_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg4.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64)

	define void @test_vsseg4_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg4_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv8i16:			; CHECK-LABEL: test_vsseg4_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0)			; CHECK-NEXT: vsseg4e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv8i16:			; CHECK-LABEL: test_vsseg4_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg2.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)

	define void @test_vsseg2_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg2_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv4i8:			; CHECK-LABEL: test_vsseg2_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0)			; CHECK-NEXT: vsseg2e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv4i8:			; CHECK-LABEL: test_vsseg2_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg3.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)

	define void @test_vsseg3_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg3_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv4i8:			; CHECK-LABEL: test_vsseg3_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg3e8.v v8, (a0)			; CHECK-NEXT: vsseg3e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv4i8:			; CHECK-LABEL: test_vsseg3_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg4.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)

	define void @test_vsseg4_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg4_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv4i8:			; CHECK-LABEL: test_vsseg4_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg4e8.v v8, (a0)			; CHECK-NEXT: vsseg4e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv4i8:			; CHECK-LABEL: test_vsseg4_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg5.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg5.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg5.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)

	define void @test_vsseg5_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg5_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv4i8:			; CHECK-LABEL: test_vsseg5_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg5e8.v v8, (a0)			; CHECK-NEXT: vsseg5e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg5.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg5_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv4i8:			; CHECK-LABEL: test_vsseg5_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg6.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg6.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg6.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)

	define void @test_vsseg6_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg6_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv4i8:			; CHECK-LABEL: test_vsseg6_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg6e8.v v8, (a0)			; CHECK-NEXT: vsseg6e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg6.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg6_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv4i8:			; CHECK-LABEL: test_vsseg6_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg7.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg7.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg7.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)

	define void @test_vsseg7_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg7_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv4i8:			; CHECK-LABEL: test_vsseg7_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg7e8.v v8, (a0)			; CHECK-NEXT: vsseg7e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg7.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg7_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv4i8:			; CHECK-LABEL: test_vsseg7_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg8.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg8.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)

	define void @test_vsseg8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv4i8:			; CHECK-LABEL: test_vsseg8_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg8e8.v v8, (a0)			; CHECK-NEXT: vsseg8e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg8_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv4i8:			; CHECK-LABEL: test_vsseg8_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
	; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg2.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)

	define void @test_vsseg2_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg2_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv1i16:			; CHECK-LABEL: test_vsseg2_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0)			; CHECK-NEXT: vsseg2e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv1i16:			; CHECK-LABEL: test_vsseg2_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg3.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)

	define void @test_vsseg3_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg3_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv1i16:			; CHECK-LABEL: test_vsseg3_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0)			; CHECK-NEXT: vsseg3e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv1i16:			; CHECK-LABEL: test_vsseg3_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg4.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)

	define void @test_vsseg4_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg4_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv1i16:			; CHECK-LABEL: test_vsseg4_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0)			; CHECK-NEXT: vsseg4e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv1i16:			; CHECK-LABEL: test_vsseg4_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg5.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg5.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg5.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)

	define void @test_vsseg5_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg5_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv1i16:			; CHECK-LABEL: test_vsseg5_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0)			; CHECK-NEXT: vsseg5e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg5.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg5_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv1i16:			; CHECK-LABEL: test_vsseg5_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg6.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg6.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg6.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)

	define void @test_vsseg6_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg6_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv1i16:			; CHECK-LABEL: test_vsseg6_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0)			; CHECK-NEXT: vsseg6e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg6.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg6_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv1i16:			; CHECK-LABEL: test_vsseg6_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg7.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg7.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg7.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)

	define void @test_vsseg7_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg7_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv1i16:			; CHECK-LABEL: test_vsseg7_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0)			; CHECK-NEXT: vsseg7e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg7.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg7_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv1i16:			; CHECK-LABEL: test_vsseg7_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg8.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg8.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg8.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)

	define void @test_vsseg8_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg8_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv1i16:			; CHECK-LABEL: test_vsseg8_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0)			; CHECK-NEXT: vsseg8e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg8.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg8_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv1i16:			; CHECK-LABEL: test_vsseg8_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)			declare void @llvm.riscv.vsseg2.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)

	define void @test_vsseg2_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl) {			define void @test_vsseg2_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv2i32:			; CHECK-LABEL: test_vsseg2_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0)			; CHECK-NEXT: vsseg2e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv2i32:			; CHECK-LABEL: test_vsseg2_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)			declare void @llvm.riscv.vsseg3.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)

	define void @test_vsseg3_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl) {			define void @test_vsseg3_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv2i32:			; CHECK-LABEL: test_vsseg3_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0)			; CHECK-NEXT: vsseg3e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv2i32:			; CHECK-LABEL: test_vsseg3_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)			declare void @llvm.riscv.vsseg4.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)

	define void @test_vsseg4_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl) {			define void @test_vsseg4_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv2i32:			; CHECK-LABEL: test_vsseg4_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0)			; CHECK-NEXT: vsseg4e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv2i32:			; CHECK-LABEL: test_vsseg4_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)			declare void @llvm.riscv.vsseg5.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
	declare void @llvm.riscv.vsseg5.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg5.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)

	define void @test_vsseg5_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl) {			define void @test_vsseg5_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv2i32:			; CHECK-LABEL: test_vsseg5_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg5e32.v v8, (a0)			; CHECK-NEXT: vsseg5e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %vl)			tail call void @llvm.riscv.vsseg5.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg5_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv2i32:			; CHECK-LABEL: test_vsseg5_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)			declare void @llvm.riscv.vsseg6.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
	declare void @llvm.riscv.vsseg6.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg6.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)

	define void @test_vsseg6_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl) {			define void @test_vsseg6_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv2i32:			; CHECK-LABEL: test_vsseg6_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg6e32.v v8, (a0)			; CHECK-NEXT: vsseg6e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %vl)			tail call void @llvm.riscv.vsseg6.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg6_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv2i32:			; CHECK-LABEL: test_vsseg6_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)			declare void @llvm.riscv.vsseg7.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
	declare void @llvm.riscv.vsseg7.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg7.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)

	define void @test_vsseg7_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl) {			define void @test_vsseg7_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv2i32:			; CHECK-LABEL: test_vsseg7_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg7e32.v v8, (a0)			; CHECK-NEXT: vsseg7e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %vl)			tail call void @llvm.riscv.vsseg7.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg7_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv2i32:			; CHECK-LABEL: test_vsseg7_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)			declare void @llvm.riscv.vsseg8.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32* , i64)
	declare void @llvm.riscv.vsseg8.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg8.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)

	define void @test_vsseg8_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl) {			define void @test_vsseg8_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv2i32:			; CHECK-LABEL: test_vsseg8_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg8e32.v v8, (a0)			; CHECK-NEXT: vsseg8e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %vl)			tail call void @llvm.riscv.vsseg8.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg8_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv2i32:			; CHECK-LABEL: test_vsseg8_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg2.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)

	define void @test_vsseg2_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg2_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv8i8:			; CHECK-LABEL: test_vsseg2_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0)			; CHECK-NEXT: vsseg2e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv8i8:			; CHECK-LABEL: test_vsseg2_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg3.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)

	define void @test_vsseg3_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg3_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv8i8:			; CHECK-LABEL: test_vsseg3_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg3e8.v v8, (a0)			; CHECK-NEXT: vsseg3e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv8i8:			; CHECK-LABEL: test_vsseg3_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg4.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)

	define void @test_vsseg4_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg4_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv8i8:			; CHECK-LABEL: test_vsseg4_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg4e8.v v8, (a0)			; CHECK-NEXT: vsseg4e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv8i8:			; CHECK-LABEL: test_vsseg4_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg5.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg5.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vsseg5.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)

	define void @test_vsseg5_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg5_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv8i8:			; CHECK-LABEL: test_vsseg5_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg5e8.v v8, (a0)			; CHECK-NEXT: vsseg5e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg5.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vsseg5_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv8i8:			; CHECK-LABEL: test_vsseg5_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg6.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg6.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vsseg6.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)

	define void @test_vsseg6_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg6_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv8i8:			; CHECK-LABEL: test_vsseg6_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg6e8.v v8, (a0)			; CHECK-NEXT: vsseg6e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg6.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vsseg6_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv8i8:			; CHECK-LABEL: test_vsseg6_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg7.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg7.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vsseg7.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)

	define void @test_vsseg7_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg7_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv8i8:			; CHECK-LABEL: test_vsseg7_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg7e8.v v8, (a0)			; CHECK-NEXT: vsseg7e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg7.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vsseg7_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv8i8:			; CHECK-LABEL: test_vsseg7_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg8.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vsseg8.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)

	define void @test_vsseg8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv8i8:			; CHECK-LABEL: test_vsseg8_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg8e8.v v8, (a0)			; CHECK-NEXT: vsseg8e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vsseg8_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv8i8:			; CHECK-LABEL: test_vsseg8_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
	; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64* , i64)			declare void @llvm.riscv.vsseg2.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i1>, i64)

	define void @test_vsseg2_nxv4i64(<vscale x 4 x i64> %val, i64* %base, i64 %vl) {			define void @test_vsseg2_nxv4i64(<vscale x 4 x i64> %val, i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv4i64:			; CHECK-LABEL: test_vsseg2_nxv4i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
	; CHECK-NEXT: vsseg2e64.v v8, (a0)			; CHECK-NEXT: vsseg2e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv4i64(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv4i64(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv4i64:			; CHECK-LABEL: test_vsseg2_mask_nxv4i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
	; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg2.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)

	define void @test_vsseg2_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg2_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv4i16:			; CHECK-LABEL: test_vsseg2_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0)			; CHECK-NEXT: vsseg2e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv4i16:			; CHECK-LABEL: test_vsseg2_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg3.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)

	define void @test_vsseg3_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg3_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv4i16:			; CHECK-LABEL: test_vsseg3_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0)			; CHECK-NEXT: vsseg3e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv4i16:			; CHECK-LABEL: test_vsseg3_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg4.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)

	define void @test_vsseg4_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg4_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv4i16:			; CHECK-LABEL: test_vsseg4_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0)			; CHECK-NEXT: vsseg4e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv4i16:			; CHECK-LABEL: test_vsseg4_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg5.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg5.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg5.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)

	define void @test_vsseg5_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg5_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv4i16:			; CHECK-LABEL: test_vsseg5_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0)			; CHECK-NEXT: vsseg5e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg5.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg5_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv4i16:			; CHECK-LABEL: test_vsseg5_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg6.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg6.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg6.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)

	define void @test_vsseg6_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg6_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv4i16:			; CHECK-LABEL: test_vsseg6_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0)			; CHECK-NEXT: vsseg6e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg6.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg6_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv4i16:			; CHECK-LABEL: test_vsseg6_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg7.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg7.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg7.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)

	define void @test_vsseg7_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg7_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv4i16:			; CHECK-LABEL: test_vsseg7_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0)			; CHECK-NEXT: vsseg7e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg7.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg7_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv4i16:			; CHECK-LABEL: test_vsseg7_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg8.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg8.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg8.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)

	define void @test_vsseg8_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg8_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv4i16:			; CHECK-LABEL: test_vsseg8_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0)			; CHECK-NEXT: vsseg8e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg8.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg8_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv4i16:			; CHECK-LABEL: test_vsseg8_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg2.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)

	define void @test_vsseg2_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg2_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv1i8:			; CHECK-LABEL: test_vsseg2_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0)			; CHECK-NEXT: vsseg2e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv1i8:			; CHECK-LABEL: test_vsseg2_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg3.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)

	define void @test_vsseg3_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg3_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv1i8:			; CHECK-LABEL: test_vsseg3_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg3e8.v v8, (a0)			; CHECK-NEXT: vsseg3e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv1i8:			; CHECK-LABEL: test_vsseg3_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg4.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)

	define void @test_vsseg4_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg4_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv1i8:			; CHECK-LABEL: test_vsseg4_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg4e8.v v8, (a0)			; CHECK-NEXT: vsseg4e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv1i8:			; CHECK-LABEL: test_vsseg4_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg5.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg5.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg5.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)

	define void @test_vsseg5_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg5_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv1i8:			; CHECK-LABEL: test_vsseg5_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg5e8.v v8, (a0)			; CHECK-NEXT: vsseg5e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg5.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg5_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv1i8:			; CHECK-LABEL: test_vsseg5_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg6.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg6.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg6.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)

	define void @test_vsseg6_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg6_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv1i8:			; CHECK-LABEL: test_vsseg6_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg6e8.v v8, (a0)			; CHECK-NEXT: vsseg6e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg6.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg6_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv1i8:			; CHECK-LABEL: test_vsseg6_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg7.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg7.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg7.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)

	define void @test_vsseg7_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg7_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv1i8:			; CHECK-LABEL: test_vsseg7_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg7e8.v v8, (a0)			; CHECK-NEXT: vsseg7e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg7.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg7_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv1i8:			; CHECK-LABEL: test_vsseg7_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg8.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg8.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)

	define void @test_vsseg8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv1i8:			; CHECK-LABEL: test_vsseg8_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg8e8.v v8, (a0)			; CHECK-NEXT: vsseg8e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg8_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv1i8:			; CHECK-LABEL: test_vsseg8_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
	; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg2.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)

	define void @test_vsseg2_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg2_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv2i8:			; CHECK-LABEL: test_vsseg2_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0)			; CHECK-NEXT: vsseg2e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv2i8:			; CHECK-LABEL: test_vsseg2_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg3.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)

	define void @test_vsseg3_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg3_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv2i8:			; CHECK-LABEL: test_vsseg3_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg3e8.v v8, (a0)			; CHECK-NEXT: vsseg3e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv2i8:			; CHECK-LABEL: test_vsseg3_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg4.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)

	define void @test_vsseg4_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg4_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv2i8:			; CHECK-LABEL: test_vsseg4_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg4e8.v v8, (a0)			; CHECK-NEXT: vsseg4e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv2i8:			; CHECK-LABEL: test_vsseg4_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg5.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg5.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg5.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)

	define void @test_vsseg5_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg5_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv2i8:			; CHECK-LABEL: test_vsseg5_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg5e8.v v8, (a0)			; CHECK-NEXT: vsseg5e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg5.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg5_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv2i8:			; CHECK-LABEL: test_vsseg5_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg6.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg6.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg6.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)

	define void @test_vsseg6_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg6_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv2i8:			; CHECK-LABEL: test_vsseg6_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg6e8.v v8, (a0)			; CHECK-NEXT: vsseg6e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg6.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg6_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv2i8:			; CHECK-LABEL: test_vsseg6_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg7.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg7.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg7.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)

	define void @test_vsseg7_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg7_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv2i8:			; CHECK-LABEL: test_vsseg7_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg7e8.v v8, (a0)			; CHECK-NEXT: vsseg7e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg7.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg7_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv2i8:			; CHECK-LABEL: test_vsseg7_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg8.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg8.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)

	define void @test_vsseg8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv2i8:			; CHECK-LABEL: test_vsseg8_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg8e8.v v8, (a0)			; CHECK-NEXT: vsseg8e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg8_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv2i8:			; CHECK-LABEL: test_vsseg8_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
	; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32* , i64)			declare void @llvm.riscv.vsseg2.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i1>, i64)

	define void @test_vsseg2_nxv8i32(<vscale x 8 x i32> %val, i32* %base, i64 %vl) {			define void @test_vsseg2_nxv8i32(<vscale x 8 x i32> %val, i32* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv8i32:			; CHECK-LABEL: test_vsseg2_nxv8i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0)			; CHECK-NEXT: vsseg2e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv8i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv8i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv8i32:			; CHECK-LABEL: test_vsseg2_mask_nxv8i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8* , i64)			declare void @llvm.riscv.vsseg2.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i1>, i64)

	define void @test_vsseg2_nxv32i8(<vscale x 32 x i8> %val, i8* %base, i64 %vl) {			define void @test_vsseg2_nxv32i8(<vscale x 32 x i8> %val, i8* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv32i8:			; CHECK-LABEL: test_vsseg2_nxv32i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0)			; CHECK-NEXT: vsseg2e8.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv32i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv32i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv32i8:			; CHECK-LABEL: test_vsseg2_mask_nxv32i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
	; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg2.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)

	define void @test_vsseg2_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg2_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv2i16:			; CHECK-LABEL: test_vsseg2_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0)			; CHECK-NEXT: vsseg2e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv2i16:			; CHECK-LABEL: test_vsseg2_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg3.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)

	define void @test_vsseg3_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg3_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv2i16:			; CHECK-LABEL: test_vsseg3_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0)			; CHECK-NEXT: vsseg3e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv2i16:			; CHECK-LABEL: test_vsseg3_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg4.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)

	define void @test_vsseg4_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg4_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv2i16:			; CHECK-LABEL: test_vsseg4_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0)			; CHECK-NEXT: vsseg4e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv2i16:			; CHECK-LABEL: test_vsseg4_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg5.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg5.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg5.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)

	define void @test_vsseg5_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg5_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv2i16:			; CHECK-LABEL: test_vsseg5_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0)			; CHECK-NEXT: vsseg5e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg5.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg5_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv2i16:			; CHECK-LABEL: test_vsseg5_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg6.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg6.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg6.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)

	define void @test_vsseg6_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg6_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv2i16:			; CHECK-LABEL: test_vsseg6_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0)			; CHECK-NEXT: vsseg6e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg6.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg6_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv2i16:			; CHECK-LABEL: test_vsseg6_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg7.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg7.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg7.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)

	define void @test_vsseg7_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg7_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv2i16:			; CHECK-LABEL: test_vsseg7_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0)			; CHECK-NEXT: vsseg7e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg7.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg7_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv2i16:			; CHECK-LABEL: test_vsseg7_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg8.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg8.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg8.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)

	define void @test_vsseg8_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl) {			define void @test_vsseg8_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv2i16:			; CHECK-LABEL: test_vsseg8_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0)			; CHECK-NEXT: vsseg8e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %vl)			tail call void @llvm.riscv.vsseg8.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg8_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv2i16:			; CHECK-LABEL: test_vsseg8_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64* , i64)			declare void @llvm.riscv.vsseg2.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64)

	define void @test_vsseg2_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %vl) {			define void @test_vsseg2_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv2i64:			; CHECK-LABEL: test_vsseg2_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vsseg2e64.v v8, (a0)			; CHECK-NEXT: vsseg2e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv2i64:			; CHECK-LABEL: test_vsseg2_mask_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64* , i64)			declare void @llvm.riscv.vsseg3.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64)

	define void @test_vsseg3_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %vl) {			define void @test_vsseg3_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv2i64:			; CHECK-LABEL: test_vsseg3_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vsseg3e64.v v8, (a0)			; CHECK-NEXT: vsseg3e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv2i64:			; CHECK-LABEL: test_vsseg3_mask_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vsseg3e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64* , i64)			declare void @llvm.riscv.vsseg4.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64)

	define void @test_vsseg4_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %vl) {			define void @test_vsseg4_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv2i64:			; CHECK-LABEL: test_vsseg4_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vsseg4e64.v v8, (a0)			; CHECK-NEXT: vsseg4e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv2i64:			; CHECK-LABEL: test_vsseg4_mask_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vsseg4e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half* , i64)			declare void @llvm.riscv.vsseg2.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i1>, i64)

	define void @test_vsseg2_nxv16f16(<vscale x 16 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg2_nxv16f16(<vscale x 16 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv16f16:			; CHECK-LABEL: test_vsseg2_nxv16f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0)			; CHECK-NEXT: vsseg2e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv16f16(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv16f16(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv16f16:			; CHECK-LABEL: test_vsseg2_mask_nxv16f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double* , i64)			declare void @llvm.riscv.vsseg2.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i1>, i64)

	define void @test_vsseg2_nxv4f64(<vscale x 4 x double> %val, double* %base, i64 %vl) {			define void @test_vsseg2_nxv4f64(<vscale x 4 x double> %val, double* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv4f64:			; CHECK-LABEL: test_vsseg2_nxv4f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
	; CHECK-NEXT: vsseg2e64.v v8, (a0)			; CHECK-NEXT: vsseg2e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv4f64(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv4f64(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv4f64:			; CHECK-LABEL: test_vsseg2_mask_nxv4f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
	; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)			declare void @llvm.riscv.vsseg2.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)

	define void @test_vsseg2_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl) {			define void @test_vsseg2_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv1f64:			; CHECK-LABEL: test_vsseg2_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg2e64.v v8, (a0)			; CHECK-NEXT: vsseg2e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv1f64:			; CHECK-LABEL: test_vsseg2_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)			declare void @llvm.riscv.vsseg3.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)

	define void @test_vsseg3_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl) {			define void @test_vsseg3_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv1f64:			; CHECK-LABEL: test_vsseg3_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg3e64.v v8, (a0)			; CHECK-NEXT: vsseg3e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv1f64:			; CHECK-LABEL: test_vsseg3_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg3e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)			declare void @llvm.riscv.vsseg4.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)

	define void @test_vsseg4_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl) {			define void @test_vsseg4_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv1f64:			; CHECK-LABEL: test_vsseg4_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg4e64.v v8, (a0)			; CHECK-NEXT: vsseg4e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv1f64:			; CHECK-LABEL: test_vsseg4_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg4e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)			declare void @llvm.riscv.vsseg5.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
	declare void @llvm.riscv.vsseg5.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg5.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)

	define void @test_vsseg5_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl) {			define void @test_vsseg5_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv1f64:			; CHECK-LABEL: test_vsseg5_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg5e64.v v8, (a0)			; CHECK-NEXT: vsseg5e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %vl)			tail call void @llvm.riscv.vsseg5.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg5_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv1f64:			; CHECK-LABEL: test_vsseg5_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg5e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)			declare void @llvm.riscv.vsseg6.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
	declare void @llvm.riscv.vsseg6.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg6.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)

	define void @test_vsseg6_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl) {			define void @test_vsseg6_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv1f64:			; CHECK-LABEL: test_vsseg6_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg6e64.v v8, (a0)			; CHECK-NEXT: vsseg6e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %vl)			tail call void @llvm.riscv.vsseg6.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg6_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv1f64:			; CHECK-LABEL: test_vsseg6_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg6e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)			declare void @llvm.riscv.vsseg7.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
	declare void @llvm.riscv.vsseg7.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg7.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)

	define void @test_vsseg7_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl) {			define void @test_vsseg7_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv1f64:			; CHECK-LABEL: test_vsseg7_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg7e64.v v8, (a0)			; CHECK-NEXT: vsseg7e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %vl)			tail call void @llvm.riscv.vsseg7.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg7_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv1f64:			; CHECK-LABEL: test_vsseg7_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg7e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)			declare void @llvm.riscv.vsseg8.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double* , i64)
	declare void @llvm.riscv.vsseg8.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg8.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)

	define void @test_vsseg8_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl) {			define void @test_vsseg8_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv1f64:			; CHECK-LABEL: test_vsseg8_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg8e64.v v8, (a0)			; CHECK-NEXT: vsseg8e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %vl)			tail call void @llvm.riscv.vsseg8.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg8_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv1f64:			; CHECK-LABEL: test_vsseg8_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
	; CHECK-NEXT: vsseg8e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)			declare void @llvm.riscv.vsseg2.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)

	define void @test_vsseg2_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl) {			define void @test_vsseg2_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv2f32:			; CHECK-LABEL: test_vsseg2_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0)			; CHECK-NEXT: vsseg2e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv2f32:			; CHECK-LABEL: test_vsseg2_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)			declare void @llvm.riscv.vsseg3.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)

	define void @test_vsseg3_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl) {			define void @test_vsseg3_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv2f32:			; CHECK-LABEL: test_vsseg3_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0)			; CHECK-NEXT: vsseg3e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv2f32:			; CHECK-LABEL: test_vsseg3_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)			declare void @llvm.riscv.vsseg4.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)

	define void @test_vsseg4_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl) {			define void @test_vsseg4_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv2f32:			; CHECK-LABEL: test_vsseg4_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0)			; CHECK-NEXT: vsseg4e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv2f32:			; CHECK-LABEL: test_vsseg4_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)			declare void @llvm.riscv.vsseg5.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
	declare void @llvm.riscv.vsseg5.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg5.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)

	define void @test_vsseg5_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl) {			define void @test_vsseg5_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv2f32:			; CHECK-LABEL: test_vsseg5_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg5e32.v v8, (a0)			; CHECK-NEXT: vsseg5e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %vl)			tail call void @llvm.riscv.vsseg5.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg5_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv2f32:			; CHECK-LABEL: test_vsseg5_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)			declare void @llvm.riscv.vsseg6.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
	declare void @llvm.riscv.vsseg6.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg6.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)

	define void @test_vsseg6_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl) {			define void @test_vsseg6_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv2f32:			; CHECK-LABEL: test_vsseg6_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg6e32.v v8, (a0)			; CHECK-NEXT: vsseg6e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %vl)			tail call void @llvm.riscv.vsseg6.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg6_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv2f32:			; CHECK-LABEL: test_vsseg6_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)			declare void @llvm.riscv.vsseg7.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
	declare void @llvm.riscv.vsseg7.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg7.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)

	define void @test_vsseg7_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl) {			define void @test_vsseg7_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv2f32:			; CHECK-LABEL: test_vsseg7_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg7e32.v v8, (a0)			; CHECK-NEXT: vsseg7e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %vl)			tail call void @llvm.riscv.vsseg7.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg7_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv2f32:			; CHECK-LABEL: test_vsseg7_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)			declare void @llvm.riscv.vsseg8.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float* , i64)
	declare void @llvm.riscv.vsseg8.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg8.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)

	define void @test_vsseg8_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl) {			define void @test_vsseg8_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv2f32:			; CHECK-LABEL: test_vsseg8_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg8e32.v v8, (a0)			; CHECK-NEXT: vsseg8e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %vl)			tail call void @llvm.riscv.vsseg8.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg8_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv2f32:			; CHECK-LABEL: test_vsseg8_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
	; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)			declare void @llvm.riscv.vsseg2.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)

	define void @test_vsseg2_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg2_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv1f16:			; CHECK-LABEL: test_vsseg2_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0)			; CHECK-NEXT: vsseg2e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv1f16:			; CHECK-LABEL: test_vsseg2_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)			declare void @llvm.riscv.vsseg3.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)

	define void @test_vsseg3_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg3_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv1f16:			; CHECK-LABEL: test_vsseg3_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0)			; CHECK-NEXT: vsseg3e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv1f16:			; CHECK-LABEL: test_vsseg3_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)			declare void @llvm.riscv.vsseg4.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)

	define void @test_vsseg4_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg4_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv1f16:			; CHECK-LABEL: test_vsseg4_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0)			; CHECK-NEXT: vsseg4e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv1f16:			; CHECK-LABEL: test_vsseg4_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)			declare void @llvm.riscv.vsseg5.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
	declare void @llvm.riscv.vsseg5.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg5.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)

	define void @test_vsseg5_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg5_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv1f16:			; CHECK-LABEL: test_vsseg5_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0)			; CHECK-NEXT: vsseg5e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg5.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg5_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv1f16:			; CHECK-LABEL: test_vsseg5_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)			declare void @llvm.riscv.vsseg6.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
	declare void @llvm.riscv.vsseg6.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg6.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)

	define void @test_vsseg6_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg6_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv1f16:			; CHECK-LABEL: test_vsseg6_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0)			; CHECK-NEXT: vsseg6e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg6.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg6_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv1f16:			; CHECK-LABEL: test_vsseg6_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)			declare void @llvm.riscv.vsseg7.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
	declare void @llvm.riscv.vsseg7.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg7.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)

	define void @test_vsseg7_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg7_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv1f16:			; CHECK-LABEL: test_vsseg7_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0)			; CHECK-NEXT: vsseg7e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg7.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg7_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv1f16:			; CHECK-LABEL: test_vsseg7_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)			declare void @llvm.riscv.vsseg8.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half* , i64)
	declare void @llvm.riscv.vsseg8.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg8.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)

	define void @test_vsseg8_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg8_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv1f16:			; CHECK-LABEL: test_vsseg8_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0)			; CHECK-NEXT: vsseg8e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg8.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg8_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv1f16:			; CHECK-LABEL: test_vsseg8_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)			declare void @llvm.riscv.vsseg2.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)

	define void @test_vsseg2_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl) {			define void @test_vsseg2_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv1f32:			; CHECK-LABEL: test_vsseg2_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0)			; CHECK-NEXT: vsseg2e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv1f32:			; CHECK-LABEL: test_vsseg2_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)			declare void @llvm.riscv.vsseg3.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)

	define void @test_vsseg3_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl) {			define void @test_vsseg3_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv1f32:			; CHECK-LABEL: test_vsseg3_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0)			; CHECK-NEXT: vsseg3e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv1f32:			; CHECK-LABEL: test_vsseg3_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)			declare void @llvm.riscv.vsseg4.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)

	define void @test_vsseg4_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl) {			define void @test_vsseg4_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv1f32:			; CHECK-LABEL: test_vsseg4_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0)			; CHECK-NEXT: vsseg4e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv1f32:			; CHECK-LABEL: test_vsseg4_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)			declare void @llvm.riscv.vsseg5.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
	declare void @llvm.riscv.vsseg5.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg5.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)

	define void @test_vsseg5_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl) {			define void @test_vsseg5_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv1f32:			; CHECK-LABEL: test_vsseg5_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg5e32.v v8, (a0)			; CHECK-NEXT: vsseg5e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %vl)			tail call void @llvm.riscv.vsseg5.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg5_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv1f32:			; CHECK-LABEL: test_vsseg5_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)			declare void @llvm.riscv.vsseg6.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
	declare void @llvm.riscv.vsseg6.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg6.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)

	define void @test_vsseg6_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl) {			define void @test_vsseg6_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv1f32:			; CHECK-LABEL: test_vsseg6_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg6e32.v v8, (a0)			; CHECK-NEXT: vsseg6e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %vl)			tail call void @llvm.riscv.vsseg6.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg6_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv1f32:			; CHECK-LABEL: test_vsseg6_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)			declare void @llvm.riscv.vsseg7.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
	declare void @llvm.riscv.vsseg7.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg7.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)

	define void @test_vsseg7_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl) {			define void @test_vsseg7_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv1f32:			; CHECK-LABEL: test_vsseg7_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg7e32.v v8, (a0)			; CHECK-NEXT: vsseg7e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %vl)			tail call void @llvm.riscv.vsseg7.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg7_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv1f32:			; CHECK-LABEL: test_vsseg7_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)			declare void @llvm.riscv.vsseg8.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float* , i64)
	declare void @llvm.riscv.vsseg8.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vsseg8.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)

	define void @test_vsseg8_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl) {			define void @test_vsseg8_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv1f32:			; CHECK-LABEL: test_vsseg8_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg8e32.v v8, (a0)			; CHECK-NEXT: vsseg8e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %vl)			tail call void @llvm.riscv.vsseg8.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vsseg8_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv1f32:			; CHECK-LABEL: test_vsseg8_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
	; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half* , i64)			declare void @llvm.riscv.vsseg2.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64)

	define void @test_vsseg2_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg2_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv8f16:			; CHECK-LABEL: test_vsseg2_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0)			; CHECK-NEXT: vsseg2e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv8f16:			; CHECK-LABEL: test_vsseg2_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i64)			declare void @llvm.riscv.vsseg3.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64)

	define void @test_vsseg3_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg3_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv8f16:			; CHECK-LABEL: test_vsseg3_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0)			; CHECK-NEXT: vsseg3e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv8f16:			; CHECK-LABEL: test_vsseg3_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i64)			declare void @llvm.riscv.vsseg4.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64)

	define void @test_vsseg4_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg4_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv8f16:			; CHECK-LABEL: test_vsseg4_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0)			; CHECK-NEXT: vsseg4e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv8f16:			; CHECK-LABEL: test_vsseg4_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float* , i64)			declare void @llvm.riscv.vsseg2.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i1>, i64)

	define void @test_vsseg2_nxv8f32(<vscale x 8 x float> %val, float* %base, i64 %vl) {			define void @test_vsseg2_nxv8f32(<vscale x 8 x float> %val, float* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv8f32:			; CHECK-LABEL: test_vsseg2_nxv8f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0)			; CHECK-NEXT: vsseg2e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv8f32(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv8f32(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv8f32:			; CHECK-LABEL: test_vsseg2_mask_nxv8f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double* , i64)			declare void @llvm.riscv.vsseg2.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64)

	define void @test_vsseg2_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %vl) {			define void @test_vsseg2_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv2f64:			; CHECK-LABEL: test_vsseg2_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vsseg2e64.v v8, (a0)			; CHECK-NEXT: vsseg2e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv2f64:			; CHECK-LABEL: test_vsseg2_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i64)			declare void @llvm.riscv.vsseg3.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64)

	define void @test_vsseg3_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %vl) {			define void @test_vsseg3_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv2f64:			; CHECK-LABEL: test_vsseg3_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vsseg3e64.v v8, (a0)			; CHECK-NEXT: vsseg3e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv2f64:			; CHECK-LABEL: test_vsseg3_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vsseg3e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i64)			declare void @llvm.riscv.vsseg4.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64)

	define void @test_vsseg4_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %vl) {			define void @test_vsseg4_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv2f64:			; CHECK-LABEL: test_vsseg4_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vsseg4e64.v v8, (a0)			; CHECK-NEXT: vsseg4e64.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv2f64:			; CHECK-LABEL: test_vsseg4_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
	; CHECK-NEXT: vsseg4e64.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e64.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)			declare void @llvm.riscv.vsseg2.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)

	define void @test_vsseg2_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg2_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv4f16:			; CHECK-LABEL: test_vsseg2_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0)			; CHECK-NEXT: vsseg2e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv4f16:			; CHECK-LABEL: test_vsseg2_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)			declare void @llvm.riscv.vsseg3.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)

	define void @test_vsseg3_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg3_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv4f16:			; CHECK-LABEL: test_vsseg3_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0)			; CHECK-NEXT: vsseg3e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv4f16:			; CHECK-LABEL: test_vsseg3_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)			declare void @llvm.riscv.vsseg4.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)

	define void @test_vsseg4_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg4_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv4f16:			; CHECK-LABEL: test_vsseg4_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0)			; CHECK-NEXT: vsseg4e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv4f16:			; CHECK-LABEL: test_vsseg4_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)			declare void @llvm.riscv.vsseg5.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
	declare void @llvm.riscv.vsseg5.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg5.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)

	define void @test_vsseg5_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg5_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv4f16:			; CHECK-LABEL: test_vsseg5_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0)			; CHECK-NEXT: vsseg5e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg5.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg5_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv4f16:			; CHECK-LABEL: test_vsseg5_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)			declare void @llvm.riscv.vsseg6.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
	declare void @llvm.riscv.vsseg6.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg6.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)

	define void @test_vsseg6_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg6_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv4f16:			; CHECK-LABEL: test_vsseg6_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0)			; CHECK-NEXT: vsseg6e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg6.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg6_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv4f16:			; CHECK-LABEL: test_vsseg6_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)			declare void @llvm.riscv.vsseg7.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
	declare void @llvm.riscv.vsseg7.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg7.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)

	define void @test_vsseg7_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg7_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv4f16:			; CHECK-LABEL: test_vsseg7_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0)			; CHECK-NEXT: vsseg7e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg7.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg7_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv4f16:			; CHECK-LABEL: test_vsseg7_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)			declare void @llvm.riscv.vsseg8.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half* , i64)
	declare void @llvm.riscv.vsseg8.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg8.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)

	define void @test_vsseg8_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg8_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv4f16:			; CHECK-LABEL: test_vsseg8_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0)			; CHECK-NEXT: vsseg8e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg8.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg8_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv4f16:			; CHECK-LABEL: test_vsseg8_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)			declare void @llvm.riscv.vsseg2.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)

	define void @test_vsseg2_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg2_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv2f16:			; CHECK-LABEL: test_vsseg2_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0)			; CHECK-NEXT: vsseg2e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv2f16:			; CHECK-LABEL: test_vsseg2_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)			declare void @llvm.riscv.vsseg3.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)

	define void @test_vsseg3_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg3_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv2f16:			; CHECK-LABEL: test_vsseg3_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0)			; CHECK-NEXT: vsseg3e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv2f16:			; CHECK-LABEL: test_vsseg3_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)			declare void @llvm.riscv.vsseg4.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)

	define void @test_vsseg4_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg4_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv2f16:			; CHECK-LABEL: test_vsseg4_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0)			; CHECK-NEXT: vsseg4e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv2f16:			; CHECK-LABEL: test_vsseg4_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg5.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)			declare void @llvm.riscv.vsseg5.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
	declare void @llvm.riscv.vsseg5.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg5.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)

	define void @test_vsseg5_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg5_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_nxv2f16:			; CHECK-LABEL: test_vsseg5_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0)			; CHECK-NEXT: vsseg5e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg5.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg5_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg5_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg5_mask_nxv2f16:			; CHECK-LABEL: test_vsseg5_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg5.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg5.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg6.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)			declare void @llvm.riscv.vsseg6.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
	declare void @llvm.riscv.vsseg6.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg6.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)

	define void @test_vsseg6_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg6_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_nxv2f16:			; CHECK-LABEL: test_vsseg6_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0)			; CHECK-NEXT: vsseg6e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg6.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg6_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg6_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg6_mask_nxv2f16:			; CHECK-LABEL: test_vsseg6_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg6.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg6.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg7.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)			declare void @llvm.riscv.vsseg7.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
	declare void @llvm.riscv.vsseg7.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg7.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)

	define void @test_vsseg7_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg7_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_nxv2f16:			; CHECK-LABEL: test_vsseg7_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0)			; CHECK-NEXT: vsseg7e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg7.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg7_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg7_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg7_mask_nxv2f16:			; CHECK-LABEL: test_vsseg7_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg7.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg7.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg8.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)			declare void @llvm.riscv.vsseg8.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half* , i64)
	declare void @llvm.riscv.vsseg8.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vsseg8.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)

	define void @test_vsseg8_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl) {			define void @test_vsseg8_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_nxv2f16:			; CHECK-LABEL: test_vsseg8_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0)			; CHECK-NEXT: vsseg8e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %vl)			tail call void @llvm.riscv.vsseg8.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg8_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vsseg8_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg8_mask_nxv2f16:			; CHECK-LABEL: test_vsseg8_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
	; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg8.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg8.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg2.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float* , i64)			declare void @llvm.riscv.vsseg2.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64)

	define void @test_vsseg2_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %vl) {			define void @test_vsseg2_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_nxv4f32:			; CHECK-LABEL: test_vsseg2_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0)			; CHECK-NEXT: vsseg2e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i64 %vl)			tail call void @llvm.riscv.vsseg2.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg2_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg2_mask_nxv4f32:			; CHECK-LABEL: test_vsseg2_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg2.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg3.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i64)			declare void @llvm.riscv.vsseg3.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i64)
	declare void @llvm.riscv.vsseg3.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg3.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64)

	define void @test_vsseg3_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %vl) {			define void @test_vsseg3_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_nxv4f32:			; CHECK-LABEL: test_vsseg3_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0)			; CHECK-NEXT: vsseg3e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i64 %vl)			tail call void @llvm.riscv.vsseg3.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg3_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg3_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg3_mask_nxv4f32:			; CHECK-LABEL: test_vsseg3_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg3.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg3.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsseg4.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i64)			declare void @llvm.riscv.vsseg4.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float* , i64)
	declare void @llvm.riscv.vsseg4.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vsseg4.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64)

	define void @test_vsseg4_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %vl) {			define void @test_vsseg4_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_nxv4f32:			; CHECK-LABEL: test_vsseg4_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0)			; CHECK-NEXT: vsseg4e32.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i64 %vl)			tail call void @llvm.riscv.vsseg4.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vsseg4_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vsseg4_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vsseg4_mask_nxv4f32:			; CHECK-LABEL: test_vsseg4_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
	; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t			; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg4.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vsseg4.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \			; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \
	; RUN: -verify-machineinstrs < %s \| FileCheck %s			; RUN: -verify-machineinstrs < %s \| FileCheck %s

	declare void @llvm.riscv.vssseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i32, <vscale x 16 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i32, <vscale x 16 x i1>, i32)

	define void @test_vssseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv16i16:			; CHECK-LABEL: test_vssseg2_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv16i16:			; CHECK-LABEL: test_vssseg2_mask_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg2_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv1i8:			; CHECK-LABEL: test_vssseg2_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv1i8:			; CHECK-LABEL: test_vssseg2_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg3.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg3.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg3.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg3_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg3_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv1i8:			; CHECK-LABEL: test_vssseg3_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg3e8.v v8, (a0), a1			; CHECK-NEXT: vssseg3e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg3.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg3_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv1i8:			; CHECK-LABEL: test_vssseg3_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg4.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg4.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg4.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg4_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg4_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv1i8:			; CHECK-LABEL: test_vssseg4_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg4e8.v v8, (a0), a1			; CHECK-NEXT: vssseg4e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg4.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg4_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv1i8:			; CHECK-LABEL: test_vssseg4_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg5.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg5.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg5.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg5_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg5_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv1i8:			; CHECK-LABEL: test_vssseg5_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg5e8.v v8, (a0), a1			; CHECK-NEXT: vssseg5e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg5.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg5_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv1i8:			; CHECK-LABEL: test_vssseg5_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg6.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg6.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg6.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg6_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg6_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv1i8:			; CHECK-LABEL: test_vssseg6_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg6e8.v v8, (a0), a1			; CHECK-NEXT: vssseg6e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg6.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg6_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv1i8:			; CHECK-LABEL: test_vssseg6_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg7.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg7.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg7.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg7_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg7_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv1i8:			; CHECK-LABEL: test_vssseg7_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg7e8.v v8, (a0), a1			; CHECK-NEXT: vssseg7e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg7.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg7_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv1i8:			; CHECK-LABEL: test_vssseg7_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg8.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg8.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv1i8:			; CHECK-LABEL: test_vssseg8_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg8e8.v v8, (a0), a1			; CHECK-NEXT: vssseg8e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg8_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv1i8:			; CHECK-LABEL: test_vssseg8_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, <vscale x 16 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, <vscale x 16 x i1>, i32)

	define void @test_vssseg2_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv16i8:			; CHECK-LABEL: test_vssseg2_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv16i8:			; CHECK-LABEL: test_vssseg2_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg3.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg3.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, <vscale x 16 x i1>, i32)			declare void @llvm.riscv.vssseg3.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, <vscale x 16 x i1>, i32)

	define void @test_vssseg3_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg3_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv16i8:			; CHECK-LABEL: test_vssseg3_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vssseg3e8.v v8, (a0), a1			; CHECK-NEXT: vssseg3e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg3.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl) {			define void @test_vssseg3_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv16i8:			; CHECK-LABEL: test_vssseg3_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg4.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg4.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, <vscale x 16 x i1>, i32)			declare void @llvm.riscv.vssseg4.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i32, <vscale x 16 x i1>, i32)

	define void @test_vssseg4_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg4_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv16i8:			; CHECK-LABEL: test_vssseg4_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vssseg4e8.v v8, (a0), a1			; CHECK-NEXT: vssseg4e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg4.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl) {			define void @test_vssseg4_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv16i8:			; CHECK-LABEL: test_vssseg4_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg2_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv2i32:			; CHECK-LABEL: test_vssseg2_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv2i32:			; CHECK-LABEL: test_vssseg2_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)			declare void @llvm.riscv.vssseg3.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)
	declare void @llvm.riscv.vssseg3.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg3.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg3_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl) {			define void @test_vssseg3_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv2i32:			; CHECK-LABEL: test_vssseg3_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg3.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg3_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv2i32:			; CHECK-LABEL: test_vssseg3_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)			declare void @llvm.riscv.vssseg4.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)
	declare void @llvm.riscv.vssseg4.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg4.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg4_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl) {			define void @test_vssseg4_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv2i32:			; CHECK-LABEL: test_vssseg4_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg4.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg4_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv2i32:			; CHECK-LABEL: test_vssseg4_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)			declare void @llvm.riscv.vssseg5.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)
	declare void @llvm.riscv.vssseg5.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg5.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg5_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl) {			define void @test_vssseg5_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv2i32:			; CHECK-LABEL: test_vssseg5_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg5e32.v v8, (a0), a1			; CHECK-NEXT: vssseg5e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg5.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg5_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv2i32:			; CHECK-LABEL: test_vssseg5_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)			declare void @llvm.riscv.vssseg6.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)
	declare void @llvm.riscv.vssseg6.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg6.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg6_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl) {			define void @test_vssseg6_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv2i32:			; CHECK-LABEL: test_vssseg6_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg6e32.v v8, (a0), a1			; CHECK-NEXT: vssseg6e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg6.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg6_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv2i32:			; CHECK-LABEL: test_vssseg6_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)			declare void @llvm.riscv.vssseg7.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)
	declare void @llvm.riscv.vssseg7.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg7.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg7_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl) {			define void @test_vssseg7_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv2i32:			; CHECK-LABEL: test_vssseg7_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg7e32.v v8, (a0), a1			; CHECK-NEXT: vssseg7e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg7.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg7_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv2i32:			; CHECK-LABEL: test_vssseg7_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)			declare void @llvm.riscv.vssseg8.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, i32)
	declare void @llvm.riscv.vssseg8.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg8.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg8_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl) {			define void @test_vssseg8_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv2i32:			; CHECK-LABEL: test_vssseg8_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg8e32.v v8, (a0), a1			; CHECK-NEXT: vssseg8e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg8.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg8_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv2i32:			; CHECK-LABEL: test_vssseg8_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg2_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv4i16:			; CHECK-LABEL: test_vssseg2_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv4i16:			; CHECK-LABEL: test_vssseg2_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg3.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg3.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg3.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg3_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg3_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv4i16:			; CHECK-LABEL: test_vssseg3_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg3.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg3_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv4i16:			; CHECK-LABEL: test_vssseg3_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg4.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg4.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg4.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg4_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg4_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv4i16:			; CHECK-LABEL: test_vssseg4_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg4.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg4_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv4i16:			; CHECK-LABEL: test_vssseg4_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg5.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg5.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg5.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg5_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg5_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv4i16:			; CHECK-LABEL: test_vssseg5_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg5.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg5_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv4i16:			; CHECK-LABEL: test_vssseg5_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg6.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg6.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg6.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg6_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg6_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv4i16:			; CHECK-LABEL: test_vssseg6_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg6.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg6_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv4i16:			; CHECK-LABEL: test_vssseg6_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg7.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg7.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg7.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg7_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg7_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv4i16:			; CHECK-LABEL: test_vssseg7_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg7.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg7_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv4i16:			; CHECK-LABEL: test_vssseg7_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg8.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg8.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg8.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg8_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg8_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv4i16:			; CHECK-LABEL: test_vssseg8_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg8.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg8_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv4i16:			; CHECK-LABEL: test_vssseg8_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg2_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv1i32:			; CHECK-LABEL: test_vssseg2_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv1i32:			; CHECK-LABEL: test_vssseg2_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)			declare void @llvm.riscv.vssseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)
	declare void @llvm.riscv.vssseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg3_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl) {			define void @test_vssseg3_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv1i32:			; CHECK-LABEL: test_vssseg3_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg3.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg3_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv1i32:			; CHECK-LABEL: test_vssseg3_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)			declare void @llvm.riscv.vssseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)
	declare void @llvm.riscv.vssseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg4_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl) {			define void @test_vssseg4_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv1i32:			; CHECK-LABEL: test_vssseg4_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg4.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg4_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv1i32:			; CHECK-LABEL: test_vssseg4_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)			declare void @llvm.riscv.vssseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)
	declare void @llvm.riscv.vssseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg5_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl) {			define void @test_vssseg5_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv1i32:			; CHECK-LABEL: test_vssseg5_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg5e32.v v8, (a0), a1			; CHECK-NEXT: vssseg5e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg5.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg5_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv1i32:			; CHECK-LABEL: test_vssseg5_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)			declare void @llvm.riscv.vssseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)
	declare void @llvm.riscv.vssseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg6_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl) {			define void @test_vssseg6_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv1i32:			; CHECK-LABEL: test_vssseg6_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg6e32.v v8, (a0), a1			; CHECK-NEXT: vssseg6e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg6.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg6_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv1i32:			; CHECK-LABEL: test_vssseg6_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)			declare void @llvm.riscv.vssseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)
	declare void @llvm.riscv.vssseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg7_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl) {			define void @test_vssseg7_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv1i32:			; CHECK-LABEL: test_vssseg7_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg7e32.v v8, (a0), a1			; CHECK-NEXT: vssseg7e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg7.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg7_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv1i32:			; CHECK-LABEL: test_vssseg7_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)			declare void @llvm.riscv.vssseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, i32)
	declare void @llvm.riscv.vssseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg8_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl) {			define void @test_vssseg8_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv1i32:			; CHECK-LABEL: test_vssseg8_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg8e32.v v8, (a0), a1			; CHECK-NEXT: vssseg8e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg8.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg8_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv1i32:			; CHECK-LABEL: test_vssseg8_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, <vscale x 8 x i1>, i32)

	define void @test_vssseg2_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv8i16:			; CHECK-LABEL: test_vssseg2_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv8i16:			; CHECK-LABEL: test_vssseg2_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg3.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg3.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vssseg3.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, <vscale x 8 x i1>, i32)

	define void @test_vssseg3_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg3_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv8i16:			; CHECK-LABEL: test_vssseg3_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg3.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vssseg3_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv8i16:			; CHECK-LABEL: test_vssseg3_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg4.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg4.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vssseg4.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i32, <vscale x 8 x i1>, i32)

	define void @test_vssseg4_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg4_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv8i16:			; CHECK-LABEL: test_vssseg4_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg4.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vssseg4_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv8i16:			; CHECK-LABEL: test_vssseg4_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32)

	define void @test_vssseg2_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv8i8:			; CHECK-LABEL: test_vssseg2_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv8i8:			; CHECK-LABEL: test_vssseg2_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg3.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg3.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vssseg3.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32)

	define void @test_vssseg3_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg3_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv8i8:			; CHECK-LABEL: test_vssseg3_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg3e8.v v8, (a0), a1			; CHECK-NEXT: vssseg3e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg3.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vssseg3_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv8i8:			; CHECK-LABEL: test_vssseg3_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg4.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg4.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vssseg4.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32)

	define void @test_vssseg4_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg4_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv8i8:			; CHECK-LABEL: test_vssseg4_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg4e8.v v8, (a0), a1			; CHECK-NEXT: vssseg4e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg4.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vssseg4_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv8i8:			; CHECK-LABEL: test_vssseg4_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg5.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg5.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vssseg5.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32)

	define void @test_vssseg5_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg5_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv8i8:			; CHECK-LABEL: test_vssseg5_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg5e8.v v8, (a0), a1			; CHECK-NEXT: vssseg5e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg5.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vssseg5_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv8i8:			; CHECK-LABEL: test_vssseg5_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg6.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg6.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vssseg6.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32)

	define void @test_vssseg6_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg6_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv8i8:			; CHECK-LABEL: test_vssseg6_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg6e8.v v8, (a0), a1			; CHECK-NEXT: vssseg6e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg6.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vssseg6_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv8i8:			; CHECK-LABEL: test_vssseg6_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg7.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg7.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vssseg7.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32)

	define void @test_vssseg7_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg7_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv8i8:			; CHECK-LABEL: test_vssseg7_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg7e8.v v8, (a0), a1			; CHECK-NEXT: vssseg7e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg7.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vssseg7_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv8i8:			; CHECK-LABEL: test_vssseg7_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg8.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vssseg8.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i32, <vscale x 8 x i1>, i32)

	define void @test_vssseg8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv8i8:			; CHECK-LABEL: test_vssseg8_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg8e8.v v8, (a0), a1			; CHECK-NEXT: vssseg8e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vssseg8_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv8i8:			; CHECK-LABEL: test_vssseg8_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, i32, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, i32, <vscale x 8 x i1>, i32)

	define void @test_vssseg2_nxv8i32(<vscale x 8 x i32> %val, i32* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv8i32(<vscale x 8 x i32> %val, i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv8i32:			; CHECK-LABEL: test_vssseg2_nxv8i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv8i32(<vscale x 8 x i32> %val, i32* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv8i32(<vscale x 8 x i32> %val, i32* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv8i32:			; CHECK-LABEL: test_vssseg2_mask_nxv8i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg2_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv4i8:			; CHECK-LABEL: test_vssseg2_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv4i8:			; CHECK-LABEL: test_vssseg2_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg3.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg3.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg3.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg3_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg3_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv4i8:			; CHECK-LABEL: test_vssseg3_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg3e8.v v8, (a0), a1			; CHECK-NEXT: vssseg3e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg3.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg3_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv4i8:			; CHECK-LABEL: test_vssseg3_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg4.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg4.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg4.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg4_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg4_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv4i8:			; CHECK-LABEL: test_vssseg4_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg4e8.v v8, (a0), a1			; CHECK-NEXT: vssseg4e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg4.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg4_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv4i8:			; CHECK-LABEL: test_vssseg4_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg5.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg5.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg5.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg5_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg5_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv4i8:			; CHECK-LABEL: test_vssseg5_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg5e8.v v8, (a0), a1			; CHECK-NEXT: vssseg5e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg5.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg5_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv4i8:			; CHECK-LABEL: test_vssseg5_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg6.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg6.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg6.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg6_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg6_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv4i8:			; CHECK-LABEL: test_vssseg6_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg6e8.v v8, (a0), a1			; CHECK-NEXT: vssseg6e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg6.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg6_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv4i8:			; CHECK-LABEL: test_vssseg6_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg7.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg7.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg7.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg7_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg7_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv4i8:			; CHECK-LABEL: test_vssseg7_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg7e8.v v8, (a0), a1			; CHECK-NEXT: vssseg7e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg7.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg7_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv4i8:			; CHECK-LABEL: test_vssseg7_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg8.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg8.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv4i8:			; CHECK-LABEL: test_vssseg8_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg8e8.v v8, (a0), a1			; CHECK-NEXT: vssseg8e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg8_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv4i8:			; CHECK-LABEL: test_vssseg8_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg2_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv1i16:			; CHECK-LABEL: test_vssseg2_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv1i16:			; CHECK-LABEL: test_vssseg2_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg3.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg3.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg3.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg3_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg3_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv1i16:			; CHECK-LABEL: test_vssseg3_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg3.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg3_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv1i16:			; CHECK-LABEL: test_vssseg3_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg4.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg4.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg4.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg4_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg4_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv1i16:			; CHECK-LABEL: test_vssseg4_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg4.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg4_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv1i16:			; CHECK-LABEL: test_vssseg4_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg5.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg5.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg5.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg5_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg5_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv1i16:			; CHECK-LABEL: test_vssseg5_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg5.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg5_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv1i16:			; CHECK-LABEL: test_vssseg5_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg6.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg6.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg6.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg6_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg6_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv1i16:			; CHECK-LABEL: test_vssseg6_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg6.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg6_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv1i16:			; CHECK-LABEL: test_vssseg6_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg7.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg7.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg7.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg7_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg7_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv1i16:			; CHECK-LABEL: test_vssseg7_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg7.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg7_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv1i16:			; CHECK-LABEL: test_vssseg7_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg8.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg8.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg8.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg8_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg8_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv1i16:			; CHECK-LABEL: test_vssseg8_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg8.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg8_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv1i16:			; CHECK-LABEL: test_vssseg8_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, i32, <vscale x 32 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, i32, <vscale x 32 x i1>, i32)

	define void @test_vssseg2_nxv32i8(<vscale x 32 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv32i8(<vscale x 32 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv32i8:			; CHECK-LABEL: test_vssseg2_nxv32i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv32i8(<vscale x 32 x i8> %val, i8* %base, i32 %offset, <vscale x 32 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv32i8(<vscale x 32 x i8> %val, i8* %base, i32 %offset, <vscale x 32 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv32i8:			; CHECK-LABEL: test_vssseg2_mask_nxv32i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, i32 %offset, <vscale x 32 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, i32 %offset, <vscale x 32 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg2_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv2i8:			; CHECK-LABEL: test_vssseg2_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv2i8:			; CHECK-LABEL: test_vssseg2_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg3.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg3.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg3.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg3_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg3_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv2i8:			; CHECK-LABEL: test_vssseg3_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg3e8.v v8, (a0), a1			; CHECK-NEXT: vssseg3e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg3.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg3_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv2i8:			; CHECK-LABEL: test_vssseg3_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg4.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg4.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg4.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg4_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg4_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv2i8:			; CHECK-LABEL: test_vssseg4_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg4e8.v v8, (a0), a1			; CHECK-NEXT: vssseg4e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg4.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg4_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv2i8:			; CHECK-LABEL: test_vssseg4_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg5.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg5.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg5.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg5_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg5_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv2i8:			; CHECK-LABEL: test_vssseg5_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg5e8.v v8, (a0), a1			; CHECK-NEXT: vssseg5e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg5.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg5_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv2i8:			; CHECK-LABEL: test_vssseg5_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg6.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg6.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg6.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg6_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg6_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv2i8:			; CHECK-LABEL: test_vssseg6_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg6e8.v v8, (a0), a1			; CHECK-NEXT: vssseg6e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg6.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg6_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv2i8:			; CHECK-LABEL: test_vssseg6_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg7.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg7.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg7.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg7_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg7_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv2i8:			; CHECK-LABEL: test_vssseg7_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg7e8.v v8, (a0), a1			; CHECK-NEXT: vssseg7e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg7.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg7_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv2i8:			; CHECK-LABEL: test_vssseg7_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)			declare void @llvm.riscv.vssseg8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, i32)
	declare void @llvm.riscv.vssseg8.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg8.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl) {			define void @test_vssseg8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv2i8:			; CHECK-LABEL: test_vssseg8_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg8e8.v v8, (a0), a1			; CHECK-NEXT: vssseg8e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg8_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv2i8:			; CHECK-LABEL: test_vssseg8_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg2_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv2i16:			; CHECK-LABEL: test_vssseg2_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv2i16:			; CHECK-LABEL: test_vssseg2_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg3.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg3.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg3.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg3_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg3_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv2i16:			; CHECK-LABEL: test_vssseg3_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg3.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg3_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv2i16:			; CHECK-LABEL: test_vssseg3_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg4.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg4.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg4.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg4_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg4_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv2i16:			; CHECK-LABEL: test_vssseg4_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg4.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg4_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv2i16:			; CHECK-LABEL: test_vssseg4_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg5.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg5.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg5.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg5_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg5_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv2i16:			; CHECK-LABEL: test_vssseg5_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg5.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg5_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv2i16:			; CHECK-LABEL: test_vssseg5_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg6.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg6.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg6.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg6_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg6_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv2i16:			; CHECK-LABEL: test_vssseg6_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg6.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg6_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv2i16:			; CHECK-LABEL: test_vssseg6_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg7.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg7.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg7.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg7_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg7_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv2i16:			; CHECK-LABEL: test_vssseg7_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg7.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg7_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv2i16:			; CHECK-LABEL: test_vssseg7_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)			declare void @llvm.riscv.vssseg8.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, i32)
	declare void @llvm.riscv.vssseg8.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg8.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg8_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl) {			define void @test_vssseg8_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv2i16:			; CHECK-LABEL: test_vssseg8_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg8.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg8_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv2i16:			; CHECK-LABEL: test_vssseg8_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg2_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv4i32:			; CHECK-LABEL: test_vssseg2_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv4i32:			; CHECK-LABEL: test_vssseg2_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, i32)			declare void @llvm.riscv.vssseg3.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, i32)
	declare void @llvm.riscv.vssseg3.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg3.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg3_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %offset, i32 %vl) {			define void @test_vssseg3_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv4i32:			; CHECK-LABEL: test_vssseg3_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg3.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg3_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv4i32:			; CHECK-LABEL: test_vssseg3_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, i32)			declare void @llvm.riscv.vssseg4.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, i32)
	declare void @llvm.riscv.vssseg4.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg4.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg4_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %offset, i32 %vl) {			define void @test_vssseg4_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv4i32:			; CHECK-LABEL: test_vssseg4_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg4.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg4_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv4i32:			; CHECK-LABEL: test_vssseg4_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, i32, <vscale x 16 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, i32, <vscale x 16 x i1>, i32)

	define void @test_vssseg2_nxv16f16(<vscale x 16 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv16f16(<vscale x 16 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv16f16:			; CHECK-LABEL: test_vssseg2_nxv16f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv16f16(<vscale x 16 x half> %val, half* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv16f16(<vscale x 16 x half> %val, half* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv16f16:			; CHECK-LABEL: test_vssseg2_mask_nxv16f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, i32 %offset, <vscale x 16 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg2_nxv4f64(<vscale x 4 x double> %val, double* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv4f64(<vscale x 4 x double> %val, double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv4f64:			; CHECK-LABEL: test_vssseg2_nxv4f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
	; CHECK-NEXT: vssseg2e64.v v8, (a0), a1			; CHECK-NEXT: vssseg2e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv4f64(<vscale x 4 x double> %val, double* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv4f64(<vscale x 4 x double> %val, double* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv4f64:			; CHECK-LABEL: test_vssseg2_mask_nxv4f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
	; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg2_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv1f64:			; CHECK-LABEL: test_vssseg2_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg2e64.v v8, (a0), a1			; CHECK-NEXT: vssseg2e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv1f64:			; CHECK-LABEL: test_vssseg2_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)			declare void @llvm.riscv.vssseg3.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)
	declare void @llvm.riscv.vssseg3.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg3.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg3_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl) {			define void @test_vssseg3_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv1f64:			; CHECK-LABEL: test_vssseg3_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg3e64.v v8, (a0), a1			; CHECK-NEXT: vssseg3e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg3.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg3_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv1f64:			; CHECK-LABEL: test_vssseg3_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg3e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)			declare void @llvm.riscv.vssseg4.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)
	declare void @llvm.riscv.vssseg4.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg4.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg4_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl) {			define void @test_vssseg4_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv1f64:			; CHECK-LABEL: test_vssseg4_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg4e64.v v8, (a0), a1			; CHECK-NEXT: vssseg4e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg4.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg4_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv1f64:			; CHECK-LABEL: test_vssseg4_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg4e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)			declare void @llvm.riscv.vssseg5.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)
	declare void @llvm.riscv.vssseg5.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg5.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg5_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl) {			define void @test_vssseg5_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv1f64:			; CHECK-LABEL: test_vssseg5_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg5e64.v v8, (a0), a1			; CHECK-NEXT: vssseg5e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg5.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg5_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv1f64:			; CHECK-LABEL: test_vssseg5_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg5e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)			declare void @llvm.riscv.vssseg6.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)
	declare void @llvm.riscv.vssseg6.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg6.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg6_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl) {			define void @test_vssseg6_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv1f64:			; CHECK-LABEL: test_vssseg6_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg6e64.v v8, (a0), a1			; CHECK-NEXT: vssseg6e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg6.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg6_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv1f64:			; CHECK-LABEL: test_vssseg6_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg6e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)			declare void @llvm.riscv.vssseg7.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)
	declare void @llvm.riscv.vssseg7.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg7.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg7_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl) {			define void @test_vssseg7_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv1f64:			; CHECK-LABEL: test_vssseg7_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg7e64.v v8, (a0), a1			; CHECK-NEXT: vssseg7e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg7.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg7_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv1f64:			; CHECK-LABEL: test_vssseg7_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg7e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)			declare void @llvm.riscv.vssseg8.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, i32)
	declare void @llvm.riscv.vssseg8.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg8.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg8_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl) {			define void @test_vssseg8_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv1f64:			; CHECK-LABEL: test_vssseg8_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg8e64.v v8, (a0), a1			; CHECK-NEXT: vssseg8e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg8.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg8_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv1f64:			; CHECK-LABEL: test_vssseg8_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg8e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg2_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv2f32:			; CHECK-LABEL: test_vssseg2_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv2f32:			; CHECK-LABEL: test_vssseg2_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)			declare void @llvm.riscv.vssseg3.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)
	declare void @llvm.riscv.vssseg3.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg3.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg3_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl) {			define void @test_vssseg3_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv2f32:			; CHECK-LABEL: test_vssseg3_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg3.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg3_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv2f32:			; CHECK-LABEL: test_vssseg3_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)			declare void @llvm.riscv.vssseg4.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)
	declare void @llvm.riscv.vssseg4.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg4.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg4_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl) {			define void @test_vssseg4_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv2f32:			; CHECK-LABEL: test_vssseg4_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg4.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg4_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv2f32:			; CHECK-LABEL: test_vssseg4_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)			declare void @llvm.riscv.vssseg5.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)
	declare void @llvm.riscv.vssseg5.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg5.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg5_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl) {			define void @test_vssseg5_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv2f32:			; CHECK-LABEL: test_vssseg5_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg5e32.v v8, (a0), a1			; CHECK-NEXT: vssseg5e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg5.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg5_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv2f32:			; CHECK-LABEL: test_vssseg5_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)			declare void @llvm.riscv.vssseg6.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)
	declare void @llvm.riscv.vssseg6.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg6.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg6_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl) {			define void @test_vssseg6_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv2f32:			; CHECK-LABEL: test_vssseg6_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg6e32.v v8, (a0), a1			; CHECK-NEXT: vssseg6e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg6.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg6_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv2f32:			; CHECK-LABEL: test_vssseg6_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)			declare void @llvm.riscv.vssseg7.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)
	declare void @llvm.riscv.vssseg7.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg7.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg7_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl) {			define void @test_vssseg7_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv2f32:			; CHECK-LABEL: test_vssseg7_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg7e32.v v8, (a0), a1			; CHECK-NEXT: vssseg7e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg7.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg7_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv2f32:			; CHECK-LABEL: test_vssseg7_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)			declare void @llvm.riscv.vssseg8.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, i32)
	declare void @llvm.riscv.vssseg8.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg8.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg8_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl) {			define void @test_vssseg8_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv2f32:			; CHECK-LABEL: test_vssseg8_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg8e32.v v8, (a0), a1			; CHECK-NEXT: vssseg8e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg8.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg8_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv2f32:			; CHECK-LABEL: test_vssseg8_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg2_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv1f16:			; CHECK-LABEL: test_vssseg2_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv1f16:			; CHECK-LABEL: test_vssseg2_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg3.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg3.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg3.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg3_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg3_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv1f16:			; CHECK-LABEL: test_vssseg3_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg3.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg3_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv1f16:			; CHECK-LABEL: test_vssseg3_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg4.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg4.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg4.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg4_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg4_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv1f16:			; CHECK-LABEL: test_vssseg4_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg4.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg4_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv1f16:			; CHECK-LABEL: test_vssseg4_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg5.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg5.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg5.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg5_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg5_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv1f16:			; CHECK-LABEL: test_vssseg5_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg5.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg5_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv1f16:			; CHECK-LABEL: test_vssseg5_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg6.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg6.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg6.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg6_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg6_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv1f16:			; CHECK-LABEL: test_vssseg6_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg6.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg6_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv1f16:			; CHECK-LABEL: test_vssseg6_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg7.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg7.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg7.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg7_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg7_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv1f16:			; CHECK-LABEL: test_vssseg7_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg7.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg7_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv1f16:			; CHECK-LABEL: test_vssseg7_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg8.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg8.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg8.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg8_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg8_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv1f16:			; CHECK-LABEL: test_vssseg8_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg8.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg8_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv1f16:			; CHECK-LABEL: test_vssseg8_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg2_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv1f32:			; CHECK-LABEL: test_vssseg2_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv1f32:			; CHECK-LABEL: test_vssseg2_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)			declare void @llvm.riscv.vssseg3.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)
	declare void @llvm.riscv.vssseg3.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg3.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg3_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl) {			define void @test_vssseg3_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv1f32:			; CHECK-LABEL: test_vssseg3_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg3.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg3_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv1f32:			; CHECK-LABEL: test_vssseg3_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)			declare void @llvm.riscv.vssseg4.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)
	declare void @llvm.riscv.vssseg4.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg4.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg4_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl) {			define void @test_vssseg4_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv1f32:			; CHECK-LABEL: test_vssseg4_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg4.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg4_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv1f32:			; CHECK-LABEL: test_vssseg4_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)			declare void @llvm.riscv.vssseg5.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)
	declare void @llvm.riscv.vssseg5.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg5.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg5_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl) {			define void @test_vssseg5_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv1f32:			; CHECK-LABEL: test_vssseg5_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg5e32.v v8, (a0), a1			; CHECK-NEXT: vssseg5e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg5.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg5_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv1f32:			; CHECK-LABEL: test_vssseg5_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)			declare void @llvm.riscv.vssseg6.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)
	declare void @llvm.riscv.vssseg6.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg6.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg6_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl) {			define void @test_vssseg6_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv1f32:			; CHECK-LABEL: test_vssseg6_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg6e32.v v8, (a0), a1			; CHECK-NEXT: vssseg6e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg6.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg6_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv1f32:			; CHECK-LABEL: test_vssseg6_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)			declare void @llvm.riscv.vssseg7.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)
	declare void @llvm.riscv.vssseg7.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg7.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg7_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl) {			define void @test_vssseg7_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv1f32:			; CHECK-LABEL: test_vssseg7_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg7e32.v v8, (a0), a1			; CHECK-NEXT: vssseg7e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg7.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg7_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv1f32:			; CHECK-LABEL: test_vssseg7_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)			declare void @llvm.riscv.vssseg8.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, i32)
	declare void @llvm.riscv.vssseg8.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32)			declare void @llvm.riscv.vssseg8.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i32, <vscale x 1 x i1>, i32)

	define void @test_vssseg8_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl) {			define void @test_vssseg8_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv1f32:			; CHECK-LABEL: test_vssseg8_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg8e32.v v8, (a0), a1			; CHECK-NEXT: vssseg8e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg8.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {			define void @test_vssseg8_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv1f32:			; CHECK-LABEL: test_vssseg8_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i32 %offset, <vscale x 1 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, <vscale x 8 x i1>, i32)

	define void @test_vssseg2_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv8f16:			; CHECK-LABEL: test_vssseg2_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv8f16:			; CHECK-LABEL: test_vssseg2_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg3.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg3.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vssseg3.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, <vscale x 8 x i1>, i32)

	define void @test_vssseg3_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg3_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv8f16:			; CHECK-LABEL: test_vssseg3_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg3.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vssseg3_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv8f16:			; CHECK-LABEL: test_vssseg3_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg4.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg4.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vssseg4.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i32, <vscale x 8 x i1>, i32)

	define void @test_vssseg4_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg4_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv8f16:			; CHECK-LABEL: test_vssseg4_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg4.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vssseg4_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv8f16:			; CHECK-LABEL: test_vssseg4_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, i32, <vscale x 8 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, i32, <vscale x 8 x i1>, i32)

	define void @test_vssseg2_nxv8f32(<vscale x 8 x float> %val, float* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv8f32(<vscale x 8 x float> %val, float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv8f32:			; CHECK-LABEL: test_vssseg2_nxv8f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv8f32(<vscale x 8 x float> %val, float* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv8f32(<vscale x 8 x float> %val, float* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv8f32:			; CHECK-LABEL: test_vssseg2_mask_nxv8f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, i32 %offset, <vscale x 8 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg2_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv2f64:			; CHECK-LABEL: test_vssseg2_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vssseg2e64.v v8, (a0), a1			; CHECK-NEXT: vssseg2e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv2f64:			; CHECK-LABEL: test_vssseg2_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, i32)			declare void @llvm.riscv.vssseg3.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, i32)
	declare void @llvm.riscv.vssseg3.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg3.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg3_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %offset, i32 %vl) {			define void @test_vssseg3_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv2f64:			; CHECK-LABEL: test_vssseg3_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vssseg3e64.v v8, (a0), a1			; CHECK-NEXT: vssseg3e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg3.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg3_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv2f64:			; CHECK-LABEL: test_vssseg3_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vssseg3e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, i32)			declare void @llvm.riscv.vssseg4.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, i32)
	declare void @llvm.riscv.vssseg4.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg4.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg4_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %offset, i32 %vl) {			define void @test_vssseg4_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv2f64:			; CHECK-LABEL: test_vssseg4_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vssseg4e64.v v8, (a0), a1			; CHECK-NEXT: vssseg4e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg4.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg4_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv2f64:			; CHECK-LABEL: test_vssseg4_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vssseg4e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg2_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv4f16:			; CHECK-LABEL: test_vssseg2_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv4f16:			; CHECK-LABEL: test_vssseg2_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg3.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg3.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg3.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg3_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg3_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv4f16:			; CHECK-LABEL: test_vssseg3_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg3.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg3_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv4f16:			; CHECK-LABEL: test_vssseg3_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg4.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg4.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg4.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg4_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg4_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv4f16:			; CHECK-LABEL: test_vssseg4_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg4.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg4_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv4f16:			; CHECK-LABEL: test_vssseg4_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg5.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg5.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg5.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg5_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg5_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv4f16:			; CHECK-LABEL: test_vssseg5_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg5.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg5_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv4f16:			; CHECK-LABEL: test_vssseg5_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg6.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg6.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg6.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg6_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg6_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv4f16:			; CHECK-LABEL: test_vssseg6_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg6.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg6_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv4f16:			; CHECK-LABEL: test_vssseg6_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg7.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg7.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg7.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg7_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg7_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv4f16:			; CHECK-LABEL: test_vssseg7_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg7.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg7_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv4f16:			; CHECK-LABEL: test_vssseg7_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg8.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg8.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg8.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg8_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg8_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv4f16:			; CHECK-LABEL: test_vssseg8_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg8.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg8_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv4f16:			; CHECK-LABEL: test_vssseg8_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg2_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv2f16:			; CHECK-LABEL: test_vssseg2_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv2f16:			; CHECK-LABEL: test_vssseg2_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg3.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg3.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg3.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg3_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg3_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv2f16:			; CHECK-LABEL: test_vssseg3_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg3.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg3_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv2f16:			; CHECK-LABEL: test_vssseg3_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg4.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg4.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg4.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg4_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg4_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv2f16:			; CHECK-LABEL: test_vssseg4_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg4.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg4_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv2f16:			; CHECK-LABEL: test_vssseg4_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg5.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg5.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg5.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg5_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg5_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv2f16:			; CHECK-LABEL: test_vssseg5_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg5.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg5_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv2f16:			; CHECK-LABEL: test_vssseg5_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg6.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg6.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg6.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg6_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg6_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv2f16:			; CHECK-LABEL: test_vssseg6_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg6.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg6_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv2f16:			; CHECK-LABEL: test_vssseg6_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg7.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg7.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg7.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg7_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg7_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv2f16:			; CHECK-LABEL: test_vssseg7_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg7.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg7_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv2f16:			; CHECK-LABEL: test_vssseg7_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)			declare void @llvm.riscv.vssseg8.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, i32)
	declare void @llvm.riscv.vssseg8.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32)			declare void @llvm.riscv.vssseg8.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i32, <vscale x 2 x i1>, i32)

	define void @test_vssseg8_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl) {			define void @test_vssseg8_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv2f16:			; CHECK-LABEL: test_vssseg8_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg8.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {			define void @test_vssseg8_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv2f16:			; CHECK-LABEL: test_vssseg8_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i32 %offset, <vscale x 2 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, i32)			declare void @llvm.riscv.vssseg2.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, i32)
	declare void @llvm.riscv.vssseg2.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg2.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg2_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %offset, i32 %vl) {			define void @test_vssseg2_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv4f32:			; CHECK-LABEL: test_vssseg2_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg2.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg2_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv4f32:			; CHECK-LABEL: test_vssseg2_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, i32)			declare void @llvm.riscv.vssseg3.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, i32)
	declare void @llvm.riscv.vssseg3.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg3.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg3_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %offset, i32 %vl) {			define void @test_vssseg3_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv4f32:			; CHECK-LABEL: test_vssseg3_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg3.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg3_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv4f32:			; CHECK-LABEL: test_vssseg3_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, i32)			declare void @llvm.riscv.vssseg4.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, i32)
	declare void @llvm.riscv.vssseg4.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, <vscale x 4 x i1>, i32)			declare void @llvm.riscv.vssseg4.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i32, <vscale x 4 x i1>, i32)

	define void @test_vssseg4_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %offset, i32 %vl) {			define void @test_vssseg4_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %offset, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv4f32:			; CHECK-LABEL: test_vssseg4_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i32 %offset, i32 %vl)			tail call void @llvm.riscv.vssseg4.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i32 %offset, i32 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {			define void @test_vssseg4_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv4f32:			; CHECK-LABEL: test_vssseg4_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i32 %offset, <vscale x 4 x i1> %mask, i32 %vl)
	ret void			ret void
	}			}

llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
	; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \			; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+experimental-zvfh \
	; RUN: -verify-machineinstrs < %s \| FileCheck %s			; RUN: -verify-machineinstrs < %s \| FileCheck %s

	declare void @llvm.riscv.vssseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, <vscale x 16 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, <vscale x 16 x i1>, i64)

	define void @test_vssseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv16i16:			; CHECK-LABEL: test_vssseg2_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv16i16:			; CHECK-LABEL: test_vssseg2_mask_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg2_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv4i32:			; CHECK-LABEL: test_vssseg2_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv4i32:			; CHECK-LABEL: test_vssseg2_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg3_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv4i32:			; CHECK-LABEL: test_vssseg3_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv4i32:			; CHECK-LABEL: test_vssseg3_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg4_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv4i32:			; CHECK-LABEL: test_vssseg4_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv4i32:			; CHECK-LABEL: test_vssseg4_mask_nxv4i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, <vscale x 16 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, <vscale x 16 x i1>, i64)

	define void @test_vssseg2_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv16i8:			; CHECK-LABEL: test_vssseg2_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv16i8:			; CHECK-LABEL: test_vssseg2_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, <vscale x 16 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, <vscale x 16 x i1>, i64)

	define void @test_vssseg3_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv16i8:			; CHECK-LABEL: test_vssseg3_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vssseg3e8.v v8, (a0), a1			; CHECK-NEXT: vssseg3e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv16i8:			; CHECK-LABEL: test_vssseg3_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, <vscale x 16 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, i64, <vscale x 16 x i1>, i64)

	define void @test_vssseg4_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv16i8:			; CHECK-LABEL: test_vssseg4_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vssseg4e8.v v8, (a0), a1			; CHECK-NEXT: vssseg4e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv16i8:			; CHECK-LABEL: test_vssseg4_mask_nxv16i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
	; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg2_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv1i64:			; CHECK-LABEL: test_vssseg2_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg2e64.v v8, (a0), a1			; CHECK-NEXT: vssseg2e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv1i64:			; CHECK-LABEL: test_vssseg2_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg3_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv1i64:			; CHECK-LABEL: test_vssseg3_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg3e64.v v8, (a0), a1			; CHECK-NEXT: vssseg3e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv1i64:			; CHECK-LABEL: test_vssseg3_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg3e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg4_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv1i64:			; CHECK-LABEL: test_vssseg4_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg4e64.v v8, (a0), a1			; CHECK-NEXT: vssseg4e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv1i64:			; CHECK-LABEL: test_vssseg4_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg4e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)			declare void @llvm.riscv.vssseg5.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)
	declare void @llvm.riscv.vssseg5.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg5.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg5_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl) {			define void @test_vssseg5_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv1i64:			; CHECK-LABEL: test_vssseg5_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg5e64.v v8, (a0), a1			; CHECK-NEXT: vssseg5e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg5.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg5_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv1i64:			; CHECK-LABEL: test_vssseg5_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg5e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)			declare void @llvm.riscv.vssseg6.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)
	declare void @llvm.riscv.vssseg6.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg6.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg6_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl) {			define void @test_vssseg6_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv1i64:			; CHECK-LABEL: test_vssseg6_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg6e64.v v8, (a0), a1			; CHECK-NEXT: vssseg6e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg6.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg6_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv1i64:			; CHECK-LABEL: test_vssseg6_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg6e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)			declare void @llvm.riscv.vssseg7.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)
	declare void @llvm.riscv.vssseg7.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg7.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg7_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl) {			define void @test_vssseg7_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv1i64:			; CHECK-LABEL: test_vssseg7_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg7e64.v v8, (a0), a1			; CHECK-NEXT: vssseg7e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg7.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg7_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv1i64:			; CHECK-LABEL: test_vssseg7_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg7e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)			declare void @llvm.riscv.vssseg8.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, i64)
	declare void @llvm.riscv.vssseg8.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg8.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg8_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl) {			define void @test_vssseg8_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv1i64:			; CHECK-LABEL: test_vssseg8_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg8e64.v v8, (a0), a1			; CHECK-NEXT: vssseg8e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg8.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg8_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv1i64:			; CHECK-LABEL: test_vssseg8_mask_nxv1i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg8e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg2_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv1i32:			; CHECK-LABEL: test_vssseg2_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv1i32:			; CHECK-LABEL: test_vssseg2_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg3_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv1i32:			; CHECK-LABEL: test_vssseg3_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv1i32:			; CHECK-LABEL: test_vssseg3_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg4_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv1i32:			; CHECK-LABEL: test_vssseg4_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv1i32:			; CHECK-LABEL: test_vssseg4_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)			declare void @llvm.riscv.vssseg5.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)
	declare void @llvm.riscv.vssseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg5.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg5_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl) {			define void @test_vssseg5_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv1i32:			; CHECK-LABEL: test_vssseg5_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg5e32.v v8, (a0), a1			; CHECK-NEXT: vssseg5e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg5.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg5_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv1i32:			; CHECK-LABEL: test_vssseg5_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)			declare void @llvm.riscv.vssseg6.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)
	declare void @llvm.riscv.vssseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg6.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg6_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl) {			define void @test_vssseg6_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv1i32:			; CHECK-LABEL: test_vssseg6_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg6e32.v v8, (a0), a1			; CHECK-NEXT: vssseg6e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg6.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg6_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv1i32:			; CHECK-LABEL: test_vssseg6_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)			declare void @llvm.riscv.vssseg7.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)
	declare void @llvm.riscv.vssseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg7.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg7_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl) {			define void @test_vssseg7_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv1i32:			; CHECK-LABEL: test_vssseg7_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg7e32.v v8, (a0), a1			; CHECK-NEXT: vssseg7e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg7.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg7_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv1i32:			; CHECK-LABEL: test_vssseg7_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)			declare void @llvm.riscv.vssseg8.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, i64)
	declare void @llvm.riscv.vssseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg8.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg8_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl) {			define void @test_vssseg8_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv1i32:			; CHECK-LABEL: test_vssseg8_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg8e32.v v8, (a0), a1			; CHECK-NEXT: vssseg8e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg8.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg8_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv1i32:			; CHECK-LABEL: test_vssseg8_mask_nxv1i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, <vscale x 8 x i1>, i64)

	define void @test_vssseg2_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv8i16:			; CHECK-LABEL: test_vssseg2_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv8i16:			; CHECK-LABEL: test_vssseg2_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, <vscale x 8 x i1>, i64)

	define void @test_vssseg3_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv8i16:			; CHECK-LABEL: test_vssseg3_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv8i16:			; CHECK-LABEL: test_vssseg3_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, i64, <vscale x 8 x i1>, i64)

	define void @test_vssseg4_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv8i16:			; CHECK-LABEL: test_vssseg4_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv8i16:			; CHECK-LABEL: test_vssseg4_mask_nxv8i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg2_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv4i8:			; CHECK-LABEL: test_vssseg2_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv4i8:			; CHECK-LABEL: test_vssseg2_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg3_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv4i8:			; CHECK-LABEL: test_vssseg3_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg3e8.v v8, (a0), a1			; CHECK-NEXT: vssseg3e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv4i8:			; CHECK-LABEL: test_vssseg3_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg4_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv4i8:			; CHECK-LABEL: test_vssseg4_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg4e8.v v8, (a0), a1			; CHECK-NEXT: vssseg4e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv4i8:			; CHECK-LABEL: test_vssseg4_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg5.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg5.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg5.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg5_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg5_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv4i8:			; CHECK-LABEL: test_vssseg5_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg5e8.v v8, (a0), a1			; CHECK-NEXT: vssseg5e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg5.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg5_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv4i8:			; CHECK-LABEL: test_vssseg5_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg6.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg6.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg6.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg6_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg6_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv4i8:			; CHECK-LABEL: test_vssseg6_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg6e8.v v8, (a0), a1			; CHECK-NEXT: vssseg6e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg6.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg6_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv4i8:			; CHECK-LABEL: test_vssseg6_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg7.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg7.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg7.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg7_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg7_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv4i8:			; CHECK-LABEL: test_vssseg7_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg7e8.v v8, (a0), a1			; CHECK-NEXT: vssseg7e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg7.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg7_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv4i8:			; CHECK-LABEL: test_vssseg7_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg8.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg8.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv4i8:			; CHECK-LABEL: test_vssseg8_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg8e8.v v8, (a0), a1			; CHECK-NEXT: vssseg8e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg8_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv4i8:			; CHECK-LABEL: test_vssseg8_mask_nxv4i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
	; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg2_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv1i16:			; CHECK-LABEL: test_vssseg2_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv1i16:			; CHECK-LABEL: test_vssseg2_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg3_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv1i16:			; CHECK-LABEL: test_vssseg3_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv1i16:			; CHECK-LABEL: test_vssseg3_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg4_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv1i16:			; CHECK-LABEL: test_vssseg4_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv1i16:			; CHECK-LABEL: test_vssseg4_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg5.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg5.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg5.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg5_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg5_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv1i16:			; CHECK-LABEL: test_vssseg5_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg5.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg5_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv1i16:			; CHECK-LABEL: test_vssseg5_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg6.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg6.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg6.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg6_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg6_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv1i16:			; CHECK-LABEL: test_vssseg6_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg6.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg6_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv1i16:			; CHECK-LABEL: test_vssseg6_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg7.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg7.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg7.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg7_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg7_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv1i16:			; CHECK-LABEL: test_vssseg7_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg7.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg7_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv1i16:			; CHECK-LABEL: test_vssseg7_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg8.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg8.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg8.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg8_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg8_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv1i16:			; CHECK-LABEL: test_vssseg8_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg8.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg8_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv1i16:			; CHECK-LABEL: test_vssseg8_mask_nxv1i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg2_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv2i32:			; CHECK-LABEL: test_vssseg2_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv2i32:			; CHECK-LABEL: test_vssseg2_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg3_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv2i32:			; CHECK-LABEL: test_vssseg3_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv2i32:			; CHECK-LABEL: test_vssseg3_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg4_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv2i32:			; CHECK-LABEL: test_vssseg4_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv2i32:			; CHECK-LABEL: test_vssseg4_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)			declare void @llvm.riscv.vssseg5.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)
	declare void @llvm.riscv.vssseg5.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg5.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg5_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl) {			define void @test_vssseg5_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv2i32:			; CHECK-LABEL: test_vssseg5_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg5e32.v v8, (a0), a1			; CHECK-NEXT: vssseg5e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg5.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg5_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv2i32:			; CHECK-LABEL: test_vssseg5_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)			declare void @llvm.riscv.vssseg6.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)
	declare void @llvm.riscv.vssseg6.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg6.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg6_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl) {			define void @test_vssseg6_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv2i32:			; CHECK-LABEL: test_vssseg6_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg6e32.v v8, (a0), a1			; CHECK-NEXT: vssseg6e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg6.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg6_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv2i32:			; CHECK-LABEL: test_vssseg6_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)			declare void @llvm.riscv.vssseg7.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)
	declare void @llvm.riscv.vssseg7.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg7.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg7_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl) {			define void @test_vssseg7_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv2i32:			; CHECK-LABEL: test_vssseg7_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg7e32.v v8, (a0), a1			; CHECK-NEXT: vssseg7e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg7.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg7_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv2i32:			; CHECK-LABEL: test_vssseg7_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)			declare void @llvm.riscv.vssseg8.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, i64)
	declare void @llvm.riscv.vssseg8.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg8.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg8_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl) {			define void @test_vssseg8_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv2i32:			; CHECK-LABEL: test_vssseg8_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg8e32.v v8, (a0), a1			; CHECK-NEXT: vssseg8e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg8.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg8_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv2i32:			; CHECK-LABEL: test_vssseg8_mask_nxv2i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64)

	define void @test_vssseg2_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv8i8:			; CHECK-LABEL: test_vssseg2_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv8i8:			; CHECK-LABEL: test_vssseg2_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64)

	define void @test_vssseg3_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv8i8:			; CHECK-LABEL: test_vssseg3_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg3e8.v v8, (a0), a1			; CHECK-NEXT: vssseg3e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv8i8:			; CHECK-LABEL: test_vssseg3_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64)

	define void @test_vssseg4_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv8i8:			; CHECK-LABEL: test_vssseg4_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg4e8.v v8, (a0), a1			; CHECK-NEXT: vssseg4e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv8i8:			; CHECK-LABEL: test_vssseg4_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg5.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg5.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vssseg5.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64)

	define void @test_vssseg5_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg5_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv8i8:			; CHECK-LABEL: test_vssseg5_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg5e8.v v8, (a0), a1			; CHECK-NEXT: vssseg5e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg5.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vssseg5_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv8i8:			; CHECK-LABEL: test_vssseg5_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg6.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg6.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vssseg6.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64)

	define void @test_vssseg6_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg6_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv8i8:			; CHECK-LABEL: test_vssseg6_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg6e8.v v8, (a0), a1			; CHECK-NEXT: vssseg6e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg6.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vssseg6_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv8i8:			; CHECK-LABEL: test_vssseg6_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg7.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg7.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vssseg7.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64)

	define void @test_vssseg7_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg7_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv8i8:			; CHECK-LABEL: test_vssseg7_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg7e8.v v8, (a0), a1			; CHECK-NEXT: vssseg7e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg7.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vssseg7_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv8i8:			; CHECK-LABEL: test_vssseg7_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg8.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vssseg8.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, i64, <vscale x 8 x i1>, i64)

	define void @test_vssseg8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv8i8:			; CHECK-LABEL: test_vssseg8_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg8e8.v v8, (a0), a1			; CHECK-NEXT: vssseg8e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vssseg8_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv8i8:			; CHECK-LABEL: test_vssseg8_mask_nxv8i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
	; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg2_nxv4i64(<vscale x 4 x i64> %val, i64* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv4i64(<vscale x 4 x i64> %val, i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv4i64:			; CHECK-LABEL: test_vssseg2_nxv4i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
	; CHECK-NEXT: vssseg2e64.v v8, (a0), a1			; CHECK-NEXT: vssseg2e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv4i64(<vscale x 4 x i64> %val, i64* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv4i64(<vscale x 4 x i64> %val, i64* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv4i64:			; CHECK-LABEL: test_vssseg2_mask_nxv4i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
	; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg2_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv4i16:			; CHECK-LABEL: test_vssseg2_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv4i16:			; CHECK-LABEL: test_vssseg2_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg3_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv4i16:			; CHECK-LABEL: test_vssseg3_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv4i16:			; CHECK-LABEL: test_vssseg3_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg4_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv4i16:			; CHECK-LABEL: test_vssseg4_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv4i16:			; CHECK-LABEL: test_vssseg4_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg5.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg5.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg5.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg5_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg5_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv4i16:			; CHECK-LABEL: test_vssseg5_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg5.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg5_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv4i16:			; CHECK-LABEL: test_vssseg5_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg6.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg6.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg6.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg6_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg6_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv4i16:			; CHECK-LABEL: test_vssseg6_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg6.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg6_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv4i16:			; CHECK-LABEL: test_vssseg6_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg7.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg7.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg7.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg7_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg7_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv4i16:			; CHECK-LABEL: test_vssseg7_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg7.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg7_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv4i16:			; CHECK-LABEL: test_vssseg7_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg8.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg8.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg8.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg8_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg8_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv4i16:			; CHECK-LABEL: test_vssseg8_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg8.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg8_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv4i16:			; CHECK-LABEL: test_vssseg8_mask_nxv4i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg2_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv1i8:			; CHECK-LABEL: test_vssseg2_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv1i8:			; CHECK-LABEL: test_vssseg2_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg3_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv1i8:			; CHECK-LABEL: test_vssseg3_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg3e8.v v8, (a0), a1			; CHECK-NEXT: vssseg3e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv1i8:			; CHECK-LABEL: test_vssseg3_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg4_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv1i8:			; CHECK-LABEL: test_vssseg4_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg4e8.v v8, (a0), a1			; CHECK-NEXT: vssseg4e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv1i8:			; CHECK-LABEL: test_vssseg4_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg5.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg5.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg5.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg5_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg5_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv1i8:			; CHECK-LABEL: test_vssseg5_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg5e8.v v8, (a0), a1			; CHECK-NEXT: vssseg5e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg5.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg5_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv1i8:			; CHECK-LABEL: test_vssseg5_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg6.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg6.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg6.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg6_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg6_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv1i8:			; CHECK-LABEL: test_vssseg6_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg6e8.v v8, (a0), a1			; CHECK-NEXT: vssseg6e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg6.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg6_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv1i8:			; CHECK-LABEL: test_vssseg6_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg7.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg7.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg7.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg7_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg7_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv1i8:			; CHECK-LABEL: test_vssseg7_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg7e8.v v8, (a0), a1			; CHECK-NEXT: vssseg7e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg7.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg7_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv1i8:			; CHECK-LABEL: test_vssseg7_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg8.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg8.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv1i8:			; CHECK-LABEL: test_vssseg8_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg8e8.v v8, (a0), a1			; CHECK-NEXT: vssseg8e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg8_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv1i8:			; CHECK-LABEL: test_vssseg8_mask_nxv1i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
	; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg2_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv2i8:			; CHECK-LABEL: test_vssseg2_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv2i8:			; CHECK-LABEL: test_vssseg2_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg3_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv2i8:			; CHECK-LABEL: test_vssseg3_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg3e8.v v8, (a0), a1			; CHECK-NEXT: vssseg3e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv2i8:			; CHECK-LABEL: test_vssseg3_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg4_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv2i8:			; CHECK-LABEL: test_vssseg4_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg4e8.v v8, (a0), a1			; CHECK-NEXT: vssseg4e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv2i8:			; CHECK-LABEL: test_vssseg4_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg5.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg5.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg5.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg5_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg5_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv2i8:			; CHECK-LABEL: test_vssseg5_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg5e8.v v8, (a0), a1			; CHECK-NEXT: vssseg5e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg5.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg5_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv2i8:			; CHECK-LABEL: test_vssseg5_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg6.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg6.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg6.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg6_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg6_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv2i8:			; CHECK-LABEL: test_vssseg6_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg6e8.v v8, (a0), a1			; CHECK-NEXT: vssseg6e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg6.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg6_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv2i8:			; CHECK-LABEL: test_vssseg6_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg7.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg7.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg7.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg7_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg7_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv2i8:			; CHECK-LABEL: test_vssseg7_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg7e8.v v8, (a0), a1			; CHECK-NEXT: vssseg7e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg7.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg7_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv2i8:			; CHECK-LABEL: test_vssseg7_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg8.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg8.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv2i8:			; CHECK-LABEL: test_vssseg8_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg8e8.v v8, (a0), a1			; CHECK-NEXT: vssseg8e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg8_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv2i8:			; CHECK-LABEL: test_vssseg8_mask_nxv2i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
	; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, i64, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, i64, <vscale x 8 x i1>, i64)

	define void @test_vssseg2_nxv8i32(<vscale x 8 x i32> %val, i32* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv8i32(<vscale x 8 x i32> %val, i32* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv8i32:			; CHECK-LABEL: test_vssseg2_nxv8i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv8i32(<vscale x 8 x i32> %val, i32* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv8i32(<vscale x 8 x i32> %val, i32* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv8i32:			; CHECK-LABEL: test_vssseg2_mask_nxv8i32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, i64, <vscale x 32 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, i64, <vscale x 32 x i1>, i64)

	define void @test_vssseg2_nxv32i8(<vscale x 32 x i8> %val, i8* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv32i8(<vscale x 32 x i8> %val, i8* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv32i8:			; CHECK-LABEL: test_vssseg2_nxv32i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv32i8(<vscale x 32 x i8> %val, i8* %base, i64 %offset, <vscale x 32 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv32i8(<vscale x 32 x i8> %val, i8* %base, i64 %offset, <vscale x 32 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv32i8:			; CHECK-LABEL: test_vssseg2_mask_nxv32i8:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
	; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, i64 %offset, <vscale x 32 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, i64 %offset, <vscale x 32 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg2_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv2i16:			; CHECK-LABEL: test_vssseg2_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv2i16:			; CHECK-LABEL: test_vssseg2_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg3_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv2i16:			; CHECK-LABEL: test_vssseg3_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv2i16:			; CHECK-LABEL: test_vssseg3_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg4_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv2i16:			; CHECK-LABEL: test_vssseg4_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv2i16:			; CHECK-LABEL: test_vssseg4_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg5.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg5.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg5.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg5_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg5_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv2i16:			; CHECK-LABEL: test_vssseg5_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg5.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg5_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv2i16:			; CHECK-LABEL: test_vssseg5_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg6.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg6.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg6.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg6_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg6_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv2i16:			; CHECK-LABEL: test_vssseg6_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg6.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg6_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv2i16:			; CHECK-LABEL: test_vssseg6_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg7.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg7.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg7.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg7_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg7_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv2i16:			; CHECK-LABEL: test_vssseg7_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg7.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg7_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv2i16:			; CHECK-LABEL: test_vssseg7_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg8.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg8.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg8.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg8_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl) {			define void @test_vssseg8_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv2i16:			; CHECK-LABEL: test_vssseg8_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg8.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg8_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv2i16:			; CHECK-LABEL: test_vssseg8_mask_nxv2i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg2_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv2i64:			; CHECK-LABEL: test_vssseg2_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vssseg2e64.v v8, (a0), a1			; CHECK-NEXT: vssseg2e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv2i64:			; CHECK-LABEL: test_vssseg2_mask_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg3_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv2i64:			; CHECK-LABEL: test_vssseg3_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vssseg3e64.v v8, (a0), a1			; CHECK-NEXT: vssseg3e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv2i64:			; CHECK-LABEL: test_vssseg3_mask_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vssseg3e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg4_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv2i64:			; CHECK-LABEL: test_vssseg4_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vssseg4e64.v v8, (a0), a1			; CHECK-NEXT: vssseg4e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv2i64:			; CHECK-LABEL: test_vssseg4_mask_nxv2i64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vssseg4e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, i64, <vscale x 16 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, i64, <vscale x 16 x i1>, i64)

	define void @test_vssseg2_nxv16f16(<vscale x 16 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv16f16(<vscale x 16 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv16f16:			; CHECK-LABEL: test_vssseg2_nxv16f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv16f16(<vscale x 16 x half> %val, half* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv16f16(<vscale x 16 x half> %val, half* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv16f16:			; CHECK-LABEL: test_vssseg2_mask_nxv16f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg2_nxv4f64(<vscale x 4 x double> %val, double* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv4f64(<vscale x 4 x double> %val, double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv4f64:			; CHECK-LABEL: test_vssseg2_nxv4f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
	; CHECK-NEXT: vssseg2e64.v v8, (a0), a1			; CHECK-NEXT: vssseg2e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv4f64(<vscale x 4 x double> %val, double* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv4f64(<vscale x 4 x double> %val, double* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv4f64:			; CHECK-LABEL: test_vssseg2_mask_nxv4f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
	; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg2_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv1f64:			; CHECK-LABEL: test_vssseg2_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg2e64.v v8, (a0), a1			; CHECK-NEXT: vssseg2e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv1f64:			; CHECK-LABEL: test_vssseg2_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg3_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv1f64:			; CHECK-LABEL: test_vssseg3_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg3e64.v v8, (a0), a1			; CHECK-NEXT: vssseg3e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv1f64:			; CHECK-LABEL: test_vssseg3_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg3e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg4_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv1f64:			; CHECK-LABEL: test_vssseg4_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg4e64.v v8, (a0), a1			; CHECK-NEXT: vssseg4e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv1f64:			; CHECK-LABEL: test_vssseg4_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg4e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)			declare void @llvm.riscv.vssseg5.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)
	declare void @llvm.riscv.vssseg5.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg5.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg5_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl) {			define void @test_vssseg5_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv1f64:			; CHECK-LABEL: test_vssseg5_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg5e64.v v8, (a0), a1			; CHECK-NEXT: vssseg5e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg5.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg5_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv1f64:			; CHECK-LABEL: test_vssseg5_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg5e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)			declare void @llvm.riscv.vssseg6.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)
	declare void @llvm.riscv.vssseg6.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg6.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg6_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl) {			define void @test_vssseg6_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv1f64:			; CHECK-LABEL: test_vssseg6_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg6e64.v v8, (a0), a1			; CHECK-NEXT: vssseg6e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg6.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg6_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv1f64:			; CHECK-LABEL: test_vssseg6_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg6e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)			declare void @llvm.riscv.vssseg7.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)
	declare void @llvm.riscv.vssseg7.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg7.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg7_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl) {			define void @test_vssseg7_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv1f64:			; CHECK-LABEL: test_vssseg7_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg7e64.v v8, (a0), a1			; CHECK-NEXT: vssseg7e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg7.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg7_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv1f64:			; CHECK-LABEL: test_vssseg7_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg7e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)			declare void @llvm.riscv.vssseg8.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, i64)
	declare void @llvm.riscv.vssseg8.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg8.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg8_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl) {			define void @test_vssseg8_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv1f64:			; CHECK-LABEL: test_vssseg8_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg8e64.v v8, (a0), a1			; CHECK-NEXT: vssseg8e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg8.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg8_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv1f64:			; CHECK-LABEL: test_vssseg8_mask_nxv1f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
	; CHECK-NEXT: vssseg8e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg2_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv2f32:			; CHECK-LABEL: test_vssseg2_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv2f32:			; CHECK-LABEL: test_vssseg2_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg3_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv2f32:			; CHECK-LABEL: test_vssseg3_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv2f32:			; CHECK-LABEL: test_vssseg3_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg4_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv2f32:			; CHECK-LABEL: test_vssseg4_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv2f32:			; CHECK-LABEL: test_vssseg4_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)			declare void @llvm.riscv.vssseg5.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)
	declare void @llvm.riscv.vssseg5.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg5.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg5_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl) {			define void @test_vssseg5_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv2f32:			; CHECK-LABEL: test_vssseg5_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg5e32.v v8, (a0), a1			; CHECK-NEXT: vssseg5e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg5.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg5_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv2f32:			; CHECK-LABEL: test_vssseg5_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)			declare void @llvm.riscv.vssseg6.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)
	declare void @llvm.riscv.vssseg6.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg6.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg6_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl) {			define void @test_vssseg6_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv2f32:			; CHECK-LABEL: test_vssseg6_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg6e32.v v8, (a0), a1			; CHECK-NEXT: vssseg6e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg6.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg6_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv2f32:			; CHECK-LABEL: test_vssseg6_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)			declare void @llvm.riscv.vssseg7.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)
	declare void @llvm.riscv.vssseg7.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg7.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg7_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl) {			define void @test_vssseg7_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv2f32:			; CHECK-LABEL: test_vssseg7_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg7e32.v v8, (a0), a1			; CHECK-NEXT: vssseg7e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg7.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg7_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv2f32:			; CHECK-LABEL: test_vssseg7_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)			declare void @llvm.riscv.vssseg8.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, i64)
	declare void @llvm.riscv.vssseg8.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg8.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg8_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl) {			define void @test_vssseg8_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv2f32:			; CHECK-LABEL: test_vssseg8_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg8e32.v v8, (a0), a1			; CHECK-NEXT: vssseg8e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg8.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg8_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv2f32:			; CHECK-LABEL: test_vssseg8_mask_nxv2f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
	; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg2_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv1f16:			; CHECK-LABEL: test_vssseg2_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv1f16:			; CHECK-LABEL: test_vssseg2_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg3_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv1f16:			; CHECK-LABEL: test_vssseg3_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv1f16:			; CHECK-LABEL: test_vssseg3_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg4_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv1f16:			; CHECK-LABEL: test_vssseg4_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv1f16:			; CHECK-LABEL: test_vssseg4_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg5.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg5.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg5.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg5_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg5_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv1f16:			; CHECK-LABEL: test_vssseg5_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg5.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg5_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv1f16:			; CHECK-LABEL: test_vssseg5_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg6.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg6.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg6.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg6_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg6_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv1f16:			; CHECK-LABEL: test_vssseg6_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg6.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg6_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv1f16:			; CHECK-LABEL: test_vssseg6_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg7.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg7.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg7.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg7_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg7_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv1f16:			; CHECK-LABEL: test_vssseg7_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg7.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg7_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv1f16:			; CHECK-LABEL: test_vssseg7_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg8.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg8.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg8.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg8_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg8_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv1f16:			; CHECK-LABEL: test_vssseg8_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg8.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg8_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv1f16:			; CHECK-LABEL: test_vssseg8_mask_nxv1f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg2_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv1f32:			; CHECK-LABEL: test_vssseg2_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv1f32:			; CHECK-LABEL: test_vssseg2_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg3_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv1f32:			; CHECK-LABEL: test_vssseg3_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv1f32:			; CHECK-LABEL: test_vssseg3_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg4_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv1f32:			; CHECK-LABEL: test_vssseg4_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv1f32:			; CHECK-LABEL: test_vssseg4_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)			declare void @llvm.riscv.vssseg5.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)
	declare void @llvm.riscv.vssseg5.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg5.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg5_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl) {			define void @test_vssseg5_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv1f32:			; CHECK-LABEL: test_vssseg5_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg5e32.v v8, (a0), a1			; CHECK-NEXT: vssseg5e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg5.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg5_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv1f32:			; CHECK-LABEL: test_vssseg5_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)			declare void @llvm.riscv.vssseg6.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)
	declare void @llvm.riscv.vssseg6.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg6.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg6_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl) {			define void @test_vssseg6_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv1f32:			; CHECK-LABEL: test_vssseg6_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg6e32.v v8, (a0), a1			; CHECK-NEXT: vssseg6e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg6.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg6_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv1f32:			; CHECK-LABEL: test_vssseg6_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)			declare void @llvm.riscv.vssseg7.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)
	declare void @llvm.riscv.vssseg7.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg7.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg7_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl) {			define void @test_vssseg7_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv1f32:			; CHECK-LABEL: test_vssseg7_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg7e32.v v8, (a0), a1			; CHECK-NEXT: vssseg7e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg7.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg7_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv1f32:			; CHECK-LABEL: test_vssseg7_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)			declare void @llvm.riscv.vssseg8.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, i64)
	declare void @llvm.riscv.vssseg8.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64)			declare void @llvm.riscv.vssseg8.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, i64, <vscale x 1 x i1>, i64)

	define void @test_vssseg8_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl) {			define void @test_vssseg8_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv1f32:			; CHECK-LABEL: test_vssseg8_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg8e32.v v8, (a0), a1			; CHECK-NEXT: vssseg8e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg8.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {			define void @test_vssseg8_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv1f32:			; CHECK-LABEL: test_vssseg8_mask_nxv1f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
	; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, <vscale x 8 x i1>, i64)

	define void @test_vssseg2_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv8f16:			; CHECK-LABEL: test_vssseg2_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv8f16:			; CHECK-LABEL: test_vssseg2_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, <vscale x 8 x i1>, i64)

	define void @test_vssseg3_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv8f16:			; CHECK-LABEL: test_vssseg3_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv8f16:			; CHECK-LABEL: test_vssseg3_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, i64, <vscale x 8 x i1>, i64)

	define void @test_vssseg4_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv8f16:			; CHECK-LABEL: test_vssseg4_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv8f16:			; CHECK-LABEL: test_vssseg4_mask_nxv8f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, i64, <vscale x 8 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, i64, <vscale x 8 x i1>, i64)

	define void @test_vssseg2_nxv8f32(<vscale x 8 x float> %val, float* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv8f32(<vscale x 8 x float> %val, float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv8f32:			; CHECK-LABEL: test_vssseg2_nxv8f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv8f32(<vscale x 8 x float> %val, float* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv8f32(<vscale x 8 x float> %val, float* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv8f32:			; CHECK-LABEL: test_vssseg2_mask_nxv8f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, i64 %offset, <vscale x 8 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg2_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv2f64:			; CHECK-LABEL: test_vssseg2_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vssseg2e64.v v8, (a0), a1			; CHECK-NEXT: vssseg2e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv2f64:			; CHECK-LABEL: test_vssseg2_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg3_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv2f64:			; CHECK-LABEL: test_vssseg3_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vssseg3e64.v v8, (a0), a1			; CHECK-NEXT: vssseg3e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv2f64:			; CHECK-LABEL: test_vssseg3_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vssseg3e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg4_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv2f64:			; CHECK-LABEL: test_vssseg4_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vssseg4e64.v v8, (a0), a1			; CHECK-NEXT: vssseg4e64.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv2f64:			; CHECK-LABEL: test_vssseg4_mask_nxv2f64:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
	; CHECK-NEXT: vssseg4e64.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e64.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg2_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv4f16:			; CHECK-LABEL: test_vssseg2_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv4f16:			; CHECK-LABEL: test_vssseg2_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg3_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv4f16:			; CHECK-LABEL: test_vssseg3_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv4f16:			; CHECK-LABEL: test_vssseg3_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg4_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv4f16:			; CHECK-LABEL: test_vssseg4_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv4f16:			; CHECK-LABEL: test_vssseg4_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg5.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg5.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg5.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg5_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg5_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv4f16:			; CHECK-LABEL: test_vssseg5_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg5.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg5_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv4f16:			; CHECK-LABEL: test_vssseg5_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg6.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg6.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg6.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg6_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg6_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv4f16:			; CHECK-LABEL: test_vssseg6_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg6.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg6_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv4f16:			; CHECK-LABEL: test_vssseg6_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg7.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg7.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg7.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg7_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg7_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv4f16:			; CHECK-LABEL: test_vssseg7_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg7.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg7_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv4f16:			; CHECK-LABEL: test_vssseg7_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg8.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg8.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg8.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg8_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg8_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv4f16:			; CHECK-LABEL: test_vssseg8_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg8.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg8_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv4f16:			; CHECK-LABEL: test_vssseg8_mask_nxv4f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg2_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv2f16:			; CHECK-LABEL: test_vssseg2_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv2f16:			; CHECK-LABEL: test_vssseg2_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg3_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv2f16:			; CHECK-LABEL: test_vssseg3_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv2f16:			; CHECK-LABEL: test_vssseg3_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg4_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv2f16:			; CHECK-LABEL: test_vssseg4_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv2f16:			; CHECK-LABEL: test_vssseg4_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg5.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg5.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg5.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg5.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg5_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg5_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_nxv2f16:			; CHECK-LABEL: test_vssseg5_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg5.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg5_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg5_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg5_mask_nxv2f16:			; CHECK-LABEL: test_vssseg5_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg5.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg5.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg6.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg6.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg6.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg6.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg6_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg6_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_nxv2f16:			; CHECK-LABEL: test_vssseg6_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg6.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg6_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg6_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg6_mask_nxv2f16:			; CHECK-LABEL: test_vssseg6_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg6.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg6.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg7.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg7.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg7.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg7.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg7_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg7_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_nxv2f16:			; CHECK-LABEL: test_vssseg7_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg7.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg7_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg7_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg7_mask_nxv2f16:			; CHECK-LABEL: test_vssseg7_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg7.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg7.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg8.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)			declare void @llvm.riscv.vssseg8.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, i64)
	declare void @llvm.riscv.vssseg8.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64)			declare void @llvm.riscv.vssseg8.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, i64, <vscale x 2 x i1>, i64)

	define void @test_vssseg8_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl) {			define void @test_vssseg8_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_nxv2f16:			; CHECK-LABEL: test_vssseg8_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg8.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg8_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {			define void @test_vssseg8_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg8_mask_nxv2f16:			; CHECK-LABEL: test_vssseg8_mask_nxv2f16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
	; CHECK-NEXT: vmv1r.v v9, v8			; CHECK-NEXT: vmv1r.v v9, v8
	; CHECK-NEXT: vmv1r.v v10, v8			; CHECK-NEXT: vmv1r.v v10, v8
	; CHECK-NEXT: vmv1r.v v11, v8			; CHECK-NEXT: vmv1r.v v11, v8
	; CHECK-NEXT: vmv1r.v v12, v8			; CHECK-NEXT: vmv1r.v v12, v8
	; CHECK-NEXT: vmv1r.v v13, v8			; CHECK-NEXT: vmv1r.v v13, v8
	; CHECK-NEXT: vmv1r.v v14, v8			; CHECK-NEXT: vmv1r.v v14, v8
	; CHECK-NEXT: vmv1r.v v15, v8			; CHECK-NEXT: vmv1r.v v15, v8
	; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
	; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg8.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg8.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, i64 %offset, <vscale x 2 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg2_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %offset, i64 %vl) {			define void @test_vssseg2_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_nxv4f32:			; CHECK-LABEL: test_vssseg2_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg2.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg2_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg2_mask_nxv4f32:			; CHECK-LABEL: test_vssseg2_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg2.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg3.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, i64)			declare void @llvm.riscv.vssseg3.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, i64)
	declare void @llvm.riscv.vssseg3.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg3.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg3_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %offset, i64 %vl) {			define void @test_vssseg3_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_nxv4f32:			; CHECK-LABEL: test_vssseg3_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg3.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg3_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg3_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg3_mask_nxv4f32:			; CHECK-LABEL: test_vssseg3_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg3.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg3.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg4.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, i64)			declare void @llvm.riscv.vssseg4.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, i64)
	declare void @llvm.riscv.vssseg4.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, <vscale x 4 x i1>, i64)			declare void @llvm.riscv.vssseg4.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, i64, <vscale x 4 x i1>, i64)

	define void @test_vssseg4_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %offset, i64 %vl) {			define void @test_vssseg4_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %offset, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_nxv4f32:			; CHECK-LABEL: test_vssseg4_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i64 %offset, i64 %vl)			tail call void @llvm.riscv.vssseg4.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i64 %offset, i64 %vl)
	ret void			ret void
	}			}

	define void @test_vssseg4_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {			define void @test_vssseg4_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl) {
	; CHECK-LABEL: test_vssseg4_mask_nxv4f32:			; CHECK-LABEL: test_vssseg4_mask_nxv4f32:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
	; CHECK-NEXT: vmv2r.v v10, v8			; CHECK-NEXT: vmv2r.v v10, v8
	; CHECK-NEXT: vmv2r.v v12, v8			; CHECK-NEXT: vmv2r.v v12, v8
	; CHECK-NEXT: vmv2r.v v14, v8			; CHECK-NEXT: vmv2r.v v14, v8
	; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu			; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
	; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg4.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)			tail call void @llvm.riscv.vssseg4.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, i64 %offset, <vscale x 4 x i1> %mask, i64 %vl)
	ret void			ret void
	}			}

llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll

This file has a very large number of changes (5,412 lines). Show File Contents

llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll

This file has a very large number of changes (7,622 lines). Show File Contents

llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll

	Show All 9 Lines

	define <vscale x 16 x i16> @test_vlseg2_mask_nxv16i16(i16* %base, <vscale x 16 x i1> %mask) {			define <vscale x 16 x i16> @test_vlseg2_mask_nxv16i16(i16* %base, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlseg2_mask_nxv16i16:			; CHECK-LABEL: test_vlseg2_mask_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu			; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu
	; CHECK-NEXT: vlseg2e16.v v4, (a0)			; CHECK-NEXT: vlseg2e16.v v4, (a0)
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.nxv16i16(<vscale x 16 x i16> undef,<vscale x 16 x i16> undef, i16* %base, i64 0)			%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.nxv16i16(<vscale x 16 x i16> undef,<vscale x 16 x i16> undef, i16* %base, i64 0)
	%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0			%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
	%2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.mask.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 16 x i1> %mask, i64 0, i64 1)			%2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.mask.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 16 x i1> %mask, i64 0, i64 1)
	%3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1			%3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
	ret <vscale x 16 x i16> %3			ret <vscale x 16 x i16> %3
	}			}

	declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, i64)			declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, i64)
	declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, <vscale x 16 x i1>, i64, i64)			declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, <vscale x 16 x i1>, i64, i64)

	define <vscale x 16 x i16> @test_vlsseg2_mask_nxv16i16(i16* %base, i64 %offset, <vscale x 16 x i1> %mask) {			define <vscale x 16 x i16> @test_vlsseg2_mask_nxv16i16(i16* %base, i64 %offset, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vlsseg2_mask_nxv16i16:			; CHECK-LABEL: test_vlsseg2_mask_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu			; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu
	; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1			; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1
	; CHECK-NEXT: vmv4r.v v8, v4			; CHECK-NEXT: vmv4r.v v8, v4
	; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t			; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i64 %offset, i64 0)			%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i64 %offset, i64 0)
	%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0			%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
	%2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.mask.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 0, i64 1)			%2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.mask.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 0, i64 1)
	%3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1			%3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
	ret <vscale x 16 x i16> %3			ret <vscale x 16 x i16> %3
	}			}
	▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines

	define <vscale x 16 x i16> @test_vlseg2ff_nxv16i16(i16* %base, i64* %outvl) {			define <vscale x 16 x i16> @test_vlseg2ff_nxv16i16(i16* %base, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_nxv16i16:			; CHECK-LABEL: test_vlseg2ff_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu			; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v4, (a0)			; CHECK-NEXT: vlseg2e16ff.v v4, (a0)
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a1)			; CHECK-NEXT: sd a0, 0(a1)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i64 0)			%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(<vscale x 16 x i16> undef, <vscale x 16 x i16> undef, i16* %base, i64 0)
	%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2			%2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 16 x i16> %1			ret <vscale x 16 x i16> %1
	}			}

	define <vscale x 16 x i16> @test_vlseg2ff_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64* %outvl) {			define <vscale x 16 x i16> @test_vlseg2ff_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64* %outvl) {
	; CHECK-LABEL: test_vlseg2ff_mask_nxv16i16:			; CHECK-LABEL: test_vlseg2ff_mask_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
	; CHECK-NEXT: vmv4r.v v4, v8			; CHECK-NEXT: vmv4r.v v4, v8
	; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu			; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu
	; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t			; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t
	; CHECK-NEXT: csrr a0, vl			; CHECK-NEXT: csrr a0, vl
	; CHECK-NEXT: sd a0, 0(a1)			; CHECK-NEXT: sd a0, 0(a1)
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 0, i64 1)			%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 0, i64 1)
	%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1			%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1
	%2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2			%2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2
	store i64 %2, i64* %outvl			store i64 %2, i64* %outvl
	ret <vscale x 16 x i16> %1			ret <vscale x 16 x i16> %1
	}			}

	declare void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16* , i64)			declare void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16* , i64)
	declare void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i64)			declare void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i64)

	define void @test_vsseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base) {			define void @test_vsseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base) {
	; CHECK-LABEL: test_vsseg2_nxv16i16:			; CHECK-LABEL: test_vsseg2_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu			; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0)			; CHECK-NEXT: vsseg2e16.v v8, (a0)
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 0)			tail call void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 0)
	ret void			ret void
	}			}

	define void @test_vsseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask) {			define void @test_vsseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vsseg2_mask_nxv16i16:			; CHECK-LABEL: test_vsseg2_mask_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu			; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu
	; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t			; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 0)			tail call void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 0)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vssseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, i64)			declare void @llvm.riscv.vssseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, i64)
	declare void @llvm.riscv.vssseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, <vscale x 16 x i1>, i64)			declare void @llvm.riscv.vssseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, <vscale x 16 x i1>, i64)

	define void @test_vssseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i64 %offset) {			define void @test_vssseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i64 %offset) {
	; CHECK-LABEL: test_vssseg2_nxv16i16:			; CHECK-LABEL: test_vssseg2_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu			; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 %offset, i64 0)			tail call void @llvm.riscv.vssseg2.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 %offset, i64 0)
	ret void			ret void
	}			}

	define void @test_vssseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i64 %offset, <vscale x 16 x i1> %mask) {			define void @test_vssseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i64 %offset, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vssseg2_mask_nxv16i16:			; CHECK-LABEL: test_vssseg2_mask_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu			; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu
	; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t			; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vssseg2.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 0)			tail call void @llvm.riscv.vssseg2.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 0)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, i64)			declare void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, i64)
	declare void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)			declare void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)

	define void @test_vsoxseg2_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index) {			define void @test_vsoxseg2_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index) {
	; CHECK-LABEL: test_vsoxseg2_nxv16i16_nxv16i16:			; CHECK-LABEL: test_vsoxseg2_nxv16i16_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v16, v12			; CHECK-NEXT: vmv4r.v v16, v12
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu			; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu
	; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16			; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 0)			tail call void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 0)
	ret void			ret void
	}			}

	define void @test_vsoxseg2_mask_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {			define void @test_vsoxseg2_mask_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_nxv16i16:			; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v16, v12			; CHECK-NEXT: vmv4r.v v16, v12
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu			; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu
	; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t			; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0)			tail call void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0)
	ret void			ret void
	}			}

	declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, i64)			declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, i64)
	declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)			declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)

	define void @test_vsuxseg2_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index) {			define void @test_vsuxseg2_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index) {
	; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv16i16:			; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v16, v12			; CHECK-NEXT: vmv4r.v v16, v12
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu			; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu
	; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16			; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 0)			tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 0)
	ret void			ret void
	}			}

	define void @test_vsuxseg2_mask_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {			define void @test_vsuxseg2_mask_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {
	; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv16i16:			; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv16i16:
	; CHECK: # %bb.0: # %entry			; CHECK: # %bb.0: # %entry
				; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
	; CHECK-NEXT: vmv4r.v v16, v12			; CHECK-NEXT: vmv4r.v v16, v12
	; CHECK-NEXT: vmv4r.v v12, v8			; CHECK-NEXT: vmv4r.v v12, v8
	; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu			; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu
	; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t			; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	entry:			entry:
	tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0)			tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0)
	ret void			ret void
	}			}

This is an archive of the discontinued LLVM Phabricator instance.

[RISCV] Disable subregister liveness by defaultClosedPublic

Details

Diff Detail

Event Timeline

Revision Contents

Diff 444691

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vector-segN-load.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll

llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll

llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll

llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll

llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll

llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll

llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll

llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll

[RISCV] Disable subregister liveness by default
ClosedPublic