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[RISCV] Add a test showing a miscompilation with subreg liveness
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Authored by frasercrmck on Jul 13 2022, 6:42 AM.

Details

Summary

This patch adds a test which shows that we may incorrectly register
allocate for RVV instructions which have no-overlap constraints on
source/dest registers of different LMUL groups.

The particular case shows that a vrgatherei16 instruction writes to a
LMUL=1 register group v11 and reads from an EMUL=2 register group
v10/v11. This breaks the overlap constraints of the vrgatherei16
instruction.

The test also shows that disabling subregister liveness fixes the test.

We use early-clobber on the VR dest and the VRM2 source to enforce
the constraint but with subregister liveness this constraint is not met.

It's unclear to me at this point whether this is per-design of
early-clobber in conjunction with subregisters (meaning we should find
another way of expressing this constraint) or whether it's a bug in the
register allocator somewhere.

Diff Detail

Event Timeline

frasercrmck created this revision.Jul 13 2022, 6:42 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 13 2022, 6:42 AM
frasercrmck requested review of this revision.Jul 13 2022, 6:42 AM
rogfer01 accepted this revision.Jul 13 2022, 12:47 PM
This revision is now accepted and ready to land.Jul 13 2022, 12:47 PM
This revision was landed with ongoing or failed builds.Jul 14 2022, 2:46 AM
This revision was automatically updated to reflect the committed changes.