[DebugInfo][NFC?] Add new MachineOperand type and change DBG_INSTR_REF syntax

[StephenTozer]

Summary

This patch implements the proposals in the RFC made earlier this year.

This patch makes two notable changes to the MIR debug info representation, which result in different MIR output but identical final DWARF output (NFC w.r.t. the full compilation). The two changes are:

1. The introduction of a new MachineOperand type, MO_DbgInstrRef, which consists of two unsigned numbers that are used to index an instruction and an output operand within that instruction, having a meaning identical to first two operands of the current DBG_INSTR_REF instruction. This operand is only used in DBG_INSTR_REF (see below).
2. A change in syntax for the DBG_INSTR_REF instruction, shuffling the operands to make it resemble DBG_VALUE_LIST instead of DBG_VALUE, and replacing the first two operands with a single MO_DbgInstrRef-type operand.

Combined, these changes do not affect anything about the debug info that we produce or how we handle it throughout CodeGen, but instead simply changes the way we represent instruction references:

Old: DBG_INSTR_REF 1, 0, !123, !456
New: DBG_INSTR_REF !123, !456, dbg-instr-ref(1, 0)

The motivation for this, as described in the RFC, is that we wish to be able to use instruction references in variadic debug values. One of the key difficulties with variadic debug values is that they must track the lifetimes of every register that they refer to, making them brittle to things like hoisting or sinking instructions - even if there is a valid range where a variadic debug value can be computed, the debug value may be terminated by shuffling instructions. As instruction references are more resilient against this sort of thing by referring to values produced by instructions instead of registers, freeing us from the need to move the debug values themselves around and preemptively terminate their ranges, it may be beneficial to allow variadic debug values to take advantage of this behaviour.

This patch does not grant this functionality, but takes care of all the foundational work to implement this feature, allowing the next patch to focus entirely on functional changes.

[StephenTozer]

Update diff to give full context, fix up a couple of slightly-inconsistently-formatted test expectations.

[StephenTozer]

Update patch with some fixes, remove tests from the patch (to bundle all the test changes into one patch later on).

[jmorse]

This all seems fine and well, I've added some nits about spellings and how things present to the developer,

This is missing test changes to account for the fact that all LL -> MIR variable locations will now be spelt differently, that should lead to a bunch of tests failing. Plus: a round-trip test for the syntax of the new operand would be good.

Seeing how this patch moves everything over to use the new operand form, how about adding a MachineVerifier check that DBG_INSTR_REF's have the correct format? That's going to catch any MIR tests where the old syntax is used, which would break in strange ways when fed into LiveDebugValues.

llvm/include/llvm/CodeGen/MachineInstr.h

1274

Un-necessary move of the label -- quite a nit, but future code archeologists looking at git blame will appreciate it not having been moved.

llvm/include/llvm/CodeGen/MachineOperand.h

67

Any particular reason for this not being at the end? I don't think it makes a difference, but on the principle of least surprise (and in case someone out there is preserving these things) it'd be better to append to this list.

599–602

I fear that this method name is going to be misinterpreted by the reader as returning what the operands index is in the owning instruction. Obviously this is a bother to think about, but worth considering. Possibly prefixing Dbg before 'Instr' and 'Op' will be clearer?

Also, for consistency, IMO it should be "Index" instead of Idx, the following method says "Index".

Similarly with the setters.

llvm/lib/CodeGen/InlineSpiller.cpp

1066 ↗

(On Diff #460351)

This seems out of place in a "adding-the-machine-operand-type" patch, would it be better re-homed into one of the later ones? If there's no specific error mode in mind where this could fire, it's probably ok to fold in as just a "general improvement"

llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp

1368

Unrelated whitespace changes undesirable

llvm/lib/CodeGen/MIRParser/MILexer.cpp

281

clang-format fixing best done in a separate / independent patch. I believe so long as it's an obvious 80-column fix or clang-format problem, you can just push it up without review.

llvm/lib/CodeGen/MIRParser/MIParser.cpp

2721–2722

If there's an obvious way to assert for that, then yes please.

llvm/lib/CodeGen/MachineFunction.cpp

1199–1201

AFAIUI this isn't necessary at this stage (and could lead to test breakage), is that right? If so, better to fold into a "making DBG_VALUE_LIST everywhere" (or whatever it gets called in the end) patch.

llvm/lib/CodeGen/MachineSink.cpp

571–574

Isn't it necessary for the variable information to go into SeenDbgVars, so that a DBG_VALUE can't re-order with a DBG_INSTR_REF

llvm/lib/CodeGen/SelectionDAG/FastISel.cpp

1255

IMO easier to read by keeping the original spelling (UseInstrRefDebugInfo && Op->isReg()) and just swapping the order of blocks -- inverting the logic causes the reader to think something complicated is going on.

[jmorse]

Ah, OK, you threw me by having the test updates in the final patch -- IMO better to have them in each patch themselves, as you're going to have to land them like that. Could you stage those test changes into this patch please?

[StephenTozer]

In D129372#3795879, @jmorse wrote:

Ah, OK, you threw me by having the test updates in the final patch -- IMO better to have them in each patch themselves, as you're going to have to land them like that. Could you stage those test changes into this patch please?

Right, it is somewhat confusing - the reason for this was mainly that this and another patch in this stack both change the way DBG_INSTR_REFs will be printed, and so it would probably create a lot of noise having both patches update every test that uses DBG_INSTR_REF. If you feel it would be better represented with all the changes in each patch exactly as they'll land, then I can do so.

[StephenTozer]

Return tests to this patch, and address the remaining review comments.

llvm/include/llvm/CodeGen/MachineOperand.h

599–602

That's a reasonable point - I'd probably object to using Dbg as the prefix though, as DbgOp is used elsewhere to refer to the operands in debug value (and as of this patch, in a DBG_INSTR_REF!). It's a long function name, but I think using InstrRef as the prefix is pretty unambiguous.

llvm/lib/CodeGen/MachineFunction.cpp

1199–1201

The reason for making this change is just that it keeps the undef-ing simple, as converting it to a DBG_VALUE would now require us to move and add operands, and after the next patch in the stack also modify the DIExpression. Since it's an undef value either way it doesn't make any difference in the final output, and AFAIK doesn't cause much/any breakage with existing tests. But if you think the tradeoff is worth it then I'm open to doing the DBG_VALUE conversion, WDYT?

[jmorse]

LGTM; the test changes from this patch are reassuringly mechanical!

llvm/include/llvm/CodeGen/MachineOperand.h

599–602

SGTM

llvm/lib/CodeGen/MachineFunction.cpp

1199–1201

SGTM

[jmorse]

llvm/lib/CodeGen/MachineFunction.cpp

1199–1201

(i.e.: that sounds like a fine reason to make this change, no need for further work)

[StephenTozer]

Rebased onto more recent state.

[StephenTozer]

Rebased again now that the patch stack is ready to land.

llvm/docs/MIRLangRef.rst

 represented using a '``$noreg``' named register, although the former syntax
 is preferred.
 
 .. _machine-operands:
 
 Machine Operands
 ----------------
 
-There are seventeen different kinds of machine operands, and all of them can be
+There are eighteen different kinds of machine operands, and all of them can be
 serialized.
 
 Immediate Operands
 ^^^^^^^^^^^^^^^^^^
 
 The immediate machine operands are untyped, 64-bit signed integers. The
 example below shows an instance of the X86 ``MOV32ri`` instruction that has an
 immediate machine operand ``-42``:

 of this operand in MIR, see :ref:`limitations <limitations>`.
 
 The syntax is:
 
 .. code-block:: text
 
     EH_LABEL <mcsymbol Ltmp1>
 
+Debug Instruction Reference Operands
+^^^^^^^^^^^^^^^^^
+
+A debug instruction reference operand is a pair of indices, referring to an
+instruction and an operand within that instruction respectively; see
+:ref:`Instruction referencing locations <instruction-referencing-locations>`.
+
+The example below uses a reference to Instruction 1, Operand 0:
+
+.. code-block:: text
+
+    DBG_INSTR_REF !123, !DIExpression(), dbg-instr-ref(1, 0), debug-location !456
+
 CFIIndex Operands
 ^^^^^^^^^^^^^^^^^
 
 A CFI Index operand is holding an index into a per-function side-table,
 ``MachineFunction::getFrameInstructions()``, which references all the frame
 instructions in a ``MachineFunction``. A ``CFI_INSTRUCTION`` may look like it
 contains multiple operands, but the only operand it contains is the CFI Index.
 The other operands are tracked by the ``MCCFIInstruction`` object.

 
 4. Specifies an expression qualifying the variable location, either inline or as a metadata node reference,
 
 While the source location identifies the ``DILocation`` for the scope of the
 variable. The second operand (``IsIndirect``) is deprecated and to be deleted.
 All additional qualifiers for the variable location should be made through the
 expression metadata.
 
+.. _instruction-referencing-locations:
+
 Instruction referencing locations
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 This experimental feature aims to separate the specification of variable
 *values* from the program point where a variable takes on that value. Changes
 in variable value occur in the same manner as ``DBG_VALUE`` meta instructions
 but using ``DBG_INSTR_REF``. Variable values are identified by a pair of
 instruction number and operand number. Consider the example below:
 
 .. code-block:: text
 
     $rbp = MOV64ri 0, debug-instr-number 1, debug-location !12
-    DBG_INSTR_REF 1, 0, !123, !DIExpression(), debug-location !456
+    DBG_INSTR_REF !123, !DIExpression(), dbg-instr-ref(1, 0), debug-location !456
 
 Instruction numbers are directly attached to machine instructions with an
 optional ``debug-instr-number`` attachment, before the optional
 ``debug-location`` attachment. The value defined in ``$rbp`` in the code
 above would be identified by the pair ``<1, 0>``.
 
-The first two operands of the ``DBG_INSTR_REF`` above record the instruction
+The 3rd operand of the ``DBG_INSTR_REF`` above records the instruction
 and operand number ``<1, 0>``, identifying the value defined by the ``MOV64ri``.
-The additional operands to ``DBG_INSTR_REF`` are identical to ``DBG_VALUE``,
+The first two operands to ``DBG_INSTR_REF`` are identical to ``DBG_VALUE_LIST``,
 and the ``DBG_INSTR_REF`` s position records where the variable takes on the
 designated value in the same way.
 
 More information about how these constructs are used is available in
 :doc:`InstrRefDebugInfo`. The related documents :doc:`SourceLevelDebugging` and
 :doc:`HowToUpdateDebugInfo` may be useful as well.

llvm/include/llvm/CodeGen/MachineInstr.h

iterator_range<mop_iterator> implicit_operands() {
     return make_range(explicit_operands().end(), operands_end());
   }
   iterator_range<const_mop_iterator> implicit_operands() const {
     return make_range(explicit_operands().end(), operands_end());
   }
   /// Returns a range over all operands that are used to determine the variable
   /// location for this DBG_VALUE instruction.
   iterator_range<mop_iterator> debug_operands() {
-    assert(isDebugValue() && "Must be a debug value instruction.");
-    return isDebugValueList()
-               ? make_range(operands_begin() + 2, operands_end())
-               : make_range(operands_begin(), operands_begin() + 1);
+    assert((isDebugValueLike()) && "Must be a debug value instruction.");
+    return isNonListDebugValue()
+               ? make_range(operands_begin(), operands_begin() + 1)
+               : make_range(operands_begin() + 2, operands_end());
   }
   /// \copydoc debug_operands()
   iterator_range<const_mop_iterator> debug_operands() const {
-    assert(isDebugValue() && "Must be a debug value instruction.");
-    return isDebugValueList()
-               ? make_range(operands_begin() + 2, operands_end())
-               : make_range(operands_begin(), operands_begin() + 1);
+    assert((isDebugValueLike()) && "Must be a debug value instruction.");
+    return isNonListDebugValue()
+               ? make_range(operands_begin(), operands_begin() + 1)
+               : make_range(operands_begin() + 2, operands_end());
   }
   /// Returns a range over all explicit operands that are register definitions.
   /// Implicit definition are not included!
   iterator_range<mop_iterator> defs() {
     return make_range(operands_begin(),
                       operands_begin() + getNumExplicitDefs());
   }
   /// \copydoc defs()
public:
   bool isDebugValueList() const {
     return getOpcode() == TargetOpcode::DBG_VALUE_LIST;
   }
   bool isDebugValue() const {
     return isNonListDebugValue() || isDebugValueList();
   }
   bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
   bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
+  bool isDebugValueLike() const { return isDebugValue() || isDebugRef(); }
   bool isDebugPHI() const { return getOpcode() == TargetOpcode::DBG_PHI; }
   bool isDebugInstr() const {
     return isDebugValue() || isDebugLabel() || isDebugRef() || isDebugPHI();
   }
   bool isDebugOrPseudoInstr() const {
     return isDebugInstr() || isPseudoProbe();
   }
 
   bool isDebugOffsetImm() const {

llvm/include/llvm/CodeGen/MachineInstrBuilder.h

const MachineInstrBuilder &add(ArrayRef<MachineOperand> MOs) const {
     for (const MachineOperand &MO : MOs) {
       MI->addOperand(*MF, MO);
     }
     return *this;
   }
 
   const MachineInstrBuilder &addMetadata(const MDNode *MD) const {
     MI->addOperand(*MF, MachineOperand::CreateMetadata(MD));
-    assert((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable())
+    assert((MI->isDebugValueLike() ? static_cast<bool>(MI->getDebugVariable())
                                    : true) &&
            "first MDNode argument of a DBG_VALUE not a variable");
     assert((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel())
                                : true) &&
            "first MDNode argument of a DBG_LABEL not a label");
     return *this;
   }
 
   const MachineInstrBuilder &addCFIIndex(unsigned CFIIndex) const {

 /// for either a value in a register or a register-indirect
 /// address.  The convention is that a DBG_VALUE is indirect iff the
 /// second operand is an immediate.
 MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
                             const MCInstrDesc &MCID, bool IsIndirect,
                             Register Reg, const MDNode *Variable,
                             const MDNode *Expr);
 
-/// This version of the builder builds a DBG_VALUE intrinsic
-/// for a MachineOperand.
-MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
-                            const MCInstrDesc &MCID, bool IsIndirect,
-                            const MachineOperand &MO, const MDNode *Variable,
-                            const MDNode *Expr);
-
 /// This version of the builder builds a DBG_VALUE or DBG_VALUE_LIST intrinsic
 /// for a MachineOperand.
 MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
                             const MCInstrDesc &MCID, bool IsIndirect,
                             ArrayRef<MachineOperand> MOs,
                             const MDNode *Variable, const MDNode *Expr);
 
 /// This version of the builder builds a DBG_VALUE intrinsic
 /// for either a value in a register or a register-indirect
 /// address and inserts it at position I.
 MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                             MachineBasicBlock::iterator I, const DebugLoc &DL,
                             const MCInstrDesc &MCID, bool IsIndirect,
                             Register Reg, const MDNode *Variable,
                             const MDNode *Expr);
 
-/// This version of the builder builds a DBG_VALUE intrinsic
-/// for a machine operand and inserts it at position I.
-MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
-                            MachineBasicBlock::iterator I, const DebugLoc &DL,
-                            const MCInstrDesc &MCID, bool IsIndirect,
-                            MachineOperand &MO, const MDNode *Variable,
-                            const MDNode *Expr);
-
-/// This version of the builder builds a DBG_VALUE or DBG_VALUE_LIST intrinsic
-/// for a machine operand and inserts it at position I.
+/// This version of the builder builds a DBG_VALUE, DBG_INSTR_REF, or
+/// DBG_VALUE_LIST intrinsic for a machine operand and inserts it at position I.
 MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                             MachineBasicBlock::iterator I, const DebugLoc &DL,
                             const MCInstrDesc &MCID, bool IsIndirect,
                             ArrayRef<MachineOperand> MOs,
                             const MDNode *Variable, const MDNode *Expr);
 
 /// Clone a DBG_VALUE whose value has been spilled to FrameIndex.
 MachineInstr *buildDbgValueForSpill(MachineBasicBlock &BB,

llvm/include/llvm/CodeGen/MachineOperand.h

enum MachineOperandType : unsigned char {
     MO_JumpTableIndex,    ///< Address of indexed Jump Table for switch
     MO_ExternalSymbol,    ///< Name of external global symbol
     MO_GlobalAddress,     ///< Address of a global value
     MO_BlockAddress,      ///< Address of a basic block
     MO_RegisterMask,      ///< Mask of preserved registers.
     MO_RegisterLiveOut,   ///< Mask of live-out registers.
     MO_Metadata,          ///< Metadata reference (for debug info)
     MO_MCSymbol,          ///< MCSymbol reference (for debug/eh info)
     MO_CFIIndex,          ///< MCCFIInstruction index.
     MO_IntrinsicID,       ///< Intrinsic ID for ISel
     MO_Predicate,         ///< Generic predicate for ISel
     MO_ShuffleMask,       ///< Other IR Constant for ISel (shuffle masks)
-    MO_Last = MO_ShuffleMask
+    MO_DbgInstrRef, ///< Integer indices referring to an instruction+operand
+    MO_Last = MO_DbgInstrRef
   };
 
 private:
   /// OpKind - Specify what kind of operand this is.  This discriminates the
   /// union.
   unsigned OpKind : 8;
 
   /// Subregister number for MO_Register.  A value of 0 indicates the
union ContentsUnion {
     ArrayRef<int> ShuffleMask; // For MO_ShuffleMask
 
     struct {                  // For MO_Register.
       // Register number is in SmallContents.RegNo.
       MachineOperand *Prev;   // Access list for register. See MRI.
       MachineOperand *Next;
     } Reg;
 
+    struct { // For MO_DbgInstrRef.
+      unsigned InstrIdx;
+      unsigned OpIdx;
+    } InstrRef;
+
     /// OffsetedInfo - This struct contains the offset and an object identifier.
     /// this represent the object as with an optional offset from it.
     struct {
       union {
         int Index;                // For MO_*Index - The index itself.
         const char *SymbolName;   // For MO_ExternalSymbol.
         const GlobalValue *GV;    // For MO_GlobalAddress.
         const BlockAddress *BA;   // For MO_BlockAddress.
public:
   bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
   /// isRegMask - Tests if this is a MO_RegisterMask operand.
   bool isRegMask() const { return OpKind == MO_RegisterMask; }
   /// isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
   bool isRegLiveOut() const { return OpKind == MO_RegisterLiveOut; }
   /// isMetadata - Tests if this is a MO_Metadata operand.
   bool isMetadata() const { return OpKind == MO_Metadata; }
   bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
+  bool isDbgInstrRef() const { return OpKind == MO_DbgInstrRef; }
   bool isCFIIndex() const { return OpKind == MO_CFIIndex; }
   bool isIntrinsicID() const { return OpKind == MO_IntrinsicID; }
   bool isPredicate() const { return OpKind == MO_Predicate; }
   bool isShuffleMask() const { return OpKind == MO_ShuffleMask; }
   //===--------------------------------------------------------------------===//
   // Accessors for Register Operands
   //===--------------------------------------------------------------------===//
 
const BlockAddress *getBlockAddress() const {
     return Contents.OffsetedInfo.Val.BA;
   }
 
   MCSymbol *getMCSymbol() const {
     assert(isMCSymbol() && "Wrong MachineOperand accessor");
     return Contents.Sym;
   }
 
+  unsigned getInstrRefInstrIndex() const {
+    assert(isDbgInstrRef() && "Wrong MachineOperand accessor");
+    return Contents.InstrRef.InstrIdx;
+  }
+
+  unsigned getInstrRefOpIndex() const {
+    assert(isDbgInstrRef() && "Wrong MachineOperand accessor");
+    return Contents.InstrRef.OpIdx;
+  }
+
   unsigned getCFIIndex() const {
     assert(isCFIIndex() && "Wrong MachineOperand accessor");
     return Contents.CFIIndex;
   }
 
   Intrinsic::ID getIntrinsicID() const {
     assert(isIntrinsicID() && "Wrong MachineOperand accessor");
     return Contents.IntrinsicID;
void setIndex(int Idx) {
     Contents.OffsetedInfo.Val.Index = Idx;
   }
 
   void setMetadata(const MDNode *MD) {
     assert(isMetadata() && "Wrong MachineOperand mutator");
     Contents.MD = MD;
   }
 
+  void setInstrRefInstrIndex(unsigned InstrIdx) {
+    assert(isDbgInstrRef() && "Wrong MachineOperand mutator");
+    Contents.InstrRef.InstrIdx = InstrIdx;
+  }
+  void setInstrRefOpIndex(unsigned OpIdx) {
+    assert(isDbgInstrRef() && "Wrong MachineOperand mutator");
+    Contents.InstrRef.OpIdx = OpIdx;
+  }
+
   void setMBB(MachineBasicBlock *MBB) {
     assert(isMBB() && "Wrong MachineOperand mutator");
     Contents.MBB = MBB;
   }
 
   /// Sets value of register mask operand referencing Mask.  The
   /// operand does not take ownership of the memory referenced by Mask, it must
   /// remain valid for the lifetime of the operand. See CreateRegMask().
public:
 
   /// Replace this operand with a frame index.
   void ChangeToFrameIndex(int Idx, unsigned TargetFlags = 0);
 
   /// Replace this operand with a target index.
   void ChangeToTargetIndex(unsigned Idx, int64_t Offset,
                            unsigned TargetFlags = 0);
 
+  /// Replace this operand with an Instruction Reference.
+  void ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx,
+                           unsigned TargetFlags = 0);
+
   /// ChangeToRegister - Replace this operand with a new register operand of
   /// the specified value.  If an operand is known to be an register already,
   /// the setReg method should be used.
   void ChangeToRegister(Register Reg, bool isDef, bool isImp = false,
                         bool isKill = false, bool isDead = false,
                         bool isUndef = false, bool isDebug = false);
 
   /// getTargetIndexName - If this MachineOperand is a TargetIndex that has a
static MachineOperand CreateMCSymbol(MCSymbol *Sym,
                                        unsigned TargetFlags = 0) {
     MachineOperand Op(MachineOperand::MO_MCSymbol);
     Op.Contents.Sym = Sym;
     Op.setOffset(0);
     Op.setTargetFlags(TargetFlags);
     return Op;
   }
 
+  static MachineOperand CreateDbgInstrRef(unsigned InstrIdx, unsigned OpIdx) {
+    MachineOperand Op(MachineOperand::MO_DbgInstrRef);
+    Op.Contents.InstrRef.InstrIdx = InstrIdx;
+    Op.Contents.InstrRef.OpIdx = OpIdx;
+    return Op;
+  }
+
   static MachineOperand CreateCFIIndex(unsigned CFIIndex) {
     MachineOperand Op(MachineOperand::MO_CFIIndex);
     Op.Contents.CFIIndex = CFIIndex;
     return Op;
   }
 
   static MachineOperand CreateIntrinsicID(Intrinsic::ID ID) {
     MachineOperand Op(MachineOperand::MO_IntrinsicID);

llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h

public:
   DbgValueProperties EmptyProperties;
 
 public:
   VLocTracker(const OverlapMap &O, const DIExpression *EmptyExpr)
       : OverlappingFragments(O), EmptyProperties(EmptyExpr, false, false) {}
 
   void defVar(const MachineInstr &MI, const DbgValueProperties &Properties,
               const SmallVectorImpl<DbgOpID> &DebugOps) {
-    assert(MI.isDebugValue() || MI.isDebugRef());
+    assert(MI.isDebugValueLike());
     DebugVariable Var(MI.getDebugVariable(), MI.getDebugExpression(),
                       MI.getDebugLoc()->getInlinedAt());
     DbgValue Rec = (DebugOps.size() > 0)
                        ? DbgValue(DebugOps, Properties)
                        : DbgValue(Properties, DbgValue::Undef);
 
     // Attempt insertion; overwrite if it's already mapped.
     auto Result = Vars.insert(std::make_pair(Var, Rec));

llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp

InstrRefBasedLDV::findLocationForMemOperand(const MachineInstr &MI) {
   return MTracker->getSpillMLoc(SpillID);
 }
 
 /// End all previous ranges related to @MI and start a new range from @MI
 /// if it is a DBG_VALUE instr.
 bool InstrRefBasedLDV::transferDebugValue(const MachineInstr &MI) {
   if (!MI.isDebugValue())
     return false;
 
   const DILocalVariable *Var = MI.getDebugVariable();
   const DIExpression *Expr = MI.getDebugExpression();
   const DILocation *DebugLoc = MI.getDebugLoc();
   const DILocation *InlinedAt = DebugLoc->getInlinedAt();
   assert(Var->isValidLocationForIntrinsic(DebugLoc) &&
          "Expected inlined-at fields to agree");
 
   DebugVariable V(Var, Expr, InlinedAt);
bool InstrRefBasedLDV::transferDebugInstrRef(MachineInstr &MI,
   if (!MI.isDebugRef())
     return false;
 
   // Only handle this instruction when we are building the variable value
   // transfer function.
   if (!VTracker && !TTracker)
     return false;
 
-  unsigned InstNo = MI.getOperand(0).getImm();
-  unsigned OpNo = MI.getOperand(1).getImm();
+  unsigned InstNo = MI.getDebugOperand(0).getInstrRefInstrIndex();
+  unsigned OpNo = MI.getDebugOperand(0).getInstrRefOpIndex();
 
   const DILocalVariable *Var = MI.getDebugVariable();
   const DIExpression *Expr = MI.getDebugExpression();
   const DILocation *DebugLoc = MI.getDebugLoc();
   const DILocation *InlinedAt = DebugLoc->getInlinedAt();
   assert(Var->isValidLocationForIntrinsic(DebugLoc) &&
          "Expected inlined-at fields to agree");
 

 
 /// Accumulate a mapping between each DILocalVariable fragment and other
 /// fragments of that DILocalVariable which overlap. This reduces work during
 /// the data-flow stage from "Find any overlapping fragments" to "Check if the
 /// known-to-overlap fragments are present".
 /// \param MI A previously unprocessed debug instruction to analyze for
 ///           fragment usage.
 void InstrRefBasedLDV::accumulateFragmentMap(MachineInstr &MI) {
-  assert(MI.isDebugValue() || MI.isDebugRef());
+  assert(MI.isDebugValueLike());
   DebugVariable MIVar(MI.getDebugVariable(), MI.getDebugExpression(),
                       MI.getDebugLoc()->getInlinedAt());
   FragmentInfo ThisFragment = MIVar.getFragmentOrDefault();
 
   // If this is the first sighting of this variable, then we are guaranteed
   // there are currently no overlapping fragments either. Initialize the set
   // of seen fragments, record no overlaps for the current one, and return.
   auto SeenIt = SeenFragments.find(MIVar.getVariable());
for (auto &MBB : MF) {
 
     // Step through each instruction in this block.
     for (auto &MI : MBB) {
       // Pass in an empty unique_ptr for the value tables when accumulating the
       // machine transfer function.
       process(MI, nullptr, nullptr);
 
       // Also accumulate fragment map.
-      if (MI.isDebugValue() || MI.isDebugRef())
+      if (MI.isDebugValueLike())
         accumulateFragmentMap(MI);
 
       // Create a map from the instruction number (if present) to the
       // MachineInstr and its position.
       if (uint64_t InstrNo = MI.peekDebugInstrNum()) {
         auto InstrAndPos = std::make_pair(&MI, CurInst);
         auto InsertResult =
             DebugInstrNumToInstr.insert(std::make_pair(InstrNo, InstrAndPos));

llvm/lib/CodeGen/LiveDebugVariables.cpp

else {
     SmallVector<MachineOperand, 4> UndefMOs(MI.getNumDebugOperands(), MO);
     UV->addDef(Idx, UndefMOs, false, IsList, *Expr);
   }
   return true;
 }
 
 MachineBasicBlock::iterator LDVImpl::handleDebugInstr(MachineInstr &MI,
                                                       SlotIndex Idx) {
-  assert(MI.isDebugValue() || MI.isDebugRef() || MI.isDebugPHI());
+  assert(MI.isDebugValueLike() || MI.isDebugPHI());
 
   // In instruction referencing mode, there should be no DBG_VALUE instructions
   // that refer to virtual registers. They might still refer to constants.
-  if (MI.isDebugValue())
-    assert(!MI.getOperand(0).isReg() || !MI.getOperand(0).getReg().isVirtual());
+  if (MI.isDebugValueLike())
+    assert(none_of(MI.debug_operands(),
+                   [](const MachineOperand &MO) {
+                     return MO.isReg() && MO.getReg().isVirtual();
+                   }) &&
+           "MIs should not refer to Virtual Registers in InstrRef mode.");
 
   // Unlink the instruction, store it in the debug instructions collection.
   auto NextInst = std::next(MI.getIterator());
   auto *MBB = MI.getParent();
   MI.removeFromParent();
   StashedDebugInstrs.push_back({&MI, Idx, MBB});
   return NextInst;
 }

llvm/lib/CodeGen/MIRParser/MILexer.h

enum TokenKind {
     kw_afn,
     kw_reassoc,
     kw_nuw,
     kw_nsw,
     kw_exact,
     kw_nofpexcept,
     kw_debug_location,
     kw_debug_instr_number,
+    kw_dbg_instr_ref,
     kw_cfi_same_value,
     kw_cfi_offset,
     kw_cfi_rel_offset,
     kw_cfi_def_cfa_register,
     kw_cfi_def_cfa_offset,
     kw_cfi_adjust_cfa_offset,
     kw_cfi_escape,
     kw_cfi_def_cfa,

llvm/lib/CodeGen/MIRParser/MILexer.cpp

return StringSwitch<MIToken::TokenKind>(Identifier)
       .Case("afn", MIToken::kw_afn)
       .Case("reassoc", MIToken::kw_reassoc)
       .Case("nuw", MIToken::kw_nuw)
       .Case("nsw", MIToken::kw_nsw)
       .Case("exact", MIToken::kw_exact)
       .Case("nofpexcept", MIToken::kw_nofpexcept)
       .Case("debug-location", MIToken::kw_debug_location)
       .Case("debug-instr-number", MIToken::kw_debug_instr_number)
+      .Case("dbg-instr-ref", MIToken::kw_dbg_instr_ref)
       .Case("same_value", MIToken::kw_cfi_same_value)
       .Case("offset", MIToken::kw_cfi_offset)
       .Case("rel_offset", MIToken::kw_cfi_rel_offset)
       .Case("def_cfa_register", MIToken::kw_cfi_def_cfa_register)
       .Case("def_cfa_offset", MIToken::kw_cfi_def_cfa_offset)
       .Case("adjust_cfa_offset", MIToken::kw_cfi_adjust_cfa_offset)
       .Case("escape", MIToken::kw_cfi_escape)
       .Case("def_cfa", MIToken::kw_cfi_def_cfa)
return StringSwitch<MIToken::TokenKind>(Identifier)
       .Case("pcsections", MIToken::kw_pcsections)
       .Case("cfi-type", MIToken::kw_cfi_type)
       .Case("bbsections", MIToken::kw_bbsections)
       .Case("unknown-size", MIToken::kw_unknown_size)
       .Case("unknown-address", MIToken::kw_unknown_address)
       .Case("distinct", MIToken::kw_distinct)
       .Case("ir-block-address-taken", MIToken::kw_ir_block_address_taken)
       .Case("machine-block-address-taken", MIToken::kw_machine_block_address_taken)
       .Default(MIToken::Identifier);
 }
 
 static Cursor maybeLexIdentifier(Cursor C, MIToken &Token) {
   if (!isalpha(C.peek()) && C.peek() != '_')
     return std::nullopt;
   auto Range = C;
   while (isIdentifierChar(C.peek()))
     C.advance();

llvm/lib/CodeGen/MIRParser/MIParser.cpp

public:
   bool parseCFIEscapeValues(std::string& Values);
   bool parseCFIOperand(MachineOperand &Dest);
   bool parseIRBlock(BasicBlock *&BB, const Function &F);
   bool parseBlockAddressOperand(MachineOperand &Dest);
   bool parseIntrinsicOperand(MachineOperand &Dest);
   bool parsePredicateOperand(MachineOperand &Dest);
   bool parseShuffleMaskOperand(MachineOperand &Dest);
   bool parseTargetIndexOperand(MachineOperand &Dest);
+  bool parseDbgInstrRefOperand(MachineOperand &Dest);
   bool parseCustomRegisterMaskOperand(MachineOperand &Dest);
   bool parseLiveoutRegisterMaskOperand(MachineOperand &Dest);
   bool parseMachineOperand(const unsigned OpCode, const unsigned OpIdx,
                            MachineOperand &Dest,
                            std::optional<unsigned> &TiedDefIdx);
   bool parseMachineOperandAndTargetFlags(const unsigned OpCode,
                                          const unsigned OpIdx,
                                          MachineOperand &Dest,
bool MIParser::parseShuffleMaskOperand(MachineOperand &Dest) {
   if (expectAndConsume(MIToken::rparen))
     return error("shufflemask should be terminated by ')'.");
 
   ArrayRef<int> MaskAlloc = MF.allocateShuffleMask(ShufMask);
   Dest = MachineOperand::CreateShuffleMask(MaskAlloc);
   return false;
 }
 
+bool MIParser::parseDbgInstrRefOperand(MachineOperand &Dest) {
+  assert(Token.is(MIToken::kw_dbg_instr_ref));
+
+  lex();
+  if (expectAndConsume(MIToken::lparen))
+    return error("expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
+
+  if (Token.isNot(MIToken::IntegerLiteral) || Token.integerValue().isNegative())
+    return error("expected unsigned integer for instruction index");
+  uint64_t InstrIdx = Token.integerValue().getZExtValue();
+  assert(InstrIdx <= std::numeric_limits<unsigned>::max() &&
+         "Instruction reference's instruction index is too large");
+  lex();
+
+  if (expectAndConsume(MIToken::comma))
+    return error("expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
+
+  if (Token.isNot(MIToken::IntegerLiteral) || Token.integerValue().isNegative())
+    return error("expected unsigned integer for operand index");
+  uint64_t OpIdx = Token.integerValue().getZExtValue();
+  assert(OpIdx <= std::numeric_limits<unsigned>::max() &&
+         "Instruction reference's operand index is too large");
+  lex();
+
+  if (expectAndConsume(MIToken::rparen))
+    return error("expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
+
+  Dest = MachineOperand::CreateDbgInstrRef(InstrIdx, OpIdx);
+  return false;
+}
+
 bool MIParser::parseTargetIndexOperand(MachineOperand &Dest) {
   assert(Token.is(MIToken::kw_target_index));
   lex();
   if (expectAndConsume(MIToken::lparen))
     return true;
   if (Token.isNot(MIToken::Identifier))
     return error("expected the name of the target index");
   int Index = 0;
case MIToken::kw_target_index:
     return parseTargetIndexOperand(Dest);
   case MIToken::kw_liveout:
     return parseLiveoutRegisterMaskOperand(Dest);
   case MIToken::kw_floatpred:
   case MIToken::kw_intpred:
     return parsePredicateOperand(Dest);
   case MIToken::kw_shufflemask:
     return parseShuffleMaskOperand(Dest);
+  case MIToken::kw_dbg_instr_ref:
+    return parseDbgInstrRefOperand(Dest);
   case MIToken::Error:
     return true;
   case MIToken::Identifier:
     if (const auto *RegMask = PFS.Target.getRegMask(Token.stringValue())) {
       Dest = MachineOperand::CreateRegMask(RegMask);
       lex();
       break;
     } else if (Token.stringValue() == "CustomRegMask") {

llvm/lib/CodeGen/MIRPrinter.cpp

void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
   case MachineOperand::MO_GlobalAddress:
   case MachineOperand::MO_RegisterLiveOut:
   case MachineOperand::MO_Metadata:
   case MachineOperand::MO_MCSymbol:
   case MachineOperand::MO_CFIIndex:
   case MachineOperand::MO_IntrinsicID:
   case MachineOperand::MO_Predicate:
   case MachineOperand::MO_BlockAddress:
+  case MachineOperand::MO_DbgInstrRef:
   case MachineOperand::MO_ShuffleMask: {
     unsigned TiedOperandIdx = 0;
     if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
     const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
     Op.print(OS, MST, TypeToPrint, OpIdx, PrintDef, /*IsStandalone=*/false,
              ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII);
       OS << formatOperandComment(MOComment);

llvm/lib/CodeGen/MIRVRegNamerUtils.cpp

auto GetHashableMO = [this](const MachineOperand &MO) -> unsigned {
     case MachineOperand::MO_ExternalSymbol:
     case MachineOperand::MO_GlobalAddress:
     case MachineOperand::MO_BlockAddress:
     case MachineOperand::MO_RegisterMask:
     case MachineOperand::MO_RegisterLiveOut:
     case MachineOperand::MO_Metadata:
     case MachineOperand::MO_MCSymbol:
     case MachineOperand::MO_ShuffleMask:
+    case MachineOperand::MO_DbgInstrRef:
       return 0;
     }
     llvm_unreachable("Unexpected MachineOperandType.");
   };
 
   SmallVector<unsigned, 16> MIOperands = {MI.getOpcode(), MI.getFlags()};
   llvm::transform(MI.uses(), std::back_inserter(MIOperands), GetHashableMO);
 

llvm/lib/CodeGen/MachineFunction.cpp

auto MachineFunction::salvageCopySSAImpl(MachineInstr &MI)
   Builder.addImm(NewNum);
   return ApplySubregisters({NewNum, 0u});
 }
 
 void MachineFunction::finalizeDebugInstrRefs() {
   auto *TII = getSubtarget().getInstrInfo();
 
   auto MakeUndefDbgValue = [&](MachineInstr &MI) {
-    const MCInstrDesc &RefII = TII->get(TargetOpcode::DBG_VALUE);
+    const MCInstrDesc &RefII = TII->get(TargetOpcode::DBG_VALUE_LIST);
     MI.setDesc(RefII);
-    MI.getOperand(0).setReg(0);
-    MI.getOperand(1).ChangeToRegister(0, false);
+    MI.getDebugOperand(0).setReg(0);
   };
 
   DenseMap<Register, DebugInstrOperandPair> ArgDbgPHIs;
   for (auto &MBB : *this) {
     for (auto &MI : MBB) {
-      if (!MI.isDebugRef() || !MI.getOperand(0).isReg())
+      if (!MI.isDebugRef() || !MI.getDebugOperand(0).isReg())
         continue;
 
-      Register Reg = MI.getOperand(0).getReg();
+      Register Reg = MI.getDebugOperand(0).getReg();
 
       // Some vregs can be deleted as redundant in the meantime. Mark those
       // as DBG_VALUE $noreg. Additionally, some normal instructions are
       // quickly deleted, leaving dangling references to vregs with no def.
       if (Reg == 0 || !RegInfo->hasOneDef(Reg)) {
         MakeUndefDbgValue(MI);
         continue;
       }
 
       assert(Reg.isVirtual());
       MachineInstr &DefMI = *RegInfo->def_instr_begin(Reg);
 
       // If we've found a copy-like instruction, follow it back to the
       // instruction that defines the source value, see salvageCopySSA docs
       // for why this is important.
       if (DefMI.isCopyLike() || TII->isCopyInstr(DefMI)) {
         auto Result = salvageCopySSA(DefMI, ArgDbgPHIs);
-        MI.getOperand(0).ChangeToImmediate(Result.first);
-        MI.getOperand(1).setImm(Result.second);
+        MI.getDebugOperand(0).ChangeToDbgInstrRef(Result.first, Result.second);
       } else {
         // Otherwise, identify the operand number that the VReg refers to.
         unsigned OperandIdx = 0;
         for (const auto &MO : DefMI.operands()) {
           if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
             break;
           ++OperandIdx;
         }
         assert(OperandIdx < DefMI.getNumOperands());
 
         // Morph this instr ref to point at the given instruction and operand.
         unsigned ID = DefMI.getDebugInstrNum();
-        MI.getOperand(0).ChangeToImmediate(ID);
-        MI.getOperand(1).setImm(OperandIdx);
+        MI.getDebugOperand(0).ChangeToDbgInstrRef(ID, OperandIdx);
       }
     }
   }
 }
 
 bool MachineFunction::useDebugInstrRef() const {
   // Disable instr-ref at -O0: it's very slow (in compile time). We can still
   // have optimized code inlined into this unoptimized code, however with

llvm/lib/CodeGen/MachineInstr.cpp

bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
   // Call instructions with different CFI types are not identical.
   if (isCall() && getCFIType() != Other.getCFIType())
     return false;
 
   return true;
 }
 
 bool MachineInstr::isEquivalentDbgInstr(const MachineInstr &Other) const {
-  if (!isDebugValue() || !Other.isDebugValue())
+  if (!isDebugValueLike() || !Other.isDebugValueLike())
     return false;
   if (getDebugLoc() != Other.getDebugLoc())
     return false;
   if (getDebugVariable() != Other.getDebugVariable())
     return false;
   if (getNumDebugOperands() != Other.getNumDebugOperands())
     return false;
   for (unsigned OpIdx = 0; OpIdx < getNumDebugOperands(); ++OpIdx)

 }
 
 const DILabel *MachineInstr::getDebugLabel() const {
   assert(isDebugLabel() && "not a DBG_LABEL");
   return cast<DILabel>(getOperand(0).getMetadata());
 }
 
 const MachineOperand &MachineInstr::getDebugVariableOp() const {
-  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
-  unsigned VariableOp = isDebugValueList() ? 0 : 2;
+  assert((isDebugValueLike()) && "not a DBG_VALUE*");
+  unsigned VariableOp = isNonListDebugValue() ? 2 : 0;
   return getOperand(VariableOp);
 }
 
 MachineOperand &MachineInstr::getDebugVariableOp() {
-  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
-  unsigned VariableOp = isDebugValueList() ? 0 : 2;
+  assert((isDebugValueLike()) && "not a DBG_VALUE*");
+  unsigned VariableOp = isNonListDebugValue() ? 2 : 0;
   return getOperand(VariableOp);
 }
 
 const DILocalVariable *MachineInstr::getDebugVariable() const {
   return cast<DILocalVariable>(getDebugVariableOp().getMetadata());
 }
 
 const MachineOperand &MachineInstr::getDebugExpressionOp() const {
-  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
-  unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
+  assert((isDebugValueLike()) && "not a DBG_VALUE*");
+  unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1;
   return getOperand(ExpressionOp);
 }
 
 MachineOperand &MachineInstr::getDebugExpressionOp() {
-  assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
-  unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
+  assert((isDebugValueLike()) && "not a DBG_VALUE*");
+  unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1;
   return getOperand(ExpressionOp);
 }
 
 const DIExpression *MachineInstr::getDebugExpression() const {
   return cast<DIExpression>(getDebugExpressionOp().getMetadata());
 }
 
 bool MachineInstr::isDebugEntryValue() const {
if (IsIndirect)
     MIB.addImm(0U);
   else
     MIB.addReg(0U);
   return MIB.addMetadata(Variable).addMetadata(Expr);
 }
 
 MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
                                   const MCInstrDesc &MCID, bool IsIndirect,
-                                  const MachineOperand &MO,
+                                  ArrayRef<MachineOperand> DebugOps,
                                   const MDNode *Variable, const MDNode *Expr) {
   assert(isa<DILocalVariable>(Variable) && "not a variable");
   assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
   assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
          "Expected inlined-at fields to agree");
-  if (MO.isReg())
-    return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
+  if (MCID.Opcode == TargetOpcode::DBG_VALUE) {
+    assert(DebugOps.size() == 1 &&
+           "DBG_VALUE must contain exactly one debug operand");
+    MachineOperand DebugOp = DebugOps[0];
+    if (DebugOp.isReg())
+      return BuildMI(MF, DL, MCID, IsIndirect, DebugOp.getReg(), Variable,
+                     Expr);
 
-  auto MIB = BuildMI(MF, DL, MCID).add(MO);
+    auto MIB = BuildMI(MF, DL, MCID).add(DebugOp);
     if (IsIndirect)
       MIB.addImm(0U);
     else
       MIB.addReg(0U);
     return MIB.addMetadata(Variable).addMetadata(Expr);
   }
 
-MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
-                                  const MCInstrDesc &MCID, bool IsIndirect,
-                                  ArrayRef<MachineOperand> MOs,
-                                  const MDNode *Variable, const MDNode *Expr) {
-  assert(isa<DILocalVariable>(Variable) && "not a variable");
-  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
-  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
-         "Expected inlined-at fields to agree");
-  if (MCID.Opcode == TargetOpcode::DBG_VALUE)
-    return BuildMI(MF, DL, MCID, IsIndirect, MOs[0], Variable, Expr);
-
   auto MIB = BuildMI(MF, DL, MCID);
   MIB.addMetadata(Variable).addMetadata(Expr);
-  for (const MachineOperand &MO : MOs)
-    if (MO.isReg())
-      MIB.addReg(MO.getReg());
+  for (const MachineOperand &DebugOp : DebugOps)
+    if (DebugOp.isReg())
+      MIB.addReg(DebugOp.getReg());
     else
-      MIB.add(MO);
+      MIB.add(DebugOp);
   return MIB;
 }
 
 MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
                                   MachineBasicBlock::iterator I,
                                   const DebugLoc &DL, const MCInstrDesc &MCID,
                                   bool IsIndirect, Register Reg,
                                   const MDNode *Variable, const MDNode *Expr) {
   MachineFunction &MF = *BB.getParent();
   MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
   BB.insert(I, MI);
   return MachineInstrBuilder(MF, MI);
 }
 
 MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
                                   MachineBasicBlock::iterator I,
                                   const DebugLoc &DL, const MCInstrDesc &MCID,
-                                  bool IsIndirect, MachineOperand &MO,
-                                  const MDNode *Variable, const MDNode *Expr) {
-  MachineFunction &MF = *BB.getParent();
-  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
-  BB.insert(I, MI);
-  return MachineInstrBuilder(MF, *MI);
-}
-
-MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
-                                  MachineBasicBlock::iterator I,
-                                  const DebugLoc &DL, const MCInstrDesc &MCID,
-                                  bool IsIndirect, ArrayRef<MachineOperand> MOs,
+                                  bool IsIndirect,
+                                  ArrayRef<MachineOperand> DebugOps,
                                   const MDNode *Variable, const MDNode *Expr) {
   MachineFunction &MF = *BB.getParent();
-  MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MOs, Variable, Expr);
+  MachineInstr *MI =
+      BuildMI(MF, DL, MCID, IsIndirect, DebugOps, Variable, Expr);
   BB.insert(I, MI);
   return MachineInstrBuilder(MF, *MI);
 }
 
 /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
 /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
 static const DIExpression *
 computeExprForSpill(const MachineInstr &MI,
for (const MachineOperand &Op : MI.getDebugOperandsForReg(SpillReg))
     SpillOperands.push_back(&Op);
   return computeExprForSpill(MI, SpillOperands);
 }
 
 MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
                                           MachineBasicBlock::iterator I,
                                           const MachineInstr &Orig,
                                           int FrameIndex, Register SpillReg) {
+  assert(!Orig.isDebugRef() &&
+         "DBG_INSTR_REF should not reference a virtual register.");
   const DIExpression *Expr = computeExprForSpill(Orig, SpillReg);
   MachineInstrBuilder NewMI =
       BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
   // Non-Variadic Operands: Location, Offset, Variable, Expression
   // Variadic Operands:     Variable, Expression, Locations...
   if (Orig.isNonListDebugValue())
     NewMI.addFrameIndex(FrameIndex).addImm(0U);
   NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);

llvm/lib/CodeGen/MachineOperand.cpp

void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
   removeRegFromUses();
 
   OpKind = MO_TargetIndex;
   setIndex(Idx);
   setOffset(Offset);
   setTargetFlags(TargetFlags);
 }
 
+void MachineOperand::ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx,
+                                         unsigned TargetFlags) {
+  assert((!isReg() || !isTied()) &&
+         "Cannot change a tied operand into a DbgInstrRef");
+
+  removeRegFromUses();
+
+  OpKind = MO_DbgInstrRef;
+  setInstrRefInstrIndex(InstrIdx);
+  setInstrRefOpIndex(OpIdx);
+  setTargetFlags(TargetFlags);
+}
+
 /// ChangeToRegister - Replace this operand with a new register operand of
 /// the specified value.  If an operand is known to be an register already,
 /// the setReg method should be used.
 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
                                       bool isKill, bool isDead, bool isUndef,
                                       bool isDebug) {
   MachineRegisterInfo *RegInfo = nullptr;
   if (MachineFunction *MF = getMFIfAvailable(*this))
if (const MachineFunction *MF = getMFIfAvailable(*this)) {
       return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
     }
     // We don't know the size of the RegMask, so we can't deep compare the two
     // reg masks.
     return false;
   }
   case MachineOperand::MO_MCSymbol:
     return getMCSymbol() == Other.getMCSymbol();
+  case MachineOperand::MO_DbgInstrRef:
+    return getInstrRefInstrIndex() == Other.getInstrRefInstrIndex() &&
+           getInstrRefOpIndex() == Other.getInstrRefOpIndex();
   case MachineOperand::MO_CFIIndex:
     return getCFIIndex() == Other.getCFIIndex();
   case MachineOperand::MO_Metadata:
     return getMetadata() == Other.getMetadata();
   case MachineOperand::MO_IntrinsicID:
     return getIntrinsicID() == Other.getIntrinsicID();
   case MachineOperand::MO_Predicate:
     return getPredicate() == Other.getPredicate();
case MachineOperand::MO_RegisterLiveOut: {
 
     assert(0 && "MachineOperand not associated with any MachineFunction");
     return hash_combine(MO.getType(), MO.getTargetFlags());
   }
   case MachineOperand::MO_Metadata:
     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
   case MachineOperand::MO_MCSymbol:
     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
+  case MachineOperand::MO_DbgInstrRef:
+    return hash_combine(MO.getType(), MO.getTargetFlags(),
+                        MO.getInstrRefInstrIndex(), MO.getInstrRefOpIndex());
   case MachineOperand::MO_CFIIndex:
     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
   case MachineOperand::MO_IntrinsicID:
     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
   case MachineOperand::MO_Predicate:
     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
   case MachineOperand::MO_ShuffleMask:
     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
case MachineOperand::MO_RegisterLiveOut: {
     break;
   }
   case MachineOperand::MO_Metadata:
     getMetadata()->printAsOperand(OS, MST);
     break;
   case MachineOperand::MO_MCSymbol:
     printSymbol(OS, *getMCSymbol());
     break;
+  case MachineOperand::MO_DbgInstrRef: {
+    OS << "dbg-instr-ref(" << getInstrRefInstrIndex() << ", "
+       << getInstrRefOpIndex() << ')';
+    break;
+  }
   case MachineOperand::MO_CFIIndex: {
     if (const MachineFunction *MF = getMFIfAvailable(*this))
       printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
     else
       OS << "<cfi directive>";
     break;
   }
   case MachineOperand::MO_IntrinsicID: {

llvm/lib/CodeGen/MachineSink.cpp

bool MachineSinking::ProcessBlock(MachineBasicBlock &MBB) {
   return MadeChange;
 }
 
 void MachineSinking::ProcessDbgInst(MachineInstr &MI) {
   // When we see DBG_VALUEs for registers, record any vreg it reads, so that
   // we know what to sink if the vreg def sinks.
   assert(MI.isDebugValue() && "Expected DBG_VALUE for processing");
 
   DebugVariable Var(MI.getDebugVariable(), MI.getDebugExpression(),
                     MI.getDebugLoc()->getInlinedAt());
   bool SeenBefore = SeenDbgVars.contains(Var);
 
   for (MachineOperand &MO : MI.debug_operands()) {
     if (MO.isReg() && MO.getReg().isVirtual())
       SeenDbgUsers[MO.getReg()].push_back(SeenDbgUser(&MI, SeenBefore));
   }
 
   // Record the variable for any DBG_VALUE, to avoid re-ordering any of them.
   SeenDbgVars.insert(Var);
 }
bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
   for (MachineInstr &MI : llvm::make_early_inc_range(llvm::reverse(CurBB))) {
     // Track the operand index for use in Copy.
     SmallVector<unsigned, 2> UsedOpsInCopy;
     // Track the register number defed in Copy.
     SmallVector<unsigned, 2> DefedRegsInCopy;
 
     // We must sink this DBG_VALUE if its operand is sunk. To avoid searching
     // for DBG_VALUEs later, record them when they're encountered.
-    if (MI.isDebugValue()) {
+    if (MI.isDebugValue() && !MI.isDebugRef()) {
       SmallDenseMap<MCRegister, SmallVector<unsigned, 2>, 4> MIUnits;
       bool IsValid = true;
       for (MachineOperand &MO : MI.debug_operands()) {
         if (MO.isReg() && Register::isPhysicalRegister(MO.getReg())) {
           // Bail if we can already tell the sink would be rejected, rather
           // than needlessly accumulating lots of DBG_VALUEs.
           if (hasRegisterDependency(&MI, UsedOpsInCopy, DefedRegsInCopy,
                                     ModifiedRegUnits, UsedRegUnits)) {

llvm/lib/CodeGen/MachineStableHash.cpp

case MachineOperand::MO_CFIIndex:
     return stable_hash_combine(MO.getType(), MO.getTargetFlags(),
                                MO.getCFIIndex());
   case MachineOperand::MO_IntrinsicID:
     return stable_hash_combine(MO.getType(), MO.getTargetFlags(),
                                MO.getIntrinsicID());
   case MachineOperand::MO_Predicate:
     return stable_hash_combine(MO.getType(), MO.getTargetFlags(),
                                MO.getPredicate());
+  case MachineOperand::MO_DbgInstrRef:
+    return stable_hash_combine(MO.getType(), MO.getInstrRefInstrIndex(),
+                               MO.getInstrRefOpIndex());
   }
   llvm_unreachable("Invalid machine operand type");
 }
 
 /// A stable hash value for machine instructions.
 /// Returns 0 if no stable hash could be computed.
 /// The hashing and equality testing functions ignore definitions so this is
 /// useful for CSE, etc.

llvm/lib/CodeGen/SelectionDAG/FastISel.cpp

if (!Op && !Address->use_empty() && isa<Instruction>(Address) &&
         (!isa<AllocaInst>(Address) ||
          !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(Address))))
       Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address),
                                      false);
 
     if (Op) {
       assert(DI->getVariable()->isValidLocationForIntrinsic(MIMD.getDL()) &&
              "Expected inlined-at fields to agree");
+      if (UseInstrRefDebugInfo && Op->isReg()) {
+        // If using instruction referencing, produce this as a DBG_INSTR_REF,
+        // to be later patched up by finalizeDebugInstrRefs. Tack a deref onto
+        // the expression, we don't have an "indirect" flag in DBG_INSTR_REF.
+        auto *NewExpr =
+           DIExpression::prepend(DI->getExpression(), DIExpression::DerefBefore);
+        BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD.getDL(),
+                TII.get(TargetOpcode::DBG_INSTR_REF), /*IsIndirect*/ false, *Op,
+                DI->getVariable(), NewExpr);
+      } else {
         // A dbg.declare describes the address of a source variable, so lower it
         // into an indirect DBG_VALUE.
-      auto Builder =
-          BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD.getDL(),
-                  TII.get(TargetOpcode::DBG_VALUE), /*IsIndirect*/ true, *Op,
-                  DI->getVariable(), DI->getExpression());
-
-      // If using instruction referencing, mutate this into a DBG_INSTR_REF,
-      // to be later patched up by finalizeDebugInstrRefs. Tack a deref onto
-      // the expression, we don't have an "indirect" flag in DBG_INSTR_REF.
-      if (UseInstrRefDebugInfo && Op->isReg()) {
-        Builder->setDesc(TII.get(TargetOpcode::DBG_INSTR_REF));
-        Builder->getOperand(1).ChangeToImmediate(0);
-        auto *NewExpr =
-           DIExpression::prepend(DI->getExpression(), DIExpression::DerefBefore);
-        Builder->getOperand(3).setMetadata(NewExpr);
       }
     } else {
       // We can't yet handle anything else here because it would require
       // generating code, thus altering codegen because of debug info.
       LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI
                         << " (no materialized reg for address)\n");
     }
     return true;
case Intrinsic::dbg_value: {
     } else if (const auto *CF = dyn_cast<ConstantFP>(V)) {
       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
           .addFPImm(CF)
           .addImm(0U)
           .addMetadata(DI->getVariable())
           .addMetadata(DI->getExpression());
     } else if (Register Reg = lookUpRegForValue(V)) {
       // FIXME: This does not handle register-indirect values at offset 0.
+      if (!UseInstrRefDebugInfo) {
         bool IsIndirect = false;
-      auto Builder =
-          BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD.getDL(), II,
-                  IsIndirect, Reg, DI->getVariable(), DI->getExpression());
-
-      // If using instruction referencing, mutate this into a DBG_INSTR_REF,
+        BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD.getDL(), II, IsIndirect,
+                Reg, DI->getVariable(), DI->getExpression());
+      } else {
+        // If using instruction referencing, produce this as a DBG_INSTR_REF,
         // to be later patched up by finalizeDebugInstrRefs.
-      if (UseInstrRefDebugInfo) {
-        Builder->setDesc(TII.get(TargetOpcode::DBG_INSTR_REF));
-        Builder->getOperand(1).ChangeToImmediate(0);
+        SmallVector<MachineOperand, 1> MOs({MachineOperand::CreateReg(
+            /* Reg */ Reg, /* isDef */ false, /* isImp */ false,
+            /* isKill */ false, /* isDead */ false,
+            /* isUndef */ false, /* isEarlyClobber */ false,
+            /* SubReg */ 0, /* isDebug */ true)});
+        BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD.getDL(),
+                TII.get(TargetOpcode::DBG_INSTR_REF), /*IsIndirect*/ false, MOs,
+                DI->getVariable(), DI->getExpression());
       }
     } else {
       // We don't know how to handle other cases, so we drop.
       LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
     }
     return true;
   }
   case Intrinsic::dbg_label: {

llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD,
   // emitted in. When this happens, or when further analysis is needed later,
   // produce an instruction like this:
   //
   //    DBG_INSTR_REF %0:gr64, 0, !123, !456
   //
   // i.e., point the instruction at the vreg, and patch it up later in
   // MachineFunction::finalizeDebugInstrRefs.
   auto EmitHalfDoneInstrRef = [&](unsigned VReg) -> MachineInstr * {
-    auto MIB = BuildMI(*MF, DL, RefII);
-    MIB.addReg(VReg);
-    MIB.addImm(0);
-    MIB.addMetadata(Var);
-    MIB.addMetadata(Expr);
-    return MIB;
+    SmallVector<MachineOperand, 1> MOs({MachineOperand::CreateReg(
+        /* Reg */ VReg, /* isDef */ false, /* isImp */ false,
+        /* isKill */ false, /* isDead */ false,
+        /* isUndef */ false, /* isEarlyClobber */ false,
+        /* SubReg */ 0, /* isDebug */ true)});
+    return BuildMI(*MF, DL, RefII, false, MOs, Var, Expr);
   };
 
   // Try to find both the defined register and the instruction defining it.
   MachineInstr *DefMI = nullptr;
   unsigned VReg;
 
   if (DbgOperand.getKind() == SDDbgOperand::VREG) {
     VReg = DbgOperand.getVReg();
InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD,
   }
 
   // Avoid copy like instructions: they don't define values, only move them.
   // Leave a virtual-register reference until it can be fixed up later, to find
   // the underlying value definition.
   if (DefMI->isCopyLike() || TII->isCopyInstr(*DefMI))
     return EmitHalfDoneInstrRef(VReg);
 
-  auto MIB = BuildMI(*MF, DL, RefII);
-
   // Find the operand number which defines the specified VReg.
   unsigned OperandIdx = 0;
   for (const auto &MO : DefMI->operands()) {
     if (MO.isReg() && MO.isDef() && MO.getReg() == VReg)
       break;
     ++OperandIdx;
   }
   assert(OperandIdx < DefMI->getNumOperands());
 
   // Make the DBG_INSTR_REF refer to that instruction, and that operand.
   unsigned InstrNum = DefMI->getDebugInstrNum();
-  MIB.addImm(InstrNum);
-  MIB.addImm(OperandIdx);
-  MIB.addMetadata(Var);
-  MIB.addMetadata(Expr);
-  return &*MIB;
+  SmallVector<MachineOperand, 1> MOs(
+      {MachineOperand::CreateDbgInstrRef(InstrNum, OperandIdx)});
+  return BuildMI(*MF, DL, RefII, false, MOs, Var, Expr);
 }
 
 MachineInstr *InstrEmitter::EmitDbgNoLocation(SDDbgValue *SD) {
   // An invalidated SDNode must generate an undef DBG_VALUE: although the
   // original value is no longer computed, earlier DBG_VALUEs live ranges
   // must not leak into later code.
   MDNode *Var = SD->getVariable();
   MDNode *Expr = SD->getExpression();

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
   // Helper to create DBG_INSTR_REFs or DBG_VALUEs, depending on what kind
   // we've been asked to pursue.
   auto MakeVRegDbgValue = [&](Register Reg, DIExpression *FragExpr,
                               bool Indirect) {
     if (Reg.isVirtual() && MF.useDebugInstrRef()) {
       // For VRegs, in instruction referencing mode, create a DBG_INSTR_REF
       // pointing at the VReg, which will be patched up later.
       auto &Inst = TII->get(TargetOpcode::DBG_INSTR_REF);
-      auto MIB = BuildMI(MF, DL, Inst);
-      MIB.addReg(Reg);
-      MIB.addImm(0);
-      MIB.addMetadata(Variable);
+      SmallVector<MachineOperand, 1> MOs({MachineOperand::CreateReg(
+          /* Reg */ Reg, /* isDef */ false, /* isImp */ false,
+          /* isKill */ false, /* isDead */ false,
+          /* isUndef */ false, /* isEarlyClobber */ false,
+          /* SubReg */ 0, /* isDebug */ true)});
+
       auto *NewDIExpr = FragExpr;
       // We don't have an "Indirect" field in DBG_INSTR_REF, fold that into
       // the DIExpression.
       if (Indirect)
         NewDIExpr = DIExpression::prepend(FragExpr, DIExpression::DerefBefore);
-      MIB.addMetadata(NewDIExpr);
-      return MIB;
+      return BuildMI(MF, DL, Inst, false, MOs, Variable, NewDIExpr);
     } else {
       // Create a completely standard DBG_VALUE.
       auto &Inst = TII->get(TargetOpcode::DBG_VALUE);
       return BuildMI(MF, DL, Inst, Indirect, Reg, Variable, FragExpr);
     }
   };
 
   if (Kind == FuncArgumentDbgValueKind::Value) {

llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

for (std::pair<unsigned, unsigned> LI : RegInfo->liveins())
         LiveInMap.insert(LI);
 
   // Insert DBG_VALUE instructions for function arguments to the entry block.
   bool InstrRef = MF->useDebugInstrRef();
   for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
     MachineInstr *MI = FuncInfo->ArgDbgValues[e - i - 1];
     assert(MI->getOpcode() != TargetOpcode::DBG_VALUE_LIST &&
            "Function parameters should not be described by DBG_VALUE_LIST.");
-    bool hasFI = MI->getOperand(0).isFI();
+    bool hasFI = MI->getDebugOperand(0).isFI();
     Register Reg =
-        hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
+        hasFI ? TRI.getFrameRegister(*MF) : MI->getDebugOperand(0).getReg();
     if (Register::isPhysicalRegister(Reg))
       EntryMBB->insert(EntryMBB->begin(), MI);
     else {
       MachineInstr *Def = RegInfo->getVRegDef(Reg);
       if (Def) {
         MachineBasicBlock::iterator InsertPos = Def;
         // FIXME: VR def may not be in entry block.
         Def->getParent()->insert(std::next(InsertPos), MI);
if (LDI != LiveInMap.end()) {
                        "- add if needed");
       MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
       MachineBasicBlock::iterator InsertPos = Def;
       const MDNode *Variable = MI->getDebugVariable();
       const MDNode *Expr = MI->getDebugExpression();
       DebugLoc DL = MI->getDebugLoc();
       bool IsIndirect = MI->isIndirectDebugValue();
       if (IsIndirect)
-        assert(MI->getOperand(1).getImm() == 0 &&
+        assert(MI->getDebugOffset().getImm() == 0 &&
                "DBG_VALUE with nonzero offset");
       assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
              "Expected inlined-at fields to agree");
       assert(MI->getOpcode() != TargetOpcode::DBG_VALUE_LIST &&
              "Didn't expect to see a DBG_VALUE_LIST here");
       // Def is never a terminator here, so it is ok to increment InsertPos.
       BuildMI(*EntryMBB, ++InsertPos, DL, TII->get(TargetOpcode::DBG_VALUE),
               IsIndirect, LDI->second, Variable, Expr);

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

static bool IsAnAddressOperand(const MachineOperand &MO) {
   case MachineOperand::MO_BlockAddress:
     return true;
   case MachineOperand::MO_RegisterMask:
   case MachineOperand::MO_RegisterLiveOut:
     return false;
   case MachineOperand::MO_Metadata:
   case MachineOperand::MO_MCSymbol:
     return true;
+  case MachineOperand::MO_DbgInstrRef:
   case MachineOperand::MO_CFIIndex:
     return false;
   case MachineOperand::MO_IntrinsicID:
   case MachineOperand::MO_Predicate:
     llvm_unreachable("should not exist post-isel");
   }
   llvm_unreachable("unhandled machine operand type");
 }

llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir

 tracksRegLiveness: true
 debugValueSubstitutions:
   - { srcinst: 2, srcop: 0, dstinst: 1, dstop: 0, subreg: 2 }
 body:             |
   bb.0:
     %0:gr16_abcd = MOV16ri 1, debug-instr-number 1, debug-location !9
 
   bb.1:
-    DBG_INSTR_REF 2, 0, !7, !DIExpression(), debug-location !9
+    DBG_INSTR_REF !7, !DIExpression(), dbg-instr-ref(2, 0), debug-location !9
     %1:gr16 = COPY %0, debug-location !9
     %2:gr16 = COPY %0
 
   bb.2:
     $ax = COPY %1, debug-location !9
     $dx = COPY %2
     RET64 killed $ax, killed $dx, debug-location !9
 ...

llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir

bb.0:
     DBG_VALUE $rcx, $noreg, !46, !17, debug-location !48
     DBG_VALUE $rcx, $noreg, !39, !17, debug-location !44
     DBG_PHI $rcx, 0
     DBG_PHI $rcx, 1
     DBG_VALUE $rbp, -20, !29, !17, debug-location !36
     $rcx = CMOV64rr killed $rcx, killed $rdx, 5, implicit killed $eflags
     $rcx = OR64rr killed $rcx, killed $rsi, implicit-def dead $eflags
     $rdx = MOVSX64rm32 $rbx, 1, $noreg, 0, $noreg :: (load (s32), align 8)
-    DBG_INSTR_REF 1, 0, !46, !17, debug-location !48
-    DBG_INSTR_REF 2, 0, !39, !17, debug-location !44
+    DBG_INSTR_REF !46, !17, dbg-instr-ref(1, 0), debug-location !48
+    DBG_INSTR_REF !39, !17, dbg-instr-ref(2, 0), debug-location !44
     TEST32mr killed $rcx, 4, killed $rdx, 0, $noreg, killed $eax, implicit-def $eflags :: (load (s32))
     JCC_1 %bb.2, 5, implicit $eflags
     JMP_1 %bb.3
 
   bb.1:
     successors: %bb.2
     liveins: $rbx, $rbp
 

llvm/test/DebugInfo/AArch64/instr-ref-const-physreg.ll

 ; RUN: llc %s -stop-before=finalize-isel -march=aarch64 -o - \
 ; RUN:     -experimental-debug-variable-locations | FileCheck %s
 
 ; Test that when an SSA Value becomes a constant-physreg copy, under the
 ; instruction referencing model, the COPY is labelled. In the general case
 ; labelling a copy is undesirable -- this test really checks that we don't
 ; crash, and we don't just drop the information.
 
 ; CHECK: DBG_PHI $xzr, 1
-; CHECK: DBG_INSTR_REF 1, 0
+; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
 
 define i64 @test() !dbg !7 {
   %foo = add i64 0, 0
   call void @llvm.dbg.value(metadata i64 %foo, metadata !12, metadata !DIExpression()), !dbg !13
   ret i64 %foo, !dbg !13
 }
 
 declare void @llvm.dbg.value(metadata, metadata, metadata)

llvm/test/DebugInfo/ARM/instr-ref-tcreturn.ll

 ; CHECK:        LOAD_STACK_GUARD
 
 ; CHECK-LABEL:  bb.2.entry:
 ; CHECK:        tBL {{.*}} &__stack_chk_fail,
 
 ; CHECK-LABEL:  bb.1.entry:
 ; CHECK:          $r0 = COPY %0
 ; CHECK-NEXT:     $r1 = COPY %1
-; CHECK-NEXT:     DBG_INSTR_REF 1, 0
+; CHECK-NEXT:     DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
 ; CHECK-NEXT:     TCRETURNdi &__divsi3, 0, csr_ios, implicit $sp, implicit $r0, implicit $r1
 
 declare i1 @ext()
 
 define i32 @test(i32 %a1, i32 %a2) #1 !dbg !5 {
 entry:
   %foo = alloca i32, i32 %a1
   %bool = call i1 @ext()

llvm/test/DebugInfo/MIR/InstrRef/accept-nonlive-reg-phis.mir

 tracksDebugUserValues: true
 frameInfo:
   maxAlignment:    4
 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
   
     DBG_PHI $fp0, 3
-    DBG_INSTR_REF 3, 0, !17, !DIExpression(), debug-location !30
+    DBG_INSTR_REF !17, !DIExpression(), dbg-instr-ref(3, 0), debug-location !30
     $eax = MOV32ri 0
     RET 0, debug-location !36
 
 ...

llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir

 # RUN: llc %s -run-pass=livedebugvalues -experimental-debug-variable-locations\
 # RUN:   -o - | FileCheck %s
 #
 # In the MIR below, there's an argument in the lowest byte of $edi. The debug
 # intrinsics correctly identify the value and where it becomes the variables
 # value, however a bug in InstrRefBasedLDV meant that not all subregisters of
 # DBG_PHI operands are tracked. That leads to the wrong DBG_VALUE location
 # being produced, and a crash under asan.
 #
 # CHECK-LABEL: name: foo
 # CHECK:       DBG_PHI $edi
-# CHECK-NEXT:  DBG_INSTR_REF 2, 0
+# CHECK-NEXT:  DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
 # CHECK-NEXT:  DBG_VALUE $dil
 --- |
   ; ModuleID = 'out.ll'
   source_filename = "out.ll"
   target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
   target triple = "x86_64-scei-ps4"
 
   @someglobal = external local_unnamed_addr global i8, align 1

 debugValueSubstitutions:
   - { srcinst: 2, srcop: 0, dstinst: 1, dstop: 0, subreg: 1 }
 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     liveins: $edi
 
     DBG_PHI $edi, 1
-    DBG_INSTR_REF 2, 0, !12, !DIExpression(), debug-location !13
+    DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(2, 0), debug-location !13
     renamable $rax = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @someglobal, $noreg, debug-location !13 :: (load (s64) from got)
     MOV8mr killed renamable $rax, 1, $noreg, 0, $noreg, renamable $dil, debug-location !13 :: (store (s8) into @someglobal)
     RET64 debug-location !13
 
 ...

llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir

bb.1.if.then:
     renamable $rbx = ADD64ri32 killed renamable $rbx, 1, implicit-def $eflags, debug-location !21
   
   bb.2.if.end:
     liveins: $rbx, $r14
   
     DBG_PHI $rbx, 1
     $rax = COPY $rbx
     $rbx = MOV64ri 0
-    DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13
+    DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(1, 0), debug-location !13
 
     ; This sequence should mark the contents of rbx on block entry as being the
     ; value for the variable at this DBG_INSTR_REF. We've force it to be in
     ; $rax now, so we should see a DBG_VALUE for rax:
     ; CHECK:      DBG_PHI $rbx, 1
     ; CHECK-NEXT: $rax = COPY $rbx
     ; CHECK-NEXT: $rbx = MOV64ri 0
-    ; CHECK-NEXT: DBG_INSTR_REF 1, 0
+    ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
     ; CHECK-NEXT: DBG_VALUE $rax, $noreg
 
     $rbx = COPY $rax
     renamable $rbx = ADD64rr killed renamable $rbx, killed renamable $r14, implicit-def $eflags, debug-location !23
     DBG_VALUE $rbx, $noreg, !12, !DIExpression(), debug-location !13
     $rdi = MOV64rr $rbx, debug-location !24
     CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !24
     $eax = MOV32rr $ebx, implicit killed $rbx, debug-location !26

llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv2.mir

bb.0:
     ;; A DBG_PHI of the stack should resolve to the stack location.
     DBG_PHI %stack.0, 1, 64
 
     ;; Reload value, clobber stack location.
     $rcx = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0)
     MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)
 
     ;; This should resolve to the loaded register.
-    DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13
-    ; CHECK:      DBG_INSTR_REF 1, 0,
+    DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(1, 0), debug-location !13
+    ; CHECK:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
     ; CHECK-NEXT: DBG_VALUE $rcx
 
     ;; And if we say it's a smaller size, we should be able to pick out smaller
     ;; subregisters within the stack slot.
     DBG_PHI %stack.0, 2, 32
     $rax = MOV64ri 0
     $rcx = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0)
     MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)
 
     ;; This should pick out the 32 bit value.
-    DBG_INSTR_REF 2, 0, !12, !DIExpression(), debug-location !13
-    ; CHECK:      DBG_INSTR_REF 2, 0,
+    DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(2, 0), debug-location !13
+    ; CHECK:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
     ; CHECK-NEXT: DBG_VALUE $ecx
 
     ;; Try all the other subregs.
     DBG_PHI %stack.0, 3, 16
     $rax = MOV64ri 0
     $rcx = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0)
     MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)
 
-    DBG_INSTR_REF 3, 0, !12, !DIExpression(), debug-location !13
-    ; CHECK:      DBG_INSTR_REF 3, 0,
+    DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(3, 0), debug-location !13
+    ; CHECK:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
     ; CHECK-NEXT: DBG_VALUE $cx
 
     DBG_PHI %stack.0, 4, 8
     $rax = MOV64ri 0
     $rcx = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0)
     MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)
 
-    DBG_INSTR_REF 4, 0, !12, !DIExpression(), debug-location !13
-    ; CHECK:      DBG_INSTR_REF 4, 0,
+    DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(4, 0), debug-location !13
+    ; CHECK:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
     ; CHECK-NEXT: DBG_VALUE $cl
 
     ;; We can't, at this time, describe subregister fields with nonzero offset.
     ;; It's easily achieved by attaching more data to stack DBG_PHIs, but it's
     ;; not clear that LLVM will ever merge registers to generate such locations.
 
     RET64 implicit $eax, debug-location !26
 
 ...

llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir

bb.1.if.then:
     renamable $rbx = ADD64ri32 killed renamable $rbx, 1, implicit-def $eflags, debug-location !22
     DBG_PHI $r14, 1
     DBG_PHI $rbx, 2
     DBG_PHI $rax, 3
 
   bb.3.if.end:
     liveins: $rbx, $r14
   
-    DBG_INSTR_REF 1, 0, !14, !DIExpression(), debug-location !13
-    DBG_INSTR_REF 2, 0, !12, !DIExpression(), debug-location !13
-    DBG_INSTR_REF 3, 0, !12, !DIExpression(), debug-location !13
+    DBG_INSTR_REF !14, !DIExpression(), dbg-instr-ref(1, 0), debug-location !13
+    DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(2, 0), debug-location !13
+    DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(3, 0), debug-location !13
 
     ; Value number 1 is live-through the above control flow from the two
     ; DBG_PHIs:
-    ; CHECK:       DBG_INSTR_REF 1, 0
+    ; CHECK:       DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
     ; CHECK-NEXT:  DBG_VALUE $r14
     ;
     ; While value number 2 has different defs that merge on entry to bb.3.
     ; These are both in $rbx though, and we should find its location:
-    ; CHECK:       DBG_INSTR_REF 2, 0
+    ; CHECK:       DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
     ; CHECK-NEXT:  DBG_VALUE $rbx
     ;
     ; Value number 3 cannot be resolved because $rax is clobbered in bb.2,
     ; meaning the merged value in bb.3 is incorrect. It should produce a
     ; DBG_VALUE $noreg.
-    ; CHECK:       DBG_INSTR_REF 3, 0
+    ; CHECK:       DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
     ; CHECK-NEXT:  DBG_VALUE $noreg
 
     renamable $rbx = ADD64rr killed renamable $rbx, killed renamable $r14, implicit-def $eflags, debug-location !28
-    DBG_INSTR_REF 2, 0, !12, !DIExpression(), debug-location !13
+    DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(2, 0), debug-location !13
 
     ; After clobbering rbx, the variable location should not be available.
-    ; CHECK:       DBG_INSTR_REF 2, 0
+    ; CHECK:       DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
     ; CHECK-NEXT:  DBG_VALUE $noreg
 
     $rdi = MOV64rr $rbx, debug-location !29
     CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !29
     $eax = MOV32rr $ebx, implicit killed $rbx, debug-location !31
     $rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !31
     CFI_INSTRUCTION def_cfa_offset 24, debug-location !31
     $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !31
     CFI_INSTRUCTION def_cfa_offset 16, debug-location !31
     $r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !31
     CFI_INSTRUCTION def_cfa_offset 8, debug-location !31
     RET64 implicit $eax, debug-location !31
 
 ...

llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir

body:             |
   bb.3:
     $r15 = MOV64ri 0
     CMP64ri8 $r15, 0, implicit-def $eflags, debug-location !19
     JCC_1 %bb.3, 5, implicit $eflags, debug-location !21
 
   bb.4:
     liveins: $rbx, $r14
   
-    DBG_INSTR_REF 1, 0, !14, !DIExpression(), debug-location !13
-    DBG_INSTR_REF 2, 0, !12, !DIExpression(), debug-location !13
-    DBG_INSTR_REF 3, 0, !12, !DIExpression(), debug-location !13
+    DBG_INSTR_REF !14, !DIExpression(), dbg-instr-ref(1, 0), debug-location !13
+    DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(2, 0), debug-location !13
+    DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(3, 0), debug-location !13
 
     ; Value number 1 is live-through the above control flow from the two
     ; DBG_PHIs:
-    ; CHECK:       DBG_INSTR_REF 1, 0
+    ; CHECK:       DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
     ; CHECK-NEXT:  DBG_VALUE $r14
     ;
     ; While value number 2 has different defs that merge on entry to bb.3.
     ; These are both in $rbx though, and we should find its location:
-    ; CHECK:       DBG_INSTR_REF 2, 0
+    ; CHECK:       DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
     ; CHECK-NEXT:  DBG_VALUE $rbx
     ;
     ; Value number 3 cannot be resolved because $rax is clobbered in bb.2,
     ; meaning the merged value in bb.3 is incorrect. It should produce a
     ; DBG_VALUE $noreg.
-    ; CHECK:       DBG_INSTR_REF 3, 0
+    ; CHECK:       DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
     ; CHECK-NEXT:  DBG_VALUE $noreg
 
     renamable $rbx = ADD64rr killed renamable $rbx, killed renamable $r14, implicit-def $eflags, debug-location !28
-    DBG_INSTR_REF 2, 0, !12, !DIExpression(), debug-location !13
+    DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(2, 0), debug-location !13
 
     ; After clobbering rbx, the variable location should not be available.
-    ; CHECK:       DBG_INSTR_REF 2, 0
+    ; CHECK:       DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
     ; CHECK-NEXT:  DBG_VALUE $noreg
 
     $rdi = MOV64rr $rbx, debug-location !29
     CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !29
     $eax = MOV32rr $ebx, implicit killed $rbx, debug-location !31
     $rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !31
     CFI_INSTRUCTION def_cfa_offset 24, debug-location !31
     $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !31
     CFI_INSTRUCTION def_cfa_offset 16, debug-location !31
     $r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !31
     CFI_INSTRUCTION def_cfa_offset 8, debug-location !31
     RET64 implicit $eax, debug-location !31
 
 ...

llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir

bb.0.entry:
     liveins: $rdi, $rdx, $rsi, $rbp, $r15, $r14, $r13, $r12, $rbx
   
     ; CHECK-LABEL: bb.0.entry:
 
     ;; PART ONE: For this first block of tests, check that information about
     ;; the size of the value on the stack makes it through to the expression.
 
     $al = MOV8ri 0, debug-instr-number 1, debug-location !7
-    DBG_INSTR_REF 1, 0, !8, !DIExpression(DW_OP_LLVM_convert, 8, DW_ATE_signed, DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value), debug-location !7
+    DBG_INSTR_REF !8, !DIExpression(DW_OP_LLVM_convert, 8, DW_ATE_signed, DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value), dbg-instr-ref(1, 0), debug-location !7
     ; CHECK:      DBG_VALUE $al, $noreg, ![[VARNUM]],
     ; CHECK-SAME: !DIExpression(DW_OP_LLVM_convert, 8, DW_ATE_signed,
     ; CHECK-SAME     : DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value)
 
     MOV8mr $rsp, 1, $noreg, -8, $noreg, renamable $al :: (store 1 into %stack.0)
     ;; Clobber to force variable location onto stack. We should use a
     ;; deref_size 1 because the value is smaller than the variable.
     $al = MOV8ri 0, debug-location !7
     ; CHECK:      DBG_VALUE $rsp, $noreg, ![[VARNUM]],
     ; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, 
     ; CHECK-SAME:     DW_OP_deref_size, 1, DW_OP_LLVM_convert, 8, DW_ATE_signed,
     ; CHECK-SAME:     DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value),
 
     ; Terminate the current variable location,
     DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7
     ; CHECK: DBG_VALUE $noreg, $noreg, ![[VARNUM]], !DIExpression()
 
     ;; Try again, but with the value originating on the stack, to ensure that
     ;; we can find its size. It should be deref_size 1 again.
     INC8m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-instr-number 2, debug-location !7 :: (store (s8) into %stack.0)
-    DBG_INSTR_REF 2, 1000000, !8, !DIExpression(DW_OP_LLVM_convert, 8, DW_ATE_signed, DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value), debug-location !7
+    DBG_INSTR_REF !8, !DIExpression(DW_OP_LLVM_convert, 8, DW_ATE_signed, DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value), dbg-instr-ref(2, 1000000), debug-location !7
     ; CHECK:      DBG_VALUE $rsp, $noreg, ![[VARNUM]],
     ; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus,
     ; CHECK-SAME:     DW_OP_deref_size, 1, DW_OP_LLVM_convert, 8, DW_ATE_signed,
     ; CHECK-SAME:     DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value),
 
     $eax = MOV32ri 0, debug-location !7
 
     ;; How about DBG_PHIs? The size of the value is communicated by the register
     ;; size, or an extra DBG_PHI operand, and that should feed through into the
     ;; decision of whether to deref_size or not.
 
     DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7
     ; CHECK: DBG_VALUE $noreg
 
     $al = MOV8ri 0, debug-location !7
     DBG_PHI $al, 7
 
     MOV32mr $rsp, 1, $noreg, -8, $noreg, renamable $eax :: (store 4 into %stack.0)
     $eax = MOV32ri 0, debug-location !7
-    DBG_INSTR_REF 7, 0, !8, !DIExpression(), debug-location !7
+    DBG_INSTR_REF !8, !DIExpression(), dbg-instr-ref(7, 0), debug-location !7
     ; CHECK:      DBG_VALUE $rsp, $noreg, ![[VARNUM]],
     ; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 1, DW_OP_stack_value)
 
     $eax = MOV32ri 0, debug-location !7
 
     ;; And for when the DBG_PHI specifies a stack size...
     DBG_PHI %stack.0, 8, 16
-    DBG_INSTR_REF 8, 0, !8, !DIExpression(), debug-location !7
+    DBG_INSTR_REF !8, !DIExpression(), dbg-instr-ref(8, 0), debug-location !7
     ; CHECK:      DBG_VALUE $rsp, $noreg, ![[VARNUM]],
     ; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 2, DW_OP_stack_value)
 
     $eax = MOV32ri 0, debug-location !7
     DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7
     ; CHECK: DBG_VALUE $noreg, $noreg
     DBG_VALUE $noreg, $noreg, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7
     ; CHECK: DBG_VALUE $noreg, $noreg
 
     ;; PART TWO: test the twelve kinds of location expression mentioned in the
     ;; opening comment of this test, in that order. Please update the opening
     ;; comment, these lines and the DWARF check lines at the same time.
     ;; In each test we'll state a location, give it an instruction to cover,
     ;; and then terminate it.
 
     ;; Scalar (32), Large value (64), no stack value,
     $rax = MOV64ri 0, debug-instr-number 10, debug-location !7
     MOV64mr $rsp, 1, $noreg, -8, $noreg, renamable $rax :: (store 8 into %stack.0)
     $rax = MOV64ri 0, debug-location !7
-    DBG_INSTR_REF 10, 0, !8, !DIExpression(), debug-location !7
+    DBG_INSTR_REF !8, !DIExpression(), dbg-instr-ref(10, 0), debug-location !7
     ; CHECK:      DBG_VALUE $rsp, $noreg, ![[VARNUM]],
     ; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 8, DW_OP_stack_value),
     $eax = MOV32ri 0, debug-location !7
     DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7
     ; CHECK: DBG_VALUE $noreg, $noreg
 
     ;; Scalar (32), Same value size (32), no stack value,
     $eax = MOV32ri 0, debug-instr-number 11, debug-location !7
     MOV32mr $rsp, 1, $noreg, -8, $noreg, renamable $eax :: (store 4 into %stack.0)
     $rax = MOV64ri 0, debug-location !7
-    DBG_INSTR_REF 11, 0, !8, !DIExpression(), debug-location !7
+    DBG_INSTR_REF !8, !DIExpression(), dbg-instr-ref(11, 0), debug-location !7
     ; CHECK:      DBG_VALUE $rsp, 0, ![[VARNUM]],
     ; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus),
     $eax = MOV32ri 0, debug-location !7
     DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7
     ; CHECK: DBG_VALUE $noreg, $noreg
 
     ;; Scalar (32), Smaller value (8), no stack value,
     $al = MOV8ri 0, debug-instr-number 12, debug-location !7
     MOV8mr $rsp, 1, $noreg, -8, $noreg, renamable $al :: (store 1 into %stack.0)
     $rax = MOV64ri 0, debug-location !7
-    DBG_INSTR_REF 12, 0, !8, !DIExpression(), debug-location !7
+    DBG_INSTR_REF !8, !DIExpression(), dbg-instr-ref(12, 0), debug-location !7
     ; CHECK:      DBG_VALUE $rsp, $noreg, ![[VARNUM]],
     ; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 1, DW_OP_stack_value),
     $eax = MOV32ri 0, debug-location !7
     DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7
     ; CHECK: DBG_VALUE $noreg, $noreg
 
     ;; Fragment (32), Larger value (64), no stack value,
     $rax = MOV64ri 0, debug-instr-number 13, debug-location !7
     MOV64mr $rsp, 1, $noreg, -8, $noreg, renamable $rax :: (store 8 into %stack.0)
     $rax = MOV64ri 0, debug-location !7
-    DBG_INSTR_REF 13, 0, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7
+    DBG_INSTR_REF !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(13, 0), debug-location !7
     ; CHECK:      DBG_VALUE $rsp, $noreg, ![[VARNUM2]],
     ; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 8, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32),
     $eax = MOV32ri 0, debug-location !7
     DBG_VALUE $noreg, $noreg, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7
     ; CHECK: DBG_VALUE $noreg, $noreg
 
     ;; Fragment (32), Same value size (32), no stack value,
     $eax = MOV32ri 0, debug-instr-number 14, debug-location !7
     MOV32mr $rsp, 1, $noreg, -8, $noreg, renamable $eax :: (store 4 into %stack.0)
     $rax = MOV64ri 0, debug-location !7
-    DBG_INSTR_REF 14, 0, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7
+    DBG_INSTR_REF !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(14, 0), debug-location !7
     ; CHECK:      DBG_VALUE $rsp, 0, ![[VARNUM2]],
     ; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_LLVM_fragment, 0, 32),
     $eax = MOV32ri 0, debug-location !7
     DBG_VALUE $noreg, $noreg, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7
     ; CHECK: DBG_VALUE $noreg, $noreg
 
     ;; Fragment (32), Smaller value (8), no stack value,
     $al = MOV8ri 0, debug-instr-number 15, debug-location !7
     MOV8mr $rsp, 1, $noreg, -8, $noreg, renamable $al :: (store 1 into %stack.0)
     $rax = MOV64ri 0, debug-location !7
-    DBG_INSTR_REF 15, 0, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7
+    DBG_INSTR_REF !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(15, 0), debug-location !7
     ; CHECK:      DBG_VALUE $rsp, $noreg, ![[VARNUM2]],
     ; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 1, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32),
     $eax = MOV32ri 0, debug-location !7
     DBG_VALUE $noreg, $noreg, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7
     ; CHECK: DBG_VALUE $noreg, $noreg
 
 
 
     ;; Scalar (32), Large value (64), with stack value,
     $rax = MOV64ri 0, debug-instr-number 16, debug-location !7
     MOV64mr $rsp, 1, $noreg, -8, $noreg, renamable $rax :: (store 8 into %stack.0)
     $rax = MOV64ri 0, debug-location !7
-    DBG_INSTR_REF 16, 0, !8, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), debug-location !7
+    DBG_INSTR_REF !8, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), dbg-instr-ref(16, 0), debug-location !7
     ; CHECK:      DBG_VALUE $rsp, $noreg, ![[VARNUM]],
     ; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 8, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value),
     $eax = MOV32ri 0, debug-location !7
     DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7
     ; CHECK: DBG_VALUE $noreg, $noreg
 
     ;; Scalar (32), Same value size (32), no stack value,
     $eax = MOV32ri 0, debug-instr-number 17, debug-location !7
     MOV32mr $rsp, 1, $noreg, -8, $noreg, renamable $eax :: (store 4 into %stack.0)
     $rax = MOV64ri 0, debug-location !7
-    DBG_INSTR_REF 17, 0, !8, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), debug-location !7
+    DBG_INSTR_REF !8, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), dbg-instr-ref(17, 0), debug-location !7
     ; CHECK:      DBG_VALUE $rsp, $noreg, ![[VARNUM]],
     ; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value),
     $eax = MOV32ri 0, debug-location !7
     DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7
     ; CHECK: DBG_VALUE $noreg, $noreg
 
     ;; Scalar (32), Smaller value (8), no stack value,
     $al = MOV8ri 0, debug-instr-number 18, debug-location !7
     MOV8mr $rsp, 1, $noreg, -8, $noreg, renamable $al :: (store 1 into %stack.0)
     $rax = MOV64ri 0, debug-location !7
-    DBG_INSTR_REF 18, 0, !8, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), debug-location !7
+    DBG_INSTR_REF !8, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), dbg-instr-ref(18, 0), debug-location !7
     ; CHECK:      DBG_VALUE $rsp, $noreg, ![[VARNUM]],
     ; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 1, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value),
     $eax = MOV32ri 0, debug-location !7
     DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7
     ; CHECK: DBG_VALUE $noreg, $noreg
 
     ;; Fragment (32), Larger value (64), no stack value,
     $rax = MOV64ri 0, debug-instr-number 19, debug-location !7
     MOV64mr $rsp, 1, $noreg, -8, $noreg, renamable $rax :: (store 8 into %stack.0)
     $rax = MOV64ri 0, debug-location !7
-    DBG_INSTR_REF 19, 0, !10, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), debug-location !7
+    DBG_INSTR_REF !10, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(19, 0), debug-location !7
     ; CHECK:      DBG_VALUE $rsp, $noreg, ![[VARNUM2]],
     ; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 8, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32),
     $eax = MOV32ri 0, debug-location !7
     DBG_VALUE $noreg, $noreg, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7
     ; CHECK: DBG_VALUE $noreg, $noreg
 
     ;; Fragment (32), Same value size (32), no stack value,
     $eax = MOV32ri 0, debug-instr-number 20, debug-location !7
     MOV32mr $rsp, 1, $noreg, -8, $noreg, renamable $eax :: (store 4 into %stack.0)
     $rax = MOV64ri 0, debug-location !7
-    DBG_INSTR_REF 20, 0, !10, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), debug-location !7
+    DBG_INSTR_REF !10, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(20, 0), debug-location !7
     ; CHECK:      DBG_VALUE $rsp, $noreg, ![[VARNUM2]],
     ; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 4, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32),
     $eax = MOV32ri 0, debug-location !7
     DBG_VALUE $noreg, $noreg, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7
     ; CHECK: DBG_VALUE $noreg, $noreg
 
     ;; Fragment (32), Smaller value (8), no stack value,
     $al = MOV8ri 0, debug-instr-number 21, debug-location !7
     MOV8mr $rsp, 1, $noreg, -8, $noreg, renamable $al :: (store 1 into %stack.0)
     $rax = MOV64ri 0, debug-location !7
-    DBG_INSTR_REF 21, 0, !10, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), debug-location !7
+    DBG_INSTR_REF !10, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(21, 0), debug-location !7
     ; CHECK:      DBG_VALUE $rsp, $noreg, ![[VARNUM2]],
     ; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 1, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32),
     $eax = MOV32ri 0, debug-location !7
     DBG_VALUE $noreg, $noreg, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7
     ; CHECK: DBG_VALUE $noreg, $noreg
 
     RET64 0, debug-location !7
 ...

llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir

bb.8:
     liveins: $rax, $rdi, $rdx, $rsi, $r8, $r9, $r10, $r11, $r14
   
     MOV64mr renamable $rdi, 1, $noreg, 16, $noreg, killed renamable $rax, debug-location !7 :: (store 8 into %ir.22)
     renamable $rax = MOV64rm $rsp, 1, $noreg, -8, $noreg :: (load 8 from %stack.0)
     MOV64mr undef renamable $rax, 1, $noreg, 0, $noreg, killed renamable $rax, debug-location !7 :: (store 8 into `%"class.llvm::Loop"*** undef`)
     MOV64mr undef renamable $rax, 1, $noreg, 0, $noreg, killed renamable $r10, debug-location !7 :: (store 8 into `%"class.llvm::Loop"*** undef`)
     MOV64mr killed renamable $rdi, 1, $noreg, 40, $noreg, killed renamable $r9, debug-location !7 :: (store 8 into %ir.24)
     renamable $rax = MOV64rm killed renamable $rsi, 1, $noreg, 24, $noreg, debug-location !7 :: (load 8 from %ir.26)
-    DBG_INSTR_REF 1, 0, !8, !DIExpression(DW_OP_LLVM_fragment, 64, 64), debug-location !7
+    DBG_INSTR_REF !8, !DIExpression(DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(1, 0), debug-location !7
     renamable $rax = SUB64rr killed renamable $rax, killed renamable $r11, implicit-def dead $eflags, debug-location !7
     renamable $r8 = SUB64rr killed renamable $r8, killed renamable $r14, implicit-def dead $eflags, debug-location !7
     renamable $r8 = exact SAR64ri killed renamable $r8, 3, implicit-def dead $eflags, debug-location !7
     renamable $rax = LEA64r killed renamable $r8, 8, killed renamable $rax, -64, $noreg, debug-location !7
     TEST64rr killed renamable $rax, renamable $rax, implicit-def $eflags, debug-location !7
     JCC_1 %bb.10, 15, implicit $eflags, debug-location !7
   
   bb.9:

llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir

 debugValueSubstitutions:
   - { srcinst: 4, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 }
 body:  |
   bb.0.entry:
     successors: %bb.1, %bb.2
     ; CHECK-LABE: bb.0.entry:
 
     $rax = MOV64ri 1, debug-instr-number 1, debug-location !17
-    DBG_INSTR_REF 1, 0, !16, !DIExpression(), debug-location !17
+    DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(1, 0), debug-location !17
     ;; First check that picking out location works as usual.
-    ; CHECK:      DBG_INSTR_REF 1, 0
+    ; CHECK:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
     ; CHECK-NEXT: DBG_VALUE $rax
 
     $rax = MOV64ri 1, debug-instr-number 2, debug-location !17
-    DBG_INSTR_REF 2, 999, !16, !DIExpression(), debug-location !17
+    DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(2, 999), debug-location !17
     ;; Test out of bounds operand number.
-    ; CHECK:      DBG_INSTR_REF 2, 999
+    ; CHECK:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 999)
     ; CHECK-NEXT: DBG_VALUE $noreg
 
     $rax = MOV64ri 1, debug-instr-number 3, debug-location !17
-    DBG_INSTR_REF 3, 1, !16, !DIExpression(), debug-location !17
+    DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(3, 1), debug-location !17
     ;; Test non-register operand
-    ; CHECK:      DBG_INSTR_REF 3, 1
+    ; CHECK:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 1)
     ; CHECK-NEXT: DBG_VALUE $noreg
 
     ;; FIXME: We should test what happens when this meta-instruction is seen
     ;; by livedbugvalues with an instruction number. However, right now it's
     ;; impossible to turn the machine-code verifier off when loading MIR?
     ;KILL implicit killed $eflags, debug-instr-number 4, debug-location !17
-    ;DBG_INSTR_REF 4, 0, !16, !DIExpression(), debug-location !17
+    ;DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(4, 0), debug-location !17
     ;;; Test non-def operand
-    ;; check:      DBG_INSTR_REF 4, 0
+    ;; check:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
     ;; check-next: DBG_VALUE $noreg
 
     $noreg = MOV32ri 1, debug-instr-number 5, debug-location !17
-    DBG_INSTR_REF 5, 0, !16, !DIExpression(), debug-location !17
+    DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(5, 0), debug-location !17
     ;; Def of $noreg?
-    ; CHECK:      DBG_INSTR_REF 5, 0
+    ; CHECK:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(5, 0)
     ; CHECK-NEXT: DBG_VALUE $noreg
 
     JCC_1 %bb.1, 1, implicit $eflags
     JMP_1 %bb.2
 
   bb.1:
     successors: %bb.3
     ; CHECK-LABEL: bb.1:
 
     DBG_PHI $rax, 6
-    DBG_INSTR_REF 6, 1, !16, !DIExpression(), debug-location !17
+    DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(6, 1), debug-location !17
     ;; Test out-of-bounds reference to a DBG_PHI.
-    ; CHECK:      DBG_INSTR_REF 6, 1
+    ; CHECK:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(6, 1)
     ; CHECK-NEXT: DBG_VALUE $noreg
 
     DBG_PHI $noreg, 7
     JMP_1 %bb.3
 
   bb.2:
     successors: %bb.3
     ; CHECK-LABEL: bb.2:
     DBG_PHI 1, 6
-    DBG_INSTR_REF 6, 0, !16, !DIExpression(), debug-location !17
+    DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(6, 0), debug-location !17
     ;; Test non-reg operand to DBG_PHI. It's not clear if this can ever happen
     ;; as the result of an optimisation, but lets test for it anyway.
-    ; CHECK:      DBG_INSTR_REF 6, 0
+    ; CHECK:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(6, 0)
     ; CHECK-NEXT: DBG_VALUE $noreg
 
     DBG_PHI 1, 7
     JMP_1 %bb.3
 
   bb.3:
     ; CHECK-LABEL: bb.3:
-    DBG_INSTR_REF 7, 0, !16, !DIExpression(), debug-location !17
+    DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(7, 0), debug-location !17
     ;; PHI resolution of illegal inputs shouldn't crash either. It should also
     ;; come out as a $noreg location.
-    ; CHECK:      DBG_INSTR_REF 7, 0
+    ; CHECK:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(7, 0)
     ; CHECK-NEXT: DBG_VALUE $noreg
 
     RET 0, debug-location !17
 
 ...

llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir

 ---
 name: _Z8bb_to_bb
 debugValueSubstitutions:
   - { srcinst: 4, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 }
 body:  |
   bb.0.entry:
     $rax = MOV64ri 1, debug-instr-number 1, debug-location !17
     ; This debug instruction should identify the value as being in $rax.
-    DBG_INSTR_REF 1, 0, !16, !DIExpression(), debug-location !17
+    DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(1, 0), debug-location !17
     ; CHECK: DBG_VALUE $rax, $noreg
 
     $rbx = COPY killed $rax, debug-location !17
     $rax = MOV64ri 1, debug-location !17
     ; CHECK: DBG_VALUE $rbx, $noreg
 
-    DBG_INSTR_REF 2, 0, !16, !DIExpression(), debug-location !17
+    DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(2, 0), debug-location !17
     ; No instruction is labelled with the number "2". This should produce an
     ; empty variable location.
     ; CHECK: DBG_VALUE $noreg, $noreg
 
     $rbx = MOV64ri 1, debug-instr-number 3, debug-location !17
     JMP_1 %bb.1
 
 
     ; CHECK-LABEL: bb.1:
   bb.1:
 
-    DBG_INSTR_REF 3, 0, !16, !DIExpression(), debug-location !17
+    DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(3, 0), debug-location !17
     ; This refers to a value def'd in a parent block -- but it should be
     ; tracked into this block.
     ; CHECK: DBG_VALUE $rbx, $noreg
     JMP_1 %bb.2
 
     ; CHECK-LABEL: bb.2:
   bb.2:
     ; Just like any other variable location, live-ins should be created for
     ; any successor blocks.
     ; CHECK: DBG_VALUE $rbx, $noreg
 
-    DBG_INSTR_REF 5, 0, !16, !DIExpression(), debug-location !17
+    DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(5, 0), debug-location !17
     ; This is a debug use-before-def: the value appears a few instructions
     ; later. Any earlier value should be terminated here, _and_ we should
     ; emit a DBG_VALUE when the value becomes available.
     ; CHECK: DBG_VALUE $noreg, $noreg
 
     $rax = MOV64ri 1, debug-location !17
     $rax = MOV64ri 1, debug-location !17
     $rcx = MOV64ri 1, debug-instr-number 5, debug-location !17
     ; CHECK: DBG_VALUE $rcx, $noreg
     $rax = MOV64ri 1, debug-location !17
 
-    DBG_INSTR_REF 6, 0, !16, !DIExpression(), debug-location !17
+    DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(6, 0), debug-location !17
     ; Another debug use-before-def, but across block boundaries.
     ; CHECK: DBG_VALUE $noreg, $noreg
     JMP_1 %bb.3
 
     ; CHECK-LABEL: bb.3:
   bb.3:
     $rax = MOV64ri 1, debug-location !17
     $rdx = MOV64ri 1, debug-instr-number 6, debug-location !17
     ; CHECK: DBG_VALUE $rdx, $noreg
 
     ; Terminate variable location for next few blocks,
     DBG_VALUE $noreg, $noreg, !16, !DIExpression(), debug-location !17
     ; CHECK: DBG_VALUE $noreg, $noreg
     JMP_1 %bb.4
 
   bb.4:
     ; The next three blocks form a debug use-before-def modelling a scenario
     ; where an instruction is sunk (debug inst in bb5, value in bb6). However,
     ; because a different path joins bb.6, we should _not_ add any DBG_VALUE.
     ; A different variable value may enter the block via the other path.
     $rdx = MOV64ri 1, implicit-def $eflags, debug-location !17
     JCC_1 %bb.6, 4, implicit $eflags, debug-location !17
   bb.5:
-    DBG_INSTR_REF 7, 0, !16, !DIExpression(), debug-location !17
+    DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(7, 0), debug-location !17
     ; CHECK: DBG_VALUE $noreg, $noreg
     JMP_1 %bb.6, debug-location !17
   bb.6:
     $rsi = MOV64ri 1, debug-instr-number 7, debug-location !17
     JMP_1 %bb.7, debug-location !17
 
   ; A use-before-def shouldn't pass another definition of the variable location
   ; or value.
   bb.7:
-    DBG_INSTR_REF 8, 0, !16, !DIExpression(), debug-location !17
+    DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(8, 0), debug-location !17
     ; CHECK: DBG_VALUE $noreg, $noreg
     DBG_VALUE $rax, $noreg, !16, !DIExpression(), debug-location !17
     ; CHECK: DBG_VALUE $rax, $noreg,
     $rdi = MOV64ri 1, debug-instr-number 8, debug-location !17
 
   ; Loops: use-before-defs should be live-through loops, assuming that nothing
   ; in that loop modifies the variable location.
   bb.8:
-    DBG_INSTR_REF 9, 0, !16, !DIExpression(), debug-location !17
+    DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(9, 0), debug-location !17
     ; CHECK: DBG_VALUE $noreg, $noreg
     JCC_1 %bb.8, 4, implicit $eflags
   bb.9:
     $rax = MOV64ri 11, debug-instr-number 9, debug-location !17
     ; CHECK: DBG_VALUE $rax, $noreg,
 
   ; Likewise, use-before-defs where anything changes the variable location
   ; or value in the loop, should be discarded.
   bb.10:
     ; live-in,
     ; CHECK: DBG_VALUE $rax, $noreg,
-    DBG_INSTR_REF 10, 0, !16, !DIExpression(), debug-location !17
+    DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(10, 0), debug-location !17
     ; CHECK: DBG_VALUE $noreg, $noreg
 
   bb.11:
     $rbx = MOV64ri 1, debug-location !17
 
   bb.12:
-    DBG_INSTR_REF 9, 0, !16, !DIExpression(), debug-location !17
+    DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(9, 0), debug-location !17
     ; This still has a value in $rax,
     ; CHECK: DBG_VALUE $rax, $noreg
     JCC_1 %bb.11, 4, implicit $eflags
 
   bb.13:
     ; Live in,
     ; CHECK: DBG_VALUE $rax, $noreg
     $rbx = MOV64ri 11, debug-instr-number 10, debug-location !17
     ; This is instruction 10 referred to in bb.10. However, as the variable
     ; location/value has been modified in the meantime, no DBG_VALUE should be
     ; generated here.
     RET64 $eax, debug-location !17
 ...

llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir

liveins: $rdi, $rax, $rbx
     $rsi = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0)
 
     ; Store a random value onto stack, forces value to be in one place only.
     ; Clobber other registers that contain the value we're to track.
     MOV64mr $rsp, 1, $noreg, 16, $noreg, $rbx :: (store 8 into %stack.0)
     $rax = MOV64ri 0
     $rdi = MOV64ri 0
 
-    DBG_INSTR_REF 1, 0, !11, !DIExpression(), debug-location !12
+    DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(1, 0), debug-location !12
     ; CHECK:      DBG_INSTR_REF
     ; CHECK-NEXT: DBG_VALUE $esi
     RET64 $rsi, debug-location !12
 ...

llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir

stack:
   - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,
       stack-id: default, callee-saved-register: '', callee-saved-restored: true,
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 body:  |
   bb.0:
   liveins: $rdi, $rax
     CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rax, debug-instr-number 4, debug-location !12
     ; CHECK:      CALL64pcrel32
-    DBG_INSTR_REF 1, 0, !11, !DIExpression(), debug-location !12
-    ; CHECK-NEXT: DBG_INSTR_REF 1, 0
+    DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(1, 0), debug-location !12
+    ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
     ; CHECK-NEXT: DBG_VALUE $al
-    DBG_INSTR_REF 5, 0, !11, !DIExpression(), debug-location !12
-    ; CHECK-NEXT: DBG_INSTR_REF 5, 0
+    DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(5, 0), debug-location !12
+    ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(5, 0)
     ; CHECK-NEXT: DBG_VALUE $ah
-    DBG_INSTR_REF 8, 0, !11, !DIExpression(), debug-location !12
-    ; CHECK-NEXT: DBG_INSTR_REF 8, 0
+    DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(8, 0), debug-location !12
+    ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(8, 0)
     ; CHECK-NEXT: DBG_VALUE $ah
-    DBG_INSTR_REF 13, 0, !11, !DIExpression(), debug-location !12
-    ; CHECK-NEXT: DBG_INSTR_REF 13, 0
+    DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(13, 0), debug-location !12
+    ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(13, 0)
     ; CHECK-NEXT: DBG_VALUE $noreg
     MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)
     $rax = MOV64ri 0, debug-location !12
     ; CHECK:      $rax = MOV64ri 0
     ; The value is now located in a spill slot, as a subregister within the
     ; slot, which InstrRefBasedLDV should be able to find.
-    DBG_INSTR_REF 1, 0, !11, !DIExpression(), debug-location !12
-    ; CHECK-NEXT: DBG_INSTR_REF 1, 0
+    DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(1, 0), debug-location !12
+    ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
     ; CHECK-NEXT: DBG_VALUE $rsp, 0, !{{[0-9]*}}, !DIExpression(DW_OP_constu, 8, DW_OP_minus)
-    DBG_INSTR_REF 5, 0, !11, !DIExpression(), debug-location !12
+    DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(5, 0), debug-location !12
     ; This and the next DBG_INSTR_REF refer to a value that is on the stack, but
     ; is located at a non-zero offset from the start of the slot -- $ah within
     ; $rax is 8 bits in. Today, InstrRefBasedLDV can't express this. It also
     ; doesn't seem likely to be profitable.
-    ; CHECK-NEXT: DBG_INSTR_REF 5, 0
+    ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(5, 0)
     ; CHECK-NEXT: DBG_VALUE $noreg
-    DBG_INSTR_REF 8, 0, !11, !DIExpression(), debug-location !12
-    ; CHECK-NEXT: DBG_INSTR_REF 8, 0
+    DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(8, 0), debug-location !12
+    ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(8, 0)
     ; CHECK-NEXT: DBG_VALUE $noreg
-    DBG_INSTR_REF 13, 0, !11, !DIExpression(), debug-location !12
-    ; CHECK-NEXT: DBG_INSTR_REF 13, 0
+    DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(13, 0), debug-location !12
+    ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(13, 0)
     ; CHECK-NEXT: DBG_VALUE $noreg
     $rax = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0)
     RET64 $rax, debug-location !12
 ...

llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir

bb.5:
     MOV64mr %33, 1, $noreg, 0, $noreg, %12, debug-location !13 :: (store (s64) into `i64* undef`)
     %11:gr32 = MOV32rm %34, 1, $noreg, 0, $noreg, debug-location !13 :: (load (s32) from `i32* undef`, align 8)
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !13
     $rdi = COPY %35, debug-location !13
     $rsi = COPY %36, debug-location !13
     CALL64r %37, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit-def $rsp, implicit-def $ssp, implicit-def $al, debug-location !13
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !13
     %13:gr32 = INC32r %6, implicit-def dead $eflags, debug-instr-number 1, debug-location !13
-    DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13
+    DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(1, 0), debug-location !13
     JMP_1 %bb.1, debug-location !13
 ...

llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir

bb.0.if.then:
     JCC_1 %bb.3, 5, implicit killed $eflags
     JMP_1 %bb.1
   
   bb.1.sw.bb:
     successors: %bb.2(0x30000000), %bb.3(0x50000000)
   
     %7:gr32 = nofpexcept CVTTSS2SIrr killed %1, implicit $mxcsr, debug-instr-number 1
     %8:gr8 = COPY killed %7.sub_8bit
-    DBG_INSTR_REF 2, 0, !6, !DIExpression(), debug-location !17
+    DBG_INSTR_REF !6, !DIExpression(), dbg-instr-ref(2, 0), debug-location !17
     TEST8rr killed %8, %8, implicit-def $eflags
     JCC_1 %bb.3, 5, implicit killed $eflags
     JMP_1 %bb.2
   
   bb.2.if.end:
     successors: %bb.3(0x80000000)
   
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp

llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir

- { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 body:  |
   bb.0:
   liveins: $rdi, $rax
     DBG_PHI $rax, 1
     MOV64mr $rsp, 1, $noreg, 16, $noreg, $rdi :: (store 8 into %stack.0)
     $rax = MOV64ri 0, debug-location !12
     INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-instr-number 3, debug-location !DILocation(line: 0, scope: !7) :: (store (s32) into %stack.0)
-    DBG_INSTR_REF 2, 0, !11, !DIExpression(), debug-location !12
-    ; CHECK:      DBG_INSTR_REF 2, 0
+    DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(2, 0), debug-location !12
+    ; CHECK:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
     ; CHECK-NEXT: DBG_VALUE $rsp
     ;; Test that the old value (from the DBG_PHI) is not tracked anywhere. It
     ;; should not be considered as being on the stack any more.
-    DBG_INSTR_REF 1, 0, !11, !DIExpression(), debug-location !12
-    ; CHECK:      DBG_INSTR_REF 1, 0
+    DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(1, 0), debug-location !12
+    ; CHECK:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
     ; CHECK-NEXT: DBG_VALUE $noreg
     INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-location !12 :: (store (s32) into %stack.0)
     ;; The above INC32m should be detected as clobbering the stack location,
     ;; even though it isn't debug labelled.
-    DBG_INSTR_REF 2, 0, !11, !DIExpression(), debug-location !12
-    ; CHECK:      DBG_INSTR_REF 2, 0
+    DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(2, 0), debug-location !12
+    ; CHECK:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
     ; CHECK-NEXT: DBG_VALUE $noreg
 
     ;; Store another debug-labelled value to the stack,
     INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-instr-number 5, debug-location !DILocation(line: 0, scope: !7) :: (store (s32) into %stack.0)
     ;; Point the variable at that value.
-    DBG_INSTR_REF 4, 0, !11, !DIExpression(), debug-location !12
-    ; CHECK:      DBG_INSTR_REF 4, 0,
+    DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(4, 0), debug-location !12
+    ; CHECK:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0),
     ; CHECK-NEXT: DBG_VALUE $rsp
     ;; Overwrite the stack: LiveDebugValues should explicitly undef the stack
     ;; location with DBG_VALUE $noreg, as DbgEntityHistoryCalculator doesn't
     ;; look at the stack.
     INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-location !DILocation(line: 0, scope: !7) :: (store (s32) into %stack.0)
     ; CHECK:      INC32m $rsp
     ; CHECK-NEXT: DBG_VALUE $noreg
 
     $rax = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0)
     RET64 $rax, debug-location !12
 ...

llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir

 #
 # CHECK-LABEL: bb.0.entry:
 # CHECK:       DBG_VALUE $rbx, $noreg, ![[FIRSTVAR]],
 # CHECK-SAME:        !DIExpression(DW_OP_LLVM_fragment, 64, 64)
 #
 # CHECK-LABEL: bb.1.if.then.i.i.i.i.i:
 # CHECK:       DBG_VALUE $rbx, $noreg, ![[FIRSTVAR]],
 # CHECK-SAME:        !DIExpression(DW_OP_LLVM_fragment, 64, 64)
-# CHECK:       DBG_INSTR_REF {{.*}} ![[FIRSTVAR]],
+# CHECK:       DBG_INSTR_REF ![[FIRSTVAR]],
 # CHECK:       DBG_VALUE $rbx, $noreg, ![[FIRSTVAR]],
 # CHECK-SAME:        !DIExpression(DW_OP_LLVM_fragment, 64, 64)
 
 # CHECK-LABEL: bb.2._Z17do_insert_cv_testI5_TreeEvv.exit:
 # CHECK:       DBG_VALUE $rbx, $noreg, ![[FIRSTVAR]],
 # CHECK-SAME:        !DIExpression(DW_OP_LLVM_fragment, 64, 64)
-# CHECK:       DBG_INSTR_REF {{.*}} ![[FIRSTVAR]],
+# CHECK:       DBG_INSTR_REF ![[FIRSTVAR]],
 # CHECK:       DBG_VALUE $rbx, $noreg, ![[FIRSTVAR]],
 # CHECK-SAME:        !DIExpression(DW_OP_LLVM_fragment, 64, 64)
 
 --- |
   source_filename = "reduced.ll"
   target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
   
   %class._Tree = type { i8 }
bb.0.entry:
     CFI_INSTRUCTION offset $rbx, -24
     CFI_INSTRUCTION offset $r14, -16
     DBG_PHI $rsi, 2
     $rbx = MOV64rr $rsi
     DBG_VALUE 2, $noreg, !10, !DIExpression(), debug-location !12
     renamable $r14d = XOR32rr undef $r14d, undef $r14d, implicit-def dead $eflags, implicit-def $r14
     dead $edi = XOR32rr undef $edi, undef $edi, implicit-def dead $eflags, implicit-def $rdi
     CALL64r undef renamable $rax, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def dead $eax, implicit-def dead $rdx
-    DBG_INSTR_REF 2, 0, !13, !DIExpression(DW_OP_LLVM_fragment, 64, 64), debug-location !15
+    DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(2, 0), debug-location !15
     dead $edi = XOR32rr undef $edi, undef $edi, implicit-def dead $eflags, implicit-def $rdi, debug-location !15
     CALL64r undef renamable $rax, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def dead $al, debug-location !15
     TEST8rr renamable $r14b, renamable $r14b, implicit-def $eflags, implicit killed $r14
     JCC_1 %bb.2, 5, implicit $eflags
   
   bb.1.if.then.i.i.i.i.i:
     dead $edi = XOR32rr undef $edi, undef $edi, implicit-def dead $eflags, implicit-def $rdi
     CALL64r undef renamable $rax, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $rax, debug-instr-number 3
     $rbx = MOV64rr killed $rax
-    DBG_INSTR_REF 3, 7, !13, !DIExpression(DW_OP_LLVM_fragment, 64, 64), debug-location !15
+    DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(3, 7), debug-location !15
   
   bb.2._Z17do_insert_cv_testI5_TreeEvv.exit:
     liveins: $rbx
   
     DBG_PHI $rbx, 1
-    DBG_INSTR_REF 1, 0, !13, !DIExpression(DW_OP_LLVM_fragment, 64, 64), debug-location !15
+    DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(1, 0), debug-location !15
     dead $edi = XOR32rr undef $edi, undef $edi, implicit-def dead $eflags, implicit-def $rdi, debug-location !16
     $esi = XOR32rr undef $esi, undef $esi, implicit-def dead $eflags, debug-location !16
     $rdx = MOV64rr killed $rbx, debug-location !16
     CALL64r undef renamable $rax, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit $esi, implicit killed $rdx, implicit-def $rsp, implicit-def $ssp, debug-location !16
     $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
     $rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags
     CFI_INSTRUCTION def_cfa_offset 24
     $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp
     CFI_INSTRUCTION def_cfa_offset 16
     $r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp
     CFI_INSTRUCTION def_cfa_offset 8
     RET64 killed $eax
 
 ...

llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir

body:             |
   ; Verify those registers land in $bx
   ; CHECK:              renamable $ebp = ADD32ri8
 
   ; DOESCOALESCE-LABEL: bb.2.if.end:
   ; CHECK-LABEL:        bb.2.if.end:
   bb.2.if.end:
     %2:gr16 = PHI %11, %bb.0, %17, %bb.1, debug-instr-number 1, debug-location !13
   ; CHECK:              DBG_PHI $bp, 1
-    DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13
+    DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(1, 0), debug-location !13
     %31:gr32 = MOVSX32rr16 %6, debug-location !13
     %30:gr32 = MOVSX32rr16 killed %2, debug-location !13
     %29:gr32 = ADD32rr killed %30, killed %31, implicit-def $eflags, debug-location !13
     %26:gr16 = COPY killed %29.sub_16bit, debug-location !13
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
     %24:gr32 = MOVSX32rr16 %26, debug-location !13
     $edi = COPY %24, debug-location !13
     CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $edi, debug-location !13
     ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
     %23:gr32 = MOVSX32rr16 %26, debug-location !13
     $eax = COPY %23, debug-location !13
     RET64 implicit $eax, debug-location !13
 
 ...

llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir

body:             |
   ; Verify that all these registers land in r14.
   ; CHECK:              renamable $r14 = ADD64ri32 killed renamable $r14
   
   ; DOESCOALESCE-LABEL: bb.2.if.end:
   ; CHECK-LABEL:        bb.2.if.end:
   bb.2.if.end:
     %2:gr64 = PHI %9, %bb.0, %10, %bb.1, debug-instr-number 1, debug-location !13
   ; CHECK:              DBG_PHI $r14, 1
-    DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13
+    DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(1, 0), debug-location !13
     %2:gr64 = ADD64rr killed %2, %6, implicit-def $eflags, debug-location !13
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
     $rdi = COPY %2, debug-location !13
     CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !13
     ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
     %13:gr32 = COPY %2.sub_32bit, debug-location !13
     $eax = COPY %13, debug-location !13
     RET64 implicit $eax, debug-location !13
 
 ...

llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir

bb.2:
     %59:gr32 = PHI %19, %bb.0, %39, %bb.1, debug-location !18
     %60:gr32 = PHI %20, %bb.0, %40, %bb.1, debug-location !18
     %61:gr32 = PHI %21, %bb.0, %41, %bb.1, debug-location !18
     %62:gr32 = PHI %22, %bb.0, %42, %bb.1, debug-location !18
     %63:gr32 = PHI %23, %bb.0, %43, %bb.1, debug-location !18
     %64:gr32 = PHI %24, %bb.0, %44, %bb.1, debug-location !18
 
     INLINEASM &"", 1, 12, %50, 12, %51, 12, %52, 12, %53, 12, %54, 12, %55, 12, %56, 12, %57, 12, %58, 12, %59, 12, %60, 12, %61, 12, %62, 12, %63, 12, %64
-    DBG_INSTR_REF 1, 0, !14, !DIExpression(), debug-location !12
+    DBG_INSTR_REF !14, !DIExpression(), dbg-instr-ref(1, 0), debug-location !12
     ; CHECK:      DBG_PHI %stack.0, 1, 16
-    ; CHECK:      DBG_INSTR_REF 1, 0
+    ; CHECK:      DBG_INSTR_REF {{.+}} dbg-instr-ref(1, 0)
     ; CHECK:      renamable $eax = MOV32rm %stack.0,
     $eax = COPY killed %0, debug-location !19
     RET 0, killed $eax, debug-location !19
 
 ...

llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir

bb.2:
     %59:gr32 = PHI %19, %bb.0, %39, %bb.1, debug-location !18
     %60:gr32 = PHI %20, %bb.0, %40, %bb.1, debug-location !18
     %61:gr32 = PHI %21, %bb.0, %41, %bb.1, debug-location !18
     %62:gr32 = PHI %22, %bb.0, %42, %bb.1, debug-location !18
     %63:gr32 = PHI %23, %bb.0, %43, %bb.1, debug-location !18
     %64:gr32 = PHI %24, %bb.0, %44, %bb.1, debug-location !18
 
     INLINEASM &"", 1, 12, %50, 12, %51, 12, %52, 12, %53, 12, %54, 12, %55, 12, %56, 12, %57, 12, %58, 12, %59, 12, %60, 12, %61, 12, %62, 12, %63, 12, %64
-    DBG_INSTR_REF 1, 0, !14, !DIExpression(), debug-location !12
+    DBG_INSTR_REF !14, !DIExpression(), dbg-instr-ref(1, 0), debug-location !12
     ; CHECK-NOT:  DBG_PHI
-    ; CHECK:      DBG_INSTR_REF 1, 0
+    ; CHECK:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
     ; CHECK-NOT:  DBG_PHI
     $eax = COPY killed %0, debug-location !19
     RET 0, killed $eax, debug-location !19
 
 ...

llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir

bb.2:
     %58:gr32 = PHI %18, %bb.0, %38, %bb.1, debug-location !18
     %59:gr32 = PHI %19, %bb.0, %39, %bb.1, debug-location !18
     %60:gr32 = PHI %20, %bb.0, %40, %bb.1, debug-location !18
     %61:gr32 = PHI %21, %bb.0, %41, %bb.1, debug-location !18
     %62:gr32 = PHI %22, %bb.0, %42, %bb.1, debug-location !18
     %63:gr32 = PHI %23, %bb.0, %43, %bb.1, debug-location !18
     %64:gr32 = PHI %24, %bb.0, %44, %bb.1, debug-location !18
 
-    DBG_INSTR_REF 1, 0, !14, !DIExpression(), debug-location !12
+    DBG_INSTR_REF !14, !DIExpression(), dbg-instr-ref(1, 0), debug-location !12
     ; CHECK:      DBG_PHI %stack.1, 1, 32
     ; CHECK:      renamable $eax = MOV32rm %stack.1,
-    ; CHECK:      DBG_INSTR_REF 1, 0
+    ; CHECK:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
     $eax = COPY killed %0, debug-location !19
     RET 0, killed $eax, debug-location !19
 
 ...

llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir

bb.0.entry:
     JCC_1 %bb.2, 5, implicit killed $eflags, debug-location !17
     JMP_1 %bb.1, debug-location !17
 
   bb.1.if.else:
 
     ; CHECK-LABEL: bb.2.if.end:
   bb.2.if.end:
     %0:gr32 = PHI %1, %bb.0, %2, %bb.1, debug-instr-number 1, debug-location !18
-    DBG_INSTR_REF 1, 0, !14, !DIExpression(), debug-location !12
+    DBG_INSTR_REF !14, !DIExpression(), dbg-instr-ref(1, 0), debug-location !12
     ; CHECK:      DBG_PHI $ebp, 1
-    ; CHECK:      DBG_INSTR_REF 1, 0
+    ; CHECK:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
     $eax = COPY killed %0, debug-location !19
     ; Confirm that %0 is allocated in $ebp,
     ; CHECK:      $eax = COPY killed renamable $ebp
     RET 0, killed $eax, debug-location !19
 
 ...

llvm/test/DebugInfo/MIR/InstrRef/pick-vphi-in-shifting-loop.mir

 # RUN: llc %s -o - -run-pass=livedebugvalues \
 # RUN:     -experimental-debug-variable-locations \
 # RUN: | FileCheck %s
 #
 # This test used to cause an infinite loop in InstrRefBasedLDV. Observe block
 # five: on the first entry the desired variable value is in $rdx and $rcx, on
 # both paths to the block. However, the block rotates values between those
 # registers, and feeds a zero-value in too. Ultimately, there is no correct
 # location for the variable in that block.
 # This caused an infinite loop in a previous implementation of LiveDebugValues.
 # Keep this around as a regression test, and check that no location is picked
 # in block 5.
 #
 # CHECK-LABEL: bb.3:
-# CHECK:       DBG_INSTR_REF 7, 0
+# CHECK:       DBG_INSTR_REF {{.+}}, dbg-instr-ref(7, 0)
 # CHECK-NEXT:  DBG_VALUE $rdx
 # CHECK-NEXT:  $rcx = MOV64rr $rdx
 # CHECK-LABEL: bb.4:
 # CHECK:       DBG_VALUE $rcx
 # CHECK-NEXT:  $rdx = MOV64rr killed $rcx
 # CHECK-LABEL: bb.5:
 # CHECK-NOT:   DBG_VALUE
 --- |
bb.0:
     $rdx = MOV64ri 0, implicit-def $eflags
     $esi = MOV32ri 0, implicit-def $eflags
   
   bb.1:
     successors: %bb.2(0x03e0f83e), %bb.1(0x7c1f07c2)
     liveins: $rcx, $rdi, $rdx, $eflags
   
     DBG_PHI $rcx, 2
-    DBG_INSTR_REF 2, 0, !18, !DIExpression(), debug-location !22
+    DBG_INSTR_REF !18, !DIExpression(), dbg-instr-ref(2, 0), debug-location !22
     JCC_1 %bb.1, 4, implicit $eflags, debug-location !22
   
   bb.2:
     successors: %bb.4(0x30000000), %bb.3(0x50000000)
     liveins: $rcx, $rdi, $eflags
   
     JCC_1 %bb.4, 4, implicit $eflags, debug-location !22
   
   bb.3:
     successors: %bb.5(0x04000000)
     liveins: $rcx, $rdi, $eflags
   
     $rdx = MOV64ri 0, debug-instr-number 7, debug-location !22
-    DBG_INSTR_REF 7, 0, !18, !DIExpression(), debug-location !22
+    DBG_INSTR_REF !18, !DIExpression(), dbg-instr-ref(7, 0), debug-location !22
     $rcx = MOV64rr $rdx
     JMP_1 %bb.5, debug-location !22
   
   bb.4:
     liveins: $rcx, $rdi, $eflags
   
     $rdx = MOV64rr killed $rcx, debug-location !22
   

llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir

 #
 ## There should be no variable location, just a single DBG_VALUE $noreg.
 # CHECK:     DBG_VALUE $noreg
 #
 ## And then another.
 # CHECK:     DBG_VALUE $noreg
 #
 ## Test that if there's no limit, we _do_ get some locations.
-# NOLIMIT:      DBG_INSTR_REF 1, 0
+# NOLIMIT:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
 # NOLIMIT-NEXT: DBG_VALUE $esi
 #
-# NOLIMIT:      DBG_INSTR_REF 5,
+# NOLIMIT:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(5,
 # NOLIMIT-NEXT: DBG_VALUE $rsp
 --- |
   define i8 @test(i32 %bar) local_unnamed_addr !dbg !7 {
   entry:
     ret i8 0, !dbg !12
   }
 
   declare dso_local void @ext(i64)
liveins: $rdi, $rax, $rbx
     $edi = COPY $eax
     MOV64mr $rsp, 1, $noreg, 16, $noreg, $rdi :: (store 8 into %stack.0)
     $rsi = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0)
 
     MOV64mr $rsp, 1, $noreg, 16, $noreg, $rbx :: (store 8 into %stack.0)
     $rax = MOV64ri 0
     $rdi = MOV64ri 0
 
-    DBG_INSTR_REF 1, 0, !11, !DIExpression(), debug-location !12
+    DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(1, 0), debug-location !12
     ; This shouldn't find anything -- we have disabled tracking of spills.
 
     ; In addition to plain spills, spills that are folded into instructions
     ; shouldn't be tracked either.
     INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-instr-number 5, debug-location !12 :: (store (s32) into %stack.0)
 
 
-    DBG_INSTR_REF 5, 1000000, !11, !DIExpression(), debug-location !12
+    DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(5, 1000000), debug-location !12
     ; Shouldn't be able to find the reference to instr 5's memory operand.
 
     RET64 $rsi, debug-location !12
 ...

llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir

body:             |
   bb.13:
     successors: %bb.18(0x2aaaaaab), %bb.14(0x55555555)
   
     %2:gr32 = PHI undef %35:gr32, %bb.11, %14, %bb.21
     %3:gr64 = PHI %36, %bb.11, %13, %bb.21
     ;AAAAAA %4:gr32 = PHI %0, %bb.11, %10, %bb.21, debug-instr-number 1
     ;BBBBBB %4:gr32 = PHI %0, %bb.11, %10, %bb.21
     %5:gr32 = PHI undef %35:gr32, %bb.11, %9, %bb.21
-    ;AAAAAA DBG_INSTR_REF 1, 0, !10, !DIExpression(), debug-location !9
+    ;AAAAAA DBG_INSTR_REF !10, !DIExpression(), dbg-instr-ref(1, 0), debug-location !9
     ;BBBBBB DBG_VALUE %4, 0, !10, !DIExpression(), debug-location !9
     %39:gr8 = COPY %27.sub_8bit
     TEST8rr killed %39, %39, implicit-def $eflags, debug-location !9
     JCC_1 %bb.18, 5, implicit killed $eflags, debug-location !9
     JMP_1 %bb.14, debug-location !9
   
   bb.14:
     successors: %bb.17(0x40000001), %bb.15(0x3fffffff)

llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir

 # RUN: llc %s -march=x86-64 -run-pass=machineverifier \
 # RUN:     -experimental-debug-variable-locations -o - 2>&1 | FileCheck %s
 #
 # REQUIRES: x86-registered-target
 #
 # CHECK:      debugValueSubstitutions:
 # CHECK-NEXT: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 }
 #
 # CHECK:      MOV64rr $rdi, debug-instr-number 2
-# CHECK-NEXT: DBG_INSTR_REF 1, 0
+# CHECK-NEXT: DBG_INSTR_REF dbg-instr-ref(1, 0)
 ---
 name: test
 tracksRegLiveness: true
 liveins:
   - { reg: '$rdi', virtual-reg: '' }
 debugValueSubstitutions:
   - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 }
 body:  |
   bb.0:
   liveins: $rdi, $rax
     $rbp = MOV64rr $rdi, debug-instr-number 2
-    DBG_INSTR_REF 1, 0
+    DBG_INSTR_REF dbg-instr-ref(1, 0)
     dead $rcx = MOV64ri 0
     CMP64ri8 renamable $rax, 1, implicit-def $eflags
     RET64 $rax
 ...

llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir

 # RUN: llc -start-after=phi-node-elimination -stop-after=virtregrewriter %s -mtriple=x86_64-unknown-unknown -o - -experimental-debug-variable-locations | FileCheck %s
 # RUN: llc -O0 -start-after=phi-node-elimination -stop-after=regallocfast %s -mtriple=x86_64-unknown-unknown -o - -experimental-debug-variable-locations | FileCheck %s --check-prefix=FASTREG
 #
 # Test that DBG_INSTR_REFs can pass through livedebugvariables to the end of
 # regalloc without problem. Program body copied from
 # livedebugvars-crossbb-interval.mir.
 #
 # CHECK-LABEL: bb.0:
-# CHECK:       DBG_INSTR_REF 1, 0
+# CHECK:       DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
 # CHECK-NEXT:  JMP_1
 # CHECK-LABEL: bb.1:
-# CHECK:       DBG_INSTR_REF 2, 0
+# CHECK:       DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
 # CHECK-NEXT:  JMP_1
 # CHECK-LABEL: bb.2:
-# CHECK:       DBG_INSTR_REF 3, 0
+# CHECK:       DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
 # CHECK-NEXT:  CALL64pcrel32
 # CHECK-LABEL: bb.3:
-# CHECK:       DBG_INSTR_REF 4, 0
+# CHECK:       DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
 # CHECK-NEXT:  JMP_1
 #
 #
 # The fast register allocator puts some spills in -- these are no-ops as far
 # as the slot indexes are concerned. It doesn't matter which side of spills
 # the DBG_INSTR_REF lands on.
 #
 # FASTREG-LABEL: bb.0:
-# FASTREG-DAG:   DBG_INSTR_REF 1, 0
+# FASTREG-DAG:   DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
 # FASTREG-DAG:   MOV64mr
 # FASTREG-DAG:   MOV32mr
 # FASTREG-NEXT:  JMP_1
 # FASTREG-LABEL: bb.1:
-# FASTREG:       DBG_INSTR_REF 2, 0
+# FASTREG:       DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
 # FASTREG-NEXT:  JMP_1
 # FASTREG-LABEL: bb.2:
-# FASTREG:       DBG_INSTR_REF 3, 0
+# FASTREG:       DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
 # FASTREG-NEXT:  CALL64pcrel32
 # FASTREG-LABEL: bb.3:
 # FASTREG-DAG:   MOV32rm
-# FASTREG-DAG:   DBG_INSTR_REF 4, 0
+# FASTREG-DAG:   DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
 # FASTREG-DAG:   MOV32mr
 # FASTREG-NEXT:  JMP_1
 # FASTREG-LABEL: bb.4:
-# FASTREG:       DBG_INSTR_REF 5, 0
+# FASTREG:       DBG_INSTR_REF {{.+}}, dbg-instr-ref(5, 0)
 # FASTREG-NEXT:  RET64
 
 --- |
   ; ModuleID = 'tmp.ll'
   source_filename = "tmp.ll"
   target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 
   %struct.a = type { i32 }

 body:             |
   bb.0:
     liveins: $rdi, $esi
 
     %4:gr32 = COPY $esi
     %2:gr64 = COPY $rdi
     %3:gr64 = COPY killed %2
     %5:gr32 = COPY killed %4
-    DBG_INSTR_REF 1, 0, !9, !DIExpression(), debug-location !16
+    DBG_INSTR_REF !9, !DIExpression(), dbg-instr-ref(1, 0), debug-location !16
     JMP_1 %bb.3
 
   bb.1:
-    DBG_INSTR_REF 2, 0, !9, !DIExpression(), debug-location !16
+    DBG_INSTR_REF !9, !DIExpression(), dbg-instr-ref(2, 0), debug-location !16
     JMP_1 %bb.4
 
   bb.2:
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !19
     $edi = COPY %6, debug-location !19
     $al = MOV8ri 0, debug-location !19
-    DBG_INSTR_REF 3, 0, !9, !DIExpression(), debug-location !16
+    DBG_INSTR_REF !9, !DIExpression(), dbg-instr-ref(3, 0), debug-location !16
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $al, implicit $edi, implicit-def $eax, debug-location !19
     ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !19
     %7:gr32 = COPY $eax, debug-location !19
     JMP_1 %bb.1
 
   bb.3:
     %6:gr32 = MOV32rm %3, 1, $noreg, 0, $noreg, debug-location !17
-    DBG_INSTR_REF 4, 0, !9, !DIExpression(), debug-location !16
+    DBG_INSTR_REF !9, !DIExpression(), dbg-instr-ref(4, 0), debug-location !16
     JMP_1 %bb.2
 
   bb.4:
     $eax = COPY %5, debug-location !18
-    DBG_INSTR_REF 5, 0, !9, !DIExpression(), debug-location !16
+    DBG_INSTR_REF !9, !DIExpression(), dbg-instr-ref(5, 0), debug-location !16
     RET64 implicit $eax, debug-location !18
 
 ...

llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir

 # RUN: llc -run-pass=twoaddressinstruction -mtriple=x86_64-- -o - %s -experimental-debug-variable-locations | FileCheck %s
 #
 # REQUIRES: x86-registered-target
 #
 # Test that a new instruction (LEA) is created when the two-addr add below is
 # converted to three address; and that an appropriate substitution is created.
 # Maybe at some point we'll normalise DBG_INSTR_REFs on output, but until then,
 # lets not.
 #
 # CHECK:      debugValueSubstitutions:
 # CHECK-NEXT:  - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 }
 #
 # CHECK:      LEA64_32r
 # CHECK-SAME: debug-instr-number 2
 #
-# CHECK:      DBG_INSTR_REF 1, 0
+# CHECK:      DBG_INSTR_REF dbg-instr-ref(1, 0)
 ---
 name:            test1
 alignment:       16
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr32 }
   - { id: 2, class: gr32 }
 liveins:
   - { reg: '$edi', virtual-reg: '%0' }
 frameInfo:
   maxAlignment:    1
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $edi
 
     %0:gr32 = COPY killed $edi
     %1:gr32 = SHL32ri killed %0, 5, implicit-def dead $eflags
     %2:gr32 = ADD32ri8_DB killed %1, 3, implicit-def dead $eflags, debug-instr-number 1
-    DBG_INSTR_REF 1, 0
+    DBG_INSTR_REF dbg-instr-ref(1, 0)
     $eax = COPY killed %2
     RET 0, killed $eax
 
 ...
 

llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir

bb.0.entry:
     frame-setup SEH_StackAlloc 4
     frame-setup SEH_EndPrologue
     renamable $eax = MOV32rm $ebp, 1, $noreg, 8, $noreg, debug-location !40 :: (dereferenceable load (s32) from %ir.x.addr)
     MOV32mr $ebp, 1, $noreg, -4, $noreg, $esp, debug-location !41 :: (store (s32) into %ir.saved_stack)
     renamable $eax = SHL32ri killed renamable $eax, 2, implicit-def dead $eflags, debug-location !41
     CALLpcrel32 &_chkstk, implicit $esp, implicit $ssp, implicit $eax, implicit $esp, implicit-def dead $eax, implicit-def $esp, implicit-def dead $eflags, debug-instr-number 2, debug-location !41
     $ebx = MOV32rr $esp, debug-location !41
     $eax = MOV32ri 0
-    DBG_INSTR_REF 2, 6, !42, !DIExpression(DW_OP_deref), debug-location !46
-    ; CHECK-LABEL: DBG_INSTR_REF 2, 6
+    DBG_INSTR_REF !42, !DIExpression(DW_OP_deref), dbg-instr-ref(2, 6), debug-location !46
+    ; CHECK-LABEL: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 6)
     ; CHECK:       DBG_VALUE $esp
 
     ;; Variable value is $esp / $ebx, will be based on $esp initially. We'll now
     ;; allocate more stack space, and several things should happen:
     ;;  * We recognise it as modifying $esp, and move the variable location to
     ;;    be based on $ebx,
     ;;  * We recognise the modified $esp as a new value, and if we assign it to
     ;;    the variable location, will base the variable on $esp,
     ;;  * Clobbering the second modified $esp won't re-locate the variable to
     ;;    $ebx, which comes from the first modified $esp.
     CALLpcrel32 &_chkstk, implicit $esp, implicit $ssp, implicit $eax, implicit $esp, implicit-def dead $eax, implicit-def $esp, implicit-def dead $eflags, debug-instr-number 3, debug-location !41
     ; CHECK-NEXT: CALLpcrel32
     ; CHECK-NEXT: DBG_VALUE $ebx
 
-    DBG_INSTR_REF 3, 6, !42, !DIExpression(DW_OP_deref), debug-location !46
-    ; CHECK-NEXT: DBG_INSTR_REF 3, 6
+    DBG_INSTR_REF !42, !DIExpression(DW_OP_deref), dbg-instr-ref(3, 6), debug-location !46
+    ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 6)
     ; CHECK-NEXT: DBG_VALUE $esp
 
     $esp = ADD32ri killed $esp, 0, implicit-def dead $eflags
     ; CHECK-NEXT: ADD32ri
 
-    DBG_INSTR_REF 3, 6, !42, !DIExpression(DW_OP_deref), debug-location !46
-    ; CHECK-NEXT: DBG_INSTR_REF 3, 6
+    DBG_INSTR_REF !42, !DIExpression(DW_OP_deref), dbg-instr-ref(3, 6), debug-location !46
+    ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 6)
     ; CHECK-NEXT: DBG_VALUE $noreg
 
     $esp = MOV32rr $ebp, debug-location !49
     $ebp = frame-destroy POP32r implicit-def $esp, implicit $esp, debug-location !49
     RET32 debug-location !49
 
 ...

llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir

 body:             |
   bb.0._ZN4llvm11raw_ostreamlsEPKc.exit2752:
     successors: %bb.1(0x30000000), %bb.2(0x50000000)
   
     %1:gr64 = IMPLICIT_DEF
     %0:gr64 = MOV64rm killed %1, 1, $noreg, 0, $noreg, debug-location !7 :: (load (s64) from `i8** undef`)
     %2:gr32 = COPY %0.sub_32bit, debug-location !7
     %3:gr32 = SUB32rm %2, %0, 1, $noreg, 0, $noreg, implicit-def $eflags, debug-instr-number 1, debug-location !7 :: (load (s32) from %ir._M_start.i2756, align 8)
-    DBG_INSTR_REF 1, 0, !8, !DIExpression(), debug-location !7
+    DBG_INSTR_REF !8, !DIExpression(), dbg-instr-ref(1, 0), debug-location !7
     JCC_1 %bb.2, 5, implicit $eflags, debug-location !7
     JMP_1 %bb.1, debug-location !7
   
   bb.1.for.cond.cleanup376:
     RET 0
   
   bb.2.for.body377:
     RET 0
 
 ...

llvm/test/DebugInfo/MIR/X86/instr-ref-join-def-vphi.mir

bb.3 (%ir-block.13, align 16):
     JCC_1 %bb.4, 14, implicit $eflags, debug-location !26
 
   bb.1 (%ir-block.3):
     successors: %bb.2(0x30000000), %bb.3(0x50000000)
     liveins: $edi, $esi
 
     DBG_PHI $esi, 3
     DBG_PHI $edi, 2
-    DBG_INSTR_REF 3, 0, !14, !DIExpression(), debug-location !16
+    DBG_INSTR_REF !14, !DIExpression(), dbg-instr-ref(3, 0), debug-location !16
     CALL64pcrel32 @"?bar@@YAHXZ", csr_win64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !19
     renamable $edi = nsw SUB32rr killed renamable $edi, killed renamable $eax, implicit-def dead $eflags, debug-instr-number 1, debug-location !19
     renamable $eax = IMUL32rri renamable $edi, -1431655765, implicit-def dead $eflags, debug-location !21
     renamable $eax = ADD32ri killed renamable $eax, 715827882, implicit-def dead $eflags, debug-location !21
     CMP32ri killed renamable $eax, 1431655764, implicit-def $eflags, debug-location !21
     JCC_1 %bb.3, 7, implicit $eflags, debug-location !21
 
   bb.2 (%ir-block.10):
     successors: %bb.3(0x80000000)
     liveins: $edi, $esi
 
     CALL64pcrel32 @"?bar@@YAHXZ", csr_win64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !22
     renamable $esi = nsw ADD32rr killed renamable $esi, killed renamable $eax, implicit-def dead $eflags, debug-instr-number 4, debug-location !22
-    DBG_INSTR_REF 4, 0, !14, !DIExpression(), debug-location !16
+    DBG_INSTR_REF !14, !DIExpression(), dbg-instr-ref(4, 0), debug-location !16
     JMP_1 %bb.3
 
   bb.4 (%ir-block.16):
     successors: %bb.5(0x40000000), %bb.6(0x40000000)
     liveins: $edi, $esi
 
     TEST8ri renamable $dil, 1, implicit-def $eflags, implicit killed $edi, debug-location !30
     JCC_1 %bb.6, 5, implicit $eflags, debug-location !30
 
   bb.5 (%ir-block.19):
     successors: %bb.6(0x80000000)
     liveins: $esi
 
     CALL64pcrel32 @"?bar@@YAHXZ", csr_win64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !31
-    DBG_INSTR_REF 5, 0, !14, !DIExpression(), debug-location !16
+    DBG_INSTR_REF !14, !DIExpression(), dbg-instr-ref(5, 0), debug-location !16
 
   bb.6 (%ir-block.22):
     liveins: $esi
 
     $eax = MOV32rr killed $esi, debug-location !35
     SEH_Epilogue debug-location !35
     $rsp = frame-destroy ADD64ri8 $rsp, 40, implicit-def dead $eflags, debug-location !35
     $rdi = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !35
     $rsi = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !35
     RET64 $eax, debug-location !35
 
 ...

llvm/test/DebugInfo/X86/dbg-value-arg-movement.ll

 ; CHECK-LABEL: bb.1.next
 ; Correctly place dbg.value in the 'next' block.
 ; CHECK:       DBG_VALUE [[ARGREG]], $noreg, [[XYZVAR]]
 
 ; INSTRREF-LABEL: body
 ; INSTRREF: DBG_PHI $edi, 1
 ; INSTRREF: DBG_VALUE $edi, $noreg, [[BAZVAR]]
 ; INSTRREF-LABEL: bb.1.next
-; INSTRREF: DBG_INSTR_REF 1, 0, [[XYZVAR]],
+; INSTRREF: DBG_INSTR_REF [[XYZVAR]], {{.+}}, dbg-instr-ref(1, 0)
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 declare i32 @ext()
 
 define dso_local i32 @bar(i32, i32) local_unnamed_addr !dbg !7 {
   %3 = srem i32 %1, %0, !dbg !15

llvm/test/DebugInfo/X86/dbg-value-funcarg.ll

 ; INSTRREF-LABEL: name:            foo_local
 ; INSTRREF-NOT: DBG_
 ; INSTRREF:      DBG_PHI $edi, 1
 ; INSTRREF:      DBG_VALUE $edi, $noreg, ![[T1A]], !DIExpression(),
 ; INSTRREF-NEXT: %0:gr32 = COPY $edi
 ; INSTRREF-NEXT: DBG_VALUE 123, $noreg, ![[LOCAL]], !DIExpression(),
 ; INSTRREF:      CALL64pcrel32 @bar,
 ; INSTRREF-NEXT: ADJCALLSTACKUP64
-; INSTRREF:      DBG_INSTR_REF 1, 0, ![[LOCAL]], !DIExpression(),
+; INSTRREF:      DBG_INSTR_REF ![[LOCAL]], !DIExpression(), dbg-instr-ref(1, 0),
 ; INSTRREF-NOT: DBG_
 ; INSTRREF:    TCRETURNdi64 @bar,
 
 entry:
   call void @llvm.dbg.value(metadata i32 %t1a, metadata !12, metadata !DIExpression()), !dbg !14
   call void @llvm.dbg.value(metadata i32 123, metadata !13, metadata !DIExpression()), !dbg !15
   tail call void @bar(i32 123) #3, !dbg !16
   call void @llvm.dbg.value(metadata i32 %t1a, metadata !13, metadata !DIExpression()), !dbg !15

 ; CHECK: TCRETURNdi64 @bar,
 ; INSTRREF-LABEL: name:            foo_other_param
 ; INSTRREF: DBG_PHI $edi, 1
 ; INSTRREF: DBG_VALUE $edi, $noreg, ![[T2A]], !DIExpression(),
 ; INSTRREF: DBG_VALUE $esi, $noreg, ![[T2B]], !DIExpression(),
 ; INSTRREF: CALL64pcrel32 @bar,
 ; INSTRREF: DBG_VALUE 123, $noreg, ![[T2B]], !DIExpression(),
 ; INSTRREF: CALL64pcrel32 @bar,
-; INSTRREF: DBG_INSTR_REF 1, 0, ![[T2B]], !DIExpression(),
+; INSTRREF: DBG_INSTR_REF ![[T2B]], !DIExpression(), dbg-instr-ref(1, 0),
 ; INSTRREF: TCRETURNdi64 @bar,
 
 entry:
   call void @llvm.dbg.value(metadata i32 %t2a, metadata !23, metadata !DIExpression()), !dbg !25
   call void @llvm.dbg.value(metadata i32 %t2b, metadata !24, metadata !DIExpression()), !dbg !26
   tail call void @bar(i32 %t2b) #3, !dbg !27
   call void @llvm.dbg.value(metadata i32 123, metadata !24, metadata !DIExpression()), !dbg !26
   tail call void @bar(i32 123) #3, !dbg !28

 ; CHECK: DBG_VALUE 123, $noreg, ![[T3A]], !DIExpression(),
 ; CHECK: CALL64pcrel32 @bar,
 ; CHECK: DBG_VALUE %0, $noreg, ![[T3A]], !DIExpression(),
 ; CHECK: TCRETURNdi64 @bar,
 ; INSTRREF-LABEL: name:            foo_same_param
 ; INSTRREF: DBG_PHI $edi, 1
 ; INSTRREF: DBG_VALUE $edi, $noreg, ![[T3A]], !DIExpression(),
 ; INSTRREF: CALL64pcrel32 @bar,
-; INSTRREF: DBG_INSTR_REF 1, 0, ![[TMP]], !DIExpression(),
+; INSTRREF: DBG_INSTR_REF ![[TMP]], !DIExpression(), dbg-instr-ref(1, 0),
 ; INSTRREF: DBG_VALUE 123, $noreg, ![[T3A]], !DIExpression(),
 ; INSTRREF: CALL64pcrel32 @bar,
-; INSTRREF: DBG_INSTR_REF 1, 0, ![[T3A]], !DIExpression(),
+; INSTRREF: DBG_INSTR_REF ![[T3A]], !DIExpression(), dbg-instr-ref(1, 0),
 ; INSTRREF: TCRETURNdi64 @bar,
 entry:
   call void @llvm.dbg.value(metadata i32 %t3a, metadata !33, metadata !DIExpression()), !dbg !35
   tail call void @bar(i32 %t3a) #3, !dbg !36
   call void @llvm.dbg.value(metadata i32 %t3a, metadata !34, metadata !DIExpression()), !dbg !37
   call void @llvm.dbg.value(metadata i32 123, metadata !33, metadata !DIExpression()), !dbg !35
   tail call void @bar(i32 123) #3, !dbg !38
   call void @llvm.dbg.value(metadata i32 %t3a, metadata !33, metadata !DIExpression()), !dbg !35

llvm/test/DebugInfo/X86/dbg-value-funcarg2.ll

 ; CHECK-NOT: DBG_VALUE
 ; CHECK-DAG: DBG_VALUE %[[R2]], $noreg, ![[S1]], !DIExpression(DW_OP_LLVM_fragment, 0, 64)
 ; CHECK-DAG: DBG_VALUE %[[R1]], $noreg, ![[S1]], !DIExpression(DW_OP_LLVM_fragment, 64, 64)
 
 ;; In instruction referencing mode, we should refer to the instruction number
 ;; of the earlier DBG_PHIs.
 ; INSTRREF:     ADJCALLSTACKUP
 ; INSTRREF-NOT: DBG_
-; INSTRREF-DAG: DBG_INSTR_REF 1, 0, ![[S1]], !DIExpression(DW_OP_LLVM_fragment, 0, 64)
-; INSTRREF-DAG: DBG_INSTR_REF 2, 0, ![[S1]], !DIExpression(DW_OP_LLVM_fragment, 64, 64)
+; INSTRREF-DAG: DBG_INSTR_REF ![[S1]], !DIExpression(DW_OP_LLVM_fragment, 0, 64), dbg-instr-ref(1, 0)
+; INSTRREF-DAG: DBG_INSTR_REF ![[S1]], !DIExpression(DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(2, 0)
 
 ; And then no more DBG_ instructions before the add.
 ; COMMON-NOT: DBG_
 ; COMMON:     ADD32rr
 
 entry:
   %tmp.sroa.0 = alloca i64, align 8
   %tmp.sroa.4 = alloca i64, align 8

llvm/test/DebugInfo/X86/dbg-value-funcarg4.ll

 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -start-after=codegenprepare -stop-before=finalize-isel -o - %s -experimental-debug-variable-locations=true | FileCheck %s --implicit-check-not=DBG_PHI
 
 ; Test that for multiple dbg.values referring to the same argument, we emit a
 ; single DBG_PHI and refer to it twice. (Using more than one DBG_PHI is fine,
 ; but inefficient).
 
 ; CHECK-DAG: ![[LOCAL:.*]] = !DILocalVariable(name: "local"
 ; CHECK-DAG: ![[LOCAL2:.*]] = !DILocalVariable(name: "local2"
 
 ; CHECK: DBG_PHI $edi, 1
 
-; CHECK: DBG_INSTR_REF 1, 0, ![[LOCAL]], !DIExpression(),
-; CHECK: DBG_INSTR_REF 1, 0, ![[LOCAL2]], !DIExpression(),
+; CHECK: DBG_INSTR_REF ![[LOCAL]], !DIExpression(), dbg-instr-ref(1, 0)
+; CHECK: DBG_INSTR_REF ![[LOCAL2]], !DIExpression(), dbg-instr-ref(1, 0)
 
 declare void @bar(i32)
 declare void @llvm.dbg.value(metadata, metadata, metadata)
 
 define dso_local void @foo_local(i32 %t1a) local_unnamed_addr !dbg !7 {
 entry:
   tail call void @bar(i32 %t1a) #3, !dbg !17
   %bees = add i32 %t1a, 3

llvm/test/DebugInfo/X86/instr-ref-dbg-declare.ll

 ; RUN: llc %s -stop-before=finalize-isel -o - \
 ; RUN:     -experimental-debug-variable-locations=true \
 ; RUN:  | FileCheck %s
 
 ;; Copy of DebugInfo/COFF/types-array-advanced.ll. This features a dbg.declare 
 ;; of something (dynamic alloca) that isn't an argument, causing a SDDbgValue
 ;; with the indirect flag set to be emitted. Test that it's preserved in
 ;; instruction referencing mode -- we don't have an IsIndirect flag on
 ;; DBG_INSTR_REF, so it gets encoded as an additional DW_OP_deref.
 ;;
 ;; NB: the original test has an additional spurious DW_OP_deref in the
 ;; dbg.declare's arguments, which is preserved here, translating to two derefs.
 
-; CHECK: DBG_INSTR_REF 1, 2, !{{[0-9]+}}, !DIExpression(DW_OP_deref, DW_OP_deref)
+; CHECK: DBG_INSTR_REF !{{[0-9]+}}, !DIExpression(DW_OP_deref, DW_OP_deref), dbg-instr-ref(1, 2)
 
 source_filename = "test/DebugInfo/COFF/types-array-advanced.ll"
 target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
 target triple = "i686-pc-windows-msvc18.0.31101"
 
 %struct.incomplete_struct = type { i32 }
 
 @"\01?multi_dim_arr@@3PAY146DA" = global [2 x [5 x [7 x i8]]] zeroinitializer, align 1, !dbg !0

llvm/test/DebugInfo/X86/instr-ref-dyn-alloca-win32.ll

 ; RUN: llc %s -o - -stop-after=machine-sink \
 ; RUN:     -experimental-debug-variable-locations=true \
 ; RUN:    | FileCheck %s --check-prefixes=DYN_LABEL
 ; RUN: llc %s -o - -stop-before=phi-node-elimination \
 ; RUN:     -experimental-debug-variable-locations=true \
 ; RUN:    | FileCheck %s --check-prefixes=DYN_LOWERED
 
 ;; This is a copy of DebugInfo/COFF/types-array-advanced.ll, checking that
 ;; DYN_ALLOCAs correctly have instruction references updated. This is compiled
 ;; from LLVM-IR because the "hasDynAlloca" flag isn't serialised to MIR, for
 ;; complicated reasons, that means we can't store as MIR.
 
 ;; The alloca instruction should be labelled, and we should refer to operand 2,
 ;; which happens to be a def of $esp
 ; DYN_LABEL: DYN_ALLOCA_32 {{.*}} debug-instr-number 1,
-; DYN_LABEL: DBG_INSTR_REF 1, 2
+; DYN_LABEL: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 2)
 
 ;; Once lowered, on win32 _chkstk alters the stack pointer. We should label the
 ;; call and it's SP operand, plus check for a value substitution.
 ; DYN_LOWERED:      debugValueSubstitutions:
 ; DYN_LOWERED-NEXT: - { srcinst: 1, srcop: 2, dstinst: 2, dstop: 6, subreg: 0 }
 ;; Test that it's operand six, and labelled.
 ; DYN_LOWERED:      CALLpcrel32 &_chkstk, implicit $esp, implicit $ssp,
 ; DYN_LOWERED-SAME: implicit killed $eax, implicit $esp, implicit-def dead $eax,

llvm/test/DebugInfo/X86/instr-ref-ir-reg-read.ll

 ; RUN: llc %s -start-after=codegenprepare -stop-before=finalize-isel \
 ; RUN:    -experimental-debug-variable-locations=true  -o - \
 ; RUN: | FileCheck %s
 
 ; Test that the given input doesn't crash with instrruction referencing variable
 ; locations. The use of llvm.read_register allows the IR to access any register
 ; at any point, which is unfortunate, but a use case that needs to be supported.
 ;
 ; Just examine to see that we read something from $rsp.
 ; CHECK-LABEL: bb.1.if.then:
 ; CHECK:       DBG_PHI $rsp, 1
-; CHECK:       DBG_INSTR_REF 1, 0
+; CHECK:       DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
 
 source_filename = "tlb-9e7172.c"
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-cros-linux-gnu"
 
 @c = dso_local local_unnamed_addr global i32 0, align 4, !dbg !0
 
 ; Function Attrs: noredzone nounwind null_pointer_is_valid optsize sspstrong

llvm/test/DebugInfo/X86/instr-ref-sdag-empty-vreg.ll

 ; RUN: llc %s -o - -stop-before=finalize-isel \
 ; RUN:  -experimental-debug-variable-locations \
 ; RUN: | FileCheck %s
 
 ;; The multiply by zero of %width below causes %width to become unused very late
 ;; in SelectionDAG. As a result, DBG_INSTR_REFs are produced that refer to a
 ;; vreg that is never defined, which risks a crash. Check that we don't crash,
 ;; and produce an empty variable location.
 
-; CHECK: DBG_VALUE $noreg
+; CHECK: DBG_VALUE_LIST {{.+}}, $noreg
 
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-unknown"
 
 %class.Color = type { i8 }
 
 define hidden void @_Z14drawXZWideLineR4Vec3RK5Colorf(ptr %color, float %width) local_unnamed_addr !dbg !7 {
 cond.false.i:

llvm/test/DebugInfo/X86/instr-ref-selectiondag.ll

 ; Note that I'm baking in an assumption of one-based ordering here. We could
 ; capture and check for the instruction numbers, we'd rely on machine verifier
 ; ensuring there were no duplicates.
 
 ; INSTRREF-LABEL: name: foo
 
 ; INSTRREF:      ADD32rr
 ; INSTRREF-SAME: debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0
+; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
 ; INSTRREF-NEXT: ADD32rr
 ; INSTRREF-SAME: debug-instr-number 2
-; INSTRREF-NEXT: DBG_INSTR_REF 2, 0
+; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
 
 ; Test that fast-isel will produce DBG_INSTR_REFs too.
 
 ; FASTISEL-INSTRREF-LABEL: name: foo
 
 ; FASTISEL-INSTRREF:      ADD32rr
 ; FASTISEL-INSTRREF-SAME: debug-instr-number 1
-; FASTISEL-INSTRREF-NEXT: DBG_INSTR_REF 1, 0
+; FASTISEL-INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
 ; FASTISEL-INSTRREF-NEXT: ADD32rr
 ; FASTISEL-INSTRREF-SAME: debug-instr-number 2
-; FASTISEL-INSTRREF-NEXT: DBG_INSTR_REF 2, 0
+; FASTISEL-INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
 
 @glob32 = global i32 0
 @glob16 = global i16 0
 @glob8 = global i8 0
 
 declare void @llvm.dbg.value(metadata, metadata, metadata)
 declare void @llvm.dbg.declare(metadata, metadata, metadata)
 

 ; INSTRREF-NEXT: DBG_PHI $rdi, 3
 ; INSTRREF-NEXT: DBG_PHI $rdi, 1
 ;; Allow arguments to be specified by physreg DBG_VALUEs.
 ; INSTRREF-NEXT: DBG_VALUE $rdi
 
 ;; Don't test the location of these instr-refs, only that the three non-argument
 ;; dbg.values become DBG_INSTR_REFs. We previously checked that these numbers
 ;; get substituted, with appropriate subregister qualifiers.
-; INSTRREF:      DBG_INSTR_REF 2, 0
-; INSTRREF:      DBG_INSTR_REF 4, 0
-; INSTRREF:      DBG_INSTR_REF 6, 0
+; INSTRREF:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
+; INSTRREF:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
+; INSTRREF:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(6, 0)
 
 ;; In fast-isel, we get four DBG_INSTR_REFs (compared to three and one
 ;; DBG_VALUE with normal isel). We get additional substitutions as a result:
 
 ; FASTISEL-INSTRREF:      debugValueSubstitutions:
 ; FASTISEL-INSTRREF-NEXT: - { srcinst: 3, srcop: 0, dstinst: 2, dstop: 0, subreg: 6 }
 ; FASTISEL-INSTRREF-NEXT: - { srcinst: 5, srcop: 0, dstinst: 4, dstop: 0, subreg: 6 }
 ; FASTISEL-INSTRREF-NEXT: - { srcinst: 6, srcop: 0, dstinst: 5, dstop: 0, subreg: 4 }
 ; FASTISEL-INSTRREF-NEXT  - { srcinst: 8, srcop: 0, dstinst: 7, dstop: 0, subreg: 6 }
 ; FASTISEL-INSTRREF-NEXT  - { srcinst: 9, srcop: 0, dstinst: 8, dstop: 0, subreg: 4 }
 ; FASTISEL-INSTRREF-NEXT  - { srcinst: 10, srcop: 0, dstinst: 9, dstop: 0, subreg: 1 }
 
 ;; Those substitutions are anchored against these DBG_PHIs:
 
 ; FASTISEL-INSTRREF:      DBG_PHI $rdi, 7
 ; FASTISEL-INSTRREF-NEXT: DBG_PHI $rdi, 4
 ; FASTISEL-INSTRREF-NEXT: DBG_PHI $rdi, 2
 ; FASTISEL-INSTRREF-NEXT: DBG_PHI $rdi, 1
 
-; FASTISEL-INSTRREF:      DBG_INSTR_REF 1, 0
-; FASTISEL-INSTRREF:      DBG_INSTR_REF 3, 0
-; FASTISEL-INSTRREF:      DBG_INSTR_REF 6, 0
-; FASTISEL-INSTRREF:      DBG_INSTR_REF 10, 0
+; FASTISEL-INSTRREF:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
+; FASTISEL-INSTRREF:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
+; FASTISEL-INSTRREF:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(6, 0)
+; FASTISEL-INSTRREF:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(10, 0)
 
 define i32 @bar(i64 %bar) !dbg !20 {
 entry:
   call void @llvm.dbg.value(metadata i64 %bar, metadata !21, metadata !DIExpression()), !dbg !22
   %0 = trunc i64 %bar to i32, !dbg !22
   call void @llvm.dbg.value(metadata i32 %0, metadata !21, metadata !DIExpression()), !dbg !22
   store i32 %0, ptr @glob32, !dbg !22
   %1 = trunc i32 %0 to i16, !dbg !22

 ; NORMAL:      %1:gr16 = COPY %0.sub_16bit
 
 ; INSTRREF-LABEL: name: baz
 
 ; INSTRREF:      debugValueSubstitutions:
 ; INSTRREF-NEXT:  - { srcinst: 2, srcop: 0, dstinst: 1, dstop: 6, subreg: 4 }
 
 ; INSTRREF:      CALL64pcrel32 target-flags(x86-plt) @xyzzy, csr_64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $rax, debug-instr-number 1
-; INSTRREF:      DBG_INSTR_REF 2, 0
+; INSTRREF:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
 
 ;; Fast-isel produces the same arrangement, a DBG_INSTR_REF pointing back to
 ;; the call instruction. However: the operand numbers are different (6 for
 ;; normal isel, 4 for fast-isel). This isn't because of debug-info differences,
 ;; it's because normal isel implicit-defs the stack registers, and fast-isel
 ;; does not. The meaning is the same.
 
 ; FASTISEL-INSTRREF-LABEL: name: baz
 
 ; FASTISEL-INSTRREF:      debugValueSubstitutions:
 ; FASTISEL-INSTRREF-NEXT:  - { srcinst: 2, srcop: 0, dstinst: 1, dstop: 4, subreg: 4 }
 
 ; FASTISEL-INSTRREF:      CALL64pcrel32 target-flags(x86-plt) @xyzzy, csr_64, implicit $rsp, implicit $ssp, implicit-def $rax, debug-instr-number 1
-; FASTISEL-INSTRREF:      DBG_INSTR_REF 2, 0
+; FASTISEL-INSTRREF:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
 
 declare i64 @xyzzy()
 
 define i32 @baz() !dbg !30 {
 entry:
   %foo = call i64 @xyzzy(), !dbg !32
   br label %shoes
 

 ;; In instruction referencing mode, the "real" argument becomes a DBG_VALUE,
 ;; but the hoisted variable location from the inlined scope is a DBG_INSTR_REF.
 
 ; INSTRREF-LABEL: name: qux
 
 ; INSTRREF:      DBG_PHI $rdi, 1
 ; INSTRREF-NEXT: DBG_VALUE $rdi, 0, ![[SOCKS]], !DIExpression(),
 ; INSTRREF-NEXT: %0:gr64 = COPY $rdi
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[KNEES]], !DIExpression(DW_OP_deref),
+; INSTRREF-NEXT: DBG_INSTR_REF ![[KNEES]], !DIExpression(DW_OP_deref), dbg-instr-ref(1, 0),
 
 ; In fast-isel mode, neither variable are hoisted or forwarded to a physreg.
 
 ; FASTISEL-INSTRREF-LABEL: name: qux
 
 ; FASTISEL-INSTRREF:      DBG_PHI $rdi, 1
-; FASTISEL-INSTRREF:      DBG_INSTR_REF 1, 0, ![[SOCKS]], !DIExpression(DW_OP_deref),
+; FASTISEL-INSTRREF:      DBG_INSTR_REF ![[SOCKS]], !DIExpression(DW_OP_deref), dbg-instr-ref(1, 0),
 
 ; FASTISEL-INSTRREF-LABEL: bb.1.lala:
-; FASTISEL-INSTRREF:      DBG_INSTR_REF 1, 0, ![[KNEES]], !DIExpression(DW_OP_deref),
+; FASTISEL-INSTRREF:      DBG_INSTR_REF ![[KNEES]], !DIExpression(DW_OP_deref), dbg-instr-ref(1, 0),
 declare i64 @cheddar(ptr %arg)
 
 define void @qux(ptr noalias sret(i32) %agg.result) !dbg !40 {
 entry:
   call void @llvm.dbg.declare(metadata ptr %agg.result, metadata !41, metadata !DIExpression()), !dbg !42
   %foo = call i64 @cheddar(ptr %agg.result), !dbg !42
   br label %lala
 

llvm/test/DebugInfo/X86/pr34545.ll

 ; RUN: llc -O1 -filetype=asm -mtriple x86_64-unknown-linux-gnu -mcpu=x86-64 \
 ; RUN:    -o - %s -stop-after=livedebugvars \
 ; RUN:    -experimental-debug-variable-locations=false \
 ; RUN: | FileCheck %s --check-prefixes=CHECK,VARLOCS
 ; RUN: llc -O1 -filetype=asm -mtriple x86_64-unknown-linux-gnu -mcpu=x86-64 \
 ; RUN:    -o - %s -stop-after=livedebugvars \
 ; RUN:    -experimental-debug-variable-locations=true \
 ; RUN: | FileCheck %s --check-prefixes=CHECK,INSTRREF
 
 ; CHECK:         $eax = MOV32rm
 ; INSTRREF-SAME:      debug-instr-number 1
-; INSTRREF:      DBG_INSTR_REF 1, 0
+; INSTRREF:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
 ; CHECK:         DBG_VALUE $eax
 ; CHECK:         $eax = SHL32rCL killed renamable $eax,
 ; INSTRREF-SAME:      debug-instr-number 2
-; INSTRREF:      DBG_INSTR_REF 2, 0
+; INSTRREF:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
 ; CHECK:         DBG_VALUE $eax
 ; CHECK:         DBG_VALUE $rsp, 0, !{{[0-9]+}}, !DIExpression(DW_OP_constu, 4, DW_OP_minus)
 ; VARLOCS:       DBG_VALUE $eax
 ; CHECK:         $eax = SHL32rCL killed renamable $eax,
 ; INSTRREF-SAME:      debug-instr-number 3
-; INSTRREF:      DBG_INSTR_REF 3, 0
+; INSTRREF:      DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
 ; CHECK:         DBG_VALUE $eax
 ; CHECK:         RET64 $eax
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 @var = local_unnamed_addr global i32 8, !dbg !0
 @sc = local_unnamed_addr global i32 1, !dbg !6

llvm/test/DebugInfo/X86/pr40427.ll

trueb:
   br label %block
 falseb:
   br label %block
 block:
 ; CHECK:      [[PHIREG:%[0-9]+]]:gr64 = PHI %6, %bb.2, %4, %bb.1
 ; CHECK-NEXT: [[LOADR:%[0-9]+]]:gr16 = MOV16rm %0,
 ; INSTRREF-SAME: debug-instr-number 1
 ; DBGVALUE-NEXT: DBG_VALUE [[LOADR]], $noreg, ![[DBGVAR]]
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[DBGVAR]]
+; INSTRREF-NEXT: DBG_INSTR_REF ![[DBGVAR]], {{.+}}, dbg-instr-ref(1, 0)
 ; CHECK-NEXT: %{{[0-9]+}}:gr32 = IMPLICIT_DEF
   %foo = phi ptr[%bees, %trueb], [%more, %falseb]
   %ret = load i32, ptr %foo, !dbg !6
   %cast = trunc i32 %ret to i16, !dbg !6
   call void @llvm.dbg.value(metadata i16 %cast, metadata !1, metadata !DIExpression()), !dbg !6
   %orly2 = add i16 %yellow, 1
   br label %bb1
 bb1:

llvm/test/DebugInfo/X86/sdag-dangling-dbgvalue.ll

 @S = global %struct.SS { i32 23, i32 -17 }, align 4, !dbg !0
 
 ; Verify that the def comes before the for foo1.
 define i32 @test1() local_unnamed_addr #0 !dbg !17 {
 ; CHECK-LABEL: bb.0.entry1
 ; CHECK-NEXT:    DBG_VALUE 0, $noreg, ![[BAR1]], !DIExpression()
 ; CHECK-NEXT:    [[REG1:%[0-9]+]]:gr64 = LEA64r 
 ; INSTRREF-SAME:    debug-instr-number 1
-; INSTRREF-NEXT:  DBG_INSTR_REF 1, 0, ![[FOO1]], !DIExpression()
+; INSTRREF-NEXT:  DBG_INSTR_REF ![[FOO1]], !DIExpression(), dbg-instr-ref(1, 0)
 ; DBGVALUE-NEXT:  DBG_VALUE [[REG1]], $noreg, ![[FOO1]], !DIExpression()
 entry1:
   call void @llvm.dbg.value(metadata ptr @S, metadata !20, metadata !DIExpression()), !dbg !23
   call void @llvm.dbg.value(metadata ptr null, metadata !22, metadata !DIExpression()), !dbg !24
   ret i32 ptrtoint (ptr @S to i32), !dbg !25
 }
 
 ; Verify that the def comes before the for foo2 and bar2.
 define i32 @test2() local_unnamed_addr #0 !dbg !26 {
 ; CHECK-LABEL: bb.0.entry2
 ; CHECK-NEXT:    [[REG2:%[0-9]+]]:gr64 = LEA64r
 ; INSTRREF-SAME:    debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[FOO2]], !DIExpression()
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[BAR2]], !DIExpression()
+; INSTRREF-NEXT: DBG_INSTR_REF ![[FOO2]], !DIExpression(), dbg-instr-ref(1, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF ![[BAR2]], !DIExpression(), dbg-instr-ref(1, 0)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, ![[FOO2]], !DIExpression
 ; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, ![[BAR2]], !DIExpression
 entry2:
   call void @llvm.dbg.value(metadata ptr @S, metadata !28, metadata !DIExpression()), !dbg !30
   call void @llvm.dbg.value(metadata ptr @S, metadata !29, metadata !DIExpression()), !dbg !31
   ret i32 add (i32 ptrtoint (ptr @S to i32), i32 ptrtoint (ptr @S to i32)), !dbg !32
 }
 
 ; Verify that the def comes before the for foo3 and bar3.
 define i32 @test3() local_unnamed_addr #0 !dbg !33 {
 ; CHECK-LABEL: bb.0.entry3
 ; CHECK-NEXT:    [[REG3:%[0-9]+]]:gr64 = LEA64r
 ; INSTRREF-SAME:    debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[BAR3]], !DIExpression()
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[FOO3]], !DIExpression()
+; INSTRREF-NEXT: DBG_INSTR_REF ![[BAR3]], !DIExpression(), dbg-instr-ref(1, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF ![[FOO3]], !DIExpression(), dbg-instr-ref(1, 0)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, ![[BAR3]], !DIExpression()
 ; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, ![[FOO3]], !DIExpression()
 entry3:
   call void @llvm.dbg.value(metadata ptr @S, metadata !36, metadata !DIExpression()), !dbg !38
   call void @llvm.dbg.value(metadata ptr @S, metadata !35, metadata !DIExpression()), !dbg !37
   ret i32 add (i32 ptrtoint (ptr @S to i32), i32 ptrtoint (ptr @S to i32)), !dbg !39
 }
 
 ; Verify that the def comes before the for bar4.
 define i32 @test4() local_unnamed_addr #0 !dbg !40 {
 ; CHECK-LABEL: bb.0.entry4
 ; CHECK-NEXT:    DBG_VALUE $noreg, $noreg, ![[FOO4]], !DIExpression()
 ; CHECK-NEXT:    DBG_VALUE 0, $noreg, ![[FOO4]], !DIExpression()
 ; CHECK-NEXT:    [[REG4:%[0-9]+]]:gr64 = LEA64r
 ; INSTRREF-SAME:    debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[BAR4]], !DIExpression()
+; INSTRREF-NEXT: DBG_INSTR_REF ![[BAR4]], !DIExpression(), dbg-instr-ref(1, 0)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG4]], $noreg, ![[BAR4]], !DIExpression()
 entry4:
   call void @llvm.dbg.value(metadata ptr @S, metadata !42, metadata !DIExpression()), !dbg !44
   call void @llvm.dbg.value(metadata ptr @S, metadata !43, metadata !DIExpression()), !dbg !45
   call void @llvm.dbg.value(metadata ptr null, metadata !42, metadata !DIExpression()), !dbg !44
   ret i32 ptrtoint (ptr @S to i32), !dbg !46
 }
 
 ; Verify that we do not get a DBG_VALUE that maps foo5 to @S here.
 define i32 @test5() local_unnamed_addr #0 !dbg !47 {
 ; CHECK-LABEL: bb.0.entry5:
 ; CHECK-NEXT:    DBG_VALUE $noreg, $noreg, ![[FOO5]], !DIExpression()
 ; CHECK-NEXT:    DBG_VALUE 0, $noreg, ![[FOO5]], !DIExpression()
 ; CHECK-NEXT:    [[REG5:%[0-9]+]]:gr64 = LEA64r
 ; INSTRREF-SAME:    debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[BAR5]], !DIExpression()
+; INSTRREF-NEXT: DBG_INSTR_REF ![[BAR5]], !DIExpression(), dbg-instr-ref(1, 0)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG5]], $noreg, ![[BAR5]], !DIExpression()
 ; CHECK-NOT:     DBG_{{.*}} ![[FOO5]], !DIExpression()
 ; CHECK:         RET
 entry5:
   call void @llvm.dbg.value(metadata ptr @S, metadata !49, metadata !DIExpression()), !dbg !51
   call void @llvm.dbg.value(metadata ptr @S, metadata !50, metadata !DIExpression()), !dbg !52
   call void @llvm.dbg.value(metadata ptr null, metadata !50, metadata !DIExpression()), !dbg !52
   ret i32 ptrtoint (ptr @S to i32), !dbg !53

llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-1.ll

 for.body.lr.ph:                                   ; preds = %entry
   %1 = load i32, ptr @end, align 4, !tbaa !31
   br label %for.body, !dbg !36
 
 for.cond.cleanup:                                 ; preds = %for.body, %entry
 ; CHECK-LABEL: bb.{{.*}}.for.cond.cleanup:
 ; CHECK:         [[REG1:%[0-9]+]]:gr32 = PHI
 ; INSTRREF-SAME:    debug-instr-number 7
-; INSTRREF-NEXT: DBG_INSTR_REF 7, 0
+; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(7, 0)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG1]]
   %x.0.lcssa = phi i32 [ 9, %entry ], [ %add, %for.body ]
   call void @llvm.dbg.value(metadata i32 %x.0.lcssa, metadata !15, metadata !DIExpression()), !dbg !26
   call void @llvm.lifetime.start.p0(i64 320, ptr nonnull %arr) #3, !dbg !37
   call void @llvm.dbg.declare(metadata ptr %arr, metadata !19, metadata !DIExpression()), !dbg !38
   call void @llvm.dbg.value(metadata i32 0, metadata !24, metadata !DIExpression()), !dbg !39
   br label %for.body4, !dbg !40
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
 ; CHECK-LABEL: bb.{{.*}}.for.body:
 ; CHECK:        [[REG2:%[0-9]+]]:gr32 = PHI
 ; INSTRREF-SAME:   debug-instr-number 3
 ; CHECK-NEXT:   [[REG3:%[0-9]+]]:gr32 = PHI
 ; INSTRREF-SAME:   debug-instr-number 4
 ; CHECK-NEXT:   [[REG4:%[0-9]+]]:gr32 = PHI
 ; INSTRREF-SAME:   debug-instr-number 5
-; INSTRREF-NEXT: DBG_INSTR_REF 3, 0
-; INSTRREF-NEXT: DBG_INSTR_REF 4, 0
-; INSTRREF-NEXT: DBG_INSTR_REF 5, 0
+; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(5, 0)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG2]]
 ; DBGVALUE-NEXT: DBG_VALUE [[REG3]]
 ; DBGVALUE-NEXT: DBG_VALUE [[REG4]]
   %u.023 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
   %y.022 = phi i32 [ 13, %for.body.lr.ph ], [ %mul, %for.body ]
   %x.021 = phi i32 [ 9, %for.body.lr.ph ], [ %add, %for.body ]
   call void @llvm.dbg.value(metadata i32 %u.023, metadata !17, metadata !DIExpression()), !dbg !28
   call void @llvm.dbg.value(metadata i32 %y.022, metadata !16, metadata !DIExpression()), !dbg !27

llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-2.ll

 for.body.lr.ph:                                   ; preds = %entry
   %1 = load i32, ptr @end, align 4, !tbaa !31
   br label %for.body, !dbg !36
 
 for.cond.cleanup:                                 ; preds = %for.body, %entry
 ; CHECK-LABEL: bb.{{.*}}.for.cond.cleanup:
 ; CHECK:         [[REG1:%[0-9]+]]:gr32 = PHI
 ; INSTRREF-SAME:      debug-instr-number 7
-; INSTRREF-NEXT: DBG_INSTR_REF 7, 0
+; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(7, 0)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG1]]
   %x.0.lcssa = phi i32 [ 9, %entry ], [ %add, %for.body ]
   call void @llvm.dbg.value(metadata i32 %x.0.lcssa, metadata !15, metadata !DIExpression()), !dbg !26
   call void @llvm.lifetime.start.p0(i64 320, ptr nonnull %arr) #3, !dbg !37
   call void @llvm.dbg.declare(metadata ptr %arr, metadata !19, metadata !DIExpression()), !dbg !38
   call void @llvm.dbg.value(metadata i32 0, metadata !24, metadata !DIExpression()), !dbg !39
   br label %for.body4, !dbg !40
 
 for.body:                                         ; preds = %for.body.lr.ph, %for.body
 ; CHECK-LABEL: bb.{{.*}}.for.body:
 ; CHECK:         [[REG2:%[0-9]+]]:gr32 = PHI
 ; INSTRREF-SAME:    debug-instr-number 4
 ; CHECK-NEXT:    [[REG3:%[0-9]+]]:gr32 = PHI
 ; INSTRREF-SAME:    debug-instr-number 3
 ; CHECK-NEXT:    [[REG4:%[0-9]+]]:gr32 = PHI
 ; INSTRREF-SAME:    debug-instr-number 6
-; INSTRREF-NEXT: DBG_INSTR_REF 3, 0, !16
+; INSTRREF-NEXT: DBG_INSTR_REF !16, {{.+}}, dbg-instr-ref(3, 0)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, !16
 ; CHECK-NEXT:    DBG_VALUE 555, $noreg, !17
 ; CHECK-NEXT:    [[ADDREG:%[0-9]+]]:gr32 = nuw nsw ADD32rr
 ; INSTRREF-SAME:    debug-instr-number 5
-; INSTRREF-NEXT: DBG_INSTR_REF 4, 0, !17
+; INSTRREF-NEXT: DBG_INSTR_REF !17, {{.+}}, dbg-instr-ref(4, 0)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, !17
 ; CHECK:         [[MULREG:%[0-9]+]]:gr32 = LEA64_32r
 ; INSTRREF-SAME:    debug-instr-number 1
 ; CHECK-NEXT:    DBG_VALUE 777, $noreg, !17
 ;;; XXX: The following DBG_INSTR_REF should have stayed below the INC32r
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, !16
+; INSTRREF-NEXT: DBG_INSTR_REF !16, {{.+}}, dbg-instr-ref(1, 0)
 ; DBGVALUE-NEXT: DBG_VALUE [[MULREG]], $noreg, !16
 ; CHECK-NEXT:    [[INCREG:%[0-9]+]]:gr32 = nuw nsw INC32r
 ; INSTRREF-SAME:    debug-instr-number 2
-; INSTRREF-NEXT: DBG_INSTR_REF 2, 0, !17
-; INSTRREF-NEXT: DBG_INSTR_REF 5, 0, !15
+; INSTRREF-NEXT: DBG_INSTR_REF !17, {{.+}}, dbg-instr-ref(2, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF !15, {{.+}}, dbg-instr-ref(5, 0)
 ; DBGVALUE-NEXT: DBG_VALUE [[INCREG]], $noreg, !17
 ; DBGVALUE-NEXT: DBG_VALUE [[ADDREG]], $noreg, !15
 ; CHECK-NEXT:    implicit-def $eflags,
-; INSTRREF-NEXT: DBG_INSTR_REF 6, 0
+; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(6, 0)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG4]]
   %u.023 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
   %y.022 = phi i32 [ 13, %for.body.lr.ph ], [ %mul, %for.body ]
   %x.021 = phi i32 [ 9, %for.body.lr.ph ], [ %add, %for.body ]
   call void @llvm.dbg.value(metadata i32 %y.022, metadata !16, metadata !DIExpression()), !dbg !27
   ; This dbg.value has been manually added compared to dbg_value_phi_isel1.ll
   call void @llvm.dbg.value(metadata i32 555, metadata !17, metadata !DIExpression()), !dbg !28
   %add = add nuw nsw i32 %y.022, %x.021, !dbg !41

llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-3.ll

 ; CHECK-NEXT:    [[REG4:%[0-9]+]]:gr32 = PHI
 ; INSTRREF-SAME:    debug-instr-number 7
 ; CHECK-NEXT:    [[REG5:%[0-9]+]]:gr32_nosp = PHI
 ; INSTRREF-SAME:    debug-instr-number 8
 ; CHECK-NEXT:    [[REG6:%[0-9]+]]:gr32 = PHI
 ; INSTRREF-SAME:    debug-instr-number 9
 ; CHECK-NEXT:    [[REG7:%[0-9]+]]:gr32 = PHI
 ; INSTRREF-SAME:    debug-instr-number 10
-; INSTRREF-NEXT: DBG_INSTR_REF 5, 0, !19, !DIExpression(DW_OP_LLVM_fragment, 0, 32)
-; INSTRREF-NEXT: DBG_INSTR_REF 6, 0, !19, !DIExpression(DW_OP_LLVM_fragment, 32, 32)
-; INSTRREF-NEXT: DBG_INSTR_REF 7, 0, !18, !DIExpression(DW_OP_LLVM_fragment, 0, 32)
-; INSTRREF-NEXT: DBG_INSTR_REF 8, 0, !18, !DIExpression(DW_OP_LLVM_fragment, 32, 32)
-; INSTRREF-NEXT: DBG_INSTR_REF 9, 0, !17, !DIExpression(DW_OP_LLVM_fragment, 0, 32)
-; INSTRREF-NEXT: DBG_INSTR_REF 10, 0, !17, !DIExpression(DW_OP_LLVM_fragment, 32, 32)
+; INSTRREF-NEXT: DBG_INSTR_REF !19, !DIExpression(DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(5, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF !19, !DIExpression(DW_OP_LLVM_fragment, 32, 32), dbg-instr-ref(6, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF !18, !DIExpression(DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(7, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF !18, !DIExpression(DW_OP_LLVM_fragment, 32, 32), dbg-instr-ref(8, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF !17, !DIExpression(DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(9, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF !17, !DIExpression(DW_OP_LLVM_fragment, 32, 32), dbg-instr-ref(10, 0)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, !19, !DIExpression(DW_OP_LLVM_fragment, 0, 32)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, !19, !DIExpression(DW_OP_LLVM_fragment, 32, 32)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG4]], $noreg, !18, !DIExpression(DW_OP_LLVM_fragment, 0, 32)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG5]], $noreg, !18, !DIExpression(DW_OP_LLVM_fragment, 32, 32)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG6]], $noreg, !17, !DIExpression(DW_OP_LLVM_fragment, 0, 32)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG7]], $noreg, !17, !DIExpression(DW_OP_LLVM_fragment, 32, 32)
   %u.023 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
   %y.022 = phi i64 [ 13, %for.body.lr.ph ], [ %mul, %for.body ]

llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-4.ll

 
 ; CHECK-LABEL: bb.{{.*}}.if.end36:
 ; CHECK:         [[REG1:%[0-9]+]]:gr32 = PHI
 ; INSTRREF-SAME:    debug-instr-number 1
 ; CHECK-NEXT:    [[REG2:%[0-9]+]]:gr32 = PHI
 ; INSTRREF-SAME:    debug-instr-number 2
 ; CHECK-NEXT:    [[REG3:%[0-9]+]]:gr32 = PHI
 ; INSTRREF-SAME:    debug-instr-number 3
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, !13, !DIExpression(DW_OP_LLVM_fragment, 0, 32)
-; INSTRREF-NEXT: DBG_INSTR_REF 2, 0, !13, !DIExpression(DW_OP_LLVM_fragment, 32, 32)
-; INSTRREF-NEXT: DBG_INSTR_REF 3, 0, !13, !DIExpression(DW_OP_LLVM_fragment, 64, 16)
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, !12, !DIExpression(DW_OP_LLVM_fragment, 10, 32)
-; INSTRREF-NEXT: DBG_INSTR_REF 2, 0, !12, !DIExpression(DW_OP_LLVM_fragment, 42, 13)
+; INSTRREF-NEXT: DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(1, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_fragment, 32, 32), dbg-instr-ref(2, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_fragment, 64, 16), dbg-instr-ref(3, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_fragment, 10, 32), dbg-instr-ref(1, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_fragment, 42, 13), dbg-instr-ref(2, 0)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG1]], $noreg,  !13, !DIExpression(DW_OP_LLVM_fragment, 0, 32)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg,  !13, !DIExpression(DW_OP_LLVM_fragment, 32, 32)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg,  !13, !DIExpression(DW_OP_LLVM_fragment, 64, 16)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG1]], $noreg,  !12, !DIExpression(DW_OP_LLVM_fragment, 10, 32)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg,  !12, !DIExpression(DW_OP_LLVM_fragment, 42, 13)
 ; CHECK-NOT:  DBG_
 
 target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"

llvm/test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll

; INSTRREF: ADD32ri8 {{.*}} debug-instr-number 1
   %cmp = icmp eq i32 %1, 0
   br i1 %cmp, label %nextbb, label %exit, !dbg !26
 
 nextbb:
 ; CHECK-LABEL: bb.{{.*}}.nextbb
   %2 = mul i32 %0, %arg1, !dbg !26
 ; CHECK: IMUL32rr
   call void @llvm.dbg.value(metadata i32 %1, metadata !16, metadata !DIExpression()), !dbg !27
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0
+; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
 ; DBGVALUE-NEXT: DBG_VALUE
   br label %exit, !dbg !26
 
 ; CHECK-LABEL: bb.{{.*}}.exit
 exit:
   %3 = phi i32 [ 12, %entry ], [ %2, %nextbb ], !dbg !26
   %4 = add i32 %1, %3, !dbg !26
   ret i32 %4, !dbg !26

llvm/test/DebugInfo/X86/sdag-ir-salvage.ll

 ; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare \
 ; RUN:    -stop-before finalize-isel %s -o -  \
 ; RUN:    -experimental-debug-variable-locations=false \
 ; RUN: | FileCheck %s --check-prefixes=CHECK,DBGVALUE
 ; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare \
 ; RUN:    -stop-before finalize-isel %s -o -  \
 ; RUN:    -experimental-debug-variable-locations=true \
 ; RUN: | FileCheck %s --check-prefixes=CHECK,INSTRREF
 
 ; Test that the dbg.value for %baz, which doesn't exist in the 'next' bb,
 ; can be salvaged back to the underlying argument vreg.
 
 ; CHECK:       ![[AAAVAR:.*]] = !DILocalVariable(name: "aaa",
 ; CHECK-LABEL: bb.0.entry:
 ; INSTRREF:    DBG_PHI $rdi, 1
 ; CHECK-LABEL: bb.1.next:
-; INSTRREF:    DBG_INSTR_REF 1, 0, ![[AAAVAR]]
+; INSTRREF:    DBG_INSTR_REF ![[AAAVAR]], {{.+}}, dbg-instr-ref(1, 0)
 ; DBGVALUE:    DBG_VALUE %{{[0-9]+}}, $noreg, ![[AAAVAR]]
 
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-linux-gnu"
 
 define i8 @f(ptr %foo) local_unnamed_addr !dbg !6 {
 entry:
   %bar = getelementptr i32, ptr %foo, i32 4

llvm/test/DebugInfo/X86/sdag-salvage-add.ll

 ;
 ; NB: instruction referencing and DBG_VALUE modes produce debug insts in a
 ; different order.
 ;
 ; CHECK:         ![[S4:.*]] = !DILocalVariable(name: "s4", 
 ; CHECK:         ![[MYVAR:.*]] = !DILocalVariable(name: "myVar", 
 ; CHECK:         $rax = MOV64rm
 ; INSTRREF-SAME: debug-instr-number 2,
-; INSTRREF-NEXT: DBG_INSTR_REF 2, 0, ![[S4]],
+; INSTRREF-NEXT: DBG_INSTR_REF ![[S4]],
 ; DBGVALUE-NEXT: DBG_VALUE $rax, $noreg, ![[MYVAR]],
 ; CHECK-SAME:       !DIExpression(DW_OP_plus_uconst, 4096, DW_OP_stack_value)
+; INSTRREF-SAME: dbg-instr-ref(2, 0)
 
-; INSTRREF:      DBG_INSTR_REF 2, 0, ![[MYVAR]],
+; INSTRREF:      DBG_INSTR_REF ![[MYVAR]],
 ; DBGVALUE:      DBG_VALUE $rax, $noreg, ![[S4]],
 ; CHECK-SAME:           !DIExpression(DW_OP_plus_uconst, 4096, DW_OP_stack_value)
+; INSTRREF-SAME: dbg-instr-ref(2, 0)
 ; CHECK-NEXT: $rdi = MOV64rm killed renamable $rax, 1, $noreg, 4096, $noreg,
 
 source_filename = "test.c"
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.13.0"
 
 %struct.S3 = type { i64 }
 %struct.S4 = type opaque

llvm/test/DebugInfo/X86/sdag-transfer-dbgvalue.ll

 ; }
 
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 ; CHECK-LABEL: bb.0.entry:
 ; CHECK:         %[[REG:[0-9]+]]:gr32 = ADD32ri %1, 512,
 ; INSTRREF-SAME:   debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0
+; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
 ; DBGVALUE-NEXT: DBG_VALUE %[[REG]]
 
 ; Function Attrs: nofree norecurse nounwind uwtable writeonly
 define dso_local i32 @foo(i32 %a, ptr nocapture %b) local_unnamed_addr !dbg !7 {
 entry:
   %add = add nsw i32 %a, 512, !dbg !18
   call void @llvm.dbg.value(metadata i32 %add, metadata !16, metadata !DIExpression()), !dbg !17
   %cmp = icmp eq i32 %add, 0, !dbg !18

llvm/test/DebugInfo/assignment-tracking/X86/loop-sink.ll

 
 ; CHECK-DAG: ![[A:[0-9]+]] = !DILocalVariable(name: "a",
 
 ; CHECK-LABEL: bb.0.entry:
 ; CHECK: DBG_VALUE $edi, $noreg, ![[A]], !DIExpression()
 ; CHECK: CALL64pcrel32 @getInt{{.*}}debug-instr-number 1
 
 ; CHECK-LABEL: bb.2.while.body:
-; CHECK: DBG_INSTR_REF 1, 6, ![[A]], !DIExpression()
+; CHECK: DBG_INSTR_REF ![[A]], !DIExpression(), dbg-instr-ref(1, 6)
 
 ; CHECK-LABEL: bb.3.while.end:
 ; CHECK: MOV32mr %stack.0.a.addr, 1, $noreg, 0, $noreg, %1
 ; CHECK-NEXT: DBG_VALUE %stack.0.a.addr, $noreg, ![[A]], !DIExpression(DW_OP_deref)
 
 target triple = "x86_64-unknown-linux-gnu"
 
 @g = dso_local local_unnamed_addr global ptr null, align 8, !dbg !0

llvm/test/DebugInfo/assignment-tracking/X86/lower-to-value.ll

 ; CHECK-NEXT: DBG_VALUE %stack.0.X, $noreg, ![[VAR]], !DIExpression(DW_OP_deref, DW_OP_LLVM_fragment, 0, 64)
 ; CHECK-NEXT: DBG_VALUE %stack.0.X, $noreg, ![[VAR]], !DIExpression(DW_OP_plus_uconst, 8, DW_OP_deref, DW_OP_LLVM_fragment, 64, 64), debug-location
 
 ;; The final assignment (X.B += 2) doesn't get stored back to the alloca. This
 ;; means that that the stack location isn't valid for the entire lifetime of X.
 ; DBGVALUE: %2:gr64 = nsw ADD64ri8 %1, 2, implicit-def dead $eflags, debug-location
 ; DBGVALUE-NEXT: DBG_VALUE %2, $noreg, ![[VAR]], !DIExpression(DW_OP_LLVM_fragment, 64, 64), debug-location
 ; INSTRREF: %2:gr64 = nsw ADD64ri8 %1, 2, implicit-def dead $eflags, debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[VAR]], !DIExpression(DW_OP_LLVM_fragment, 64, 64), debug-location
+; INSTRREF-NEXT: DBG_INSTR_REF ![[VAR]], !DIExpression(DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(1, 0), debug-location
 
 source_filename = "test.cpp"
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 %struct.Ex = type { i64, i64 }
 
 define dso_local i64 @_Z3funv() local_unnamed_addr !dbg !7 {

llvm/test/DebugInfo/assignment-tracking/X86/sdag-dangling-dbgassign.ll

 @S = global %struct.SS { i32 23, i32 -17 }, align 4, !dbg !0
 
 ; Verify that the def comes before the for foo1.
 define i32 @test1() local_unnamed_addr #0 !dbg !17 {
 ; CHECK-LABEL: bb.0.entry1
 ; CHECK-NEXT:    DBG_VALUE 0, $noreg, ![[BAR1]], !DIExpression()
 ; CHECK-NEXT:    [[REG1:%[0-9]+]]:gr64 = LEA64r
 ; INSTRREF-SAME:    debug-instr-number 1
-; INSTRREF-NEXT:  DBG_INSTR_REF 1, 0, ![[FOO1]], !DIExpression()
+; INSTRREF-NEXT:  DBG_INSTR_REF ![[FOO1]], !DIExpression(), dbg-instr-ref(1, 0)
 ; DBGVALUE-NEXT:  DBG_VALUE [[REG1]], $noreg, ![[FOO1]], !DIExpression()
 entry1:
   call void @llvm.dbg.assign(metadata ptr @S, metadata !20, metadata !DIExpression(), metadata !54, metadata ptr undef, metadata !DIExpression()), !dbg !23
   call void @llvm.dbg.assign(metadata ptr null, metadata !22, metadata !DIExpression(), metadata !54, metadata ptr undef, metadata !DIExpression()), !dbg !24
   ret i32 ptrtoint (ptr @S to i32), !dbg !25
 }
 
 ; Verify that the def comes before the for foo2 and bar2.
 define i32 @test2() local_unnamed_addr #0 !dbg !26 {
 ; CHECK-LABEL: bb.0.entry2
 ; CHECK-NEXT:    [[REG2:%[0-9]+]]:gr64 = LEA64r
 ; INSTRREF-SAME:    debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[FOO2]], !DIExpression()
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[BAR2]], !DIExpression()
+; INSTRREF-NEXT: DBG_INSTR_REF ![[FOO2]], !DIExpression(), dbg-instr-ref(1, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF ![[BAR2]], !DIExpression(), dbg-instr-ref(1, 0)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, ![[FOO2]], !DIExpression
 ; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, ![[BAR2]], !DIExpression
 entry2:
   call void @llvm.dbg.assign(metadata ptr @S, metadata !28, metadata !DIExpression(), metadata !54, metadata ptr undef, metadata !DIExpression()), !dbg !30
   call void @llvm.dbg.assign(metadata ptr @S, metadata !29, metadata !DIExpression(), metadata !54, metadata ptr undef, metadata !DIExpression()), !dbg !31
   ret i32 add (i32 ptrtoint (ptr @S to i32), i32 ptrtoint (ptr @S to i32)), !dbg !32
 }
 
 ; Verify that the def comes before the for foo3 and bar3.
 define i32 @test3() local_unnamed_addr #0 !dbg !33 {
 ; CHECK-LABEL: bb.0.entry3
 ; CHECK-NEXT:    [[REG3:%[0-9]+]]:gr64 = LEA64r
 ; INSTRREF-SAME:    debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[BAR3]], !DIExpression()
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[FOO3]], !DIExpression()
+; INSTRREF-NEXT: DBG_INSTR_REF ![[BAR3]], !DIExpression(), dbg-instr-ref(1, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF ![[FOO3]], !DIExpression(), dbg-instr-ref(1, 0)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, ![[BAR3]], !DIExpression()
 ; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, ![[FOO3]], !DIExpression()
 entry3:
   call void @llvm.dbg.assign(metadata ptr @S, metadata !36, metadata !DIExpression(), metadata !54, metadata ptr undef, metadata !DIExpression()), !dbg !38
   call void @llvm.dbg.assign(metadata ptr @S, metadata !35, metadata !DIExpression(), metadata !54, metadata ptr undef, metadata !DIExpression()), !dbg !37
   ret i32 add (i32 ptrtoint (ptr @S to i32), i32 ptrtoint (ptr @S to i32)), !dbg !39
 }
 
 ; Verify that the def comes before the for bar4.
 define i32 @test4() local_unnamed_addr #0 !dbg !40 {
 ; CHECK-LABEL: bb.0.entry4
 ;; NOTE: The check for `DBG_VALUE $noreg, $noreg, ![[FOO4]], !DIExpression()`
 ;; has been removed because AT lowering removes redundant debug intrinsics.
 ; CHECK-NEXT:    DBG_VALUE 0, $noreg, ![[FOO4]], !DIExpression()
 ; CHECK-NEXT:    [[REG4:%[0-9]+]]:gr64 = LEA64r
 ; INSTRREF-SAME:    debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[BAR4]], !DIExpression()
+; INSTRREF-NEXT: DBG_INSTR_REF ![[BAR4]], !DIExpression(), dbg-instr-ref(1, 0)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG4]], $noreg, ![[BAR4]], !DIExpression()
 entry4:
   call void @llvm.dbg.assign(metadata ptr @S, metadata !42, metadata !DIExpression(), metadata !54, metadata ptr undef, metadata !DIExpression()), !dbg !44
   call void @llvm.dbg.assign(metadata ptr @S, metadata !43, metadata !DIExpression(), metadata !54, metadata ptr undef, metadata !DIExpression()), !dbg !45
   call void @llvm.dbg.assign(metadata ptr null, metadata !42, metadata !DIExpression(), metadata !54, metadata ptr undef, metadata !DIExpression()), !dbg !44
   ret i32 ptrtoint (ptr @S to i32), !dbg !46
 }
 
 ; Verify that we do not get a DBG_VALUE that maps foo5 to @S here.
 define i32 @test5() local_unnamed_addr #0 !dbg !47 {
 ; CHECK-LABEL: bb.0.entry5:
 ; cHECK-NEXT:    DBG_VALUE $noreg, $noreg, ![[FOO5]], !DIExpression()
 ; CHECK-NEXT:    DBG_VALUE 0, $noreg, ![[FOO5]], !DIExpression()
 ; CHECK-NEXT:    [[REG5:%[0-9]+]]:gr64 = LEA64r
 ; INSTRREF-SAME:    debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[BAR5]], !DIExpression()
+; INSTRREF-NEXT: DBG_INSTR_REF ![[BAR5]], !DIExpression(), dbg-instr-ref(1, 0)
 ; DBGVALUE-NEXT: DBG_VALUE [[REG5]], $noreg, ![[BAR5]], !DIExpression()
 ; CHECK-NOT:     DBG_{{.*}} ![[FOO5]], !DIExpression()
 ; CHECK:         RET
 entry5:
   call void @llvm.dbg.assign(metadata ptr @S, metadata !49, metadata !DIExpression(), metadata !54, metadata ptr undef, metadata !DIExpression()), !dbg !51
   call void @llvm.dbg.assign(metadata ptr @S, metadata !50, metadata !DIExpression(), metadata !54, metadata ptr undef, metadata !DIExpression()), !dbg !52
   call void @llvm.dbg.assign(metadata ptr null, metadata !50, metadata !DIExpression(), metadata !54, metadata ptr undef, metadata !DIExpression()), !dbg !52
   ret i32 ptrtoint (ptr @S to i32), !dbg !53

llvm/test/DebugInfo/assignment-tracking/X86/sdag-ir-salvage-assign.ll

 
 ; Test that the dbg.value for %baz, which doesn't exist in the 'next' bb,
 ; can be salvaged back to the underlying argument vreg.
 
 ; CHECK:       ![[AAAVAR:.*]] = !DILocalVariable(name: "aaa",
 ; CHECK-LABEL: bb.0.entry:
 ; INSTRREF:    DBG_PHI $rdi, 1
 ; CHECK-LABEL: bb.1.next:
-; INSTRREF:    DBG_INSTR_REF 1, 0, ![[AAAVAR]]
+; INSTRREF:    DBG_INSTR_REF ![[AAAVAR]], {{.+}}, dbg-instr-ref(1, 0)
 ; DBGVALUE:    DBG_VALUE %{{[0-9]+}}, $noreg, ![[AAAVAR]]
 
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-linux-gnu"
 
 define i8 @f(ptr %foo) local_unnamed_addr !dbg !6 {
 entry:
   %bar = getelementptr i32, ptr %foo, i32 4

llvm/test/DebugInfo/assignment-tracking/X86/sdag-transfer-dbgassign.ll

 
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 ; CHECK-LABEL: bb.0.entry:
 ; DBGVALUE:       %[[REG:[0-9]+]]:gr32 = ADD32ri %1, 512
 ; DBGVALUE-NEXT:  DBG_VALUE %[[REG]]
 ; INSTRREF:       ADD32ri %1, 512, {{.*}}debug-instr-number 1
-; INSTRREF-NEXT:  DBG_INSTR_REF 1, 0
+; INSTRREF-NEXT:  DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
 
 ; Function Attrs: nofree norecurse nounwind uwtable writeonly
 define dso_local i32 @foo(i32 %a, ptr nocapture %b) local_unnamed_addr !dbg !7 {
 entry:
   %add = add nsw i32 %a, 512, !dbg !18
   call void @llvm.dbg.assign(metadata i32 %add, metadata !16, metadata !DIExpression(), metadata !19, metadata ptr undef, metadata !DIExpression()), !dbg !17
   %cmp = icmp eq i32 %add, 0, !dbg !18
   br i1 %cmp, label %if.end, label %if.then, !dbg !18