This is an archive of the discontinued LLVM Phabricator instance.

Differential D133932

[DebugInfo] Update existing tests to match new DBG_INSTR_REF format and behaviour
AbandonedPublic

Authored by StephenTozer on Sep 15 2022, 3:42 AM.

Details

Reviewers
jmorse
Orlando
Summary

This patch consolidates a large number of test changes from changes earlier in the patch stack. The reason for pulling all of them into a single patch, instead of putting them alongside the specific patches, is that a lot of these tests are touched multiple times in the stack and would likely take up a lot more reviewer time than simply looking at the final result. These tests will be squashed into the associated patch(es) when these reviews land.

Diff Detail

Revision Contents

PathSize
llvm/
test/
CodeGen/
X86/
2 lines
4 lines
DebugInfo/
AArch64/
2 lines
ARM/
2 lines
COFF/
2 lines
MIR/
InstrRef/
2 lines
6 lines
6 lines
24 lines
24 lines
24 lines
106 lines
6 lines
48 lines
54 lines
4 lines
48 lines
2 lines
2 lines
2 lines
28 lines
30 lines
2 lines
2 lines
4 lines
4 lines
4 lines
4 lines
12 lines
16 lines
2 lines
4 lines
28 lines
4 lines
20 lines
2 lines
X86/
8 lines
X86/
2 lines
8 lines
4 lines
4 lines
6 lines
6 lines
2 lines
2 lines
2 lines
2 lines
32 lines
6 lines
4 lines
2 lines
18 lines
2 lines
2 lines
14 lines
8 lines
14 lines
12 lines
10 lines
2 lines
2 lines
12 lines
2 lines
4 lines
2 lines

Diff 460352

llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir

Show All 33 Lines
tracksRegLiveness: true tracksRegLiveness: true
debugValueSubstitutions: debugValueSubstitutions:
- { srcinst: 2, srcop: 0, dstinst: 1, dstop: 0, subreg: 2 } - { srcinst: 2, srcop: 0, dstinst: 1, dstop: 0, subreg: 2 }
body: | body: |
bb.0: bb.0:
%0:gr16_abcd = MOV16ri 1, debug-instr-number 1, debug-location !9 %0:gr16_abcd = MOV16ri 1, debug-instr-number 1, debug-location !9
bb.1: bb.1:
DBG_INSTR_REF 2, 0, !7, !DIExpression(), debug-location !9 DBG_INSTR_REF !7, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(2, 0), debug-location !9
%1:gr16 = COPY %0, debug-location !9 %1:gr16 = COPY %0, debug-location !9
%2:gr16 = COPY %0 %2:gr16 = COPY %0
bb.2: bb.2:
$ax = COPY %1, debug-location !9 $ax = COPY %1, debug-location !9
$dx = COPY %2 $dx = COPY %2
RET64 killed $ax, killed $dx, debug-location !9 RET64 killed $ax, killed $dx, debug-location !9
... ...
Show All 17 Lines

llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir

Show First 20 Lines • Show All 292 Lines • ▼ Show 20 Lines bb.0:
DBG_VALUE $rcx, $noreg, !46, !17, debug-location !48 DBG_VALUE $rcx, $noreg, !46, !17, debug-location !48
DBG_VALUE $rcx, $noreg, !39, !17, debug-location !44 DBG_VALUE $rcx, $noreg, !39, !17, debug-location !44
DBG_PHI $rcx, 0 DBG_PHI $rcx, 0
DBG_PHI $rcx, 1 DBG_PHI $rcx, 1
DBG_VALUE $rbp, -20, !29, !17, debug-location !36 DBG_VALUE $rbp, -20, !29, !17, debug-location !36
$rcx = CMOV64rr killed $rcx, killed $rdx, 5, implicit killed $eflags $rcx = CMOV64rr killed $rcx, killed $rdx, 5, implicit killed $eflags
$rcx = OR64rr killed $rcx, killed $rsi, implicit-def dead $eflags $rcx = OR64rr killed $rcx, killed $rsi, implicit-def dead $eflags
$rdx = MOVSX64rm32 $rbx, 1, $noreg, 0, $noreg :: (load (s32), align 8) $rdx = MOVSX64rm32 $rbx, 1, $noreg, 0, $noreg :: (load (s32), align 8)
DBG_INSTR_REF 1, 0, !46, !17, debug-location !48 DBG_INSTR_REF !46, !17, dbg-instr-ref(1, 0), debug-location !48
DBG_INSTR_REF 2, 0, !39, !17, debug-location !44 DBG_INSTR_REF !39, !17, dbg-instr-ref(2, 0), debug-location !44
TEST32mr killed $rcx, 4, killed $rdx, 0, $noreg, killed $eax, implicit-def $eflags :: (load (s32)) TEST32mr killed $rcx, 4, killed $rdx, 0, $noreg, killed $eax, implicit-def $eflags :: (load (s32))
JCC_1 %bb.2, 5, implicit $eflags JCC_1 %bb.2, 5, implicit $eflags
JMP_1 %bb.3 JMP_1 %bb.3
bb.1: bb.1:
successors: %bb.2 successors: %bb.2
liveins: $rbx, $rbp liveins: $rbx, $rbp
Show All 25 Lines

llvm/test/DebugInfo/AArch64/instr-ref-const-physreg.ll

; RUN: llc %s -stop-before=finalize-isel -march=aarch64 -o - \ ; RUN: llc %s -stop-before=finalize-isel -march=aarch64 -o - \
; RUN: -experimental-debug-variable-locations | FileCheck %s ; RUN: -experimental-debug-variable-locations | FileCheck %s
; Test that when an SSA Value becomes a constant-physreg copy, under the ; Test that when an SSA Value becomes a constant-physreg copy, under the
; instruction referencing model, the COPY is labelled. In the general case ; instruction referencing model, the COPY is labelled. In the general case
; labelling a copy is undesirable -- this test really checks that we don't ; labelling a copy is undesirable -- this test really checks that we don't
; crash, and we don't just drop the information. ; crash, and we don't just drop the information.
; CHECK: DBG_PHI $xzr, 1 ; CHECK: DBG_PHI $xzr, 1
; CHECK: DBG_INSTR_REF 1, 0 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
define i64 @test() !dbg !7 { define i64 @test() !dbg !7 {
%foo = add i64 0, 0 %foo = add i64 0, 0
call void @llvm.dbg.value(metadata i64 %foo, metadata !12, metadata !DIExpression()), !dbg !13 call void @llvm.dbg.value(metadata i64 %foo, metadata !12, metadata !DIExpression()), !dbg !13
ret i64 %foo, !dbg !13 ret i64 %foo, !dbg !13
} }
declare void @llvm.dbg.value(metadata, metadata, metadata) declare void @llvm.dbg.value(metadata, metadata, metadata)
Show All 20 Lines

llvm/test/DebugInfo/ARM/instr-ref-tcreturn.ll

Show All 19 Lines
; CHECK: LOAD_STACK_GUARD ; CHECK: LOAD_STACK_GUARD
; CHECK-LABEL: bb.2.entry: ; CHECK-LABEL: bb.2.entry:
; CHECK: tBL {{.*}} &__stack_chk_fail, ; CHECK: tBL {{.*}} &__stack_chk_fail,
; CHECK-LABEL: bb.1.entry: ; CHECK-LABEL: bb.1.entry:
; CHECK: $r0 = COPY %0 ; CHECK: $r0 = COPY %0
; CHECK-NEXT: $r1 = COPY %1 ; CHECK-NEXT: $r1 = COPY %1
; CHECK-NEXT: DBG_INSTR_REF 1, 0 ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NEXT: TCRETURNdi &__divsi3, 0, csr_ios, implicit $sp, implicit $r0, implicit $r1 ; CHECK-NEXT: TCRETURNdi &__divsi3, 0, csr_ios, implicit $sp, implicit $r0, implicit $r1
declare i1 @ext() declare i1 @ext()
define i32 @test(i32 %a1, i32 %a2) #1 !dbg !5 { define i32 @test(i32 %a1, i32 %a2) #1 !dbg !5 {
entry: entry:
%foo = alloca i32, i32 %a1 %foo = alloca i32, i32 %a1
%bool = call i1 @ext() %bool = call i1 @ext()
Show All 30 Lines

llvm/test/DebugInfo/COFF/pieces.ll

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; ASM: retq ; ASM: retq
; ASM-LABEL: bitpiece_spill: # @bitpiece_spill ; ASM-LABEL: bitpiece_spill: # @bitpiece_spill
; ASM: #DEBUG_VALUE: bitpiece_spill:o <- [DW_OP_LLVM_fragment 0 32] 0 ; ASM: #DEBUG_VALUE: bitpiece_spill:o <- [DW_OP_LLVM_fragment 0 32] 0
; ASM: xorl %ecx, %ecx ; ASM: xorl %ecx, %ecx
; ASM: callq g ; ASM: callq g
; ASM: movl %eax, [[offset_o_x:[0-9]+]](%rsp) # 4-byte Spill ; ASM: movl %eax, [[offset_o_x:[0-9]+]](%rsp) # 4-byte Spill
; ASM: [[spill_o_x_start:\.Ltmp[0-9]+]]: ; ASM: [[spill_o_x_start:\.Ltmp[0-9]+]]:
; ASM: #DEBUG_VALUE: bitpiece_spill:o <- [DW_OP_plus_uconst [[offset_o_x]], DW_OP_LLVM_fragment 32 32] [$rsp+0] ; ASM: #DEBUG_VALUE: bitpiece_spill:o <- [DW_OP_plus_uconst [[offset_o_x]], DW_OP_deref, DW_OP_LLVM_fragment 32 32] $rsp
; ASM: #APP ; ASM: #APP
; ASM: #NO_APP ; ASM: #NO_APP
; ASM: movl [[offset_o_x]](%rsp), %eax # 4-byte Reload ; ASM: movl [[offset_o_x]](%rsp), %eax # 4-byte Reload
; ASM: retq ; ASM: retq
; ASM: [[spill_o_x_end_func:\.Ltmp[0-9]+]]: ; ASM: [[spill_o_x_end_func:\.Ltmp[0-9]+]]:
; ASM-NEXT: .Lfunc_end4: ; ASM-NEXT: .Lfunc_end4:
▲ Show 20 Lines • Show All 338 Lines • Show Last 20 Lines

llvm/test/DebugInfo/MIR/InstrRef/accept-nonlive-reg-phis.mir

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
tracksDebugUserValues: true tracksDebugUserValues: true
frameInfo: frameInfo:
maxAlignment: 4 maxAlignment: 4
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
bb.0.entry: bb.0.entry:
DBG_PHI $fp0, 3 DBG_PHI $fp0, 3
DBG_INSTR_REF 3, 0, !17, !DIExpression(), debug-location !30 DBG_INSTR_REF !17, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(3, 0), debug-location !30
$eax = MOV32ri 0 $eax = MOV32ri 0
RET 0, debug-location !36 RET 0, debug-location !36
... ...

llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir

# RUN: llc %s -run-pass=livedebugvalues -experimental-debug-variable-locations\ # RUN: llc %s -run-pass=livedebugvalues -experimental-debug-variable-locations\
# RUN: -o - | FileCheck %s # RUN: -o - | FileCheck %s
# #
# In the MIR below, there's an argument in the lowest byte of $edi. The debug # In the MIR below, there's an argument in the lowest byte of $edi. The debug
# intrinsics correctly identify the value and where it becomes the variables # intrinsics correctly identify the value and where it becomes the variables
# value, however a bug in InstrRefBasedLDV meant that not all subregisters of # value, however a bug in InstrRefBasedLDV meant that not all subregisters of
# DBG_PHI operands are tracked. That leads to the wrong DBG_VALUE location # DBG_PHI operands are tracked. That leads to the wrong DBG_VALUE location
# being produced, and a crash under asan. # being produced, and a crash under asan.
# #
# CHECK-LABEL: name: foo # CHECK-LABEL: name: foo
# CHECK: DBG_PHI $edi # CHECK: DBG_PHI $edi
# CHECK-NEXT: DBG_INSTR_REF 2, 0 # CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
# CHECK-NEXT: DBG_VALUE $dil # CHECK-NEXT: DBG_VALUE_LIST {{.+}} $dil
--- | --- |
; ModuleID = 'out.ll' ; ModuleID = 'out.ll'
source_filename = "out.ll" source_filename = "out.ll"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-scei-ps4" target triple = "x86_64-scei-ps4"
@someglobal = external local_unnamed_addr global i8, align 1 @someglobal = external local_unnamed_addr global i8, align 1
Show All 36 Lines
debugValueSubstitutions: debugValueSubstitutions:
- { srcinst: 2, srcop: 0, dstinst: 1, dstop: 0, subreg: 1 } - { srcinst: 2, srcop: 0, dstinst: 1, dstop: 0, subreg: 1 }
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $edi liveins: $edi
DBG_PHI $edi, 1 DBG_PHI $edi, 1
DBG_INSTR_REF 2, 0, !12, !DIExpression(), debug-location !13 DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(2, 0), debug-location !13
renamable $rax = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @someglobal, $noreg, debug-location !13 :: (load (s64) from got) renamable $rax = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @someglobal, $noreg, debug-location !13 :: (load (s64) from got)
MOV8mr killed renamable $rax, 1, $noreg, 0, $noreg, renamable $dil, debug-location !13 :: (store (s8) into @someglobal) MOV8mr killed renamable $rax, 1, $noreg, 0, $noreg, renamable $dil, debug-location !13 :: (store (s8) into @someglobal)
RET64 debug-location !13 RET64 debug-location !13
... ...

llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir

Show First 20 Lines • Show All 128 Lines • ▼ Show 20 Lines bb.1.if.then:
renamable $rbx = ADD64ri32 killed renamable $rbx, 1, implicit-def $eflags, debug-location !21 renamable $rbx = ADD64ri32 killed renamable $rbx, 1, implicit-def $eflags, debug-location !21
bb.2.if.end: bb.2.if.end:
liveins: $rbx, $r14 liveins: $rbx, $r14
DBG_PHI $rbx, 1 DBG_PHI $rbx, 1
$rax = COPY $rbx $rax = COPY $rbx
$rbx = MOV64ri 0 $rbx = MOV64ri 0
DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13 DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !13
; This sequence should mark the contents of rbx on block entry as being the ; This sequence should mark the contents of rbx on block entry as being the
; value for the variable at this DBG_INSTR_REF. We've force it to be in ; value for the variable at this DBG_INSTR_REF. We've force it to be in
; $rax now, so we should see a DBG_VALUE for rax: ; $rax now, so we should see a DBG_VALUE for rax:
; CHECK: DBG_PHI $rbx, 1 ; CHECK: DBG_PHI $rbx, 1
; CHECK-NEXT: $rax = COPY $rbx ; CHECK-NEXT: $rax = COPY $rbx
; CHECK-NEXT: $rbx = MOV64ri 0 ; CHECK-NEXT: $rbx = MOV64ri 0
; CHECK-NEXT: DBG_INSTR_REF 1, 0 ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NEXT: DBG_VALUE $rax, $noreg ; CHECK-NEXT: DBG_VALUE_LIST {{.+}} $rax
$rbx = COPY $rax $rbx = COPY $rax
renamable $rbx = ADD64rr killed renamable $rbx, killed renamable $r14, implicit-def $eflags, debug-location !23 renamable $rbx = ADD64rr killed renamable $rbx, killed renamable $r14, implicit-def $eflags, debug-location !23
DBG_VALUE $rbx, $noreg, !12, !DIExpression(), debug-location !13 DBG_VALUE $rbx, $noreg, !12, !DIExpression(), debug-location !13
$rdi = MOV64rr $rbx, debug-location !24 $rdi = MOV64rr $rbx, debug-location !24
CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !24 CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !24
$eax = MOV32rr $ebx, implicit killed $rbx, debug-location !26 $eax = MOV32rr $ebx, implicit killed $rbx, debug-location !26
$rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !26 $rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !26
CFI_INSTRUCTION def_cfa_offset 24, debug-location !26 CFI_INSTRUCTION def_cfa_offset 24, debug-location !26
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !26 $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !26
CFI_INSTRUCTION def_cfa_offset 16, debug-location !26 CFI_INSTRUCTION def_cfa_offset 16, debug-location !26
$r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !26 $r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !26
CFI_INSTRUCTION def_cfa_offset 8, debug-location !26 CFI_INSTRUCTION def_cfa_offset 8, debug-location !26
RET64 implicit $eax, debug-location !26 RET64 implicit $eax, debug-location !26
... ...

llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv2.mir

Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Lines bb.0:
;; A DBG_PHI of the stack should resolve to the stack location. ;; A DBG_PHI of the stack should resolve to the stack location.
DBG_PHI %stack.0, 1, 64 DBG_PHI %stack.0, 1, 64
;; Reload value, clobber stack location. ;; Reload value, clobber stack location.
$rcx = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0) $rcx = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0)
MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0) MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)
;; This should resolve to the loaded register. ;; This should resolve to the loaded register.
DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13 DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !13
; CHECK: DBG_INSTR_REF 1, 0, ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NEXT: DBG_VALUE $rcx ; CHECK-NEXT: DBG_VALUE_LIST {{.+}} $rcx
;; And if we say it's a smaller size, we should be able to pick out smaller ;; And if we say it's a smaller size, we should be able to pick out smaller
;; subregisters within the stack slot. ;; subregisters within the stack slot.
DBG_PHI %stack.0, 2, 32 DBG_PHI %stack.0, 2, 32
$rax = MOV64ri 0 $rax = MOV64ri 0
$rcx = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0) $rcx = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0)
MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0) MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)
;; This should pick out the 32 bit value. ;; This should pick out the 32 bit value.
DBG_INSTR_REF 2, 0, !12, !DIExpression(), debug-location !13 DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(2, 0), debug-location !13
; CHECK: DBG_INSTR_REF 2, 0, ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
; CHECK-NEXT: DBG_VALUE $ecx ; CHECK-NEXT: DBG_VALUE_LIST {{.+}} $ecx
;; Try all the other subregs. ;; Try all the other subregs.
DBG_PHI %stack.0, 3, 16 DBG_PHI %stack.0, 3, 16
$rax = MOV64ri 0 $rax = MOV64ri 0
$rcx = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0) $rcx = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0)
MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0) MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)
DBG_INSTR_REF 3, 0, !12, !DIExpression(), debug-location !13 DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(3, 0), debug-location !13
; CHECK: DBG_INSTR_REF 3, 0, ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
; CHECK-NEXT: DBG_VALUE $cx ; CHECK-NEXT: DBG_VALUE_LIST {{.+}} $cx
DBG_PHI %stack.0, 4, 8 DBG_PHI %stack.0, 4, 8
$rax = MOV64ri 0 $rax = MOV64ri 0
$rcx = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0) $rcx = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0)
MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0) MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)
DBG_INSTR_REF 4, 0, !12, !DIExpression(), debug-location !13 DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(4, 0), debug-location !13
; CHECK: DBG_INSTR_REF 4, 0, ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
; CHECK-NEXT: DBG_VALUE $cl ; CHECK-NEXT: DBG_VALUE_LIST {{.+}} $cl
;; We can't, at this time, describe subregister fields with nonzero offset. ;; We can't, at this time, describe subregister fields with nonzero offset.
;; It's easily achieved by attaching more data to stack DBG_PHIs, but it's ;; It's easily achieved by attaching more data to stack DBG_PHIs, but it's
;; not clear that LLVM will ever merge registers to generate such locations. ;; not clear that LLVM will ever merge registers to generate such locations.
RET64 implicit $eax, debug-location !26 RET64 implicit $eax, debug-location !26
... ...

llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir

Show First 20 Lines • Show All 152 Lines • ▼ Show 20 Lines bb.1.if.then:
renamable $rbx = ADD64ri32 killed renamable $rbx, 1, implicit-def $eflags, debug-location !22 renamable $rbx = ADD64ri32 killed renamable $rbx, 1, implicit-def $eflags, debug-location !22
DBG_PHI $r14, 1 DBG_PHI $r14, 1
DBG_PHI $rbx, 2 DBG_PHI $rbx, 2
DBG_PHI $rax, 3 DBG_PHI $rax, 3
bb.3.if.end: bb.3.if.end:
liveins: $rbx, $r14 liveins: $rbx, $r14
DBG_INSTR_REF 1, 0, !14, !DIExpression(), debug-location !13 DBG_INSTR_REF !14, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !13
DBG_INSTR_REF 2, 0, !12, !DIExpression(), debug-location !13 DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(2, 0), debug-location !13
DBG_INSTR_REF 3, 0, !12, !DIExpression(), debug-location !13 DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(3, 0), debug-location !13
; Value number 1 is live-through the above control flow from the two ; Value number 1 is live-through the above control flow from the two
; DBG_PHIs: ; DBG_PHIs:
; CHECK: DBG_INSTR_REF 1, 0 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NEXT: DBG_VALUE $r14 ; CHECK-NEXT: DBG_VALUE_LIST {{.+}} $r14
; ;
; While value number 2 has different defs that merge on entry to bb.3. ; While value number 2 has different defs that merge on entry to bb.3.
; These are both in $rbx though, and we should find its location: ; These are both in $rbx though, and we should find its location:
; CHECK: DBG_INSTR_REF 2, 0 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
; CHECK-NEXT: DBG_VALUE $rbx ; CHECK-NEXT: DBG_VALUE_LIST {{.+}} $rbx
; ;
; Value number 3 cannot be resolved because $rax is clobbered in bb.2, ; Value number 3 cannot be resolved because $rax is clobbered in bb.2,
; meaning the merged value in bb.3 is incorrect. It should produce a ; meaning the merged value in bb.3 is incorrect. It should produce a
; DBG_VALUE $noreg. ; DBG_VALUE $noreg.
; CHECK: DBG_INSTR_REF 3, 0 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE_LIST {{.+}} $noreg
renamable $rbx = ADD64rr killed renamable $rbx, killed renamable $r14, implicit-def $eflags, debug-location !28 renamable $rbx = ADD64rr killed renamable $rbx, killed renamable $r14, implicit-def $eflags, debug-location !28
DBG_INSTR_REF 2, 0, !12, !DIExpression(), debug-location !13 DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(2, 0), debug-location !13
; After clobbering rbx, the variable location should not be available. ; After clobbering rbx, the variable location should not be available.
; CHECK: DBG_INSTR_REF 2, 0 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE_LIST {{.+}} $noreg
$rdi = MOV64rr $rbx, debug-location !29 $rdi = MOV64rr $rbx, debug-location !29
CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !29 CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !29
$eax = MOV32rr $ebx, implicit killed $rbx, debug-location !31 $eax = MOV32rr $ebx, implicit killed $rbx, debug-location !31
$rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !31 $rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !31
CFI_INSTRUCTION def_cfa_offset 24, debug-location !31 CFI_INSTRUCTION def_cfa_offset 24, debug-location !31
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !31 $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !31
CFI_INSTRUCTION def_cfa_offset 16, debug-location !31 CFI_INSTRUCTION def_cfa_offset 16, debug-location !31
$r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !31 $r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !31
CFI_INSTRUCTION def_cfa_offset 8, debug-location !31 CFI_INSTRUCTION def_cfa_offset 8, debug-location !31
RET64 implicit $eax, debug-location !31 RET64 implicit $eax, debug-location !31
... ...

llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir

Show First 20 Lines • Show All 158 Lines • ▼ Show 20 Linesbody: |
bb.3: bb.3:
$r15 = MOV64ri 0 $r15 = MOV64ri 0
CMP64ri8 $r15, 0, implicit-def $eflags, debug-location !19 CMP64ri8 $r15, 0, implicit-def $eflags, debug-location !19
JCC_1 %bb.3, 5, implicit $eflags, debug-location !21 JCC_1 %bb.3, 5, implicit $eflags, debug-location !21
bb.4: bb.4:
liveins: $rbx, $r14 liveins: $rbx, $r14
DBG_INSTR_REF 1, 0, !14, !DIExpression(), debug-location !13 DBG_INSTR_REF !14, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !13
DBG_INSTR_REF 2, 0, !12, !DIExpression(), debug-location !13 DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(2, 0), debug-location !13
DBG_INSTR_REF 3, 0, !12, !DIExpression(), debug-location !13 DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(3, 0), debug-location !13
; Value number 1 is live-through the above control flow from the two ; Value number 1 is live-through the above control flow from the two
; DBG_PHIs: ; DBG_PHIs:
; CHECK: DBG_INSTR_REF 1, 0 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NEXT: DBG_VALUE $r14 ; CHECK-NEXT: DBG_VALUE_LIST {{.+}} $r14
; ;
; While value number 2 has different defs that merge on entry to bb.3. ; While value number 2 has different defs that merge on entry to bb.3.
; These are both in $rbx though, and we should find its location: ; These are both in $rbx though, and we should find its location:
; CHECK: DBG_INSTR_REF 2, 0 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
; CHECK-NEXT: DBG_VALUE $rbx ; CHECK-NEXT: DBG_VALUE_LIST {{.+}} $rbx
; ;
; Value number 3 cannot be resolved because $rax is clobbered in bb.2, ; Value number 3 cannot be resolved because $rax is clobbered in bb.2,
; meaning the merged value in bb.3 is incorrect. It should produce a ; meaning the merged value in bb.3 is incorrect. It should produce a
; DBG_VALUE $noreg. ; DBG_VALUE $noreg.
; CHECK: DBG_INSTR_REF 3, 0 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE_LIST {{.+}} $noreg
renamable $rbx = ADD64rr killed renamable $rbx, killed renamable $r14, implicit-def $eflags, debug-location !28 renamable $rbx = ADD64rr killed renamable $rbx, killed renamable $r14, implicit-def $eflags, debug-location !28
DBG_INSTR_REF 2, 0, !12, !DIExpression(), debug-location !13 DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(2, 0), debug-location !13
; After clobbering rbx, the variable location should not be available. ; After clobbering rbx, the variable location should not be available.
; CHECK: DBG_INSTR_REF 2, 0 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE_LIST {{.+}} $noreg
$rdi = MOV64rr $rbx, debug-location !29 $rdi = MOV64rr $rbx, debug-location !29
CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !29 CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !29
$eax = MOV32rr $ebx, implicit killed $rbx, debug-location !31 $eax = MOV32rr $ebx, implicit killed $rbx, debug-location !31
$rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !31 $rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !31
CFI_INSTRUCTION def_cfa_offset 24, debug-location !31 CFI_INSTRUCTION def_cfa_offset 24, debug-location !31
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !31 $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !31
CFI_INSTRUCTION def_cfa_offset 16, debug-location !31 CFI_INSTRUCTION def_cfa_offset 16, debug-location !31
$r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !31 $r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !31
CFI_INSTRUCTION def_cfa_offset 8, debug-location !31 CFI_INSTRUCTION def_cfa_offset 8, debug-location !31
RET64 implicit $eax, debug-location !31 RET64 implicit $eax, debug-location !31
... ...

llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir

Show First 20 Lines • Show All 162 Lines • ▼ Show 20 Lines bb.0.entry:
liveins: $rdi, $rdx, $rsi, $rbp, $r15, $r14, $r13, $r12, $rbx liveins: $rdi, $rdx, $rsi, $rbp, $r15, $r14, $r13, $r12, $rbx
; CHECK-LABEL: bb.0.entry: ; CHECK-LABEL: bb.0.entry:
;; PART ONE: For this first block of tests, check that information about ;; PART ONE: For this first block of tests, check that information about
;; the size of the value on the stack makes it through to the expression. ;; the size of the value on the stack makes it through to the expression.
$al = MOV8ri 0, debug-instr-number 1, debug-location !7 $al = MOV8ri 0, debug-instr-number 1, debug-location !7
DBG_INSTR_REF 1, 0, !8, !DIExpression(DW_OP_LLVM_convert, 8, DW_ATE_signed, DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value), debug-location !7 DBG_INSTR_REF !8, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_convert, 8, DW_ATE_signed, DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value), dbg-instr-ref(1, 0), debug-location !7
; CHECK: DBG_VALUE $al, $noreg, ![[VARNUM]], ; CHECK: DBG_VALUE_LIST ![[VARNUM]],
; CHECK-SAME: !DIExpression(DW_OP_LLVM_convert, 8, DW_ATE_signed, ; CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_convert, 8, DW_ATE_signed,
; CHECK-SAME : DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value) ; CHECK-SAME : DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value), $al
MOV8mr $rsp, 1, $noreg, -8, $noreg, renamable $al :: (store 1 into %stack.0) MOV8mr $rsp, 1, $noreg, -8, $noreg, renamable $al :: (store 1 into %stack.0)
;; Clobber to force variable location onto stack. We should use a ;; Clobber to force variable location onto stack. We should use a
;; deref_size 1 because the value is smaller than the variable. ;; deref_size 1 because the value is smaller than the variable.
$al = MOV8ri 0, debug-location !7 $al = MOV8ri 0, debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM]], ; CHECK: DBG_VALUE_LIST ![[VARNUM]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, ; CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 8, DW_OP_minus,
; CHECK-SAME: DW_OP_deref_size, 1, DW_OP_LLVM_convert, 8, DW_ATE_signed, ; CHECK-SAME: DW_OP_deref_size, 1, DW_OP_LLVM_convert, 8, DW_ATE_signed,
; CHECK-SAME: DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value), ; CHECK-SAME: DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value), $rsp
; Terminate the current variable location, ; Terminate the current variable location,
DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7 DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7
; CHECK: DBG_VALUE $noreg, $noreg, ![[VARNUM]], !DIExpression() ; CHECK: DBG_VALUE $noreg, $noreg, ![[VARNUM]], !DIExpression()
;; Try again, but with the value originating on the stack, to ensure that ;; Try again, but with the value originating on the stack, to ensure that
;; we can find its size. It should be deref_size 1 again. ;; we can find its size. It should be deref_size 1 again.
INC8m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-instr-number 2, debug-location !7 :: (store (s8) into %stack.0) INC8m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-instr-number 2, debug-location !7 :: (store (s8) into %stack.0)
DBG_INSTR_REF 2, 1000000, !8, !DIExpression(DW_OP_LLVM_convert, 8, DW_ATE_signed, DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value), debug-location !7 DBG_INSTR_REF !8, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_convert, 8, DW_ATE_signed, DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value), dbg-instr-ref(2, 1000000), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM]], ; CHECK: DBG_VALUE_LIST ![[VARNUM]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, ; CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 8, DW_OP_minus,
; CHECK-SAME: DW_OP_deref_size, 1, DW_OP_LLVM_convert, 8, DW_ATE_signed, ; CHECK-SAME: DW_OP_deref_size, 1, DW_OP_LLVM_convert, 8, DW_ATE_signed,
; CHECK-SAME: DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value), ; CHECK-SAME: DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value), $rsp
$eax = MOV32ri 0, debug-location !7 $eax = MOV32ri 0, debug-location !7
;; How about DBG_PHIs? The size of the value is communicated by the register ;; How about DBG_PHIs? The size of the value is communicated by the register
;; size, or an extra DBG_PHI operand, and that should feed through into the ;; size, or an extra DBG_PHI operand, and that should feed through into the
;; decision of whether to deref_size or not. ;; decision of whether to deref_size or not.
DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7 DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7
; CHECK: DBG_VALUE $noreg ; CHECK: DBG_VALUE $noreg
$al = MOV8ri 0, debug-location !7 $al = MOV8ri 0, debug-location !7
DBG_PHI $al, 7 DBG_PHI $al, 7
MOV32mr $rsp, 1, $noreg, -8, $noreg, renamable $eax :: (store 4 into %stack.0) MOV32mr $rsp, 1, $noreg, -8, $noreg, renamable $eax :: (store 4 into %stack.0)
$eax = MOV32ri 0, debug-location !7 $eax = MOV32ri 0, debug-location !7
DBG_INSTR_REF 7, 0, !8, !DIExpression(), debug-location !7 DBG_INSTR_REF !8, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(7, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM]], ; CHECK: DBG_VALUE_LIST ![[VARNUM]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 1, DW_OP_stack_value) ; CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 1, DW_OP_stack_value), $rsp
$eax = MOV32ri 0, debug-location !7 $eax = MOV32ri 0, debug-location !7
;; And for when the DBG_PHI specifies a stack size... ;; And for when the DBG_PHI specifies a stack size...
DBG_PHI %stack.0, 8, 16 DBG_PHI %stack.0, 8, 16
DBG_INSTR_REF 8, 0, !8, !DIExpression(), debug-location !7 DBG_INSTR_REF !8, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(8, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM]], ; CHECK: DBG_VALUE_LIST ![[VARNUM]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 2, DW_OP_stack_value) ; CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 2, DW_OP_stack_value), $rsp
$eax = MOV32ri 0, debug-location !7 $eax = MOV32ri 0, debug-location !7
DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7 DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE $noreg, $noreg
DBG_VALUE $noreg, $noreg, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7 DBG_VALUE $noreg, $noreg, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE $noreg, $noreg
;; PART TWO: test the twelve kinds of location expression mentioned in the ;; PART TWO: test the twelve kinds of location expression mentioned in the
;; opening comment of this test, in that order. Please update the opening ;; opening comment of this test, in that order. Please update the opening
;; comment, these lines and the DWARF check lines at the same time. ;; comment, these lines and the DWARF check lines at the same time.
;; In each test we'll state a location, give it an instruction to cover, ;; In each test we'll state a location, give it an instruction to cover,
;; and then terminate it. ;; and then terminate it.
;; Scalar (32), Large value (64), no stack value, ;; Scalar (32), Large value (64), no stack value,
$rax = MOV64ri 0, debug-instr-number 10, debug-location !7 $rax = MOV64ri 0, debug-instr-number 10, debug-location !7
MOV64mr $rsp, 1, $noreg, -8, $noreg, renamable $rax :: (store 8 into %stack.0) MOV64mr $rsp, 1, $noreg, -8, $noreg, renamable $rax :: (store 8 into %stack.0)
$rax = MOV64ri 0, debug-location !7 $rax = MOV64ri 0, debug-location !7
DBG_INSTR_REF 10, 0, !8, !DIExpression(), debug-location !7 DBG_INSTR_REF !8, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(10, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM]], ; CHECK: DBG_VALUE_LIST ![[VARNUM]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 8, DW_OP_stack_value), ; CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 8, DW_OP_stack_value), $rsp
$eax = MOV32ri 0, debug-location !7 $eax = MOV32ri 0, debug-location !7
DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7 DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE $noreg, $noreg
;; Scalar (32), Same value size (32), no stack value, ;; Scalar (32), Same value size (32), no stack value,
$eax = MOV32ri 0, debug-instr-number 11, debug-location !7 $eax = MOV32ri 0, debug-instr-number 11, debug-location !7
MOV32mr $rsp, 1, $noreg, -8, $noreg, renamable $eax :: (store 4 into %stack.0) MOV32mr $rsp, 1, $noreg, -8, $noreg, renamable $eax :: (store 4 into %stack.0)
$rax = MOV64ri 0, debug-location !7 $rax = MOV64ri 0, debug-location !7
DBG_INSTR_REF 11, 0, !8, !DIExpression(), debug-location !7 DBG_INSTR_REF !8, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(11, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, 0, ![[VARNUM]], ; CHECK: DBG_VALUE_LIST ![[VARNUM]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus), ; CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 8, DW_OP_minus, DW_OP_deref), $rsp
$eax = MOV32ri 0, debug-location !7 $eax = MOV32ri 0, debug-location !7
DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7 DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE $noreg, $noreg
;; Scalar (32), Smaller value (8), no stack value, ;; Scalar (32), Smaller value (8), no stack value,
$al = MOV8ri 0, debug-instr-number 12, debug-location !7 $al = MOV8ri 0, debug-instr-number 12, debug-location !7
MOV8mr $rsp, 1, $noreg, -8, $noreg, renamable $al :: (store 1 into %stack.0) MOV8mr $rsp, 1, $noreg, -8, $noreg, renamable $al :: (store 1 into %stack.0)
$rax = MOV64ri 0, debug-location !7 $rax = MOV64ri 0, debug-location !7
DBG_INSTR_REF 12, 0, !8, !DIExpression(), debug-location !7 DBG_INSTR_REF !8, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(12, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM]], ; CHECK: DBG_VALUE_LIST ![[VARNUM]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 1, DW_OP_stack_value), ; CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 1, DW_OP_stack_value), $rsp
$eax = MOV32ri 0, debug-location !7 $eax = MOV32ri 0, debug-location !7
DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7 DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE $noreg, $noreg
;; Fragment (32), Larger value (64), no stack value, ;; Fragment (32), Larger value (64), no stack value,
$rax = MOV64ri 0, debug-instr-number 13, debug-location !7 $rax = MOV64ri 0, debug-instr-number 13, debug-location !7
MOV64mr $rsp, 1, $noreg, -8, $noreg, renamable $rax :: (store 8 into %stack.0) MOV64mr $rsp, 1, $noreg, -8, $noreg, renamable $rax :: (store 8 into %stack.0)
$rax = MOV64ri 0, debug-location !7 $rax = MOV64ri 0, debug-location !7
DBG_INSTR_REF 13, 0, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7 DBG_INSTR_REF !10, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(13, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM2]], ; CHECK: DBG_VALUE_LIST ![[VARNUM2]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 8, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), ; CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 8, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), $rsp
$eax = MOV32ri 0, debug-location !7 $eax = MOV32ri 0, debug-location !7
DBG_VALUE $noreg, $noreg, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7 DBG_VALUE $noreg, $noreg, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE $noreg, $noreg
;; Fragment (32), Same value size (32), no stack value, ;; Fragment (32), Same value size (32), no stack value,
$eax = MOV32ri 0, debug-instr-number 14, debug-location !7 $eax = MOV32ri 0, debug-instr-number 14, debug-location !7
MOV32mr $rsp, 1, $noreg, -8, $noreg, renamable $eax :: (store 4 into %stack.0) MOV32mr $rsp, 1, $noreg, -8, $noreg, renamable $eax :: (store 4 into %stack.0)
$rax = MOV64ri 0, debug-location !7 $rax = MOV64ri 0, debug-location !7
DBG_INSTR_REF 14, 0, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7 DBG_INSTR_REF !10, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(14, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, 0, ![[VARNUM2]], ; CHECK: DBG_VALUE_LIST ![[VARNUM2]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_LLVM_fragment, 0, 32), ; CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 8, DW_OP_minus, DW_OP_deref, DW_OP_LLVM_fragment, 0, 32), $rsp
$eax = MOV32ri 0, debug-location !7 $eax = MOV32ri 0, debug-location !7
DBG_VALUE $noreg, $noreg, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7 DBG_VALUE $noreg, $noreg, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE $noreg, $noreg
;; Fragment (32), Smaller value (8), no stack value, ;; Fragment (32), Smaller value (8), no stack value,
$al = MOV8ri 0, debug-instr-number 15, debug-location !7 $al = MOV8ri 0, debug-instr-number 15, debug-location !7
MOV8mr $rsp, 1, $noreg, -8, $noreg, renamable $al :: (store 1 into %stack.0) MOV8mr $rsp, 1, $noreg, -8, $noreg, renamable $al :: (store 1 into %stack.0)
$rax = MOV64ri 0, debug-location !7 $rax = MOV64ri 0, debug-location !7
DBG_INSTR_REF 15, 0, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7 DBG_INSTR_REF !10, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(15, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM2]], ; CHECK: DBG_VALUE_LIST ![[VARNUM2]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 1, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), ; CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 1, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), $rsp
$eax = MOV32ri 0, debug-location !7 $eax = MOV32ri 0, debug-location !7
DBG_VALUE $noreg, $noreg, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7 DBG_VALUE $noreg, $noreg, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE $noreg, $noreg
;; Scalar (32), Large value (64), with stack value, ;; Scalar (32), Large value (64), with stack value,
$rax = MOV64ri 0, debug-instr-number 16, debug-location !7 $rax = MOV64ri 0, debug-instr-number 16, debug-location !7
MOV64mr $rsp, 1, $noreg, -8, $noreg, renamable $rax :: (store 8 into %stack.0) MOV64mr $rsp, 1, $noreg, -8, $noreg, renamable $rax :: (store 8 into %stack.0)
$rax = MOV64ri 0, debug-location !7 $rax = MOV64ri 0, debug-location !7
DBG_INSTR_REF 16, 0, !8, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), debug-location !7 DBG_INSTR_REF !8, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), dbg-instr-ref(16, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM]], ; CHECK: DBG_VALUE_LIST ![[VARNUM]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 8, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), ; CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 8, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), $rsp
$eax = MOV32ri 0, debug-location !7 $eax = MOV32ri 0, debug-location !7
DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7 DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE $noreg, $noreg
;; Scalar (32), Same value size (32), no stack value, ;; Scalar (32), Same value size (32), no stack value,
$eax = MOV32ri 0, debug-instr-number 17, debug-location !7 $eax = MOV32ri 0, debug-instr-number 17, debug-location !7
MOV32mr $rsp, 1, $noreg, -8, $noreg, renamable $eax :: (store 4 into %stack.0) MOV32mr $rsp, 1, $noreg, -8, $noreg, renamable $eax :: (store 4 into %stack.0)
$rax = MOV64ri 0, debug-location !7 $rax = MOV64ri 0, debug-location !7
DBG_INSTR_REF 17, 0, !8, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), debug-location !7 DBG_INSTR_REF !8, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), dbg-instr-ref(17, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM]], ; CHECK: DBG_VALUE_LIST ![[VARNUM]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), ; CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 8, DW_OP_minus, DW_OP_deref, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), $rsp
$eax = MOV32ri 0, debug-location !7 $eax = MOV32ri 0, debug-location !7
DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7 DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE $noreg, $noreg
;; Scalar (32), Smaller value (8), no stack value, ;; Scalar (32), Smaller value (8), no stack value,
$al = MOV8ri 0, debug-instr-number 18, debug-location !7 $al = MOV8ri 0, debug-instr-number 18, debug-location !7
MOV8mr $rsp, 1, $noreg, -8, $noreg, renamable $al :: (store 1 into %stack.0) MOV8mr $rsp, 1, $noreg, -8, $noreg, renamable $al :: (store 1 into %stack.0)
$rax = MOV64ri 0, debug-location !7 $rax = MOV64ri 0, debug-location !7
DBG_INSTR_REF 18, 0, !8, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), debug-location !7 DBG_INSTR_REF !8, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), dbg-instr-ref(18, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM]], ; CHECK: DBG_VALUE_LIST ![[VARNUM]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 1, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), ; CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 1, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), $rsp
$eax = MOV32ri 0, debug-location !7 $eax = MOV32ri 0, debug-location !7
DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7 DBG_VALUE $noreg, $noreg, !8, !DIExpression(), debug-location !7
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE $noreg, $noreg
;; Fragment (32), Larger value (64), no stack value, ;; Fragment (32), Larger value (64), no stack value,
$rax = MOV64ri 0, debug-instr-number 19, debug-location !7 $rax = MOV64ri 0, debug-instr-number 19, debug-location !7
MOV64mr $rsp, 1, $noreg, -8, $noreg, renamable $rax :: (store 8 into %stack.0) MOV64mr $rsp, 1, $noreg, -8, $noreg, renamable $rax :: (store 8 into %stack.0)
$rax = MOV64ri 0, debug-location !7 $rax = MOV64ri 0, debug-location !7
DBG_INSTR_REF 19, 0, !10, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), debug-location !7 DBG_INSTR_REF !10, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(19, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM2]], ; CHECK: DBG_VALUE_LIST ![[VARNUM2]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 8, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), ; CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 8, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), $rsp
$eax = MOV32ri 0, debug-location !7 $eax = MOV32ri 0, debug-location !7
DBG_VALUE $noreg, $noreg, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7 DBG_VALUE $noreg, $noreg, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE $noreg, $noreg
;; Fragment (32), Same value size (32), no stack value, ;; Fragment (32), Same value size (32), no stack value,
$eax = MOV32ri 0, debug-instr-number 20, debug-location !7 $eax = MOV32ri 0, debug-instr-number 20, debug-location !7
MOV32mr $rsp, 1, $noreg, -8, $noreg, renamable $eax :: (store 4 into %stack.0) MOV32mr $rsp, 1, $noreg, -8, $noreg, renamable $eax :: (store 4 into %stack.0)
$rax = MOV64ri 0, debug-location !7 $rax = MOV64ri 0, debug-location !7
DBG_INSTR_REF 20, 0, !10, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), debug-location !7 DBG_INSTR_REF !10, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(20, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM2]], ; CHECK: DBG_VALUE_LIST ![[VARNUM2]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 4, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), ; CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 4, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), $rsp
$eax = MOV32ri 0, debug-location !7 $eax = MOV32ri 0, debug-location !7
DBG_VALUE $noreg, $noreg, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7 DBG_VALUE $noreg, $noreg, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE $noreg, $noreg
;; Fragment (32), Smaller value (8), no stack value, ;; Fragment (32), Smaller value (8), no stack value,
$al = MOV8ri 0, debug-instr-number 21, debug-location !7 $al = MOV8ri 0, debug-instr-number 21, debug-location !7
MOV8mr $rsp, 1, $noreg, -8, $noreg, renamable $al :: (store 1 into %stack.0) MOV8mr $rsp, 1, $noreg, -8, $noreg, renamable $al :: (store 1 into %stack.0)
$rax = MOV64ri 0, debug-location !7 $rax = MOV64ri 0, debug-location !7
DBG_INSTR_REF 21, 0, !10, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), debug-location !7 DBG_INSTR_REF !10, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(21, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM2]], ; CHECK: DBG_VALUE_LIST ![[VARNUM2]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 1, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), ; CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 1, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), $rsp
$eax = MOV32ri 0, debug-location !7 $eax = MOV32ri 0, debug-location !7
DBG_VALUE $noreg, $noreg, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7 DBG_VALUE $noreg, $noreg, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE $noreg, $noreg
RET64 0, debug-location !7 RET64 0, debug-location !7
... ...

llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir

Show All 14 Lines
# 8 and used for a comparison and a DBG_INSTR_REF. A valid variable location # 8 and used for a comparison and a DBG_INSTR_REF. A valid variable location
# should be emitted -- it's not too important what the location is, this test # should be emitted -- it's not too important what the location is, this test
# is that LiveDebugValues can track the value, not where it puts it. # is that LiveDebugValues can track the value, not where it puts it.
# #
## Capture variable num, ## Capture variable num,
# CHECK: ![[VARNUM:[0-9]+]] = !DILocalVariable # CHECK: ![[VARNUM:[0-9]+]] = !DILocalVariable
# #
# CHECK-LABEL: bb.8: # CHECK-LABEL: bb.8:
# CHECK: DBG_VALUE $rsp, 0, ![[VARNUM]], !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_LLVM_fragment, 64, 64), # CHECK: DBG_VALUE_LIST ![[VARNUM]], !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 8, DW_OP_minus, DW_OP_deref, DW_OP_LLVM_fragment, 64, 64), $rsp,
# CHECK-LABEL: bb.9: # CHECK-LABEL: bb.9:
# CHECK: DBG_VALUE $rsp, 0, ![[VARNUM]], !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_LLVM_fragment, 64, 64), # CHECK: DBG_VALUE_LIST ![[VARNUM]], !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 8, DW_OP_minus, DW_OP_deref, DW_OP_LLVM_fragment, 64, 64), $rsp,
--- | --- |
; ModuleID = 'missingvar.ll' ; ModuleID = 'missingvar.ll'
source_filename = "/fast/fs/llvm34/lib/Analysis/LoopPass.cpp" source_filename = "/fast/fs/llvm34/lib/Analysis/LoopPass.cpp"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
%"class.std::deque" = type { %"class.std::_Deque_base" } %"class.std::deque" = type { %"class.std::_Deque_base" }
▲ Show 20 Lines • Show All 263 Lines • ▼ Show 20 Lines bb.8:
liveins: $rax, $rdi, $rdx, $rsi, $r8, $r9, $r10, $r11, $r14 liveins: $rax, $rdi, $rdx, $rsi, $r8, $r9, $r10, $r11, $r14
MOV64mr renamable $rdi, 1, $noreg, 16, $noreg, killed renamable $rax, debug-location !7 :: (store 8 into %ir.22) MOV64mr renamable $rdi, 1, $noreg, 16, $noreg, killed renamable $rax, debug-location !7 :: (store 8 into %ir.22)
renamable $rax = MOV64rm $rsp, 1, $noreg, -8, $noreg :: (load 8 from %stack.0) renamable $rax = MOV64rm $rsp, 1, $noreg, -8, $noreg :: (load 8 from %stack.0)
MOV64mr undef renamable $rax, 1, $noreg, 0, $noreg, killed renamable $rax, debug-location !7 :: (store 8 into `%"class.llvm::Loop"*** undef`) MOV64mr undef renamable $rax, 1, $noreg, 0, $noreg, killed renamable $rax, debug-location !7 :: (store 8 into `%"class.llvm::Loop"*** undef`)
MOV64mr undef renamable $rax, 1, $noreg, 0, $noreg, killed renamable $r10, debug-location !7 :: (store 8 into `%"class.llvm::Loop"*** undef`) MOV64mr undef renamable $rax, 1, $noreg, 0, $noreg, killed renamable $r10, debug-location !7 :: (store 8 into `%"class.llvm::Loop"*** undef`)
MOV64mr killed renamable $rdi, 1, $noreg, 40, $noreg, killed renamable $r9, debug-location !7 :: (store 8 into %ir.24) MOV64mr killed renamable $rdi, 1, $noreg, 40, $noreg, killed renamable $r9, debug-location !7 :: (store 8 into %ir.24)
renamable $rax = MOV64rm killed renamable $rsi, 1, $noreg, 24, $noreg, debug-location !7 :: (load 8 from %ir.26) renamable $rax = MOV64rm killed renamable $rsi, 1, $noreg, 24, $noreg, debug-location !7 :: (load 8 from %ir.26)
DBG_INSTR_REF 1, 0, !8, !DIExpression(DW_OP_LLVM_fragment, 64, 64), debug-location !7 DBG_INSTR_REF !8, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(1, 0), debug-location !7
renamable $rax = SUB64rr killed renamable $rax, killed renamable $r11, implicit-def dead $eflags, debug-location !7 renamable $rax = SUB64rr killed renamable $rax, killed renamable $r11, implicit-def dead $eflags, debug-location !7
renamable $r8 = SUB64rr killed renamable $r8, killed renamable $r14, implicit-def dead $eflags, debug-location !7 renamable $r8 = SUB64rr killed renamable $r8, killed renamable $r14, implicit-def dead $eflags, debug-location !7
renamable $r8 = exact SAR64ri killed renamable $r8, 3, implicit-def dead $eflags, debug-location !7 renamable $r8 = exact SAR64ri killed renamable $r8, 3, implicit-def dead $eflags, debug-location !7
renamable $rax = LEA64r killed renamable $r8, 8, killed renamable $rax, -64, $noreg, debug-location !7 renamable $rax = LEA64r killed renamable $r8, 8, killed renamable $rax, -64, $noreg, debug-location !7
TEST64rr killed renamable $rax, renamable $rax, implicit-def $eflags, debug-location !7 TEST64rr killed renamable $rax, renamable $rax, implicit-def $eflags, debug-location !7
JCC_1 %bb.10, 15, implicit $eflags, debug-location !7 JCC_1 %bb.10, 15, implicit $eflags, debug-location !7
bb.9: bb.9:
Show All 20 Lines

llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir

Show All 39 Lines
debugValueSubstitutions: debugValueSubstitutions:
- { srcinst: 4, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 } - { srcinst: 4, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 }
body: | body: |
bb.0.entry: bb.0.entry:
successors: %bb.1, %bb.2 successors: %bb.1, %bb.2
; CHECK-LABE: bb.0.entry: ; CHECK-LABE: bb.0.entry:
$rax = MOV64ri 1, debug-instr-number 1, debug-location !17 $rax = MOV64ri 1, debug-instr-number 1, debug-location !17
DBG_INSTR_REF 1, 0, !16, !DIExpression(), debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !17
;; First check that picking out location works as usual. ;; First check that picking out location works as usual.
; CHECK: DBG_INSTR_REF 1, 0 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NEXT: DBG_VALUE $rax ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $rax
$rax = MOV64ri 1, debug-instr-number 2, debug-location !17 $rax = MOV64ri 1, debug-instr-number 2, debug-location !17
DBG_INSTR_REF 2, 999, !16, !DIExpression(), debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(2, 999), debug-location !17
;; Test out of bounds operand number. ;; Test out of bounds operand number.
; CHECK: DBG_INSTR_REF 2, 999 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 999)
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $noreg
$rax = MOV64ri 1, debug-instr-number 3, debug-location !17 $rax = MOV64ri 1, debug-instr-number 3, debug-location !17
DBG_INSTR_REF 3, 1, !16, !DIExpression(), debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(3, 1), debug-location !17
;; Test non-register operand ;; Test non-register operand
; CHECK: DBG_INSTR_REF 3, 1 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 1)
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $noreg
;; FIXME: We should test what happens when this meta-instruction is seen ;; FIXME: We should test what happens when this meta-instruction is seen
;; by livedbugvalues with an instruction number. However, right now it's ;; by livedbugvalues with an instruction number. However, right now it's
;; impossible to turn the machine-code verifier off when loading MIR? ;; impossible to turn the machine-code verifier off when loading MIR?
;KILL implicit killed $eflags, debug-instr-number 4, debug-location !17 ;KILL implicit killed $eflags, debug-instr-number 4, debug-location !17
;DBG_INSTR_REF 4, 0, !16, !DIExpression(), debug-location !17 ;DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(4, 0), debug-location !17
;;; Test non-def operand ;;; Test non-def operand
;; check: DBG_INSTR_REF 4, 0 ;; check: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
;; check-next: DBG_VALUE $noreg ;; check-next: DBG_VALUE_LIST {{.+}}, $noreg
$noreg = MOV32ri 1, debug-instr-number 5, debug-location !17 $noreg = MOV32ri 1, debug-instr-number 5, debug-location !17
DBG_INSTR_REF 5, 0, !16, !DIExpression(), debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(5, 0), debug-location !17
;; Def of $noreg? ;; Def of $noreg?
; CHECK: DBG_INSTR_REF 5, 0 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(5, 0)
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $noreg
JCC_1 %bb.1, 1, implicit $eflags JCC_1 %bb.1, 1, implicit $eflags
JMP_1 %bb.2 JMP_1 %bb.2
bb.1: bb.1:
successors: %bb.3 successors: %bb.3
; CHECK-LABEL: bb.1: ; CHECK-LABEL: bb.1:
DBG_PHI $rax, 6 DBG_PHI $rax, 6
DBG_INSTR_REF 6, 1, !16, !DIExpression(), debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(6, 1), debug-location !17
;; Test out-of-bounds reference to a DBG_PHI. ;; Test out-of-bounds reference to a DBG_PHI.
; CHECK: DBG_INSTR_REF 6, 1 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(6, 1)
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $noreg
DBG_PHI $noreg, 7 DBG_PHI $noreg, 7
JMP_1 %bb.3 JMP_1 %bb.3
bb.2: bb.2:
successors: %bb.3 successors: %bb.3
; CHECK-LABEL: bb.2: ; CHECK-LABEL: bb.2:
DBG_PHI 1, 6 DBG_PHI 1, 6
DBG_INSTR_REF 6, 0, !16, !DIExpression(), debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(6, 0), debug-location !17
;; Test non-reg operand to DBG_PHI. It's not clear if this can ever happen ;; Test non-reg operand to DBG_PHI. It's not clear if this can ever happen
;; as the result of an optimisation, but lets test for it anyway. ;; as the result of an optimisation, but lets test for it anyway.
; CHECK: DBG_INSTR_REF 6, 0 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(6, 0)
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $noreg
DBG_PHI 1, 7 DBG_PHI 1, 7
JMP_1 %bb.3 JMP_1 %bb.3
bb.3: bb.3:
; CHECK-LABEL: bb.3: ; CHECK-LABEL: bb.3:
DBG_INSTR_REF 7, 0, !16, !DIExpression(), debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(7, 0), debug-location !17
;; PHI resolution of illegal inputs shouldn't crash either. It should also ;; PHI resolution of illegal inputs shouldn't crash either. It should also
;; come out as a $noreg location. ;; come out as a $noreg location.
; CHECK: DBG_INSTR_REF 7, 0 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(7, 0)
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $noreg
RET 0, debug-location !17 RET 0, debug-location !17
... ...

llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir

Show All 31 Lines
--- ---
name: _Z8bb_to_bb name: _Z8bb_to_bb
debugValueSubstitutions: debugValueSubstitutions:
- { srcinst: 4, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 } - { srcinst: 4, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 }
body: | body: |
bb.0.entry: bb.0.entry:
$rax = MOV64ri 1, debug-instr-number 1, debug-location !17 $rax = MOV64ri 1, debug-instr-number 1, debug-location !17
; This debug instruction should identify the value as being in $rax. ; This debug instruction should identify the value as being in $rax.
DBG_INSTR_REF 1, 0, !16, !DIExpression(), debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !17
; CHECK: DBG_VALUE $rax, $noreg ; CHECK: DBG_VALUE_LIST {{.+}}, $rax
$rbx = COPY killed $rax, debug-location !17 $rbx = COPY killed $rax, debug-location !17
$rax = MOV64ri 1, debug-location !17 $rax = MOV64ri 1, debug-location !17
; CHECK: DBG_VALUE $rbx, $noreg ; CHECK: DBG_VALUE_LIST {{.+}}, $rbx
DBG_INSTR_REF 2, 0, !16, !DIExpression(), debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(2, 0), debug-location !17
; No instruction is labelled with the number "2". This should produce an ; No instruction is labelled with the number "2". This should produce an
; empty variable location. ; empty variable location.
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE_LIST {{.+}}, $noreg
$rbx = MOV64ri 1, debug-instr-number 3, debug-location !17 $rbx = MOV64ri 1, debug-instr-number 3, debug-location !17
JMP_1 %bb.1 JMP_1 %bb.1
; CHECK-LABEL: bb.1: ; CHECK-LABEL: bb.1:
bb.1: bb.1:
DBG_INSTR_REF 3, 0, !16, !DIExpression(), debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(3, 0), debug-location !17
; This refers to a value def'd in a parent block -- but it should be ; This refers to a value def'd in a parent block -- but it should be
; tracked into this block. ; tracked into this block.
; CHECK: DBG_VALUE $rbx, $noreg ; CHECK: DBG_VALUE_LIST {{.+}}, $rbx
JMP_1 %bb.2 JMP_1 %bb.2
; CHECK-LABEL: bb.2: ; CHECK-LABEL: bb.2:
bb.2: bb.2:
; Just like any other variable location, live-ins should be created for ; Just like any other variable location, live-ins should be created for
; any successor blocks. ; any successor blocks.
; CHECK: DBG_VALUE $rbx, $noreg ; CHECK: DBG_VALUE_LIST {{.+}}, $rbx
DBG_INSTR_REF 5, 0, !16, !DIExpression(), debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(5, 0), debug-location !17
; This is a debug use-before-def: the value appears a few instructions ; This is a debug use-before-def: the value appears a few instructions
; later. Any earlier value should be terminated here, _and_ we should ; later. Any earlier value should be terminated here, _and_ we should
; emit a DBG_VALUE when the value becomes available. ; emit a DBG_VALUE when the value becomes available.
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE_LIST {{.+}}, $noreg
$rax = MOV64ri 1, debug-location !17 $rax = MOV64ri 1, debug-location !17
$rax = MOV64ri 1, debug-location !17 $rax = MOV64ri 1, debug-location !17
$rcx = MOV64ri 1, debug-instr-number 5, debug-location !17 $rcx = MOV64ri 1, debug-instr-number 5, debug-location !17
; CHECK: DBG_VALUE $rcx, $noreg ; CHECK: DBG_VALUE_LIST {{.+}}, $rcx
$rax = MOV64ri 1, debug-location !17 $rax = MOV64ri 1, debug-location !17
DBG_INSTR_REF 6, 0, !16, !DIExpression(), debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(6, 0), debug-location !17
; Another debug use-before-def, but across block boundaries. ; Another debug use-before-def, but across block boundaries.
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE_LIST {{.+}}, $noreg
JMP_1 %bb.3 JMP_1 %bb.3
; CHECK-LABEL: bb.3: ; CHECK-LABEL: bb.3:
bb.3: bb.3:
$rax = MOV64ri 1, debug-location !17 $rax = MOV64ri 1, debug-location !17
$rdx = MOV64ri 1, debug-instr-number 6, debug-location !17 $rdx = MOV64ri 1, debug-instr-number 6, debug-location !17
; CHECK: DBG_VALUE $rdx, $noreg ; CHECK: DBG_VALUE_LIST {{.+}}, $rdx
; Terminate variable location for next few blocks, ; Terminate variable location for next few blocks,
DBG_VALUE $noreg, $noreg, !16, !DIExpression(), debug-location !17 DBG_VALUE $noreg, $noreg, !16, !DIExpression(), debug-location !17
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE $noreg, $noreg
JMP_1 %bb.4 JMP_1 %bb.4
bb.4: bb.4:
; The next three blocks form a debug use-before-def modelling a scenario ; The next three blocks form a debug use-before-def modelling a scenario
; where an instruction is sunk (debug inst in bb5, value in bb6). However, ; where an instruction is sunk (debug inst in bb5, value in bb6). However,
; because a different path joins bb.6, we should _not_ add any DBG_VALUE. ; because a different path joins bb.6, we should _not_ add any DBG_VALUE.
; A different variable value may enter the block via the other path. ; A different variable value may enter the block via the other path.
$rdx = MOV64ri 1, implicit-def $eflags, debug-location !17 $rdx = MOV64ri 1, implicit-def $eflags, debug-location !17
JCC_1 %bb.6, 4, implicit $eflags, debug-location !17 JCC_1 %bb.6, 4, implicit $eflags, debug-location !17
bb.5: bb.5:
DBG_INSTR_REF 7, 0, !16, !DIExpression(), debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(7, 0), debug-location !17
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE_LIST {{.+}}, $noreg
JMP_1 %bb.6, debug-location !17 JMP_1 %bb.6, debug-location !17
bb.6: bb.6:
$rsi = MOV64ri 1, debug-instr-number 7, debug-location !17 $rsi = MOV64ri 1, debug-instr-number 7, debug-location !17
JMP_1 %bb.7, debug-location !17 JMP_1 %bb.7, debug-location !17
; A use-before-def shouldn't pass another definition of the variable location ; A use-before-def shouldn't pass another definition of the variable location
; or value. ; or value.
bb.7: bb.7:
DBG_INSTR_REF 8, 0, !16, !DIExpression(), debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(8, 0), debug-location !17
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE_LIST {{.+}}, $noreg
DBG_VALUE $rax, $noreg, !16, !DIExpression(), debug-location !17 DBG_VALUE $rax, $noreg, !16, !DIExpression(), debug-location !17
; CHECK: DBG_VALUE $rax, $noreg, ; CHECK: DBG_VALUE $rax, $noreg,
$rdi = MOV64ri 1, debug-instr-number 8, debug-location !17 $rdi = MOV64ri 1, debug-instr-number 8, debug-location !17
; Loops: use-before-defs should be live-through loops, assuming that nothing ; Loops: use-before-defs should be live-through loops, assuming that nothing
; in that loop modifies the variable location. ; in that loop modifies the variable location.
bb.8: bb.8:
DBG_INSTR_REF 9, 0, !16, !DIExpression(), debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(9, 0), debug-location !17
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE_LIST {{.+}}, $noreg
JCC_1 %bb.8, 4, implicit $eflags JCC_1 %bb.8, 4, implicit $eflags
bb.9: bb.9:
$rax = MOV64ri 11, debug-instr-number 9, debug-location !17 $rax = MOV64ri 11, debug-instr-number 9, debug-location !17
; CHECK: DBG_VALUE $rax, $noreg, ; CHECK: DBG_VALUE_LIST {{.+}}, $rax
; Likewise, use-before-defs where anything changes the variable location ; Likewise, use-before-defs where anything changes the variable location
; or value in the loop, should be discarded. ; or value in the loop, should be discarded.
bb.10: bb.10:
; live-in, ; live-in,
; CHECK: DBG_VALUE $rax, $noreg, ; CHECK: DBG_VALUE_LIST {{.+}}, $rax
DBG_INSTR_REF 10, 0, !16, !DIExpression(), debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(10, 0), debug-location !17
; CHECK: DBG_VALUE $noreg, $noreg ; CHECK: DBG_VALUE_LIST {{.+}}, $noreg
bb.11: bb.11:
$rbx = MOV64ri 1, debug-location !17 $rbx = MOV64ri 1, debug-location !17
bb.12: bb.12:
DBG_INSTR_REF 9, 0, !16, !DIExpression(), debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(9, 0), debug-location !17
; This still has a value in $rax, ; This still has a value in $rax,
; CHECK: DBG_VALUE $rax, $noreg ; CHECK: DBG_VALUE_LIST {{.+}}, $rax
JCC_1 %bb.11, 4, implicit $eflags JCC_1 %bb.11, 4, implicit $eflags
bb.13: bb.13:
; Live in, ; Live in,
; CHECK: DBG_VALUE $rax, $noreg ; CHECK: DBG_VALUE_LIST {{.+}}, $rax
$rbx = MOV64ri 11, debug-instr-number 10, debug-location !17 $rbx = MOV64ri 11, debug-instr-number 10, debug-location !17
; This is instruction 10 referred to in bb.10. However, as the variable ; This is instruction 10 referred to in bb.10. However, as the variable
; location/value has been modified in the meantime, no DBG_VALUE should be ; location/value has been modified in the meantime, no DBG_VALUE should be
; generated here. ; generated here.
RET64 $eax, debug-location !17 RET64 $eax, debug-location !17
... ...

llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines liveins: $rdi, $rax, $rbx
$rsi = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0) $rsi = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0)
; Store a random value onto stack, forces value to be in one place only. ; Store a random value onto stack, forces value to be in one place only.
; Clobber other registers that contain the value we're to track. ; Clobber other registers that contain the value we're to track.
MOV64mr $rsp, 1, $noreg, 16, $noreg, $rbx :: (store 8 into %stack.0) MOV64mr $rsp, 1, $noreg, 16, $noreg, $rbx :: (store 8 into %stack.0)
$rax = MOV64ri 0 $rax = MOV64ri 0
$rdi = MOV64ri 0 $rdi = MOV64ri 0
DBG_INSTR_REF 1, 0, !11, !DIExpression(), debug-location !12 DBG_INSTR_REF !11, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !12
; CHECK: DBG_INSTR_REF ; CHECK: DBG_INSTR_REF
; CHECK-NEXT: DBG_VALUE $esi ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $esi
RET64 $rsi, debug-location !12 RET64 $rsi, debug-location !12
... ...

llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Linesstack:
- { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8, - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body: | body: |
bb.0: bb.0:
liveins: $rdi, $rax liveins: $rdi, $rax
CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rax, debug-instr-number 4, debug-location !12 CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rax, debug-instr-number 4, debug-location !12
; CHECK: CALL64pcrel32 ; CHECK: CALL64pcrel32
DBG_INSTR_REF 1, 0, !11, !DIExpression(), debug-location !12 DBG_INSTR_REF !11, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !12
; CHECK-NEXT: DBG_INSTR_REF 1, 0 ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NEXT: DBG_VALUE $al ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $al
DBG_INSTR_REF 5, 0, !11, !DIExpression(), debug-location !12 DBG_INSTR_REF !11, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(5, 0), debug-location !12
; CHECK-NEXT: DBG_INSTR_REF 5, 0 ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(5, 0)
; CHECK-NEXT: DBG_VALUE $ah ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $ah
DBG_INSTR_REF 8, 0, !11, !DIExpression(), debug-location !12 DBG_INSTR_REF !11, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(8, 0), debug-location !12
; CHECK-NEXT: DBG_INSTR_REF 8, 0 ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(8, 0)
; CHECK-NEXT: DBG_VALUE $ah ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $ah
DBG_INSTR_REF 13, 0, !11, !DIExpression(), debug-location !12 DBG_INSTR_REF !11, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(13, 0), debug-location !12
; CHECK-NEXT: DBG_INSTR_REF 13, 0 ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(13, 0)
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $noreg
MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0) MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)
$rax = MOV64ri 0, debug-location !12 $rax = MOV64ri 0, debug-location !12
; CHECK: $rax = MOV64ri 0 ; CHECK: $rax = MOV64ri 0
; The value is now located in a spill slot, as a subregister within the ; The value is now located in a spill slot, as a subregister within the
; slot, which InstrRefBasedLDV should be able to find. ; slot, which InstrRefBasedLDV should be able to find.
DBG_INSTR_REF 1, 0, !11, !DIExpression(), debug-location !12 DBG_INSTR_REF !11, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !12
; CHECK-NEXT: DBG_INSTR_REF 1, 0 ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NEXT: DBG_VALUE $rsp, 0, !{{[0-9]*}}, !DIExpression(DW_OP_constu, 8, DW_OP_minus) ; CHECK-NEXT: DBG_VALUE_LIST !{{[0-9]*}}, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 8, DW_OP_minus, DW_OP_deref), $rsp
DBG_INSTR_REF 5, 0, !11, !DIExpression(), debug-location !12 DBG_INSTR_REF !11, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(5, 0), debug-location !12
; This and the next DBG_INSTR_REF refer to a value that is on the stack, but ; This and the next DBG_INSTR_REF refer to a value that is on the stack, but
; is located at a non-zero offset from the start of the slot -- $ah within ; is located at a non-zero offset from the start of the slot -- $ah within
; $rax is 8 bits in. Today, InstrRefBasedLDV can't express this. It also ; $rax is 8 bits in. Today, InstrRefBasedLDV can't express this. It also
; doesn't seem likely to be profitable. ; doesn't seem likely to be profitable.
; CHECK-NEXT: DBG_INSTR_REF 5, 0 ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(5, 0)
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $noreg
DBG_INSTR_REF 8, 0, !11, !DIExpression(), debug-location !12 DBG_INSTR_REF !11, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(8, 0), debug-location !12
; CHECK-NEXT: DBG_INSTR_REF 8, 0 ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(8, 0)
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $noreg
DBG_INSTR_REF 13, 0, !11, !DIExpression(), debug-location !12 DBG_INSTR_REF !11, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(13, 0), debug-location !12
; CHECK-NEXT: DBG_INSTR_REF 13, 0 ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(13, 0)
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $noreg
$rax = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0) $rax = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0)
RET64 $rax, debug-location !12 RET64 $rax, debug-location !12
... ...

llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir

Show First 20 Lines • Show All 165 Lines • ▼ Show 20 Lines bb.5:
MOV64mr %33, 1, $noreg, 0, $noreg, %12, debug-location !13 :: (store (s64) into `i64* undef`) MOV64mr %33, 1, $noreg, 0, $noreg, %12, debug-location !13 :: (store (s64) into `i64* undef`)
%11:gr32 = MOV32rm %34, 1, $noreg, 0, $noreg, debug-location !13 :: (load (s32) from `i32* undef`, align 8) %11:gr32 = MOV32rm %34, 1, $noreg, 0, $noreg, debug-location !13 :: (load (s32) from `i32* undef`, align 8)
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !13 ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !13
$rdi = COPY %35, debug-location !13 $rdi = COPY %35, debug-location !13
$rsi = COPY %36, debug-location !13 $rsi = COPY %36, debug-location !13
CALL64r %37, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit-def $rsp, implicit-def $ssp, implicit-def $al, debug-location !13 CALL64r %37, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit-def $rsp, implicit-def $ssp, implicit-def $al, debug-location !13
ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !13 ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !13
%13:gr32 = INC32r %6, implicit-def dead $eflags, debug-instr-number 1, debug-location !13 %13:gr32 = INC32r %6, implicit-def dead $eflags, debug-instr-number 1, debug-location !13
DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13 DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !13
JMP_1 %bb.1, debug-location !13 JMP_1 %bb.1, debug-location !13
... ...

llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding.mir

Show First 20 Lines • Show All 244 Lines • ▼ Show 20 Lines bb.12:
MOV8mr %34, 1, $noreg, 0, $noreg, %1, debug-location !13 :: (store (s8) into `i8* undef`, align 8) MOV8mr %34, 1, $noreg, 0, $noreg, %1, debug-location !13 :: (store (s8) into `i8* undef`, align 8)
%35:gr64 = IMPLICIT_DEF %35:gr64 = IMPLICIT_DEF
MOV64mr %35, 1, $noreg, 0, $noreg, %4, debug-location !13 :: (store (s64) into `%"class.llvm::Instruction"** undef`) MOV64mr %35, 1, $noreg, 0, $noreg, %4, debug-location !13 :: (store (s64) into `%"class.llvm::Instruction"** undef`)
%36:gr8 = IMPLICIT_DEF %36:gr8 = IMPLICIT_DEF
$al = COPY %36 $al = COPY %36
RET 0, $al RET 0, $al
bb.13: bb.13:
DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13 DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !13
%32:gr64 = IMPLICIT_DEF %32:gr64 = IMPLICIT_DEF
MOV8mr killed %32, 1, $noreg, 0, $noreg, %0, debug-location !13 :: (store (s8) into `i8* undef`, align 8) MOV8mr killed %32, 1, $noreg, 0, $noreg, %0, debug-location !13 :: (store (s8) into `i8* undef`, align 8)
%33:gr8 = IMPLICIT_DEF %33:gr8 = IMPLICIT_DEF
$al = COPY %33 $al = COPY %33
RET 0, $al RET 0, $al
... ...

llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir

Show First 20 Lines • Show All 105 Lines • ▼ Show 20 Lines bb.0.if.then:
JCC_1 %bb.3, 5, implicit killed $eflags JCC_1 %bb.3, 5, implicit killed $eflags
JMP_1 %bb.1 JMP_1 %bb.1
bb.1.sw.bb: bb.1.sw.bb:
successors: %bb.2(0x30000000), %bb.3(0x50000000) successors: %bb.2(0x30000000), %bb.3(0x50000000)
%7:gr32 = nofpexcept CVTTSS2SIrr killed %1, implicit $mxcsr, debug-instr-number 1 %7:gr32 = nofpexcept CVTTSS2SIrr killed %1, implicit $mxcsr, debug-instr-number 1
%8:gr8 = COPY killed %7.sub_8bit %8:gr8 = COPY killed %7.sub_8bit
DBG_INSTR_REF 2, 0, !6, !DIExpression(), debug-location !17 DBG_INSTR_REF !6, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(2, 0), debug-location !17
TEST8rr killed %8, %8, implicit-def $eflags TEST8rr killed %8, %8, implicit-def $eflags
JCC_1 %bb.3, 5, implicit killed $eflags JCC_1 %bb.3, 5, implicit killed $eflags
JMP_1 %bb.2 JMP_1 %bb.2
bb.2.if.end: bb.2.if.end:
successors: %bb.3(0x80000000) successors: %bb.3(0x80000000)
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
Show All 10 Lines

llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body: | body: |
bb.0: bb.0:
liveins: $rdi, $rax liveins: $rdi, $rax
DBG_PHI $rax, 1 DBG_PHI $rax, 1
MOV64mr $rsp, 1, $noreg, 16, $noreg, $rdi :: (store 8 into %stack.0) MOV64mr $rsp, 1, $noreg, 16, $noreg, $rdi :: (store 8 into %stack.0)
$rax = MOV64ri 0, debug-location !12 $rax = MOV64ri 0, debug-location !12
INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-instr-number 3, debug-location !DILocation(line: 0, scope: !7) :: (store (s32) into %stack.0) INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-instr-number 3, debug-location !DILocation(line: 0, scope: !7) :: (store (s32) into %stack.0)
DBG_INSTR_REF 2, 0, !11, !DIExpression(), debug-location !12 DBG_INSTR_REF !11, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(2, 0), debug-location !12
; CHECK: DBG_INSTR_REF 2, 0 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
; CHECK-NEXT: DBG_VALUE $rsp ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $rsp
;; Test that the old value (from the DBG_PHI) is not tracked anywhere. It ;; Test that the old value (from the DBG_PHI) is not tracked anywhere. It
;; should not be considered as being on the stack any more. ;; should not be considered as being on the stack any more.
DBG_INSTR_REF 1, 0, !11, !DIExpression(), debug-location !12 DBG_INSTR_REF !11, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !12
; CHECK: DBG_INSTR_REF 1, 0 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $noreg
INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-location !12 :: (store (s32) into %stack.0) INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-location !12 :: (store (s32) into %stack.0)
;; The above INC32m should be detected as clobbering the stack location, ;; The above INC32m should be detected as clobbering the stack location,
;; even though it isn't debug labelled. ;; even though it isn't debug labelled.
DBG_INSTR_REF 2, 0, !11, !DIExpression(), debug-location !12 DBG_INSTR_REF !11, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(2, 0), debug-location !12
; CHECK: DBG_INSTR_REF 2, 0 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $noreg
;; Store another debug-labelled value to the stack, ;; Store another debug-labelled value to the stack,
INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-instr-number 5, debug-location !DILocation(line: 0, scope: !7) :: (store (s32) into %stack.0) INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-instr-number 5, debug-location !DILocation(line: 0, scope: !7) :: (store (s32) into %stack.0)
;; Point the variable at that value. ;; Point the variable at that value.
DBG_INSTR_REF 4, 0, !11, !DIExpression(), debug-location !12 DBG_INSTR_REF !11, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(4, 0), debug-location !12
; CHECK: DBG_INSTR_REF 4, 0, ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0),
; CHECK-NEXT: DBG_VALUE $rsp ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $rsp
;; Overwrite the stack: LiveDebugValues should explicitly undef the stack ;; Overwrite the stack: LiveDebugValues should explicitly undef the stack
;; location with DBG_VALUE $noreg, as DbgEntityHistoryCalculator doesn't ;; location with DBG_VALUE_LIST $noreg, as DbgEntityHistoryCalculator doesn't
;; look at the stack. ;; look at the stack.
INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-location !DILocation(line: 0, scope: !7) :: (store (s32) into %stack.0) INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-location !DILocation(line: 0, scope: !7) :: (store (s32) into %stack.0)
; CHECK: INC32m $rsp ; CHECK: INC32m $rsp
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $noreg
$rax = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0) $rax = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0)
RET64 $rax, debug-location !12 RET64 $rax, debug-location !12
... ...

llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir

# RUN: llc %s -o - -run-pass=livedebugvalues -march=x86-64 \ # RUN: llc %s -o - -run-pass=livedebugvalues -march=x86-64 \
# RUN: -experimental-debug-variable-locations=true \ # RUN: -experimental-debug-variable-locations=true \
# RUN: | FileCheck %s # RUN: | FileCheck %s
# #
## This test used to crash InstrRefBasedLDV, due to fragment information going ## This test used to crash InstrRefBasedLDV, due to fragment information going
## missing; test for that, and also check what happens when we have assignments ## missing; test for that, and also check what happens when we have assignments
## outside of lexical scope. In the IR below, "_First" is only in scope in the ## outside of lexical scope. In the IR below, "_First" is only in scope in the
## entry block, but is assigned in every block. Under current behaviour, that ## entry block, but is assigned in every block. Under current behaviour, that
## means that InstrRefBasedLDV will propagate its location through all blocks. ## means that InstrRefBasedLDV will propagate its location through all blocks.
# #
# CHECK: ![[FIRSTVAR:[0-9]+]] = !DILocalVariable(name: "_First", # CHECK: ![[FIRSTVAR:[0-9]+]] = !DILocalVariable(name: "_First",
# #
# CHECK-LABEL: bb.0.entry: # CHECK-LABEL: bb.0.entry:
# CHECK: DBG_VALUE $rbx, $noreg, ![[FIRSTVAR]], # CHECK: DBG_VALUE_LIST ![[FIRSTVAR]],
# CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 64, 64) # CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 64), $rbx
# #
# CHECK-LABEL: bb.1.if.then.i.i.i.i.i: # CHECK-LABEL: bb.1.if.then.i.i.i.i.i:
# CHECK: DBG_VALUE $rbx, $noreg, ![[FIRSTVAR]], # CHECK: DBG_VALUE_LIST ![[FIRSTVAR]],
# CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 64, 64) # CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 64), $rbx
# CHECK: DBG_INSTR_REF {{.*}} ![[FIRSTVAR]], # CHECK: DBG_INSTR_REF ![[FIRSTVAR]],
# CHECK: DBG_VALUE $rbx, $noreg, ![[FIRSTVAR]], # CHECK: DBG_VALUE_LIST ![[FIRSTVAR]],
# CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 64, 64) # CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 64), $rbx
# CHECK-LABEL: bb.2._Z17do_insert_cv_testI5_TreeEvv.exit: # CHECK-LABEL: bb.2._Z17do_insert_cv_testI5_TreeEvv.exit:
# CHECK: DBG_VALUE $rbx, $noreg, ![[FIRSTVAR]], # CHECK: DBG_VALUE_LIST ![[FIRSTVAR]],
# CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 64, 64) # CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 64), $rbx
# CHECK: DBG_INSTR_REF {{.*}} ![[FIRSTVAR]], # CHECK: DBG_INSTR_REF ![[FIRSTVAR]],
# CHECK: DBG_VALUE $rbx, $noreg, ![[FIRSTVAR]], # CHECK: DBG_VALUE_LIST ![[FIRSTVAR]],
# CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 64, 64) # CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 64), $rbx
--- | --- |
source_filename = "reduced.ll" source_filename = "reduced.ll"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
%class._Tree = type { i8 } %class._Tree = type { i8 }
%class._Tree_const_iterator = type { %class._Tree_unchecked_const_iterator } %class._Tree_const_iterator = type { %class._Tree_unchecked_const_iterator }
%class._Tree_unchecked_const_iterator = type { %struct._Iterator_base0, i32* } %class._Tree_unchecked_const_iterator = type { %struct._Iterator_base0, i32* }
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines bb.0.entry:
CFI_INSTRUCTION offset $rbx, -24 CFI_INSTRUCTION offset $rbx, -24
CFI_INSTRUCTION offset $r14, -16 CFI_INSTRUCTION offset $r14, -16
DBG_PHI $rsi, 2 DBG_PHI $rsi, 2
$rbx = MOV64rr $rsi $rbx = MOV64rr $rsi
DBG_VALUE 2, $noreg, !10, !DIExpression(), debug-location !12 DBG_VALUE 2, $noreg, !10, !DIExpression(), debug-location !12
renamable $r14d = XOR32rr undef $r14d, undef $r14d, implicit-def dead $eflags, implicit-def $r14 renamable $r14d = XOR32rr undef $r14d, undef $r14d, implicit-def dead $eflags, implicit-def $r14
dead $edi = XOR32rr undef $edi, undef $edi, implicit-def dead $eflags, implicit-def $rdi dead $edi = XOR32rr undef $edi, undef $edi, implicit-def dead $eflags, implicit-def $rdi
CALL64r undef renamable $rax, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def dead $eax, implicit-def dead $rdx CALL64r undef renamable $rax, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def dead $eax, implicit-def dead $rdx
DBG_INSTR_REF 2, 0, !13, !DIExpression(DW_OP_LLVM_fragment, 64, 64), debug-location !15 DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(2, 0), debug-location !15
dead $edi = XOR32rr undef $edi, undef $edi, implicit-def dead $eflags, implicit-def $rdi, debug-location !15 dead $edi = XOR32rr undef $edi, undef $edi, implicit-def dead $eflags, implicit-def $rdi, debug-location !15
CALL64r undef renamable $rax, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def dead $al, debug-location !15 CALL64r undef renamable $rax, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def dead $al, debug-location !15
TEST8rr renamable $r14b, renamable $r14b, implicit-def $eflags, implicit killed $r14 TEST8rr renamable $r14b, renamable $r14b, implicit-def $eflags, implicit killed $r14
JCC_1 %bb.2, 5, implicit $eflags JCC_1 %bb.2, 5, implicit $eflags
bb.1.if.then.i.i.i.i.i: bb.1.if.then.i.i.i.i.i:
dead $edi = XOR32rr undef $edi, undef $edi, implicit-def dead $eflags, implicit-def $rdi dead $edi = XOR32rr undef $edi, undef $edi, implicit-def dead $eflags, implicit-def $rdi
CALL64r undef renamable $rax, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $rax, debug-instr-number 3 CALL64r undef renamable $rax, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $rax, debug-instr-number 3
$rbx = MOV64rr killed $rax $rbx = MOV64rr killed $rax
DBG_INSTR_REF 3, 7, !13, !DIExpression(DW_OP_LLVM_fragment, 64, 64), debug-location !15 DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(3, 7), debug-location !15
bb.2._Z17do_insert_cv_testI5_TreeEvv.exit: bb.2._Z17do_insert_cv_testI5_TreeEvv.exit:
liveins: $rbx liveins: $rbx
DBG_PHI $rbx, 1 DBG_PHI $rbx, 1
DBG_INSTR_REF 1, 0, !13, !DIExpression(DW_OP_LLVM_fragment, 64, 64), debug-location !15 DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(1, 0), debug-location !15
dead $edi = XOR32rr undef $edi, undef $edi, implicit-def dead $eflags, implicit-def $rdi, debug-location !16 dead $edi = XOR32rr undef $edi, undef $edi, implicit-def dead $eflags, implicit-def $rdi, debug-location !16
$esi = XOR32rr undef $esi, undef $esi, implicit-def dead $eflags, debug-location !16 $esi = XOR32rr undef $esi, undef $esi, implicit-def dead $eflags, debug-location !16
$rdx = MOV64rr killed $rbx, debug-location !16 $rdx = MOV64rr killed $rbx, debug-location !16
CALL64r undef renamable $rax, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit $esi, implicit killed $rdx, implicit-def $rsp, implicit-def $ssp, debug-location !16 CALL64r undef renamable $rax, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit $esi, implicit killed $rdx, implicit-def $rsp, implicit-def $ssp, debug-location !16
$eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
$rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags $rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags
CFI_INSTRUCTION def_cfa_offset 24 CFI_INSTRUCTION def_cfa_offset 24
$rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
$r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp $r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 8 CFI_INSTRUCTION def_cfa_offset 8
RET64 killed $eax RET64 killed $eax
... ...

llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir

Show First 20 Lines • Show All 138 Lines • ▼ Show 20 Linesbody: |
; Verify those registers land in $bx ; Verify those registers land in $bx
; CHECK: renamable $ebp = ADD32ri8 ; CHECK: renamable $ebp = ADD32ri8
; DOESCOALESCE-LABEL: bb.2.if.end: ; DOESCOALESCE-LABEL: bb.2.if.end:
; CHECK-LABEL: bb.2.if.end: ; CHECK-LABEL: bb.2.if.end:
bb.2.if.end: bb.2.if.end:
%2:gr16 = PHI %11, %bb.0, %17, %bb.1, debug-instr-number 1, debug-location !13 %2:gr16 = PHI %11, %bb.0, %17, %bb.1, debug-instr-number 1, debug-location !13
; CHECK: DBG_PHI $bp, 1 ; CHECK: DBG_PHI $bp, 1
DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13 DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !13
%31:gr32 = MOVSX32rr16 %6, debug-location !13 %31:gr32 = MOVSX32rr16 %6, debug-location !13
%30:gr32 = MOVSX32rr16 killed %2, debug-location !13 %30:gr32 = MOVSX32rr16 killed %2, debug-location !13
%29:gr32 = ADD32rr killed %30, killed %31, implicit-def $eflags, debug-location !13 %29:gr32 = ADD32rr killed %30, killed %31, implicit-def $eflags, debug-location !13
%26:gr16 = COPY killed %29.sub_16bit, debug-location !13 %26:gr16 = COPY killed %29.sub_16bit, debug-location !13
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13 ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
%24:gr32 = MOVSX32rr16 %26, debug-location !13 %24:gr32 = MOVSX32rr16 %26, debug-location !13
$edi = COPY %24, debug-location !13 $edi = COPY %24, debug-location !13
CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $edi, debug-location !13 CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $edi, debug-location !13
ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13 ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
%23:gr32 = MOVSX32rr16 %26, debug-location !13 %23:gr32 = MOVSX32rr16 %26, debug-location !13
$eax = COPY %23, debug-location !13 $eax = COPY %23, debug-location !13
RET64 implicit $eax, debug-location !13 RET64 implicit $eax, debug-location !13
... ...

llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir

Show First 20 Lines • Show All 141 Lines • ▼ Show 20 Linesbody: |
; Verify that all these registers land in rbx. ; Verify that all these registers land in rbx.
; CHECK: renamable $rbx = ADD64ri32 killed renamable $rbx ; CHECK: renamable $rbx = ADD64ri32 killed renamable $rbx
; DOESCOALESCE-LABEL: bb.2.if.end: ; DOESCOALESCE-LABEL: bb.2.if.end:
; CHECK-LABEL: bb.2.if.end: ; CHECK-LABEL: bb.2.if.end:
bb.2.if.end: bb.2.if.end:
%2:gr64 = PHI %9, %bb.0, %10, %bb.1, debug-instr-number 1, debug-location !13 %2:gr64 = PHI %9, %bb.0, %10, %bb.1, debug-instr-number 1, debug-location !13
; CHECK: DBG_PHI $rbx, 1 ; CHECK: DBG_PHI $rbx, 1
DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13 DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !13
%14:gr64 = ADD64rr killed %2, %6, implicit-def $eflags, debug-location !13 %14:gr64 = ADD64rr killed %2, %6, implicit-def $eflags, debug-location !13
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13 ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
$rdi = COPY %14, debug-location !13 $rdi = COPY %14, debug-location !13
CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !13 CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !13
ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13 ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
%13:gr32 = COPY %14.sub_32bit, debug-location !13 %13:gr32 = COPY %14.sub_32bit, debug-location !13
$eax = COPY %13, debug-location !13 $eax = COPY %13, debug-location !13
RET64 implicit $eax, debug-location !13 RET64 implicit $eax, debug-location !13
... ...

llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir

Show First 20 Lines • Show All 140 Lines • ▼ Show 20 Lines bb.2:
%59:gr32 = PHI %19, %bb.0, %39, %bb.1, debug-location !18 %59:gr32 = PHI %19, %bb.0, %39, %bb.1, debug-location !18
%60:gr32 = PHI %20, %bb.0, %40, %bb.1, debug-location !18 %60:gr32 = PHI %20, %bb.0, %40, %bb.1, debug-location !18
%61:gr32 = PHI %21, %bb.0, %41, %bb.1, debug-location !18 %61:gr32 = PHI %21, %bb.0, %41, %bb.1, debug-location !18
%62:gr32 = PHI %22, %bb.0, %42, %bb.1, debug-location !18 %62:gr32 = PHI %22, %bb.0, %42, %bb.1, debug-location !18
%63:gr32 = PHI %23, %bb.0, %43, %bb.1, debug-location !18 %63:gr32 = PHI %23, %bb.0, %43, %bb.1, debug-location !18
%64:gr32 = PHI %24, %bb.0, %44, %bb.1, debug-location !18 %64:gr32 = PHI %24, %bb.0, %44, %bb.1, debug-location !18
INLINEASM &"", 1, 12, %50, 12, %51, 12, %52, 12, %53, 12, %54, 12, %55, 12, %56, 12, %57, 12, %58, 12, %59, 12, %60, 12, %61, 12, %62, 12, %63, 12, %64 INLINEASM &"", 1, 12, %50, 12, %51, 12, %52, 12, %53, 12, %54, 12, %55, 12, %56, 12, %57, 12, %58, 12, %59, 12, %60, 12, %61, 12, %62, 12, %63, 12, %64
DBG_INSTR_REF 1, 0, !14, !DIExpression(), debug-location !12 DBG_INSTR_REF !14, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !12
; CHECK: DBG_PHI %stack.0, 1, 16 ; CHECK: DBG_PHI %stack.0, 1, 16
; CHECK: DBG_INSTR_REF 1, 0 ; CHECK: DBG_INSTR_REF {{.+}} dbg-instr-ref(1, 0)
; CHECK: renamable $eax = MOV32rm %stack.0, ; CHECK: renamable $eax = MOV32rm %stack.0,
$eax = COPY killed %0, debug-location !19 $eax = COPY killed %0, debug-location !19
RET 0, killed $eax, debug-location !19 RET 0, killed $eax, debug-location !19
... ...

llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir

Show First 20 Lines • Show All 139 Lines • ▼ Show 20 Lines bb.2:
%59:gr32 = PHI %19, %bb.0, %39, %bb.1, debug-location !18 %59:gr32 = PHI %19, %bb.0, %39, %bb.1, debug-location !18
%60:gr32 = PHI %20, %bb.0, %40, %bb.1, debug-location !18 %60:gr32 = PHI %20, %bb.0, %40, %bb.1, debug-location !18
%61:gr32 = PHI %21, %bb.0, %41, %bb.1, debug-location !18 %61:gr32 = PHI %21, %bb.0, %41, %bb.1, debug-location !18
%62:gr32 = PHI %22, %bb.0, %42, %bb.1, debug-location !18 %62:gr32 = PHI %22, %bb.0, %42, %bb.1, debug-location !18
%63:gr32 = PHI %23, %bb.0, %43, %bb.1, debug-location !18 %63:gr32 = PHI %23, %bb.0, %43, %bb.1, debug-location !18
%64:gr32 = PHI %24, %bb.0, %44, %bb.1, debug-location !18 %64:gr32 = PHI %24, %bb.0, %44, %bb.1, debug-location !18
INLINEASM &"", 1, 12, %50, 12, %51, 12, %52, 12, %53, 12, %54, 12, %55, 12, %56, 12, %57, 12, %58, 12, %59, 12, %60, 12, %61, 12, %62, 12, %63, 12, %64 INLINEASM &"", 1, 12, %50, 12, %51, 12, %52, 12, %53, 12, %54, 12, %55, 12, %56, 12, %57, 12, %58, 12, %59, 12, %60, 12, %61, 12, %62, 12, %63, 12, %64
DBG_INSTR_REF 1, 0, !14, !DIExpression(), debug-location !12 DBG_INSTR_REF !14, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !12
; CHECK-NOT: DBG_PHI ; CHECK-NOT: DBG_PHI
; CHECK: DBG_INSTR_REF 1, 0 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NOT: DBG_PHI ; CHECK-NOT: DBG_PHI
$eax = COPY killed %0, debug-location !19 $eax = COPY killed %0, debug-location !19
RET 0, killed $eax, debug-location !19 RET 0, killed $eax, debug-location !19
... ...

llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir

Show First 20 Lines • Show All 133 Lines • ▼ Show 20 Lines bb.2:
%58:gr32 = PHI %18, %bb.0, %38, %bb.1, debug-location !18 %58:gr32 = PHI %18, %bb.0, %38, %bb.1, debug-location !18
%59:gr32 = PHI %19, %bb.0, %39, %bb.1, debug-location !18 %59:gr32 = PHI %19, %bb.0, %39, %bb.1, debug-location !18
%60:gr32 = PHI %20, %bb.0, %40, %bb.1, debug-location !18 %60:gr32 = PHI %20, %bb.0, %40, %bb.1, debug-location !18
%61:gr32 = PHI %21, %bb.0, %41, %bb.1, debug-location !18 %61:gr32 = PHI %21, %bb.0, %41, %bb.1, debug-location !18
%62:gr32 = PHI %22, %bb.0, %42, %bb.1, debug-location !18 %62:gr32 = PHI %22, %bb.0, %42, %bb.1, debug-location !18
%63:gr32 = PHI %23, %bb.0, %43, %bb.1, debug-location !18 %63:gr32 = PHI %23, %bb.0, %43, %bb.1, debug-location !18
%64:gr32 = PHI %24, %bb.0, %44, %bb.1, debug-location !18 %64:gr32 = PHI %24, %bb.0, %44, %bb.1, debug-location !18
DBG_INSTR_REF 1, 0, !14, !DIExpression(), debug-location !12 DBG_INSTR_REF !14, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !12
; CHECK: DBG_PHI %stack.1, 1, 32 ; CHECK: DBG_PHI %stack.1, 1, 32
; CHECK: renamable $eax = MOV32rm %stack.1, ; CHECK: renamable $eax = MOV32rm %stack.1,
; CHECK: DBG_INSTR_REF 1, 0 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
$eax = COPY killed %0, debug-location !19 $eax = COPY killed %0, debug-location !19
RET 0, killed $eax, debug-location !19 RET 0, killed $eax, debug-location !19
... ...

llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir

Show First 20 Lines • Show All 114 Lines • ▼ Show 20 Lines bb.0.entry:
JCC_1 %bb.2, 5, implicit killed $eflags, debug-location !17 JCC_1 %bb.2, 5, implicit killed $eflags, debug-location !17
JMP_1 %bb.1, debug-location !17 JMP_1 %bb.1, debug-location !17
bb.1.if.else: bb.1.if.else:
; CHECK-LABEL: bb.2.if.end: ; CHECK-LABEL: bb.2.if.end:
bb.2.if.end: bb.2.if.end:
%0:gr32 = PHI %1, %bb.0, %2, %bb.1, debug-instr-number 1, debug-location !18 %0:gr32 = PHI %1, %bb.0, %2, %bb.1, debug-instr-number 1, debug-location !18
DBG_INSTR_REF 1, 0, !14, !DIExpression(), debug-location !12 DBG_INSTR_REF !14, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !12
; CHECK: DBG_PHI $ebp, 1 ; CHECK: DBG_PHI $ebp, 1
; CHECK: DBG_INSTR_REF 1, 0 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
$eax = COPY killed %0, debug-location !19 $eax = COPY killed %0, debug-location !19
; Confirm that %0 is allocated in $ebp, ; Confirm that %0 is allocated in $ebp,
; CHECK: $eax = COPY killed renamable $ebp ; CHECK: $eax = COPY killed renamable $ebp
RET 0, killed $eax, debug-location !19 RET 0, killed $eax, debug-location !19
... ...

llvm/test/DebugInfo/MIR/InstrRef/pick-vphi-in-shifting-loop.mir

# RUN: llc %s -o - -run-pass=livedebugvalues \ # RUN: llc %s -o - -run-pass=livedebugvalues \
# RUN: -experimental-debug-variable-locations \ # RUN: -experimental-debug-variable-locations \
# RUN: | FileCheck %s # RUN: | FileCheck %s
# #
# This test used to cause an infinite loop in InstrRefBasedLDV. Observe block # This test used to cause an infinite loop in InstrRefBasedLDV. Observe block
# five: on the first entry the desired variable value is in $rdx and $rcx, on # five: on the first entry the desired variable value is in $rdx and $rcx, on
# both paths to the block. However, the block rotates values between those # both paths to the block. However, the block rotates values between those
# registers, and feeds a zero-value in too. Ultimately, there is no correct # registers, and feeds a zero-value in too. Ultimately, there is no correct
# location for the variable in that block. # location for the variable in that block.
# This caused an infinite loop in a previous implementation of LiveDebugValues. # This caused an infinite loop in a previous implementation of LiveDebugValues.
# Keep this around as a regression test, and check that no location is picked # Keep this around as a regression test, and check that no location is picked
# in block 5. # in block 5.
# #
# CHECK-LABEL: bb.3: # CHECK-LABEL: bb.3:
# CHECK: DBG_INSTR_REF 7, 0 # CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(7, 0)
# CHECK-NEXT: DBG_VALUE $rdx # CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $rdx
# CHECK-NEXT: $rcx = MOV64rr $rdx # CHECK-NEXT: $rcx = MOV64rr $rdx
# CHECK-LABEL: bb.4: # CHECK-LABEL: bb.4:
# CHECK: DBG_VALUE $rcx # CHECK: DBG_VALUE_LIST {{.+}}, $rcx
# CHECK-NEXT: $rdx = MOV64rr killed $rcx # CHECK-NEXT: $rdx = MOV64rr killed $rcx
# CHECK-LABEL: bb.5: # CHECK-LABEL: bb.5:
# CHEKC-NOT: DBG_VALUE # CHECK-NOT: DBG_VALUE
--- | --- |
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
; Function Attrs: nofree norecurse nosync nounwind readonly uwtable ; Function Attrs: nofree norecurse nosync nounwind readonly uwtable
define dso_local void @bees() local_unnamed_addr !dbg !13 { define dso_local void @bees() local_unnamed_addr !dbg !13 {
entry: entry:
ret void, !dbg !22 ret void, !dbg !22
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines bb.0:
$rdx = MOV64ri 0, implicit-def $eflags $rdx = MOV64ri 0, implicit-def $eflags
$esi = MOV32ri 0, implicit-def $eflags $esi = MOV32ri 0, implicit-def $eflags
bb.1: bb.1:
successors: %bb.2(0x03e0f83e), %bb.1(0x7c1f07c2) successors: %bb.2(0x03e0f83e), %bb.1(0x7c1f07c2)
liveins: $rcx, $rdi, $rdx, $eflags liveins: $rcx, $rdi, $rdx, $eflags
DBG_PHI $rcx, 2 DBG_PHI $rcx, 2
DBG_INSTR_REF 2, 0, !18, !DIExpression(), debug-location !22 DBG_INSTR_REF !18, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(2, 0), debug-location !22
JCC_1 %bb.1, 4, implicit $eflags, debug-location !22 JCC_1 %bb.1, 4, implicit $eflags, debug-location !22
bb.2: bb.2:
successors: %bb.4(0x30000000), %bb.3(0x50000000) successors: %bb.4(0x30000000), %bb.3(0x50000000)
liveins: $rcx, $rdi, $eflags liveins: $rcx, $rdi, $eflags
JCC_1 %bb.4, 4, implicit $eflags, debug-location !22 JCC_1 %bb.4, 4, implicit $eflags, debug-location !22
bb.3: bb.3:
successors: %bb.5(0x04000000) successors: %bb.5(0x04000000)
liveins: $rcx, $rdi, $eflags liveins: $rcx, $rdi, $eflags
$rdx = MOV64ri 0, debug-instr-number 7, debug-location !22 $rdx = MOV64ri 0, debug-instr-number 7, debug-location !22
DBG_INSTR_REF 7, 0, !18, !DIExpression(), debug-location !22 DBG_INSTR_REF !18, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(7, 0), debug-location !22
$rcx = MOV64rr $rdx $rcx = MOV64rr $rdx
JMP_1 %bb.5, debug-location !22 JMP_1 %bb.5, debug-location !22
bb.4: bb.4:
liveins: $rcx, $rdi, $eflags liveins: $rcx, $rdi, $eflags
$rdx = MOV64rr killed $rcx, debug-location !22 $rdx = MOV64rr killed $rcx, debug-location !22
Show All 12 Lines

llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir

Show All 13 Lines
# #
# This is a copy of livedebugvalues_stackslot_subregs.mir, here the stack slot # This is a copy of livedebugvalues_stackslot_subregs.mir, here the stack slot
# limit is set to zero, meaning the spill shouldn't be tracked. # limit is set to zero, meaning the spill shouldn't be tracked.
# #
## Capture variable num, ## Capture variable num,
# CHECK: ![[VARNUM:[0-9]+]] = !DILocalVariable # CHECK: ![[VARNUM:[0-9]+]] = !DILocalVariable
# #
## There should be no variable location, just a single DBG_VALUE $noreg. ## There should be no variable location, just a single DBG_VALUE $noreg.
# CHECK: DBG_VALUE $noreg # CHECK: DBG_VALUE_LIST {{.+}} $noreg
# #
## And then another. ## And then another.
# CHECK: DBG_VALUE $noreg # CHECK: DBG_VALUE_LIST {{.+}} $noreg
# #
## Test that if there's no limit, we _do_ get some locations. ## Test that if there's no limit, we _do_ get some locations.
# NOLIMIT: DBG_INSTR_REF 1, 0 # NOLIMIT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
# NOLIMIT-NEXT: DBG_VALUE $esi # NOLIMIT-NEXT: DBG_VALUE_LIST {{.+}} $esi
# #
# NOLIMIT: DBG_INSTR_REF 5, # NOLIMIT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(5,
# NOLIMIT-NEXT: DBG_VALUE $rsp # NOLIMIT-NEXT: DBG_VALUE_LIST {{.+}} $rsp
--- | --- |
define i8 @test(i32 %bar) local_unnamed_addr !dbg !7 { define i8 @test(i32 %bar) local_unnamed_addr !dbg !7 {
entry: entry:
ret i8 0, !dbg !12 ret i8 0, !dbg !12
} }
declare dso_local void @ext(i64) declare dso_local void @ext(i64)
Show All 29 Lines liveins: $rdi, $rax, $rbx
$edi = COPY $eax $edi = COPY $eax
MOV64mr $rsp, 1, $noreg, 16, $noreg, $rdi :: (store 8 into %stack.0) MOV64mr $rsp, 1, $noreg, 16, $noreg, $rdi :: (store 8 into %stack.0)
$rsi = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0) $rsi = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0)
MOV64mr $rsp, 1, $noreg, 16, $noreg, $rbx :: (store 8 into %stack.0) MOV64mr $rsp, 1, $noreg, 16, $noreg, $rbx :: (store 8 into %stack.0)
$rax = MOV64ri 0 $rax = MOV64ri 0
$rdi = MOV64ri 0 $rdi = MOV64ri 0
DBG_INSTR_REF 1, 0, !11, !DIExpression(), debug-location !12 DBG_INSTR_REF !11, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !12
; This shouldn't find anything -- we have disabled tracking of spills. ; This shouldn't find anything -- we have disabled tracking of spills.
; In addition to plain spills, spills that are folded into instructions ; In addition to plain spills, spills that are folded into instructions
; shouldn't be tracked either. ; shouldn't be tracked either.
INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-instr-number 5, debug-location !12 :: (store (s32) into %stack.0) INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-instr-number 5, debug-location !12 :: (store (s32) into %stack.0)
DBG_INSTR_REF 5, 1000000, !11, !DIExpression(), debug-location !12 DBG_INSTR_REF !11, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(5, 1000000), debug-location !12
; Shouldn't be able to find the reference to instr 5's memory operand. ; Shouldn't be able to find the reference to instr 5's memory operand.
RET64 $rsi, debug-location !12 RET64 $rsi, debug-location !12
... ...

llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir

Show First 20 Lines • Show All 213 Lines • ▼ Show 20 Linesbody: |
bb.13: bb.13:
successors: %bb.18(0x2aaaaaab), %bb.14(0x55555555) successors: %bb.18(0x2aaaaaab), %bb.14(0x55555555)
%2:gr32 = PHI undef %35:gr32, %bb.11, %14, %bb.21 %2:gr32 = PHI undef %35:gr32, %bb.11, %14, %bb.21
%3:gr64 = PHI %36, %bb.11, %13, %bb.21 %3:gr64 = PHI %36, %bb.11, %13, %bb.21
;AAAAAA %4:gr32 = PHI %0, %bb.11, %10, %bb.21, debug-instr-number 1 ;AAAAAA %4:gr32 = PHI %0, %bb.11, %10, %bb.21, debug-instr-number 1
;BBBBBB %4:gr32 = PHI %0, %bb.11, %10, %bb.21 ;BBBBBB %4:gr32 = PHI %0, %bb.11, %10, %bb.21
%5:gr32 = PHI undef %35:gr32, %bb.11, %9, %bb.21 %5:gr32 = PHI undef %35:gr32, %bb.11, %9, %bb.21
;AAAAAA DBG_INSTR_REF 1, 0, !10, !DIExpression(), debug-location !9 ;AAAAAA DBG_INSTR_REF !10, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !9
;BBBBBB DBG_VALUE %4, 0, !10, !DIExpression(), debug-location !9 ;BBBBBB DBG_VALUE %4, 0, !10, !DIExpression(), debug-location !9
%39:gr8 = COPY %27.sub_8bit %39:gr8 = COPY %27.sub_8bit
TEST8rr killed %39, %39, implicit-def $eflags, debug-location !9 TEST8rr killed %39, %39, implicit-def $eflags, debug-location !9
JCC_1 %bb.18, 5, implicit killed $eflags, debug-location !9 JCC_1 %bb.18, 5, implicit killed $eflags, debug-location !9
JMP_1 %bb.14, debug-location !9 JMP_1 %bb.14, debug-location !9
bb.14: bb.14:
successors: %bb.17(0x40000001), %bb.15(0x3fffffff) successors: %bb.17(0x40000001), %bb.15(0x3fffffff)
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines

llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir

# RUN: llc %s -march=x86-64 -run-pass=machineverifier \ # RUN: llc %s -march=x86-64 -run-pass=machineverifier \
# RUN: -experimental-debug-variable-locations -o - 2>&1 | FileCheck %s # RUN: -experimental-debug-variable-locations -o - 2>&1 | FileCheck %s
# #
# REQUIRES: x86-registered-target # REQUIRES: x86-registered-target
# #
# CHECK: debugValueSubstitutions: # CHECK: debugValueSubstitutions:
# CHECK-NEXT: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 } # CHECK-NEXT: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 }
# #
# CHECK: MOV64rr $rdi, debug-instr-number 2 # CHECK: MOV64rr $rdi, debug-instr-number 2
# CHECK-NEXT: DBG_INSTR_REF 1, 0 # CHECK-NEXT: DBG_INSTR_REF dbg-instr-ref(1, 0)
--- ---
name: test name: test
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$rdi', virtual-reg: '' } - { reg: '$rdi', virtual-reg: '' }
debugValueSubstitutions: debugValueSubstitutions:
- { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 } - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 }
body: | body: |
bb.0: bb.0:
liveins: $rdi, $rax liveins: $rdi, $rax
$rbp = MOV64rr $rdi, debug-instr-number 2 $rbp = MOV64rr $rdi, debug-instr-number 2
DBG_INSTR_REF 1, 0 DBG_INSTR_REF dbg-instr-ref(1, 0)
dead $rcx = MOV64ri 0 dead $rcx = MOV64ri 0
CMP64ri8 renamable $rax, 1, implicit-def $eflags CMP64ri8 renamable $rax, 1, implicit-def $eflags
RET64 $rax RET64 $rax
... ...

llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir

# RUN: llc -start-after=phi-node-elimination -stop-after=virtregrewriter %s -mtriple=x86_64-unknown-unknown -o - -experimental-debug-variable-locations | FileCheck %s # RUN: llc -start-after=phi-node-elimination -stop-after=virtregrewriter %s -mtriple=x86_64-unknown-unknown -o - -experimental-debug-variable-locations | FileCheck %s
# RUN: llc -O0 -start-after=phi-node-elimination -stop-after=regallocfast %s -mtriple=x86_64-unknown-unknown -o - -experimental-debug-variable-locations | FileCheck %s --check-prefix=FASTREG # RUN: llc -O0 -start-after=phi-node-elimination -stop-after=regallocfast %s -mtriple=x86_64-unknown-unknown -o - -experimental-debug-variable-locations | FileCheck %s --check-prefix=FASTREG
# #
# Test that DBG_INSTR_REFs can pass through livedebugvariables to the end of # Test that DBG_INSTR_REFs can pass through livedebugvariables to the end of
# regalloc without problem. Program body copied from # regalloc without problem. Program body copied from
# livedebugvars-crossbb-interval.mir. # livedebugvars-crossbb-interval.mir.
# #
# CHECK-LABEL: bb.0: # CHECK-LABEL: bb.0:
# CHECK: DBG_INSTR_REF 1, 0 # CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
# CHECK-NEXT: JMP_1 # CHECK-NEXT: JMP_1
# CHECK-LABEL: bb.1: # CHECK-LABEL: bb.1:
# CHECK: DBG_INSTR_REF 2, 0 # CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
# CHECK-NEXT: JMP_1 # CHECK-NEXT: JMP_1
# CHECK-LABEL: bb.2: # CHECK-LABEL: bb.2:
# CHECK: DBG_INSTR_REF 3, 0 # CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
# CHECK-NEXT: CALL64pcrel32 # CHECK-NEXT: CALL64pcrel32
# CHECK-LABEL: bb.3: # CHECK-LABEL: bb.3:
# CHECK: DBG_INSTR_REF 4, 0 # CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
# CHECK-NEXT: JMP_1 # CHECK-NEXT: JMP_1
# #
# #
# The fast register allocator puts some spills in -- these are no-ops as far # The fast register allocator puts some spills in -- these are no-ops as far
# as the slot indexes are concerned. It doesn't matter which side of spills # as the slot indexes are concerned. It doesn't matter which side of spills
# the DBG_INSTR_REF lands on. # the DBG_INSTR_REF lands on.
# #
# FASTREG-LABEL: bb.0: # FASTREG-LABEL: bb.0:
# FASTREG-DAG: DBG_INSTR_REF 1, 0 # FASTREG-DAG: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
# FASTREG-DAG: MOV64mr # FASTREG-DAG: MOV64mr
# FASTREG-DAG: MOV32mr # FASTREG-DAG: MOV32mr
# FASTREG-NEXT: JMP_1 # FASTREG-NEXT: JMP_1
# FASTREG-LABEL: bb.1: # FASTREG-LABEL: bb.1:
# FASTREG: DBG_INSTR_REF 2, 0 # FASTREG: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
# FASTREG-NEXT: JMP_1 # FASTREG-NEXT: JMP_1
# FASTREG-LABEL: bb.2: # FASTREG-LABEL: bb.2:
# FASTREG: DBG_INSTR_REF 3, 0 # FASTREG: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
# FASTREG-NEXT: CALL64pcrel32 # FASTREG-NEXT: CALL64pcrel32
# FASTREG-LABEL: bb.3: # FASTREG-LABEL: bb.3:
# FASTREG-DAG: MOV32rm # FASTREG-DAG: MOV32rm
# FASTREG-DAG: DBG_INSTR_REF 4, 0 # FASTREG-DAG: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
# FASTREG-DAG: MOV32mr # FASTREG-DAG: MOV32mr
# FASTREG-NEXT: JMP_1 # FASTREG-NEXT: JMP_1
# FASTREG-LABEL: bb.4: # FASTREG-LABEL: bb.4:
# FASTREG: DBG_INSTR_REF 5, 0 # FASTREG: DBG_INSTR_REF {{.+}}, dbg-instr-ref(5, 0)
# FASTREG-NEXT: RET64 # FASTREG-NEXT: RET64
--- | --- |
; ModuleID = 'tmp.ll' ; ModuleID = 'tmp.ll'
source_filename = "tmp.ll" source_filename = "tmp.ll"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
%struct.a = type { i32 } %struct.a = type { i32 }
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $rdi, $esi liveins: $rdi, $esi
%4:gr32 = COPY $esi %4:gr32 = COPY $esi
%2:gr64 = COPY $rdi %2:gr64 = COPY $rdi
%3:gr64 = COPY killed %2 %3:gr64 = COPY killed %2
%5:gr32 = COPY killed %4 %5:gr32 = COPY killed %4
DBG_INSTR_REF 1, 0, !9, !DIExpression(), debug-location !16 DBG_INSTR_REF !9, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !16
JMP_1 %bb.3 JMP_1 %bb.3
bb.1: bb.1:
DBG_INSTR_REF 2, 0, !9, !DIExpression(), debug-location !16 DBG_INSTR_REF !9, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(2, 0), debug-location !16
JMP_1 %bb.4 JMP_1 %bb.4
bb.2: bb.2:
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !19 ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !19
$edi = COPY %6, debug-location !19 $edi = COPY %6, debug-location !19
$al = MOV8ri 0, debug-location !19 $al = MOV8ri 0, debug-location !19
DBG_INSTR_REF 3, 0, !9, !DIExpression(), debug-location !16 DBG_INSTR_REF !9, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(3, 0), debug-location !16
CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $al, implicit $edi, implicit-def $eax, debug-location !19 CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $al, implicit $edi, implicit-def $eax, debug-location !19
ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !19 ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !19
%7:gr32 = COPY $eax, debug-location !19 %7:gr32 = COPY $eax, debug-location !19
JMP_1 %bb.1 JMP_1 %bb.1
bb.3: bb.3:
%6:gr32 = MOV32rm %3, 1, $noreg, 0, $noreg, debug-location !17 %6:gr32 = MOV32rm %3, 1, $noreg, 0, $noreg, debug-location !17
DBG_INSTR_REF 4, 0, !9, !DIExpression(), debug-location !16 DBG_INSTR_REF !9, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(4, 0), debug-location !16
JMP_1 %bb.2 JMP_1 %bb.2
bb.4: bb.4:
$eax = COPY %5, debug-location !18 $eax = COPY %5, debug-location !18
DBG_INSTR_REF 5, 0, !9, !DIExpression(), debug-location !16 DBG_INSTR_REF !9, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(5, 0), debug-location !16
RET64 implicit $eax, debug-location !18 RET64 implicit $eax, debug-location !18
... ...

llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir

# RUN: llc -run-pass=twoaddressinstruction -mtriple=x86_64-- -o - %s -experimental-debug-variable-locations | FileCheck %s # RUN: llc -run-pass=twoaddressinstruction -mtriple=x86_64-- -o - %s -experimental-debug-variable-locations | FileCheck %s
# #
# REQUIRES: x86-registered-target # REQUIRES: x86-registered-target
# #
# Test that a new instruction (LEA) is created when the two-addr add below is # Test that a new instruction (LEA) is created when the two-addr add below is
# converted to three address; and that an appropriate substitution is created. # converted to three address; and that an appropriate substitution is created.
# Maybe at some point we'll normalise DBG_INSTR_REFs on output, but until then, # Maybe at some point we'll normalise DBG_INSTR_REFs on output, but until then,
# lets not. # lets not.
# #
# CHECK: debugValueSubstitutions: # CHECK: debugValueSubstitutions:
# CHECK-NEXT: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 } # CHECK-NEXT: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 }
# #
# CHECK: LEA64_32r # CHECK: LEA64_32r
# CHECK-SAME: debug-instr-number 2 # CHECK-SAME: debug-instr-number 2
# #
# CHECK: DBG_INSTR_REF 1, 0 # CHECK: DBG_INSTR_REF dbg-instr-ref(1, 0)
--- ---
name: test1 name: test1
alignment: 16 alignment: 16
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gr32 } - { id: 0, class: gr32 }
- { id: 1, class: gr32 } - { id: 1, class: gr32 }
- { id: 2, class: gr32 } - { id: 2, class: gr32 }
liveins: liveins:
- { reg: '$edi', virtual-reg: '%0' } - { reg: '$edi', virtual-reg: '%0' }
frameInfo: frameInfo:
maxAlignment: 1 maxAlignment: 1
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
bb.0: bb.0:
liveins: $edi liveins: $edi
%0:gr32 = COPY killed $edi %0:gr32 = COPY killed $edi
%1:gr32 = SHL32ri killed %0, 5, implicit-def dead $eflags %1:gr32 = SHL32ri killed %0, 5, implicit-def dead $eflags
%2:gr32 = ADD32ri8_DB killed %1, 3, implicit-def dead $eflags, debug-instr-number 1 %2:gr32 = ADD32ri8_DB killed %1, 3, implicit-def dead $eflags, debug-instr-number 1
DBG_INSTR_REF 1, 0 DBG_INSTR_REF dbg-instr-ref(1, 0)
$eax = COPY killed %2 $eax = COPY killed %2
RET 0, killed $eax RET 0, killed $eax
... ...

llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir

Show First 20 Lines • Show All 136 Lines • ▼ Show 20 Lines bb.0.entry:
frame-setup SEH_StackAlloc 4 frame-setup SEH_StackAlloc 4
frame-setup SEH_EndPrologue frame-setup SEH_EndPrologue
renamable $eax = MOV32rm $ebp, 1, $noreg, 8, $noreg, debug-location !40 :: (dereferenceable load (s32) from %ir.x.addr) renamable $eax = MOV32rm $ebp, 1, $noreg, 8, $noreg, debug-location !40 :: (dereferenceable load (s32) from %ir.x.addr)
MOV32mr $ebp, 1, $noreg, -4, $noreg, $esp, debug-location !41 :: (store (s32) into %ir.saved_stack) MOV32mr $ebp, 1, $noreg, -4, $noreg, $esp, debug-location !41 :: (store (s32) into %ir.saved_stack)
renamable $eax = SHL32ri killed renamable $eax, 2, implicit-def dead $eflags, debug-location !41 renamable $eax = SHL32ri killed renamable $eax, 2, implicit-def dead $eflags, debug-location !41
CALLpcrel32 &_chkstk, implicit $esp, implicit $ssp, implicit $eax, implicit $esp, implicit-def dead $eax, implicit-def $esp, implicit-def dead $eflags, debug-instr-number 2, debug-location !41 CALLpcrel32 &_chkstk, implicit $esp, implicit $ssp, implicit $eax, implicit $esp, implicit-def dead $eax, implicit-def $esp, implicit-def dead $eflags, debug-instr-number 2, debug-location !41
$ebx = MOV32rr $esp, debug-location !41 $ebx = MOV32rr $esp, debug-location !41
$eax = MOV32ri 0 $eax = MOV32ri 0
DBG_INSTR_REF 2, 6, !42, !DIExpression(DW_OP_deref), debug-location !46 DBG_INSTR_REF !42, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_deref), dbg-instr-ref(2, 6), debug-location !46
; CHECK-LABEL: DBG_INSTR_REF 2, 6 ; CHECK-LABEL: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 6)
; CHECK: DBG_VALUE $esp ; CHECK: DBG_VALUE_LIST {{.+}}, $esp
;; Variable value is $esp / $ebx, will be based on $esp initially. We'll now ;; Variable value is $esp / $ebx, will be based on $esp initially. We'll now
;; allocate more stack space, and several things should happen: ;; allocate more stack space, and several things should happen:
;; * We recognise it as modifying $esp, and move the variable location to ;; * We recognise it as modifying $esp, and move the variable location to
;; be based on $ebx, ;; be based on $ebx,
;; * We recognise the modified $esp as a new value, and if we assign it to ;; * We recognise the modified $esp as a new value, and if we assign it to
;; the variable location, will base the variable on $esp, ;; the variable location, will base the variable on $esp,
;; * Clobbering the second modified $esp won't re-locate the variable to ;; * Clobbering the second modified $esp won't re-locate the variable to
;; $ebx, which comes from the first modified $esp. ;; $ebx, which comes from the first modified $esp.
CALLpcrel32 &_chkstk, implicit $esp, implicit $ssp, implicit $eax, implicit $esp, implicit-def dead $eax, implicit-def $esp, implicit-def dead $eflags, debug-instr-number 3, debug-location !41 CALLpcrel32 &_chkstk, implicit $esp, implicit $ssp, implicit $eax, implicit $esp, implicit-def dead $eax, implicit-def $esp, implicit-def dead $eflags, debug-instr-number 3, debug-location !41
; CHECK-NEXT: CALLpcrel32 ; CHECK-NEXT: CALLpcrel32
; CHECK-NEXT: DBG_VALUE $ebx ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $ebx
DBG_INSTR_REF 3, 6, !42, !DIExpression(DW_OP_deref), debug-location !46 DBG_INSTR_REF !42, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_deref), dbg-instr-ref(3, 6), debug-location !46
; CHECK-NEXT: DBG_INSTR_REF 3, 6 ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 6)
; CHECK-NEXT: DBG_VALUE $esp ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $esp
$esp = ADD32ri killed $esp, 0, implicit-def dead $eflags $esp = ADD32ri killed $esp, 0, implicit-def dead $eflags
; CHECK-NEXT: ADD32ri ; CHECK-NEXT: ADD32ri
DBG_INSTR_REF 3, 6, !42, !DIExpression(DW_OP_deref), debug-location !46 DBG_INSTR_REF !42, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_deref), dbg-instr-ref(3, 6), debug-location !46
; CHECK-NEXT: DBG_INSTR_REF 3, 6 ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 6)
; CHECK-NEXT: DBG_VALUE $noreg ; CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $noreg
$esp = MOV32rr $ebp, debug-location !49 $esp = MOV32rr $ebp, debug-location !49
$ebp = frame-destroy POP32r implicit-def $esp, implicit $esp, debug-location !49 $ebp = frame-destroy POP32r implicit-def $esp, implicit $esp, debug-location !49
RET32 debug-location !49 RET32 debug-location !49
... ...

llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
body: | body: |
bb.0._ZN4llvm11raw_ostreamlsEPKc.exit2752: bb.0._ZN4llvm11raw_ostreamlsEPKc.exit2752:
successors: %bb.1(0x30000000), %bb.2(0x50000000) successors: %bb.1(0x30000000), %bb.2(0x50000000)
%1:gr64 = IMPLICIT_DEF %1:gr64 = IMPLICIT_DEF
%0:gr64 = MOV64rm killed %1, 1, $noreg, 0, $noreg, debug-location !7 :: (load (s64) from `i8** undef`) %0:gr64 = MOV64rm killed %1, 1, $noreg, 0, $noreg, debug-location !7 :: (load (s64) from `i8** undef`)
%2:gr32 = COPY %0.sub_32bit, debug-location !7 %2:gr32 = COPY %0.sub_32bit, debug-location !7
%3:gr32 = SUB32rm %2, %0, 1, $noreg, 0, $noreg, implicit-def $eflags, debug-instr-number 1, debug-location !7 :: (load (s32) from %ir._M_start.i2756, align 8) %3:gr32 = SUB32rm %2, %0, 1, $noreg, 0, $noreg, implicit-def $eflags, debug-instr-number 1, debug-location !7 :: (load (s32) from %ir._M_start.i2756, align 8)
DBG_INSTR_REF 1, 0, !8, !DIExpression(), debug-location !7 DBG_INSTR_REF !8, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !7
JCC_1 %bb.2, 5, implicit $eflags, debug-location !7 JCC_1 %bb.2, 5, implicit $eflags, debug-location !7
JMP_1 %bb.1, debug-location !7 JMP_1 %bb.1, debug-location !7
bb.1.for.cond.cleanup376: bb.1.for.cond.cleanup376:
RET 0 RET 0
bb.2.for.body377: bb.2.for.body377:
RET 0 RET 0
... ...

llvm/test/DebugInfo/MIR/X86/instr-ref-join-def-vphi.mir

# RUN: llc -run-pass=livedebugvalues %s -o - -experimental-debug-variable-locations | FileCheck %s --check-prefixes=CHECK # RUN: llc -run-pass=livedebugvalues %s -o - -experimental-debug-variable-locations | FileCheck %s --check-prefixes=CHECK
# Test that we do not drop debug values when joining a VPHI and a Def that use # Test that we do not drop debug values when joining a VPHI and a Def that use
# the same value. # the same value.
# In this test case, the live out value for "a" from bb.4 is a VPHI with a # In this test case, the live out value for "a" from bb.4 is a VPHI with a
# defined value, the value live-in register $esi at bb.3. In bb.5, we also have # defined value, the value live-in register $esi at bb.3. In bb.5, we also have
# a DBG_INSTR_REF that explicitly defines "a" as holding that same value. When # a DBG_INSTR_REF that explicitly defines "a" as holding that same value. When
# joining these values to determine the live-in value of "a" at bb.6, we should # joining these values to determine the live-in value of "a" at bb.6, we should
# recognize that these values are identical and produce a valid live-in debug # recognize that these values are identical and produce a valid live-in debug
# value. # value.
# CHECK: ![[VAR:[0-9]+]] = !DILocalVariable(name: "a" # CHECK: ![[VAR:[0-9]+]] = !DILocalVariable(name: "a"
# CHECK-LABEL: bb.6 # CHECK-LABEL: bb.6
# CHECK: DBG_VALUE $esi, $noreg, ![[VAR]], !DIExpression() # CHECK: DBG_VALUE_LIST ![[VAR]], !DIExpression(DW_OP_LLVM_arg, 0), $esi
--- | --- |
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
; Function Attrs: mustprogress uwtable ; Function Attrs: mustprogress uwtable
define dso_local noundef i32 @"?foo@@YAHH@Z"(i32 noundef %0) local_unnamed_addr #0 !dbg !8 { define dso_local noundef i32 @"?foo@@YAHH@Z"(i32 noundef %0) local_unnamed_addr #0 !dbg !8 {
call void @llvm.dbg.value(metadata i32 %0, metadata !14, metadata !DIExpression()), !dbg !16 call void @llvm.dbg.value(metadata i32 %0, metadata !14, metadata !DIExpression()), !dbg !16
▲ Show 20 Lines • Show All 168 Lines • ▼ Show 20 Lines bb.3 (%ir-block.13, align 16):
JCC_1 %bb.4, 14, implicit $eflags, debug-location !26 JCC_1 %bb.4, 14, implicit $eflags, debug-location !26
bb.1 (%ir-block.3): bb.1 (%ir-block.3):
successors: %bb.2(0x30000000), %bb.3(0x50000000) successors: %bb.2(0x30000000), %bb.3(0x50000000)
liveins: $edi, $esi liveins: $edi, $esi
DBG_PHI $esi, 3 DBG_PHI $esi, 3
DBG_PHI $edi, 2 DBG_PHI $edi, 2
DBG_INSTR_REF 3, 0, !14, !DIExpression(), debug-location !16 DBG_INSTR_REF !14, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(3, 0), debug-location !16
CALL64pcrel32 @"?bar@@YAHXZ", csr_win64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !19 CALL64pcrel32 @"?bar@@YAHXZ", csr_win64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !19
renamable $edi = nsw SUB32rr killed renamable $edi, killed renamable $eax, implicit-def dead $eflags, debug-instr-number 1, debug-location !19 renamable $edi = nsw SUB32rr killed renamable $edi, killed renamable $eax, implicit-def dead $eflags, debug-instr-number 1, debug-location !19
renamable $eax = IMUL32rri renamable $edi, -1431655765, implicit-def dead $eflags, debug-location !21 renamable $eax = IMUL32rri renamable $edi, -1431655765, implicit-def dead $eflags, debug-location !21
renamable $eax = ADD32ri killed renamable $eax, 715827882, implicit-def dead $eflags, debug-location !21 renamable $eax = ADD32ri killed renamable $eax, 715827882, implicit-def dead $eflags, debug-location !21
CMP32ri killed renamable $eax, 1431655764, implicit-def $eflags, debug-location !21 CMP32ri killed renamable $eax, 1431655764, implicit-def $eflags, debug-location !21
JCC_1 %bb.3, 7, implicit $eflags, debug-location !21 JCC_1 %bb.3, 7, implicit $eflags, debug-location !21
bb.2 (%ir-block.10): bb.2 (%ir-block.10):
successors: %bb.3(0x80000000) successors: %bb.3(0x80000000)
liveins: $edi, $esi liveins: $edi, $esi
CALL64pcrel32 @"?bar@@YAHXZ", csr_win64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !22 CALL64pcrel32 @"?bar@@YAHXZ", csr_win64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !22
renamable $esi = nsw ADD32rr killed renamable $esi, killed renamable $eax, implicit-def dead $eflags, debug-instr-number 4, debug-location !22 renamable $esi = nsw ADD32rr killed renamable $esi, killed renamable $eax, implicit-def dead $eflags, debug-instr-number 4, debug-location !22
DBG_INSTR_REF 4, 0, !14, !DIExpression(), debug-location !16 DBG_INSTR_REF !14, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(4, 0), debug-location !16
JMP_1 %bb.3 JMP_1 %bb.3
bb.4 (%ir-block.16): bb.4 (%ir-block.16):
successors: %bb.5(0x40000000), %bb.6(0x40000000) successors: %bb.5(0x40000000), %bb.6(0x40000000)
liveins: $edi, $esi liveins: $edi, $esi
TEST8ri renamable $dil, 1, implicit-def $eflags, implicit killed $edi, debug-location !30 TEST8ri renamable $dil, 1, implicit-def $eflags, implicit killed $edi, debug-location !30
JCC_1 %bb.6, 5, implicit $eflags, debug-location !30 JCC_1 %bb.6, 5, implicit $eflags, debug-location !30
bb.5 (%ir-block.19): bb.5 (%ir-block.19):
successors: %bb.6(0x80000000) successors: %bb.6(0x80000000)
liveins: $esi liveins: $esi
CALL64pcrel32 @"?bar@@YAHXZ", csr_win64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !31 CALL64pcrel32 @"?bar@@YAHXZ", csr_win64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !31
DBG_INSTR_REF 5, 0, !14, !DIExpression(), debug-location !16 DBG_INSTR_REF !14, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(5, 0), debug-location !16
bb.6 (%ir-block.22): bb.6 (%ir-block.22):
liveins: $esi liveins: $esi
$eax = MOV32rr killed $esi, debug-location !35 $eax = MOV32rr killed $esi, debug-location !35
SEH_Epilogue debug-location !35 SEH_Epilogue debug-location !35
$rsp = frame-destroy ADD64ri8 $rsp, 40, implicit-def dead $eflags, debug-location !35 $rsp = frame-destroy ADD64ri8 $rsp, 40, implicit-def dead $eflags, debug-location !35
$rdi = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !35 $rdi = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !35
$rsi = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !35 $rsi = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !35
RET64 $eax, debug-location !35 RET64 $eax, debug-location !35
... ...

llvm/test/DebugInfo/X86/dbg-value-arg-movement.ll

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; CHECK-LABEL: bb.1.next ; CHECK-LABEL: bb.1.next
; Correctly place dbg.value in the 'next' block. ; Correctly place dbg.value in the 'next' block.
; CHECK: DBG_VALUE [[ARGREG]], $noreg, [[XYZVAR]] ; CHECK: DBG_VALUE [[ARGREG]], $noreg, [[XYZVAR]]
; INSTRREF-LABEL: body ; INSTRREF-LABEL: body
; INSTRREF: DBG_PHI $edi, 1 ; INSTRREF: DBG_PHI $edi, 1
; INSTRREF: DBG_VALUE $edi, $noreg, [[BAZVAR]] ; INSTRREF: DBG_VALUE $edi, $noreg, [[BAZVAR]]
; INSTRREF-LABEL: bb.1.next ; INSTRREF-LABEL: bb.1.next
; INSTRREF: DBG_INSTR_REF 1, 0, [[XYZVAR]], ; INSTRREF: DBG_INSTR_REF [[XYZVAR]], {{.+}}, dbg-instr-ref(1, 0)
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
declare i32 @ext() declare i32 @ext()
define dso_local i32 @bar(i32, i32) local_unnamed_addr !dbg !7 { define dso_local i32 @bar(i32, i32) local_unnamed_addr !dbg !7 {
%3 = srem i32 %1, %0, !dbg !15 %3 = srem i32 %1, %0, !dbg !15
▲ Show 20 Lines • Show All 42 Lines • Show Last 20 Lines

llvm/test/DebugInfo/X86/dbg-value-funcarg.ll

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; INSTRREF-LABEL: name: foo_local ; INSTRREF-LABEL: name: foo_local
; INSTRREF-NOT: DBG_ ; INSTRREF-NOT: DBG_
; INSTRREF: DBG_PHI $edi, 1 ; INSTRREF: DBG_PHI $edi, 1
; INSTRREF: DBG_VALUE $edi, $noreg, ![[T1A]], !DIExpression(), ; INSTRREF: DBG_VALUE $edi, $noreg, ![[T1A]], !DIExpression(),
; INSTRREF-NEXT: %0:gr32 = COPY $edi ; INSTRREF-NEXT: %0:gr32 = COPY $edi
; INSTRREF-NEXT: DBG_VALUE 123, $noreg, ![[LOCAL]], !DIExpression(), ; INSTRREF-NEXT: DBG_VALUE 123, $noreg, ![[LOCAL]], !DIExpression(),
; INSTRREF: CALL64pcrel32 @bar, ; INSTRREF: CALL64pcrel32 @bar,
; INSTRREF-NEXT: ADJCALLSTACKUP64 ; INSTRREF-NEXT: ADJCALLSTACKUP64
; INSTRREF: DBG_INSTR_REF 1, 0, ![[LOCAL]], !DIExpression(), ; INSTRREF: DBG_INSTR_REF ![[LOCAL]], !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0),
; INSTRREF-NOT: DBG_ ; INSTRREF-NOT: DBG_
; INSTRREF: TCRETURNdi64 @bar, ; INSTRREF: TCRETURNdi64 @bar,
entry: entry:
call void @llvm.dbg.value(metadata i32 %t1a, metadata !12, metadata !DIExpression()), !dbg !14 call void @llvm.dbg.value(metadata i32 %t1a, metadata !12, metadata !DIExpression()), !dbg !14
call void @llvm.dbg.value(metadata i32 123, metadata !13, metadata !DIExpression()), !dbg !15 call void @llvm.dbg.value(metadata i32 123, metadata !13, metadata !DIExpression()), !dbg !15
tail call void @bar(i32 123) #3, !dbg !16 tail call void @bar(i32 123) #3, !dbg !16
call void @llvm.dbg.value(metadata i32 %t1a, metadata !13, metadata !DIExpression()), !dbg !15 call void @llvm.dbg.value(metadata i32 %t1a, metadata !13, metadata !DIExpression()), !dbg !15
Show All 18 Lines
; CHECK: TCRETURNdi64 @bar, ; CHECK: TCRETURNdi64 @bar,
; INSTRREF-LABEL: name: foo_other_param ; INSTRREF-LABEL: name: foo_other_param
; INSTRREF: DBG_PHI $edi, 1 ; INSTRREF: DBG_PHI $edi, 1
; INSTRREF: DBG_VALUE $edi, $noreg, ![[T2A]], !DIExpression(), ; INSTRREF: DBG_VALUE $edi, $noreg, ![[T2A]], !DIExpression(),
; INSTRREF: DBG_VALUE $esi, $noreg, ![[T2B]], !DIExpression(), ; INSTRREF: DBG_VALUE $esi, $noreg, ![[T2B]], !DIExpression(),
; INSTRREF: CALL64pcrel32 @bar, ; INSTRREF: CALL64pcrel32 @bar,
; INSTRREF: DBG_VALUE 123, $noreg, ![[T2B]], !DIExpression(), ; INSTRREF: DBG_VALUE 123, $noreg, ![[T2B]], !DIExpression(),
; INSTRREF: CALL64pcrel32 @bar, ; INSTRREF: CALL64pcrel32 @bar,
; INSTRREF: DBG_INSTR_REF 1, 0, ![[T2B]], !DIExpression(), ; INSTRREF: DBG_INSTR_REF ![[T2B]], !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0),
; INSTRREF: TCRETURNdi64 @bar, ; INSTRREF: TCRETURNdi64 @bar,
entry: entry:
call void @llvm.dbg.value(metadata i32 %t2a, metadata !23, metadata !DIExpression()), !dbg !25 call void @llvm.dbg.value(metadata i32 %t2a, metadata !23, metadata !DIExpression()), !dbg !25
call void @llvm.dbg.value(metadata i32 %t2b, metadata !24, metadata !DIExpression()), !dbg !26 call void @llvm.dbg.value(metadata i32 %t2b, metadata !24, metadata !DIExpression()), !dbg !26
tail call void @bar(i32 %t2b) #3, !dbg !27 tail call void @bar(i32 %t2b) #3, !dbg !27
call void @llvm.dbg.value(metadata i32 123, metadata !24, metadata !DIExpression()), !dbg !26 call void @llvm.dbg.value(metadata i32 123, metadata !24, metadata !DIExpression()), !dbg !26
tail call void @bar(i32 123) #3, !dbg !28 tail call void @bar(i32 123) #3, !dbg !28
Show All 12 Lines
; CHECK: DBG_VALUE 123, $noreg, ![[T3A]], !DIExpression(), ; CHECK: DBG_VALUE 123, $noreg, ![[T3A]], !DIExpression(),
; CHECK: CALL64pcrel32 @bar, ; CHECK: CALL64pcrel32 @bar,
; CHECK: DBG_VALUE %0, $noreg, ![[T3A]], !DIExpression(), ; CHECK: DBG_VALUE %0, $noreg, ![[T3A]], !DIExpression(),
; CHECK: TCRETURNdi64 @bar, ; CHECK: TCRETURNdi64 @bar,
; INSTRREF-LABEL: name: foo_same_param ; INSTRREF-LABEL: name: foo_same_param
; INSTRREF: DBG_PHI $edi, 1 ; INSTRREF: DBG_PHI $edi, 1
; INSTRREF: DBG_VALUE $edi, $noreg, ![[T3A]], !DIExpression(), ; INSTRREF: DBG_VALUE $edi, $noreg, ![[T3A]], !DIExpression(),
; INSTRREF: CALL64pcrel32 @bar, ; INSTRREF: CALL64pcrel32 @bar,
; INSTRREF: DBG_INSTR_REF 1, 0, ![[TMP]], !DIExpression(), ; INSTRREF: DBG_INSTR_REF ![[TMP]], !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0),
; INSTRREF: DBG_VALUE 123, $noreg, ![[T3A]], !DIExpression(), ; INSTRREF: DBG_VALUE 123, $noreg, ![[T3A]], !DIExpression(),
; INSTRREF: CALL64pcrel32 @bar, ; INSTRREF: CALL64pcrel32 @bar,
; INSTRREF: DBG_INSTR_REF 1, 0, ![[T3A]], !DIExpression(), ; INSTRREF: DBG_INSTR_REF ![[T3A]], !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0),
; INSTRREF: TCRETURNdi64 @bar, ; INSTRREF: TCRETURNdi64 @bar,
entry: entry:
call void @llvm.dbg.value(metadata i32 %t3a, metadata !33, metadata !DIExpression()), !dbg !35 call void @llvm.dbg.value(metadata i32 %t3a, metadata !33, metadata !DIExpression()), !dbg !35
tail call void @bar(i32 %t3a) #3, !dbg !36 tail call void @bar(i32 %t3a) #3, !dbg !36
call void @llvm.dbg.value(metadata i32 %t3a, metadata !34, metadata !DIExpression()), !dbg !37 call void @llvm.dbg.value(metadata i32 %t3a, metadata !34, metadata !DIExpression()), !dbg !37
call void @llvm.dbg.value(metadata i32 123, metadata !33, metadata !DIExpression()), !dbg !35 call void @llvm.dbg.value(metadata i32 123, metadata !33, metadata !DIExpression()), !dbg !35
tail call void @bar(i32 123) #3, !dbg !38 tail call void @bar(i32 123) #3, !dbg !38
call void @llvm.dbg.value(metadata i32 %t3a, metadata !33, metadata !DIExpression()), !dbg !35 call void @llvm.dbg.value(metadata i32 %t3a, metadata !33, metadata !DIExpression()), !dbg !35
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/test/DebugInfo/X86/dbg-value-funcarg2.ll

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; CHECK-NOT: DBG_VALUE ; CHECK-NOT: DBG_VALUE
; CHECK-DAG: DBG_VALUE %[[R2]], $noreg, ![[S1]], !DIExpression(DW_OP_LLVM_fragment, 0, 64) ; CHECK-DAG: DBG_VALUE %[[R2]], $noreg, ![[S1]], !DIExpression(DW_OP_LLVM_fragment, 0, 64)
; CHECK-DAG: DBG_VALUE %[[R1]], $noreg, ![[S1]], !DIExpression(DW_OP_LLVM_fragment, 64, 64) ; CHECK-DAG: DBG_VALUE %[[R1]], $noreg, ![[S1]], !DIExpression(DW_OP_LLVM_fragment, 64, 64)
;; In instruction referencing mode, we should refer to the instruction number ;; In instruction referencing mode, we should refer to the instruction number
;; of the earlier DBG_PHIs. ;; of the earlier DBG_PHIs.
; INSTRREF: ADJCALLSTACKUP ; INSTRREF: ADJCALLSTACKUP
; INSTRREF-NOT: DBG_ ; INSTRREF-NOT: DBG_
; INSTRREF-DAG: DBG_INSTR_REF 1, 0, ![[S1]], !DIExpression(DW_OP_LLVM_fragment, 0, 64) ; INSTRREF-DAG: DBG_INSTR_REF ![[S1]], !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 0, 64), dbg-instr-ref(1, 0)
; INSTRREF-DAG: DBG_INSTR_REF 2, 0, ![[S1]], !DIExpression(DW_OP_LLVM_fragment, 64, 64) ; INSTRREF-DAG: DBG_INSTR_REF ![[S1]], !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(2, 0)
; And then no more DBG_ instructions before the add. ; And then no more DBG_ instructions before the add.
; COMMON-NOT: DBG_ ; COMMON-NOT: DBG_
; COMMON: ADD32rr ; COMMON: ADD32rr
entry: entry:
%tmp.sroa.0 = alloca i64, align 8 %tmp.sroa.0 = alloca i64, align 8
%tmp.sroa.4 = alloca i64, align 8 %tmp.sroa.4 = alloca i64, align 8
▲ Show 20 Lines • Show All 67 Lines • Show Last 20 Lines

llvm/test/DebugInfo/X86/dbg-value-funcarg4.ll

; RUN: llc -mtriple=x86_64-unknown-linux-gnu -start-after=codegenprepare -stop-before=finalize-isel -o - %s -experimental-debug-variable-locations=true | FileCheck %s --implicit-check-not=DBG_PHI ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -start-after=codegenprepare -stop-before=finalize-isel -o - %s -experimental-debug-variable-locations=true | FileCheck %s --implicit-check-not=DBG_PHI
; Test that for multiple dbg.values referring to the same argument, we emit a ; Test that for multiple dbg.values referring to the same argument, we emit a
; single DBG_PHI and refer to it twice. (Using more than one DBG_PHI is fine, ; single DBG_PHI and refer to it twice. (Using more than one DBG_PHI is fine,
; but inefficient). ; but inefficient).
; CHECK-DAG: ![[LOCAL:.*]] = !DILocalVariable(name: "local" ; CHECK-DAG: ![[LOCAL:.*]] = !DILocalVariable(name: "local"
; CHECK-DAG: ![[LOCAL2:.*]] = !DILocalVariable(name: "local2" ; CHECK-DAG: ![[LOCAL2:.*]] = !DILocalVariable(name: "local2"
; CHECK: DBG_PHI $edi, 1 ; CHECK: DBG_PHI $edi, 1
; CHECK: DBG_INSTR_REF 1, 0, ![[LOCAL]], !DIExpression(), ; CHECK: DBG_INSTR_REF ![[LOCAL]], !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0)
; CHECK: DBG_INSTR_REF 1, 0, ![[LOCAL2]], !DIExpression(), ; CHECK: DBG_INSTR_REF ![[LOCAL2]], !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0)
declare void @bar(i32) declare void @bar(i32)
declare void @llvm.dbg.value(metadata, metadata, metadata) declare void @llvm.dbg.value(metadata, metadata, metadata)
define dso_local void @foo_local(i32 %t1a) local_unnamed_addr !dbg !7 { define dso_local void @foo_local(i32 %t1a) local_unnamed_addr !dbg !7 {
entry: entry:
tail call void @bar(i32 %t1a) #3, !dbg !17 tail call void @bar(i32 %t1a) #3, !dbg !17
%bees = add i32 %t1a, 3 %bees = add i32 %t1a, 3
Show All 30 Lines

llvm/test/DebugInfo/X86/dbg-value-list-selectiondag-salvage.ll

; RUN: llc %s -start-after=codegenprepare -stop-before=finalize-isel -o - | FileCheck %s ; RUN: llc %s -start-after=codegenprepare -stop-before=finalize-isel -experimental-debug-variable-locations=true -o - | FileCheck %s
;; Generated from clang -O2 -emit-llvm -S -g reduce.c -o - ;; Generated from clang -O2 -emit-llvm -S -g reduce.c -o -
;; $ cat reduce.c ;; $ cat reduce.c
;; struct { ;; struct {
;; int a; ;; int a;
;; } * b; ;; } * b;
;; int c; ;; int c;
;; void d() { ;; void d() {
;; int *e = &b->a - 1; // XXX ;; int *e = &b->a - 1; // XXX
;; c = *e; ;; c = *e;
;; } ;; }
;; ;;
;; The line marked XXX becomes a load and gep in IR. We have a variadic ;; The line marked XXX becomes a load and gep in IR. We have a variadic
;; dbg.value using the gep, but we lose that gep in SelectionDAG. Ensure that ;; dbg.value using the gep, but we lose that gep in SelectionDAG. Ensure that
;; we salvage the value. ;; we salvage the value.
; CHECK: [[E_REG:%[0-9]+]]{{.+}} = MOV{{.+}} @b ; CHECK: {{%[0-9]+.+}} = MOV{{.+}} @b, {{.+}}, debug-instr-number [[INSTR_NUM:[0-9]+]]
; CHECK: DBG_VALUE_LIST {{.*}}, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 4, DW_OP_minus, DW_OP_stack_value), [[E_REG]], debug-location ; CHECK: DBG_INSTR_REF {{.*}}, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 4, DW_OP_minus, DW_OP_stack_value), dbg-instr-ref([[INSTR_NUM]], 0), debug-location
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
%struct.anon = type { i32 } %struct.anon = type { i32 }
@b = dso_local local_unnamed_addr global %struct.anon* null, align 8, !dbg !0 @b = dso_local local_unnamed_addr global %struct.anon* null, align 8, !dbg !0
@c = dso_local local_unnamed_addr global i32 0, align 4, !dbg !6 @c = dso_local local_unnamed_addr global i32 0, align 4, !dbg !6
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

llvm/test/DebugInfo/X86/debug_value_list_selectiondag.ll

; RUN: llc %s -start-after=codegenprepare -stop-before=finalize-isel -o - | FileCheck --check-prefixes=CHECK,DAG %s ; RUN: llc %s -start-after=codegenprepare -stop-before=finalize-isel -experimental-debug-variable-locations=false -o - | FileCheck --check-prefixes=CHECK,DAG %s
; RUN: llc %s -fast-isel=true -start-after=codegenprepare -stop-before=finalize-isel -o - | FileCheck --check-prefixes=CHECK,FAST %s ; RUN: llc %s -fast-isel=true -start-after=codegenprepare -stop-before=finalize-isel -experimental-debug-variable-locations=false -o - | FileCheck --check-prefixes=CHECK,FAST %s
; RUN: llc %s -global-isel=true -start-after=codegenprepare -stop-before=finalize-isel -o - | FileCheck --check-prefixes=CHECK,GLOBAL %s ; RUN: llc %s -global-isel=true -start-after=codegenprepare -stop-before=finalize-isel -experimental-debug-variable-locations=false -o - | FileCheck --check-prefixes=CHECK,GLOBAL %s
;; Test that a dbg.value that uses a DIArgList is correctly converted to a ;; Test that a dbg.value that uses a DIArgList is correctly converted to a
;; DBG_VALUE_LIST that uses the registers corresponding to its operands. ;; DBG_VALUE_LIST that uses the registers corresponding to its operands.
; CHECK-DAG: [[A_VAR:![0-9]+]] = !DILocalVariable(name: "a" ; CHECK-DAG: [[A_VAR:![0-9]+]] = !DILocalVariable(name: "a"
; CHECK-DAG: [[B_VAR:![0-9]+]] = !DILocalVariable(name: "b" ; CHECK-DAG: [[B_VAR:![0-9]+]] = !DILocalVariable(name: "b"
; CHECK-DAG: [[C_VAR:![0-9]+]] = !DILocalVariable(name: "c" ; CHECK-DAG: [[C_VAR:![0-9]+]] = !DILocalVariable(name: "c"
; CHECK-LABEL: bb.{{(0|1)}}.entry ; CHECK-LABEL: bb.{{(0|1)}}.entry
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

llvm/test/DebugInfo/X86/instr-ref-dbg-declare.ll

; RUN: llc %s -stop-before=finalize-isel -o - \ ; RUN: llc %s -stop-before=finalize-isel -o - \
; RUN: -experimental-debug-variable-locations=true \ ; RUN: -experimental-debug-variable-locations=true \
; RUN: | FileCheck %s ; RUN: | FileCheck %s
;; Copy of DebugInfo/COFF/types-array-advanced.ll. This features a dbg.declare ;; Copy of DebugInfo/COFF/types-array-advanced.ll. This features a dbg.declare
;; of something (dynamic alloca) that isn't an argument, causing a SDDbgValue ;; of something (dynamic alloca) that isn't an argument, causing a SDDbgValue
;; with the indirect flag set to be emitted. Test that it's preserved in ;; with the indirect flag set to be emitted. Test that it's preserved in
;; instruction referencing mode -- we don't have an IsIndirect flag on ;; instruction referencing mode -- we don't have an IsIndirect flag on
;; DBG_INSTR_REF, so it gets encoded as an additional DW_OP_deref. ;; DBG_INSTR_REF, so it gets encoded as an additional DW_OP_deref.
;; ;;
;; NB: the original test has an additional spurious DW_OP_deref in the ;; NB: the original test has an additional spurious DW_OP_deref in the
;; dbg.declare's arguments, which is preserved here, translating to two derefs. ;; dbg.declare's arguments, which is preserved here, translating to two derefs.
; CHECK: DBG_INSTR_REF 1, 2, !{{[0-9]+}}, !DIExpression(DW_OP_deref, DW_OP_deref) ; CHECK: DBG_INSTR_REF !{{[0-9]+}}, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_deref, DW_OP_deref), dbg-instr-ref(1, 2)
source_filename = "test/DebugInfo/COFF/types-array-advanced.ll" source_filename = "test/DebugInfo/COFF/types-array-advanced.ll"
target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
target triple = "i686-pc-windows-msvc18.0.31101" target triple = "i686-pc-windows-msvc18.0.31101"
%struct.incomplete_struct = type { i32 } %struct.incomplete_struct = type { i32 }
@"\01?multi_dim_arr@@3PAY146DA" = global [2 x [5 x [7 x i8]]] zeroinitializer, align 1, !dbg !0 @"\01?multi_dim_arr@@3PAY146DA" = global [2 x [5 x [7 x i8]]] zeroinitializer, align 1, !dbg !0
▲ Show 20 Lines • Show All 90 Lines • Show Last 20 Lines

llvm/test/DebugInfo/X86/instr-ref-dyn-alloca-win32.ll

; RUN: llc %s -o - -stop-after=machine-sink \ ; RUN: llc %s -o - -stop-after=machine-sink \
; RUN: -experimental-debug-variable-locations=true \ ; RUN: -experimental-debug-variable-locations=true \
; RUN: | FileCheck %s --check-prefixes=DYN_LABEL ; RUN: | FileCheck %s --check-prefixes=DYN_LABEL
; RUN: llc %s -o - -stop-before=phi-node-elimination \ ; RUN: llc %s -o - -stop-before=phi-node-elimination \
; RUN: -experimental-debug-variable-locations=true \ ; RUN: -experimental-debug-variable-locations=true \
; RUN: | FileCheck %s --check-prefixes=DYN_LOWERED ; RUN: | FileCheck %s --check-prefixes=DYN_LOWERED
;; This is a copy of DebugInfo/COFF/types-array-advanced.ll, checking that ;; This is a copy of DebugInfo/COFF/types-array-advanced.ll, checking that
;; DYN_ALLOCAs correctly have instruction references updated. This is compiled ;; DYN_ALLOCAs correctly have instruction references updated. This is compiled
;; from LLVM-IR because the "hasDynAlloca" flag isn't serialised to MIR, for ;; from LLVM-IR because the "hasDynAlloca" flag isn't serialised to MIR, for
;; complicated reasons, that means we can't store as MIR. ;; complicated reasons, that means we can't store as MIR.
;; The alloca instruction should be labelled, and we should refer to operand 2, ;; The alloca instruction should be labelled, and we should refer to operand 2,
;; which happens to be a def of $esp ;; which happens to be a def of $esp
; DYN_LABEL: DYN_ALLOCA_32 {{.*}} debug-instr-number 1, ; DYN_LABEL: DYN_ALLOCA_32 {{.*}} debug-instr-number 1,
; DYN_LABEL: DBG_INSTR_REF 1, 2 ; DYN_LABEL: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 2)
;; Once lowered, on win32 _chkstk alters the stack pointer. We should label the ;; Once lowered, on win32 _chkstk alters the stack pointer. We should label the
;; call and it's SP operand, plus check for a value substitution. ;; call and it's SP operand, plus check for a value substitution.
; DYN_LOWERED: debugValueSubstitutions: ; DYN_LOWERED: debugValueSubstitutions:
; DYN_LOWERED-NEXT: - { srcinst: 1, srcop: 2, dstinst: 2, dstop: 6, subreg: 0 } ; DYN_LOWERED-NEXT: - { srcinst: 1, srcop: 2, dstinst: 2, dstop: 6, subreg: 0 }
;; Test that it's operand six, and labelled. ;; Test that it's operand six, and labelled.
; DYN_LOWERED: CALLpcrel32 &_chkstk, implicit $esp, implicit $ssp, ; DYN_LOWERED: CALLpcrel32 &_chkstk, implicit $esp, implicit $ssp,
; DYN_LOWERED-SAME: implicit killed $eax, implicit $esp, implicit-def dead $eax, ; DYN_LOWERED-SAME: implicit killed $eax, implicit $esp, implicit-def dead $eax,
▲ Show 20 Lines • Show All 99 Lines • Show Last 20 Lines

llvm/test/DebugInfo/X86/instr-ref-ir-reg-read.ll

; RUN: llc %s -start-after=codegenprepare -stop-before=finalize-isel \ ; RUN: llc %s -start-after=codegenprepare -stop-before=finalize-isel \
; RUN: -experimental-debug-variable-locations=true -o - \ ; RUN: -experimental-debug-variable-locations=true -o - \
; RUN: | FileCheck %s ; RUN: | FileCheck %s
; Test that the given input doesn't crash with instrruction referencing variable ; Test that the given input doesn't crash with instrruction referencing variable
; locations. The use of llvm.read_register allows the IR to access any register ; locations. The use of llvm.read_register allows the IR to access any register
; at any point, which is unfortunate, but a use case that needs to be supported. ; at any point, which is unfortunate, but a use case that needs to be supported.
; ;
; Just examine to see that we read something from $rsp. ; Just examine to see that we read something from $rsp.
; CHECK-LABEL: bb.1.if.then: ; CHECK-LABEL: bb.1.if.then:
; CHECK: DBG_PHI $rsp, 1 ; CHECK: DBG_PHI $rsp, 1
; CHECK: DBG_INSTR_REF 1, 0 ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
source_filename = "tlb-9e7172.c" source_filename = "tlb-9e7172.c"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-cros-linux-gnu" target triple = "x86_64-cros-linux-gnu"
@c = dso_local local_unnamed_addr global i32 0, align 4, !dbg !0 @c = dso_local local_unnamed_addr global i32 0, align 4, !dbg !0
; Function Attrs: noredzone nounwind null_pointer_is_valid optsize sspstrong ; Function Attrs: noredzone nounwind null_pointer_is_valid optsize sspstrong
▲ Show 20 Lines • Show All 65 Lines • Show Last 20 Lines

llvm/test/DebugInfo/X86/instr-ref-sdag-empty-vreg.ll

; RUN: llc %s -o - -stop-before=finalize-isel \ ; RUN: llc %s -o - -stop-before=finalize-isel \
; RUN: -experimental-debug-variable-locations \ ; RUN: -experimental-debug-variable-locations \
; RUN: | FileCheck %s ; RUN: | FileCheck %s
;; The multiply by zero of %width below causes %width to become unused very late ;; The multiply by zero of %width below causes %width to become unused very late
;; in SelectionDAG. As a result, DBG_INSTR_REFs are produced that refer to a ;; in SelectionDAG. As a result, DBG_INSTR_REFs are produced that refer to a
;; vreg that is never defined, which risks a crash. Check that we don't crash, ;; vreg that is never defined, which risks a crash. Check that we don't crash,
;; and produce an empty variable location. ;; and produce an empty variable location.
; CHECK: DBG_VALUE $noreg ; CHECK: DBG_VALUE_LIST {{.+}}, $noreg
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-unknown" target triple = "x86_64-unknown-unknown"
%class.Color = type { i8 } %class.Color = type { i8 }
define hidden void @_Z14drawXZWideLineR4Vec3RK5Colorf(%class.Color* %color, float %width) local_unnamed_addr !dbg !7 { define hidden void @_Z14drawXZWideLineR4Vec3RK5Colorf(%class.Color* %color, float %width) local_unnamed_addr !dbg !7 {
cond.false.i: cond.false.i:
Show All 27 Lines

llvm/test/DebugInfo/X86/instr-ref-selectiondag.ll

Show All 31 Lines
; Note that I'm baking in an assumption of one-based ordering here. We could ; Note that I'm baking in an assumption of one-based ordering here. We could
; capture and check for the instruction numbers, we'd rely on machine verifier ; capture and check for the instruction numbers, we'd rely on machine verifier
; ensuring there were no duplicates. ; ensuring there were no duplicates.
; INSTRREF-LABEL: name: foo ; INSTRREF-LABEL: name: foo
; INSTRREF: ADD32rr ; INSTRREF: ADD32rr
; INSTRREF-SAME: debug-instr-number 1 ; INSTRREF-SAME: debug-instr-number 1
; INSTRREF-NEXT: DBG_INSTR_REF 1, 0 ; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; INSTRREF-NEXT: ADD32rr ; INSTRREF-NEXT: ADD32rr
; INSTRREF-SAME: debug-instr-number 2 ; INSTRREF-SAME: debug-instr-number 2
; INSTRREF-NEXT: DBG_INSTR_REF 2, 0 ; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
; Test that fast-isel will produce DBG_INSTR_REFs too. ; Test that fast-isel will produce DBG_INSTR_REFs too.
; FASTISEL-INSTRREF-LABEL: name: foo ; FASTISEL-INSTRREF-LABEL: name: foo
; FASTISEL-INSTRREF: ADD32rr ; FASTISEL-INSTRREF: ADD32rr
; FASTISEL-INSTRREF-SAME: debug-instr-number 1 ; FASTISEL-INSTRREF-SAME: debug-instr-number 1
; FASTISEL-INSTRREF-NEXT: DBG_INSTR_REF 1, 0 ; FASTISEL-INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; FASTISEL-INSTRREF-NEXT: ADD32rr ; FASTISEL-INSTRREF-NEXT: ADD32rr
; FASTISEL-INSTRREF-SAME: debug-instr-number 2 ; FASTISEL-INSTRREF-SAME: debug-instr-number 2
; FASTISEL-INSTRREF-NEXT: DBG_INSTR_REF 2, 0 ; FASTISEL-INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
@glob32 = global i32 0 @glob32 = global i32 0
@glob16 = global i16 0 @glob16 = global i16 0
@glob8 = global i8 0 @glob8 = global i8 0
declare void @llvm.dbg.value(metadata, metadata, metadata) declare void @llvm.dbg.value(metadata, metadata, metadata)
declare void @llvm.dbg.declare(metadata, metadata, metadata) declare void @llvm.dbg.declare(metadata, metadata, metadata)
Show All 39 Lines
; INSTRREF-NEXT: DBG_PHI $rdi, 3 ; INSTRREF-NEXT: DBG_PHI $rdi, 3
; INSTRREF-NEXT: DBG_PHI $rdi, 1 ; INSTRREF-NEXT: DBG_PHI $rdi, 1
;; Allow arguments to be specified by physreg DBG_VALUEs. ;; Allow arguments to be specified by physreg DBG_VALUEs.
; INSTRREF-NEXT: DBG_VALUE $rdi ; INSTRREF-NEXT: DBG_VALUE $rdi
;; Don't test the location of these instr-refs, only that the three non-argument ;; Don't test the location of these instr-refs, only that the three non-argument
;; dbg.values become DBG_INSTR_REFs. We previously checked that these numbers ;; dbg.values become DBG_INSTR_REFs. We previously checked that these numbers
;; get substituted, with appropriate subregister qualifiers. ;; get substituted, with appropriate subregister qualifiers.
; INSTRREF: DBG_INSTR_REF 2, 0 ; INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
; INSTRREF: DBG_INSTR_REF 4, 0 ; INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
; INSTRREF: DBG_INSTR_REF 6, 0 ; INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(6, 0)
;; In fast-isel, we get four DBG_INSTR_REFs (compared to three and one ;; In fast-isel, we get four DBG_INSTR_REFs (compared to three and one
;; DBG_VALUE with normal isel). We get additional substitutions as a result: ;; DBG_VALUE with normal isel). We get additional substitutions as a result:
; FASTISEL-INSTRREF: debugValueSubstitutions: ; FASTISEL-INSTRREF: debugValueSubstitutions:
; FASTISEL-INSTRREF-NEXT: - { srcinst: 3, srcop: 0, dstinst: 2, dstop: 0, subreg: 6 } ; FASTISEL-INSTRREF-NEXT: - { srcinst: 3, srcop: 0, dstinst: 2, dstop: 0, subreg: 6 }
; FASTISEL-INSTRREF-NEXT: - { srcinst: 5, srcop: 0, dstinst: 4, dstop: 0, subreg: 6 } ; FASTISEL-INSTRREF-NEXT: - { srcinst: 5, srcop: 0, dstinst: 4, dstop: 0, subreg: 6 }
; FASTISEL-INSTRREF-NEXT: - { srcinst: 6, srcop: 0, dstinst: 5, dstop: 0, subreg: 4 } ; FASTISEL-INSTRREF-NEXT: - { srcinst: 6, srcop: 0, dstinst: 5, dstop: 0, subreg: 4 }
; FASTISEL-INSTRREF-NEXT - { srcinst: 8, srcop: 0, dstinst: 7, dstop: 0, subreg: 6 } ; FASTISEL-INSTRREF-NEXT - { srcinst: 8, srcop: 0, dstinst: 7, dstop: 0, subreg: 6 }
; FASTISEL-INSTRREF-NEXT - { srcinst: 9, srcop: 0, dstinst: 8, dstop: 0, subreg: 4 } ; FASTISEL-INSTRREF-NEXT - { srcinst: 9, srcop: 0, dstinst: 8, dstop: 0, subreg: 4 }
; FASTISEL-INSTRREF-NEXT - { srcinst: 10, srcop: 0, dstinst: 9, dstop: 0, subreg: 1 } ; FASTISEL-INSTRREF-NEXT - { srcinst: 10, srcop: 0, dstinst: 9, dstop: 0, subreg: 1 }
;; Those substitutions are anchored against these DBG_PHIs: ;; Those substitutions are anchored against these DBG_PHIs:
; FASTISEL-INSTRREF: DBG_PHI $rdi, 7 ; FASTISEL-INSTRREF: DBG_PHI $rdi, 7
; FASTISEL-INSTRREF-NEXT: DBG_PHI $rdi, 4 ; FASTISEL-INSTRREF-NEXT: DBG_PHI $rdi, 4
; FASTISEL-INSTRREF-NEXT: DBG_PHI $rdi, 2 ; FASTISEL-INSTRREF-NEXT: DBG_PHI $rdi, 2
; FASTISEL-INSTRREF-NEXT: DBG_PHI $rdi, 1 ; FASTISEL-INSTRREF-NEXT: DBG_PHI $rdi, 1
; FASTISEL-INSTRREF: DBG_INSTR_REF 1, 0 ; FASTISEL-INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; FASTISEL-INSTRREF: DBG_INSTR_REF 3, 0 ; FASTISEL-INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
; FASTISEL-INSTRREF: DBG_INSTR_REF 6, 0 ; FASTISEL-INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(6, 0)
; FASTISEL-INSTRREF: DBG_INSTR_REF 10, 0 ; FASTISEL-INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(10, 0)
define i32 @bar(i64 %bar) !dbg !20 { define i32 @bar(i64 %bar) !dbg !20 {
entry: entry:
call void @llvm.dbg.value(metadata i64 %bar, metadata !21, metadata !DIExpression()), !dbg !22 call void @llvm.dbg.value(metadata i64 %bar, metadata !21, metadata !DIExpression()), !dbg !22
%0 = trunc i64 %bar to i32, !dbg !22 %0 = trunc i64 %bar to i32, !dbg !22
call void @llvm.dbg.value(metadata i32 %0, metadata !21, metadata !DIExpression()), !dbg !22 call void @llvm.dbg.value(metadata i32 %0, metadata !21, metadata !DIExpression()), !dbg !22
store i32 %0, i32 *@glob32, !dbg !22 store i32 %0, i32 *@glob32, !dbg !22
%1 = trunc i32 %0 to i16, !dbg !22 %1 = trunc i32 %0 to i16, !dbg !22
Show All 23 Lines
; NORMAL: %1:gr16 = COPY %0.sub_16bit ; NORMAL: %1:gr16 = COPY %0.sub_16bit
; INSTRREF-LABEL: name: baz ; INSTRREF-LABEL: name: baz
; INSTRREF: debugValueSubstitutions: ; INSTRREF: debugValueSubstitutions:
; INSTRREF-NEXT: - { srcinst: 2, srcop: 0, dstinst: 1, dstop: 6, subreg: 4 } ; INSTRREF-NEXT: - { srcinst: 2, srcop: 0, dstinst: 1, dstop: 6, subreg: 4 }
; INSTRREF: CALL64pcrel32 target-flags(x86-plt) @xyzzy, csr_64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $rax, debug-instr-number 1 ; INSTRREF: CALL64pcrel32 target-flags(x86-plt) @xyzzy, csr_64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $rax, debug-instr-number 1
; INSTRREF: DBG_INSTR_REF 2, 0 ; INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
;; Fast-isel produces the same arrangement, a DBG_INSTR_REF pointing back to ;; Fast-isel produces the same arrangement, a DBG_INSTR_REF pointing back to
;; the call instruction. However: the operand numbers are different (6 for ;; the call instruction. However: the operand numbers are different (6 for
;; normal isel, 4 for fast-isel). This isn't because of debug-info differences, ;; normal isel, 4 for fast-isel). This isn't because of debug-info differences,
;; it's because normal isel implicit-defs the stack registers, and fast-isel ;; it's because normal isel implicit-defs the stack registers, and fast-isel
;; does not. The meaning is the same. ;; does not. The meaning is the same.
; FASTISEL-INSTRREF-LABEL: name: baz ; FASTISEL-INSTRREF-LABEL: name: baz
; FASTISEL-INSTRREF: debugValueSubstitutions: ; FASTISEL-INSTRREF: debugValueSubstitutions:
; FASTISEL-INSTRREF-NEXT: - { srcinst: 2, srcop: 0, dstinst: 1, dstop: 4, subreg: 4 } ; FASTISEL-INSTRREF-NEXT: - { srcinst: 2, srcop: 0, dstinst: 1, dstop: 4, subreg: 4 }
; FASTISEL-INSTRREF: CALL64pcrel32 target-flags(x86-plt) @xyzzy, csr_64, implicit $rsp, implicit $ssp, implicit-def $rax, debug-instr-number 1 ; FASTISEL-INSTRREF: CALL64pcrel32 target-flags(x86-plt) @xyzzy, csr_64, implicit $rsp, implicit $ssp, implicit-def $rax, debug-instr-number 1
; FASTISEL-INSTRREF: DBG_INSTR_REF 2, 0 ; FASTISEL-INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
declare i64 @xyzzy() declare i64 @xyzzy()
define i32 @baz() !dbg !30 { define i32 @baz() !dbg !30 {
entry: entry:
%foo = call i64 @xyzzy(), !dbg !32 %foo = call i64 @xyzzy(), !dbg !32
br label %shoes br label %shoes
Show All 28 Lines
;; In instruction referencing mode, the "real" argument becomes a DBG_VALUE, ;; In instruction referencing mode, the "real" argument becomes a DBG_VALUE,
;; but the hoisted variable location from the inlined scope is a DBG_INSTR_REF. ;; but the hoisted variable location from the inlined scope is a DBG_INSTR_REF.
; INSTRREF-LABEL: name: qux ; INSTRREF-LABEL: name: qux
; INSTRREF: DBG_PHI $rdi, 1 ; INSTRREF: DBG_PHI $rdi, 1
; INSTRREF-NEXT: DBG_VALUE $rdi, 0, ![[SOCKS]], !DIExpression(), ; INSTRREF-NEXT: DBG_VALUE $rdi, 0, ![[SOCKS]], !DIExpression(),
; INSTRREF-NEXT: %0:gr64 = COPY $rdi ; INSTRREF-NEXT: %0:gr64 = COPY $rdi
; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[KNEES]], !DIExpression(DW_OP_deref), ; INSTRREF-NEXT: DBG_INSTR_REF ![[KNEES]], !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_deref), dbg-instr-ref(1, 0),
; In fast-isel mode, neither variable are hoisted or forwarded to a physreg. ; In fast-isel mode, neither variable are hoisted or forwarded to a physreg.
; FASTISEL-INSTRREF-LABEL: name: qux ; FASTISEL-INSTRREF-LABEL: name: qux
; FASTISEL-INSTRREF: DBG_PHI $rdi, 1 ; FASTISEL-INSTRREF: DBG_PHI $rdi, 1
; FASTISEL-INSTRREF: DBG_INSTR_REF 1, 0, ![[SOCKS]], !DIExpression(DW_OP_deref), ; FASTISEL-INSTRREF: DBG_INSTR_REF ![[SOCKS]], !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_deref), dbg-instr-ref(1, 0),
; FASTISEL-INSTRREF-LABEL: bb.1.lala: ; FASTISEL-INSTRREF-LABEL: bb.1.lala:
; FASTISEL-INSTRREF: DBG_INSTR_REF 1, 0, ![[KNEES]], !DIExpression(DW_OP_deref), ; FASTISEL-INSTRREF: DBG_INSTR_REF ![[KNEES]], !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_deref), dbg-instr-ref(1, 0),
declare i64 @cheddar(i32 *%arg) declare i64 @cheddar(i32 *%arg)
define void @qux(i32* noalias sret(i32) %agg.result) !dbg !40 { define void @qux(i32* noalias sret(i32) %agg.result) !dbg !40 {
entry: entry:
call void @llvm.dbg.declare(metadata i32 *%agg.result, metadata !41, metadata !DIExpression()), !dbg !42 call void @llvm.dbg.declare(metadata i32 *%agg.result, metadata !41, metadata !DIExpression()), !dbg !42
%foo = call i64 @cheddar(i32 *%agg.result), !dbg !42 %foo = call i64 @cheddar(i32 *%agg.result), !dbg !42
br label %lala br label %lala
Show All 34 Lines

llvm/test/DebugInfo/X86/live-debug-values-expr-conflict.ll

Show All 24 Lines
; CHECK: ![[BAZVAR:[0-9]+]] = !DILocalVariable(name: "baz", ; CHECK: ![[BAZVAR:[0-9]+]] = !DILocalVariable(name: "baz",
; CHECK-LABEL: bb.0.entry: ; CHECK-LABEL: bb.0.entry:
; CHECK: DBG_VALUE {{[0-9a-zA-Z$%_]*}}, $noreg, ![[BAZVAR]], ; CHECK: DBG_VALUE {{[0-9a-zA-Z$%_]*}}, $noreg, ![[BAZVAR]],
; CHECK-SAME: !DIExpression() ; CHECK-SAME: !DIExpression()
; CHECK-LABEL: bb.1.if.then: ; CHECK-LABEL: bb.1.if.then:
; CHECK-LABEL: bb.2.if.else: ; CHECK-LABEL: bb.2.if.else:
; CHECK: DBG_VALUE {{[0-9a-zA-Z$%_]*}}, $noreg, ![[BAZVAR]], ; CHECK: DBG_VALUE {{[0-9a-zA-Z$%_]*}}, $noreg, ![[BAZVAR]],
; CHECK-SAME: !DIExpression() ; CHECK-SAME: !DIExpression()
; CHECK: DBG_VALUE {{[0-9a-zA-Z$%_]*}}, $noreg, ![[BAZVAR]], ; CHECK: DBG_VALUE_LIST ![[BAZVAR]],
; CHECK-SAME: !DIExpression(DW_OP_plus_uconst, 1, DW_OP_stack_value) ; CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_plus_uconst, 1, DW_OP_stack_value)
; CHECK-SAME: {{[0-9a-zA-Z$%_]*}}
; CHECK-LABEL: bb.3.if.end: ; CHECK-LABEL: bb.3.if.end:
; CHECK-NOT: DBG_VALUE ; CHECK-NOT: DBG_VALUE
; CHECK-NOT: DBG_VALUE_LIST
declare void @escape1(i32) declare void @escape1(i32)
declare void @escape2(i32) declare void @escape2(i32)
declare void @llvm.dbg.value(metadata, metadata, metadata) declare void @llvm.dbg.value(metadata, metadata, metadata)
define i32 @foo(i32 returned %bar) !dbg !7 { define i32 @foo(i32 returned %bar) !dbg !7 {
entry: entry:
call void @llvm.dbg.value(metadata i32 %bar, metadata !13, metadata !DIExpression()), !dbg !14 call void @llvm.dbg.value(metadata i32 %bar, metadata !13, metadata !DIExpression()), !dbg !14
Show All 31 Lines

llvm/test/DebugInfo/X86/live-debug-vars-loc-limit.ll

; RUN: llc --stop-after=virtregrewriter -o - %s | FileCheck %s ; RUN: llc --stop-after=virtregrewriter -experimental-debug-variable-locations=false -o - %s | FileCheck %s
; Check that any debug value with 64+ unique machine location operands is set ; Check that any debug value with 64+ unique machine location operands is set
; undef by LiveDebugVariables. ; undef by LiveDebugVariables.
; This test uses constant i32 values in the DIArgList instead of SSA values, as ; This test uses constant i32 values in the DIArgList instead of SSA values, as
; it allows the test case to be much simpler. If at some point we are able to ; it allows the test case to be much simpler. If at some point we are able to
; simplify such constant expressions, this test will fail; if that happens, ; simplify such constant expressions, this test will fail; if that happens,
; there is another version of this test that uses SSA values at: ; there is another version of this test that uses SSA values at:
; https://reviews.llvm.org/D101373?id=340953 ; https://reviews.llvm.org/D101373?id=340953
; CHECK: ![[VAR_A:[0-9]+]] = !DILocalVariable(name: "a" ; CHECK: ![[VAR_A:[0-9]+]] = !DILocalVariable(name: "a"
; CHECK-NOT: DBG_VALUE ; CHECK-NOT: DBG_VALUE
; CHECK: DBG_VALUE_LIST ![[VAR_A]], !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_stack_value), $noreg ; CHECK: DBG_VALUE_LIST ![[VAR_A]], !DIExpression(DW_OP_LLVM_arg, 0), $noreg
; CHECK-NOT: DBG_VALUE ; CHECK-NOT: DBG_VALUE
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define dso_local i32 @_Z3fooi(i32 returned %b) local_unnamed_addr !dbg !8 { define dso_local i32 @_Z3fooi(i32 returned %b) local_unnamed_addr !dbg !8 {
entry: entry:
call void @llvm.dbg.value(metadata !DIArgList(i32 1, i32 126, i32 124, i32 122, i32 120, i32 118, i32 116, i32 114, i32 112, i32 110, i32 108, i32 106, i32 104, i32 102, i32 100, i32 98, i32 96, i32 94, i32 92, i32 90, i32 88, i32 86, i32 84, i32 82, i32 80, i32 78, i32 76, i32 74, i32 72, i32 70, i32 68, i32 66, i32 64, i32 62, i32 60, i32 58, i32 56, i32 54, i32 52, i32 50, i32 48, i32 46, i32 44, i32 42, i32 40, i32 38, i32 36, i32 34, i32 32, i32 30, i32 28, i32 26, i32 24, i32 22, i32 20, i32 18, i32 16, i32 14, i32 12, i32 10, i32 8, i32 6, i32 4, i32 2), metadata !14, metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 63, DW_OP_plus, DW_OP_LLVM_arg, 62, DW_OP_plus, DW_OP_LLVM_arg, 61, DW_OP_plus, DW_OP_LLVM_arg, 60, DW_OP_plus, DW_OP_LLVM_arg, 59, DW_OP_plus, DW_OP_LLVM_arg, 58, DW_OP_plus, DW_OP_LLVM_arg, 57, DW_OP_plus, DW_OP_LLVM_arg, 56, DW_OP_plus, DW_OP_LLVM_arg, 55, DW_OP_plus, DW_OP_LLVM_arg, 54, DW_OP_plus, DW_OP_LLVM_arg, 53, DW_OP_plus, DW_OP_LLVM_arg, 52, DW_OP_plus, DW_OP_LLVM_arg, 51, DW_OP_plus, DW_OP_LLVM_arg, 50, DW_OP_plus, DW_OP_LLVM_arg, 49, DW_OP_plus, DW_OP_LLVM_arg, 48, DW_OP_plus, DW_OP_LLVM_arg, 47, DW_OP_plus, DW_OP_LLVM_arg, 46, DW_OP_plus, DW_OP_LLVM_arg, 45, DW_OP_plus, DW_OP_LLVM_arg, 44, DW_OP_plus, DW_OP_LLVM_arg, 43, DW_OP_plus, DW_OP_LLVM_arg, 42, DW_OP_plus, DW_OP_LLVM_arg, 41, DW_OP_plus, DW_OP_LLVM_arg, 40, DW_OP_plus, DW_OP_LLVM_arg, 39, DW_OP_plus, DW_OP_LLVM_arg, 38, DW_OP_plus, DW_OP_LLVM_arg, 37, DW_OP_plus, DW_OP_LLVM_arg, 36, DW_OP_plus, DW_OP_LLVM_arg, 35, DW_OP_plus, DW_OP_LLVM_arg, 34, DW_OP_plus, DW_OP_LLVM_arg, 33, DW_OP_plus, DW_OP_LLVM_arg, 32, DW_OP_plus, DW_OP_LLVM_arg, 31, DW_OP_plus, DW_OP_LLVM_arg, 30, DW_OP_plus, DW_OP_LLVM_arg, 29, DW_OP_plus, DW_OP_LLVM_arg, 28, DW_OP_plus, DW_OP_LLVM_arg, 27, DW_OP_plus, DW_OP_LLVM_arg, 26, DW_OP_plus, DW_OP_LLVM_arg, 25, DW_OP_plus, DW_OP_LLVM_arg, 24, DW_OP_plus, DW_OP_LLVM_arg, 23, DW_OP_plus, DW_OP_LLVM_arg, 22, DW_OP_plus, DW_OP_LLVM_arg, 21, DW_OP_plus, DW_OP_LLVM_arg, 20, DW_OP_plus, DW_OP_LLVM_arg, 19, DW_OP_plus, DW_OP_LLVM_arg, 18, DW_OP_plus, DW_OP_LLVM_arg, 17, DW_OP_plus, DW_OP_LLVM_arg, 16, DW_OP_plus, DW_OP_LLVM_arg, 15, DW_OP_plus, DW_OP_LLVM_arg, 14, DW_OP_plus, DW_OP_LLVM_arg, 13, DW_OP_plus, DW_OP_LLVM_arg, 12, DW_OP_plus, DW_OP_LLVM_arg, 11, DW_OP_plus, DW_OP_LLVM_arg, 10, DW_OP_plus, DW_OP_LLVM_arg, 9, DW_OP_plus, DW_OP_LLVM_arg, 8, DW_OP_plus, DW_OP_LLVM_arg, 7, DW_OP_plus, DW_OP_LLVM_arg, 6, DW_OP_plus, DW_OP_LLVM_arg, 5, DW_OP_plus, DW_OP_LLVM_arg, 4, DW_OP_plus, DW_OP_LLVM_arg, 3, DW_OP_plus, DW_OP_LLVM_arg, 2, DW_OP_plus, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_stack_value)), !dbg !15 call void @llvm.dbg.value(metadata !DIArgList(i32 1, i32 126, i32 124, i32 122, i32 120, i32 118, i32 116, i32 114, i32 112, i32 110, i32 108, i32 106, i32 104, i32 102, i32 100, i32 98, i32 96, i32 94, i32 92, i32 90, i32 88, i32 86, i32 84, i32 82, i32 80, i32 78, i32 76, i32 74, i32 72, i32 70, i32 68, i32 66, i32 64, i32 62, i32 60, i32 58, i32 56, i32 54, i32 52, i32 50, i32 48, i32 46, i32 44, i32 42, i32 40, i32 38, i32 36, i32 34, i32 32, i32 30, i32 28, i32 26, i32 24, i32 22, i32 20, i32 18, i32 16, i32 14, i32 12, i32 10, i32 8, i32 6, i32 4, i32 2), metadata !14, metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 63, DW_OP_plus, DW_OP_LLVM_arg, 62, DW_OP_plus, DW_OP_LLVM_arg, 61, DW_OP_plus, DW_OP_LLVM_arg, 60, DW_OP_plus, DW_OP_LLVM_arg, 59, DW_OP_plus, DW_OP_LLVM_arg, 58, DW_OP_plus, DW_OP_LLVM_arg, 57, DW_OP_plus, DW_OP_LLVM_arg, 56, DW_OP_plus, DW_OP_LLVM_arg, 55, DW_OP_plus, DW_OP_LLVM_arg, 54, DW_OP_plus, DW_OP_LLVM_arg, 53, DW_OP_plus, DW_OP_LLVM_arg, 52, DW_OP_plus, DW_OP_LLVM_arg, 51, DW_OP_plus, DW_OP_LLVM_arg, 50, DW_OP_plus, DW_OP_LLVM_arg, 49, DW_OP_plus, DW_OP_LLVM_arg, 48, DW_OP_plus, DW_OP_LLVM_arg, 47, DW_OP_plus, DW_OP_LLVM_arg, 46, DW_OP_plus, DW_OP_LLVM_arg, 45, DW_OP_plus, DW_OP_LLVM_arg, 44, DW_OP_plus, DW_OP_LLVM_arg, 43, DW_OP_plus, DW_OP_LLVM_arg, 42, DW_OP_plus, DW_OP_LLVM_arg, 41, DW_OP_plus, DW_OP_LLVM_arg, 40, DW_OP_plus, DW_OP_LLVM_arg, 39, DW_OP_plus, DW_OP_LLVM_arg, 38, DW_OP_plus, DW_OP_LLVM_arg, 37, DW_OP_plus, DW_OP_LLVM_arg, 36, DW_OP_plus, DW_OP_LLVM_arg, 35, DW_OP_plus, DW_OP_LLVM_arg, 34, DW_OP_plus, DW_OP_LLVM_arg, 33, DW_OP_plus, DW_OP_LLVM_arg, 32, DW_OP_plus, DW_OP_LLVM_arg, 31, DW_OP_plus, DW_OP_LLVM_arg, 30, DW_OP_plus, DW_OP_LLVM_arg, 29, DW_OP_plus, DW_OP_LLVM_arg, 28, DW_OP_plus, DW_OP_LLVM_arg, 27, DW_OP_plus, DW_OP_LLVM_arg, 26, DW_OP_plus, DW_OP_LLVM_arg, 25, DW_OP_plus, DW_OP_LLVM_arg, 24, DW_OP_plus, DW_OP_LLVM_arg, 23, DW_OP_plus, DW_OP_LLVM_arg, 22, DW_OP_plus, DW_OP_LLVM_arg, 21, DW_OP_plus, DW_OP_LLVM_arg, 20, DW_OP_plus, DW_OP_LLVM_arg, 19, DW_OP_plus, DW_OP_LLVM_arg, 18, DW_OP_plus, DW_OP_LLVM_arg, 17, DW_OP_plus, DW_OP_LLVM_arg, 16, DW_OP_plus, DW_OP_LLVM_arg, 15, DW_OP_plus, DW_OP_LLVM_arg, 14, DW_OP_plus, DW_OP_LLVM_arg, 13, DW_OP_plus, DW_OP_LLVM_arg, 12, DW_OP_plus, DW_OP_LLVM_arg, 11, DW_OP_plus, DW_OP_LLVM_arg, 10, DW_OP_plus, DW_OP_LLVM_arg, 9, DW_OP_plus, DW_OP_LLVM_arg, 8, DW_OP_plus, DW_OP_LLVM_arg, 7, DW_OP_plus, DW_OP_LLVM_arg, 6, DW_OP_plus, DW_OP_LLVM_arg, 5, DW_OP_plus, DW_OP_LLVM_arg, 4, DW_OP_plus, DW_OP_LLVM_arg, 3, DW_OP_plus, DW_OP_LLVM_arg, 2, DW_OP_plus, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_stack_value)), !dbg !15
Show All 26 Lines

llvm/test/DebugInfo/X86/pieces-4.ll

Show All 10 Lines
; asm volatile("" : : : "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", ; asm volatile("" : : : "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp",
; "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"); ; "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15");
; return o.x; ; return o.x;
; } ; }
; CHECK-LABEL: bitpiece_spill: # @bitpiece_spill ; CHECK-LABEL: bitpiece_spill: # @bitpiece_spill
; CHECK: callq g ; CHECK: callq g
; CHECK: movl %eax, [[offs:[0-9]+]](%rsp) # 4-byte Spill ; CHECK: movl %eax, [[offs:[0-9]+]](%rsp) # 4-byte Spill
; CHECK: #DEBUG_VALUE: bitpiece_spill:o <- [DW_OP_plus_uconst [[offs]], DW_OP_LLVM_fragment 0 32] [$rsp+0] ; CHECK: #DEBUG_VALUE: bitpiece_spill:o <- [DW_OP_plus_uconst [[offs]], DW_OP_deref, DW_OP_LLVM_fragment 0 32] $rsp
; CHECK: #DEBUG_VALUE: bitpiece_spill:o <- [DW_OP_LLVM_fragment 32 32] 0 ; CHECK: #DEBUG_VALUE: bitpiece_spill:o <- [DW_OP_LLVM_fragment 32 32] 0
; CHECK: #APP ; CHECK: #APP
; CHECK: #NO_APP ; CHECK: #NO_APP
; CHECK: movl [[offs]](%rsp), %eax # 4-byte Reload ; CHECK: movl [[offs]](%rsp), %eax # 4-byte Reload
; CHECK: retq ; CHECK: retq
; DWARF: .debug_loc contents: ; DWARF: .debug_loc contents:
; DWARF-NEXT: 0x00000000: ; DWARF-NEXT: 0x00000000:
▲ Show 20 Lines • Show All 62 Lines • Show Last 20 Lines

llvm/test/DebugInfo/X86/pr34545.ll

; RUN: llc -O1 -filetype=asm -mtriple x86_64-unknown-linux-gnu -mcpu=x86-64 \ ; RUN: llc -O1 -filetype=asm -mtriple x86_64-unknown-linux-gnu -mcpu=x86-64 \
; RUN: -o - %s -stop-after=livedebugvars \ ; RUN: -o - %s -stop-after=livedebugvars \
; RUN: -experimental-debug-variable-locations=false \ ; RUN: -experimental-debug-variable-locations=false \
; RUN: | FileCheck %s --check-prefixes=CHECK,VARLOCS ; RUN: | FileCheck %s --check-prefixes=CHECK,VARLOCS
; RUN: llc -O1 -filetype=asm -mtriple x86_64-unknown-linux-gnu -mcpu=x86-64 \ ; RUN: llc -O1 -filetype=asm -mtriple x86_64-unknown-linux-gnu -mcpu=x86-64 \
; RUN: -o - %s -stop-after=livedebugvars \ ; RUN: -o - %s -stop-after=livedebugvars \
; RUN: -experimental-debug-variable-locations=true \ ; RUN: -experimental-debug-variable-locations=true \
; RUN: | FileCheck %s --check-prefixes=CHECK,INSTRREF ; RUN: | FileCheck %s --check-prefixes=CHECK,INSTRREF
; CHECK: $eax = MOV32rm ; CHECK: $eax = MOV32rm
; INSTRREF-SAME: debug-instr-number 1 ; INSTRREF-SAME: debug-instr-number 1
; INSTRREF: DBG_INSTR_REF 1, 0 ; INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK: DBG_VALUE $eax ; VARLOCS: DBG_VALUE $eax
; INSTRREF: DBG_VALUE_LIST {{.+}} $eax
; CHECK: $eax = SHL32rCL killed renamable $eax, ; CHECK: $eax = SHL32rCL killed renamable $eax,
; INSTRREF-SAME: debug-instr-number 2 ; INSTRREF-SAME: debug-instr-number 2
; INSTRREF: DBG_INSTR_REF 2, 0 ; INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
; CHECK: DBG_VALUE $eax ; VARLOCS: DBG_VALUE $eax
; CHECK: DBG_VALUE $rsp, 0, !{{[0-9]+}}, !DIExpression(DW_OP_constu, 4, DW_OP_minus) ; INSTRREF: DBG_VALUE_LIST {{.+}} $eax
; VARLOCS: DBG_VALUE $rsp, 0, !{{[0-9]+}}, !DIExpression(DW_OP_constu, 4, DW_OP_minus)
; INSTRREF: DBG_VALUE_LIST !{{[0-9]+}}, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_constu, 4, DW_OP_minus, DW_OP_deref), $rsp
; VARLOCS: DBG_VALUE $eax ; VARLOCS: DBG_VALUE $eax
; CHECK: $eax = SHL32rCL killed renamable $eax, ; CHECK: $eax = SHL32rCL killed renamable $eax,
; INSTRREF-SAME: debug-instr-number 3 ; INSTRREF-SAME: debug-instr-number 3
; INSTRREF: DBG_INSTR_REF 3, 0 ; INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
; CHECK: DBG_VALUE $eax ; VARLOCS: DBG_VALUE $eax
; INSTRREF: DBG_VALUE_LIST {{.+}} $eax
; CHECK: RET64 $eax ; CHECK: RET64 $eax
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
@var = local_unnamed_addr global i32 8, !dbg !0 @var = local_unnamed_addr global i32 8, !dbg !0
@sc = local_unnamed_addr global i32 1, !dbg !6 @sc = local_unnamed_addr global i32 1, !dbg !6
Show All 40 Lines

llvm/test/DebugInfo/X86/pr40427.ll

Show All 24 Linestrueb:
br label %block br label %block
falseb: falseb:
br label %block br label %block
block: block:
; CHECK: [[PHIREG:%[0-9]+]]:gr64 = PHI %6, %bb.2, %4, %bb.1 ; CHECK: [[PHIREG:%[0-9]+]]:gr64 = PHI %6, %bb.2, %4, %bb.1
; CHECK-NEXT: [[LOADR:%[0-9]+]]:gr16 = MOV16rm %0, ; CHECK-NEXT: [[LOADR:%[0-9]+]]:gr16 = MOV16rm %0,
; INSTRREF-SAME: debug-instr-number 1 ; INSTRREF-SAME: debug-instr-number 1
; DBGVALUE-NEXT: DBG_VALUE [[LOADR]], $noreg, ![[DBGVAR]] ; DBGVALUE-NEXT: DBG_VALUE [[LOADR]], $noreg, ![[DBGVAR]]
; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[DBGVAR]] ; INSTRREF-NEXT: DBG_INSTR_REF ![[DBGVAR]], {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NEXT: %{{[0-9]+}}:gr32 = IMPLICIT_DEF ; CHECK-NEXT: %{{[0-9]+}}:gr32 = IMPLICIT_DEF
%foo = phi i64 *[%bees, %trueb], [%more, %falseb] %foo = phi i64 *[%bees, %trueb], [%more, %falseb]
%forks = bitcast i64 *%foo to i32 * %forks = bitcast i64 *%foo to i32 *
%ret = load i32, i32 *%forks, !dbg !6 %ret = load i32, i32 *%forks, !dbg !6
%cast = trunc i32 %ret to i16, !dbg !6 %cast = trunc i32 %ret to i16, !dbg !6
call void @llvm.dbg.value(metadata i16 %cast, metadata !1, metadata !DIExpression()), !dbg !6 call void @llvm.dbg.value(metadata i16 %cast, metadata !1, metadata !DIExpression()), !dbg !6
%orly2 = add i16 %yellow, 1 %orly2 = add i16 %yellow, 1
br label %bb1 br label %bb1
Show All 16 Lines

llvm/test/DebugInfo/X86/sdag-combine.ll

Show All 11 Lines
declare void @llvm.dbg.declare(metadata, metadata, metadata) #0 declare void @llvm.dbg.declare(metadata, metadata, metadata) #0
; Function Attrs: nounwind readnone speculatable ; Function Attrs: nounwind readnone speculatable
define swiftcc void @g() #0 !dbg !5 { define swiftcc void @g() #0 !dbg !5 {
entry: entry:
%0 = alloca %TSb, align 1 %0 = alloca %TSb, align 1
%1 = call swiftcc i1 @f(), !dbg !7 %1 = call swiftcc i1 @f(), !dbg !7
; CHECK: DBG_VALUE $rcx, $noreg, !8, !DIExpression(), ; CHECK: DBG_VALUE $rcx, $noreg, !8, !DIExpression(),
; INSTRREF: DBG_VALUE $ecx, $noreg, !8, !DIExpression(), ; INSTRREF: DBG_VALUE_LIST !8, !DIExpression(DW_OP_LLVM_arg, 0), $ecx
call void @llvm.dbg.value(metadata i1 %1, metadata !8, metadata !DIExpression()), !dbg !7 call void @llvm.dbg.value(metadata i1 %1, metadata !8, metadata !DIExpression()), !dbg !7
%2 = getelementptr inbounds %TSb, %TSb* %0, i32 0, i32 0, !dbg !7 %2 = getelementptr inbounds %TSb, %TSb* %0, i32 0, i32 0, !dbg !7
store i1 %1, i1* %2, align 1, !dbg !7 store i1 %1, i1* %2, align 1, !dbg !7
%3 = zext i1 %1 to i64, !dbg !7 %3 = zext i1 %1 to i64, !dbg !7
call void asm sideeffect "", "r"(i64 %3), !dbg !7 call void asm sideeffect "", "r"(i64 %3), !dbg !7
ret void, !dbg !7 ret void, !dbg !7
} }
Show All 20 Lines

llvm/test/DebugInfo/X86/sdag-dangling-dbgvalue.ll

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
@S = global %struct.SS { i32 23, i32 -17 }, align 4, !dbg !0 @S = global %struct.SS { i32 23, i32 -17 }, align 4, !dbg !0
; Verify that the def comes before the for foo1. ; Verify that the def comes before the for foo1.
define i32 @test1() local_unnamed_addr #0 !dbg !17 { define i32 @test1() local_unnamed_addr #0 !dbg !17 {
; CHECK-LABEL: bb.0.entry1 ; CHECK-LABEL: bb.0.entry1
; CHECK-NEXT: DBG_VALUE 0, $noreg, ![[BAR1]], !DIExpression() ; CHECK-NEXT: DBG_VALUE 0, $noreg, ![[BAR1]], !DIExpression()
; CHECK-NEXT: [[REG1:%[0-9]+]]:gr64 = LEA64r ; CHECK-NEXT: [[REG1:%[0-9]+]]:gr64 = LEA64r
; INSTRREF-SAME: debug-instr-number 1 ; INSTRREF-SAME: debug-instr-number 1
; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[FOO1]], !DIExpression() ; INSTRREF-NEXT: DBG_INSTR_REF ![[FOO1]], !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG1]], $noreg, ![[FOO1]], !DIExpression() ; DBGVALUE-NEXT: DBG_VALUE [[REG1]], $noreg, ![[FOO1]], !DIExpression()
entry1: entry1:
call void @llvm.dbg.value(metadata %struct.SS* @S, metadata !20, metadata !DIExpression()), !dbg !23 call void @llvm.dbg.value(metadata %struct.SS* @S, metadata !20, metadata !DIExpression()), !dbg !23
call void @llvm.dbg.value(metadata %struct.SS* null, metadata !22, metadata !DIExpression()), !dbg !24 call void @llvm.dbg.value(metadata %struct.SS* null, metadata !22, metadata !DIExpression()), !dbg !24
ret i32 ptrtoint (%struct.SS* @S to i32), !dbg !25 ret i32 ptrtoint (%struct.SS* @S to i32), !dbg !25
} }
; Verify that the def comes before the for foo2 and bar2. ; Verify that the def comes before the for foo2 and bar2.
define i32 @test2() local_unnamed_addr #0 !dbg !26 { define i32 @test2() local_unnamed_addr #0 !dbg !26 {
; CHECK-LABEL: bb.0.entry2 ; CHECK-LABEL: bb.0.entry2
; CHECK-NEXT: [[REG2:%[0-9]+]]:gr64 = LEA64r ; CHECK-NEXT: [[REG2:%[0-9]+]]:gr64 = LEA64r
; INSTRREF-SAME: debug-instr-number 1 ; INSTRREF-SAME: debug-instr-number 1
; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[FOO2]], !DIExpression() ; INSTRREF-NEXT: DBG_INSTR_REF ![[FOO2]], !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0)
; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[BAR2]], !DIExpression() ; INSTRREF-NEXT: DBG_INSTR_REF ![[BAR2]], !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, ![[FOO2]], !DIExpression ; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, ![[FOO2]], !DIExpression
; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, ![[BAR2]], !DIExpression ; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, ![[BAR2]], !DIExpression
entry2: entry2:
call void @llvm.dbg.value(metadata %struct.SS* @S, metadata !28, metadata !DIExpression()), !dbg !30 call void @llvm.dbg.value(metadata %struct.SS* @S, metadata !28, metadata !DIExpression()), !dbg !30
call void @llvm.dbg.value(metadata %struct.SS* @S, metadata !29, metadata !DIExpression()), !dbg !31 call void @llvm.dbg.value(metadata %struct.SS* @S, metadata !29, metadata !DIExpression()), !dbg !31
ret i32 add (i32 ptrtoint (%struct.SS* @S to i32), i32 ptrtoint (%struct.SS* @S to i32)), !dbg !32 ret i32 add (i32 ptrtoint (%struct.SS* @S to i32), i32 ptrtoint (%struct.SS* @S to i32)), !dbg !32
} }
; Verify that the def comes before the for foo3 and bar3. ; Verify that the def comes before the for foo3 and bar3.
define i32 @test3() local_unnamed_addr #0 !dbg !33 { define i32 @test3() local_unnamed_addr #0 !dbg !33 {
; CHECK-LABEL: bb.0.entry3 ; CHECK-LABEL: bb.0.entry3
; CHECK-NEXT: [[REG3:%[0-9]+]]:gr64 = LEA64r ; CHECK-NEXT: [[REG3:%[0-9]+]]:gr64 = LEA64r
; INSTRREF-SAME: debug-instr-number 1 ; INSTRREF-SAME: debug-instr-number 1
; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[BAR3]], !DIExpression() ; INSTRREF-NEXT: DBG_INSTR_REF ![[BAR3]], !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0)
; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[FOO3]], !DIExpression() ; INSTRREF-NEXT: DBG_INSTR_REF ![[FOO3]], !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, ![[BAR3]], !DIExpression() ; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, ![[BAR3]], !DIExpression()
; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, ![[FOO3]], !DIExpression() ; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, ![[FOO3]], !DIExpression()
entry3: entry3:
call void @llvm.dbg.value(metadata %struct.SS* @S, metadata !36, metadata !DIExpression()), !dbg !38 call void @llvm.dbg.value(metadata %struct.SS* @S, metadata !36, metadata !DIExpression()), !dbg !38
call void @llvm.dbg.value(metadata %struct.SS* @S, metadata !35, metadata !DIExpression()), !dbg !37 call void @llvm.dbg.value(metadata %struct.SS* @S, metadata !35, metadata !DIExpression()), !dbg !37
ret i32 add (i32 ptrtoint (%struct.SS* @S to i32), i32 ptrtoint (%struct.SS* @S to i32)), !dbg !39 ret i32 add (i32 ptrtoint (%struct.SS* @S to i32), i32 ptrtoint (%struct.SS* @S to i32)), !dbg !39
} }
; Verify that the def comes before the for bar4. ; Verify that the def comes before the for bar4.
define i32 @test4() local_unnamed_addr #0 !dbg !40 { define i32 @test4() local_unnamed_addr #0 !dbg !40 {
; CHECK-LABEL: bb.0.entry4 ; CHECK-LABEL: bb.0.entry4
; CHECK-NEXT: DBG_VALUE $noreg, $noreg, ![[FOO4]], !DIExpression() ; CHECK-NEXT: DBG_VALUE $noreg, $noreg, ![[FOO4]], !DIExpression()
; CHECK-NEXT: DBG_VALUE 0, $noreg, ![[FOO4]], !DIExpression() ; CHECK-NEXT: DBG_VALUE 0, $noreg, ![[FOO4]], !DIExpression()
; CHECK-NEXT: [[REG4:%[0-9]+]]:gr64 = LEA64r ; CHECK-NEXT: [[REG4:%[0-9]+]]:gr64 = LEA64r
; INSTRREF-SAME: debug-instr-number 1 ; INSTRREF-SAME: debug-instr-number 1
; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[BAR4]], !DIExpression() ; INSTRREF-NEXT: DBG_INSTR_REF ![[BAR4]], !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG4]], $noreg, ![[BAR4]], !DIExpression() ; DBGVALUE-NEXT: DBG_VALUE [[REG4]], $noreg, ![[BAR4]], !DIExpression()
entry4: entry4:
call void @llvm.dbg.value(metadata %struct.SS* @S, metadata !42, metadata !DIExpression()), !dbg !44 call void @llvm.dbg.value(metadata %struct.SS* @S, metadata !42, metadata !DIExpression()), !dbg !44
call void @llvm.dbg.value(metadata %struct.SS* @S, metadata !43, metadata !DIExpression()), !dbg !45 call void @llvm.dbg.value(metadata %struct.SS* @S, metadata !43, metadata !DIExpression()), !dbg !45
call void @llvm.dbg.value(metadata %struct.SS* null, metadata !42, metadata !DIExpression()), !dbg !44 call void @llvm.dbg.value(metadata %struct.SS* null, metadata !42, metadata !DIExpression()), !dbg !44
ret i32 ptrtoint (%struct.SS* @S to i32), !dbg !46 ret i32 ptrtoint (%struct.SS* @S to i32), !dbg !46
} }
; Verify that we do not get a DBG_VALUE that maps foo5 to @S here. ; Verify that we do not get a DBG_VALUE that maps foo5 to @S here.
define i32 @test5() local_unnamed_addr #0 !dbg !47 { define i32 @test5() local_unnamed_addr #0 !dbg !47 {
; CHECK-LABEL: bb.0.entry5: ; CHECK-LABEL: bb.0.entry5:
; CHECK-NEXT: DBG_VALUE $noreg, $noreg, ![[FOO5]], !DIExpression() ; CHECK-NEXT: DBG_VALUE $noreg, $noreg, ![[FOO5]], !DIExpression()
; CHECK-NEXT: DBG_VALUE 0, $noreg, ![[FOO5]], !DIExpression() ; CHECK-NEXT: DBG_VALUE 0, $noreg, ![[FOO5]], !DIExpression()
; CHECK-NEXT: [[REG5:%[0-9]+]]:gr64 = LEA64r ; CHECK-NEXT: [[REG5:%[0-9]+]]:gr64 = LEA64r
; INSTRREF-SAME: debug-instr-number 1 ; INSTRREF-SAME: debug-instr-number 1
; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[BAR5]], !DIExpression() ; INSTRREF-NEXT: DBG_INSTR_REF ![[BAR5]], !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG5]], $noreg, ![[BAR5]], !DIExpression() ; DBGVALUE-NEXT: DBG_VALUE [[REG5]], $noreg, ![[BAR5]], !DIExpression()
; CHECK-NOT: DBG_{{.*}} ![[FOO5]], !DIExpression() ; CHECK-NOT: DBG_{{.*}} ![[FOO5]], !DIExpression()
; CHECK: RET ; CHECK: RET
entry5: entry5:
call void @llvm.dbg.value(metadata %struct.SS* @S, metadata !49, metadata !DIExpression()), !dbg !51 call void @llvm.dbg.value(metadata %struct.SS* @S, metadata !49, metadata !DIExpression()), !dbg !51
call void @llvm.dbg.value(metadata %struct.SS* @S, metadata !50, metadata !DIExpression()), !dbg !52 call void @llvm.dbg.value(metadata %struct.SS* @S, metadata !50, metadata !DIExpression()), !dbg !52
call void @llvm.dbg.value(metadata %struct.SS* null, metadata !50, metadata !DIExpression()), !dbg !52 call void @llvm.dbg.value(metadata %struct.SS* null, metadata !50, metadata !DIExpression()), !dbg !52
ret i32 ptrtoint (%struct.SS* @S to i32), !dbg !53 ret i32 ptrtoint (%struct.SS* @S to i32), !dbg !53
▲ Show 20 Lines • Show All 66 Lines • Show Last 20 Lines

llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-1.ll

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
for.body.lr.ph: ; preds = %entry for.body.lr.ph: ; preds = %entry
%1 = load i32, i32* @end, align 4, !tbaa !31 %1 = load i32, i32* @end, align 4, !tbaa !31
br label %for.body, !dbg !36 br label %for.body, !dbg !36
for.cond.cleanup: ; preds = %for.body, %entry for.cond.cleanup: ; preds = %for.body, %entry
; CHECK-LABEL: bb.{{.*}}.for.cond.cleanup: ; CHECK-LABEL: bb.{{.*}}.for.cond.cleanup:
; CHECK: [[REG1:%[0-9]+]]:gr32 = PHI ; CHECK: [[REG1:%[0-9]+]]:gr32 = PHI
; INSTRREF-SAME: debug-instr-number 7 ; INSTRREF-SAME: debug-instr-number 7
; INSTRREF-NEXT: DBG_INSTR_REF 7, 0 ; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(7, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG1]] ; DBGVALUE-NEXT: DBG_VALUE [[REG1]]
%x.0.lcssa = phi i32 [ 9, %entry ], [ %add, %for.body ] %x.0.lcssa = phi i32 [ 9, %entry ], [ %add, %for.body ]
call void @llvm.dbg.value(metadata i32 %x.0.lcssa, metadata !15, metadata !DIExpression()), !dbg !26 call void @llvm.dbg.value(metadata i32 %x.0.lcssa, metadata !15, metadata !DIExpression()), !dbg !26
%2 = bitcast [80 x i32]* %arr to i8*, !dbg !37 %2 = bitcast [80 x i32]* %arr to i8*, !dbg !37
call void @llvm.lifetime.start.p0i8(i64 320, i8* nonnull %2) #3, !dbg !37 call void @llvm.lifetime.start.p0i8(i64 320, i8* nonnull %2) #3, !dbg !37
call void @llvm.dbg.declare(metadata [80 x i32]* %arr, metadata !19, metadata !DIExpression()), !dbg !38 call void @llvm.dbg.declare(metadata [80 x i32]* %arr, metadata !19, metadata !DIExpression()), !dbg !38
call void @llvm.dbg.value(metadata i32 0, metadata !24, metadata !DIExpression()), !dbg !39 call void @llvm.dbg.value(metadata i32 0, metadata !24, metadata !DIExpression()), !dbg !39
br label %for.body4, !dbg !40 br label %for.body4, !dbg !40
for.body: ; preds = %for.body.lr.ph, %for.body for.body: ; preds = %for.body.lr.ph, %for.body
; CHECK-LABEL: bb.{{.*}}.for.body: ; CHECK-LABEL: bb.{{.*}}.for.body:
; CHECK: [[REG2:%[0-9]+]]:gr32 = PHI ; CHECK: [[REG2:%[0-9]+]]:gr32 = PHI
; INSTRREF-SAME: debug-instr-number 3 ; INSTRREF-SAME: debug-instr-number 3
; CHECK-NEXT: [[REG3:%[0-9]+]]:gr32 = PHI ; CHECK-NEXT: [[REG3:%[0-9]+]]:gr32 = PHI
; INSTRREF-SAME: debug-instr-number 4 ; INSTRREF-SAME: debug-instr-number 4
; CHECK-NEXT: [[REG4:%[0-9]+]]:gr32 = PHI ; CHECK-NEXT: [[REG4:%[0-9]+]]:gr32 = PHI
; INSTRREF-SAME: debug-instr-number 5 ; INSTRREF-SAME: debug-instr-number 5
; INSTRREF-NEXT: DBG_INSTR_REF 3, 0 ; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
; INSTRREF-NEXT: DBG_INSTR_REF 4, 0 ; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
; INSTRREF-NEXT: DBG_INSTR_REF 5, 0 ; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(5, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG2]] ; DBGVALUE-NEXT: DBG_VALUE [[REG2]]
; DBGVALUE-NEXT: DBG_VALUE [[REG3]] ; DBGVALUE-NEXT: DBG_VALUE [[REG3]]
; DBGVALUE-NEXT: DBG_VALUE [[REG4]] ; DBGVALUE-NEXT: DBG_VALUE [[REG4]]
%u.023 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ] %u.023 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
%y.022 = phi i32 [ 13, %for.body.lr.ph ], [ %mul, %for.body ] %y.022 = phi i32 [ 13, %for.body.lr.ph ], [ %mul, %for.body ]
%x.021 = phi i32 [ 9, %for.body.lr.ph ], [ %add, %for.body ] %x.021 = phi i32 [ 9, %for.body.lr.ph ], [ %add, %for.body ]
call void @llvm.dbg.value(metadata i32 %u.023, metadata !17, metadata !DIExpression()), !dbg !28 call void @llvm.dbg.value(metadata i32 %u.023, metadata !17, metadata !DIExpression()), !dbg !28
call void @llvm.dbg.value(metadata i32 %y.022, metadata !16, metadata !DIExpression()), !dbg !27 call void @llvm.dbg.value(metadata i32 %y.022, metadata !16, metadata !DIExpression()), !dbg !27
▲ Show 20 Lines • Show All 105 Lines • Show Last 20 Lines

llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-2.ll

Show All 28 Lines
for.body.lr.ph: ; preds = %entry for.body.lr.ph: ; preds = %entry
%1 = load i32, i32* @end, align 4, !tbaa !31 %1 = load i32, i32* @end, align 4, !tbaa !31
br label %for.body, !dbg !36 br label %for.body, !dbg !36
for.cond.cleanup: ; preds = %for.body, %entry for.cond.cleanup: ; preds = %for.body, %entry
; CHECK-LABEL: bb.{{.*}}.for.cond.cleanup: ; CHECK-LABEL: bb.{{.*}}.for.cond.cleanup:
; CHECK: [[REG1:%[0-9]+]]:gr32 = PHI ; CHECK: [[REG1:%[0-9]+]]:gr32 = PHI
; INSTRREF-SAME: debug-instr-number 7 ; INSTRREF-SAME: debug-instr-number 7
; INSTRREF-NEXT: DBG_INSTR_REF 7, 0 ; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(7, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG1]] ; DBGVALUE-NEXT: DBG_VALUE [[REG1]]
%x.0.lcssa = phi i32 [ 9, %entry ], [ %add, %for.body ] %x.0.lcssa = phi i32 [ 9, %entry ], [ %add, %for.body ]
call void @llvm.dbg.value(metadata i32 %x.0.lcssa, metadata !15, metadata !DIExpression()), !dbg !26 call void @llvm.dbg.value(metadata i32 %x.0.lcssa, metadata !15, metadata !DIExpression()), !dbg !26
%2 = bitcast [80 x i32]* %arr to i8*, !dbg !37 %2 = bitcast [80 x i32]* %arr to i8*, !dbg !37
call void @llvm.lifetime.start.p0i8(i64 320, i8* nonnull %2) #3, !dbg !37 call void @llvm.lifetime.start.p0i8(i64 320, i8* nonnull %2) #3, !dbg !37
call void @llvm.dbg.declare(metadata [80 x i32]* %arr, metadata !19, metadata !DIExpression()), !dbg !38 call void @llvm.dbg.declare(metadata [80 x i32]* %arr, metadata !19, metadata !DIExpression()), !dbg !38
call void @llvm.dbg.value(metadata i32 0, metadata !24, metadata !DIExpression()), !dbg !39 call void @llvm.dbg.value(metadata i32 0, metadata !24, metadata !DIExpression()), !dbg !39
br label %for.body4, !dbg !40 br label %for.body4, !dbg !40
for.body: ; preds = %for.body.lr.ph, %for.body for.body: ; preds = %for.body.lr.ph, %for.body
; CHECK-LABEL: bb.{{.*}}.for.body: ; CHECK-LABEL: bb.{{.*}}.for.body:
; CHECK: [[REG2:%[0-9]+]]:gr32 = PHI ; CHECK: [[REG2:%[0-9]+]]:gr32 = PHI
; INSTRREF-SAME: debug-instr-number 4 ; INSTRREF-SAME: debug-instr-number 4
; CHECK-NEXT: [[REG3:%[0-9]+]]:gr32 = PHI ; CHECK-NEXT: [[REG3:%[0-9]+]]:gr32 = PHI
; INSTRREF-SAME: debug-instr-number 3 ; INSTRREF-SAME: debug-instr-number 3
; CHECK-NEXT: [[REG4:%[0-9]+]]:gr32 = PHI ; CHECK-NEXT: [[REG4:%[0-9]+]]:gr32 = PHI
; INSTRREF-SAME: debug-instr-number 6 ; INSTRREF-SAME: debug-instr-number 6
; INSTRREF-NEXT: DBG_INSTR_REF 3, 0, !16 ; INSTRREF-NEXT: DBG_INSTR_REF !16, {{.+}}, dbg-instr-ref(3, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, !16 ; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, !16
; CHECK-NEXT: DBG_VALUE 555, $noreg, !17 ; CHECK-NEXT: DBG_VALUE 555, $noreg, !17
; CHECK-NEXT: [[ADDREG:%[0-9]+]]:gr32 = nuw nsw ADD32rr ; CHECK-NEXT: [[ADDREG:%[0-9]+]]:gr32 = nuw nsw ADD32rr
; INSTRREF-SAME: debug-instr-number 5 ; INSTRREF-SAME: debug-instr-number 5
; INSTRREF-NEXT: DBG_INSTR_REF 4, 0, !17 ; INSTRREF-NEXT: DBG_INSTR_REF !17, {{.+}}, dbg-instr-ref(4, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, !17 ; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, !17
; CHECK: [[MULREG:%[0-9]+]]:gr32 = LEA64_32r ; CHECK: [[MULREG:%[0-9]+]]:gr32 = LEA64_32r
; INSTRREF-SAME: debug-instr-number 1 ; INSTRREF-SAME: debug-instr-number 1
; CHECK-NEXT: DBG_VALUE 777, $noreg, !17 ; CHECK-NEXT: DBG_VALUE 777, $noreg, !17
;;; XXX: The following DBG_INSTR_REF should have stayed below the INC32r ;;; XXX: The following DBG_INSTR_REF should have stayed below the INC32r
; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, !16 ; INSTRREF-NEXT: DBG_INSTR_REF !16, {{.+}}, dbg-instr-ref(1, 0)
; DBGVALUE-NEXT: DBG_VALUE [[MULREG]], $noreg, !16 ; DBGVALUE-NEXT: DBG_VALUE [[MULREG]], $noreg, !16
; CHECK-NEXT: [[INCREG:%[0-9]+]]:gr32 = nuw nsw INC32r ; CHECK-NEXT: [[INCREG:%[0-9]+]]:gr32 = nuw nsw INC32r
; INSTRREF-SAME: debug-instr-number 2 ; INSTRREF-SAME: debug-instr-number 2
; INSTRREF-NEXT: DBG_INSTR_REF 2, 0, !17 ; INSTRREF-NEXT: DBG_INSTR_REF !17, {{.+}}, dbg-instr-ref(2, 0)
; INSTRREF-NEXT: DBG_INSTR_REF 5, 0, !15 ; INSTRREF-NEXT: DBG_INSTR_REF !15, {{.+}}, dbg-instr-ref(5, 0)
; DBGVALUE-NEXT: DBG_VALUE [[INCREG]], $noreg, !17 ; DBGVALUE-NEXT: DBG_VALUE [[INCREG]], $noreg, !17
; DBGVALUE-NEXT: DBG_VALUE [[ADDREG]], $noreg, !15 ; DBGVALUE-NEXT: DBG_VALUE [[ADDREG]], $noreg, !15
; CHECK-NEXT: implicit-def $eflags, ; CHECK-NEXT: implicit-def $eflags,
; INSTRREF-NEXT: DBG_INSTR_REF 6, 0 ; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(6, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG4]] ; DBGVALUE-NEXT: DBG_VALUE [[REG4]]
%u.023 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ] %u.023 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
%y.022 = phi i32 [ 13, %for.body.lr.ph ], [ %mul, %for.body ] %y.022 = phi i32 [ 13, %for.body.lr.ph ], [ %mul, %for.body ]
%x.021 = phi i32 [ 9, %for.body.lr.ph ], [ %add, %for.body ] %x.021 = phi i32 [ 9, %for.body.lr.ph ], [ %add, %for.body ]
call void @llvm.dbg.value(metadata i32 %y.022, metadata !16, metadata !DIExpression()), !dbg !27 call void @llvm.dbg.value(metadata i32 %y.022, metadata !16, metadata !DIExpression()), !dbg !27
; This dbg.value has been manually added compared to dbg_value_phi_isel1.ll ; This dbg.value has been manually added compared to dbg_value_phi_isel1.ll
call void @llvm.dbg.value(metadata i32 555, metadata !17, metadata !DIExpression()), !dbg !28 call void @llvm.dbg.value(metadata i32 555, metadata !17, metadata !DIExpression()), !dbg !28
%add = add nuw nsw i32 %y.022, %x.021, !dbg !41 %add = add nuw nsw i32 %y.022, %x.021, !dbg !41
▲ Show 20 Lines • Show All 109 Lines • Show Last 20 Lines

llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-3.ll

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[REG4:%[0-9]+]]:gr32 = PHI ; CHECK-NEXT: [[REG4:%[0-9]+]]:gr32 = PHI
; INSTRREF-SAME: debug-instr-number 7 ; INSTRREF-SAME: debug-instr-number 7
; CHECK-NEXT: [[REG5:%[0-9]+]]:gr32_nosp = PHI ; CHECK-NEXT: [[REG5:%[0-9]+]]:gr32_nosp = PHI
; INSTRREF-SAME: debug-instr-number 8 ; INSTRREF-SAME: debug-instr-number 8
; CHECK-NEXT: [[REG6:%[0-9]+]]:gr32 = PHI ; CHECK-NEXT: [[REG6:%[0-9]+]]:gr32 = PHI
; INSTRREF-SAME: debug-instr-number 9 ; INSTRREF-SAME: debug-instr-number 9
; CHECK-NEXT: [[REG7:%[0-9]+]]:gr32 = PHI ; CHECK-NEXT: [[REG7:%[0-9]+]]:gr32 = PHI
; INSTRREF-SAME: debug-instr-number 10 ; INSTRREF-SAME: debug-instr-number 10
; INSTRREF-NEXT: DBG_INSTR_REF 5, 0, !19, !DIExpression(DW_OP_LLVM_fragment, 0, 32) ; INSTRREF-NEXT: DBG_INSTR_REF !19, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(5, 0)
; INSTRREF-NEXT: DBG_INSTR_REF 6, 0, !19, !DIExpression(DW_OP_LLVM_fragment, 32, 32) ; INSTRREF-NEXT: DBG_INSTR_REF !19, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 32, 32), dbg-instr-ref(6, 0)
; INSTRREF-NEXT: DBG_INSTR_REF 7, 0, !18, !DIExpression(DW_OP_LLVM_fragment, 0, 32) ; INSTRREF-NEXT: DBG_INSTR_REF !18, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(7, 0)
; INSTRREF-NEXT: DBG_INSTR_REF 8, 0, !18, !DIExpression(DW_OP_LLVM_fragment, 32, 32) ; INSTRREF-NEXT: DBG_INSTR_REF !18, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 32, 32), dbg-instr-ref(8, 0)
; INSTRREF-NEXT: DBG_INSTR_REF 9, 0, !17, !DIExpression(DW_OP_LLVM_fragment, 0, 32) ; INSTRREF-NEXT: DBG_INSTR_REF !17, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(9, 0)
; INSTRREF-NEXT: DBG_INSTR_REF 10, 0, !17, !DIExpression(DW_OP_LLVM_fragment, 32, 32) ; INSTRREF-NEXT: DBG_INSTR_REF !17, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 32, 32), dbg-instr-ref(10, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, !19, !DIExpression(DW_OP_LLVM_fragment, 0, 32) ; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, !19, !DIExpression(DW_OP_LLVM_fragment, 0, 32)
; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, !19, !DIExpression(DW_OP_LLVM_fragment, 32, 32) ; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, !19, !DIExpression(DW_OP_LLVM_fragment, 32, 32)
; DBGVALUE-NEXT: DBG_VALUE [[REG4]], $noreg, !18, !DIExpression(DW_OP_LLVM_fragment, 0, 32) ; DBGVALUE-NEXT: DBG_VALUE [[REG4]], $noreg, !18, !DIExpression(DW_OP_LLVM_fragment, 0, 32)
; DBGVALUE-NEXT: DBG_VALUE [[REG5]], $noreg, !18, !DIExpression(DW_OP_LLVM_fragment, 32, 32) ; DBGVALUE-NEXT: DBG_VALUE [[REG5]], $noreg, !18, !DIExpression(DW_OP_LLVM_fragment, 32, 32)
; DBGVALUE-NEXT: DBG_VALUE [[REG6]], $noreg, !17, !DIExpression(DW_OP_LLVM_fragment, 0, 32) ; DBGVALUE-NEXT: DBG_VALUE [[REG6]], $noreg, !17, !DIExpression(DW_OP_LLVM_fragment, 0, 32)
; DBGVALUE-NEXT: DBG_VALUE [[REG7]], $noreg, !17, !DIExpression(DW_OP_LLVM_fragment, 32, 32) ; DBGVALUE-NEXT: DBG_VALUE [[REG7]], $noreg, !17, !DIExpression(DW_OP_LLVM_fragment, 32, 32)
%u.023 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ] %u.023 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
%y.022 = phi i64 [ 13, %for.body.lr.ph ], [ %mul, %for.body ] %y.022 = phi i64 [ 13, %for.body.lr.ph ], [ %mul, %for.body ]
▲ Show 20 Lines • Show All 94 Lines • Show Last 20 Lines

llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-4.ll

Show All 13 Lines
; CHECK-LABEL: bb.{{.*}}.if.end36: ; CHECK-LABEL: bb.{{.*}}.if.end36:
; CHECK: [[REG1:%[0-9]+]]:gr32 = PHI ; CHECK: [[REG1:%[0-9]+]]:gr32 = PHI
; INSTRREF-SAME: debug-instr-number 1 ; INSTRREF-SAME: debug-instr-number 1
; CHECK-NEXT: [[REG2:%[0-9]+]]:gr32 = PHI ; CHECK-NEXT: [[REG2:%[0-9]+]]:gr32 = PHI
; INSTRREF-SAME: debug-instr-number 2 ; INSTRREF-SAME: debug-instr-number 2
; CHECK-NEXT: [[REG3:%[0-9]+]]:gr32 = PHI ; CHECK-NEXT: [[REG3:%[0-9]+]]:gr32 = PHI
; INSTRREF-SAME: debug-instr-number 3 ; INSTRREF-SAME: debug-instr-number 3
; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, !13, !DIExpression(DW_OP_LLVM_fragment, 0, 32) ; INSTRREF-NEXT: DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(1, 0)
; INSTRREF-NEXT: DBG_INSTR_REF 2, 0, !13, !DIExpression(DW_OP_LLVM_fragment, 32, 32) ; INSTRREF-NEXT: DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 32, 32), dbg-instr-ref(2, 0)
; INSTRREF-NEXT: DBG_INSTR_REF 3, 0, !13, !DIExpression(DW_OP_LLVM_fragment, 64, 16) ; INSTRREF-NEXT: DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 16), dbg-instr-ref(3, 0)
; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, !12, !DIExpression(DW_OP_LLVM_fragment, 10, 32) ; INSTRREF-NEXT: DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 10, 32), dbg-instr-ref(1, 0)
; INSTRREF-NEXT: DBG_INSTR_REF 2, 0, !12, !DIExpression(DW_OP_LLVM_fragment, 42, 13) ; INSTRREF-NEXT: DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 42, 13), dbg-instr-ref(2, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG1]], $noreg, !13, !DIExpression(DW_OP_LLVM_fragment, 0, 32) ; DBGVALUE-NEXT: DBG_VALUE [[REG1]], $noreg, !13, !DIExpression(DW_OP_LLVM_fragment, 0, 32)
; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, !13, !DIExpression(DW_OP_LLVM_fragment, 32, 32) ; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, !13, !DIExpression(DW_OP_LLVM_fragment, 32, 32)
; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, !13, !DIExpression(DW_OP_LLVM_fragment, 64, 16) ; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, !13, !DIExpression(DW_OP_LLVM_fragment, 64, 16)
; DBGVALUE-NEXT: DBG_VALUE [[REG1]], $noreg, !12, !DIExpression(DW_OP_LLVM_fragment, 10, 32) ; DBGVALUE-NEXT: DBG_VALUE [[REG1]], $noreg, !12, !DIExpression(DW_OP_LLVM_fragment, 10, 32)
; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, !12, !DIExpression(DW_OP_LLVM_fragment, 42, 13) ; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, !12, !DIExpression(DW_OP_LLVM_fragment, 42, 13)
; CHECK-NOT: DBG_ ; CHECK-NOT: DBG_
target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
▲ Show 20 Lines • Show All 69 Lines • Show Last 20 Lines

llvm/test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll

Show All 24 Lines; INSTRREF: ADD32ri8 {{.*}} debug-instr-number 1
%cmp = icmp eq i32 %1, 0 %cmp = icmp eq i32 %1, 0
br i1 %cmp, label %nextbb, label %exit, !dbg !26 br i1 %cmp, label %nextbb, label %exit, !dbg !26
nextbb: nextbb:
; CHECK-LABEL: bb.{{.*}}.nextbb ; CHECK-LABEL: bb.{{.*}}.nextbb
%2 = mul i32 %0, %arg1, !dbg !26 %2 = mul i32 %0, %arg1, !dbg !26
; CHECK: IMUL32rr ; CHECK: IMUL32rr
call void @llvm.dbg.value(metadata i32 %1, metadata !16, metadata !DIExpression()), !dbg !27 call void @llvm.dbg.value(metadata i32 %1, metadata !16, metadata !DIExpression()), !dbg !27
; INSTRREF-NEXT: DBG_INSTR_REF 1, 0 ; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; DBGVALUE-NEXT: DBG_VALUE ; DBGVALUE-NEXT: DBG_VALUE
br label %exit, !dbg !26 br label %exit, !dbg !26
; CHECK-LABEL: bb.{{.*}}.exit ; CHECK-LABEL: bb.{{.*}}.exit
exit: exit:
%3 = phi i32 [ 12, %entry ], [ %2, %nextbb ], !dbg !26 %3 = phi i32 [ 12, %entry ], [ %2, %nextbb ], !dbg !26
%4 = add i32 %1, %3, !dbg !26 %4 = add i32 %1, %3, !dbg !26
ret i32 %4, !dbg !26 ret i32 %4, !dbg !26
Show All 27 Lines

llvm/test/DebugInfo/X86/sdag-ir-salvage.ll

; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare \ ; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare \
; RUN: -stop-before finalize-isel %s -o - \ ; RUN: -stop-before finalize-isel %s -o - \
; RUN: -experimental-debug-variable-locations=false \ ; RUN: -experimental-debug-variable-locations=false \
; RUN: | FileCheck %s --check-prefixes=CHECK,DBGVALUE ; RUN: | FileCheck %s --check-prefixes=CHECK,DBGVALUE
; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare \ ; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare \
; RUN: -stop-before finalize-isel %s -o - \ ; RUN: -stop-before finalize-isel %s -o - \
; RUN: -experimental-debug-variable-locations=true \ ; RUN: -experimental-debug-variable-locations=true \
; RUN: | FileCheck %s --check-prefixes=CHECK,INSTRREF ; RUN: | FileCheck %s --check-prefixes=CHECK,INSTRREF
; Test that the dbg.value for %baz, which doesn't exist in the 'next' bb, ; Test that the dbg.value for %baz, which doesn't exist in the 'next' bb,
; can be salvaged back to the underlying argument vreg. ; can be salvaged back to the underlying argument vreg.
; CHECK: ![[AAAVAR:.*]] = !DILocalVariable(name: "aaa", ; CHECK: ![[AAAVAR:.*]] = !DILocalVariable(name: "aaa",
; CHECK-LABEL: bb.0.entry: ; CHECK-LABEL: bb.0.entry:
; INSTRREF: DBG_PHI $rdi, 1 ; INSTRREF: DBG_PHI $rdi, 1
; CHECK-LABEL: bb.1.next: ; CHECK-LABEL: bb.1.next:
; INSTRREF: DBG_INSTR_REF 1, 0, ![[AAAVAR]] ; INSTRREF: DBG_INSTR_REF ![[AAAVAR]], {{.+}}, dbg-instr-ref(1, 0)
; DBGVALUE: DBG_VALUE %{{[0-9]+}}, $noreg, ![[AAAVAR]] ; DBGVALUE: DBG_VALUE %{{[0-9]+}}, $noreg, ![[AAAVAR]]
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-linux-gnu" target triple = "x86_64-linux-gnu"
define i8 @f(i32* %foo) local_unnamed_addr !dbg !6 { define i8 @f(i32* %foo) local_unnamed_addr !dbg !6 {
entry: entry:
%bar = getelementptr i32, i32* %foo, i32 4 %bar = getelementptr i32, i32* %foo, i32 4
▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

llvm/test/DebugInfo/X86/sdag-salvage-add.ll

Show All 28 Lines
; ;
; NB: instruction referencing and DBG_VALUE modes produce debug insts in a ; NB: instruction referencing and DBG_VALUE modes produce debug insts in a
; different order. ; different order.
; ;
; CHECK: ![[S4:.*]] = !DILocalVariable(name: "s4", ; CHECK: ![[S4:.*]] = !DILocalVariable(name: "s4",
; CHECK: ![[MYVAR:.*]] = !DILocalVariable(name: "myVar", ; CHECK: ![[MYVAR:.*]] = !DILocalVariable(name: "myVar",
; CHECK: $rax = MOV64rm ; CHECK: $rax = MOV64rm
; INSTRREF-SAME: debug-instr-number 2, ; INSTRREF-SAME: debug-instr-number 2,
; INSTRREF-NEXT: DBG_INSTR_REF 2, 0, ![[S4]], ; INSTRREF-NEXT: DBG_INSTR_REF ![[S4]],
; DBGVALUE-NEXT: DBG_VALUE $rax, $noreg, ![[MYVAR]], ; DBGVALUE-NEXT: DBG_VALUE $rax, $noreg, ![[MYVAR]],
; CHECK-SAME: !DIExpression(DW_OP_plus_uconst, 4096, DW_OP_stack_value) ; DBGVALUE-SAME: !DIExpression(DW_OP_plus_uconst, 4096, DW_OP_stack_value)
; INSTRREF-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_plus_uconst, 4096, DW_OP_stack_value)
; INSTRREF-SAME: dbg-instr-ref(2, 0)
; INSTRREF: DBG_INSTR_REF 2, 0, ![[MYVAR]], ; INSTRREF: DBG_INSTR_REF ![[MYVAR]],
; DBGVALUE: DBG_VALUE $rax, $noreg, ![[S4]], ; DBGVALUE: DBG_VALUE $rax, $noreg, ![[S4]],
; CHECK-SAME: !DIExpression(DW_OP_plus_uconst, 4096, DW_OP_stack_value) ; DBGVALUE-SAME: !DIExpression(DW_OP_plus_uconst, 4096, DW_OP_stack_value)
; INSTRREF-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_plus_uconst, 4096, DW_OP_stack_value)
; INSTRREF-SAME: dbg-instr-ref(2, 0)
; CHECK-NEXT: $rdi = MOV64rm killed renamable $rax, 1, $noreg, 4096, $noreg, ; CHECK-NEXT: $rdi = MOV64rm killed renamable $rax, 1, $noreg, 4096, $noreg,
source_filename = "test.c" source_filename = "test.c"
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.13.0" target triple = "x86_64-apple-macosx10.13.0"
%struct.S3 = type { i64 } %struct.S3 = type { i64 }
%struct.S4 = type opaque %struct.S4 = type opaque
▲ Show 20 Lines • Show All 72 Lines • Show Last 20 Lines

llvm/test/DebugInfo/X86/sdag-transfer-dbgvalue.ll

Show All 18 Lines
; } ; }
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
; CHECK-LABEL: bb.0.entry: ; CHECK-LABEL: bb.0.entry:
; CHECK: %[[REG:[0-9]+]]:gr32 = ADD32ri %1, 512, ; CHECK: %[[REG:[0-9]+]]:gr32 = ADD32ri %1, 512,
; INSTRREF-SAME: debug-instr-number 1 ; INSTRREF-SAME: debug-instr-number 1
; INSTRREF-NEXT: DBG_INSTR_REF 1, 0 ; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; DBGVALUE-NEXT: DBG_VALUE %[[REG]] ; DBGVALUE-NEXT: DBG_VALUE %[[REG]]
; Function Attrs: nofree norecurse nounwind uwtable writeonly ; Function Attrs: nofree norecurse nounwind uwtable writeonly
define dso_local i32 @foo(i32 %a, i32* nocapture %b) local_unnamed_addr !dbg !7 { define dso_local i32 @foo(i32 %a, i32* nocapture %b) local_unnamed_addr !dbg !7 {
entry: entry:
%add = add nsw i32 %a, 512, !dbg !18 %add = add nsw i32 %a, 512, !dbg !18
call void @llvm.dbg.value(metadata i32 %add, metadata !16, metadata !DIExpression()), !dbg !17 call void @llvm.dbg.value(metadata i32 %add, metadata !16, metadata !DIExpression()), !dbg !17
%cmp = icmp eq i32 %add, 0, !dbg !18 %cmp = icmp eq i32 %add, 0, !dbg !18
Show All 36 Lines

llvm/test/DebugInfo/X86/sdagsplit-1.ll

; RUN: llc %s -stop-after=livedebugvars -o %t -experimental-debug-variable-locations=true ; RUN: llc %s -stop-after=livedebugvars -o %t -experimental-debug-variable-locations=true
; RUN: cat %t | FileCheck %s ; RUN: cat %t | FileCheck %s
; ;
; Test that we can emit debug info for large values that are split ; Test that we can emit debug info for large values that are split
; up across multiple registers by the SelectionDAG type legalizer. ; up across multiple registers by the SelectionDAG type legalizer.
; ;
; // Compile with -O1 -m32. ; // Compile with -O1 -m32.
; long long foo (long long a, long long b) ; long long foo (long long a, long long b)
; { ; {
; long long res = b+1; ; long long res = b+1;
; if ( a == b ) ; if ( a == b )
; return res; ; return res;
; return 0; ; return 0;
; } ; }
; ;
; CHECK-DAG: DBG_VALUE ${{[a-z]+}}, $noreg, !{{[0-9]+}}, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location ; CHECK-DAG: DBG_VALUE_LIST !{{[0-9]+}}, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 0, 32), ${{[a-z]+}}, debug-location
; CHECK-DAG: DBG_VALUE ${{[a-z]+}}, $noreg, !{{[0-9]+}}, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location ; CHECK-DAG: DBG_VALUE_LIST !{{[0-9]+}}, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 32, 32), ${{[a-z]+}}, debug-location
; ModuleID = 'sdagsplit-1.c' ; ModuleID = 'sdagsplit-1.c'
target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128" target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
target triple = "i386" target triple = "i386"
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define i64 @foo(i64 %a, i64 %b) local_unnamed_addr #0 !dbg !8 { define i64 @foo(i64 %a, i64 %b) local_unnamed_addr #0 !dbg !8 {
entry: entry:
▲ Show 20 Lines • Show All 44 Lines • Show Last 20 Lines

llvm/test/DebugInfo/X86/spill-nospill.ll

Show All 18 Lines
; g(y); ; g(y);
; g(y); ; g(y);
; return x + y; ; return x + y;
; } ; }
; CHECK-LABEL: f: # @f ; CHECK-LABEL: f: # @f
; CHECK: callq g ; CHECK: callq g
; CHECK: movl %eax, [[X_OFFS:[0-9]+]](%rsp) # 4-byte Spill ; CHECK: movl %eax, [[X_OFFS:[0-9]+]](%rsp) # 4-byte Spill
; CHECK: #DEBUG_VALUE: f:x <- [DW_OP_plus_uconst [[X_OFFS]]] [$rsp+0] ; CHECK: #DEBUG_VALUE: f:x <- [DW_OP_plus_uconst [[X_OFFS]], DW_OP_deref] $rsp
; CHECK: #APP ; CHECK: #APP
; CHECK: #NO_APP ; CHECK: #NO_APP
; CHECK: callq g ; CHECK: callq g
; CHECK: movl %eax, %[[CSR:[^ ]*]] ; CHECK: movl %eax, %[[CSR:[^ ]*]]
; CHECK: #DEBUG_VALUE: f:y <- $esi ; CHECK: #DEBUG_VALUE: f:y <- $esi
; CHECK: movl %eax, %ecx ; CHECK: movl %eax, %ecx
; CHECK: callq g ; CHECK: callq g
; CHECK: movl %[[CSR]], %ecx ; CHECK: movl %[[CSR]], %ecx
▲ Show 20 Lines • Show All 77 Lines • Show Last 20 Lines