This is an archive of the discontinued LLVM Phabricator instance.

Differential D128187

[RISCV] Add ADDI instr to compute FrameIndex address for RVV
ClosedPublic

Authored by StephenFan on Jun 20 2022, 5:30 AM.

Details

Reviewers
frasercrmck
craig.topper
reames
jacquesguan
luismarques
kito-cheng
Commits
rGc06d0b4d02ea: [RISCV] Add ADDI instr for computing FrameIndex address
Summary

RVV doesn't have an immediate field for memory addressing. Currently,
we build MachineInstructions in PEI to computing stack offset for
RVV load store instructions. These instructions were added too late to
can be optimized by CSE, LICM... passes.

This patch makes FrameIndex SDNodes can't be matched in RVV Load Store
instruction selection patterns. So that the FrameIndex SDNodes would be
selected as ADDI GPR, targetframeindex, 0.

There are 2 advantages to such change:

  1. Stack objects address computing can be optimized by machine function passes.
  2. Since the ADDI instruction's destination register can be used as a temp register, we can save an emergency spill slot.

Diff Detail

Event Timeline

StephenFan created this revision.Jun 20 2022, 5:30 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 20 2022, 5:30 AM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 28 others. · View Herald Transcript
StephenFan requested review of this revision.Jun 20 2022, 5:30 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 20 2022, 5:30 AM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B170830: Diff 438349.Jun 20 2022, 5:31 AM
StephenFan retitled this revision from [RISCV] Add ADDI instr for computing FrameIndex address to [RISCV] Add ADDI instr to compute FrameIndex address for RVV.Jun 20 2022, 5:34 AM
StephenFan edited the summary of this revision. (Show Details)Jun 20 2022, 5:36 AM
StephenFan updated this revision to Diff 438353.Jun 20 2022, 5:40 AM

update.

Harbormaster completed remote builds in B170832: Diff 438353.Jun 20 2022, 5:41 AM
StephenFan updated this revision to Diff 438354.Jun 20 2022, 5:41 AM

Remove blank line

kito-cheng added inline comments.Jun 20 2022, 5:42 AM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
1830

This blank line seems added by accident?

Harbormaster completed remote builds in B170833: Diff 438354.Jun 20 2022, 5:42 AM
StephenFan added a parent revision: D128188: [RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset.Jun 20 2022, 5:48 AM
StephenFan marked an inline comment as done.
StephenFan added a reviewer: kito-cheng.Jun 20 2022, 5:53 AM
craig.topper accepted this revision.Jun 20 2022, 8:21 AM

LGTM

This revision is now accepted and ready to land.Jun 20 2022, 8:21 AM
craig.topper mentioned this in rG5e944e9eb72a: [RISCV] Refactor SelectAddrRegImm to not depend on SelectBaseAddr..Jun 26 2022, 11:15 AM
craig.topper added inline comments.Jun 26 2022, 11:15 AM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
1823

I did some refactoring in SelectAddrRegImm to remove the dependency on SelectBaseAddr. You can remove it in this patch.

This revision was landed with ongoing or failed builds.Jul 4 2022, 7:14 AM
Closed by commit rGc06d0b4d02ea: [RISCV] Add ADDI instr for computing FrameIndex address (authored by StephenFan). · Explain Why
This revision was automatically updated to reflect the committed changes.
StephenFan added a commit: rGc06d0b4d02ea: [RISCV] Add ADDI instr for computing FrameIndex address.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
4 lines
1 line
36 lines
test/
CodeGen/
RISCV/
rvv/
16 lines
98 lines
62 lines
162 lines
18 lines
24 lines
12 lines
24 lines
16 lines
111 lines
301 lines
148 lines
36 lines
5 lines
10 lines
24 lines
112 lines
140 lines
32 lines
24 lines
36 lines
16 lines
16 lines
16 lines
16 lines
16 lines
16 lines
8 lines
16 lines
16 lines
16 lines
8 lines
8 lines
8 lines
8 lines
16 lines
16 lines
3 lines
68 lines
4 lines
2 lines
19 lines
60 lines
72 lines
40 lines
7 lines
10 lines
18 lines
16 lines
16 lines
8 lines
8 lines
16 lines
16 lines
16 lines
8 lines
16 lines
16 lines
16 lines
16 lines
16 lines
16 lines
16 lines
16 lines
16 lines
12 lines
8 lines
8 lines
12 lines
8 lines
16 lines
8 lines
16 lines
8 lines
16 lines
8 lines
16 lines
8 lines
8 lines
8 lines
12 lines
18 lines
18 lines
12 lines
12 lines
12 lines
12 lines
12 lines
12 lines
12 lines
8 lines
16 lines
16 lines
16 lines
16 lines
16 lines
8 lines
12 lines
12 lines
8 lines
16 lines
8 lines
16 lines
8 lines
12 lines
60 lines
16 lines
16 lines
16 lines
16 lines
16 lines
16 lines
8 lines
16 lines
16 lines
16 lines
8 lines
16 lines
8 lines
8 lines
8 lines
16 lines
12 lines
16 lines
8 lines
16 lines
8 lines
8 lines
16 lines
16 lines
16 lines
8 lines
16 lines
74 lines
4 lines

Diff 438354

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Show First 20 Lines • Show All 281 Lines • ▼ Show 20 Lines
void RISCVDAGToDAGISel::addVectorLoadStoreOperands( void RISCVDAGToDAGISel::addVectorLoadStoreOperands(
SDNode *Node, unsigned Log2SEW, const SDLoc &DL, unsigned CurOp, SDNode *Node, unsigned Log2SEW, const SDLoc &DL, unsigned CurOp,
bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl<SDValue> &Operands, bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl<SDValue> &Operands,
bool IsLoad, MVT *IndexVT) { bool IsLoad, MVT *IndexVT) {
SDValue Chain = Node->getOperand(0); SDValue Chain = Node->getOperand(0);
SDValue Glue; SDValue Glue;
SDValue Base; Operands.push_back(Node->getOperand(CurOp++)); // Base pointer.
SelectBaseAddr(Node->getOperand(CurOp++), Base);
Operands.push_back(Base); // Base pointer.
if (IsStridedOrIndexed) { if (IsStridedOrIndexed) {
Operands.push_back(Node->getOperand(CurOp++)); // Index. Operands.push_back(Node->getOperand(CurOp++)); // Index.
if (IndexVT) if (IndexVT)
*IndexVT = Operands.back()->getSimpleValueType(0); *IndexVT = Operands.back()->getSimpleValueType(0);
} }
if (IsMasked) { if (IsMasked) {
▲ Show 20 Lines • Show All 1,516 Lines • ▼ Show 20 Lines if (isInt<12>(CN->getSExtValue())) {
Subtarget->getXLenVT()); Subtarget->getXLenVT());
return true; return true;
} }
} }
return false; return false;
} }
bool RISCVDAGToDAGISel::SelectBaseAddr(SDValue Addr, SDValue &Base) { bool RISCVDAGToDAGISel::SelectBaseAddr(SDValue Addr, SDValue &Base) {
craig.topperUnsubmitted
Not Done
ReplyInline Actions

I did some refactoring in SelectAddrRegImm to remove the dependency on SelectBaseAddr. You can remove it in this patch.

craig.topper: I did some refactoring in SelectAddrRegImm to remove the dependency on SelectBaseAddr. You can…
// If this is FrameIndex, select it directly. Otherwise just let it get // If this is FrameIndex, select it directly. Otherwise just let it get
// selected to a register independently. // selected to a register independently.
if (auto *FIN = dyn_cast<FrameIndexSDNode>(Addr)) if (auto *FIN = dyn_cast<FrameIndexSDNode>(Addr))
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), Subtarget->getXLenVT()); Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), Subtarget->getXLenVT());
else else
Base = Addr; Base = Addr;
return true; return true;
kito-chengUnsubmitted
Done
ReplyInline Actions

This blank line seems added by accident?

kito-cheng: This blank line seems added by accident?
} }
bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base, bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
SDValue &Offset) { SDValue &Offset) {
if (CurDAG->isBaseWithConstantOffset(Addr)) { if (CurDAG->isBaseWithConstantOffset(Addr)) {
auto *CN = cast<ConstantSDNode>(Addr.getOperand(1)); auto *CN = cast<ConstantSDNode>(Addr.getOperand(1));
if (isInt<12>(CN->getSExtValue())) { if (isInt<12>(CN->getSExtValue())) {
Offset = CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(Addr), Offset = CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(Addr),
▲ Show 20 Lines • Show All 593 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfo.td

Show First 20 Lines • Show All 367 Lines • ▼ Show 20 Lines
def uimm6gt32 : ImmLeaf<XLenVT, [{ def uimm6gt32 : ImmLeaf<XLenVT, [{
return isUInt<6>(Imm) && Imm > 32; return isUInt<6>(Imm) && Imm > 32;
}]>; }]>;
// Addressing modes. // Addressing modes.
// Necessary because a frameindex can't be matched directly in a pattern. // Necessary because a frameindex can't be matched directly in a pattern.
def FrameAddrRegImm : ComplexPattern<iPTR, 2, "SelectFrameAddrRegImm", def FrameAddrRegImm : ComplexPattern<iPTR, 2, "SelectFrameAddrRegImm",
[frameindex, or, add]>; [frameindex, or, add]>;
def BaseAddr : ComplexPattern<iPTR, 1, "SelectBaseAddr">;
def AddrRegImm : ComplexPattern<iPTR, 2, "SelectAddrRegImm">; def AddrRegImm : ComplexPattern<iPTR, 2, "SelectAddrRegImm">;
// Return the negation of an immediate value. // Return the negation of an immediate value.
def NegImm : SDNodeXForm<imm, [{ def NegImm : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(-N->getSExtValue(), SDLoc(N), return CurDAG->getTargetConstant(-N->getSExtValue(), SDLoc(N),
N->getValueType(0)); N->getValueType(0));
}]>; }]>;
▲ Show 20 Lines • Show All 1,266 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Show All 28 Linesmulticlass VPatUSLoadStoreSDNode<ValueType type,
LMULInfo vlmul, LMULInfo vlmul,
OutPatFrag avl, OutPatFrag avl,
VReg reg_class, VReg reg_class,
int sew = !shl(1, log2sew)> int sew = !shl(1, log2sew)>
{ {
defvar load_instr = !cast<Instruction>("PseudoVLE"#sew#"_V_"#vlmul.MX); defvar load_instr = !cast<Instruction>("PseudoVLE"#sew#"_V_"#vlmul.MX);
defvar store_instr = !cast<Instruction>("PseudoVSE"#sew#"_V_"#vlmul.MX); defvar store_instr = !cast<Instruction>("PseudoVSE"#sew#"_V_"#vlmul.MX);
// Load // Load
def : Pat<(type (load BaseAddr:$rs1)), def : Pat<(type (load GPR:$rs1)),
(load_instr BaseAddr:$rs1, avl, log2sew)>; (load_instr GPR:$rs1, avl, log2sew)>;
// Store // Store
def : Pat<(store type:$rs2, BaseAddr:$rs1), def : Pat<(store type:$rs2, GPR:$rs1),
(store_instr reg_class:$rs2, BaseAddr:$rs1, avl, log2sew)>; (store_instr reg_class:$rs2, GPR:$rs1, avl, log2sew)>;
} }
multiclass VPatUSLoadStoreWholeVRSDNode<ValueType type, multiclass VPatUSLoadStoreWholeVRSDNode<ValueType type,
int log2sew, int log2sew,
LMULInfo vlmul, LMULInfo vlmul,
VReg reg_class, VReg reg_class,
int sew = !shl(1, log2sew)> int sew = !shl(1, log2sew)>
{ {
defvar load_instr = defvar load_instr =
!cast<Instruction>("VL"#!substr(vlmul.MX, 1)#"RE"#sew#"_V"); !cast<Instruction>("VL"#!substr(vlmul.MX, 1)#"RE"#sew#"_V");
defvar store_instr = defvar store_instr =
!cast<Instruction>("VS"#!substr(vlmul.MX, 1)#"R_V"); !cast<Instruction>("VS"#!substr(vlmul.MX, 1)#"R_V");
// Load // Load
def : Pat<(type (load BaseAddr:$rs1)), def : Pat<(type (load GPR:$rs1)),
(load_instr BaseAddr:$rs1)>; (load_instr GPR:$rs1)>;
// Store // Store
def : Pat<(store type:$rs2, BaseAddr:$rs1), def : Pat<(store type:$rs2, GPR:$rs1),
(store_instr reg_class:$rs2, BaseAddr:$rs1)>; (store_instr reg_class:$rs2, GPR:$rs1)>;
} }
multiclass VPatUSLoadStoreMaskSDNode<MTypeInfo m> multiclass VPatUSLoadStoreMaskSDNode<MTypeInfo m>
{ {
defvar load_instr = !cast<Instruction>("PseudoVLM_V_"#m.BX); defvar load_instr = !cast<Instruction>("PseudoVLM_V_"#m.BX);
defvar store_instr = !cast<Instruction>("PseudoVSM_V_"#m.BX); defvar store_instr = !cast<Instruction>("PseudoVSM_V_"#m.BX);
// Load // Load
def : Pat<(m.Mask (load BaseAddr:$rs1)), def : Pat<(m.Mask (load GPR:$rs1)),
(load_instr BaseAddr:$rs1, m.AVL, m.Log2SEW)>; (load_instr GPR:$rs1, m.AVL, m.Log2SEW)>;
// Store // Store
def : Pat<(store m.Mask:$rs2, BaseAddr:$rs1), def : Pat<(store m.Mask:$rs2, GPR:$rs1),
(store_instr VR:$rs2, BaseAddr:$rs1, m.AVL, m.Log2SEW)>; (store_instr VR:$rs2, GPR:$rs1, m.AVL, m.Log2SEW)>;
} }
class VPatBinarySDNode_VV<SDNode vop, class VPatBinarySDNode_VV<SDNode vop,
string instruction_name, string instruction_name,
ValueType result_type, ValueType result_type,
ValueType op_type, ValueType op_type,
int sew, int sew,
LMULInfo vlmul, LMULInfo vlmul,
▲ Show 20 Lines • Show All 952 Lines • ▼ Show 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Vector Element Extracts // Vector Element Extracts
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasVInstructionsAnyF] in let Predicates = [HasVInstructionsAnyF] in
foreach vti = AllFloatVectors in { foreach vti = AllFloatVectors in {
// Fold store of vmv.f.s to a vse with VL=1. // Fold store of vmv.f.s to a vse with VL=1.
defvar store_instr = !cast<Instruction>("PseudoVSE"#vti.SEW#"_V_"#vti.LMul.MX); defvar store_instr = !cast<Instruction>("PseudoVSE"#vti.SEW#"_V_"#vti.LMul.MX);
def : Pat<(store (vti.Scalar (int_riscv_vfmv_f_s (vti.Vector vti.RegClass:$rs2))), BaseAddr:$rs1),
(store_instr vti.RegClass:$rs2, BaseAddr:$rs1, 1, vti.Log2SEW)>; let AddedComplexity = 1 in {
def : Pat<(store (extractelt (vti.Vector vti.RegClass:$rs2), 0), BaseAddr:$rs1), // Add complexity to increase the priority of this pattern being matched.
(store_instr vti.RegClass:$rs2, BaseAddr:$rs1, 1, vti.Log2SEW)>; def : Pat<(store (vti.Scalar (int_riscv_vfmv_f_s (vti.Vector vti.RegClass:$rs2))), GPR:$rs1),
(store_instr vti.RegClass:$rs2, GPR:$rs1, 1, vti.Log2SEW)>;
def : Pat<(store (extractelt (vti.Vector vti.RegClass:$rs2), 0), GPR:$rs1),
(store_instr vti.RegClass:$rs2, GPR:$rs1, 1, vti.Log2SEW)>;
}
defvar vmv_f_s_inst = !cast<Instruction>(!strconcat("PseudoVFMV_", defvar vmv_f_s_inst = !cast<Instruction>(!strconcat("PseudoVFMV_",
vti.ScalarSuffix, vti.ScalarSuffix,
"_S_", vti.LMul.MX)); "_S_", vti.LMul.MX));
// Only pattern-match extract-element operations where the index is 0. Any // Only pattern-match extract-element operations where the index is 0. Any
// other index will have been custom-lowered to slide the vector correctly // other index will have been custom-lowered to slide the vector correctly
// into place. // into place.
def : Pat<(vti.Scalar (extractelt (vti.Vector vti.RegClass:$rs2), 0)), def : Pat<(vti.Scalar (extractelt (vti.Vector vti.RegClass:$rs2), 0)),
(vmv_f_s_inst vti.RegClass:$rs2, vti.Log2SEW)>; (vmv_f_s_inst vti.RegClass:$rs2, vti.Log2SEW)>;
} }

llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll

Show All 25 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @access_fixed_and_vector_objects(i64 *%val) { define <vscale x 1 x i64> @access_fixed_and_vector_objects(i64 *%val) {
; RV64IV-LABEL: access_fixed_and_vector_objects: ; RV64IV-LABEL: access_fixed_and_vector_objects:
; RV64IV: # %bb.0: ; RV64IV: # %bb.0:
; RV64IV-NEXT: addi sp, sp, -544 ; RV64IV-NEXT: addi sp, sp, -528
; RV64IV-NEXT: .cfi_def_cfa_offset 544 ; RV64IV-NEXT: .cfi_def_cfa_offset 528
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: sub sp, sp, a0 ; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: addi a0, sp, 24 ; RV64IV-NEXT: addi a0, sp, 8
; RV64IV-NEXT: vl1re64.v v8, (a0) ; RV64IV-NEXT: vl1re64.v v8, (a0)
; RV64IV-NEXT: ld a0, 536(sp) ; RV64IV-NEXT: addi a0, sp, 528
; RV64IV-NEXT: addi a1, sp, 544 ; RV64IV-NEXT: ld a1, 520(sp)
; RV64IV-NEXT: vl1re64.v v9, (a1) ; RV64IV-NEXT: vl1re64.v v9, (a0)
; RV64IV-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; RV64IV-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64IV-NEXT: vadd.vv v8, v8, v9 ; RV64IV-NEXT: vadd.vv v8, v8, v9
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: add sp, sp, a0 ; RV64IV-NEXT: add sp, sp, a0
; RV64IV-NEXT: addi sp, sp, 544 ; RV64IV-NEXT: addi sp, sp, 528
; RV64IV-NEXT: ret ; RV64IV-NEXT: ret
%local = alloca i64 %local = alloca i64
%vector = alloca <vscale x 1 x i64> %vector = alloca <vscale x 1 x i64>
%array = alloca [64 x i64] %array = alloca [64 x i64]
%vptr = bitcast [64 x i64]* %array to <vscale x 1 x i64>* %vptr = bitcast [64 x i64]* %array to <vscale x 1 x i64>*
%v1 = load <vscale x 1 x i64>, <vscale x 1 x i64>* %vptr %v1 = load <vscale x 1 x i64>, <vscale x 1 x i64>* %vptr
%v2 = load <vscale x 1 x i64>, <vscale x 1 x i64>* %vector %v2 = load <vscale x 1 x i64>, <vscale x 1 x i64>* %vector
%len = load i64, i64* %local %len = load i64, i64* %local
Show All 9 Lines

llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll

Show First 20 Lines • Show All 1,010 Lines • ▼ Show 20 Lines
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: addi a1, sp, 8 ; RV32-NEXT: addi a1, sp, 8
; RV32-NEXT: vlse64.v v10, (a1), zero ; RV32-NEXT: vlse64.v v10, (a1), zero
; RV32-NEXT: vsrl.vi v11, v8, 24 ; RV32-NEXT: vsrl.vi v11, v8, 24
; RV32-NEXT: vand.vx v11, v11, a0 ; RV32-NEXT: vand.vx v11, v11, a0
; RV32-NEXT: vsrl.vi v12, v8, 8 ; RV32-NEXT: vsrl.vi v12, v8, 8
; RV32-NEXT: vand.vv v10, v12, v10 ; RV32-NEXT: vand.vv v10, v12, v10
; RV32-NEXT: vor.vv v10, v10, v11 ; RV32-NEXT: vor.vv v10, v10, v11
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v11, (a1), zero
; RV32-NEXT: vlse64.v v11, (a0), zero
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: vsll.vx v10, v8, a2 ; RV32-NEXT: vsll.vx v10, v8, a2
; RV32-NEXT: vsll.vx v12, v8, a3 ; RV32-NEXT: vsll.vx v12, v8, a3
; RV32-NEXT: vand.vv v11, v12, v11 ; RV32-NEXT: vand.vv v11, v12, v11
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v12, (a1), zero
; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vor.vv v10, v10, v11 ; RV32-NEXT: vor.vv v10, v10, v11
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v11, (a1), zero
; RV32-NEXT: vlse64.v v11, (a0), zero
; RV32-NEXT: vsll.vi v13, v8, 8 ; RV32-NEXT: vsll.vi v13, v8, 8
; RV32-NEXT: vand.vv v12, v13, v12 ; RV32-NEXT: vand.vv v12, v13, v12
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vand.vv v8, v8, v11 ; RV32-NEXT: vand.vv v8, v8, v11
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v11, (a1), zero
; RV32-NEXT: vlse64.v v11, (a0), zero
; RV32-NEXT: vor.vv v8, v10, v8 ; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: vsrl.vi v9, v8, 4 ; RV32-NEXT: vsrl.vi v9, v8, 4
; RV32-NEXT: vand.vv v9, v9, v11 ; RV32-NEXT: vand.vv v9, v9, v11
; RV32-NEXT: vand.vv v8, v8, v11 ; RV32-NEXT: vand.vv v8, v8, v11
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v10, (a1), zero
; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsll.vi v8, v8, 4 ; RV32-NEXT: vsll.vi v8, v8, 4
; RV32-NEXT: vor.vv v8, v9, v8 ; RV32-NEXT: vor.vv v8, v9, v8
; RV32-NEXT: vsrl.vi v9, v8, 2 ; RV32-NEXT: vsrl.vi v9, v8, 2
; RV32-NEXT: vand.vv v9, v9, v10 ; RV32-NEXT: vand.vv v9, v9, v10
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v10, (a1), zero
; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsll.vi v8, v8, 2 ; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vor.vv v8, v9, v8 ; RV32-NEXT: vor.vv v8, v9, v8
; RV32-NEXT: vsrl.vi v9, v8, 1 ; RV32-NEXT: vsrl.vi v9, v8, 1
; RV32-NEXT: vand.vv v9, v9, v10 ; RV32-NEXT: vand.vv v9, v9, v10
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: vadd.vv v8, v8, v8 ; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vor.vv v8, v9, v8 ; RV32-NEXT: vor.vv v8, v9, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: addi a1, sp, 8 ; RV32-NEXT: addi a1, sp, 8
; RV32-NEXT: vlse64.v v12, (a1), zero ; RV32-NEXT: vlse64.v v12, (a1), zero
; RV32-NEXT: vsrl.vi v14, v8, 24 ; RV32-NEXT: vsrl.vi v14, v8, 24
; RV32-NEXT: vand.vx v14, v14, a0 ; RV32-NEXT: vand.vx v14, v14, a0
; RV32-NEXT: vsrl.vi v16, v8, 8 ; RV32-NEXT: vsrl.vi v16, v8, 8
; RV32-NEXT: vand.vv v12, v16, v12 ; RV32-NEXT: vand.vv v12, v16, v12
; RV32-NEXT: vor.vv v12, v12, v14 ; RV32-NEXT: vor.vv v12, v12, v14
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v14, (a1), zero
; RV32-NEXT: vlse64.v v14, (a0), zero
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsll.vx v12, v8, a2 ; RV32-NEXT: vsll.vx v12, v8, a2
; RV32-NEXT: vsll.vx v16, v8, a3 ; RV32-NEXT: vsll.vx v16, v8, a3
; RV32-NEXT: vand.vv v14, v16, v14 ; RV32-NEXT: vand.vv v14, v16, v14
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v16, (a1), zero
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vor.vv v12, v12, v14 ; RV32-NEXT: vor.vv v12, v12, v14
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v14, (a1), zero
; RV32-NEXT: vlse64.v v14, (a0), zero
; RV32-NEXT: vsll.vi v18, v8, 8 ; RV32-NEXT: vsll.vi v18, v8, 8
; RV32-NEXT: vand.vv v16, v18, v16 ; RV32-NEXT: vand.vv v16, v18, v16
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vand.vv v8, v8, v14 ; RV32-NEXT: vand.vv v8, v8, v14
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v14, (a1), zero
; RV32-NEXT: vlse64.v v14, (a0), zero
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vsrl.vi v10, v8, 4 ; RV32-NEXT: vsrl.vi v10, v8, 4
; RV32-NEXT: vand.vv v10, v10, v14 ; RV32-NEXT: vand.vv v10, v10, v14
; RV32-NEXT: vand.vv v8, v8, v14 ; RV32-NEXT: vand.vv v8, v8, v14
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v12, (a1), zero
; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsll.vi v8, v8, 4 ; RV32-NEXT: vsll.vi v8, v8, 4
; RV32-NEXT: vor.vv v8, v10, v8 ; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: vsrl.vi v10, v8, 2 ; RV32-NEXT: vsrl.vi v10, v8, 2
; RV32-NEXT: vand.vv v10, v10, v12 ; RV32-NEXT: vand.vv v10, v10, v12
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v12, (a1), zero
; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsll.vi v8, v8, 2 ; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vor.vv v8, v10, v8 ; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: vsrl.vi v10, v8, 1 ; RV32-NEXT: vsrl.vi v10, v8, 1
; RV32-NEXT: vand.vv v10, v10, v12 ; RV32-NEXT: vand.vv v10, v10, v12
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: vadd.vv v8, v8, v8 ; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vor.vv v8, v10, v8 ; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: addi a1, sp, 8 ; RV32-NEXT: addi a1, sp, 8
; RV32-NEXT: vlse64.v v16, (a1), zero ; RV32-NEXT: vlse64.v v16, (a1), zero
; RV32-NEXT: vsrl.vi v20, v8, 24 ; RV32-NEXT: vsrl.vi v20, v8, 24
; RV32-NEXT: vand.vx v20, v20, a0 ; RV32-NEXT: vand.vx v20, v20, a0
; RV32-NEXT: vsrl.vi v24, v8, 8 ; RV32-NEXT: vsrl.vi v24, v8, 8
; RV32-NEXT: vand.vv v16, v24, v16 ; RV32-NEXT: vand.vv v16, v24, v16
; RV32-NEXT: vor.vv v16, v16, v20 ; RV32-NEXT: vor.vv v16, v16, v20
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v20, (a1), zero
; RV32-NEXT: vlse64.v v20, (a0), zero
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsll.vx v16, v8, a2 ; RV32-NEXT: vsll.vx v16, v8, a2
; RV32-NEXT: vsll.vx v24, v8, a3 ; RV32-NEXT: vsll.vx v24, v8, a3
; RV32-NEXT: vand.vv v20, v24, v20 ; RV32-NEXT: vand.vv v20, v24, v20
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v24, (a1), zero
; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vor.vv v16, v16, v20 ; RV32-NEXT: vor.vv v16, v16, v20
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v20, (a1), zero
; RV32-NEXT: vlse64.v v20, (a0), zero
; RV32-NEXT: vsll.vi v28, v8, 8 ; RV32-NEXT: vsll.vi v28, v8, 8
; RV32-NEXT: vand.vv v24, v28, v24 ; RV32-NEXT: vand.vv v24, v28, v24
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vand.vv v8, v8, v20 ; RV32-NEXT: vand.vv v8, v8, v20
; RV32-NEXT: vor.vv v8, v8, v24 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v20, (a1), zero
; RV32-NEXT: vlse64.v v20, (a0), zero
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: vsrl.vi v12, v8, 4 ; RV32-NEXT: vsrl.vi v12, v8, 4
; RV32-NEXT: vand.vv v12, v12, v20 ; RV32-NEXT: vand.vv v12, v12, v20
; RV32-NEXT: vand.vv v8, v8, v20 ; RV32-NEXT: vand.vv v8, v8, v20
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v16, (a1), zero
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsll.vi v8, v8, 4 ; RV32-NEXT: vsll.vi v8, v8, 4
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vsrl.vi v12, v8, 2 ; RV32-NEXT: vsrl.vi v12, v8, 2
; RV32-NEXT: vand.vv v12, v12, v16 ; RV32-NEXT: vand.vv v12, v12, v16
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v16, (a1), zero
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsll.vi v8, v8, 2 ; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vsrl.vi v12, v8, 1 ; RV32-NEXT: vsrl.vi v12, v8, 1
; RV32-NEXT: vand.vv v12, v12, v16 ; RV32-NEXT: vand.vv v12, v12, v16
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vadd.vv v8, v8, v8 ; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a2, 12(sp) ; RV32-NEXT: sw a2, 12(sp)
; RV32-NEXT: sw a2, 8(sp) ; RV32-NEXT: sw a2, 8(sp)
; RV32-NEXT: lui a2, 349525 ; RV32-NEXT: lui a2, 349525
; RV32-NEXT: addi a2, a2, 1365 ; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: sw a2, 12(sp) ; RV32-NEXT: sw a2, 12(sp)
; RV32-NEXT: sw a2, 8(sp) ; RV32-NEXT: sw a2, 8(sp)
; RV32-NEXT: li a2, 56 ; RV32-NEXT: li a2, 56
; RV32-NEXT: vsetvli a3, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a3, zero, e64, m8, ta, mu
; RV32-NEXT: vsrl.vx v16, v8, a2
; RV32-NEXT: li a3, 40 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vsrl.vx v24, v8, a3 ; RV32-NEXT: vsrl.vx v16, v8, a3
; RV32-NEXT: addi a4, sp, 8 ; RV32-NEXT: vand.vx v16, v16, a1
; RV32-NEXT: vlse64.v v0, (a4), zero ; RV32-NEXT: addi a1, sp, 8
; RV32-NEXT: vand.vx v24, v24, a1 ; RV32-NEXT: vlse64.v v24, (a1), zero
; RV32-NEXT: vor.vv v16, v24, v16 ; RV32-NEXT: vsrl.vx v0, v8, a2
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: slli a4, a4, 3
; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vsrl.vi v24, v8, 8 ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vand.vv v24, v24, v0 ; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: vand.vv v24, v0, v24
; RV32-NEXT: vsrl.vi v0, v8, 24 ; RV32-NEXT: vsrl.vi v0, v8, 24
; RV32-NEXT: vand.vx v0, v0, a0 ; RV32-NEXT: vand.vx v0, v0, a0
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v16, (a1), zero
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8re8.v v0, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8re8.v v0, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsll.vx v24, v8, a3 ; RV32-NEXT: vsll.vx v24, v8, a3
; RV32-NEXT: vand.vv v16, v24, v16 ; RV32-NEXT: vand.vv v16, v24, v16
; RV32-NEXT: vsll.vx v24, v8, a2 ; RV32-NEXT: vsll.vx v24, v8, a2
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v0, (a1), zero
; RV32-NEXT: vlse64.v v0, (a0), zero
; RV32-NEXT: vor.vv v16, v24, v16 ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v16, (a1), zero
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsll.vi v24, v8, 8 ; RV32-NEXT: vsll.vi v24, v8, 8
; RV32-NEXT: vand.vv v24, v24, v0 ; RV32-NEXT: vand.vv v24, v24, v0
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vor.vv v8, v8, v24 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v16, (a1), zero
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8re8.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8re8.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v24, v8 ; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8re8.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8re8.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v24 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vsrl.vi v24, v8, 4 ; RV32-NEXT: vsrl.vi v24, v8, 4
; RV32-NEXT: vand.vv v24, v24, v16 ; RV32-NEXT: vand.vv v24, v24, v16
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v16, (a1), zero
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsll.vi v8, v8, 4 ; RV32-NEXT: vsll.vi v8, v8, 4
; RV32-NEXT: vor.vv v8, v24, v8 ; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: vsrl.vi v24, v8, 2 ; RV32-NEXT: vsrl.vi v24, v8, 2
; RV32-NEXT: vand.vv v24, v24, v16 ; RV32-NEXT: vand.vv v24, v24, v16
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v16, (a1), zero
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsll.vi v8, v8, 2 ; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vor.vv v8, v24, v8 ; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: vsrl.vi v24, v8, 1 ; RV32-NEXT: vsrl.vi v24, v8, 1
; RV32-NEXT: vand.vv v24, v24, v16 ; RV32-NEXT: vand.vv v24, v24, v16
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vadd.vv v8, v8, v8 ; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vor.vv v8, v24, v8 ; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
▲ Show 20 Lines • Show All 65 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll

Show First 20 Lines • Show All 299 Lines • ▼ Show 20 Lines
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: addi a1, sp, 8 ; RV32-NEXT: addi a1, sp, 8
; RV32-NEXT: vlse64.v v10, (a1), zero ; RV32-NEXT: vlse64.v v10, (a1), zero
; RV32-NEXT: vsrl.vi v11, v8, 24 ; RV32-NEXT: vsrl.vi v11, v8, 24
; RV32-NEXT: vand.vx v11, v11, a0 ; RV32-NEXT: vand.vx v11, v11, a0
; RV32-NEXT: vsrl.vi v12, v8, 8 ; RV32-NEXT: vsrl.vi v12, v8, 8
; RV32-NEXT: vand.vv v10, v12, v10 ; RV32-NEXT: vand.vv v10, v12, v10
; RV32-NEXT: vor.vv v10, v10, v11 ; RV32-NEXT: vor.vv v10, v10, v11
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v11, (a1), zero
; RV32-NEXT: vlse64.v v11, (a0), zero
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: vsll.vx v10, v8, a2 ; RV32-NEXT: vsll.vx v10, v8, a2
; RV32-NEXT: vsll.vx v12, v8, a3 ; RV32-NEXT: vsll.vx v12, v8, a3
; RV32-NEXT: vand.vv v11, v12, v11 ; RV32-NEXT: vand.vv v11, v12, v11
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v12, (a1), zero
; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vor.vv v10, v10, v11 ; RV32-NEXT: vor.vv v10, v10, v11
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v11, (a1), zero
; RV32-NEXT: vlse64.v v11, (a0), zero
; RV32-NEXT: vsll.vi v13, v8, 8 ; RV32-NEXT: vsll.vi v13, v8, 8
; RV32-NEXT: vand.vv v12, v13, v12 ; RV32-NEXT: vand.vv v12, v13, v12
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vand.vv v8, v8, v11 ; RV32-NEXT: vand.vv v8, v8, v11
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: vor.vv v8, v10, v8 ; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: addi a1, sp, 8 ; RV32-NEXT: addi a1, sp, 8
; RV32-NEXT: vlse64.v v12, (a1), zero ; RV32-NEXT: vlse64.v v12, (a1), zero
; RV32-NEXT: vsrl.vi v14, v8, 24 ; RV32-NEXT: vsrl.vi v14, v8, 24
; RV32-NEXT: vand.vx v14, v14, a0 ; RV32-NEXT: vand.vx v14, v14, a0
; RV32-NEXT: vsrl.vi v16, v8, 8 ; RV32-NEXT: vsrl.vi v16, v8, 8
; RV32-NEXT: vand.vv v12, v16, v12 ; RV32-NEXT: vand.vv v12, v16, v12
; RV32-NEXT: vor.vv v12, v12, v14 ; RV32-NEXT: vor.vv v12, v12, v14
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v14, (a1), zero
; RV32-NEXT: vlse64.v v14, (a0), zero
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsll.vx v12, v8, a2 ; RV32-NEXT: vsll.vx v12, v8, a2
; RV32-NEXT: vsll.vx v16, v8, a3 ; RV32-NEXT: vsll.vx v16, v8, a3
; RV32-NEXT: vand.vv v14, v16, v14 ; RV32-NEXT: vand.vv v14, v16, v14
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v16, (a1), zero
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vor.vv v12, v12, v14 ; RV32-NEXT: vor.vv v12, v12, v14
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v14, (a1), zero
; RV32-NEXT: vlse64.v v14, (a0), zero
; RV32-NEXT: vsll.vi v18, v8, 8 ; RV32-NEXT: vsll.vi v18, v8, 8
; RV32-NEXT: vand.vv v16, v18, v16 ; RV32-NEXT: vand.vv v16, v18, v16
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vand.vv v8, v8, v14 ; RV32-NEXT: vand.vv v8, v8, v14
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: addi a1, sp, 8 ; RV32-NEXT: addi a1, sp, 8
; RV32-NEXT: vlse64.v v16, (a1), zero ; RV32-NEXT: vlse64.v v16, (a1), zero
; RV32-NEXT: vsrl.vi v20, v8, 24 ; RV32-NEXT: vsrl.vi v20, v8, 24
; RV32-NEXT: vand.vx v20, v20, a0 ; RV32-NEXT: vand.vx v20, v20, a0
; RV32-NEXT: vsrl.vi v24, v8, 8 ; RV32-NEXT: vsrl.vi v24, v8, 8
; RV32-NEXT: vand.vv v16, v24, v16 ; RV32-NEXT: vand.vv v16, v24, v16
; RV32-NEXT: vor.vv v16, v16, v20 ; RV32-NEXT: vor.vv v16, v16, v20
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v20, (a1), zero
; RV32-NEXT: vlse64.v v20, (a0), zero
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsll.vx v16, v8, a2 ; RV32-NEXT: vsll.vx v16, v8, a2
; RV32-NEXT: vsll.vx v24, v8, a3 ; RV32-NEXT: vsll.vx v24, v8, a3
; RV32-NEXT: vand.vv v20, v24, v20 ; RV32-NEXT: vand.vv v20, v24, v20
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v24, (a1), zero
; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vor.vv v16, v16, v20 ; RV32-NEXT: vor.vv v16, v16, v20
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v20, (a1), zero
; RV32-NEXT: vlse64.v v20, (a0), zero
; RV32-NEXT: vsll.vi v28, v8, 8 ; RV32-NEXT: vsll.vi v28, v8, 8
; RV32-NEXT: vand.vv v24, v28, v24 ; RV32-NEXT: vand.vv v24, v28, v24
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vand.vv v8, v8, v20 ; RV32-NEXT: vand.vv v8, v8, v20
; RV32-NEXT: vor.vv v8, v8, v24 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw zero, 8(sp) ; RV32-NEXT: sw zero, 8(sp)
; RV32-NEXT: li a1, 255 ; RV32-NEXT: li a1, 255
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: lui a1, 16 ; RV32-NEXT: lui a1, 16
; RV32-NEXT: addi a1, a1, -256 ; RV32-NEXT: addi a1, a1, -256
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: li a2, 56 ; RV32-NEXT: li a2, 56
; RV32-NEXT: vsetvli a3, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a3, zero, e64, m8, ta, mu
; RV32-NEXT: vsrl.vx v16, v8, a2
; RV32-NEXT: li a3, 40 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vsrl.vx v24, v8, a3 ; RV32-NEXT: vsrl.vx v16, v8, a3
; RV32-NEXT: addi a4, sp, 8 ; RV32-NEXT: vand.vx v16, v16, a1
; RV32-NEXT: vlse64.v v0, (a4), zero ; RV32-NEXT: addi a1, sp, 8
; RV32-NEXT: vand.vx v24, v24, a1 ; RV32-NEXT: vlse64.v v24, (a1), zero
; RV32-NEXT: vor.vv v16, v24, v16 ; RV32-NEXT: vsrl.vx v0, v8, a2
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: slli a4, a4, 3
; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vsrl.vi v24, v8, 8 ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vand.vv v24, v24, v0 ; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: vand.vv v24, v0, v24
; RV32-NEXT: vsrl.vi v0, v8, 24 ; RV32-NEXT: vsrl.vi v0, v8, 24
; RV32-NEXT: vand.vx v0, v0, a0 ; RV32-NEXT: vand.vx v0, v0, a0
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v16, (a1), zero
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8re8.v v0, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8re8.v v0, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsll.vx v0, v8, a3 ; RV32-NEXT: vsll.vx v0, v8, a3
; RV32-NEXT: vand.vv v16, v0, v16 ; RV32-NEXT: vand.vv v16, v0, v16
; RV32-NEXT: vsll.vx v0, v8, a2 ; RV32-NEXT: vsll.vx v0, v8, a2
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v24, (a1), zero
; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vor.vv v16, v0, v16 ; RV32-NEXT: vor.vv v16, v0, v16
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v0, (a1), zero
; RV32-NEXT: vlse64.v v0, (a0), zero
; RV32-NEXT: vsll.vi v16, v8, 8 ; RV32-NEXT: vsll.vi v16, v8, 8
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vand.vv v8, v8, v0 ; RV32-NEXT: vand.vv v8, v8, v0
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll

Show First 20 Lines • Show All 296 Lines • ▼ Show 20 Lines
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: andi sp, sp, -128 ; RV32-NEXT: andi sp, sp, -128
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a3, a0, a1 ; RV32-NEXT: add a3, a0, a1
; RV32-NEXT: vl8re32.v v24, (a3) ; RV32-NEXT: vl8re32.v v24, (a3)
; RV32-NEXT: vl8re32.v v0, (a0) ; RV32-NEXT: vl8re32.v v0, (a0)
; RV32-NEXT: addi a0, sp, 128 ; RV32-NEXT: addi a0, sp, 128
; RV32-NEXT: add a0, a0, a1 ; RV32-NEXT: vs8r.v v8, (a0)
; RV32-NEXT: vs8r.v v16, (a0) ; RV32-NEXT: add a1, a0, a1
; RV32-NEXT: addi a0, sp, 128 ; RV32-NEXT: addi a0, sp, 128
; RV32-NEXT: li a3, 2 ; RV32-NEXT: li a3, 2
; RV32-NEXT: addi a1, sp, 128 ; RV32-NEXT: vs8r.v v16, (a1)
; RV32-NEXT: vs8r.v v8, (a1)
; RV32-NEXT: vmv8r.v v8, v0 ; RV32-NEXT: vmv8r.v v8, v0
; RV32-NEXT: vmv8r.v v16, v24 ; RV32-NEXT: vmv8r.v v16, v24
; RV32-NEXT: call ext2@plt ; RV32-NEXT: call ext2@plt
; RV32-NEXT: addi sp, s0, -144 ; RV32-NEXT: addi sp, s0, -144
; RV32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload ; RV32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 144 ; RV32-NEXT: addi sp, sp, 144
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
Show All 10 Lines
; RV64-NEXT: sub sp, sp, a1 ; RV64-NEXT: sub sp, sp, a1
; RV64-NEXT: andi sp, sp, -128 ; RV64-NEXT: andi sp, sp, -128
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3 ; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a3, a0, a1 ; RV64-NEXT: add a3, a0, a1
; RV64-NEXT: vl8re32.v v24, (a3) ; RV64-NEXT: vl8re32.v v24, (a3)
; RV64-NEXT: vl8re32.v v0, (a0) ; RV64-NEXT: vl8re32.v v0, (a0)
; RV64-NEXT: addi a0, sp, 128 ; RV64-NEXT: addi a0, sp, 128
; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: vs8r.v v8, (a0)
; RV64-NEXT: vs8r.v v16, (a0) ; RV64-NEXT: add a1, a0, a1
; RV64-NEXT: addi a0, sp, 128 ; RV64-NEXT: addi a0, sp, 128
; RV64-NEXT: li a3, 2 ; RV64-NEXT: li a3, 2
; RV64-NEXT: addi a1, sp, 128 ; RV64-NEXT: vs8r.v v16, (a1)
; RV64-NEXT: vs8r.v v8, (a1)
; RV64-NEXT: vmv8r.v v8, v0 ; RV64-NEXT: vmv8r.v v8, v0
; RV64-NEXT: vmv8r.v v16, v24 ; RV64-NEXT: vmv8r.v v16, v24
; RV64-NEXT: call ext2@plt ; RV64-NEXT: call ext2@plt
; RV64-NEXT: addi sp, s0, -144 ; RV64-NEXT: addi sp, s0, -144
; RV64-NEXT: ld ra, 136(sp) # 8-byte Folded Reload ; RV64-NEXT: ld ra, 136(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 144 ; RV64-NEXT: addi sp, sp, 144
; RV64-NEXT: ret ; RV64-NEXT: ret
%t = call fastcc <vscale x 32 x i32> @ext2(<vscale x 32 x i32> %y, <vscale x 32 x i32> %x, i32 %w, i32 2) %t = call fastcc <vscale x 32 x i32> @ext2(<vscale x 32 x i32> %y, <vscale x 32 x i32> %x, i32 %w, i32 2)
Show All 20 Lines
; RV32-NEXT: vl8re32.v v24, (a3) ; RV32-NEXT: vl8re32.v v24, (a3)
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3 ; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 128 ; RV32-NEXT: addi a3, a3, 128
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: add a3, a0, a1 ; RV32-NEXT: add a3, a0, a1
; RV32-NEXT: vl8re32.v v24, (a3) ; RV32-NEXT: vl8re32.v v24, (a3)
; RV32-NEXT: addi a3, sp, 128
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vl8re32.v v0, (a2) ; RV32-NEXT: vl8re32.v v0, (a2)
; RV32-NEXT: addi a2, sp, 128 ; RV32-NEXT: vl8re32.v v24, (a0)
; RV32-NEXT: vs8r.v v0, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vl8re32.v v0, (a0)
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 128 ; RV32-NEXT: addi a0, a0, 128
; RV32-NEXT: vs8r.v v8, (a0)
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 5
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 128
; RV32-NEXT: vs8r.v v24, (a2)
; RV32-NEXT: add a0, a0, a1 ; RV32-NEXT: add a0, a0, a1
; RV32-NEXT: vs8r.v v16, (a0) ; RV32-NEXT: vs8r.v v16, (a0)
; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 128 ; RV32-NEXT: addi a0, a0, 128
; RV32-NEXT: add a0, a0, a1 ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: vs8r.v v24, (a0) ; RV32-NEXT: slli a2, a2, 4
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: addi a2, a2, 128
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 128
; RV32-NEXT: vs8r.v v8, (a0)
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 128
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a2, a1, 128
; RV32-NEXT: li a5, 42 ; RV32-NEXT: li a5, 42
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: addi a3, sp, 128
; RV32-NEXT: slli a1, a1, 5 ; RV32-NEXT: vl8re8.v v8, (a3) # Unknown-size Folded Reload
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: vs8r.v v8, (a1)
; RV32-NEXT: addi a1, a1, 128 ; RV32-NEXT: vmv8r.v v8, v0
; RV32-NEXT: vs8r.v v0, (a1)
; RV32-NEXT: addi a1, sp, 128
; RV32-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 128 ; RV32-NEXT: addi a1, a1, 128
; RV32-NEXT: vl8re8.v v16, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vl8re8.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: call ext3@plt ; RV32-NEXT: call ext3@plt
; RV32-NEXT: addi sp, s0, -144 ; RV32-NEXT: addi sp, s0, -144
; RV32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload ; RV32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
Show All 19 Lines
; RV64-NEXT: vl8re32.v v24, (a3) ; RV64-NEXT: vl8re32.v v24, (a3)
; RV64-NEXT: csrr a3, vlenb ; RV64-NEXT: csrr a3, vlenb
; RV64-NEXT: slli a3, a3, 3 ; RV64-NEXT: slli a3, a3, 3
; RV64-NEXT: add a3, sp, a3 ; RV64-NEXT: add a3, sp, a3
; RV64-NEXT: addi a3, a3, 128 ; RV64-NEXT: addi a3, a3, 128
; RV64-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV64-NEXT: add a3, a0, a1 ; RV64-NEXT: add a3, a0, a1
; RV64-NEXT: vl8re32.v v24, (a3) ; RV64-NEXT: vl8re32.v v24, (a3)
; RV64-NEXT: addi a3, sp, 128
; RV64-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV64-NEXT: vl8re32.v v0, (a2) ; RV64-NEXT: vl8re32.v v0, (a2)
; RV64-NEXT: addi a2, sp, 128 ; RV64-NEXT: vl8re32.v v24, (a0)
; RV64-NEXT: vs8r.v v0, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vl8re32.v v0, (a0)
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4 ; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0 ; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 128 ; RV64-NEXT: addi a0, a0, 128
; RV64-NEXT: vs8r.v v8, (a0)
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a2, a2, 5
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 128
; RV64-NEXT: vs8r.v v24, (a2)
; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: vs8r.v v16, (a0) ; RV64-NEXT: vs8r.v v16, (a0)
; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 5 ; RV64-NEXT: slli a0, a0, 5
; RV64-NEXT: add a0, sp, a0 ; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 128 ; RV64-NEXT: addi a0, a0, 128
; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: vs8r.v v24, (a0) ; RV64-NEXT: slli a2, a2, 4
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: slli a0, a0, 4 ; RV64-NEXT: addi a2, a2, 128
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 128
; RV64-NEXT: vs8r.v v8, (a0)
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 5
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 128
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 4
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a2, a1, 128
; RV64-NEXT: li a5, 42 ; RV64-NEXT: li a5, 42
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: addi a3, sp, 128
; RV64-NEXT: slli a1, a1, 5 ; RV64-NEXT: vl8re8.v v8, (a3) # Unknown-size Folded Reload
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: vs8r.v v8, (a1)
; RV64-NEXT: addi a1, a1, 128 ; RV64-NEXT: vmv8r.v v8, v0
; RV64-NEXT: vs8r.v v0, (a1)
; RV64-NEXT: addi a1, sp, 128
; RV64-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3 ; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 128 ; RV64-NEXT: addi a1, a1, 128
; RV64-NEXT: vl8re8.v v16, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8re8.v v16, (a1) # Unknown-size Folded Reload
; RV64-NEXT: call ext3@plt ; RV64-NEXT: call ext3@plt
; RV64-NEXT: addi sp, s0, -144 ; RV64-NEXT: addi sp, s0, -144
; RV64-NEXT: ld ra, 136(sp) # 8-byte Folded Reload ; RV64-NEXT: ld ra, 136(sp) # 8-byte Folded Reload
Show All 33 Lines
; RV32-NEXT: addi s0, sp, 144 ; RV32-NEXT: addi s0, sp, 144
; RV32-NEXT: .cfi_def_cfa s0, 0 ; RV32-NEXT: .cfi_def_cfa s0, 0
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: sub sp, sp, a0 ; RV32-NEXT: sub sp, sp, a0
; RV32-NEXT: andi sp, sp, -128 ; RV32-NEXT: andi sp, sp, -128
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, mu
; RV32-NEXT: vmv.v.i v8, 0
; RV32-NEXT: addi a1, sp, 128 ; RV32-NEXT: addi a1, sp, 128
; RV32-NEXT: vs8r.v v8, (a1)
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 4
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 128
; RV32-NEXT: vs8r.v v8, (a2)
; RV32-NEXT: add a1, a1, a0 ; RV32-NEXT: add a1, a1, a0
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, mu
; RV32-NEXT: vmv.v.i v8, 0
; RV32-NEXT: vs8r.v v8, (a1) ; RV32-NEXT: vs8r.v v8, (a1)
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: add a0, a2, a0
; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 128
; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: vs8r.v v8, (a0)
; RV32-NEXT: addi a0, sp, 128
; RV32-NEXT: vs8r.v v8, (a0)
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: li a2, 2 ; RV32-NEXT: li a2, 2
; RV32-NEXT: li a3, 3 ; RV32-NEXT: li a3, 3
; RV32-NEXT: li a4, 4 ; RV32-NEXT: li a4, 4
; RV32-NEXT: li a5, 5 ; RV32-NEXT: li a5, 5
; RV32-NEXT: li a6, 6 ; RV32-NEXT: li a6, 6
; RV32-NEXT: li a7, 7 ; RV32-NEXT: li a7, 7
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr t0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli t0, t0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add t0, sp, t0
; RV32-NEXT: addi t2, a0, 128 ; RV32-NEXT: addi t2, t0, 128
; RV32-NEXT: addi t4, sp, 128 ; RV32-NEXT: addi t4, sp, 128
; RV32-NEXT: li t6, 8 ; RV32-NEXT: li t6, 8
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 128
; RV32-NEXT: vs8r.v v8, (a0) ; RV32-NEXT: vs8r.v v8, (a0)
; RV32-NEXT: li a0, 0 ; RV32-NEXT: li a0, 0
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: call vector_arg_indirect_stack@plt ; RV32-NEXT: call vector_arg_indirect_stack@plt
; RV32-NEXT: addi sp, s0, -144 ; RV32-NEXT: addi sp, s0, -144
; RV32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload ; RV32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 144 ; RV32-NEXT: addi sp, sp, 144
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: pass_vector_arg_indirect_stack: ; RV64-LABEL: pass_vector_arg_indirect_stack:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -144 ; RV64-NEXT: addi sp, sp, -144
; RV64-NEXT: .cfi_def_cfa_offset 144 ; RV64-NEXT: .cfi_def_cfa_offset 144
; RV64-NEXT: sd ra, 136(sp) # 8-byte Folded Spill ; RV64-NEXT: sd ra, 136(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8 ; RV64-NEXT: .cfi_offset ra, -8
; RV64-NEXT: addi s0, sp, 144 ; RV64-NEXT: addi s0, sp, 144
; RV64-NEXT: .cfi_def_cfa s0, 0 ; RV64-NEXT: .cfi_def_cfa s0, 0
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 5 ; RV64-NEXT: slli a0, a0, 5
; RV64-NEXT: sub sp, sp, a0 ; RV64-NEXT: sub sp, sp, a0
; RV64-NEXT: andi sp, sp, -128 ; RV64-NEXT: andi sp, sp, -128
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3 ; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: vsetvli a1, zero, e32, m8, ta, mu
; RV64-NEXT: vmv.v.i v8, 0
; RV64-NEXT: addi a1, sp, 128 ; RV64-NEXT: addi a1, sp, 128
; RV64-NEXT: vs8r.v v8, (a1)
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a2, a2, 4
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 128
; RV64-NEXT: vs8r.v v8, (a2)
; RV64-NEXT: add a1, a1, a0 ; RV64-NEXT: add a1, a1, a0
; RV64-NEXT: vsetvli a2, zero, e32, m8, ta, mu
; RV64-NEXT: vmv.v.i v8, 0
; RV64-NEXT: vs8r.v v8, (a1) ; RV64-NEXT: vs8r.v v8, (a1)
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: add a0, a2, a0
; RV64-NEXT: slli a1, a1, 4
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 128
; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: vs8r.v v8, (a0)
; RV64-NEXT: addi a0, sp, 128
; RV64-NEXT: vs8r.v v8, (a0)
; RV64-NEXT: li a1, 1 ; RV64-NEXT: li a1, 1
; RV64-NEXT: li a2, 2 ; RV64-NEXT: li a2, 2
; RV64-NEXT: li a3, 3 ; RV64-NEXT: li a3, 3
; RV64-NEXT: li a4, 4 ; RV64-NEXT: li a4, 4
; RV64-NEXT: li a5, 5 ; RV64-NEXT: li a5, 5
; RV64-NEXT: li a6, 6 ; RV64-NEXT: li a6, 6
; RV64-NEXT: li a7, 7 ; RV64-NEXT: li a7, 7
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr t0, vlenb
; RV64-NEXT: slli a0, a0, 4 ; RV64-NEXT: slli t0, t0, 4
; RV64-NEXT: add a0, sp, a0 ; RV64-NEXT: add t0, sp, t0
; RV64-NEXT: addi t2, a0, 128 ; RV64-NEXT: addi t2, t0, 128
; RV64-NEXT: addi t4, sp, 128 ; RV64-NEXT: addi t4, sp, 128
; RV64-NEXT: li t6, 8 ; RV64-NEXT: li t6, 8
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 128
; RV64-NEXT: vs8r.v v8, (a0) ; RV64-NEXT: vs8r.v v8, (a0)
; RV64-NEXT: li a0, 0 ; RV64-NEXT: li a0, 0
; RV64-NEXT: vmv.v.i v16, 0 ; RV64-NEXT: vmv.v.i v16, 0
; RV64-NEXT: call vector_arg_indirect_stack@plt ; RV64-NEXT: call vector_arg_indirect_stack@plt
; RV64-NEXT: addi sp, s0, -144 ; RV64-NEXT: addi sp, s0, -144
; RV64-NEXT: ld ra, 136(sp) # 8-byte Folded Reload ; RV64-NEXT: ld ra, 136(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 144 ; RV64-NEXT: addi sp, sp, 144
; RV64-NEXT: ret ; RV64-NEXT: ret
%s = call fastcc <vscale x 32 x i32> @vector_arg_indirect_stack(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, <vscale x 32 x i32> zeroinitializer, <vscale x 32 x i32> zeroinitializer, <vscale x 32 x i32> zeroinitializer, i32 8) %s = call fastcc <vscale x 32 x i32> @vector_arg_indirect_stack(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, <vscale x 32 x i32> zeroinitializer, <vscale x 32 x i32> zeroinitializer, <vscale x 32 x i32> zeroinitializer, i32 8)
ret <vscale x 32 x i32> %s ret <vscale x 32 x i32> %s
} }

llvm/test/CodeGen/RISCV/rvv/calling-conv.ll

Show All 27 Lines
; RV32-NEXT: sw ra, 140(sp) # 4-byte Folded Spill ; RV32-NEXT: sw ra, 140(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: addi s0, sp, 144 ; RV32-NEXT: addi s0, sp, 144
; RV32-NEXT: .cfi_def_cfa s0, 0 ; RV32-NEXT: .cfi_def_cfa s0, 0
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: sub sp, sp, a0 ; RV32-NEXT: sub sp, sp, a0
; RV32-NEXT: andi sp, sp, -128 ; RV32-NEXT: andi sp, sp, -128
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: addi a1, sp, 128
; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: vs8r.v v16, (a0)
; RV32-NEXT: addi a0, sp, 128 ; RV32-NEXT: addi a0, sp, 128
; RV32-NEXT: vs8r.v v8, (a0) ; RV32-NEXT: vs8r.v v8, (a0)
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a0, a0, a1
; RV32-NEXT: vs8r.v v16, (a0)
; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; RV32-NEXT: vmv.v.i v8, 0 ; RV32-NEXT: vmv.v.i v8, 0
; RV32-NEXT: addi a0, sp, 128 ; RV32-NEXT: addi a0, sp, 128
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: call callee_scalable_vector_split_indirect@plt ; RV32-NEXT: call callee_scalable_vector_split_indirect@plt
; RV32-NEXT: addi sp, s0, -144 ; RV32-NEXT: addi sp, s0, -144
; RV32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload ; RV32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 144 ; RV32-NEXT: addi sp, sp, 144
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: caller_scalable_vector_split_indirect: ; RV64-LABEL: caller_scalable_vector_split_indirect:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -144 ; RV64-NEXT: addi sp, sp, -144
; RV64-NEXT: .cfi_def_cfa_offset 144 ; RV64-NEXT: .cfi_def_cfa_offset 144
; RV64-NEXT: sd ra, 136(sp) # 8-byte Folded Spill ; RV64-NEXT: sd ra, 136(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8 ; RV64-NEXT: .cfi_offset ra, -8
; RV64-NEXT: addi s0, sp, 144 ; RV64-NEXT: addi s0, sp, 144
; RV64-NEXT: .cfi_def_cfa s0, 0 ; RV64-NEXT: .cfi_def_cfa s0, 0
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4 ; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: sub sp, sp, a0 ; RV64-NEXT: sub sp, sp, a0
; RV64-NEXT: andi sp, sp, -128 ; RV64-NEXT: andi sp, sp, -128
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: addi a1, sp, 128
; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: vs8r.v v16, (a0)
; RV64-NEXT: addi a0, sp, 128 ; RV64-NEXT: addi a0, sp, 128
; RV64-NEXT: vs8r.v v8, (a0) ; RV64-NEXT: vs8r.v v8, (a0)
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: vs8r.v v16, (a0)
; RV64-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; RV64-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; RV64-NEXT: vmv.v.i v8, 0 ; RV64-NEXT: vmv.v.i v8, 0
; RV64-NEXT: addi a0, sp, 128 ; RV64-NEXT: addi a0, sp, 128
; RV64-NEXT: vmv.v.i v16, 0 ; RV64-NEXT: vmv.v.i v16, 0
; RV64-NEXT: call callee_scalable_vector_split_indirect@plt ; RV64-NEXT: call callee_scalable_vector_split_indirect@plt
; RV64-NEXT: addi sp, s0, -144 ; RV64-NEXT: addi sp, s0, -144
; RV64-NEXT: ld ra, 136(sp) # 8-byte Folded Reload ; RV64-NEXT: ld ra, 136(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 144 ; RV64-NEXT: addi sp, sp, 144
; RV64-NEXT: ret ; RV64-NEXT: ret
%c = alloca i64 %c = alloca i64
%a = call <vscale x 32 x i32> @callee_scalable_vector_split_indirect(<vscale x 32 x i32> zeroinitializer, <vscale x 32 x i32> %x) %a = call <vscale x 32 x i32> @callee_scalable_vector_split_indirect(<vscale x 32 x i32> zeroinitializer, <vscale x 32 x i32> %x)
ret <vscale x 32 x i32> %a ret <vscale x 32 x i32> %a
} }

llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll

Show First 20 Lines • Show All 1,249 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsrl.vi v9, v8, 16 ; RV32-NEXT: vsrl.vi v9, v8, 16
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: li a0, 32 ; RV32-NEXT: li a0, 32
; RV32-NEXT: vsrl.vx v9, v8, a0 ; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vnot.v v8, v8 ; RV32-NEXT: vnot.v v8, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsrl.vi v11, v8, 1 ; RV32-NEXT: vsrl.vi v11, v8, 1
; RV32-NEXT: vand.vv v9, v11, v9 ; RV32-NEXT: vand.vv v9, v11, v9
; RV32-NEXT: vsub.vv v8, v8, v9 ; RV32-NEXT: vsub.vv v8, v8, v9
; RV32-NEXT: vand.vv v9, v8, v10 ; RV32-NEXT: vand.vv v9, v8, v10
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: vadd.vv v8, v9, v8 ; RV32-NEXT: vadd.vv v8, v9, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsrl.vi v11, v8, 4 ; RV32-NEXT: vsrl.vi v11, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v11 ; RV32-NEXT: vadd.vv v8, v8, v11
; RV32-NEXT: vand.vv v8, v8, v9 ; RV32-NEXT: vand.vv v8, v8, v9
; RV32-NEXT: vmul.vv v8, v8, v10 ; RV32-NEXT: vmul.vv v8, v8, v10
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: vsrl.vx v8, v8, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsrl.vi v10, v8, 16 ; RV32-NEXT: vsrl.vi v10, v8, 16
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: li a0, 32 ; RV32-NEXT: li a0, 32
; RV32-NEXT: vsrl.vx v10, v8, a0 ; RV32-NEXT: vsrl.vx v10, v8, a0
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vnot.v v8, v8 ; RV32-NEXT: vnot.v v8, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsrl.vi v14, v8, 1 ; RV32-NEXT: vsrl.vi v14, v8, 1
; RV32-NEXT: vand.vv v10, v14, v10 ; RV32-NEXT: vand.vv v10, v14, v10
; RV32-NEXT: vsub.vv v8, v8, v10 ; RV32-NEXT: vsub.vv v8, v8, v10
; RV32-NEXT: vand.vv v10, v8, v12 ; RV32-NEXT: vand.vv v10, v8, v12
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: vadd.vv v8, v10, v8 ; RV32-NEXT: vadd.vv v8, v10, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsrl.vi v14, v8, 4 ; RV32-NEXT: vsrl.vi v14, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v14 ; RV32-NEXT: vadd.vv v8, v8, v14
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: vmul.vv v8, v8, v12 ; RV32-NEXT: vmul.vv v8, v8, v12
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: vsrl.vx v8, v8, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsrl.vi v12, v8, 16 ; RV32-NEXT: vsrl.vi v12, v8, 16
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: li a0, 32 ; RV32-NEXT: li a0, 32
; RV32-NEXT: vsrl.vx v12, v8, a0 ; RV32-NEXT: vsrl.vx v12, v8, a0
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vnot.v v8, v8 ; RV32-NEXT: vnot.v v8, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsrl.vi v20, v8, 1 ; RV32-NEXT: vsrl.vi v20, v8, 1
; RV32-NEXT: vand.vv v12, v20, v12 ; RV32-NEXT: vand.vv v12, v20, v12
; RV32-NEXT: vsub.vv v8, v8, v12 ; RV32-NEXT: vsub.vv v8, v8, v12
; RV32-NEXT: vand.vv v12, v8, v16 ; RV32-NEXT: vand.vv v12, v8, v16
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vadd.vv v8, v12, v8 ; RV32-NEXT: vadd.vv v8, v12, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsrl.vi v20, v8, 4 ; RV32-NEXT: vsrl.vi v20, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v20 ; RV32-NEXT: vadd.vv v8, v8, v20
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: vmul.vv v8, v8, v16 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: vsrl.vx v8, v8, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsrl.vi v16, v8, 16 ; RV32-NEXT: vsrl.vi v16, v8, 16
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: li a0, 32 ; RV32-NEXT: li a0, 32
; RV32-NEXT: vsrl.vx v16, v8, a0 ; RV32-NEXT: vsrl.vx v16, v8, a0
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vnot.v v8, v8 ; RV32-NEXT: vnot.v v8, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsrl.vi v0, v8, 1 ; RV32-NEXT: vsrl.vi v0, v8, 1
; RV32-NEXT: vand.vv v16, v0, v16 ; RV32-NEXT: vand.vv v16, v0, v16
; RV32-NEXT: vsub.vv v8, v8, v16 ; RV32-NEXT: vsub.vv v8, v8, v16
; RV32-NEXT: vand.vv v16, v8, v24 ; RV32-NEXT: vand.vv v16, v8, v24
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vadd.vv v8, v16, v8 ; RV32-NEXT: vadd.vv v8, v16, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsrl.vi v0, v8, 4 ; RV32-NEXT: vsrl.vi v0, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v0 ; RV32-NEXT: vadd.vv v8, v8, v0
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vmul.vv v8, v8, v24 ; RV32-NEXT: vmul.vv v8, v8, v24
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: vsrl.vx v8, v8, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 1,234 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsrl.vi v9, v8, 16 ; RV32-NEXT: vsrl.vi v9, v8, 16
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: li a0, 32 ; RV32-NEXT: li a0, 32
; RV32-NEXT: vsrl.vx v9, v8, a0 ; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vnot.v v8, v8 ; RV32-NEXT: vnot.v v8, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsrl.vi v11, v8, 1 ; RV32-NEXT: vsrl.vi v11, v8, 1
; RV32-NEXT: vand.vv v9, v11, v9 ; RV32-NEXT: vand.vv v9, v11, v9
; RV32-NEXT: vsub.vv v8, v8, v9 ; RV32-NEXT: vsub.vv v8, v8, v9
; RV32-NEXT: vand.vv v9, v8, v10 ; RV32-NEXT: vand.vv v9, v8, v10
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: vadd.vv v8, v9, v8 ; RV32-NEXT: vadd.vv v8, v9, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsrl.vi v11, v8, 4 ; RV32-NEXT: vsrl.vi v11, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v11 ; RV32-NEXT: vadd.vv v8, v8, v11
; RV32-NEXT: vand.vv v8, v8, v9 ; RV32-NEXT: vand.vv v8, v8, v9
; RV32-NEXT: vmul.vv v8, v8, v10 ; RV32-NEXT: vmul.vv v8, v8, v10
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: vsrl.vx v8, v8, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsrl.vi v10, v8, 16 ; RV32-NEXT: vsrl.vi v10, v8, 16
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: li a0, 32 ; RV32-NEXT: li a0, 32
; RV32-NEXT: vsrl.vx v10, v8, a0 ; RV32-NEXT: vsrl.vx v10, v8, a0
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vnot.v v8, v8 ; RV32-NEXT: vnot.v v8, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsrl.vi v14, v8, 1 ; RV32-NEXT: vsrl.vi v14, v8, 1
; RV32-NEXT: vand.vv v10, v14, v10 ; RV32-NEXT: vand.vv v10, v14, v10
; RV32-NEXT: vsub.vv v8, v8, v10 ; RV32-NEXT: vsub.vv v8, v8, v10
; RV32-NEXT: vand.vv v10, v8, v12 ; RV32-NEXT: vand.vv v10, v8, v12
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: vadd.vv v8, v10, v8 ; RV32-NEXT: vadd.vv v8, v10, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsrl.vi v14, v8, 4 ; RV32-NEXT: vsrl.vi v14, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v14 ; RV32-NEXT: vadd.vv v8, v8, v14
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: vmul.vv v8, v8, v12 ; RV32-NEXT: vmul.vv v8, v8, v12
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: vsrl.vx v8, v8, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsrl.vi v12, v8, 16 ; RV32-NEXT: vsrl.vi v12, v8, 16
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: li a0, 32 ; RV32-NEXT: li a0, 32
; RV32-NEXT: vsrl.vx v12, v8, a0 ; RV32-NEXT: vsrl.vx v12, v8, a0
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vnot.v v8, v8 ; RV32-NEXT: vnot.v v8, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsrl.vi v20, v8, 1 ; RV32-NEXT: vsrl.vi v20, v8, 1
; RV32-NEXT: vand.vv v12, v20, v12 ; RV32-NEXT: vand.vv v12, v20, v12
; RV32-NEXT: vsub.vv v8, v8, v12 ; RV32-NEXT: vsub.vv v8, v8, v12
; RV32-NEXT: vand.vv v12, v8, v16 ; RV32-NEXT: vand.vv v12, v8, v16
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vadd.vv v8, v12, v8 ; RV32-NEXT: vadd.vv v8, v12, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsrl.vi v20, v8, 4 ; RV32-NEXT: vsrl.vi v20, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v20 ; RV32-NEXT: vadd.vv v8, v8, v20
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: vmul.vv v8, v8, v16 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: vsrl.vx v8, v8, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsrl.vi v16, v8, 16 ; RV32-NEXT: vsrl.vi v16, v8, 16
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: li a0, 32 ; RV32-NEXT: li a0, 32
; RV32-NEXT: vsrl.vx v16, v8, a0 ; RV32-NEXT: vsrl.vx v16, v8, a0
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vnot.v v8, v8 ; RV32-NEXT: vnot.v v8, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsrl.vi v0, v8, 1 ; RV32-NEXT: vsrl.vi v0, v8, 1
; RV32-NEXT: vand.vv v16, v0, v16 ; RV32-NEXT: vand.vv v16, v0, v16
; RV32-NEXT: vsub.vv v8, v8, v16 ; RV32-NEXT: vsub.vv v8, v8, v16
; RV32-NEXT: vand.vv v16, v8, v24 ; RV32-NEXT: vand.vv v16, v8, v24
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vadd.vv v8, v16, v8 ; RV32-NEXT: vadd.vv v8, v16, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsrl.vi v0, v8, 4 ; RV32-NEXT: vsrl.vi v0, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v0 ; RV32-NEXT: vadd.vv v8, v8, v0
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vmul.vv v8, v8, v24 ; RV32-NEXT: vmul.vv v8, v8, v24
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: vsrl.vx v8, v8, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 44 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll

Show First 20 Lines • Show All 767 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 4112 ; RV32-NEXT: lui a0, 4112
; RV32-NEXT: addi a0, a0, 257 ; RV32-NEXT: addi a0, a0, 257
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsrl.vi v11, v8, 1 ; RV32-NEXT: vsrl.vi v11, v8, 1
; RV32-NEXT: vand.vv v9, v11, v9 ; RV32-NEXT: vand.vv v9, v11, v9
; RV32-NEXT: vsub.vv v8, v8, v9 ; RV32-NEXT: vsub.vv v8, v8, v9
; RV32-NEXT: vand.vv v9, v8, v10 ; RV32-NEXT: vand.vv v9, v8, v10
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: vadd.vv v8, v9, v8 ; RV32-NEXT: vadd.vv v8, v9, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsrl.vi v11, v8, 4 ; RV32-NEXT: vsrl.vi v11, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v11 ; RV32-NEXT: vadd.vv v8, v8, v11
; RV32-NEXT: vand.vv v8, v8, v9 ; RV32-NEXT: vand.vv v8, v8, v9
; RV32-NEXT: vmul.vv v8, v8, v10 ; RV32-NEXT: vmul.vv v8, v8, v10
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: vsrl.vx v8, v8, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 4112 ; RV32-NEXT: lui a0, 4112
; RV32-NEXT: addi a0, a0, 257 ; RV32-NEXT: addi a0, a0, 257
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsrl.vi v14, v8, 1 ; RV32-NEXT: vsrl.vi v14, v8, 1
; RV32-NEXT: vand.vv v10, v14, v10 ; RV32-NEXT: vand.vv v10, v14, v10
; RV32-NEXT: vsub.vv v8, v8, v10 ; RV32-NEXT: vsub.vv v8, v8, v10
; RV32-NEXT: vand.vv v10, v8, v12 ; RV32-NEXT: vand.vv v10, v8, v12
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: vadd.vv v8, v10, v8 ; RV32-NEXT: vadd.vv v8, v10, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsrl.vi v14, v8, 4 ; RV32-NEXT: vsrl.vi v14, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v14 ; RV32-NEXT: vadd.vv v8, v8, v14
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: vmul.vv v8, v8, v12 ; RV32-NEXT: vmul.vv v8, v8, v12
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: vsrl.vx v8, v8, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 4112 ; RV32-NEXT: lui a0, 4112
; RV32-NEXT: addi a0, a0, 257 ; RV32-NEXT: addi a0, a0, 257
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsrl.vi v20, v8, 1 ; RV32-NEXT: vsrl.vi v20, v8, 1
; RV32-NEXT: vand.vv v12, v20, v12 ; RV32-NEXT: vand.vv v12, v20, v12
; RV32-NEXT: vsub.vv v8, v8, v12 ; RV32-NEXT: vsub.vv v8, v8, v12
; RV32-NEXT: vand.vv v12, v8, v16 ; RV32-NEXT: vand.vv v12, v8, v16
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vadd.vv v8, v12, v8 ; RV32-NEXT: vadd.vv v8, v12, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsrl.vi v20, v8, 4 ; RV32-NEXT: vsrl.vi v20, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v20 ; RV32-NEXT: vadd.vv v8, v8, v20
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: vmul.vv v8, v8, v16 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: vsrl.vx v8, v8, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 4112 ; RV32-NEXT: lui a0, 4112
; RV32-NEXT: addi a0, a0, 257 ; RV32-NEXT: addi a0, a0, 257
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsrl.vi v0, v8, 1 ; RV32-NEXT: vsrl.vi v0, v8, 1
; RV32-NEXT: vand.vv v16, v0, v16 ; RV32-NEXT: vand.vv v16, v0, v16
; RV32-NEXT: vsub.vv v8, v8, v16 ; RV32-NEXT: vsub.vv v8, v8, v16
; RV32-NEXT: vand.vv v16, v8, v24 ; RV32-NEXT: vand.vv v16, v8, v24
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vadd.vv v8, v16, v8 ; RV32-NEXT: vadd.vv v8, v16, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsrl.vi v0, v8, 4 ; RV32-NEXT: vsrl.vi v0, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v0 ; RV32-NEXT: vadd.vv v8, v8, v0
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vmul.vv v8, v8, v24 ; RV32-NEXT: vmul.vv v8, v8, v24
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: vsrl.vx v8, v8, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
Show All 31 Lines

llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll

Show First 20 Lines • Show All 1,121 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: li a0, 1 ; RV32-NEXT: li a0, 1
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vsub.vx v9, v8, a0 ; RV32-NEXT: vsub.vx v9, v8, a0
; RV32-NEXT: vnot.v v8, v8 ; RV32-NEXT: vnot.v v8, v8
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vand.vv v8, v8, v9 ; RV32-NEXT: vand.vv v8, v8, v9
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsrl.vi v11, v8, 1 ; RV32-NEXT: vsrl.vi v11, v8, 1
; RV32-NEXT: vand.vv v10, v11, v10 ; RV32-NEXT: vand.vv v10, v11, v10
; RV32-NEXT: vsub.vv v8, v8, v10 ; RV32-NEXT: vsub.vv v8, v8, v10
; RV32-NEXT: vand.vv v10, v8, v9 ; RV32-NEXT: vand.vv v10, v8, v9
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v9 ; RV32-NEXT: vand.vv v8, v8, v9
; RV32-NEXT: vadd.vv v8, v10, v8 ; RV32-NEXT: vadd.vv v8, v10, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsrl.vi v11, v8, 4 ; RV32-NEXT: vsrl.vi v11, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v11 ; RV32-NEXT: vadd.vv v8, v8, v11
; RV32-NEXT: vand.vv v8, v8, v9 ; RV32-NEXT: vand.vv v8, v8, v9
; RV32-NEXT: vmul.vv v8, v8, v10 ; RV32-NEXT: vmul.vv v8, v8, v10
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: vsrl.vx v8, v8, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: li a0, 1 ; RV32-NEXT: li a0, 1
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vsub.vx v10, v8, a0 ; RV32-NEXT: vsub.vx v10, v8, a0
; RV32-NEXT: vnot.v v8, v8 ; RV32-NEXT: vnot.v v8, v8
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsrl.vi v14, v8, 1 ; RV32-NEXT: vsrl.vi v14, v8, 1
; RV32-NEXT: vand.vv v12, v14, v12 ; RV32-NEXT: vand.vv v12, v14, v12
; RV32-NEXT: vsub.vv v8, v8, v12 ; RV32-NEXT: vsub.vv v8, v8, v12
; RV32-NEXT: vand.vv v12, v8, v10 ; RV32-NEXT: vand.vv v12, v8, v10
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: vadd.vv v8, v12, v8 ; RV32-NEXT: vadd.vv v8, v12, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsrl.vi v14, v8, 4 ; RV32-NEXT: vsrl.vi v14, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v14 ; RV32-NEXT: vadd.vv v8, v8, v14
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: vmul.vv v8, v8, v12 ; RV32-NEXT: vmul.vv v8, v8, v12
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: vsrl.vx v8, v8, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: li a0, 1 ; RV32-NEXT: li a0, 1
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vsub.vx v12, v8, a0 ; RV32-NEXT: vsub.vx v12, v8, a0
; RV32-NEXT: vnot.v v8, v8 ; RV32-NEXT: vnot.v v8, v8
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsrl.vi v20, v8, 1 ; RV32-NEXT: vsrl.vi v20, v8, 1
; RV32-NEXT: vand.vv v16, v20, v16 ; RV32-NEXT: vand.vv v16, v20, v16
; RV32-NEXT: vsub.vv v8, v8, v16 ; RV32-NEXT: vsub.vv v8, v8, v16
; RV32-NEXT: vand.vv v16, v8, v12 ; RV32-NEXT: vand.vv v16, v8, v12
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: vadd.vv v8, v16, v8 ; RV32-NEXT: vadd.vv v8, v16, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsrl.vi v20, v8, 4 ; RV32-NEXT: vsrl.vi v20, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v20 ; RV32-NEXT: vadd.vv v8, v8, v20
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: vmul.vv v8, v8, v16 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: vsrl.vx v8, v8, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: li a0, 1 ; RV32-NEXT: li a0, 1
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vsub.vx v16, v8, a0 ; RV32-NEXT: vsub.vx v16, v8, a0
; RV32-NEXT: vnot.v v8, v8 ; RV32-NEXT: vnot.v v8, v8
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsrl.vi v0, v8, 1 ; RV32-NEXT: vsrl.vi v0, v8, 1
; RV32-NEXT: vand.vv v24, v0, v24 ; RV32-NEXT: vand.vv v24, v0, v24
; RV32-NEXT: vsub.vv v8, v8, v24 ; RV32-NEXT: vsub.vv v8, v8, v24
; RV32-NEXT: vand.vv v24, v8, v16 ; RV32-NEXT: vand.vv v24, v8, v16
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vadd.vv v8, v24, v8 ; RV32-NEXT: vadd.vv v8, v24, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsrl.vi v0, v8, 4 ; RV32-NEXT: vsrl.vi v0, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v0 ; RV32-NEXT: vadd.vv v8, v8, v0
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vmul.vv v8, v8, v24 ; RV32-NEXT: vmul.vv v8, v8, v24
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: vsrl.vx v8, v8, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 1,096 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: li a0, 1 ; RV32-NEXT: li a0, 1
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vsub.vx v9, v8, a0 ; RV32-NEXT: vsub.vx v9, v8, a0
; RV32-NEXT: vnot.v v8, v8 ; RV32-NEXT: vnot.v v8, v8
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vand.vv v8, v8, v9 ; RV32-NEXT: vand.vv v8, v8, v9
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsrl.vi v11, v8, 1 ; RV32-NEXT: vsrl.vi v11, v8, 1
; RV32-NEXT: vand.vv v10, v11, v10 ; RV32-NEXT: vand.vv v10, v11, v10
; RV32-NEXT: vsub.vv v8, v8, v10 ; RV32-NEXT: vsub.vv v8, v8, v10
; RV32-NEXT: vand.vv v10, v8, v9 ; RV32-NEXT: vand.vv v10, v8, v9
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v9 ; RV32-NEXT: vand.vv v8, v8, v9
; RV32-NEXT: vadd.vv v8, v10, v8 ; RV32-NEXT: vadd.vv v8, v10, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsrl.vi v11, v8, 4 ; RV32-NEXT: vsrl.vi v11, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v11 ; RV32-NEXT: vadd.vv v8, v8, v11
; RV32-NEXT: vand.vv v8, v8, v9 ; RV32-NEXT: vand.vv v8, v8, v9
; RV32-NEXT: vmul.vv v8, v8, v10 ; RV32-NEXT: vmul.vv v8, v8, v10
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: vsrl.vx v8, v8, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: li a0, 1 ; RV32-NEXT: li a0, 1
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vsub.vx v10, v8, a0 ; RV32-NEXT: vsub.vx v10, v8, a0
; RV32-NEXT: vnot.v v8, v8 ; RV32-NEXT: vnot.v v8, v8
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsrl.vi v14, v8, 1 ; RV32-NEXT: vsrl.vi v14, v8, 1
; RV32-NEXT: vand.vv v12, v14, v12 ; RV32-NEXT: vand.vv v12, v14, v12
; RV32-NEXT: vsub.vv v8, v8, v12 ; RV32-NEXT: vsub.vv v8, v8, v12
; RV32-NEXT: vand.vv v12, v8, v10 ; RV32-NEXT: vand.vv v12, v8, v10
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: vadd.vv v8, v12, v8 ; RV32-NEXT: vadd.vv v8, v12, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsrl.vi v14, v8, 4 ; RV32-NEXT: vsrl.vi v14, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v14 ; RV32-NEXT: vadd.vv v8, v8, v14
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: vmul.vv v8, v8, v12 ; RV32-NEXT: vmul.vv v8, v8, v12
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: vsrl.vx v8, v8, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: li a0, 1 ; RV32-NEXT: li a0, 1
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vsub.vx v12, v8, a0 ; RV32-NEXT: vsub.vx v12, v8, a0
; RV32-NEXT: vnot.v v8, v8 ; RV32-NEXT: vnot.v v8, v8
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsrl.vi v20, v8, 1 ; RV32-NEXT: vsrl.vi v20, v8, 1
; RV32-NEXT: vand.vv v16, v20, v16 ; RV32-NEXT: vand.vv v16, v20, v16
; RV32-NEXT: vsub.vv v8, v8, v16 ; RV32-NEXT: vsub.vv v8, v8, v16
; RV32-NEXT: vand.vv v16, v8, v12 ; RV32-NEXT: vand.vv v16, v8, v12
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: vadd.vv v8, v16, v8 ; RV32-NEXT: vadd.vv v8, v16, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsrl.vi v20, v8, 4 ; RV32-NEXT: vsrl.vi v20, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v20 ; RV32-NEXT: vadd.vv v8, v8, v20
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: vmul.vv v8, v8, v16 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: vsrl.vx v8, v8, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: li a0, 1 ; RV32-NEXT: li a0, 1
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vsub.vx v16, v8, a0 ; RV32-NEXT: vsub.vx v16, v8, a0
; RV32-NEXT: vnot.v v8, v8 ; RV32-NEXT: vnot.v v8, v8
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsrl.vi v0, v8, 1 ; RV32-NEXT: vsrl.vi v0, v8, 1
; RV32-NEXT: vand.vv v24, v0, v24 ; RV32-NEXT: vand.vv v24, v0, v24
; RV32-NEXT: vsub.vv v8, v8, v24 ; RV32-NEXT: vsub.vv v8, v8, v24
; RV32-NEXT: vand.vv v24, v8, v16 ; RV32-NEXT: vand.vv v24, v8, v16
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vadd.vv v8, v24, v8 ; RV32-NEXT: vadd.vv v8, v24, v8
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsrl.vi v0, v8, 4 ; RV32-NEXT: vsrl.vi v0, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v0 ; RV32-NEXT: vadd.vv v8, v8, v0
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vmul.vv v8, v8, v24 ; RV32-NEXT: vmul.vv v8, v8, v24
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: vsrl.vx v8, v8, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
Show All 34 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll

Show First 20 Lines • Show All 149 Lines • ▼ Show 20 Lines
; RV32ELEN32-NEXT: vmv.x.s a1, v9 ; RV32ELEN32-NEXT: vmv.x.s a1, v9
; RV32ELEN32-NEXT: vmv.x.s a0, v8 ; RV32ELEN32-NEXT: vmv.x.s a0, v8
; RV32ELEN32-NEXT: ret ; RV32ELEN32-NEXT: ret
; ;
; RV64ELEN32-LABEL: bitcast_v8i8_i64: ; RV64ELEN32-LABEL: bitcast_v8i8_i64:
; RV64ELEN32: # %bb.0: ; RV64ELEN32: # %bb.0:
; RV64ELEN32-NEXT: addi sp, sp, -16 ; RV64ELEN32-NEXT: addi sp, sp, -16
; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16 ; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV64ELEN32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64ELEN32-NEXT: addi a0, sp, 8 ; RV64ELEN32-NEXT: addi a0, sp, 8
; RV64ELEN32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64ELEN32-NEXT: vse8.v v8, (a0) ; RV64ELEN32-NEXT: vse8.v v8, (a0)
; RV64ELEN32-NEXT: ld a0, 8(sp) ; RV64ELEN32-NEXT: ld a0, 8(sp)
; RV64ELEN32-NEXT: addi sp, sp, 16 ; RV64ELEN32-NEXT: addi sp, sp, 16
; RV64ELEN32-NEXT: ret ; RV64ELEN32-NEXT: ret
%b = bitcast <8 x i8> %a to i64 %b = bitcast <8 x i8> %a to i64
ret i64 %b ret i64 %b
} }
Show All 20 Lines
; RV32ELEN32-NEXT: vmv.x.s a1, v9 ; RV32ELEN32-NEXT: vmv.x.s a1, v9
; RV32ELEN32-NEXT: vmv.x.s a0, v8 ; RV32ELEN32-NEXT: vmv.x.s a0, v8
; RV32ELEN32-NEXT: ret ; RV32ELEN32-NEXT: ret
; ;
; RV64ELEN32-LABEL: bitcast_v4i16_i64: ; RV64ELEN32-LABEL: bitcast_v4i16_i64:
; RV64ELEN32: # %bb.0: ; RV64ELEN32: # %bb.0:
; RV64ELEN32-NEXT: addi sp, sp, -16 ; RV64ELEN32-NEXT: addi sp, sp, -16
; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16 ; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV64ELEN32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; RV64ELEN32-NEXT: addi a0, sp, 8 ; RV64ELEN32-NEXT: addi a0, sp, 8
; RV64ELEN32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; RV64ELEN32-NEXT: vse16.v v8, (a0) ; RV64ELEN32-NEXT: vse16.v v8, (a0)
; RV64ELEN32-NEXT: ld a0, 8(sp) ; RV64ELEN32-NEXT: ld a0, 8(sp)
; RV64ELEN32-NEXT: addi sp, sp, 16 ; RV64ELEN32-NEXT: addi sp, sp, 16
; RV64ELEN32-NEXT: ret ; RV64ELEN32-NEXT: ret
%b = bitcast <4 x i16> %a to i64 %b = bitcast <4 x i16> %a to i64
ret i64 %b ret i64 %b
} }
Show All 20 Lines
; RV32ELEN32-NEXT: vmv.x.s a1, v9 ; RV32ELEN32-NEXT: vmv.x.s a1, v9
; RV32ELEN32-NEXT: vmv.x.s a0, v8 ; RV32ELEN32-NEXT: vmv.x.s a0, v8
; RV32ELEN32-NEXT: ret ; RV32ELEN32-NEXT: ret
; ;
; RV64ELEN32-LABEL: bitcast_v2i32_i64: ; RV64ELEN32-LABEL: bitcast_v2i32_i64:
; RV64ELEN32: # %bb.0: ; RV64ELEN32: # %bb.0:
; RV64ELEN32-NEXT: addi sp, sp, -16 ; RV64ELEN32-NEXT: addi sp, sp, -16
; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16 ; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV64ELEN32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; RV64ELEN32-NEXT: addi a0, sp, 8 ; RV64ELEN32-NEXT: addi a0, sp, 8
; RV64ELEN32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; RV64ELEN32-NEXT: vse32.v v8, (a0) ; RV64ELEN32-NEXT: vse32.v v8, (a0)
; RV64ELEN32-NEXT: ld a0, 8(sp) ; RV64ELEN32-NEXT: ld a0, 8(sp)
; RV64ELEN32-NEXT: addi sp, sp, 16 ; RV64ELEN32-NEXT: addi sp, sp, 16
; RV64ELEN32-NEXT: ret ; RV64ELEN32-NEXT: ret
%b = bitcast <2 x i32> %a to i64 %b = bitcast <2 x i32> %a to i64
ret i64 %b ret i64 %b
} }
▲ Show 20 Lines • Show All 106 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; ELEN32-LABEL: bitcast_v8i8_f64: ; ELEN32-LABEL: bitcast_v8i8_f64:
; ELEN32: # %bb.0: ; ELEN32: # %bb.0:
; ELEN32-NEXT: addi sp, sp, -16 ; ELEN32-NEXT: addi sp, sp, -16
; ELEN32-NEXT: .cfi_def_cfa_offset 16 ; ELEN32-NEXT: .cfi_def_cfa_offset 16
; ELEN32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; ELEN32-NEXT: addi a0, sp, 8 ; ELEN32-NEXT: addi a0, sp, 8
; ELEN32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; ELEN32-NEXT: vse8.v v8, (a0) ; ELEN32-NEXT: vse8.v v8, (a0)
; ELEN32-NEXT: fld fa0, 8(sp) ; ELEN32-NEXT: fld fa0, 8(sp)
; ELEN32-NEXT: addi sp, sp, 16 ; ELEN32-NEXT: addi sp, sp, 16
; ELEN32-NEXT: ret ; ELEN32-NEXT: ret
%b = bitcast <8 x i8> %a to double %b = bitcast <8 x i8> %a to double
ret double %b ret double %b
} }
define double @bitcast_v4i16_f64(<4 x i16> %a) { define double @bitcast_v4i16_f64(<4 x i16> %a) {
; CHECK-LABEL: bitcast_v4i16_f64: ; CHECK-LABEL: bitcast_v4i16_f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; ELEN32-LABEL: bitcast_v4i16_f64: ; ELEN32-LABEL: bitcast_v4i16_f64:
; ELEN32: # %bb.0: ; ELEN32: # %bb.0:
; ELEN32-NEXT: addi sp, sp, -16 ; ELEN32-NEXT: addi sp, sp, -16
; ELEN32-NEXT: .cfi_def_cfa_offset 16 ; ELEN32-NEXT: .cfi_def_cfa_offset 16
; ELEN32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; ELEN32-NEXT: addi a0, sp, 8 ; ELEN32-NEXT: addi a0, sp, 8
; ELEN32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; ELEN32-NEXT: vse16.v v8, (a0) ; ELEN32-NEXT: vse16.v v8, (a0)
; ELEN32-NEXT: fld fa0, 8(sp) ; ELEN32-NEXT: fld fa0, 8(sp)
; ELEN32-NEXT: addi sp, sp, 16 ; ELEN32-NEXT: addi sp, sp, 16
; ELEN32-NEXT: ret ; ELEN32-NEXT: ret
%b = bitcast <4 x i16> %a to double %b = bitcast <4 x i16> %a to double
ret double %b ret double %b
} }
define double @bitcast_v2i32_f64(<2 x i32> %a) { define double @bitcast_v2i32_f64(<2 x i32> %a) {
; CHECK-LABEL: bitcast_v2i32_f64: ; CHECK-LABEL: bitcast_v2i32_f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; ELEN32-LABEL: bitcast_v2i32_f64: ; ELEN32-LABEL: bitcast_v2i32_f64:
; ELEN32: # %bb.0: ; ELEN32: # %bb.0:
; ELEN32-NEXT: addi sp, sp, -16 ; ELEN32-NEXT: addi sp, sp, -16
; ELEN32-NEXT: .cfi_def_cfa_offset 16 ; ELEN32-NEXT: .cfi_def_cfa_offset 16
; ELEN32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; ELEN32-NEXT: addi a0, sp, 8 ; ELEN32-NEXT: addi a0, sp, 8
; ELEN32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; ELEN32-NEXT: vse32.v v8, (a0) ; ELEN32-NEXT: vse32.v v8, (a0)
; ELEN32-NEXT: fld fa0, 8(sp) ; ELEN32-NEXT: fld fa0, 8(sp)
; ELEN32-NEXT: addi sp, sp, 16 ; ELEN32-NEXT: addi sp, sp, 16
; ELEN32-NEXT: ret ; ELEN32-NEXT: ret
%b = bitcast <2 x i32> %a to double %b = bitcast <2 x i32> %a to double
ret double %b ret double %b
} }
▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
; RV32ELEN32-NEXT: vmv.s.x v8, a0 ; RV32ELEN32-NEXT: vmv.s.x v8, a0
; RV32ELEN32-NEXT: ret ; RV32ELEN32-NEXT: ret
; ;
; RV64ELEN32-LABEL: bitcast_i64_v4i16: ; RV64ELEN32-LABEL: bitcast_i64_v4i16:
; RV64ELEN32: # %bb.0: ; RV64ELEN32: # %bb.0:
; RV64ELEN32-NEXT: addi sp, sp, -16 ; RV64ELEN32-NEXT: addi sp, sp, -16
; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16 ; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV64ELEN32-NEXT: sd a0, 8(sp) ; RV64ELEN32-NEXT: sd a0, 8(sp)
; RV64ELEN32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; RV64ELEN32-NEXT: addi a0, sp, 8 ; RV64ELEN32-NEXT: addi a0, sp, 8
; RV64ELEN32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; RV64ELEN32-NEXT: vle16.v v8, (a0) ; RV64ELEN32-NEXT: vle16.v v8, (a0)
; RV64ELEN32-NEXT: addi sp, sp, 16 ; RV64ELEN32-NEXT: addi sp, sp, 16
; RV64ELEN32-NEXT: ret ; RV64ELEN32-NEXT: ret
%b = bitcast i64 %a to <4 x i16> %b = bitcast i64 %a to <4 x i16>
ret <4 x i16> %b ret <4 x i16> %b
} }
define <2 x i32> @bitcast_i64_v2i32(i64 %a) { define <2 x i32> @bitcast_i64_v2i32(i64 %a) {
Show All 21 Lines
; RV32ELEN32-NEXT: vmv.s.x v8, a0 ; RV32ELEN32-NEXT: vmv.s.x v8, a0
; RV32ELEN32-NEXT: ret ; RV32ELEN32-NEXT: ret
; ;
; RV64ELEN32-LABEL: bitcast_i64_v2i32: ; RV64ELEN32-LABEL: bitcast_i64_v2i32:
; RV64ELEN32: # %bb.0: ; RV64ELEN32: # %bb.0:
; RV64ELEN32-NEXT: addi sp, sp, -16 ; RV64ELEN32-NEXT: addi sp, sp, -16
; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16 ; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV64ELEN32-NEXT: sd a0, 8(sp) ; RV64ELEN32-NEXT: sd a0, 8(sp)
; RV64ELEN32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; RV64ELEN32-NEXT: addi a0, sp, 8 ; RV64ELEN32-NEXT: addi a0, sp, 8
; RV64ELEN32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; RV64ELEN32-NEXT: vle32.v v8, (a0) ; RV64ELEN32-NEXT: vle32.v v8, (a0)
; RV64ELEN32-NEXT: addi sp, sp, 16 ; RV64ELEN32-NEXT: addi sp, sp, 16
; RV64ELEN32-NEXT: ret ; RV64ELEN32-NEXT: ret
%b = bitcast i64 %a to <2 x i32> %b = bitcast i64 %a to <2 x i32>
ret <2 x i32> %b ret <2 x i32> %b
} }
define <1 x i64> @bitcast_i64_v1i64(i64 %a) { define <1 x i64> @bitcast_i64_v1i64(i64 %a) {
Show All 22 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll

Show First 20 Lines • Show All 277 Lines • ▼ Show 20 Lines
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%t = call fastcc <32 x i32> @ext2(<32 x i32> %y, <32 x i32> %x, i32 %w, i32 2) %t = call fastcc <32 x i32> @ext2(<32 x i32> %y, <32 x i32> %x, i32 %w, i32 2)
ret <32 x i32> %t ret <32 x i32> %t
} }
define fastcc <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x i32> %y, <32 x i32> %z, i32 %w) { define fastcc <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x i32> %y, <32 x i32> %z, i32 %w) {
; LMULMAX8-LABEL: ret_v32i32_call_v32i32_v32i32_v32i32_i32: ; LMULMAX8-LABEL: ret_v32i32_call_v32i32_v32i32_v32i32_i32:
; LMULMAX8: # %bb.0: ; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: addi sp, sp, -384 ; LMULMAX8-NEXT: addi sp, sp, -256
; LMULMAX8-NEXT: .cfi_def_cfa_offset 384 ; LMULMAX8-NEXT: .cfi_def_cfa_offset 256
; LMULMAX8-NEXT: sd ra, 376(sp) # 8-byte Folded Spill ; LMULMAX8-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
; LMULMAX8-NEXT: sd s0, 368(sp) # 8-byte Folded Spill ; LMULMAX8-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
; LMULMAX8-NEXT: .cfi_offset ra, -8 ; LMULMAX8-NEXT: .cfi_offset ra, -8
; LMULMAX8-NEXT: .cfi_offset s0, -16 ; LMULMAX8-NEXT: .cfi_offset s0, -16
; LMULMAX8-NEXT: addi s0, sp, 384 ; LMULMAX8-NEXT: addi s0, sp, 256
; LMULMAX8-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX8-NEXT: .cfi_def_cfa s0, 0
; LMULMAX8-NEXT: andi sp, sp, -128 ; LMULMAX8-NEXT: andi sp, sp, -128
; LMULMAX8-NEXT: li a2, 32 ; LMULMAX8-NEXT: li a2, 32
; LMULMAX8-NEXT: vsetvli zero, a2, e32, m8, ta, mu ; LMULMAX8-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; LMULMAX8-NEXT: vle32.v v24, (a0) ; LMULMAX8-NEXT: vle32.v v24, (a0)
; LMULMAX8-NEXT: addi a0, sp, 128 ; LMULMAX8-NEXT: mv a3, sp
; LMULMAX8-NEXT: mv a0, sp
; LMULMAX8-NEXT: li a2, 42 ; LMULMAX8-NEXT: li a2, 42
; LMULMAX8-NEXT: addi a3, sp, 128
; LMULMAX8-NEXT: vse32.v v8, (a3) ; LMULMAX8-NEXT: vse32.v v8, (a3)
; LMULMAX8-NEXT: vmv.v.v v8, v24 ; LMULMAX8-NEXT: vmv.v.v v8, v24
; LMULMAX8-NEXT: call ext3@plt ; LMULMAX8-NEXT: call ext3@plt
; LMULMAX8-NEXT: addi sp, s0, -384 ; LMULMAX8-NEXT: addi sp, s0, -256
; LMULMAX8-NEXT: ld ra, 376(sp) # 8-byte Folded Reload ; LMULMAX8-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
; LMULMAX8-NEXT: ld s0, 368(sp) # 8-byte Folded Reload ; LMULMAX8-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; LMULMAX8-NEXT: addi sp, sp, 384 ; LMULMAX8-NEXT: addi sp, sp, 256
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX4-LABEL: ret_v32i32_call_v32i32_v32i32_v32i32_i32: ; LMULMAX4-LABEL: ret_v32i32_call_v32i32_v32i32_v32i32_i32:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: addi sp, sp, -384 ; LMULMAX4-NEXT: addi sp, sp, -256
; LMULMAX4-NEXT: .cfi_def_cfa_offset 384 ; LMULMAX4-NEXT: .cfi_def_cfa_offset 256
; LMULMAX4-NEXT: sd ra, 376(sp) # 8-byte Folded Spill ; LMULMAX4-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
; LMULMAX4-NEXT: sd s0, 368(sp) # 8-byte Folded Spill ; LMULMAX4-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
; LMULMAX4-NEXT: .cfi_offset ra, -8 ; LMULMAX4-NEXT: .cfi_offset ra, -8
; LMULMAX4-NEXT: .cfi_offset s0, -16 ; LMULMAX4-NEXT: .cfi_offset s0, -16
; LMULMAX4-NEXT: addi s0, sp, 384 ; LMULMAX4-NEXT: addi s0, sp, 256
; LMULMAX4-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX4-NEXT: .cfi_def_cfa s0, 0
; LMULMAX4-NEXT: andi sp, sp, -128 ; LMULMAX4-NEXT: andi sp, sp, -128
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; LMULMAX4-NEXT: vle32.v v24, (a0) ; LMULMAX4-NEXT: vle32.v v24, (a0)
; LMULMAX4-NEXT: addi a0, a0, 64 ; LMULMAX4-NEXT: addi a0, a0, 64
; LMULMAX4-NEXT: vle32.v v28, (a0) ; LMULMAX4-NEXT: vle32.v v28, (a0)
; LMULMAX4-NEXT: addi a0, sp, 192 ; LMULMAX4-NEXT: addi a0, sp, 64
; LMULMAX4-NEXT: vse32.v v12, (a0) ; LMULMAX4-NEXT: vse32.v v12, (a0)
; LMULMAX4-NEXT: addi a0, sp, 128 ; LMULMAX4-NEXT: mv a1, sp
; LMULMAX4-NEXT: mv a0, sp
; LMULMAX4-NEXT: li a3, 42 ; LMULMAX4-NEXT: li a3, 42
; LMULMAX4-NEXT: addi a1, sp, 128
; LMULMAX4-NEXT: vse32.v v8, (a1) ; LMULMAX4-NEXT: vse32.v v8, (a1)
; LMULMAX4-NEXT: vmv.v.v v8, v24 ; LMULMAX4-NEXT: vmv.v.v v8, v24
; LMULMAX4-NEXT: vmv.v.v v12, v28 ; LMULMAX4-NEXT: vmv.v.v v12, v28
; LMULMAX4-NEXT: call ext3@plt ; LMULMAX4-NEXT: call ext3@plt
; LMULMAX4-NEXT: addi sp, s0, -384 ; LMULMAX4-NEXT: addi sp, s0, -256
; LMULMAX4-NEXT: ld ra, 376(sp) # 8-byte Folded Reload ; LMULMAX4-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: ld s0, 368(sp) # 8-byte Folded Reload ; LMULMAX4-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: addi sp, sp, 384 ; LMULMAX4-NEXT: addi sp, sp, 256
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%t = call fastcc <32 x i32> @ext3(<32 x i32> %z, <32 x i32> %y, <32 x i32> %x, i32 %w, i32 42) %t = call fastcc <32 x i32> @ext3(<32 x i32> %z, <32 x i32> %y, <32 x i32> %x, i32 %w, i32 42)
ret <32 x i32> %t ret <32 x i32> %t
} }
; A test case where the normal calling convention would pass directly via the ; A test case where the normal calling convention would pass directly via the
; stack, but with fastcc can pass indirectly with the extra GPR registers ; stack, but with fastcc can pass indirectly with the extra GPR registers
; allowed. ; allowed.
Show All 18 Lines; LMULMAX4-NEXT: ret
%s = add <32 x i32> %x, %z %s = add <32 x i32> %x, %z
ret <32 x i32> %s ret <32 x i32> %s
} }
; Calling the function above. Ensure we pass the arguments correctly. ; Calling the function above. Ensure we pass the arguments correctly.
define fastcc <32 x i32> @pass_vector_arg_indirect_stack(<32 x i32> %x, <32 x i32> %y, <32 x i32> %z) { define fastcc <32 x i32> @pass_vector_arg_indirect_stack(<32 x i32> %x, <32 x i32> %y, <32 x i32> %z) {
; LMULMAX8-LABEL: pass_vector_arg_indirect_stack: ; LMULMAX8-LABEL: pass_vector_arg_indirect_stack:
; LMULMAX8: # %bb.0: ; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: addi sp, sp, -384 ; LMULMAX8-NEXT: addi sp, sp, -256
; LMULMAX8-NEXT: .cfi_def_cfa_offset 384 ; LMULMAX8-NEXT: .cfi_def_cfa_offset 256
; LMULMAX8-NEXT: sd ra, 376(sp) # 8-byte Folded Spill ; LMULMAX8-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
; LMULMAX8-NEXT: sd s0, 368(sp) # 8-byte Folded Spill ; LMULMAX8-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
; LMULMAX8-NEXT: .cfi_offset ra, -8 ; LMULMAX8-NEXT: .cfi_offset ra, -8
; LMULMAX8-NEXT: .cfi_offset s0, -16 ; LMULMAX8-NEXT: .cfi_offset s0, -16
; LMULMAX8-NEXT: addi s0, sp, 384 ; LMULMAX8-NEXT: addi s0, sp, 256
; LMULMAX8-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX8-NEXT: .cfi_def_cfa s0, 0
; LMULMAX8-NEXT: andi sp, sp, -128 ; LMULMAX8-NEXT: andi sp, sp, -128
; LMULMAX8-NEXT: li a0, 32 ; LMULMAX8-NEXT: li a0, 32
; LMULMAX8-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; LMULMAX8-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; LMULMAX8-NEXT: vmv.v.i v8, 0 ; LMULMAX8-NEXT: vmv.v.i v8, 0
; LMULMAX8-NEXT: mv a0, sp
; LMULMAX8-NEXT: li a1, 1 ; LMULMAX8-NEXT: li a1, 1
; LMULMAX8-NEXT: li a2, 2 ; LMULMAX8-NEXT: li a2, 2
; LMULMAX8-NEXT: li a3, 3 ; LMULMAX8-NEXT: li a3, 3
; LMULMAX8-NEXT: li a4, 4 ; LMULMAX8-NEXT: li a4, 4
; LMULMAX8-NEXT: li a5, 5 ; LMULMAX8-NEXT: li a5, 5
; LMULMAX8-NEXT: li a6, 6 ; LMULMAX8-NEXT: li a6, 6
; LMULMAX8-NEXT: li a7, 7 ; LMULMAX8-NEXT: li a7, 7
; LMULMAX8-NEXT: addi t2, sp, 128 ; LMULMAX8-NEXT: mv t2, sp
; LMULMAX8-NEXT: li t3, 8 ; LMULMAX8-NEXT: li t3, 8
; LMULMAX8-NEXT: addi a0, sp, 128
; LMULMAX8-NEXT: vse32.v v8, (a0) ; LMULMAX8-NEXT: vse32.v v8, (a0)
; LMULMAX8-NEXT: li a0, 0 ; LMULMAX8-NEXT: li a0, 0
; LMULMAX8-NEXT: vmv.v.i v16, 0 ; LMULMAX8-NEXT: vmv.v.i v16, 0
; LMULMAX8-NEXT: call vector_arg_indirect_stack@plt ; LMULMAX8-NEXT: call vector_arg_indirect_stack@plt
; LMULMAX8-NEXT: addi sp, s0, -384 ; LMULMAX8-NEXT: addi sp, s0, -256
; LMULMAX8-NEXT: ld ra, 376(sp) # 8-byte Folded Reload ; LMULMAX8-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
; LMULMAX8-NEXT: ld s0, 368(sp) # 8-byte Folded Reload ; LMULMAX8-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; LMULMAX8-NEXT: addi sp, sp, 384 ; LMULMAX8-NEXT: addi sp, sp, 256
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX4-LABEL: pass_vector_arg_indirect_stack: ; LMULMAX4-LABEL: pass_vector_arg_indirect_stack:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: addi sp, sp, -384 ; LMULMAX4-NEXT: addi sp, sp, -256
; LMULMAX4-NEXT: .cfi_def_cfa_offset 384 ; LMULMAX4-NEXT: .cfi_def_cfa_offset 256
; LMULMAX4-NEXT: sd ra, 376(sp) # 8-byte Folded Spill ; LMULMAX4-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
; LMULMAX4-NEXT: sd s0, 368(sp) # 8-byte Folded Spill ; LMULMAX4-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
; LMULMAX4-NEXT: .cfi_offset ra, -8 ; LMULMAX4-NEXT: .cfi_offset ra, -8
; LMULMAX4-NEXT: .cfi_offset s0, -16 ; LMULMAX4-NEXT: .cfi_offset s0, -16
; LMULMAX4-NEXT: addi s0, sp, 384 ; LMULMAX4-NEXT: addi s0, sp, 256
; LMULMAX4-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX4-NEXT: .cfi_def_cfa s0, 0
; LMULMAX4-NEXT: andi sp, sp, -128 ; LMULMAX4-NEXT: andi sp, sp, -128
; LMULMAX4-NEXT: addi a0, sp, 192 ; LMULMAX4-NEXT: addi a0, sp, 64
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; LMULMAX4-NEXT: vmv.v.i v8, 0 ; LMULMAX4-NEXT: vmv.v.i v8, 0
; LMULMAX4-NEXT: vse32.v v8, (a0) ; LMULMAX4-NEXT: vse32.v v8, (a0)
; LMULMAX4-NEXT: mv a0, sp
; LMULMAX4-NEXT: li a1, 1 ; LMULMAX4-NEXT: li a1, 1
; LMULMAX4-NEXT: li a2, 2 ; LMULMAX4-NEXT: li a2, 2
; LMULMAX4-NEXT: li a3, 3 ; LMULMAX4-NEXT: li a3, 3
; LMULMAX4-NEXT: li a4, 4 ; LMULMAX4-NEXT: li a4, 4
; LMULMAX4-NEXT: li a5, 5 ; LMULMAX4-NEXT: li a5, 5
; LMULMAX4-NEXT: li a6, 6 ; LMULMAX4-NEXT: li a6, 6
; LMULMAX4-NEXT: li a7, 7 ; LMULMAX4-NEXT: li a7, 7
; LMULMAX4-NEXT: addi t2, sp, 128 ; LMULMAX4-NEXT: mv t2, sp
; LMULMAX4-NEXT: li t4, 8 ; LMULMAX4-NEXT: li t4, 8
; LMULMAX4-NEXT: addi a0, sp, 128
; LMULMAX4-NEXT: vse32.v v8, (a0) ; LMULMAX4-NEXT: vse32.v v8, (a0)
; LMULMAX4-NEXT: li a0, 0 ; LMULMAX4-NEXT: li a0, 0
; LMULMAX4-NEXT: vmv.v.i v12, 0 ; LMULMAX4-NEXT: vmv.v.i v12, 0
; LMULMAX4-NEXT: vmv.v.i v16, 0 ; LMULMAX4-NEXT: vmv.v.i v16, 0
; LMULMAX4-NEXT: vmv.v.i v20, 0 ; LMULMAX4-NEXT: vmv.v.i v20, 0
; LMULMAX4-NEXT: call vector_arg_indirect_stack@plt ; LMULMAX4-NEXT: call vector_arg_indirect_stack@plt
; LMULMAX4-NEXT: addi sp, s0, -384 ; LMULMAX4-NEXT: addi sp, s0, -256
; LMULMAX4-NEXT: ld ra, 376(sp) # 8-byte Folded Reload ; LMULMAX4-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: ld s0, 368(sp) # 8-byte Folded Reload ; LMULMAX4-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: addi sp, sp, 384 ; LMULMAX4-NEXT: addi sp, sp, 256
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%s = call fastcc <32 x i32> @vector_arg_indirect_stack(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, <32 x i32> zeroinitializer, <32 x i32> zeroinitializer, <32 x i32> zeroinitializer, i32 8) %s = call fastcc <32 x i32> @vector_arg_indirect_stack(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, <32 x i32> zeroinitializer, <32 x i32> zeroinitializer, <32 x i32> zeroinitializer, i32 8)
ret <32 x i32> %s ret <32 x i32> %s
} }
; A pathological test case where even with fastcc we must use the stack for arguments %13 and %z ; A pathological test case where even with fastcc we must use the stack for arguments %13 and %z
define fastcc <32 x i32> @vector_arg_direct_stack(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12, i32 %13, <32 x i32> %x, <32 x i32> %y, <32 x i32> %z, i32 %last) { define fastcc <32 x i32> @vector_arg_direct_stack(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12, i32 %13, <32 x i32> %x, <32 x i32> %y, <32 x i32> %z, i32 %last) {
; LMULMAX8-LABEL: vector_arg_direct_stack: ; LMULMAX8-LABEL: vector_arg_direct_stack:
; LMULMAX8: # %bb.0: ; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: addi sp, sp, -16
; LMULMAX8-NEXT: .cfi_def_cfa_offset 16
; LMULMAX8-NEXT: li a0, 32 ; LMULMAX8-NEXT: li a0, 32
; LMULMAX8-NEXT: addi a1, sp, 8
; LMULMAX8-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; LMULMAX8-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; LMULMAX8-NEXT: addi a0, sp, 24 ; LMULMAX8-NEXT: vle32.v v24, (a1)
; LMULMAX8-NEXT: vle32.v v24, (a0)
; LMULMAX8-NEXT: vadd.vv v8, v8, v16 ; LMULMAX8-NEXT: vadd.vv v8, v8, v16
; LMULMAX8-NEXT: vadd.vv v8, v8, v24 ; LMULMAX8-NEXT: vadd.vv v8, v8, v24
; LMULMAX8-NEXT: addi sp, sp, 16
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX4-LABEL: vector_arg_direct_stack: ; LMULMAX4-LABEL: vector_arg_direct_stack:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: addi sp, sp, -16
; LMULMAX4-NEXT: .cfi_def_cfa_offset 16
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; LMULMAX4-NEXT: addi a0, sp, 24 ; LMULMAX4-NEXT: addi a0, sp, 8
; LMULMAX4-NEXT: vle32.v v24, (a0) ; LMULMAX4-NEXT: vle32.v v24, (a0)
; LMULMAX4-NEXT: addi a0, sp, 88 ; LMULMAX4-NEXT: addi a0, sp, 72
; LMULMAX4-NEXT: vle32.v v28, (a0) ; LMULMAX4-NEXT: vle32.v v28, (a0)
; LMULMAX4-NEXT: vadd.vv v12, v12, v20 ; LMULMAX4-NEXT: vadd.vv v12, v12, v20
; LMULMAX4-NEXT: vadd.vv v8, v8, v16 ; LMULMAX4-NEXT: vadd.vv v8, v8, v16
; LMULMAX4-NEXT: vadd.vv v8, v8, v24 ; LMULMAX4-NEXT: vadd.vv v8, v8, v24
; LMULMAX4-NEXT: vadd.vv v12, v12, v28 ; LMULMAX4-NEXT: vadd.vv v12, v12, v28
; LMULMAX4-NEXT: addi sp, sp, 16
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%s = add <32 x i32> %x, %y %s = add <32 x i32> %x, %y
%t = add <32 x i32> %s, %z %t = add <32 x i32> %s, %z
ret <32 x i32> %t ret <32 x i32> %t
} }
; Calling the function above. Ensure we pass the arguments correctly. ; Calling the function above. Ensure we pass the arguments correctly.
define fastcc <32 x i32> @pass_vector_arg_direct_stack(<32 x i32> %x, <32 x i32> %y, <32 x i32> %z) { define fastcc <32 x i32> @pass_vector_arg_direct_stack(<32 x i32> %x, <32 x i32> %y, <32 x i32> %z) {
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines; LMULMAX4-NEXT: ret
ret <32 x i32> %s ret <32 x i32> %s
} }
; A pathological test case where even with fastcc we must use the stack for ; A pathological test case where even with fastcc we must use the stack for
; mask argument %m2. %m1 is passed via v0. ; mask argument %m2. %m1 is passed via v0.
define fastcc <4 x i1> @vector_mask_arg_direct_stack(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12, i32 %13, <32 x i32> %x, <32 x i32> %y, <32 x i32> %z, <4 x i1> %m1, <4 x i1> %m2, i32 %last) { define fastcc <4 x i1> @vector_mask_arg_direct_stack(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12, i32 %13, <32 x i32> %x, <32 x i32> %y, <32 x i32> %z, <4 x i1> %m1, <4 x i1> %m2, i32 %last) {
; CHECK-LABEL: vector_mask_arg_direct_stack: ; CHECK-LABEL: vector_mask_arg_direct_stack:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi a0, sp, 136
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: addi a0, sp, 152
; CHECK-NEXT: vlm.v v8, (a0) ; CHECK-NEXT: vlm.v v8, (a0)
; CHECK-NEXT: vmxor.mm v0, v0, v8 ; CHECK-NEXT: vmxor.mm v0, v0, v8
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = xor <4 x i1> %m1, %m2 %r = xor <4 x i1> %m1, %m2
ret <4 x i1> %r ret <4 x i1> %r
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll

Show First 20 Lines • Show All 776 Lines • ▼ Show 20 Lines
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%t = call <32 x i32> @ext2(<32 x i32> %y, <32 x i32> %x, i32 %w, i32 2) %t = call <32 x i32> @ext2(<32 x i32> %y, <32 x i32> %x, i32 %w, i32 2)
ret <32 x i32> %t ret <32 x i32> %t
} }
define <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x i32> %y, <32 x i32> %z, i32 %w) { define <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x i32> %y, <32 x i32> %z, i32 %w) {
; LMULMAX8-LABEL: ret_v32i32_call_v32i32_v32i32_v32i32_i32: ; LMULMAX8-LABEL: ret_v32i32_call_v32i32_v32i32_v32i32_i32:
; LMULMAX8: # %bb.0: ; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: addi sp, sp, -384 ; LMULMAX8-NEXT: addi sp, sp, -256
; LMULMAX8-NEXT: .cfi_def_cfa_offset 384 ; LMULMAX8-NEXT: .cfi_def_cfa_offset 256
; LMULMAX8-NEXT: sd ra, 376(sp) # 8-byte Folded Spill ; LMULMAX8-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
; LMULMAX8-NEXT: sd s0, 368(sp) # 8-byte Folded Spill ; LMULMAX8-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
; LMULMAX8-NEXT: .cfi_offset ra, -8 ; LMULMAX8-NEXT: .cfi_offset ra, -8
; LMULMAX8-NEXT: .cfi_offset s0, -16 ; LMULMAX8-NEXT: .cfi_offset s0, -16
; LMULMAX8-NEXT: addi s0, sp, 384 ; LMULMAX8-NEXT: addi s0, sp, 256
; LMULMAX8-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX8-NEXT: .cfi_def_cfa s0, 0
; LMULMAX8-NEXT: andi sp, sp, -128 ; LMULMAX8-NEXT: andi sp, sp, -128
; LMULMAX8-NEXT: li a2, 32 ; LMULMAX8-NEXT: li a2, 32
; LMULMAX8-NEXT: vsetvli zero, a2, e32, m8, ta, mu ; LMULMAX8-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; LMULMAX8-NEXT: vle32.v v24, (a0) ; LMULMAX8-NEXT: vle32.v v24, (a0)
; LMULMAX8-NEXT: addi a0, sp, 128 ; LMULMAX8-NEXT: mv a3, sp
; LMULMAX8-NEXT: mv a0, sp
; LMULMAX8-NEXT: li a2, 42 ; LMULMAX8-NEXT: li a2, 42
; LMULMAX8-NEXT: addi a3, sp, 128
; LMULMAX8-NEXT: vse32.v v8, (a3) ; LMULMAX8-NEXT: vse32.v v8, (a3)
; LMULMAX8-NEXT: vmv.v.v v8, v24 ; LMULMAX8-NEXT: vmv.v.v v8, v24
; LMULMAX8-NEXT: call ext3@plt ; LMULMAX8-NEXT: call ext3@plt
; LMULMAX8-NEXT: addi sp, s0, -384 ; LMULMAX8-NEXT: addi sp, s0, -256
; LMULMAX8-NEXT: ld ra, 376(sp) # 8-byte Folded Reload ; LMULMAX8-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
; LMULMAX8-NEXT: ld s0, 368(sp) # 8-byte Folded Reload ; LMULMAX8-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; LMULMAX8-NEXT: addi sp, sp, 384 ; LMULMAX8-NEXT: addi sp, sp, 256
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX4-LABEL: ret_v32i32_call_v32i32_v32i32_v32i32_i32: ; LMULMAX4-LABEL: ret_v32i32_call_v32i32_v32i32_v32i32_i32:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: addi sp, sp, -384 ; LMULMAX4-NEXT: addi sp, sp, -256
; LMULMAX4-NEXT: .cfi_def_cfa_offset 384 ; LMULMAX4-NEXT: .cfi_def_cfa_offset 256
; LMULMAX4-NEXT: sd ra, 376(sp) # 8-byte Folded Spill ; LMULMAX4-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
; LMULMAX4-NEXT: sd s0, 368(sp) # 8-byte Folded Spill ; LMULMAX4-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
; LMULMAX4-NEXT: .cfi_offset ra, -8 ; LMULMAX4-NEXT: .cfi_offset ra, -8
; LMULMAX4-NEXT: .cfi_offset s0, -16 ; LMULMAX4-NEXT: .cfi_offset s0, -16
; LMULMAX4-NEXT: addi s0, sp, 384 ; LMULMAX4-NEXT: addi s0, sp, 256
; LMULMAX4-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX4-NEXT: .cfi_def_cfa s0, 0
; LMULMAX4-NEXT: andi sp, sp, -128 ; LMULMAX4-NEXT: andi sp, sp, -128
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; LMULMAX4-NEXT: vle32.v v24, (a0) ; LMULMAX4-NEXT: vle32.v v24, (a0)
; LMULMAX4-NEXT: addi a0, a0, 64 ; LMULMAX4-NEXT: addi a0, a0, 64
; LMULMAX4-NEXT: vle32.v v28, (a0) ; LMULMAX4-NEXT: vle32.v v28, (a0)
; LMULMAX4-NEXT: addi a0, sp, 192 ; LMULMAX4-NEXT: addi a0, sp, 64
; LMULMAX4-NEXT: vse32.v v12, (a0) ; LMULMAX4-NEXT: vse32.v v12, (a0)
; LMULMAX4-NEXT: addi a0, sp, 128 ; LMULMAX4-NEXT: mv a1, sp
; LMULMAX4-NEXT: mv a0, sp
; LMULMAX4-NEXT: li a3, 42 ; LMULMAX4-NEXT: li a3, 42
; LMULMAX4-NEXT: addi a1, sp, 128
; LMULMAX4-NEXT: vse32.v v8, (a1) ; LMULMAX4-NEXT: vse32.v v8, (a1)
; LMULMAX4-NEXT: vmv.v.v v8, v24 ; LMULMAX4-NEXT: vmv.v.v v8, v24
; LMULMAX4-NEXT: vmv.v.v v12, v28 ; LMULMAX4-NEXT: vmv.v.v v12, v28
; LMULMAX4-NEXT: call ext3@plt ; LMULMAX4-NEXT: call ext3@plt
; LMULMAX4-NEXT: addi sp, s0, -384 ; LMULMAX4-NEXT: addi sp, s0, -256
; LMULMAX4-NEXT: ld ra, 376(sp) # 8-byte Folded Reload ; LMULMAX4-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: ld s0, 368(sp) # 8-byte Folded Reload ; LMULMAX4-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: addi sp, sp, 384 ; LMULMAX4-NEXT: addi sp, sp, 256
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
; ;
; LMULMAX2-LABEL: ret_v32i32_call_v32i32_v32i32_v32i32_i32: ; LMULMAX2-LABEL: ret_v32i32_call_v32i32_v32i32_v32i32_i32:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi sp, sp, -384 ; LMULMAX2-NEXT: addi sp, sp, -256
; LMULMAX2-NEXT: .cfi_def_cfa_offset 384 ; LMULMAX2-NEXT: .cfi_def_cfa_offset 256
; LMULMAX2-NEXT: sd ra, 376(sp) # 8-byte Folded Spill ; LMULMAX2-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
; LMULMAX2-NEXT: sd s0, 368(sp) # 8-byte Folded Spill ; LMULMAX2-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
; LMULMAX2-NEXT: .cfi_offset ra, -8 ; LMULMAX2-NEXT: .cfi_offset ra, -8
; LMULMAX2-NEXT: .cfi_offset s0, -16 ; LMULMAX2-NEXT: .cfi_offset s0, -16
; LMULMAX2-NEXT: addi s0, sp, 384 ; LMULMAX2-NEXT: addi s0, sp, 256
; LMULMAX2-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX2-NEXT: .cfi_def_cfa s0, 0
; LMULMAX2-NEXT: andi sp, sp, -128 ; LMULMAX2-NEXT: andi sp, sp, -128
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-NEXT: vle32.v v24, (a0) ; LMULMAX2-NEXT: vle32.v v24, (a0)
; LMULMAX2-NEXT: addi a1, a0, 32 ; LMULMAX2-NEXT: addi a1, a0, 32
; LMULMAX2-NEXT: vle32.v v26, (a1) ; LMULMAX2-NEXT: vle32.v v26, (a1)
; LMULMAX2-NEXT: addi a1, a0, 64 ; LMULMAX2-NEXT: addi a1, a0, 64
; LMULMAX2-NEXT: vle32.v v28, (a1) ; LMULMAX2-NEXT: vle32.v v28, (a1)
; LMULMAX2-NEXT: addi a0, a0, 96 ; LMULMAX2-NEXT: addi a0, a0, 96
; LMULMAX2-NEXT: vle32.v v30, (a0) ; LMULMAX2-NEXT: vle32.v v30, (a0)
; LMULMAX2-NEXT: addi a0, sp, 224 ; LMULMAX2-NEXT: addi a0, sp, 96
; LMULMAX2-NEXT: vse32.v v14, (a0) ; LMULMAX2-NEXT: vse32.v v14, (a0)
; LMULMAX2-NEXT: addi a0, sp, 192 ; LMULMAX2-NEXT: addi a0, sp, 64
; LMULMAX2-NEXT: vse32.v v12, (a0) ; LMULMAX2-NEXT: vse32.v v12, (a0)
; LMULMAX2-NEXT: addi a0, sp, 160 ; LMULMAX2-NEXT: addi a0, sp, 32
; LMULMAX2-NEXT: vse32.v v10, (a0) ; LMULMAX2-NEXT: vse32.v v10, (a0)
; LMULMAX2-NEXT: addi a0, sp, 128 ; LMULMAX2-NEXT: mv a1, sp
; LMULMAX2-NEXT: mv a0, sp
; LMULMAX2-NEXT: li a5, 42 ; LMULMAX2-NEXT: li a5, 42
; LMULMAX2-NEXT: addi a1, sp, 128
; LMULMAX2-NEXT: vse32.v v8, (a1) ; LMULMAX2-NEXT: vse32.v v8, (a1)
; LMULMAX2-NEXT: vmv.v.v v8, v24 ; LMULMAX2-NEXT: vmv.v.v v8, v24
; LMULMAX2-NEXT: vmv.v.v v10, v26 ; LMULMAX2-NEXT: vmv.v.v v10, v26
; LMULMAX2-NEXT: vmv.v.v v12, v28 ; LMULMAX2-NEXT: vmv.v.v v12, v28
; LMULMAX2-NEXT: vmv.v.v v14, v30 ; LMULMAX2-NEXT: vmv.v.v v14, v30
; LMULMAX2-NEXT: call ext3@plt ; LMULMAX2-NEXT: call ext3@plt
; LMULMAX2-NEXT: addi sp, s0, -384 ; LMULMAX2-NEXT: addi sp, s0, -256
; LMULMAX2-NEXT: ld ra, 376(sp) # 8-byte Folded Reload ; LMULMAX2-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
; LMULMAX2-NEXT: ld s0, 368(sp) # 8-byte Folded Reload ; LMULMAX2-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; LMULMAX2-NEXT: addi sp, sp, 384 ; LMULMAX2-NEXT: addi sp, sp, 256
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: ret_v32i32_call_v32i32_v32i32_v32i32_i32: ; LMULMAX1-LABEL: ret_v32i32_call_v32i32_v32i32_v32i32_i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi sp, sp, -384 ; LMULMAX1-NEXT: addi sp, sp, -256
; LMULMAX1-NEXT: .cfi_def_cfa_offset 384 ; LMULMAX1-NEXT: .cfi_def_cfa_offset 256
; LMULMAX1-NEXT: sd ra, 376(sp) # 8-byte Folded Spill ; LMULMAX1-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
; LMULMAX1-NEXT: sd s0, 368(sp) # 8-byte Folded Spill ; LMULMAX1-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
; LMULMAX1-NEXT: sd s1, 360(sp) # 8-byte Folded Spill ; LMULMAX1-NEXT: sd s1, 232(sp) # 8-byte Folded Spill
; LMULMAX1-NEXT: .cfi_offset ra, -8 ; LMULMAX1-NEXT: .cfi_offset ra, -8
; LMULMAX1-NEXT: .cfi_offset s0, -16 ; LMULMAX1-NEXT: .cfi_offset s0, -16
; LMULMAX1-NEXT: .cfi_offset s1, -24 ; LMULMAX1-NEXT: .cfi_offset s1, -24
; LMULMAX1-NEXT: addi s0, sp, 384 ; LMULMAX1-NEXT: addi s0, sp, 256
; LMULMAX1-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX1-NEXT: .cfi_def_cfa s0, 0
; LMULMAX1-NEXT: andi sp, sp, -128 ; LMULMAX1-NEXT: andi sp, sp, -128
; LMULMAX1-NEXT: mv s1, sp ; LMULMAX1-NEXT: mv s1, sp
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vle32.v v24, (a0) ; LMULMAX1-NEXT: vle32.v v24, (a0)
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vle32.v v25, (a1) ; LMULMAX1-NEXT: vle32.v v25, (a1)
; LMULMAX1-NEXT: addi a1, a0, 32 ; LMULMAX1-NEXT: addi a1, a0, 32
; LMULMAX1-NEXT: vle32.v v26, (a1) ; LMULMAX1-NEXT: vle32.v v26, (a1)
; LMULMAX1-NEXT: addi a1, a0, 48 ; LMULMAX1-NEXT: addi a1, a0, 48
; LMULMAX1-NEXT: vle32.v v27, (a1) ; LMULMAX1-NEXT: vle32.v v27, (a1)
; LMULMAX1-NEXT: addi a1, a0, 64 ; LMULMAX1-NEXT: addi a1, a0, 64
; LMULMAX1-NEXT: vle32.v v28, (a1) ; LMULMAX1-NEXT: vle32.v v28, (a1)
; LMULMAX1-NEXT: addi a1, a0, 80 ; LMULMAX1-NEXT: addi a1, a0, 80
; LMULMAX1-NEXT: vle32.v v29, (a1) ; LMULMAX1-NEXT: vle32.v v29, (a1)
; LMULMAX1-NEXT: addi a1, a0, 96 ; LMULMAX1-NEXT: addi a1, a0, 96
; LMULMAX1-NEXT: vle32.v v30, (a1) ; LMULMAX1-NEXT: vle32.v v30, (a1)
; LMULMAX1-NEXT: addi a0, a0, 112 ; LMULMAX1-NEXT: addi a0, a0, 112
; LMULMAX1-NEXT: vle32.v v31, (a0) ; LMULMAX1-NEXT: vle32.v v31, (a0)
; LMULMAX1-NEXT: ld a0, 0(s0) ; LMULMAX1-NEXT: ld a1, 0(s0)
; LMULMAX1-NEXT: addi sp, sp, -16 ; LMULMAX1-NEXT: addi sp, sp, -16
; LMULMAX1-NEXT: addi a1, s1, 240 ; LMULMAX1-NEXT: addi a0, s1, 112
; LMULMAX1-NEXT: vse32.v v15, (a1) ; LMULMAX1-NEXT: vse32.v v15, (a0)
; LMULMAX1-NEXT: addi a1, s1, 224 ; LMULMAX1-NEXT: addi a0, s1, 96
; LMULMAX1-NEXT: vse32.v v14, (a1) ; LMULMAX1-NEXT: vse32.v v14, (a0)
; LMULMAX1-NEXT: addi a1, s1, 208 ; LMULMAX1-NEXT: addi a0, s1, 80
; LMULMAX1-NEXT: vse32.v v13, (a1) ; LMULMAX1-NEXT: vse32.v v13, (a0)
; LMULMAX1-NEXT: addi a1, s1, 192 ; LMULMAX1-NEXT: addi a0, s1, 64
; LMULMAX1-NEXT: vse32.v v12, (a1) ; LMULMAX1-NEXT: vse32.v v12, (a0)
; LMULMAX1-NEXT: addi a1, s1, 176 ; LMULMAX1-NEXT: addi a0, s1, 48
; LMULMAX1-NEXT: vse32.v v11, (a1) ; LMULMAX1-NEXT: vse32.v v11, (a0)
; LMULMAX1-NEXT: addi a1, s1, 160 ; LMULMAX1-NEXT: addi a0, s1, 32
; LMULMAX1-NEXT: vse32.v v10, (a1) ; LMULMAX1-NEXT: vse32.v v10, (a0)
; LMULMAX1-NEXT: addi a1, s1, 144 ; LMULMAX1-NEXT: addi a0, s1, 16
; LMULMAX1-NEXT: vse32.v v9, (a1) ; LMULMAX1-NEXT: vse32.v v9, (a0)
; LMULMAX1-NEXT: li a1, 42 ; LMULMAX1-NEXT: mv a0, s1
; LMULMAX1-NEXT: sd a1, 8(sp) ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: sd a0, 0(sp) ; LMULMAX1-NEXT: li a0, 42
; LMULMAX1-NEXT: addi a0, s1, 128 ; LMULMAX1-NEXT: sd a0, 8(sp)
; LMULMAX1-NEXT: addi a1, s1, 128 ; LMULMAX1-NEXT: mv a0, s1
; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: sd a1, 0(sp)
; LMULMAX1-NEXT: vmv.v.v v8, v24 ; LMULMAX1-NEXT: vmv.v.v v8, v24
; LMULMAX1-NEXT: vmv.v.v v9, v25 ; LMULMAX1-NEXT: vmv.v.v v9, v25
; LMULMAX1-NEXT: vmv.v.v v10, v26 ; LMULMAX1-NEXT: vmv.v.v v10, v26
; LMULMAX1-NEXT: vmv.v.v v11, v27 ; LMULMAX1-NEXT: vmv.v.v v11, v27
; LMULMAX1-NEXT: vmv.v.v v12, v28 ; LMULMAX1-NEXT: vmv.v.v v12, v28
; LMULMAX1-NEXT: vmv.v.v v13, v29 ; LMULMAX1-NEXT: vmv.v.v v13, v29
; LMULMAX1-NEXT: vmv.v.v v14, v30 ; LMULMAX1-NEXT: vmv.v.v v14, v30
; LMULMAX1-NEXT: vmv.v.v v15, v31 ; LMULMAX1-NEXT: vmv.v.v v15, v31
; LMULMAX1-NEXT: call ext3@plt ; LMULMAX1-NEXT: call ext3@plt
; LMULMAX1-NEXT: addi sp, sp, 16 ; LMULMAX1-NEXT: addi sp, sp, 16
; LMULMAX1-NEXT: addi sp, s0, -384 ; LMULMAX1-NEXT: addi sp, s0, -256
; LMULMAX1-NEXT: ld ra, 376(sp) # 8-byte Folded Reload ; LMULMAX1-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
; LMULMAX1-NEXT: ld s0, 368(sp) # 8-byte Folded Reload ; LMULMAX1-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; LMULMAX1-NEXT: ld s1, 360(sp) # 8-byte Folded Reload ; LMULMAX1-NEXT: ld s1, 232(sp) # 8-byte Folded Reload
; LMULMAX1-NEXT: addi sp, sp, 384 ; LMULMAX1-NEXT: addi sp, sp, 256
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%t = call <32 x i32> @ext3(<32 x i32> %z, <32 x i32> %y, <32 x i32> %x, i32 %w, i32 42) %t = call <32 x i32> @ext3(<32 x i32> %z, <32 x i32> %y, <32 x i32> %x, i32 %w, i32 42)
ret <32 x i32> %t ret <32 x i32> %t
} }
; Test various configurations of split vector types where the values are split ; Test various configurations of split vector types where the values are split
; across both registers and the stack. ; across both registers and the stack.
; LMUL8: Ins: v8,v9,v10,v11,v12, v16m8 y[0:31], a0+0 z[0:31] ; LMUL8: Ins: v8,v9,v10,v11,v12, v16m8 y[0:31], a0+0 z[0:31]
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%v0 = add <32 x i32> %y, %z %v0 = add <32 x i32> %y, %z
ret <32 x i32> %v0 ret <32 x i32> %v0
} }
define <32 x i32> @call_split_vector_args(<2 x i32>* %pa, <32 x i32>* %pb) { define <32 x i32> @call_split_vector_args(<2 x i32>* %pa, <32 x i32>* %pb) {
; LMULMAX8-LABEL: call_split_vector_args: ; LMULMAX8-LABEL: call_split_vector_args:
; LMULMAX8: # %bb.0: ; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: addi sp, sp, -384 ; LMULMAX8-NEXT: addi sp, sp, -256
; LMULMAX8-NEXT: .cfi_def_cfa_offset 384 ; LMULMAX8-NEXT: .cfi_def_cfa_offset 256
; LMULMAX8-NEXT: sd ra, 376(sp) # 8-byte Folded Spill ; LMULMAX8-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
; LMULMAX8-NEXT: sd s0, 368(sp) # 8-byte Folded Spill ; LMULMAX8-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
; LMULMAX8-NEXT: .cfi_offset ra, -8 ; LMULMAX8-NEXT: .cfi_offset ra, -8
; LMULMAX8-NEXT: .cfi_offset s0, -16 ; LMULMAX8-NEXT: .cfi_offset s0, -16
; LMULMAX8-NEXT: addi s0, sp, 384 ; LMULMAX8-NEXT: addi s0, sp, 256
; LMULMAX8-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX8-NEXT: .cfi_def_cfa s0, 0
; LMULMAX8-NEXT: andi sp, sp, -128 ; LMULMAX8-NEXT: andi sp, sp, -128
; LMULMAX8-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX8-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX8-NEXT: vle32.v v8, (a0) ; LMULMAX8-NEXT: vle32.v v8, (a0)
; LMULMAX8-NEXT: li a0, 32 ; LMULMAX8-NEXT: li a0, 32
; LMULMAX8-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; LMULMAX8-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; LMULMAX8-NEXT: vle32.v v16, (a1) ; LMULMAX8-NEXT: vle32.v v16, (a1)
; LMULMAX8-NEXT: addi a0, sp, 128 ; LMULMAX8-NEXT: mv a1, sp
; LMULMAX8-NEXT: addi a1, sp, 128 ; LMULMAX8-NEXT: mv a0, sp
; LMULMAX8-NEXT: vse32.v v16, (a1) ; LMULMAX8-NEXT: vse32.v v16, (a1)
; LMULMAX8-NEXT: vmv1r.v v9, v8 ; LMULMAX8-NEXT: vmv1r.v v9, v8
; LMULMAX8-NEXT: vmv1r.v v10, v8 ; LMULMAX8-NEXT: vmv1r.v v10, v8
; LMULMAX8-NEXT: vmv1r.v v11, v8 ; LMULMAX8-NEXT: vmv1r.v v11, v8
; LMULMAX8-NEXT: vmv1r.v v12, v8 ; LMULMAX8-NEXT: vmv1r.v v12, v8
; LMULMAX8-NEXT: call split_vector_args@plt ; LMULMAX8-NEXT: call split_vector_args@plt
; LMULMAX8-NEXT: addi sp, s0, -384 ; LMULMAX8-NEXT: addi sp, s0, -256
; LMULMAX8-NEXT: ld ra, 376(sp) # 8-byte Folded Reload ; LMULMAX8-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
; LMULMAX8-NEXT: ld s0, 368(sp) # 8-byte Folded Reload ; LMULMAX8-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; LMULMAX8-NEXT: addi sp, sp, 384 ; LMULMAX8-NEXT: addi sp, sp, 256
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX4-LABEL: call_split_vector_args: ; LMULMAX4-LABEL: call_split_vector_args:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: addi sp, sp, -384 ; LMULMAX4-NEXT: addi sp, sp, -256
; LMULMAX4-NEXT: .cfi_def_cfa_offset 384 ; LMULMAX4-NEXT: .cfi_def_cfa_offset 256
; LMULMAX4-NEXT: sd ra, 376(sp) # 8-byte Folded Spill ; LMULMAX4-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
; LMULMAX4-NEXT: sd s0, 368(sp) # 8-byte Folded Spill ; LMULMAX4-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
; LMULMAX4-NEXT: .cfi_offset ra, -8 ; LMULMAX4-NEXT: .cfi_offset ra, -8
; LMULMAX4-NEXT: .cfi_offset s0, -16 ; LMULMAX4-NEXT: .cfi_offset s0, -16
; LMULMAX4-NEXT: addi s0, sp, 384 ; LMULMAX4-NEXT: addi s0, sp, 256
; LMULMAX4-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX4-NEXT: .cfi_def_cfa s0, 0
; LMULMAX4-NEXT: andi sp, sp, -128 ; LMULMAX4-NEXT: andi sp, sp, -128
; LMULMAX4-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX4-NEXT: vle32.v v8, (a0) ; LMULMAX4-NEXT: vle32.v v8, (a0)
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; LMULMAX4-NEXT: vle32.v v16, (a1) ; LMULMAX4-NEXT: vle32.v v16, (a1)
; LMULMAX4-NEXT: addi a0, a1, 64 ; LMULMAX4-NEXT: addi a0, a1, 64
; LMULMAX4-NEXT: vle32.v v20, (a0) ; LMULMAX4-NEXT: vle32.v v20, (a0)
; LMULMAX4-NEXT: addi a0, sp, 192 ; LMULMAX4-NEXT: addi a0, sp, 64
; LMULMAX4-NEXT: vse32.v v20, (a0) ; LMULMAX4-NEXT: vse32.v v20, (a0)
; LMULMAX4-NEXT: addi a0, sp, 128 ; LMULMAX4-NEXT: mv a1, sp
; LMULMAX4-NEXT: addi a1, sp, 128 ; LMULMAX4-NEXT: mv a0, sp
; LMULMAX4-NEXT: vse32.v v16, (a1) ; LMULMAX4-NEXT: vse32.v v16, (a1)
; LMULMAX4-NEXT: vmv1r.v v9, v8 ; LMULMAX4-NEXT: vmv1r.v v9, v8
; LMULMAX4-NEXT: vmv1r.v v10, v8 ; LMULMAX4-NEXT: vmv1r.v v10, v8
; LMULMAX4-NEXT: vmv1r.v v11, v8 ; LMULMAX4-NEXT: vmv1r.v v11, v8
; LMULMAX4-NEXT: vmv1r.v v12, v8 ; LMULMAX4-NEXT: vmv1r.v v12, v8
; LMULMAX4-NEXT: call split_vector_args@plt ; LMULMAX4-NEXT: call split_vector_args@plt
; LMULMAX4-NEXT: addi sp, s0, -384 ; LMULMAX4-NEXT: addi sp, s0, -256
; LMULMAX4-NEXT: ld ra, 376(sp) # 8-byte Folded Reload ; LMULMAX4-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: ld s0, 368(sp) # 8-byte Folded Reload ; LMULMAX4-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: addi sp, sp, 384 ; LMULMAX4-NEXT: addi sp, sp, 256
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
; ;
; LMULMAX2-LABEL: call_split_vector_args: ; LMULMAX2-LABEL: call_split_vector_args:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi sp, sp, -256 ; LMULMAX2-NEXT: addi sp, sp, -128
; LMULMAX2-NEXT: .cfi_def_cfa_offset 256 ; LMULMAX2-NEXT: .cfi_def_cfa_offset 128
; LMULMAX2-NEXT: sd ra, 248(sp) # 8-byte Folded Spill ; LMULMAX2-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
; LMULMAX2-NEXT: sd s0, 240(sp) # 8-byte Folded Spill ; LMULMAX2-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
; LMULMAX2-NEXT: .cfi_offset ra, -8 ; LMULMAX2-NEXT: .cfi_offset ra, -8
; LMULMAX2-NEXT: .cfi_offset s0, -16 ; LMULMAX2-NEXT: .cfi_offset s0, -16
; LMULMAX2-NEXT: addi s0, sp, 256 ; LMULMAX2-NEXT: addi s0, sp, 128
; LMULMAX2-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX2-NEXT: .cfi_def_cfa s0, 0
; LMULMAX2-NEXT: andi sp, sp, -128 ; LMULMAX2-NEXT: andi sp, sp, -128
; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX2-NEXT: vle32.v v8, (a0) ; LMULMAX2-NEXT: vle32.v v8, (a0)
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-NEXT: vle32.v v14, (a1) ; LMULMAX2-NEXT: vle32.v v14, (a1)
; LMULMAX2-NEXT: addi a0, a1, 32 ; LMULMAX2-NEXT: addi a0, a1, 32
; LMULMAX2-NEXT: vle32.v v16, (a0) ; LMULMAX2-NEXT: vle32.v v16, (a0)
; LMULMAX2-NEXT: addi a0, a1, 64 ; LMULMAX2-NEXT: addi a0, a1, 64
; LMULMAX2-NEXT: vle32.v v18, (a0) ; LMULMAX2-NEXT: vle32.v v18, (a0)
; LMULMAX2-NEXT: addi a0, a1, 96 ; LMULMAX2-NEXT: addi a0, a1, 96
; LMULMAX2-NEXT: vle32.v v20, (a0) ; LMULMAX2-NEXT: vle32.v v20, (a0)
; LMULMAX2-NEXT: addi a0, sp, 192 ; LMULMAX2-NEXT: addi a0, sp, 64
; LMULMAX2-NEXT: vse32.v v20, (a0) ; LMULMAX2-NEXT: vse32.v v20, (a0)
; LMULMAX2-NEXT: addi a0, sp, 160 ; LMULMAX2-NEXT: addi a0, sp, 32
; LMULMAX2-NEXT: vse32.v v18, (a0) ; LMULMAX2-NEXT: vse32.v v18, (a0)
; LMULMAX2-NEXT: addi a0, sp, 128 ; LMULMAX2-NEXT: mv a1, sp
; LMULMAX2-NEXT: addi a1, sp, 128 ; LMULMAX2-NEXT: mv a0, sp
; LMULMAX2-NEXT: vse32.v v16, (a1) ; LMULMAX2-NEXT: vse32.v v16, (a1)
; LMULMAX2-NEXT: vmv1r.v v9, v8 ; LMULMAX2-NEXT: vmv1r.v v9, v8
; LMULMAX2-NEXT: vmv1r.v v10, v8 ; LMULMAX2-NEXT: vmv1r.v v10, v8
; LMULMAX2-NEXT: vmv1r.v v11, v8 ; LMULMAX2-NEXT: vmv1r.v v11, v8
; LMULMAX2-NEXT: vmv1r.v v12, v8 ; LMULMAX2-NEXT: vmv1r.v v12, v8
; LMULMAX2-NEXT: vmv.v.v v22, v14 ; LMULMAX2-NEXT: vmv.v.v v22, v14
; LMULMAX2-NEXT: call split_vector_args@plt ; LMULMAX2-NEXT: call split_vector_args@plt
; LMULMAX2-NEXT: addi sp, s0, -256 ; LMULMAX2-NEXT: addi sp, s0, -128
; LMULMAX2-NEXT: ld ra, 248(sp) # 8-byte Folded Reload ; LMULMAX2-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
; LMULMAX2-NEXT: ld s0, 240(sp) # 8-byte Folded Reload ; LMULMAX2-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
; LMULMAX2-NEXT: addi sp, sp, 256 ; LMULMAX2-NEXT: addi sp, sp, 128
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: call_split_vector_args: ; LMULMAX1-LABEL: call_split_vector_args:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi sp, sp, -256 ; LMULMAX1-NEXT: addi sp, sp, -128
; LMULMAX1-NEXT: .cfi_def_cfa_offset 256 ; LMULMAX1-NEXT: .cfi_def_cfa_offset 128
; LMULMAX1-NEXT: sd ra, 248(sp) # 8-byte Folded Spill ; LMULMAX1-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
; LMULMAX1-NEXT: sd s0, 240(sp) # 8-byte Folded Spill ; LMULMAX1-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
; LMULMAX1-NEXT: .cfi_offset ra, -8 ; LMULMAX1-NEXT: .cfi_offset ra, -8
; LMULMAX1-NEXT: .cfi_offset s0, -16 ; LMULMAX1-NEXT: .cfi_offset s0, -16
; LMULMAX1-NEXT: addi s0, sp, 256 ; LMULMAX1-NEXT: addi s0, sp, 128
; LMULMAX1-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX1-NEXT: .cfi_def_cfa s0, 0
; LMULMAX1-NEXT: andi sp, sp, -128 ; LMULMAX1-NEXT: andi sp, sp, -128
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vle32.v v8, (a0) ; LMULMAX1-NEXT: vle32.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vle32.v v13, (a1) ; LMULMAX1-NEXT: vle32.v v13, (a1)
; LMULMAX1-NEXT: addi a0, a1, 32 ; LMULMAX1-NEXT: addi a0, a1, 32
; LMULMAX1-NEXT: vle32.v v15, (a0) ; LMULMAX1-NEXT: vle32.v v15, (a0)
; LMULMAX1-NEXT: addi a0, a1, 16 ; LMULMAX1-NEXT: addi a0, a1, 16
; LMULMAX1-NEXT: vle32.v v14, (a0) ; LMULMAX1-NEXT: vle32.v v14, (a0)
; LMULMAX1-NEXT: addi a0, a1, 48 ; LMULMAX1-NEXT: addi a0, a1, 48
; LMULMAX1-NEXT: vle32.v v16, (a0) ; LMULMAX1-NEXT: vle32.v v16, (a0)
; LMULMAX1-NEXT: addi a0, a1, 64 ; LMULMAX1-NEXT: addi a0, a1, 64
; LMULMAX1-NEXT: vle32.v v17, (a0) ; LMULMAX1-NEXT: vle32.v v17, (a0)
; LMULMAX1-NEXT: addi a0, a1, 80 ; LMULMAX1-NEXT: addi a0, a1, 80
; LMULMAX1-NEXT: vle32.v v18, (a0) ; LMULMAX1-NEXT: vle32.v v18, (a0)
; LMULMAX1-NEXT: addi a0, a1, 96 ; LMULMAX1-NEXT: addi a0, a1, 96
; LMULMAX1-NEXT: vle32.v v19, (a0) ; LMULMAX1-NEXT: vle32.v v19, (a0)
; LMULMAX1-NEXT: addi a0, a1, 112 ; LMULMAX1-NEXT: addi a0, a1, 112
; LMULMAX1-NEXT: vle32.v v20, (a0) ; LMULMAX1-NEXT: vle32.v v20, (a0)
; LMULMAX1-NEXT: addi a0, sp, 192 ; LMULMAX1-NEXT: addi a0, sp, 64
; LMULMAX1-NEXT: vse32.v v20, (a0) ; LMULMAX1-NEXT: vse32.v v20, (a0)
; LMULMAX1-NEXT: addi a0, sp, 176 ; LMULMAX1-NEXT: addi a0, sp, 48
; LMULMAX1-NEXT: vse32.v v19, (a0) ; LMULMAX1-NEXT: vse32.v v19, (a0)
; LMULMAX1-NEXT: addi a0, sp, 160 ; LMULMAX1-NEXT: addi a0, sp, 32
; LMULMAX1-NEXT: vse32.v v18, (a0) ; LMULMAX1-NEXT: vse32.v v18, (a0)
; LMULMAX1-NEXT: addi a0, sp, 144 ; LMULMAX1-NEXT: addi a0, sp, 16
; LMULMAX1-NEXT: vse32.v v17, (a0) ; LMULMAX1-NEXT: vse32.v v17, (a0)
; LMULMAX1-NEXT: addi a0, sp, 128 ; LMULMAX1-NEXT: mv a1, sp
; LMULMAX1-NEXT: addi a1, sp, 128 ; LMULMAX1-NEXT: mv a0, sp
; LMULMAX1-NEXT: vse32.v v16, (a1) ; LMULMAX1-NEXT: vse32.v v16, (a1)
; LMULMAX1-NEXT: vmv1r.v v9, v8 ; LMULMAX1-NEXT: vmv1r.v v9, v8
; LMULMAX1-NEXT: vmv1r.v v10, v8 ; LMULMAX1-NEXT: vmv1r.v v10, v8
; LMULMAX1-NEXT: vmv1r.v v11, v8 ; LMULMAX1-NEXT: vmv1r.v v11, v8
; LMULMAX1-NEXT: vmv1r.v v12, v8 ; LMULMAX1-NEXT: vmv1r.v v12, v8
; LMULMAX1-NEXT: vmv.v.v v21, v13 ; LMULMAX1-NEXT: vmv.v.v v21, v13
; LMULMAX1-NEXT: vmv.v.v v22, v14 ; LMULMAX1-NEXT: vmv.v.v v22, v14
; LMULMAX1-NEXT: vmv.v.v v23, v15 ; LMULMAX1-NEXT: vmv.v.v v23, v15
; LMULMAX1-NEXT: call split_vector_args@plt ; LMULMAX1-NEXT: call split_vector_args@plt
; LMULMAX1-NEXT: addi sp, s0, -256 ; LMULMAX1-NEXT: addi sp, s0, -128
; LMULMAX1-NEXT: ld ra, 248(sp) # 8-byte Folded Reload ; LMULMAX1-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
; LMULMAX1-NEXT: ld s0, 240(sp) # 8-byte Folded Reload ; LMULMAX1-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
; LMULMAX1-NEXT: addi sp, sp, 256 ; LMULMAX1-NEXT: addi sp, sp, 128
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %pa %a = load <2 x i32>, <2 x i32>* %pa
%b = load <32 x i32>, <32 x i32>* %pb %b = load <32 x i32>, <32 x i32>* %pb
%r = call <32 x i32> @split_vector_args(<2 x i32> %a, <2 x i32> %a, <2 x i32> %a, <2 x i32> %a, <2 x i32> %a, <32 x i32> %b, <32 x i32> %b) %r = call <32 x i32> @split_vector_args(<2 x i32> %a, <2 x i32> %a, <2 x i32> %a, <2 x i32> %a, <2 x i32> %a, <32 x i32> %b, <32 x i32> %b)
ret <32 x i32> %r ret <32 x i32> %r
} }
; A rather pathological test case in which we exhaust all vector registers and ; A rather pathological test case in which we exhaust all vector registers and
; all scalar registers, forcing %z and %8 to go through the stack. ; all scalar registers, forcing %z and %8 to go through the stack.
define <32 x i32> @vector_arg_via_stack(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, <32 x i32> %x, <32 x i32> %y, <32 x i32> %z, i32 %8) { define <32 x i32> @vector_arg_via_stack(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, <32 x i32> %x, <32 x i32> %y, <32 x i32> %z, i32 %8) {
; LMULMAX8-LABEL: vector_arg_via_stack: ; LMULMAX8-LABEL: vector_arg_via_stack:
; LMULMAX8: # %bb.0: ; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: addi sp, sp, -16
; LMULMAX8-NEXT: .cfi_def_cfa_offset 16
; LMULMAX8-NEXT: li a0, 32 ; LMULMAX8-NEXT: li a0, 32
; LMULMAX8-NEXT: mv a1, sp
; LMULMAX8-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; LMULMAX8-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; LMULMAX8-NEXT: addi a0, sp, 16 ; LMULMAX8-NEXT: vle32.v v16, (a1)
; LMULMAX8-NEXT: vle32.v v16, (a0)
; LMULMAX8-NEXT: vadd.vv v8, v8, v16 ; LMULMAX8-NEXT: vadd.vv v8, v8, v16
; LMULMAX8-NEXT: addi sp, sp, 16
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX4-LABEL: vector_arg_via_stack: ; LMULMAX4-LABEL: vector_arg_via_stack:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: addi sp, sp, -16
; LMULMAX4-NEXT: .cfi_def_cfa_offset 16
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; LMULMAX4-NEXT: addi a0, sp, 16 ; LMULMAX4-NEXT: mv a0, sp
; LMULMAX4-NEXT: vle32.v v16, (a0) ; LMULMAX4-NEXT: vle32.v v16, (a0)
; LMULMAX4-NEXT: addi a0, sp, 80 ; LMULMAX4-NEXT: addi a0, sp, 64
; LMULMAX4-NEXT: vle32.v v20, (a0) ; LMULMAX4-NEXT: vle32.v v20, (a0)
; LMULMAX4-NEXT: vadd.vv v8, v8, v16 ; LMULMAX4-NEXT: vadd.vv v8, v8, v16
; LMULMAX4-NEXT: vadd.vv v12, v12, v20 ; LMULMAX4-NEXT: vadd.vv v12, v12, v20
; LMULMAX4-NEXT: addi sp, sp, 16
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
; ;
; LMULMAX2-LABEL: vector_arg_via_stack: ; LMULMAX2-LABEL: vector_arg_via_stack:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi sp, sp, -16
; LMULMAX2-NEXT: .cfi_def_cfa_offset 16
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-NEXT: addi a0, sp, 16 ; LMULMAX2-NEXT: addi a0, sp, 64
; LMULMAX2-NEXT: vle32.v v16, (a0) ; LMULMAX2-NEXT: vle32.v v16, (a0)
; LMULMAX2-NEXT: addi a0, sp, 48 ; LMULMAX2-NEXT: mv a0, sp
; LMULMAX2-NEXT: vle32.v v18, (a0) ; LMULMAX2-NEXT: vle32.v v18, (a0)
; LMULMAX2-NEXT: addi a0, sp, 80 ; LMULMAX2-NEXT: addi a0, sp, 32
; LMULMAX2-NEXT: vle32.v v20, (a0) ; LMULMAX2-NEXT: vle32.v v20, (a0)
; LMULMAX2-NEXT: addi a0, sp, 112 ; LMULMAX2-NEXT: addi a0, sp, 96
; LMULMAX2-NEXT: vle32.v v22, (a0) ; LMULMAX2-NEXT: vle32.v v22, (a0)
; LMULMAX2-NEXT: vadd.vv v8, v8, v16 ; LMULMAX2-NEXT: vadd.vv v8, v8, v18
; LMULMAX2-NEXT: vadd.vv v10, v10, v18 ; LMULMAX2-NEXT: vadd.vv v10, v10, v20
; LMULMAX2-NEXT: vadd.vv v12, v12, v20 ; LMULMAX2-NEXT: vadd.vv v12, v12, v16
; LMULMAX2-NEXT: vadd.vv v14, v14, v22 ; LMULMAX2-NEXT: vadd.vv v14, v14, v22
; LMULMAX2-NEXT: addi sp, sp, 16
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: vector_arg_via_stack: ; LMULMAX1-LABEL: vector_arg_via_stack:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi sp, sp, -16 ; LMULMAX1-NEXT: addi a0, sp, 112
; LMULMAX1-NEXT: .cfi_def_cfa_offset 16
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: addi a0, sp, 128
; LMULMAX1-NEXT: vle32.v v16, (a0) ; LMULMAX1-NEXT: vle32.v v16, (a0)
; LMULMAX1-NEXT: addi a0, sp, 112
; LMULMAX1-NEXT: vle32.v v17, (a0)
; LMULMAX1-NEXT: addi a0, sp, 96 ; LMULMAX1-NEXT: addi a0, sp, 96
; LMULMAX1-NEXT: vle32.v v18, (a0) ; LMULMAX1-NEXT: vle32.v v17, (a0)
; LMULMAX1-NEXT: addi a0, sp, 80 ; LMULMAX1-NEXT: addi a0, sp, 80
; LMULMAX1-NEXT: vle32.v v18, (a0)
; LMULMAX1-NEXT: addi a0, sp, 64
; LMULMAX1-NEXT: vle32.v v19, (a0) ; LMULMAX1-NEXT: vle32.v v19, (a0)
; LMULMAX1-NEXT: addi a0, sp, 16
; LMULMAX1-NEXT: vle32.v v20, (a0)
; LMULMAX1-NEXT: addi a0, sp, 32 ; LMULMAX1-NEXT: addi a0, sp, 32
; LMULMAX1-NEXT: vle32.v v20, (a0)
; LMULMAX1-NEXT: mv a0, sp
; LMULMAX1-NEXT: vle32.v v21, (a0) ; LMULMAX1-NEXT: vle32.v v21, (a0)
; LMULMAX1-NEXT: addi a0, sp, 48 ; LMULMAX1-NEXT: addi a0, sp, 16
; LMULMAX1-NEXT: vle32.v v22, (a0) ; LMULMAX1-NEXT: vle32.v v22, (a0)
; LMULMAX1-NEXT: addi a0, sp, 64 ; LMULMAX1-NEXT: addi a0, sp, 48
; LMULMAX1-NEXT: vle32.v v23, (a0) ; LMULMAX1-NEXT: vle32.v v23, (a0)
; LMULMAX1-NEXT: vadd.vv v8, v8, v20 ; LMULMAX1-NEXT: vadd.vv v8, v8, v21
; LMULMAX1-NEXT: vadd.vv v9, v9, v21 ; LMULMAX1-NEXT: vadd.vv v9, v9, v22
; LMULMAX1-NEXT: vadd.vv v10, v10, v22 ; LMULMAX1-NEXT: vadd.vv v10, v10, v20
; LMULMAX1-NEXT: vadd.vv v11, v11, v23 ; LMULMAX1-NEXT: vadd.vv v11, v11, v23
; LMULMAX1-NEXT: vadd.vv v12, v12, v19 ; LMULMAX1-NEXT: vadd.vv v12, v12, v19
; LMULMAX1-NEXT: vadd.vv v13, v13, v18 ; LMULMAX1-NEXT: vadd.vv v13, v13, v18
; LMULMAX1-NEXT: vadd.vv v14, v14, v17 ; LMULMAX1-NEXT: vadd.vv v14, v14, v17
; LMULMAX1-NEXT: vadd.vv v15, v15, v16 ; LMULMAX1-NEXT: vadd.vv v15, v15, v16
; LMULMAX1-NEXT: addi sp, sp, 16
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%s = add <32 x i32> %x, %z %s = add <32 x i32> %x, %z
ret <32 x i32> %s ret <32 x i32> %s
} }
; Calling the function above. Ensure we pass the arguments correctly. ; Calling the function above. Ensure we pass the arguments correctly.
define <32 x i32> @pass_vector_arg_via_stack(<32 x i32> %x, <32 x i32> %y, <32 x i32> %z) { define <32 x i32> @pass_vector_arg_via_stack(<32 x i32> %x, <32 x i32> %y, <32 x i32> %z) {
; LMULMAX8-LABEL: pass_vector_arg_via_stack: ; LMULMAX8-LABEL: pass_vector_arg_via_stack:
▲ Show 20 Lines • Show All 144 Lines • ▼ Show 20 Lines; LMULMAX1-NEXT: ret
ret <32 x i32> %s ret <32 x i32> %s
} }
; Another pathological case but where a small mask vector must be passed on the ; Another pathological case but where a small mask vector must be passed on the
; stack. ; stack.
define <4 x i1> @vector_mask_arg_via_stack(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, <32 x i32> %x, <32 x i32> %y, <32 x i32> %z, i32 %8, <4 x i1> %9, <4 x i1> %10) { define <4 x i1> @vector_mask_arg_via_stack(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, <32 x i32> %x, <32 x i32> %y, <32 x i32> %z, i32 %8, <4 x i1> %9, <4 x i1> %10) {
; CHECK-LABEL: vector_mask_arg_via_stack: ; CHECK-LABEL: vector_mask_arg_via_stack:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi a0, sp, 136
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: addi a0, sp, 152
; CHECK-NEXT: vlm.v v0, (a0) ; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
ret <4 x i1> %10 ret <4 x i1> %10
} }
; Calling the function above. Ensure we pass the mask arguments correctly. We ; Calling the function above. Ensure we pass the mask arguments correctly. We
; legalize stores of small masks such that the value is at least byte-sized. ; legalize stores of small masks such that the value is at least byte-sized.
define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) { define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) {
; LMULMAX8-LABEL: pass_vector_mask_arg_via_stack: ; LMULMAX8-LABEL: pass_vector_mask_arg_via_stack:
▲ Show 20 Lines • Show All 189 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll

Show First 20 Lines • Show All 315 Lines • ▼ Show 20 Lines; RV64ZBS-NEXT: ret
%b = icmp eq <128 x i8> %a, zeroinitializer %b = icmp eq <128 x i8> %a, zeroinitializer
%c = extractelement <128 x i1> %b, i64 %idx %c = extractelement <128 x i1> %b, i64 %idx
ret i1 %c ret i1 %c
} }
define i1 @extractelt_v256i1(<256 x i8>* %x, i64 %idx) nounwind { define i1 @extractelt_v256i1(<256 x i8>* %x, i64 %idx) nounwind {
; RV32-LABEL: extractelt_v256i1: ; RV32-LABEL: extractelt_v256i1:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -512 ; RV32-NEXT: addi sp, sp, -384
; RV32-NEXT: sw ra, 508(sp) # 4-byte Folded Spill ; RV32-NEXT: sw ra, 380(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s0, 504(sp) # 4-byte Folded Spill ; RV32-NEXT: sw s0, 376(sp) # 4-byte Folded Spill
; RV32-NEXT: addi s0, sp, 512 ; RV32-NEXT: addi s0, sp, 384
; RV32-NEXT: andi sp, sp, -128 ; RV32-NEXT: andi sp, sp, -128
; RV32-NEXT: andi a1, a1, 255 ; RV32-NEXT: andi a1, a1, 255
; RV32-NEXT: li a2, 128
; RV32-NEXT: vsetvli zero, a2, e8, m8, ta, mu
; RV32-NEXT: addi a2, a0, 128 ; RV32-NEXT: addi a2, a0, 128
; RV32-NEXT: li a3, 128 ; RV32-NEXT: vle8.v v16, (a2)
; RV32-NEXT: vsetvli zero, a3, e8, m8, ta, mu ; RV32-NEXT: vle8.v v24, (a0)
; RV32-NEXT: vle8.v v16, (a0) ; RV32-NEXT: mv a0, sp
; RV32-NEXT: vle8.v v24, (a2) ; RV32-NEXT: add a1, a0, a1
; RV32-NEXT: addi a0, sp, 128
; RV32-NEXT: add a0, a0, a1
; RV32-NEXT: vmseq.vi v8, v16, 0 ; RV32-NEXT: vmseq.vi v8, v16, 0
; RV32-NEXT: vmseq.vi v0, v24, 0 ; RV32-NEXT: vmseq.vi v0, v24, 0
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: vmerge.vim v24, v16, 1, v0 ; RV32-NEXT: vmerge.vim v24, v16, 1, v0
; RV32-NEXT: addi a1, sp, 256 ; RV32-NEXT: vse8.v v24, (a0)
; RV32-NEXT: vse8.v v24, (a1)
; RV32-NEXT: vmv1r.v v0, v8 ; RV32-NEXT: vmv1r.v v0, v8
; RV32-NEXT: vmerge.vim v8, v16, 1, v0 ; RV32-NEXT: vmerge.vim v8, v16, 1, v0
; RV32-NEXT: addi a1, sp, 128 ; RV32-NEXT: addi a0, sp, 128
; RV32-NEXT: vse8.v v8, (a1) ; RV32-NEXT: vse8.v v8, (a0)
; RV32-NEXT: lb a0, 0(a0) ; RV32-NEXT: lb a0, 0(a1)
; RV32-NEXT: addi sp, s0, -512 ; RV32-NEXT: addi sp, s0, -384
; RV32-NEXT: lw ra, 508(sp) # 4-byte Folded Reload ; RV32-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 504(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s0, 376(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 512 ; RV32-NEXT: addi sp, sp, 384
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: extractelt_v256i1: ; RV64-LABEL: extractelt_v256i1:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -512 ; RV64-NEXT: addi sp, sp, -384
; RV64-NEXT: sd ra, 504(sp) # 8-byte Folded Spill ; RV64-NEXT: sd ra, 376(sp) # 8-byte Folded Spill
; RV64-NEXT: sd s0, 496(sp) # 8-byte Folded Spill ; RV64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
; RV64-NEXT: addi s0, sp, 512 ; RV64-NEXT: addi s0, sp, 384
; RV64-NEXT: andi sp, sp, -128 ; RV64-NEXT: andi sp, sp, -128
; RV64-NEXT: andi a1, a1, 255 ; RV64-NEXT: andi a1, a1, 255
; RV64-NEXT: li a2, 128
; RV64-NEXT: vsetvli zero, a2, e8, m8, ta, mu
; RV64-NEXT: addi a2, a0, 128 ; RV64-NEXT: addi a2, a0, 128
; RV64-NEXT: li a3, 128 ; RV64-NEXT: vle8.v v16, (a2)
; RV64-NEXT: vsetvli zero, a3, e8, m8, ta, mu ; RV64-NEXT: vle8.v v24, (a0)
; RV64-NEXT: vle8.v v16, (a0) ; RV64-NEXT: mv a0, sp
; RV64-NEXT: vle8.v v24, (a2) ; RV64-NEXT: add a1, a0, a1
; RV64-NEXT: addi a0, sp, 128
; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: vmseq.vi v8, v16, 0 ; RV64-NEXT: vmseq.vi v8, v16, 0
; RV64-NEXT: vmseq.vi v0, v24, 0 ; RV64-NEXT: vmseq.vi v0, v24, 0
; RV64-NEXT: vmv.v.i v16, 0 ; RV64-NEXT: vmv.v.i v16, 0
; RV64-NEXT: vmerge.vim v24, v16, 1, v0 ; RV64-NEXT: vmerge.vim v24, v16, 1, v0
; RV64-NEXT: addi a1, sp, 256 ; RV64-NEXT: vse8.v v24, (a0)
; RV64-NEXT: vse8.v v24, (a1)
; RV64-NEXT: vmv1r.v v0, v8 ; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: vmerge.vim v8, v16, 1, v0 ; RV64-NEXT: vmerge.vim v8, v16, 1, v0
; RV64-NEXT: addi a1, sp, 128 ; RV64-NEXT: addi a0, sp, 128
; RV64-NEXT: vse8.v v8, (a1) ; RV64-NEXT: vse8.v v8, (a0)
; RV64-NEXT: lb a0, 0(a0) ; RV64-NEXT: lb a0, 0(a1)
; RV64-NEXT: addi sp, s0, -512 ; RV64-NEXT: addi sp, s0, -384
; RV64-NEXT: ld ra, 504(sp) # 8-byte Folded Reload ; RV64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 496(sp) # 8-byte Folded Reload ; RV64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 512 ; RV64-NEXT: addi sp, sp, 384
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32ZBS-LABEL: extractelt_v256i1: ; RV32ZBS-LABEL: extractelt_v256i1:
; RV32ZBS: # %bb.0: ; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: addi sp, sp, -512 ; RV32ZBS-NEXT: addi sp, sp, -384
; RV32ZBS-NEXT: sw ra, 508(sp) # 4-byte Folded Spill ; RV32ZBS-NEXT: sw ra, 380(sp) # 4-byte Folded Spill
; RV32ZBS-NEXT: sw s0, 504(sp) # 4-byte Folded Spill ; RV32ZBS-NEXT: sw s0, 376(sp) # 4-byte Folded Spill
; RV32ZBS-NEXT: addi s0, sp, 512 ; RV32ZBS-NEXT: addi s0, sp, 384
; RV32ZBS-NEXT: andi sp, sp, -128 ; RV32ZBS-NEXT: andi sp, sp, -128
; RV32ZBS-NEXT: andi a1, a1, 255 ; RV32ZBS-NEXT: andi a1, a1, 255
; RV32ZBS-NEXT: li a2, 128
; RV32ZBS-NEXT: vsetvli zero, a2, e8, m8, ta, mu
; RV32ZBS-NEXT: addi a2, a0, 128 ; RV32ZBS-NEXT: addi a2, a0, 128
; RV32ZBS-NEXT: li a3, 128 ; RV32ZBS-NEXT: vle8.v v16, (a2)
; RV32ZBS-NEXT: vsetvli zero, a3, e8, m8, ta, mu ; RV32ZBS-NEXT: vle8.v v24, (a0)
; RV32ZBS-NEXT: vle8.v v16, (a0) ; RV32ZBS-NEXT: mv a0, sp
; RV32ZBS-NEXT: vle8.v v24, (a2) ; RV32ZBS-NEXT: add a1, a0, a1
; RV32ZBS-NEXT: addi a0, sp, 128
; RV32ZBS-NEXT: add a0, a0, a1
; RV32ZBS-NEXT: vmseq.vi v8, v16, 0 ; RV32ZBS-NEXT: vmseq.vi v8, v16, 0
; RV32ZBS-NEXT: vmseq.vi v0, v24, 0 ; RV32ZBS-NEXT: vmseq.vi v0, v24, 0
; RV32ZBS-NEXT: vmv.v.i v16, 0 ; RV32ZBS-NEXT: vmv.v.i v16, 0
; RV32ZBS-NEXT: vmerge.vim v24, v16, 1, v0 ; RV32ZBS-NEXT: vmerge.vim v24, v16, 1, v0
; RV32ZBS-NEXT: addi a1, sp, 256 ; RV32ZBS-NEXT: vse8.v v24, (a0)
; RV32ZBS-NEXT: vse8.v v24, (a1)
; RV32ZBS-NEXT: vmv1r.v v0, v8 ; RV32ZBS-NEXT: vmv1r.v v0, v8
; RV32ZBS-NEXT: vmerge.vim v8, v16, 1, v0 ; RV32ZBS-NEXT: vmerge.vim v8, v16, 1, v0
; RV32ZBS-NEXT: addi a1, sp, 128 ; RV32ZBS-NEXT: addi a0, sp, 128
; RV32ZBS-NEXT: vse8.v v8, (a1) ; RV32ZBS-NEXT: vse8.v v8, (a0)
; RV32ZBS-NEXT: lb a0, 0(a0) ; RV32ZBS-NEXT: lb a0, 0(a1)
; RV32ZBS-NEXT: addi sp, s0, -512 ; RV32ZBS-NEXT: addi sp, s0, -384
; RV32ZBS-NEXT: lw ra, 508(sp) # 4-byte Folded Reload ; RV32ZBS-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
; RV32ZBS-NEXT: lw s0, 504(sp) # 4-byte Folded Reload ; RV32ZBS-NEXT: lw s0, 376(sp) # 4-byte Folded Reload
; RV32ZBS-NEXT: addi sp, sp, 512 ; RV32ZBS-NEXT: addi sp, sp, 384
; RV32ZBS-NEXT: ret ; RV32ZBS-NEXT: ret
; ;
; RV64ZBS-LABEL: extractelt_v256i1: ; RV64ZBS-LABEL: extractelt_v256i1:
; RV64ZBS: # %bb.0: ; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: addi sp, sp, -512 ; RV64ZBS-NEXT: addi sp, sp, -384
; RV64ZBS-NEXT: sd ra, 504(sp) # 8-byte Folded Spill ; RV64ZBS-NEXT: sd ra, 376(sp) # 8-byte Folded Spill
; RV64ZBS-NEXT: sd s0, 496(sp) # 8-byte Folded Spill ; RV64ZBS-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
; RV64ZBS-NEXT: addi s0, sp, 512 ; RV64ZBS-NEXT: addi s0, sp, 384
; RV64ZBS-NEXT: andi sp, sp, -128 ; RV64ZBS-NEXT: andi sp, sp, -128
; RV64ZBS-NEXT: andi a1, a1, 255 ; RV64ZBS-NEXT: andi a1, a1, 255
; RV64ZBS-NEXT: li a2, 128
; RV64ZBS-NEXT: vsetvli zero, a2, e8, m8, ta, mu
; RV64ZBS-NEXT: addi a2, a0, 128 ; RV64ZBS-NEXT: addi a2, a0, 128
; RV64ZBS-NEXT: li a3, 128 ; RV64ZBS-NEXT: vle8.v v16, (a2)
; RV64ZBS-NEXT: vsetvli zero, a3, e8, m8, ta, mu ; RV64ZBS-NEXT: vle8.v v24, (a0)
; RV64ZBS-NEXT: vle8.v v16, (a0) ; RV64ZBS-NEXT: mv a0, sp
; RV64ZBS-NEXT: vle8.v v24, (a2) ; RV64ZBS-NEXT: add a1, a0, a1
; RV64ZBS-NEXT: addi a0, sp, 128
; RV64ZBS-NEXT: add a0, a0, a1
; RV64ZBS-NEXT: vmseq.vi v8, v16, 0 ; RV64ZBS-NEXT: vmseq.vi v8, v16, 0
; RV64ZBS-NEXT: vmseq.vi v0, v24, 0 ; RV64ZBS-NEXT: vmseq.vi v0, v24, 0
; RV64ZBS-NEXT: vmv.v.i v16, 0 ; RV64ZBS-NEXT: vmv.v.i v16, 0
; RV64ZBS-NEXT: vmerge.vim v24, v16, 1, v0 ; RV64ZBS-NEXT: vmerge.vim v24, v16, 1, v0
; RV64ZBS-NEXT: addi a1, sp, 256 ; RV64ZBS-NEXT: vse8.v v24, (a0)
; RV64ZBS-NEXT: vse8.v v24, (a1)
; RV64ZBS-NEXT: vmv1r.v v0, v8 ; RV64ZBS-NEXT: vmv1r.v v0, v8
; RV64ZBS-NEXT: vmerge.vim v8, v16, 1, v0 ; RV64ZBS-NEXT: vmerge.vim v8, v16, 1, v0
; RV64ZBS-NEXT: addi a1, sp, 128 ; RV64ZBS-NEXT: addi a0, sp, 128
; RV64ZBS-NEXT: vse8.v v8, (a1) ; RV64ZBS-NEXT: vse8.v v8, (a0)
; RV64ZBS-NEXT: lb a0, 0(a0) ; RV64ZBS-NEXT: lb a0, 0(a1)
; RV64ZBS-NEXT: addi sp, s0, -512 ; RV64ZBS-NEXT: addi sp, s0, -384
; RV64ZBS-NEXT: ld ra, 504(sp) # 8-byte Folded Reload ; RV64ZBS-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
; RV64ZBS-NEXT: ld s0, 496(sp) # 8-byte Folded Reload ; RV64ZBS-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; RV64ZBS-NEXT: addi sp, sp, 512 ; RV64ZBS-NEXT: addi sp, sp, 384
; RV64ZBS-NEXT: ret ; RV64ZBS-NEXT: ret
%a = load <256 x i8>, <256 x i8>* %x %a = load <256 x i8>, <256 x i8>* %x
%b = icmp eq <256 x i8> %a, zeroinitializer %b = icmp eq <256 x i8> %a, zeroinitializer
%c = extractelement <256 x i1> %b, i64 %idx %c = extractelement <256 x i1> %b, i64 %idx
ret i1 %c ret i1 %c
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; LMULMAX1-NEXT: vmv.s.x v8, a0 ; LMULMAX1-NEXT: vmv.s.x v8, a0
; LMULMAX1-NEXT: vrgather.vi v9, v11, 3, v0.t ; LMULMAX1-NEXT: vrgather.vi v9, v11, 3, v0.t
; LMULMAX1-NEXT: vmv.v.v v0, v8 ; LMULMAX1-NEXT: vmv.v.v v0, v8
; LMULMAX1-NEXT: vmerge.vvm v8, v9, v12, v0 ; LMULMAX1-NEXT: vmerge.vvm v8, v9, v12, v0
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX2-LABEL: hang_when_merging_stores_after_legalization: ; LMULMAX2-LABEL: hang_when_merging_stores_after_legalization:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi sp, sp, -32 ; LMULMAX2-NEXT: addi sp, sp, -16
; LMULMAX2-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX2-NEXT: .cfi_def_cfa_offset 16
; LMULMAX2-NEXT: addi a0, sp, 24 ; LMULMAX2-NEXT: addi a0, sp, 8
; LMULMAX2-NEXT: vsetivli zero, 1, e32, m2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 1, e32, m2, ta, mu
; LMULMAX2-NEXT: vse32.v v10, (a0) ; LMULMAX2-NEXT: vse32.v v10, (a0)
; LMULMAX2-NEXT: vslidedown.vi v10, v10, 7 ; LMULMAX2-NEXT: mv a0, sp
; LMULMAX2-NEXT: addi a0, sp, 28
; LMULMAX2-NEXT: vse32.v v10, (a0)
; LMULMAX2-NEXT: vslidedown.vi v10, v8, 7
; LMULMAX2-NEXT: addi a0, sp, 20
; LMULMAX2-NEXT: vse32.v v10, (a0)
; LMULMAX2-NEXT: addi a0, sp, 16
; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: vslidedown.vi v10, v10, 7
; LMULMAX2-NEXT: addi a1, sp, 12
; LMULMAX2-NEXT: vse32.v v10, (a1)
; LMULMAX2-NEXT: vslidedown.vi v8, v8, 7
; LMULMAX2-NEXT: addi a1, sp, 4
; LMULMAX2-NEXT: vse32.v v8, (a1)
; LMULMAX2-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX2-NEXT: addi a0, sp, 16
; LMULMAX2-NEXT: vle32.v v8, (a0) ; LMULMAX2-NEXT: vle32.v v8, (a0)
; LMULMAX2-NEXT: addi sp, sp, 32 ; LMULMAX2-NEXT: addi sp, sp, 16
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
%z = shufflevector <8 x float> %x, <8 x float> %y, <4 x i32> <i32 0, i32 7, i32 8, i32 15> %z = shufflevector <8 x float> %x, <8 x float> %y, <4 x i32> <i32 0, i32 7, i32 8, i32 15>
ret <4 x float> %z ret <4 x float> %z
} }
define void @buildvec_dominant0_v2f32(<2 x float>* %x) { define void @buildvec_dominant0_v2f32(<2 x float>* %x) {
; CHECK-LABEL: buildvec_dominant0_v2f32: ; CHECK-LABEL: buildvec_dominant0_v2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Lines; LMULMAX2-NEXT: ret
%ins = insertelement <8 x float> poison, float %x, i32 0 %ins = insertelement <8 x float> poison, float %x, i32 0
%splat = shufflevector <8 x float> %ins, <8 x float> poison, <8 x i32> zeroinitializer %splat = shufflevector <8 x float> %ins, <8 x float> poison, <8 x i32> zeroinitializer
ret <8 x float> %splat ret <8 x float> %splat
} }
define <8 x float> @splat_idx_v8f32(<8 x float> %v, i64 %idx) { define <8 x float> @splat_idx_v8f32(<8 x float> %v, i64 %idx) {
; LMULMAX1-LABEL: splat_idx_v8f32: ; LMULMAX1-LABEL: splat_idx_v8f32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi sp, sp, -48 ; LMULMAX1-NEXT: addi sp, sp, -32
; LMULMAX1-NEXT: .cfi_def_cfa_offset 48 ; LMULMAX1-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-NEXT: andi a0, a0, 7 ; LMULMAX1-NEXT: andi a0, a0, 7
; LMULMAX1-NEXT: slli a0, a0, 2 ; LMULMAX1-NEXT: slli a0, a0, 2
; LMULMAX1-NEXT: addi a1, sp, 16 ; LMULMAX1-NEXT: mv a1, sp
; LMULMAX1-NEXT: add a0, a1, a0 ; LMULMAX1-NEXT: add a0, a1, a0
; LMULMAX1-NEXT: addi a1, sp, 32 ; LMULMAX1-NEXT: addi a2, sp, 16
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vse32.v v9, (a1) ; LMULMAX1-NEXT: vse32.v v9, (a2)
; LMULMAX1-NEXT: addi a1, sp, 16
; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: vse32.v v8, (a1)
; LMULMAX1-NEXT: vlse32.v v8, (a0), zero ; LMULMAX1-NEXT: vlse32.v v8, (a0), zero
; LMULMAX1-NEXT: vmv.v.v v9, v8 ; LMULMAX1-NEXT: vmv.v.v v9, v8
; LMULMAX1-NEXT: addi sp, sp, 48 ; LMULMAX1-NEXT: addi sp, sp, 32
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX2-LABEL: splat_idx_v8f32: ; LMULMAX2-LABEL: splat_idx_v8f32:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-NEXT: vrgather.vx v10, v8, a0 ; LMULMAX2-NEXT: vrgather.vx v10, v8, a0
; LMULMAX2-NEXT: vmv.v.v v8, v10 ; LMULMAX2-NEXT: vmv.v.v v8, v10
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
▲ Show 20 Lines • Show All 53 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll

Show First 20 Lines • Show All 568 Lines • ▼ Show 20 Lines
; CHECK-NEXT: andi sp, sp, -64 ; CHECK-NEXT: andi sp, sp, -64
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 128 ; CHECK-NEXT: addi a0, sp, 128
; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: addi a2, sp, 64 ; CHECK-NEXT: addi a2, sp, 64
; CHECK-NEXT: add a2, a2, a0 ; CHECK-NEXT: add a3, a2, a0
; CHECK-NEXT: vl8re64.v v8, (a2) ; CHECK-NEXT: vl8re64.v v8, (a3)
; CHECK-NEXT: addi a2, sp, 64
; CHECK-NEXT: vl8re64.v v16, (a2) ; CHECK-NEXT: vl8re64.v v16, (a2)
; CHECK-NEXT: add a0, a1, a0 ; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: vs8r.v v8, (a0) ; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vs8r.v v16, (a1) ; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: addi sp, s0, -64 ; CHECK-NEXT: addi sp, s0, -64
; CHECK-NEXT: addi sp, sp, 64 ; CHECK-NEXT: addi sp, sp, 64
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i64>, <2 x i64>* %psv %sv = load <2 x i64>, <2 x i64>* %psv
Show All 21 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
define void @splat_v2i64(<2 x i64>* %x, i64 %y) { define void @splat_v2i64(<2 x i64>* %x, i64 %y) {
; LMULMAX8-RV32-LABEL: splat_v2i64: ; LMULMAX8-RV32-LABEL: splat_v2i64:
; LMULMAX8-RV32: # %bb.0: ; LMULMAX8-RV32: # %bb.0:
; LMULMAX8-RV32-NEXT: addi sp, sp, -16 ; LMULMAX8-RV32-NEXT: addi sp, sp, -16
; LMULMAX8-RV32-NEXT: .cfi_def_cfa_offset 16 ; LMULMAX8-RV32-NEXT: .cfi_def_cfa_offset 16
; LMULMAX8-RV32-NEXT: sw a2, 12(sp) ; LMULMAX8-RV32-NEXT: sw a2, 12(sp)
; LMULMAX8-RV32-NEXT: sw a1, 8(sp) ; LMULMAX8-RV32-NEXT: sw a1, 8(sp)
; LMULMAX8-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX8-RV32-NEXT: addi a1, sp, 8 ; LMULMAX8-RV32-NEXT: addi a1, sp, 8
; LMULMAX8-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX8-RV32-NEXT: vlse64.v v8, (a1), zero ; LMULMAX8-RV32-NEXT: vlse64.v v8, (a1), zero
; LMULMAX8-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX8-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX8-RV32-NEXT: addi sp, sp, 16 ; LMULMAX8-RV32-NEXT: addi sp, sp, 16
; LMULMAX8-RV32-NEXT: ret ; LMULMAX8-RV32-NEXT: ret
; ;
; LMULMAX2-RV32-LABEL: splat_v2i64: ; LMULMAX2-RV32-LABEL: splat_v2i64:
; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: addi sp, sp, -16 ; LMULMAX2-RV32-NEXT: addi sp, sp, -16
; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 16 ; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 16
; LMULMAX2-RV32-NEXT: sw a2, 12(sp) ; LMULMAX2-RV32-NEXT: sw a2, 12(sp)
; LMULMAX2-RV32-NEXT: sw a1, 8(sp) ; LMULMAX2-RV32-NEXT: sw a1, 8(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 8 ; LMULMAX2-RV32-NEXT: addi a1, sp, 8
; LMULMAX2-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX2-RV32-NEXT: vlse64.v v8, (a1), zero ; LMULMAX2-RV32-NEXT: vlse64.v v8, (a1), zero
; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, sp, 16 ; LMULMAX2-RV32-NEXT: addi sp, sp, 16
; LMULMAX2-RV32-NEXT: ret ; LMULMAX2-RV32-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: splat_v2i64: ; LMULMAX1-RV32-LABEL: splat_v2i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi sp, sp, -16 ; LMULMAX1-RV32-NEXT: addi sp, sp, -16
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 16 ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 16
; LMULMAX1-RV32-NEXT: sw a2, 12(sp) ; LMULMAX1-RV32-NEXT: sw a2, 12(sp)
; LMULMAX1-RV32-NEXT: sw a1, 8(sp) ; LMULMAX1-RV32-NEXT: sw a1, 8(sp)
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, sp, 8 ; LMULMAX1-RV32-NEXT: addi a1, sp, 8
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vlse64.v v8, (a1), zero ; LMULMAX1-RV32-NEXT: vlse64.v v8, (a1), zero
; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi sp, sp, 16 ; LMULMAX1-RV32-NEXT: addi sp, sp, 16
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX8-RV64-LABEL: splat_v2i64: ; LMULMAX8-RV64-LABEL: splat_v2i64:
; LMULMAX8-RV64: # %bb.0: ; LMULMAX8-RV64: # %bb.0:
; LMULMAX8-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX8-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
define void @splat_v4i64(<4 x i64>* %x, i64 %y) { define void @splat_v4i64(<4 x i64>* %x, i64 %y) {
; LMULMAX8-RV32-LABEL: splat_v4i64: ; LMULMAX8-RV32-LABEL: splat_v4i64:
; LMULMAX8-RV32: # %bb.0: ; LMULMAX8-RV32: # %bb.0:
; LMULMAX8-RV32-NEXT: addi sp, sp, -16 ; LMULMAX8-RV32-NEXT: addi sp, sp, -16
; LMULMAX8-RV32-NEXT: .cfi_def_cfa_offset 16 ; LMULMAX8-RV32-NEXT: .cfi_def_cfa_offset 16
; LMULMAX8-RV32-NEXT: sw a2, 12(sp) ; LMULMAX8-RV32-NEXT: sw a2, 12(sp)
; LMULMAX8-RV32-NEXT: sw a1, 8(sp) ; LMULMAX8-RV32-NEXT: sw a1, 8(sp)
; LMULMAX8-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; LMULMAX8-RV32-NEXT: addi a1, sp, 8 ; LMULMAX8-RV32-NEXT: addi a1, sp, 8
; LMULMAX8-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; LMULMAX8-RV32-NEXT: vlse64.v v8, (a1), zero ; LMULMAX8-RV32-NEXT: vlse64.v v8, (a1), zero
; LMULMAX8-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX8-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX8-RV32-NEXT: addi sp, sp, 16 ; LMULMAX8-RV32-NEXT: addi sp, sp, 16
; LMULMAX8-RV32-NEXT: ret ; LMULMAX8-RV32-NEXT: ret
; ;
; LMULMAX2-RV32-LABEL: splat_v4i64: ; LMULMAX2-RV32-LABEL: splat_v4i64:
; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: addi sp, sp, -16 ; LMULMAX2-RV32-NEXT: addi sp, sp, -16
; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 16 ; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 16
; LMULMAX2-RV32-NEXT: sw a2, 12(sp) ; LMULMAX2-RV32-NEXT: sw a2, 12(sp)
; LMULMAX2-RV32-NEXT: sw a1, 8(sp) ; LMULMAX2-RV32-NEXT: sw a1, 8(sp)
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; LMULMAX2-RV32-NEXT: addi a1, sp, 8 ; LMULMAX2-RV32-NEXT: addi a1, sp, 8
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; LMULMAX2-RV32-NEXT: vlse64.v v8, (a1), zero ; LMULMAX2-RV32-NEXT: vlse64.v v8, (a1), zero
; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: addi sp, sp, 16 ; LMULMAX2-RV32-NEXT: addi sp, sp, 16
; LMULMAX2-RV32-NEXT: ret ; LMULMAX2-RV32-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: splat_v4i64: ; LMULMAX1-RV32-LABEL: splat_v4i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: li a3, 5 ; LMULMAX1-RV32-NEXT: li a3, 5
▲ Show 20 Lines • Show All 627 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; FIXME: optsize isn't smaller than the code above ; FIXME: optsize isn't smaller than the code above
define <2 x i1> @buildvec_mask_optsize_nonconst_v2i1(i1 %x, i1 %y) optsize { define <2 x i1> @buildvec_mask_optsize_nonconst_v2i1(i1 %x, i1 %y) optsize {
; CHECK-LABEL: buildvec_mask_optsize_nonconst_v2i1: ; CHECK-LABEL: buildvec_mask_optsize_nonconst_v2i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: sb a1, 15(sp) ; CHECK-NEXT: sb a1, 15(sp)
; CHECK-NEXT: sb a0, 14(sp) ; CHECK-NEXT: sb a0, 14(sp)
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: addi a0, sp, 14 ; CHECK-NEXT: addi a0, sp, 14
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; ZVE32F-LABEL: buildvec_mask_optsize_nonconst_v2i1: ; ZVE32F-LABEL: buildvec_mask_optsize_nonconst_v2i1:
; ZVE32F: # %bb.0: ; ZVE32F: # %bb.0:
; ZVE32F-NEXT: addi sp, sp, -16 ; ZVE32F-NEXT: addi sp, sp, -16
; ZVE32F-NEXT: .cfi_def_cfa_offset 16 ; ZVE32F-NEXT: .cfi_def_cfa_offset 16
; ZVE32F-NEXT: sb a1, 15(sp) ; ZVE32F-NEXT: sb a1, 15(sp)
; ZVE32F-NEXT: sb a0, 14(sp) ; ZVE32F-NEXT: sb a0, 14(sp)
; ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; ZVE32F-NEXT: addi a0, sp, 14 ; ZVE32F-NEXT: addi a0, sp, 14
; ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; ZVE32F-NEXT: vle8.v v8, (a0) ; ZVE32F-NEXT: vle8.v v8, (a0)
; ZVE32F-NEXT: vand.vi v8, v8, 1 ; ZVE32F-NEXT: vand.vi v8, v8, 1
; ZVE32F-NEXT: vmsne.vi v0, v8, 0 ; ZVE32F-NEXT: vmsne.vi v0, v8, 0
; ZVE32F-NEXT: addi sp, sp, 16 ; ZVE32F-NEXT: addi sp, sp, 16
; ZVE32F-NEXT: ret ; ZVE32F-NEXT: ret
%1 = insertelement <2 x i1> poison, i1 %x, i32 0 %1 = insertelement <2 x i1> poison, i1 %x, i32 0
%2 = insertelement <2 x i1> %1, i1 %y, i32 1 %2 = insertelement <2 x i1> %1, i1 %y, i32 1
ret <2 x i1> %2 ret <2 x i1> %2
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
; CHECK-LABEL: buildvec_mask_optsize_nonconst_v4i1: ; CHECK-LABEL: buildvec_mask_optsize_nonconst_v4i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: sb a1, 15(sp) ; CHECK-NEXT: sb a1, 15(sp)
; CHECK-NEXT: sb a1, 14(sp) ; CHECK-NEXT: sb a1, 14(sp)
; CHECK-NEXT: sb a0, 13(sp) ; CHECK-NEXT: sb a0, 13(sp)
; CHECK-NEXT: sb a0, 12(sp) ; CHECK-NEXT: sb a0, 12(sp)
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: addi a0, sp, 12 ; CHECK-NEXT: addi a0, sp, 12
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; ZVE32F-LABEL: buildvec_mask_optsize_nonconst_v4i1: ; ZVE32F-LABEL: buildvec_mask_optsize_nonconst_v4i1:
; ZVE32F: # %bb.0: ; ZVE32F: # %bb.0:
; ZVE32F-NEXT: addi sp, sp, -16 ; ZVE32F-NEXT: addi sp, sp, -16
; ZVE32F-NEXT: .cfi_def_cfa_offset 16 ; ZVE32F-NEXT: .cfi_def_cfa_offset 16
; ZVE32F-NEXT: sb a1, 15(sp) ; ZVE32F-NEXT: sb a1, 15(sp)
; ZVE32F-NEXT: sb a1, 14(sp) ; ZVE32F-NEXT: sb a1, 14(sp)
; ZVE32F-NEXT: sb a0, 13(sp) ; ZVE32F-NEXT: sb a0, 13(sp)
; ZVE32F-NEXT: sb a0, 12(sp) ; ZVE32F-NEXT: sb a0, 12(sp)
; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; ZVE32F-NEXT: addi a0, sp, 12 ; ZVE32F-NEXT: addi a0, sp, 12
; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; ZVE32F-NEXT: vle8.v v8, (a0) ; ZVE32F-NEXT: vle8.v v8, (a0)
; ZVE32F-NEXT: vand.vi v8, v8, 1 ; ZVE32F-NEXT: vand.vi v8, v8, 1
; ZVE32F-NEXT: vmsne.vi v0, v8, 0 ; ZVE32F-NEXT: vmsne.vi v0, v8, 0
; ZVE32F-NEXT: addi sp, sp, 16 ; ZVE32F-NEXT: addi sp, sp, 16
; ZVE32F-NEXT: ret ; ZVE32F-NEXT: ret
%1 = insertelement <4 x i1> poison, i1 %x, i32 0 %1 = insertelement <4 x i1> poison, i1 %x, i32 0
%2 = insertelement <4 x i1> %1, i1 %x, i32 1 %2 = insertelement <4 x i1> %1, i1 %x, i32 1
%3 = insertelement <4 x i1> %2, i1 %y, i32 2 %3 = insertelement <4 x i1> %2, i1 %y, i32 2
%4 = insertelement <4 x i1> %3, i1 %y, i32 3 %4 = insertelement <4 x i1> %3, i1 %y, i32 3
ret <4 x i1> %4 ret <4 x i1> %4
} }
define <4 x i1> @buildvec_mask_nonconst_v4i1_2(i1 %x, i1 %y) { define <4 x i1> @buildvec_mask_nonconst_v4i1_2(i1 %x, i1 %y) {
; CHECK-LABEL: buildvec_mask_nonconst_v4i1_2: ; CHECK-LABEL: buildvec_mask_nonconst_v4i1_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: sb a1, 15(sp) ; CHECK-NEXT: sb a1, 15(sp)
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: sb a1, 14(sp) ; CHECK-NEXT: sb a1, 14(sp)
; CHECK-NEXT: sb a0, 13(sp) ; CHECK-NEXT: sb a0, 13(sp)
; CHECK-NEXT: sb zero, 12(sp) ; CHECK-NEXT: sb zero, 12(sp)
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: addi a0, sp, 12 ; CHECK-NEXT: addi a0, sp, 12
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; ZVE32F-LABEL: buildvec_mask_nonconst_v4i1_2: ; ZVE32F-LABEL: buildvec_mask_nonconst_v4i1_2:
; ZVE32F: # %bb.0: ; ZVE32F: # %bb.0:
; ZVE32F-NEXT: addi sp, sp, -16 ; ZVE32F-NEXT: addi sp, sp, -16
; ZVE32F-NEXT: .cfi_def_cfa_offset 16 ; ZVE32F-NEXT: .cfi_def_cfa_offset 16
; ZVE32F-NEXT: sb a1, 15(sp) ; ZVE32F-NEXT: sb a1, 15(sp)
; ZVE32F-NEXT: li a1, 1 ; ZVE32F-NEXT: li a1, 1
; ZVE32F-NEXT: sb a1, 14(sp) ; ZVE32F-NEXT: sb a1, 14(sp)
; ZVE32F-NEXT: sb a0, 13(sp) ; ZVE32F-NEXT: sb a0, 13(sp)
; ZVE32F-NEXT: sb zero, 12(sp) ; ZVE32F-NEXT: sb zero, 12(sp)
; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; ZVE32F-NEXT: addi a0, sp, 12 ; ZVE32F-NEXT: addi a0, sp, 12
; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; ZVE32F-NEXT: vle8.v v8, (a0) ; ZVE32F-NEXT: vle8.v v8, (a0)
; ZVE32F-NEXT: vand.vi v8, v8, 1 ; ZVE32F-NEXT: vand.vi v8, v8, 1
; ZVE32F-NEXT: vmsne.vi v0, v8, 0 ; ZVE32F-NEXT: vmsne.vi v0, v8, 0
; ZVE32F-NEXT: addi sp, sp, 16 ; ZVE32F-NEXT: addi sp, sp, 16
; ZVE32F-NEXT: ret ; ZVE32F-NEXT: ret
%1 = insertelement <4 x i1> poison, i1 0, i32 0 %1 = insertelement <4 x i1> poison, i1 0, i32 0
%2 = insertelement <4 x i1> %1, i1 %x, i32 1 %2 = insertelement <4 x i1> %1, i1 %x, i32 1
%3 = insertelement <4 x i1> %2, i1 1, i32 2 %3 = insertelement <4 x i1> %2, i1 1, i32 2
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; CHECK-NEXT: sb zero, 14(sp) ; CHECK-NEXT: sb zero, 14(sp)
; CHECK-NEXT: sb a3, 13(sp) ; CHECK-NEXT: sb a3, 13(sp)
; CHECK-NEXT: sb a0, 12(sp) ; CHECK-NEXT: sb a0, 12(sp)
; CHECK-NEXT: sb a1, 11(sp) ; CHECK-NEXT: sb a1, 11(sp)
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: sb a1, 10(sp) ; CHECK-NEXT: sb a1, 10(sp)
; CHECK-NEXT: sb a0, 9(sp) ; CHECK-NEXT: sb a0, 9(sp)
; CHECK-NEXT: sb a0, 8(sp) ; CHECK-NEXT: sb a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; ZVE32F-LABEL: buildvec_mask_nonconst_v8i1_2: ; ZVE32F-LABEL: buildvec_mask_nonconst_v8i1_2:
; ZVE32F: # %bb.0: ; ZVE32F: # %bb.0:
; ZVE32F-NEXT: addi sp, sp, -16 ; ZVE32F-NEXT: addi sp, sp, -16
; ZVE32F-NEXT: .cfi_def_cfa_offset 16 ; ZVE32F-NEXT: .cfi_def_cfa_offset 16
; ZVE32F-NEXT: sb a2, 15(sp) ; ZVE32F-NEXT: sb a2, 15(sp)
; ZVE32F-NEXT: sb zero, 14(sp) ; ZVE32F-NEXT: sb zero, 14(sp)
; ZVE32F-NEXT: sb a3, 13(sp) ; ZVE32F-NEXT: sb a3, 13(sp)
; ZVE32F-NEXT: sb a0, 12(sp) ; ZVE32F-NEXT: sb a0, 12(sp)
; ZVE32F-NEXT: sb a1, 11(sp) ; ZVE32F-NEXT: sb a1, 11(sp)
; ZVE32F-NEXT: li a1, 1 ; ZVE32F-NEXT: li a1, 1
; ZVE32F-NEXT: sb a1, 10(sp) ; ZVE32F-NEXT: sb a1, 10(sp)
; ZVE32F-NEXT: sb a0, 9(sp) ; ZVE32F-NEXT: sb a0, 9(sp)
; ZVE32F-NEXT: sb a0, 8(sp) ; ZVE32F-NEXT: sb a0, 8(sp)
; ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; ZVE32F-NEXT: addi a0, sp, 8 ; ZVE32F-NEXT: addi a0, sp, 8
; ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; ZVE32F-NEXT: vle8.v v8, (a0) ; ZVE32F-NEXT: vle8.v v8, (a0)
; ZVE32F-NEXT: vand.vi v8, v8, 1 ; ZVE32F-NEXT: vand.vi v8, v8, 1
; ZVE32F-NEXT: vmsne.vi v0, v8, 0 ; ZVE32F-NEXT: vmsne.vi v0, v8, 0
; ZVE32F-NEXT: addi sp, sp, 16 ; ZVE32F-NEXT: addi sp, sp, 16
; ZVE32F-NEXT: ret ; ZVE32F-NEXT: ret
%1 = insertelement <8 x i1> poison, i1 %x, i32 0 %1 = insertelement <8 x i1> poison, i1 %x, i32 0
%2 = insertelement <8 x i1> %1, i1 %x, i32 1 %2 = insertelement <8 x i1> %1, i1 %x, i32 1
%3 = insertelement <8 x i1> %2, i1 1, i32 2 %3 = insertelement <8 x i1> %2, i1 1, i32 2
Show All 14 Lines
; CHECK-NEXT: sb zero, 14(sp) ; CHECK-NEXT: sb zero, 14(sp)
; CHECK-NEXT: sb a3, 13(sp) ; CHECK-NEXT: sb a3, 13(sp)
; CHECK-NEXT: sb a0, 12(sp) ; CHECK-NEXT: sb a0, 12(sp)
; CHECK-NEXT: sb a1, 11(sp) ; CHECK-NEXT: sb a1, 11(sp)
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: sb a1, 10(sp) ; CHECK-NEXT: sb a1, 10(sp)
; CHECK-NEXT: sb a0, 9(sp) ; CHECK-NEXT: sb a0, 9(sp)
; CHECK-NEXT: sb a0, 8(sp) ; CHECK-NEXT: sb a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; ZVE32F-LABEL: buildvec_mask_optsize_nonconst_v8i1_2: ; ZVE32F-LABEL: buildvec_mask_optsize_nonconst_v8i1_2:
; ZVE32F: # %bb.0: ; ZVE32F: # %bb.0:
; ZVE32F-NEXT: addi sp, sp, -16 ; ZVE32F-NEXT: addi sp, sp, -16
; ZVE32F-NEXT: .cfi_def_cfa_offset 16 ; ZVE32F-NEXT: .cfi_def_cfa_offset 16
; ZVE32F-NEXT: sb a2, 15(sp) ; ZVE32F-NEXT: sb a2, 15(sp)
; ZVE32F-NEXT: sb zero, 14(sp) ; ZVE32F-NEXT: sb zero, 14(sp)
; ZVE32F-NEXT: sb a3, 13(sp) ; ZVE32F-NEXT: sb a3, 13(sp)
; ZVE32F-NEXT: sb a0, 12(sp) ; ZVE32F-NEXT: sb a0, 12(sp)
; ZVE32F-NEXT: sb a1, 11(sp) ; ZVE32F-NEXT: sb a1, 11(sp)
; ZVE32F-NEXT: li a1, 1 ; ZVE32F-NEXT: li a1, 1
; ZVE32F-NEXT: sb a1, 10(sp) ; ZVE32F-NEXT: sb a1, 10(sp)
; ZVE32F-NEXT: sb a0, 9(sp) ; ZVE32F-NEXT: sb a0, 9(sp)
; ZVE32F-NEXT: sb a0, 8(sp) ; ZVE32F-NEXT: sb a0, 8(sp)
; ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; ZVE32F-NEXT: addi a0, sp, 8 ; ZVE32F-NEXT: addi a0, sp, 8
; ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; ZVE32F-NEXT: vle8.v v8, (a0) ; ZVE32F-NEXT: vle8.v v8, (a0)
; ZVE32F-NEXT: vand.vi v8, v8, 1 ; ZVE32F-NEXT: vand.vi v8, v8, 1
; ZVE32F-NEXT: vmsne.vi v0, v8, 0 ; ZVE32F-NEXT: vmsne.vi v0, v8, 0
; ZVE32F-NEXT: addi sp, sp, 16 ; ZVE32F-NEXT: addi sp, sp, 16
; ZVE32F-NEXT: ret ; ZVE32F-NEXT: ret
%1 = insertelement <8 x i1> poison, i1 %x, i32 0 %1 = insertelement <8 x i1> poison, i1 %x, i32 0
%2 = insertelement <8 x i1> %1, i1 %x, i32 1 %2 = insertelement <8 x i1> %1, i1 %x, i32 1
%3 = insertelement <8 x i1> %2, i1 1, i32 2 %3 = insertelement <8 x i1> %2, i1 1, i32 2
Show All 13 Lines
; CHECK-NEXT: sb a1, 15(sp) ; CHECK-NEXT: sb a1, 15(sp)
; CHECK-NEXT: sb a1, 14(sp) ; CHECK-NEXT: sb a1, 14(sp)
; CHECK-NEXT: sb a1, 13(sp) ; CHECK-NEXT: sb a1, 13(sp)
; CHECK-NEXT: sb a0, 12(sp) ; CHECK-NEXT: sb a0, 12(sp)
; CHECK-NEXT: sb a1, 11(sp) ; CHECK-NEXT: sb a1, 11(sp)
; CHECK-NEXT: sb a1, 10(sp) ; CHECK-NEXT: sb a1, 10(sp)
; CHECK-NEXT: sb a0, 9(sp) ; CHECK-NEXT: sb a0, 9(sp)
; CHECK-NEXT: sb a0, 8(sp) ; CHECK-NEXT: sb a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; ZVE32F-LABEL: buildvec_mask_optsize_nonconst_v8i1: ; ZVE32F-LABEL: buildvec_mask_optsize_nonconst_v8i1:
; ZVE32F: # %bb.0: ; ZVE32F: # %bb.0:
; ZVE32F-NEXT: addi sp, sp, -16 ; ZVE32F-NEXT: addi sp, sp, -16
; ZVE32F-NEXT: .cfi_def_cfa_offset 16 ; ZVE32F-NEXT: .cfi_def_cfa_offset 16
; ZVE32F-NEXT: sb a1, 15(sp) ; ZVE32F-NEXT: sb a1, 15(sp)
; ZVE32F-NEXT: sb a1, 14(sp) ; ZVE32F-NEXT: sb a1, 14(sp)
; ZVE32F-NEXT: sb a1, 13(sp) ; ZVE32F-NEXT: sb a1, 13(sp)
; ZVE32F-NEXT: sb a0, 12(sp) ; ZVE32F-NEXT: sb a0, 12(sp)
; ZVE32F-NEXT: sb a1, 11(sp) ; ZVE32F-NEXT: sb a1, 11(sp)
; ZVE32F-NEXT: sb a1, 10(sp) ; ZVE32F-NEXT: sb a1, 10(sp)
; ZVE32F-NEXT: sb a0, 9(sp) ; ZVE32F-NEXT: sb a0, 9(sp)
; ZVE32F-NEXT: sb a0, 8(sp) ; ZVE32F-NEXT: sb a0, 8(sp)
; ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; ZVE32F-NEXT: addi a0, sp, 8 ; ZVE32F-NEXT: addi a0, sp, 8
; ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; ZVE32F-NEXT: vle8.v v8, (a0) ; ZVE32F-NEXT: vle8.v v8, (a0)
; ZVE32F-NEXT: vand.vi v8, v8, 1 ; ZVE32F-NEXT: vand.vi v8, v8, 1
; ZVE32F-NEXT: vmsne.vi v0, v8, 0 ; ZVE32F-NEXT: vmsne.vi v0, v8, 0
; ZVE32F-NEXT: addi sp, sp, 16 ; ZVE32F-NEXT: addi sp, sp, 16
; ZVE32F-NEXT: ret ; ZVE32F-NEXT: ret
%1 = insertelement <8 x i1> poison, i1 %x, i32 0 %1 = insertelement <8 x i1> poison, i1 %x, i32 0
%2 = insertelement <8 x i1> %1, i1 %x, i32 1 %2 = insertelement <8 x i1> %1, i1 %x, i32 1
%3 = insertelement <8 x i1> %2, i1 %y, i32 2 %3 = insertelement <8 x i1> %2, i1 %y, i32 2
▲ Show 20 Lines • Show All 505 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,240 Lines • ▼ Show 20 Lines
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64V-NEXT: vsll.vi v8, v8, 3 ; RV64V-NEXT: vsll.vi v8, v8, 3
; RV64V-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64V-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64V-NEXT: vmv.v.v v8, v12 ; RV64V-NEXT: vmv.v.v v8, v12
; RV64V-NEXT: ret ; RV64V-NEXT: ret
; ;
; RV32ZVE32F-LABEL: mgather_baseidx_v8i64: ; RV32ZVE32F-LABEL: mgather_baseidx_v8i64:
; RV32ZVE32F: # %bb.0: ; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: addi sp, sp, -128 ; RV32ZVE32F-NEXT: addi sp, sp, -96
; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 128 ; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 96
; RV32ZVE32F-NEXT: sw ra, 124(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw ra, 92(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s0, 120(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s0, 88(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s2, 116(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s2, 84(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s3, 112(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s3, 80(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s4, 108(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s4, 76(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s5, 104(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s5, 72(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s6, 100(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s6, 68(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s7, 96(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s7, 64(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s8, 92(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s8, 60(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s9, 88(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s9, 56(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s10, 84(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s10, 52(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s11, 80(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s11, 48(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: .cfi_offset ra, -4 ; RV32ZVE32F-NEXT: .cfi_offset ra, -4
; RV32ZVE32F-NEXT: .cfi_offset s0, -8 ; RV32ZVE32F-NEXT: .cfi_offset s0, -8
; RV32ZVE32F-NEXT: .cfi_offset s2, -12 ; RV32ZVE32F-NEXT: .cfi_offset s2, -12
; RV32ZVE32F-NEXT: .cfi_offset s3, -16 ; RV32ZVE32F-NEXT: .cfi_offset s3, -16
; RV32ZVE32F-NEXT: .cfi_offset s4, -20 ; RV32ZVE32F-NEXT: .cfi_offset s4, -20
; RV32ZVE32F-NEXT: .cfi_offset s5, -24 ; RV32ZVE32F-NEXT: .cfi_offset s5, -24
; RV32ZVE32F-NEXT: .cfi_offset s6, -28 ; RV32ZVE32F-NEXT: .cfi_offset s6, -28
; RV32ZVE32F-NEXT: .cfi_offset s7, -32 ; RV32ZVE32F-NEXT: .cfi_offset s7, -32
; RV32ZVE32F-NEXT: .cfi_offset s8, -36 ; RV32ZVE32F-NEXT: .cfi_offset s8, -36
; RV32ZVE32F-NEXT: .cfi_offset s9, -40 ; RV32ZVE32F-NEXT: .cfi_offset s9, -40
; RV32ZVE32F-NEXT: .cfi_offset s10, -44 ; RV32ZVE32F-NEXT: .cfi_offset s10, -44
; RV32ZVE32F-NEXT: .cfi_offset s11, -48 ; RV32ZVE32F-NEXT: .cfi_offset s11, -48
; RV32ZVE32F-NEXT: addi s0, sp, 128 ; RV32ZVE32F-NEXT: addi s0, sp, 96
; RV32ZVE32F-NEXT: .cfi_def_cfa s0, 0 ; RV32ZVE32F-NEXT: .cfi_def_cfa s0, 0
; RV32ZVE32F-NEXT: andi sp, sp, -32 ; RV32ZVE32F-NEXT: andi sp, sp, -32
; RV32ZVE32F-NEXT: lw a4, 60(a3) ; RV32ZVE32F-NEXT: lw a4, 60(a3)
; RV32ZVE32F-NEXT: lw a5, 56(a3) ; RV32ZVE32F-NEXT: lw a5, 56(a3)
; RV32ZVE32F-NEXT: lw a6, 52(a3) ; RV32ZVE32F-NEXT: lw a6, 52(a3)
; RV32ZVE32F-NEXT: lw a7, 48(a3) ; RV32ZVE32F-NEXT: lw a7, 48(a3)
; RV32ZVE32F-NEXT: lw t0, 44(a3) ; RV32ZVE32F-NEXT: lw t0, 44(a3)
; RV32ZVE32F-NEXT: lw t1, 40(a3) ; RV32ZVE32F-NEXT: lw t1, 40(a3)
Show All 10 Lines
; RV32ZVE32F-NEXT: lw s6, 0(a2) ; RV32ZVE32F-NEXT: lw s6, 0(a2)
; RV32ZVE32F-NEXT: lw s7, 8(a2) ; RV32ZVE32F-NEXT: lw s7, 8(a2)
; RV32ZVE32F-NEXT: lw s8, 16(a2) ; RV32ZVE32F-NEXT: lw s8, 16(a2)
; RV32ZVE32F-NEXT: lw s9, 24(a2) ; RV32ZVE32F-NEXT: lw s9, 24(a2)
; RV32ZVE32F-NEXT: lw s10, 56(a2) ; RV32ZVE32F-NEXT: lw s10, 56(a2)
; RV32ZVE32F-NEXT: lw s11, 48(a2) ; RV32ZVE32F-NEXT: lw s11, 48(a2)
; RV32ZVE32F-NEXT: lw ra, 40(a2) ; RV32ZVE32F-NEXT: lw ra, 40(a2)
; RV32ZVE32F-NEXT: lw a2, 32(a2) ; RV32ZVE32F-NEXT: lw a2, 32(a2)
; RV32ZVE32F-NEXT: sw s10, 60(sp) ; RV32ZVE32F-NEXT: sw s10, 28(sp)
; RV32ZVE32F-NEXT: sw s11, 56(sp) ; RV32ZVE32F-NEXT: sw s11, 24(sp)
; RV32ZVE32F-NEXT: sw ra, 52(sp) ; RV32ZVE32F-NEXT: sw ra, 20(sp)
; RV32ZVE32F-NEXT: sw a2, 48(sp) ; RV32ZVE32F-NEXT: sw a2, 16(sp)
; RV32ZVE32F-NEXT: sw s9, 44(sp) ; RV32ZVE32F-NEXT: sw s9, 12(sp)
; RV32ZVE32F-NEXT: sw s8, 40(sp) ; RV32ZVE32F-NEXT: sw s8, 8(sp)
; RV32ZVE32F-NEXT: sw s7, 36(sp) ; RV32ZVE32F-NEXT: sw s7, 4(sp)
; RV32ZVE32F-NEXT: sw s6, 32(sp) ; RV32ZVE32F-NEXT: sw s6, 0(sp)
; RV32ZVE32F-NEXT: mv a2, sp
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32ZVE32F-NEXT: addi a2, sp, 32
; RV32ZVE32F-NEXT: vle32.v v8, (a2) ; RV32ZVE32F-NEXT: vle32.v v8, (a2)
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3 ; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1 ; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
; RV32ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, mu ; RV32ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, mu
; RV32ZVE32F-NEXT: vmv.x.s a1, v0 ; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi a2, a1, 1 ; RV32ZVE32F-NEXT: andi a2, a1, 1
; RV32ZVE32F-NEXT: bnez a2, .LBB57_10 ; RV32ZVE32F-NEXT: bnez a2, .LBB57_10
; RV32ZVE32F-NEXT: # %bb.1: # %else ; RV32ZVE32F-NEXT: # %bb.1: # %else
Show All 35 Lines
; RV32ZVE32F-NEXT: sw t3, 32(a0) ; RV32ZVE32F-NEXT: sw t3, 32(a0)
; RV32ZVE32F-NEXT: sw t2, 36(a0) ; RV32ZVE32F-NEXT: sw t2, 36(a0)
; RV32ZVE32F-NEXT: sw t1, 40(a0) ; RV32ZVE32F-NEXT: sw t1, 40(a0)
; RV32ZVE32F-NEXT: sw t0, 44(a0) ; RV32ZVE32F-NEXT: sw t0, 44(a0)
; RV32ZVE32F-NEXT: sw a7, 48(a0) ; RV32ZVE32F-NEXT: sw a7, 48(a0)
; RV32ZVE32F-NEXT: sw a6, 52(a0) ; RV32ZVE32F-NEXT: sw a6, 52(a0)
; RV32ZVE32F-NEXT: sw a5, 56(a0) ; RV32ZVE32F-NEXT: sw a5, 56(a0)
; RV32ZVE32F-NEXT: sw a4, 60(a0) ; RV32ZVE32F-NEXT: sw a4, 60(a0)
; RV32ZVE32F-NEXT: addi sp, s0, -128 ; RV32ZVE32F-NEXT: addi sp, s0, -96
; RV32ZVE32F-NEXT: lw ra, 124(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw ra, 92(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s0, 120(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s0, 88(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s2, 116(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s2, 84(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s3, 112(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s3, 80(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s4, 108(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s4, 76(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s5, 104(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s5, 72(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s6, 100(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s6, 68(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s7, 96(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s7, 64(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s8, 92(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s8, 60(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s9, 88(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s9, 56(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s10, 84(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s10, 52(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s11, 80(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s11, 48(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: addi sp, sp, 128 ; RV32ZVE32F-NEXT: addi sp, sp, 96
; RV32ZVE32F-NEXT: ret ; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB57_10: # %cond.load ; RV32ZVE32F-NEXT: .LBB57_10: # %cond.load
; RV32ZVE32F-NEXT: vsetivli zero, 0, e32, m2, ta, mu ; RV32ZVE32F-NEXT: vsetivli zero, 0, e32, m2, ta, mu
; RV32ZVE32F-NEXT: vmv.x.s a2, v8 ; RV32ZVE32F-NEXT: vmv.x.s a2, v8
; RV32ZVE32F-NEXT: lw s4, 4(a2) ; RV32ZVE32F-NEXT: lw s4, 4(a2)
; RV32ZVE32F-NEXT: lw a3, 0(a2) ; RV32ZVE32F-NEXT: lw a3, 0(a2)
; RV32ZVE32F-NEXT: andi a2, a1, 2 ; RV32ZVE32F-NEXT: andi a2, a1, 2
; RV32ZVE32F-NEXT: beqz a2, .LBB57_2 ; RV32ZVE32F-NEXT: beqz a2, .LBB57_2
▲ Show 20 Lines • Show All 5,307 Lines • ▼ Show 20 Lines
; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64V-NEXT: vsll.vi v8, v8, 3 ; RV64V-NEXT: vsll.vi v8, v8, 3
; RV64V-NEXT: vluxei64.v v12, (a0), v8, v0.t ; RV64V-NEXT: vluxei64.v v12, (a0), v8, v0.t
; RV64V-NEXT: vmv.v.v v8, v12 ; RV64V-NEXT: vmv.v.v v8, v12
; RV64V-NEXT: ret ; RV64V-NEXT: ret
; ;
; RV32ZVE32F-LABEL: mgather_baseidx_v8f64: ; RV32ZVE32F-LABEL: mgather_baseidx_v8f64:
; RV32ZVE32F: # %bb.0: ; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: addi sp, sp, -96 ; RV32ZVE32F-NEXT: addi sp, sp, -64
; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 96 ; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 64
; RV32ZVE32F-NEXT: sw ra, 92(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s0, 88(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: .cfi_offset ra, -4 ; RV32ZVE32F-NEXT: .cfi_offset ra, -4
; RV32ZVE32F-NEXT: .cfi_offset s0, -8 ; RV32ZVE32F-NEXT: .cfi_offset s0, -8
; RV32ZVE32F-NEXT: addi s0, sp, 96 ; RV32ZVE32F-NEXT: addi s0, sp, 64
; RV32ZVE32F-NEXT: .cfi_def_cfa s0, 0 ; RV32ZVE32F-NEXT: .cfi_def_cfa s0, 0
; RV32ZVE32F-NEXT: andi sp, sp, -32 ; RV32ZVE32F-NEXT: andi sp, sp, -32
; RV32ZVE32F-NEXT: lw a3, 0(a2) ; RV32ZVE32F-NEXT: lw a3, 0(a2)
; RV32ZVE32F-NEXT: lw a4, 8(a2) ; RV32ZVE32F-NEXT: lw a4, 8(a2)
; RV32ZVE32F-NEXT: lw a5, 16(a2) ; RV32ZVE32F-NEXT: lw a5, 16(a2)
; RV32ZVE32F-NEXT: lw a6, 24(a2) ; RV32ZVE32F-NEXT: lw a6, 24(a2)
; RV32ZVE32F-NEXT: lw a7, 56(a2) ; RV32ZVE32F-NEXT: lw a7, 56(a2)
; RV32ZVE32F-NEXT: lw t0, 48(a2) ; RV32ZVE32F-NEXT: lw t0, 48(a2)
; RV32ZVE32F-NEXT: lw t1, 40(a2) ; RV32ZVE32F-NEXT: lw t1, 40(a2)
; RV32ZVE32F-NEXT: lw a2, 32(a2) ; RV32ZVE32F-NEXT: lw a2, 32(a2)
; RV32ZVE32F-NEXT: sw a7, 60(sp) ; RV32ZVE32F-NEXT: sw a7, 28(sp)
; RV32ZVE32F-NEXT: sw t0, 56(sp) ; RV32ZVE32F-NEXT: sw t0, 24(sp)
; RV32ZVE32F-NEXT: sw t1, 52(sp) ; RV32ZVE32F-NEXT: sw t1, 20(sp)
; RV32ZVE32F-NEXT: sw a2, 48(sp) ; RV32ZVE32F-NEXT: sw a2, 16(sp)
; RV32ZVE32F-NEXT: sw a6, 44(sp) ; RV32ZVE32F-NEXT: sw a6, 12(sp)
; RV32ZVE32F-NEXT: sw a5, 40(sp) ; RV32ZVE32F-NEXT: sw a5, 8(sp)
; RV32ZVE32F-NEXT: sw a4, 36(sp) ; RV32ZVE32F-NEXT: sw a4, 4(sp)
; RV32ZVE32F-NEXT: sw a3, 32(sp) ; RV32ZVE32F-NEXT: sw a3, 0(sp)
; RV32ZVE32F-NEXT: mv a2, sp
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32ZVE32F-NEXT: addi a2, sp, 32
; RV32ZVE32F-NEXT: vle32.v v8, (a2) ; RV32ZVE32F-NEXT: vle32.v v8, (a2)
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3 ; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1 ; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
; RV32ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, mu ; RV32ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, mu
; RV32ZVE32F-NEXT: vmv.x.s a1, v0 ; RV32ZVE32F-NEXT: vmv.x.s a1, v0
; RV32ZVE32F-NEXT: andi a2, a1, 1 ; RV32ZVE32F-NEXT: andi a2, a1, 1
; RV32ZVE32F-NEXT: bnez a2, .LBB96_10 ; RV32ZVE32F-NEXT: bnez a2, .LBB96_10
; RV32ZVE32F-NEXT: # %bb.1: # %else ; RV32ZVE32F-NEXT: # %bb.1: # %else
Show All 26 Lines
; RV32ZVE32F-NEXT: fsd fa0, 0(a0) ; RV32ZVE32F-NEXT: fsd fa0, 0(a0)
; RV32ZVE32F-NEXT: fsd fa1, 8(a0) ; RV32ZVE32F-NEXT: fsd fa1, 8(a0)
; RV32ZVE32F-NEXT: fsd fa2, 16(a0) ; RV32ZVE32F-NEXT: fsd fa2, 16(a0)
; RV32ZVE32F-NEXT: fsd fa3, 24(a0) ; RV32ZVE32F-NEXT: fsd fa3, 24(a0)
; RV32ZVE32F-NEXT: fsd fa4, 32(a0) ; RV32ZVE32F-NEXT: fsd fa4, 32(a0)
; RV32ZVE32F-NEXT: fsd fa5, 40(a0) ; RV32ZVE32F-NEXT: fsd fa5, 40(a0)
; RV32ZVE32F-NEXT: fsd fa6, 48(a0) ; RV32ZVE32F-NEXT: fsd fa6, 48(a0)
; RV32ZVE32F-NEXT: fsd fa7, 56(a0) ; RV32ZVE32F-NEXT: fsd fa7, 56(a0)
; RV32ZVE32F-NEXT: addi sp, s0, -96 ; RV32ZVE32F-NEXT: addi sp, s0, -64
; RV32ZVE32F-NEXT: lw ra, 92(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s0, 88(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: addi sp, sp, 96 ; RV32ZVE32F-NEXT: addi sp, sp, 64
; RV32ZVE32F-NEXT: ret ; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB96_10: # %cond.load ; RV32ZVE32F-NEXT: .LBB96_10: # %cond.load
; RV32ZVE32F-NEXT: vsetivli zero, 0, e32, m2, ta, mu ; RV32ZVE32F-NEXT: vsetivli zero, 0, e32, m2, ta, mu
; RV32ZVE32F-NEXT: vmv.x.s a2, v8 ; RV32ZVE32F-NEXT: vmv.x.s a2, v8
; RV32ZVE32F-NEXT: fld fa0, 0(a2) ; RV32ZVE32F-NEXT: fld fa0, 0(a2)
; RV32ZVE32F-NEXT: andi a2, a1, 2 ; RV32ZVE32F-NEXT: andi a2, a1, 2
; RV32ZVE32F-NEXT: beqz a2, .LBB96_2 ; RV32ZVE32F-NEXT: beqz a2, .LBB96_2
; RV32ZVE32F-NEXT: .LBB96_11: # %cond.load1 ; RV32ZVE32F-NEXT: .LBB96_11: # %cond.load1
▲ Show 20 Lines • Show All 914 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 267 Lines • ▼ Show 20 Lines
; RV32ZVE32F-LABEL: mscatter_v2i64_truncstore_v2i8: ; RV32ZVE32F-LABEL: mscatter_v2i64_truncstore_v2i8:
; RV32ZVE32F: # %bb.0: ; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: addi sp, sp, -16 ; RV32ZVE32F-NEXT: addi sp, sp, -16
; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 16 ; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 16
; RV32ZVE32F-NEXT: lw a1, 8(a0) ; RV32ZVE32F-NEXT: lw a1, 8(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0) ; RV32ZVE32F-NEXT: lw a0, 0(a0)
; RV32ZVE32F-NEXT: sb a1, 15(sp) ; RV32ZVE32F-NEXT: sb a1, 15(sp)
; RV32ZVE32F-NEXT: sb a0, 14(sp) ; RV32ZVE32F-NEXT: sb a0, 14(sp)
; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; RV32ZVE32F-NEXT: addi a0, sp, 15 ; RV32ZVE32F-NEXT: addi a0, sp, 15
; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; RV32ZVE32F-NEXT: vle8.v v9, (a0) ; RV32ZVE32F-NEXT: vle8.v v9, (a0)
; RV32ZVE32F-NEXT: addi a0, sp, 14 ; RV32ZVE32F-NEXT: addi a0, sp, 14
; RV32ZVE32F-NEXT: vle8.v v10, (a0) ; RV32ZVE32F-NEXT: vle8.v v10, (a0)
; RV32ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, tu, mu ; RV32ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, tu, mu
; RV32ZVE32F-NEXT: vslideup.vi v10, v9, 1 ; RV32ZVE32F-NEXT: vslideup.vi v10, v9, 1
; RV32ZVE32F-NEXT: vsoxei32.v v10, (zero), v8, v0.t ; RV32ZVE32F-NEXT: vsoxei32.v v10, (zero), v8, v0.t
; RV32ZVE32F-NEXT: addi sp, sp, 16 ; RV32ZVE32F-NEXT: addi sp, sp, 16
; RV32ZVE32F-NEXT: ret ; RV32ZVE32F-NEXT: ret
Show All 11 Lines
; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 0 ; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 0
; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64ZVE32F-NEXT: vmsne.vi v8, v9, 0 ; RV64ZVE32F-NEXT: vmsne.vi v8, v9, 0
; RV64ZVE32F-NEXT: addi a4, sp, 15 ; RV64ZVE32F-NEXT: addi a4, sp, 15
; RV64ZVE32F-NEXT: vsm.v v8, (a4) ; RV64ZVE32F-NEXT: vsm.v v8, (a4)
; RV64ZVE32F-NEXT: lbu a4, 15(sp) ; RV64ZVE32F-NEXT: lbu a4, 15(sp)
; RV64ZVE32F-NEXT: sb a1, 14(sp) ; RV64ZVE32F-NEXT: sb a1, 14(sp)
; RV64ZVE32F-NEXT: sb a0, 13(sp) ; RV64ZVE32F-NEXT: sb a0, 13(sp)
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; RV64ZVE32F-NEXT: addi a0, sp, 14 ; RV64ZVE32F-NEXT: addi a0, sp, 14
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; RV64ZVE32F-NEXT: vle8.v v9, (a0) ; RV64ZVE32F-NEXT: vle8.v v9, (a0)
; RV64ZVE32F-NEXT: addi a0, sp, 13 ; RV64ZVE32F-NEXT: addi a0, sp, 13
; RV64ZVE32F-NEXT: vle8.v v8, (a0) ; RV64ZVE32F-NEXT: vle8.v v8, (a0)
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, tu, mu ; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, tu, mu
; RV64ZVE32F-NEXT: andi a0, a4, 1 ; RV64ZVE32F-NEXT: andi a0, a4, 1
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 ; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: bnez a0, .LBB4_3 ; RV64ZVE32F-NEXT: bnez a0, .LBB4_3
; RV64ZVE32F-NEXT: # %bb.1: # %else ; RV64ZVE32F-NEXT: # %bb.1: # %else
▲ Show 20 Lines • Show All 585 Lines • ▼ Show 20 Lines
; RV32ZVE32F-LABEL: mscatter_v2i64_truncstore_v2i16: ; RV32ZVE32F-LABEL: mscatter_v2i64_truncstore_v2i16:
; RV32ZVE32F: # %bb.0: ; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: addi sp, sp, -16 ; RV32ZVE32F-NEXT: addi sp, sp, -16
; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 16 ; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 16
; RV32ZVE32F-NEXT: lw a1, 8(a0) ; RV32ZVE32F-NEXT: lw a1, 8(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0) ; RV32ZVE32F-NEXT: lw a0, 0(a0)
; RV32ZVE32F-NEXT: sh a1, 14(sp) ; RV32ZVE32F-NEXT: sh a1, 14(sp)
; RV32ZVE32F-NEXT: sh a0, 12(sp) ; RV32ZVE32F-NEXT: sh a0, 12(sp)
; RV32ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
; RV32ZVE32F-NEXT: addi a0, sp, 14 ; RV32ZVE32F-NEXT: addi a0, sp, 14
; RV32ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
; RV32ZVE32F-NEXT: vle16.v v9, (a0) ; RV32ZVE32F-NEXT: vle16.v v9, (a0)
; RV32ZVE32F-NEXT: addi a0, sp, 12 ; RV32ZVE32F-NEXT: addi a0, sp, 12
; RV32ZVE32F-NEXT: vle16.v v10, (a0) ; RV32ZVE32F-NEXT: vle16.v v10, (a0)
; RV32ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, tu, mu ; RV32ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, tu, mu
; RV32ZVE32F-NEXT: vslideup.vi v10, v9, 1 ; RV32ZVE32F-NEXT: vslideup.vi v10, v9, 1
; RV32ZVE32F-NEXT: vsoxei32.v v10, (zero), v8, v0.t ; RV32ZVE32F-NEXT: vsoxei32.v v10, (zero), v8, v0.t
; RV32ZVE32F-NEXT: addi sp, sp, 16 ; RV32ZVE32F-NEXT: addi sp, sp, 16
; RV32ZVE32F-NEXT: ret ; RV32ZVE32F-NEXT: ret
Show All 11 Lines
; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 0 ; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 0
; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64ZVE32F-NEXT: vmsne.vi v8, v9, 0 ; RV64ZVE32F-NEXT: vmsne.vi v8, v9, 0
; RV64ZVE32F-NEXT: addi a4, sp, 15 ; RV64ZVE32F-NEXT: addi a4, sp, 15
; RV64ZVE32F-NEXT: vsm.v v8, (a4) ; RV64ZVE32F-NEXT: vsm.v v8, (a4)
; RV64ZVE32F-NEXT: lbu a4, 15(sp) ; RV64ZVE32F-NEXT: lbu a4, 15(sp)
; RV64ZVE32F-NEXT: sh a1, 12(sp) ; RV64ZVE32F-NEXT: sh a1, 12(sp)
; RV64ZVE32F-NEXT: sh a0, 10(sp) ; RV64ZVE32F-NEXT: sh a0, 10(sp)
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
; RV64ZVE32F-NEXT: addi a0, sp, 12 ; RV64ZVE32F-NEXT: addi a0, sp, 12
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
; RV64ZVE32F-NEXT: vle16.v v9, (a0) ; RV64ZVE32F-NEXT: vle16.v v9, (a0)
; RV64ZVE32F-NEXT: addi a0, sp, 10 ; RV64ZVE32F-NEXT: addi a0, sp, 10
; RV64ZVE32F-NEXT: vle16.v v8, (a0) ; RV64ZVE32F-NEXT: vle16.v v8, (a0)
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, tu, mu ; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, tu, mu
; RV64ZVE32F-NEXT: andi a0, a4, 1 ; RV64ZVE32F-NEXT: andi a0, a4, 1
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 ; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: bnez a0, .LBB13_3 ; RV64ZVE32F-NEXT: bnez a0, .LBB13_3
; RV64ZVE32F-NEXT: # %bb.1: # %else ; RV64ZVE32F-NEXT: # %bb.1: # %else
▲ Show 20 Lines • Show All 936 Lines • ▼ Show 20 Lines
; RV32ZVE32F-NEXT: vlse32.v v9, (a0), zero ; RV32ZVE32F-NEXT: vlse32.v v9, (a0), zero
; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, tu, mu ; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; RV32ZVE32F-NEXT: vmv.s.x v9, a1 ; RV32ZVE32F-NEXT: vmv.s.x v9, a1
; RV32ZVE32F-NEXT: vsoxei32.v v9, (zero), v8, v0.t ; RV32ZVE32F-NEXT: vsoxei32.v v9, (zero), v8, v0.t
; RV32ZVE32F-NEXT: ret ; RV32ZVE32F-NEXT: ret
; ;
; RV64ZVE32F-LABEL: mscatter_v2i64_truncstore_v2i32: ; RV64ZVE32F-LABEL: mscatter_v2i64_truncstore_v2i32:
; RV64ZVE32F: # %bb.0: ; RV64ZVE32F: # %bb.0:
; RV64ZVE32F-NEXT: addi sp, sp, -32 ; RV64ZVE32F-NEXT: addi sp, sp, -16
; RV64ZVE32F-NEXT: .cfi_def_cfa_offset 32 ; RV64ZVE32F-NEXT: .cfi_def_cfa_offset 16
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV64ZVE32F-NEXT: vmv.v.i v8, 0 ; RV64ZVE32F-NEXT: vmv.v.i v8, 0
; RV64ZVE32F-NEXT: vmerge.vim v8, v8, 1, v0 ; RV64ZVE32F-NEXT: vmerge.vim v8, v8, 1, v0
; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64ZVE32F-NEXT: vmv.v.i v9, 0 ; RV64ZVE32F-NEXT: vmv.v.i v9, 0
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 0 ; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 0
; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64ZVE32F-NEXT: vmsne.vi v8, v9, 0 ; RV64ZVE32F-NEXT: vmsne.vi v8, v9, 0
; RV64ZVE32F-NEXT: addi a4, sp, 31 ; RV64ZVE32F-NEXT: addi a4, sp, 15
; RV64ZVE32F-NEXT: vsm.v v8, (a4) ; RV64ZVE32F-NEXT: vsm.v v8, (a4)
; RV64ZVE32F-NEXT: lbu a4, 31(sp) ; RV64ZVE32F-NEXT: lbu a4, 15(sp)
; RV64ZVE32F-NEXT: sw a1, 24(sp) ; RV64ZVE32F-NEXT: sw a1, 8(sp)
; RV64ZVE32F-NEXT: sw a0, 20(sp) ; RV64ZVE32F-NEXT: sw a0, 4(sp)
; RV64ZVE32F-NEXT: addi a0, sp, 8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; RV64ZVE32F-NEXT: addi a0, sp, 24
; RV64ZVE32F-NEXT: vle32.v v9, (a0) ; RV64ZVE32F-NEXT: vle32.v v9, (a0)
; RV64ZVE32F-NEXT: addi a0, sp, 20 ; RV64ZVE32F-NEXT: addi a0, sp, 4
; RV64ZVE32F-NEXT: vle32.v v8, (a0) ; RV64ZVE32F-NEXT: vle32.v v8, (a0)
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, mu ; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, mu
; RV64ZVE32F-NEXT: andi a0, a4, 1 ; RV64ZVE32F-NEXT: andi a0, a4, 1
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 ; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: bnez a0, .LBB24_3 ; RV64ZVE32F-NEXT: bnez a0, .LBB24_3
; RV64ZVE32F-NEXT: # %bb.1: # %else ; RV64ZVE32F-NEXT: # %bb.1: # %else
; RV64ZVE32F-NEXT: andi a0, a4, 2 ; RV64ZVE32F-NEXT: andi a0, a4, 2
; RV64ZVE32F-NEXT: bnez a0, .LBB24_4 ; RV64ZVE32F-NEXT: bnez a0, .LBB24_4
; RV64ZVE32F-NEXT: .LBB24_2: # %else2 ; RV64ZVE32F-NEXT: .LBB24_2: # %else2
; RV64ZVE32F-NEXT: addi sp, sp, 32 ; RV64ZVE32F-NEXT: addi sp, sp, 16
; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: ret
; RV64ZVE32F-NEXT: .LBB24_3: # %cond.store ; RV64ZVE32F-NEXT: .LBB24_3: # %cond.store
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; RV64ZVE32F-NEXT: vse32.v v8, (a2) ; RV64ZVE32F-NEXT: vse32.v v8, (a2)
; RV64ZVE32F-NEXT: andi a0, a4, 2 ; RV64ZVE32F-NEXT: andi a0, a4, 2
; RV64ZVE32F-NEXT: beqz a0, .LBB24_2 ; RV64ZVE32F-NEXT: beqz a0, .LBB24_2
; RV64ZVE32F-NEXT: .LBB24_4: # %cond.store1 ; RV64ZVE32F-NEXT: .LBB24_4: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vse32.v v8, (a3) ; RV64ZVE32F-NEXT: vse32.v v8, (a3)
; RV64ZVE32F-NEXT: addi sp, sp, 32 ; RV64ZVE32F-NEXT: addi sp, sp, 16
; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: ret
%tval = trunc <2 x i64> %val to <2 x i32> %tval = trunc <2 x i64> %val to <2 x i32>
call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> %tval, <2 x i32*> %ptrs, i32 4, <2 x i1> %m) call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> %tval, <2 x i32*> %ptrs, i32 4, <2 x i1> %m)
ret void ret void
} }
declare void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32>, <4 x i32*>, i32, <4 x i1>) declare void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32>, <4 x i32*>, i32, <4 x i1>)
▲ Show 20 Lines • Show All 4,147 Lines • ▼ Show 20 Lines
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsll.vi v12, v12, 3 ; RV64-NEXT: vsll.vi v12, v12, 3
; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32ZVE32F-LABEL: mscatter_baseidx_v8i64: ; RV32ZVE32F-LABEL: mscatter_baseidx_v8i64:
; RV32ZVE32F: # %bb.0: ; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: addi sp, sp, -128 ; RV32ZVE32F-NEXT: addi sp, sp, -96
; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 128 ; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 96
; RV32ZVE32F-NEXT: sw ra, 124(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw ra, 92(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s0, 120(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s0, 88(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s2, 116(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s2, 84(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s3, 112(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s3, 80(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s4, 108(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s4, 76(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s5, 104(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s5, 72(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s6, 100(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s6, 68(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s7, 96(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s7, 64(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s8, 92(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s8, 60(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s9, 88(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s9, 56(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s10, 84(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s10, 52(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s11, 80(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s11, 48(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: .cfi_offset ra, -4 ; RV32ZVE32F-NEXT: .cfi_offset ra, -4
; RV32ZVE32F-NEXT: .cfi_offset s0, -8 ; RV32ZVE32F-NEXT: .cfi_offset s0, -8
; RV32ZVE32F-NEXT: .cfi_offset s2, -12 ; RV32ZVE32F-NEXT: .cfi_offset s2, -12
; RV32ZVE32F-NEXT: .cfi_offset s3, -16 ; RV32ZVE32F-NEXT: .cfi_offset s3, -16
; RV32ZVE32F-NEXT: .cfi_offset s4, -20 ; RV32ZVE32F-NEXT: .cfi_offset s4, -20
; RV32ZVE32F-NEXT: .cfi_offset s5, -24 ; RV32ZVE32F-NEXT: .cfi_offset s5, -24
; RV32ZVE32F-NEXT: .cfi_offset s6, -28 ; RV32ZVE32F-NEXT: .cfi_offset s6, -28
; RV32ZVE32F-NEXT: .cfi_offset s7, -32 ; RV32ZVE32F-NEXT: .cfi_offset s7, -32
; RV32ZVE32F-NEXT: .cfi_offset s8, -36 ; RV32ZVE32F-NEXT: .cfi_offset s8, -36
; RV32ZVE32F-NEXT: .cfi_offset s9, -40 ; RV32ZVE32F-NEXT: .cfi_offset s9, -40
; RV32ZVE32F-NEXT: .cfi_offset s10, -44 ; RV32ZVE32F-NEXT: .cfi_offset s10, -44
; RV32ZVE32F-NEXT: .cfi_offset s11, -48 ; RV32ZVE32F-NEXT: .cfi_offset s11, -48
; RV32ZVE32F-NEXT: addi s0, sp, 128 ; RV32ZVE32F-NEXT: addi s0, sp, 96
; RV32ZVE32F-NEXT: .cfi_def_cfa s0, 0 ; RV32ZVE32F-NEXT: .cfi_def_cfa s0, 0
; RV32ZVE32F-NEXT: andi sp, sp, -32 ; RV32ZVE32F-NEXT: andi sp, sp, -32
; RV32ZVE32F-NEXT: lw a3, 60(a0) ; RV32ZVE32F-NEXT: lw a3, 60(a0)
; RV32ZVE32F-NEXT: lw a4, 56(a0) ; RV32ZVE32F-NEXT: lw a4, 56(a0)
; RV32ZVE32F-NEXT: lw a5, 52(a0) ; RV32ZVE32F-NEXT: lw a5, 52(a0)
; RV32ZVE32F-NEXT: lw a6, 48(a0) ; RV32ZVE32F-NEXT: lw a6, 48(a0)
; RV32ZVE32F-NEXT: lw a7, 44(a0) ; RV32ZVE32F-NEXT: lw a7, 44(a0)
; RV32ZVE32F-NEXT: lw t0, 40(a0) ; RV32ZVE32F-NEXT: lw t0, 40(a0)
Show All 10 Lines
; RV32ZVE32F-NEXT: lw a0, 0(a2) ; RV32ZVE32F-NEXT: lw a0, 0(a2)
; RV32ZVE32F-NEXT: lw s6, 8(a2) ; RV32ZVE32F-NEXT: lw s6, 8(a2)
; RV32ZVE32F-NEXT: lw s7, 16(a2) ; RV32ZVE32F-NEXT: lw s7, 16(a2)
; RV32ZVE32F-NEXT: lw s8, 24(a2) ; RV32ZVE32F-NEXT: lw s8, 24(a2)
; RV32ZVE32F-NEXT: lw s9, 56(a2) ; RV32ZVE32F-NEXT: lw s9, 56(a2)
; RV32ZVE32F-NEXT: lw s10, 48(a2) ; RV32ZVE32F-NEXT: lw s10, 48(a2)
; RV32ZVE32F-NEXT: lw s11, 40(a2) ; RV32ZVE32F-NEXT: lw s11, 40(a2)
; RV32ZVE32F-NEXT: lw a2, 32(a2) ; RV32ZVE32F-NEXT: lw a2, 32(a2)
; RV32ZVE32F-NEXT: sw s9, 60(sp) ; RV32ZVE32F-NEXT: sw s9, 28(sp)
; RV32ZVE32F-NEXT: sw s10, 56(sp) ; RV32ZVE32F-NEXT: sw s10, 24(sp)
; RV32ZVE32F-NEXT: sw s11, 52(sp) ; RV32ZVE32F-NEXT: sw s11, 20(sp)
; RV32ZVE32F-NEXT: sw a2, 48(sp) ; RV32ZVE32F-NEXT: sw a2, 16(sp)
; RV32ZVE32F-NEXT: sw s8, 44(sp) ; RV32ZVE32F-NEXT: sw s8, 12(sp)
; RV32ZVE32F-NEXT: sw s7, 40(sp) ; RV32ZVE32F-NEXT: sw s7, 8(sp)
; RV32ZVE32F-NEXT: sw s6, 36(sp) ; RV32ZVE32F-NEXT: sw s6, 4(sp)
; RV32ZVE32F-NEXT: sw a0, 32(sp) ; RV32ZVE32F-NEXT: sw a0, 0(sp)
; RV32ZVE32F-NEXT: mv a0, sp
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32ZVE32F-NEXT: addi a0, sp, 32
; RV32ZVE32F-NEXT: vle32.v v8, (a0) ; RV32ZVE32F-NEXT: vle32.v v8, (a0)
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3 ; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1 ; RV32ZVE32F-NEXT: vadd.vx v8, v8, a1
; RV32ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, mu ; RV32ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, mu
; RV32ZVE32F-NEXT: vmv.x.s a0, v0 ; RV32ZVE32F-NEXT: vmv.x.s a0, v0
; RV32ZVE32F-NEXT: andi a1, a0, 1 ; RV32ZVE32F-NEXT: andi a1, a0, 1
; RV32ZVE32F-NEXT: bnez a1, .LBB51_10 ; RV32ZVE32F-NEXT: bnez a1, .LBB51_10
; RV32ZVE32F-NEXT: # %bb.1: # %else ; RV32ZVE32F-NEXT: # %bb.1: # %else
Show All 19 Lines
; RV32ZVE32F-NEXT: beqz a0, .LBB51_9 ; RV32ZVE32F-NEXT: beqz a0, .LBB51_9
; RV32ZVE32F-NEXT: .LBB51_8: # %cond.store13 ; RV32ZVE32F-NEXT: .LBB51_8: # %cond.store13
; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, mu ; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, mu
; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 7 ; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 7
; RV32ZVE32F-NEXT: vmv.x.s a0, v8 ; RV32ZVE32F-NEXT: vmv.x.s a0, v8
; RV32ZVE32F-NEXT: sw a4, 0(a0) ; RV32ZVE32F-NEXT: sw a4, 0(a0)
; RV32ZVE32F-NEXT: sw a3, 4(a0) ; RV32ZVE32F-NEXT: sw a3, 4(a0)
; RV32ZVE32F-NEXT: .LBB51_9: # %else14 ; RV32ZVE32F-NEXT: .LBB51_9: # %else14
; RV32ZVE32F-NEXT: addi sp, s0, -128 ; RV32ZVE32F-NEXT: addi sp, s0, -96
; RV32ZVE32F-NEXT: lw ra, 124(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw ra, 92(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s0, 120(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s0, 88(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s2, 116(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s2, 84(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s3, 112(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s3, 80(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s4, 108(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s4, 76(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s5, 104(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s5, 72(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s6, 100(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s6, 68(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s7, 96(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s7, 64(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s8, 92(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s8, 60(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s9, 88(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s9, 56(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s10, 84(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s10, 52(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s11, 80(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s11, 48(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: addi sp, sp, 128 ; RV32ZVE32F-NEXT: addi sp, sp, 96
; RV32ZVE32F-NEXT: ret ; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB51_10: # %cond.store ; RV32ZVE32F-NEXT: .LBB51_10: # %cond.store
; RV32ZVE32F-NEXT: vsetivli zero, 0, e32, m2, ta, mu ; RV32ZVE32F-NEXT: vsetivli zero, 0, e32, m2, ta, mu
; RV32ZVE32F-NEXT: vmv.x.s a1, v8 ; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: sw s5, 4(a1) ; RV32ZVE32F-NEXT: sw s5, 4(a1)
; RV32ZVE32F-NEXT: sw s4, 0(a1) ; RV32ZVE32F-NEXT: sw s4, 0(a1)
; RV32ZVE32F-NEXT: andi a1, a0, 2 ; RV32ZVE32F-NEXT: andi a1, a0, 2
; RV32ZVE32F-NEXT: beqz a1, .LBB51_2 ; RV32ZVE32F-NEXT: beqz a1, .LBB51_2
▲ Show 20 Lines • Show All 4,813 Lines • ▼ Show 20 Lines
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vsll.vi v12, v12, 3 ; RV64-NEXT: vsll.vi v12, v12, 3
; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v12, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32ZVE32F-LABEL: mscatter_baseidx_v8f64: ; RV32ZVE32F-LABEL: mscatter_baseidx_v8f64:
; RV32ZVE32F: # %bb.0: ; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: addi sp, sp, -96 ; RV32ZVE32F-NEXT: addi sp, sp, -64
; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 96 ; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 64
; RV32ZVE32F-NEXT: sw ra, 92(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: sw s0, 88(sp) # 4-byte Folded Spill ; RV32ZVE32F-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; RV32ZVE32F-NEXT: .cfi_offset ra, -4 ; RV32ZVE32F-NEXT: .cfi_offset ra, -4
; RV32ZVE32F-NEXT: .cfi_offset s0, -8 ; RV32ZVE32F-NEXT: .cfi_offset s0, -8
; RV32ZVE32F-NEXT: addi s0, sp, 96 ; RV32ZVE32F-NEXT: addi s0, sp, 64
; RV32ZVE32F-NEXT: .cfi_def_cfa s0, 0 ; RV32ZVE32F-NEXT: .cfi_def_cfa s0, 0
; RV32ZVE32F-NEXT: andi sp, sp, -32 ; RV32ZVE32F-NEXT: andi sp, sp, -32
; RV32ZVE32F-NEXT: lw a2, 0(a1) ; RV32ZVE32F-NEXT: lw a2, 0(a1)
; RV32ZVE32F-NEXT: lw a3, 8(a1) ; RV32ZVE32F-NEXT: lw a3, 8(a1)
; RV32ZVE32F-NEXT: lw a4, 16(a1) ; RV32ZVE32F-NEXT: lw a4, 16(a1)
; RV32ZVE32F-NEXT: lw a5, 24(a1) ; RV32ZVE32F-NEXT: lw a5, 24(a1)
; RV32ZVE32F-NEXT: lw a6, 56(a1) ; RV32ZVE32F-NEXT: lw a6, 56(a1)
; RV32ZVE32F-NEXT: lw a7, 48(a1) ; RV32ZVE32F-NEXT: lw a7, 48(a1)
; RV32ZVE32F-NEXT: lw t0, 40(a1) ; RV32ZVE32F-NEXT: lw t0, 40(a1)
; RV32ZVE32F-NEXT: lw a1, 32(a1) ; RV32ZVE32F-NEXT: lw a1, 32(a1)
; RV32ZVE32F-NEXT: sw a6, 60(sp) ; RV32ZVE32F-NEXT: sw a6, 28(sp)
; RV32ZVE32F-NEXT: sw a7, 56(sp) ; RV32ZVE32F-NEXT: sw a7, 24(sp)
; RV32ZVE32F-NEXT: sw t0, 52(sp) ; RV32ZVE32F-NEXT: sw t0, 20(sp)
; RV32ZVE32F-NEXT: sw a1, 48(sp) ; RV32ZVE32F-NEXT: sw a1, 16(sp)
; RV32ZVE32F-NEXT: sw a5, 44(sp) ; RV32ZVE32F-NEXT: sw a5, 12(sp)
; RV32ZVE32F-NEXT: sw a4, 40(sp) ; RV32ZVE32F-NEXT: sw a4, 8(sp)
; RV32ZVE32F-NEXT: sw a3, 36(sp) ; RV32ZVE32F-NEXT: sw a3, 4(sp)
; RV32ZVE32F-NEXT: sw a2, 32(sp) ; RV32ZVE32F-NEXT: sw a2, 0(sp)
; RV32ZVE32F-NEXT: mv a1, sp
; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV32ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32ZVE32F-NEXT: addi a1, sp, 32
; RV32ZVE32F-NEXT: vle32.v v8, (a1) ; RV32ZVE32F-NEXT: vle32.v v8, (a1)
; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3 ; RV32ZVE32F-NEXT: vsll.vi v8, v8, 3
; RV32ZVE32F-NEXT: vadd.vx v8, v8, a0 ; RV32ZVE32F-NEXT: vadd.vx v8, v8, a0
; RV32ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, mu ; RV32ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, mu
; RV32ZVE32F-NEXT: vmv.x.s a0, v0 ; RV32ZVE32F-NEXT: vmv.x.s a0, v0
; RV32ZVE32F-NEXT: andi a1, a0, 1 ; RV32ZVE32F-NEXT: andi a1, a0, 1
; RV32ZVE32F-NEXT: bnez a1, .LBB90_10 ; RV32ZVE32F-NEXT: bnez a1, .LBB90_10
; RV32ZVE32F-NEXT: # %bb.1: # %else ; RV32ZVE32F-NEXT: # %bb.1: # %else
Show All 18 Lines
; RV32ZVE32F-NEXT: andi a0, a0, -128 ; RV32ZVE32F-NEXT: andi a0, a0, -128
; RV32ZVE32F-NEXT: beqz a0, .LBB90_9 ; RV32ZVE32F-NEXT: beqz a0, .LBB90_9
; RV32ZVE32F-NEXT: .LBB90_8: # %cond.store13 ; RV32ZVE32F-NEXT: .LBB90_8: # %cond.store13
; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, mu ; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, mu
; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 7 ; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 7
; RV32ZVE32F-NEXT: vmv.x.s a0, v8 ; RV32ZVE32F-NEXT: vmv.x.s a0, v8
; RV32ZVE32F-NEXT: fsd fa7, 0(a0) ; RV32ZVE32F-NEXT: fsd fa7, 0(a0)
; RV32ZVE32F-NEXT: .LBB90_9: # %else14 ; RV32ZVE32F-NEXT: .LBB90_9: # %else14
; RV32ZVE32F-NEXT: addi sp, s0, -96 ; RV32ZVE32F-NEXT: addi sp, s0, -64
; RV32ZVE32F-NEXT: lw ra, 92(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: lw s0, 88(sp) # 4-byte Folded Reload ; RV32ZVE32F-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32ZVE32F-NEXT: addi sp, sp, 96 ; RV32ZVE32F-NEXT: addi sp, sp, 64
; RV32ZVE32F-NEXT: ret ; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB90_10: # %cond.store ; RV32ZVE32F-NEXT: .LBB90_10: # %cond.store
; RV32ZVE32F-NEXT: vsetivli zero, 0, e32, m2, ta, mu ; RV32ZVE32F-NEXT: vsetivli zero, 0, e32, m2, ta, mu
; RV32ZVE32F-NEXT: vmv.x.s a1, v8 ; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: fsd fa0, 0(a1) ; RV32ZVE32F-NEXT: fsd fa0, 0(a1)
; RV32ZVE32F-NEXT: andi a1, a0, 2 ; RV32ZVE32F-NEXT: andi a1, a0, 2
; RV32ZVE32F-NEXT: beqz a1, .LBB90_2 ; RV32ZVE32F-NEXT: beqz a1, .LBB90_2
; RV32ZVE32F-NEXT: .LBB90_11: # %cond.store1 ; RV32ZVE32F-NEXT: .LBB90_11: # %cond.store1
▲ Show 20 Lines • Show All 782 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll

Show First 20 Lines • Show All 877 Lines • ▼ Show 20 Lines
define signext i64 @vpreduce_add_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_add_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_add_v2i64: ; RV32-LABEL: vpreduce_add_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
; RV32-NEXT: vredsum.vs v9, v8, v9, v0.t ; RV32-NEXT: vredsum.vs v9, v8, v9, v0.t
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v9, a1 ; RV32-NEXT: vsrl.vx v8, v9, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_umax_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_umax_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_umax_v2i64: ; RV32-LABEL: vpreduce_umax_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t ; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v9, a1 ; RV32-NEXT: vsrl.vx v8, v9, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_smax_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_smax_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_smax_v2i64: ; RV32-LABEL: vpreduce_smax_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
; RV32-NEXT: vredmax.vs v9, v8, v9, v0.t ; RV32-NEXT: vredmax.vs v9, v8, v9, v0.t
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v9, a1 ; RV32-NEXT: vsrl.vx v8, v9, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_umin_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_umin_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_umin_v2i64: ; RV32-LABEL: vpreduce_umin_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t ; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v9, a1 ; RV32-NEXT: vsrl.vx v8, v9, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_smin_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_smin_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_smin_v2i64: ; RV32-LABEL: vpreduce_smin_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
; RV32-NEXT: vredmin.vs v9, v8, v9, v0.t ; RV32-NEXT: vredmin.vs v9, v8, v9, v0.t
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v9, a1 ; RV32-NEXT: vsrl.vx v8, v9, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_and_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_and_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_and_v2i64: ; RV32-LABEL: vpreduce_and_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
; RV32-NEXT: vredand.vs v9, v8, v9, v0.t ; RV32-NEXT: vredand.vs v9, v8, v9, v0.t
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v9, a1 ; RV32-NEXT: vsrl.vx v8, v9, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_or_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_or_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_or_v2i64: ; RV32-LABEL: vpreduce_or_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
; RV32-NEXT: vredor.vs v9, v8, v9, v0.t ; RV32-NEXT: vredor.vs v9, v8, v9, v0.t
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v9, a1 ; RV32-NEXT: vsrl.vx v8, v9, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_xor_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_xor_v2i64(i64 signext %s, <2 x i64> %v, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_xor_v2i64: ; RV32-LABEL: vpreduce_xor_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
; RV32-NEXT: vredxor.vs v9, v8, v9, v0.t ; RV32-NEXT: vredxor.vs v9, v8, v9, v0.t
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v9, a1 ; RV32-NEXT: vsrl.vx v8, v9, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_add_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_add_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_add_v4i64: ; RV32-LABEL: vpreduce_add_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
; RV32-NEXT: vredsum.vs v10, v8, v10, v0.t ; RV32-NEXT: vredsum.vs v10, v8, v10, v0.t
; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v10, a1 ; RV32-NEXT: vsrl.vx v8, v10, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_umax_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_umax_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_umax_v4i64: ; RV32-LABEL: vpreduce_umax_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
; RV32-NEXT: vredmaxu.vs v10, v8, v10, v0.t ; RV32-NEXT: vredmaxu.vs v10, v8, v10, v0.t
; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v10, a1 ; RV32-NEXT: vsrl.vx v8, v10, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_smax_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_smax_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_smax_v4i64: ; RV32-LABEL: vpreduce_smax_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
; RV32-NEXT: vredmax.vs v10, v8, v10, v0.t ; RV32-NEXT: vredmax.vs v10, v8, v10, v0.t
; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v10, a1 ; RV32-NEXT: vsrl.vx v8, v10, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_umin_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_umin_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_umin_v4i64: ; RV32-LABEL: vpreduce_umin_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
; RV32-NEXT: vredminu.vs v10, v8, v10, v0.t ; RV32-NEXT: vredminu.vs v10, v8, v10, v0.t
; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v10, a1 ; RV32-NEXT: vsrl.vx v8, v10, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_smin_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_smin_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_smin_v4i64: ; RV32-LABEL: vpreduce_smin_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
; RV32-NEXT: vredmin.vs v10, v8, v10, v0.t ; RV32-NEXT: vredmin.vs v10, v8, v10, v0.t
; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v10, a1 ; RV32-NEXT: vsrl.vx v8, v10, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_and_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_and_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_and_v4i64: ; RV32-LABEL: vpreduce_and_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
; RV32-NEXT: vredand.vs v10, v8, v10, v0.t ; RV32-NEXT: vredand.vs v10, v8, v10, v0.t
; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v10, a1 ; RV32-NEXT: vsrl.vx v8, v10, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_or_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_or_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_or_v4i64: ; RV32-LABEL: vpreduce_or_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
; RV32-NEXT: vredor.vs v10, v8, v10, v0.t ; RV32-NEXT: vredor.vs v10, v8, v10, v0.t
; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v10, a1 ; RV32-NEXT: vsrl.vx v8, v10, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_xor_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_xor_v4i64(i64 signext %s, <4 x i64> %v, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_xor_v4i64: ; RV32-LABEL: vpreduce_xor_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
; RV32-NEXT: vredxor.vs v10, v8, v10, v0.t ; RV32-NEXT: vredxor.vs v10, v8, v10, v0.t
; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v10, a1 ; RV32-NEXT: vsrl.vx v8, v10, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 14 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll

Show First 20 Lines • Show All 4,462 Lines • ▼ Show 20 Lines
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: li a0, -1 ; RV32-NEXT: li a0, -1
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: lui a0, 524288
; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vredmin.vs v8, v8, v9 ; RV32-NEXT: vredmin.vs v8, v8, v9
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 24 Lines
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: li a0, -1 ; RV32-NEXT: li a0, -1
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: lui a0, 524288
; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vredmin.vs v8, v8, v10 ; RV32-NEXT: vredmin.vs v8, v8, v10
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 24 Lines
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: li a0, -1 ; RV32-NEXT: li a0, -1
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: lui a0, 524288
; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vredmin.vs v8, v8, v12 ; RV32-NEXT: vredmin.vs v8, v8, v12
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 24 Lines
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: li a0, -1 ; RV32-NEXT: li a0, -1
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: lui a0, 524288
; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vredmin.vs v8, v8, v16 ; RV32-NEXT: vredmin.vs v8, v8, v16
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 27 Lines
; RV32-NEXT: addi a0, a0, 128 ; RV32-NEXT: addi a0, a0, 128
; RV32-NEXT: vle64.v v16, (a0) ; RV32-NEXT: vle64.v v16, (a0)
; RV32-NEXT: li a0, -1 ; RV32-NEXT: li a0, -1
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: lui a0, 524288
; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: vmin.vv v8, v8, v16 ; RV32-NEXT: vmin.vv v8, v8, v16
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vredmin.vs v8, v8, v16 ; RV32-NEXT: vredmin.vs v8, v8, v16
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 35 Lines
; RV32-NEXT: li a0, -1 ; RV32-NEXT: li a0, -1
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: lui a0, 524288
; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: vmin.vv v24, v0, v24 ; RV32-NEXT: vmin.vv v24, v0, v24
; RV32-NEXT: vmin.vv v8, v8, v16 ; RV32-NEXT: vmin.vv v8, v8, v16
; RV32-NEXT: vmin.vv v8, v8, v24 ; RV32-NEXT: vmin.vv v8, v8, v24
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vredmin.vs v8, v8, v16 ; RV32-NEXT: vredmin.vs v8, v8, v16
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
▲ Show 20 Lines • Show All 490 Lines • ▼ Show 20 Lines
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: lui a0, 524288
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw zero, 8(sp) ; RV32-NEXT: sw zero, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vredmax.vs v8, v8, v9 ; RV32-NEXT: vredmax.vs v8, v8, v9
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 22 Lines
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: lui a0, 524288
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw zero, 8(sp) ; RV32-NEXT: sw zero, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vredmax.vs v8, v8, v10 ; RV32-NEXT: vredmax.vs v8, v8, v10
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 22 Lines
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: lui a0, 524288
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw zero, 8(sp) ; RV32-NEXT: sw zero, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vredmax.vs v8, v8, v12 ; RV32-NEXT: vredmax.vs v8, v8, v12
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 22 Lines
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: lui a0, 524288
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw zero, 8(sp) ; RV32-NEXT: sw zero, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vredmax.vs v8, v8, v16 ; RV32-NEXT: vredmax.vs v8, v8, v16
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 25 Lines
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: addi a0, a0, 128 ; RV32-NEXT: addi a0, a0, 128
; RV32-NEXT: vle64.v v16, (a0) ; RV32-NEXT: vle64.v v16, (a0)
; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: lui a0, 524288
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw zero, 8(sp) ; RV32-NEXT: sw zero, 8(sp)
; RV32-NEXT: vmax.vv v8, v8, v16 ; RV32-NEXT: vmax.vv v8, v8, v16
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vredmax.vs v8, v8, v16 ; RV32-NEXT: vredmax.vs v8, v8, v16
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 33 Lines
; RV32-NEXT: addi a0, a0, 128 ; RV32-NEXT: addi a0, a0, 128
; RV32-NEXT: vle64.v v0, (a0) ; RV32-NEXT: vle64.v v0, (a0)
; RV32-NEXT: lui a0, 524288 ; RV32-NEXT: lui a0, 524288
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw zero, 8(sp) ; RV32-NEXT: sw zero, 8(sp)
; RV32-NEXT: vmax.vv v24, v0, v24 ; RV32-NEXT: vmax.vv v24, v0, v24
; RV32-NEXT: vmax.vv v8, v8, v16 ; RV32-NEXT: vmax.vv v8, v8, v16
; RV32-NEXT: vmax.vv v8, v8, v24 ; RV32-NEXT: vmax.vv v8, v8, v24
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vredmax.vs v8, v8, v16 ; RV32-NEXT: vredmax.vs v8, v8, v16
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
▲ Show 20 Lines • Show All 2,142 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll

Show First 20 Lines • Show All 1,458 Lines • ▼ Show 20 Lines
define <8 x i1> @icmp_eq_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @icmp_eq_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_eq_vx_v8i64: ; RV32-LABEL: icmp_eq_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vmseq.vv v12, v8, v16, v0.t ; RV32-NEXT: vmseq.vv v12, v8, v16, v0.t
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_eq_vx_v8i64: ; RV64-LABEL: icmp_eq_vx_v8i64:
Show All 10 Lines
define <8 x i1> @icmp_eq_vx_swap_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @icmp_eq_vx_swap_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_eq_vx_swap_v8i64: ; RV32-LABEL: icmp_eq_vx_swap_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vmseq.vv v12, v16, v8, v0.t ; RV32-NEXT: vmseq.vv v12, v16, v8, v0.t
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_eq_vx_swap_v8i64: ; RV64-LABEL: icmp_eq_vx_swap_v8i64:
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define <8 x i1> @icmp_ne_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @icmp_ne_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_ne_vx_v8i64: ; RV32-LABEL: icmp_ne_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vmsne.vv v12, v8, v16, v0.t ; RV32-NEXT: vmsne.vv v12, v8, v16, v0.t
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ne_vx_v8i64: ; RV64-LABEL: icmp_ne_vx_v8i64:
Show All 10 Lines
define <8 x i1> @icmp_ne_vx_swap_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @icmp_ne_vx_swap_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_ne_vx_swap_v8i64: ; RV32-LABEL: icmp_ne_vx_swap_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vmsne.vv v12, v16, v8, v0.t ; RV32-NEXT: vmsne.vv v12, v16, v8, v0.t
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ne_vx_swap_v8i64: ; RV64-LABEL: icmp_ne_vx_swap_v8i64:
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define <8 x i1> @icmp_ugt_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @icmp_ugt_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_ugt_vx_v8i64: ; RV32-LABEL: icmp_ugt_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vmsltu.vv v12, v16, v8, v0.t ; RV32-NEXT: vmsltu.vv v12, v16, v8, v0.t
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ugt_vx_v8i64: ; RV64-LABEL: icmp_ugt_vx_v8i64:
Show All 10 Lines
define <8 x i1> @icmp_ugt_vx_swap_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @icmp_ugt_vx_swap_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_ugt_vx_swap_v8i64: ; RV32-LABEL: icmp_ugt_vx_swap_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vmsltu.vv v12, v8, v16, v0.t ; RV32-NEXT: vmsltu.vv v12, v8, v16, v0.t
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ugt_vx_swap_v8i64: ; RV64-LABEL: icmp_ugt_vx_swap_v8i64:
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define <8 x i1> @icmp_uge_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @icmp_uge_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_uge_vx_v8i64: ; RV32-LABEL: icmp_uge_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vmsleu.vv v12, v16, v8, v0.t ; RV32-NEXT: vmsleu.vv v12, v16, v8, v0.t
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_uge_vx_v8i64: ; RV64-LABEL: icmp_uge_vx_v8i64:
Show All 12 Lines
define <8 x i1> @icmp_uge_vx_swap_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @icmp_uge_vx_swap_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_uge_vx_swap_v8i64: ; RV32-LABEL: icmp_uge_vx_swap_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vmsleu.vv v12, v8, v16, v0.t ; RV32-NEXT: vmsleu.vv v12, v8, v16, v0.t
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_uge_vx_swap_v8i64: ; RV64-LABEL: icmp_uge_vx_swap_v8i64:
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define <8 x i1> @icmp_ult_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @icmp_ult_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_ult_vx_v8i64: ; RV32-LABEL: icmp_ult_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vmsltu.vv v12, v8, v16, v0.t ; RV32-NEXT: vmsltu.vv v12, v8, v16, v0.t
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ult_vx_v8i64: ; RV64-LABEL: icmp_ult_vx_v8i64:
Show All 10 Lines
define <8 x i1> @icmp_ult_vx_swap_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @icmp_ult_vx_swap_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_ult_vx_swap_v8i64: ; RV32-LABEL: icmp_ult_vx_swap_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vmsltu.vv v12, v16, v8, v0.t ; RV32-NEXT: vmsltu.vv v12, v16, v8, v0.t
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ult_vx_swap_v8i64: ; RV64-LABEL: icmp_ult_vx_swap_v8i64:
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define <8 x i1> @icmp_sgt_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @icmp_sgt_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_sgt_vx_v8i64: ; RV32-LABEL: icmp_sgt_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vmslt.vv v12, v16, v8, v0.t ; RV32-NEXT: vmslt.vv v12, v16, v8, v0.t
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sgt_vx_v8i64: ; RV64-LABEL: icmp_sgt_vx_v8i64:
Show All 10 Lines
define <8 x i1> @icmp_sgt_vx_swap_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @icmp_sgt_vx_swap_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_sgt_vx_swap_v8i64: ; RV32-LABEL: icmp_sgt_vx_swap_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vmslt.vv v12, v8, v16, v0.t ; RV32-NEXT: vmslt.vv v12, v8, v16, v0.t
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sgt_vx_swap_v8i64: ; RV64-LABEL: icmp_sgt_vx_swap_v8i64:
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define <8 x i1> @icmp_sge_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @icmp_sge_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_sge_vx_v8i64: ; RV32-LABEL: icmp_sge_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vmsle.vv v12, v16, v8, v0.t ; RV32-NEXT: vmsle.vv v12, v16, v8, v0.t
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sge_vx_v8i64: ; RV64-LABEL: icmp_sge_vx_v8i64:
Show All 12 Lines
define <8 x i1> @icmp_sge_vx_swap_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @icmp_sge_vx_swap_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_sge_vx_swap_v8i64: ; RV32-LABEL: icmp_sge_vx_swap_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vmsle.vv v12, v8, v16, v0.t ; RV32-NEXT: vmsle.vv v12, v8, v16, v0.t
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sge_vx_swap_v8i64: ; RV64-LABEL: icmp_sge_vx_swap_v8i64:
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define <8 x i1> @icmp_slt_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @icmp_slt_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_slt_vx_v8i64: ; RV32-LABEL: icmp_slt_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vmslt.vv v12, v8, v16, v0.t ; RV32-NEXT: vmslt.vv v12, v8, v16, v0.t
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_slt_vx_v8i64: ; RV64-LABEL: icmp_slt_vx_v8i64:
Show All 10 Lines
define <8 x i1> @icmp_slt_vx_swap_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @icmp_slt_vx_swap_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_slt_vx_swap_v8i64: ; RV32-LABEL: icmp_slt_vx_swap_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vmslt.vv v12, v16, v8, v0.t ; RV32-NEXT: vmslt.vv v12, v16, v8, v0.t
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_slt_vx_swap_v8i64: ; RV64-LABEL: icmp_slt_vx_swap_v8i64:
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define <8 x i1> @icmp_sle_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @icmp_sle_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_sle_vx_v8i64: ; RV32-LABEL: icmp_sle_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vmsle.vv v12, v8, v16, v0.t ; RV32-NEXT: vmsle.vv v12, v8, v16, v0.t
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sle_vx_v8i64: ; RV64-LABEL: icmp_sle_vx_v8i64:
Show All 10 Lines
define <8 x i1> @icmp_sle_vx_swap_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @icmp_sle_vx_swap_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_sle_vx_swap_v8i64: ; RV32-LABEL: icmp_sle_vx_swap_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; RV32-NEXT: vmsle.vv v12, v16, v8, v0.t ; RV32-NEXT: vmsle.vv v12, v16, v8, v0.t
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sle_vx_swap_v8i64: ; RV64-LABEL: icmp_sle_vx_swap_v8i64:
Show All 38 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll

Show First 20 Lines • Show All 1,134 Lines • ▼ Show 20 Lines
define <2 x i64> @vadd_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) { define <2 x i64> @vadd_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vadd_vx_v2i64: ; RV32-LABEL: vadd_vx_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vadd.vv v8, v8, v9, v0.t ; RV32-NEXT: vadd.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_v2i64: ; RV64-LABEL: vadd_vx_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vadd.vx v8, v8, a0, v0.t ; RV64-NEXT: vadd.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
%v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v ret <2 x i64> %v
} }
define <2 x i64> @vadd_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) { define <2 x i64> @vadd_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vadd_vx_v2i64_unmasked: ; RV32-LABEL: vadd_vx_v2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vadd.vv v8, v8, v9 ; RV32-NEXT: vadd.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_v2i64_unmasked: ; RV64-LABEL: vadd_vx_v2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
define <4 x i64> @vadd_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) { define <4 x i64> @vadd_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vadd_vx_v4i64: ; RV32-LABEL: vadd_vx_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vadd.vv v8, v8, v10, v0.t ; RV32-NEXT: vadd.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_v4i64: ; RV64-LABEL: vadd_vx_v4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vadd.vx v8, v8, a0, v0.t ; RV64-NEXT: vadd.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
%v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) %v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v ret <4 x i64> %v
} }
define <4 x i64> @vadd_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) { define <4 x i64> @vadd_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vadd_vx_v4i64_unmasked: ; RV32-LABEL: vadd_vx_v4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vadd.vv v8, v8, v10 ; RV32-NEXT: vadd.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_v4i64_unmasked: ; RV64-LABEL: vadd_vx_v4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
define <8 x i64> @vadd_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vadd_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vadd_vx_v8i64: ; RV32-LABEL: vadd_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vadd.vv v8, v8, v12, v0.t ; RV32-NEXT: vadd.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_v8i64: ; RV64-LABEL: vadd_vx_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vadd.vx v8, v8, a0, v0.t ; RV64-NEXT: vadd.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
%v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) %v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
define <8 x i64> @vadd_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) { define <8 x i64> @vadd_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vadd_vx_v8i64_unmasked: ; RV32-LABEL: vadd_vx_v8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vadd.vv v8, v8, v12 ; RV32-NEXT: vadd.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_v8i64_unmasked: ; RV64-LABEL: vadd_vx_v8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
define <16 x i64> @vadd_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vadd_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vadd_vx_v16i64: ; RV32-LABEL: vadd_vx_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t ; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_v16i64: ; RV64-LABEL: vadd_vx_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vadd.vx v8, v8, a0, v0.t ; RV64-NEXT: vadd.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
%vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
%v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) %v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
define <16 x i64> @vadd_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) { define <16 x i64> @vadd_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vadd_vx_v16i64_unmasked: ; RV32-LABEL: vadd_vx_v16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vadd.vv v8, v8, v16 ; RV32-NEXT: vadd.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_v16i64_unmasked: ; RV64-LABEL: vadd_vx_v16i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 198 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll

Show First 20 Lines • Show All 979 Lines • ▼ Show 20 Lines
define <2 x i64> @vand_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) { define <2 x i64> @vand_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vand_vx_v2i64: ; RV32-LABEL: vand_vx_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vand.vv v8, v8, v9, v0.t ; RV32-NEXT: vand.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vand_vx_v2i64: ; RV64-LABEL: vand_vx_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
%v = call <2 x i64> @llvm.vp.and.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) %v = call <2 x i64> @llvm.vp.and.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v ret <2 x i64> %v
} }
define <2 x i64> @vand_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) { define <2 x i64> @vand_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vand_vx_v2i64_unmasked: ; RV32-LABEL: vand_vx_v2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vand.vv v8, v8, v9 ; RV32-NEXT: vand.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vand_vx_v2i64_unmasked: ; RV64-LABEL: vand_vx_v2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
define <4 x i64> @vand_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) { define <4 x i64> @vand_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vand_vx_v4i64: ; RV32-LABEL: vand_vx_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vand.vv v8, v8, v10, v0.t ; RV32-NEXT: vand.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vand_vx_v4i64: ; RV64-LABEL: vand_vx_v4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
%v = call <4 x i64> @llvm.vp.and.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) %v = call <4 x i64> @llvm.vp.and.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v ret <4 x i64> %v
} }
define <4 x i64> @vand_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) { define <4 x i64> @vand_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vand_vx_v4i64_unmasked: ; RV32-LABEL: vand_vx_v4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vand_vx_v4i64_unmasked: ; RV64-LABEL: vand_vx_v4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
define <8 x i64> @vand_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vand_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vand_vx_v8i64: ; RV32-LABEL: vand_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vand.vv v8, v8, v12, v0.t ; RV32-NEXT: vand.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vand_vx_v8i64: ; RV64-LABEL: vand_vx_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
%v = call <8 x i64> @llvm.vp.and.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) %v = call <8 x i64> @llvm.vp.and.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
define <8 x i64> @vand_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) { define <8 x i64> @vand_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vand_vx_v8i64_unmasked: ; RV32-LABEL: vand_vx_v8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vand_vx_v8i64_unmasked: ; RV64-LABEL: vand_vx_v8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 168 Lines • ▼ Show 20 Lines
define <16 x i64> @vand_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vand_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vand_vx_v16i64: ; RV32-LABEL: vand_vx_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vand_vx_v16i64: ; RV64-LABEL: vand_vx_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
%vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
%v = call <16 x i64> @llvm.vp.and.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) %v = call <16 x i64> @llvm.vp.and.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
define <16 x i64> @vand_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) { define <16 x i64> @vand_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vand_vx_v16i64_unmasked: ; RV32-LABEL: vand_vx_v16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vand_vx_v16i64_unmasked: ; RV64-LABEL: vand_vx_v16i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 36 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll

Show First 20 Lines • Show All 658 Lines • ▼ Show 20 Lines
define <2 x i64> @vdiv_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) { define <2 x i64> @vdiv_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vdiv_vx_v2i64: ; RV32-LABEL: vdiv_vx_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vdiv.vv v8, v8, v9, v0.t ; RV32-NEXT: vdiv.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdiv_vx_v2i64: ; RV64-LABEL: vdiv_vx_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vdiv.vx v8, v8, a0, v0.t ; RV64-NEXT: vdiv.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
%v = call <2 x i64> @llvm.vp.sdiv.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) %v = call <2 x i64> @llvm.vp.sdiv.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v ret <2 x i64> %v
} }
define <2 x i64> @vdiv_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) { define <2 x i64> @vdiv_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vdiv_vx_v2i64_unmasked: ; RV32-LABEL: vdiv_vx_v2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vdiv.vv v8, v8, v9 ; RV32-NEXT: vdiv.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdiv_vx_v2i64_unmasked: ; RV64-LABEL: vdiv_vx_v2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <4 x i64> @vdiv_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) { define <4 x i64> @vdiv_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vdiv_vx_v4i64: ; RV32-LABEL: vdiv_vx_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vdiv.vv v8, v8, v10, v0.t ; RV32-NEXT: vdiv.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdiv_vx_v4i64: ; RV64-LABEL: vdiv_vx_v4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vdiv.vx v8, v8, a0, v0.t ; RV64-NEXT: vdiv.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
%v = call <4 x i64> @llvm.vp.sdiv.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) %v = call <4 x i64> @llvm.vp.sdiv.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v ret <4 x i64> %v
} }
define <4 x i64> @vdiv_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) { define <4 x i64> @vdiv_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vdiv_vx_v4i64_unmasked: ; RV32-LABEL: vdiv_vx_v4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vdiv.vv v8, v8, v10 ; RV32-NEXT: vdiv.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdiv_vx_v4i64_unmasked: ; RV64-LABEL: vdiv_vx_v4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <8 x i64> @vdiv_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vdiv_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vdiv_vx_v8i64: ; RV32-LABEL: vdiv_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vdiv.vv v8, v8, v12, v0.t ; RV32-NEXT: vdiv.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdiv_vx_v8i64: ; RV64-LABEL: vdiv_vx_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vdiv.vx v8, v8, a0, v0.t ; RV64-NEXT: vdiv.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
%v = call <8 x i64> @llvm.vp.sdiv.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) %v = call <8 x i64> @llvm.vp.sdiv.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
define <8 x i64> @vdiv_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) { define <8 x i64> @vdiv_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vdiv_vx_v8i64_unmasked: ; RV32-LABEL: vdiv_vx_v8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vdiv.vv v8, v8, v12 ; RV32-NEXT: vdiv.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdiv_vx_v8i64_unmasked: ; RV64-LABEL: vdiv_vx_v8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <16 x i64> @vdiv_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vdiv_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vdiv_vx_v16i64: ; RV32-LABEL: vdiv_vx_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vdiv.vv v8, v8, v16, v0.t ; RV32-NEXT: vdiv.vv v8, v8, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdiv_vx_v16i64: ; RV64-LABEL: vdiv_vx_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vdiv.vx v8, v8, a0, v0.t ; RV64-NEXT: vdiv.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
%vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
%v = call <16 x i64> @llvm.vp.sdiv.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) %v = call <16 x i64> @llvm.vp.sdiv.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
define <16 x i64> @vdiv_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) { define <16 x i64> @vdiv_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vdiv_vx_v16i64_unmasked: ; RV32-LABEL: vdiv_vx_v16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vdiv.vv v8, v8, v16 ; RV32-NEXT: vdiv.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdiv_vx_v16i64_unmasked: ; RV64-LABEL: vdiv_vx_v16i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 10 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll

Show First 20 Lines • Show All 657 Lines • ▼ Show 20 Lines
define <2 x i64> @vdivu_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) { define <2 x i64> @vdivu_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vdivu_vx_v2i64: ; RV32-LABEL: vdivu_vx_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vdivu.vv v8, v8, v9, v0.t ; RV32-NEXT: vdivu.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdivu_vx_v2i64: ; RV64-LABEL: vdivu_vx_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vdivu.vx v8, v8, a0, v0.t ; RV64-NEXT: vdivu.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
%v = call <2 x i64> @llvm.vp.udiv.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) %v = call <2 x i64> @llvm.vp.udiv.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v ret <2 x i64> %v
} }
define <2 x i64> @vdivu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) { define <2 x i64> @vdivu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vdivu_vx_v2i64_unmasked: ; RV32-LABEL: vdivu_vx_v2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vdivu.vv v8, v8, v9 ; RV32-NEXT: vdivu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdivu_vx_v2i64_unmasked: ; RV64-LABEL: vdivu_vx_v2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <4 x i64> @vdivu_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) { define <4 x i64> @vdivu_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vdivu_vx_v4i64: ; RV32-LABEL: vdivu_vx_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vdivu.vv v8, v8, v10, v0.t ; RV32-NEXT: vdivu.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdivu_vx_v4i64: ; RV64-LABEL: vdivu_vx_v4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vdivu.vx v8, v8, a0, v0.t ; RV64-NEXT: vdivu.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
%v = call <4 x i64> @llvm.vp.udiv.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) %v = call <4 x i64> @llvm.vp.udiv.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v ret <4 x i64> %v
} }
define <4 x i64> @vdivu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) { define <4 x i64> @vdivu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vdivu_vx_v4i64_unmasked: ; RV32-LABEL: vdivu_vx_v4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vdivu.vv v8, v8, v10 ; RV32-NEXT: vdivu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdivu_vx_v4i64_unmasked: ; RV64-LABEL: vdivu_vx_v4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <8 x i64> @vdivu_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vdivu_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vdivu_vx_v8i64: ; RV32-LABEL: vdivu_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vdivu.vv v8, v8, v12, v0.t ; RV32-NEXT: vdivu.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdivu_vx_v8i64: ; RV64-LABEL: vdivu_vx_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vdivu.vx v8, v8, a0, v0.t ; RV64-NEXT: vdivu.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
%v = call <8 x i64> @llvm.vp.udiv.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) %v = call <8 x i64> @llvm.vp.udiv.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
define <8 x i64> @vdivu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) { define <8 x i64> @vdivu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vdivu_vx_v8i64_unmasked: ; RV32-LABEL: vdivu_vx_v8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vdivu.vv v8, v8, v12 ; RV32-NEXT: vdivu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdivu_vx_v8i64_unmasked: ; RV64-LABEL: vdivu_vx_v8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <16 x i64> @vdivu_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vdivu_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vdivu_vx_v16i64: ; RV32-LABEL: vdivu_vx_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vdivu.vv v8, v8, v16, v0.t ; RV32-NEXT: vdivu.vv v8, v8, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdivu_vx_v16i64: ; RV64-LABEL: vdivu_vx_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vdivu.vx v8, v8, a0, v0.t ; RV64-NEXT: vdivu.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
%vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
%v = call <16 x i64> @llvm.vp.udiv.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) %v = call <16 x i64> @llvm.vp.udiv.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
define <16 x i64> @vdivu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) { define <16 x i64> @vdivu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vdivu_vx_v16i64_unmasked: ; RV32-LABEL: vdivu_vx_v16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vdivu.vv v8, v8, v16 ; RV32-NEXT: vdivu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdivu_vx_v16i64_unmasked: ; RV64-LABEL: vdivu_vx_v16i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 10 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll

Show First 20 Lines • Show All 703 Lines • ▼ Show 20 Lines
define <2 x i64> @vmul_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) { define <2 x i64> @vmul_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vmul_vx_v2i64: ; RV32-LABEL: vmul_vx_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vmul.vv v8, v8, v9, v0.t ; RV32-NEXT: vmul.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmul_vx_v2i64: ; RV64-LABEL: vmul_vx_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
%v = call <2 x i64> @llvm.vp.mul.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) %v = call <2 x i64> @llvm.vp.mul.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v ret <2 x i64> %v
} }
define <2 x i64> @vmul_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) { define <2 x i64> @vmul_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vmul_vx_v2i64_unmasked: ; RV32-LABEL: vmul_vx_v2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vmul.vv v8, v8, v9 ; RV32-NEXT: vmul.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmul_vx_v2i64_unmasked: ; RV64-LABEL: vmul_vx_v2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <4 x i64> @vmul_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) { define <4 x i64> @vmul_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vmul_vx_v4i64: ; RV32-LABEL: vmul_vx_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vmul.vv v8, v8, v10, v0.t ; RV32-NEXT: vmul.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmul_vx_v4i64: ; RV64-LABEL: vmul_vx_v4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
%v = call <4 x i64> @llvm.vp.mul.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) %v = call <4 x i64> @llvm.vp.mul.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v ret <4 x i64> %v
} }
define <4 x i64> @vmul_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) { define <4 x i64> @vmul_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vmul_vx_v4i64_unmasked: ; RV32-LABEL: vmul_vx_v4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vmul.vv v8, v8, v10 ; RV32-NEXT: vmul.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmul_vx_v4i64_unmasked: ; RV64-LABEL: vmul_vx_v4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <8 x i64> @vmul_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vmul_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vmul_vx_v8i64: ; RV32-LABEL: vmul_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vmul.vv v8, v8, v12, v0.t ; RV32-NEXT: vmul.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmul_vx_v8i64: ; RV64-LABEL: vmul_vx_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
%v = call <8 x i64> @llvm.vp.mul.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) %v = call <8 x i64> @llvm.vp.mul.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
define <8 x i64> @vmul_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) { define <8 x i64> @vmul_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vmul_vx_v8i64_unmasked: ; RV32-LABEL: vmul_vx_v8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vmul.vv v8, v8, v12 ; RV32-NEXT: vmul.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmul_vx_v8i64_unmasked: ; RV64-LABEL: vmul_vx_v8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <16 x i64> @vmul_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vmul_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vmul_vx_v16i64: ; RV32-LABEL: vmul_vx_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vmul.vv v8, v8, v16, v0.t ; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmul_vx_v16i64: ; RV64-LABEL: vmul_vx_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
%vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
%v = call <16 x i64> @llvm.vp.mul.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) %v = call <16 x i64> @llvm.vp.mul.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
define <16 x i64> @vmul_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) { define <16 x i64> @vmul_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vmul_vx_v16i64_unmasked: ; RV32-LABEL: vmul_vx_v16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vmul.vv v8, v8, v16 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmul_vx_v16i64_unmasked: ; RV64-LABEL: vmul_vx_v16i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 10 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll

Show First 20 Lines • Show All 1,041 Lines • ▼ Show 20 Lines
define <2 x i64> @vor_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) { define <2 x i64> @vor_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vor_vx_v2i64: ; RV32-LABEL: vor_vx_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vor.vv v8, v8, v9, v0.t ; RV32-NEXT: vor.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vor_vx_v2i64: ; RV64-LABEL: vor_vx_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vor.vx v8, v8, a0, v0.t ; RV64-NEXT: vor.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
%v = call <2 x i64> @llvm.vp.or.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) %v = call <2 x i64> @llvm.vp.or.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v ret <2 x i64> %v
} }
define <2 x i64> @vor_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) { define <2 x i64> @vor_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vor_vx_v2i64_unmasked: ; RV32-LABEL: vor_vx_v2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vor_vx_v2i64_unmasked: ; RV64-LABEL: vor_vx_v2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
define <4 x i64> @vor_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) { define <4 x i64> @vor_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vor_vx_v4i64: ; RV32-LABEL: vor_vx_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vor.vv v8, v8, v10, v0.t ; RV32-NEXT: vor.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vor_vx_v4i64: ; RV64-LABEL: vor_vx_v4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vor.vx v8, v8, a0, v0.t ; RV64-NEXT: vor.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
%v = call <4 x i64> @llvm.vp.or.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) %v = call <4 x i64> @llvm.vp.or.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v ret <4 x i64> %v
} }
define <4 x i64> @vor_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) { define <4 x i64> @vor_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vor_vx_v4i64_unmasked: ; RV32-LABEL: vor_vx_v4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vor_vx_v4i64_unmasked: ; RV64-LABEL: vor_vx_v4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
define <8 x i64> @vor_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vor_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vor_vx_v8i64: ; RV32-LABEL: vor_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vor.vv v8, v8, v12, v0.t ; RV32-NEXT: vor.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vor_vx_v8i64: ; RV64-LABEL: vor_vx_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vor.vx v8, v8, a0, v0.t ; RV64-NEXT: vor.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
%v = call <8 x i64> @llvm.vp.or.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) %v = call <8 x i64> @llvm.vp.or.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
define <8 x i64> @vor_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) { define <8 x i64> @vor_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vor_vx_v8i64_unmasked: ; RV32-LABEL: vor_vx_v8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vor_vx_v8i64_unmasked: ; RV64-LABEL: vor_vx_v8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
define <16 x i64> @vor_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vor_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vor_vx_v16i64: ; RV32-LABEL: vor_vx_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vor.vv v8, v8, v16, v0.t ; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vor_vx_v16i64: ; RV64-LABEL: vor_vx_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vor.vx v8, v8, a0, v0.t ; RV64-NEXT: vor.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
%vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
%v = call <16 x i64> @llvm.vp.or.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) %v = call <16 x i64> @llvm.vp.or.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
define <16 x i64> @vor_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) { define <16 x i64> @vor_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vor_vx_v16i64_unmasked: ; RV32-LABEL: vor_vx_v16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vor_vx_v16i64_unmasked: ; RV64-LABEL: vor_vx_v16i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 36 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll

Show First 20 Lines • Show All 564 Lines • ▼ Show 20 Lines
define <2 x i64> @vpmerge_vx_v2i64(i64 %a, <2 x i64> %vb, <2 x i1> %m, i32 zeroext %evl) { define <2 x i64> @vpmerge_vx_v2i64(i64 %a, <2 x i64> %vb, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpmerge_vx_v2i64: ; RV32-LABEL: vpmerge_vx_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
; RV32-NEXT: vmerge.vvm v8, v8, v9, v0 ; RV32-NEXT: vmerge.vvm v8, v8, v9, v0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpmerge_vx_v2i64: ; RV64-LABEL: vpmerge_vx_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 33 Lines
define <4 x i64> @vpmerge_vx_v4i64(i64 %a, <4 x i64> %vb, <4 x i1> %m, i32 zeroext %evl) { define <4 x i64> @vpmerge_vx_v4i64(i64 %a, <4 x i64> %vb, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpmerge_vx_v4i64: ; RV32-LABEL: vpmerge_vx_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
; RV32-NEXT: vmerge.vvm v8, v8, v10, v0 ; RV32-NEXT: vmerge.vvm v8, v8, v10, v0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpmerge_vx_v4i64: ; RV64-LABEL: vpmerge_vx_v4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 33 Lines
define <8 x i64> @vpmerge_vx_v8i64(i64 %a, <8 x i64> %vb, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vpmerge_vx_v8i64(i64 %a, <8 x i64> %vb, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpmerge_vx_v8i64: ; RV32-LABEL: vpmerge_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu
; RV32-NEXT: vmerge.vvm v8, v8, v12, v0 ; RV32-NEXT: vmerge.vvm v8, v8, v12, v0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpmerge_vx_v8i64: ; RV64-LABEL: vpmerge_vx_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 33 Lines
define <16 x i64> @vpmerge_vx_v16i64(i64 %a, <16 x i64> %vb, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vpmerge_vx_v16i64(i64 %a, <16 x i64> %vb, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpmerge_vx_v16i64: ; RV32-LABEL: vpmerge_vx_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, tu, mu
; RV32-NEXT: vmerge.vvm v8, v8, v16, v0 ; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpmerge_vx_v16i64: ; RV64-LABEL: vpmerge_vx_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 468 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll

Show First 20 Lines • Show All 658 Lines • ▼ Show 20 Lines
define <2 x i64> @vrem_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) { define <2 x i64> @vrem_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vrem_vx_v2i64: ; RV32-LABEL: vrem_vx_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vrem.vv v8, v8, v9, v0.t ; RV32-NEXT: vrem.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrem_vx_v2i64: ; RV64-LABEL: vrem_vx_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vrem.vx v8, v8, a0, v0.t ; RV64-NEXT: vrem.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
%v = call <2 x i64> @llvm.vp.srem.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) %v = call <2 x i64> @llvm.vp.srem.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v ret <2 x i64> %v
} }
define <2 x i64> @vrem_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) { define <2 x i64> @vrem_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vrem_vx_v2i64_unmasked: ; RV32-LABEL: vrem_vx_v2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vrem.vv v8, v8, v9 ; RV32-NEXT: vrem.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrem_vx_v2i64_unmasked: ; RV64-LABEL: vrem_vx_v2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <4 x i64> @vrem_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) { define <4 x i64> @vrem_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vrem_vx_v4i64: ; RV32-LABEL: vrem_vx_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vrem.vv v8, v8, v10, v0.t ; RV32-NEXT: vrem.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrem_vx_v4i64: ; RV64-LABEL: vrem_vx_v4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vrem.vx v8, v8, a0, v0.t ; RV64-NEXT: vrem.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
%v = call <4 x i64> @llvm.vp.srem.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) %v = call <4 x i64> @llvm.vp.srem.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v ret <4 x i64> %v
} }
define <4 x i64> @vrem_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) { define <4 x i64> @vrem_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vrem_vx_v4i64_unmasked: ; RV32-LABEL: vrem_vx_v4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vrem.vv v8, v8, v10 ; RV32-NEXT: vrem.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrem_vx_v4i64_unmasked: ; RV64-LABEL: vrem_vx_v4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <8 x i64> @vrem_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vrem_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vrem_vx_v8i64: ; RV32-LABEL: vrem_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vrem.vv v8, v8, v12, v0.t ; RV32-NEXT: vrem.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrem_vx_v8i64: ; RV64-LABEL: vrem_vx_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vrem.vx v8, v8, a0, v0.t ; RV64-NEXT: vrem.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
%v = call <8 x i64> @llvm.vp.srem.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) %v = call <8 x i64> @llvm.vp.srem.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
define <8 x i64> @vrem_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) { define <8 x i64> @vrem_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vrem_vx_v8i64_unmasked: ; RV32-LABEL: vrem_vx_v8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vrem.vv v8, v8, v12 ; RV32-NEXT: vrem.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrem_vx_v8i64_unmasked: ; RV64-LABEL: vrem_vx_v8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <16 x i64> @vrem_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vrem_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vrem_vx_v16i64: ; RV32-LABEL: vrem_vx_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vrem.vv v8, v8, v16, v0.t ; RV32-NEXT: vrem.vv v8, v8, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrem_vx_v16i64: ; RV64-LABEL: vrem_vx_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vrem.vx v8, v8, a0, v0.t ; RV64-NEXT: vrem.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
%vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
%v = call <16 x i64> @llvm.vp.srem.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) %v = call <16 x i64> @llvm.vp.srem.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
define <16 x i64> @vrem_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) { define <16 x i64> @vrem_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vrem_vx_v16i64_unmasked: ; RV32-LABEL: vrem_vx_v16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vrem.vv v8, v8, v16 ; RV32-NEXT: vrem.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrem_vx_v16i64_unmasked: ; RV64-LABEL: vrem_vx_v16i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 10 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll

Show First 20 Lines • Show All 657 Lines • ▼ Show 20 Lines
define <2 x i64> @vremu_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) { define <2 x i64> @vremu_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vremu_vx_v2i64: ; RV32-LABEL: vremu_vx_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vremu.vv v8, v8, v9, v0.t ; RV32-NEXT: vremu.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vremu_vx_v2i64: ; RV64-LABEL: vremu_vx_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vremu.vx v8, v8, a0, v0.t ; RV64-NEXT: vremu.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
%v = call <2 x i64> @llvm.vp.urem.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) %v = call <2 x i64> @llvm.vp.urem.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v ret <2 x i64> %v
} }
define <2 x i64> @vremu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) { define <2 x i64> @vremu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vremu_vx_v2i64_unmasked: ; RV32-LABEL: vremu_vx_v2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vremu.vv v8, v8, v9 ; RV32-NEXT: vremu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vremu_vx_v2i64_unmasked: ; RV64-LABEL: vremu_vx_v2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <4 x i64> @vremu_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) { define <4 x i64> @vremu_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vremu_vx_v4i64: ; RV32-LABEL: vremu_vx_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vremu.vv v8, v8, v10, v0.t ; RV32-NEXT: vremu.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vremu_vx_v4i64: ; RV64-LABEL: vremu_vx_v4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vremu.vx v8, v8, a0, v0.t ; RV64-NEXT: vremu.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
%v = call <4 x i64> @llvm.vp.urem.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) %v = call <4 x i64> @llvm.vp.urem.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v ret <4 x i64> %v
} }
define <4 x i64> @vremu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) { define <4 x i64> @vremu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vremu_vx_v4i64_unmasked: ; RV32-LABEL: vremu_vx_v4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vremu.vv v8, v8, v10 ; RV32-NEXT: vremu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vremu_vx_v4i64_unmasked: ; RV64-LABEL: vremu_vx_v4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <8 x i64> @vremu_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vremu_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vremu_vx_v8i64: ; RV32-LABEL: vremu_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vremu.vv v8, v8, v12, v0.t ; RV32-NEXT: vremu.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vremu_vx_v8i64: ; RV64-LABEL: vremu_vx_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vremu.vx v8, v8, a0, v0.t ; RV64-NEXT: vremu.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
%v = call <8 x i64> @llvm.vp.urem.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) %v = call <8 x i64> @llvm.vp.urem.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
define <8 x i64> @vremu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) { define <8 x i64> @vremu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vremu_vx_v8i64_unmasked: ; RV32-LABEL: vremu_vx_v8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vremu.vv v8, v8, v12 ; RV32-NEXT: vremu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vremu_vx_v8i64_unmasked: ; RV64-LABEL: vremu_vx_v8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <16 x i64> @vremu_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vremu_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vremu_vx_v16i64: ; RV32-LABEL: vremu_vx_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vremu.vv v8, v8, v16, v0.t ; RV32-NEXT: vremu.vv v8, v8, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vremu_vx_v16i64: ; RV64-LABEL: vremu_vx_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vremu.vx v8, v8, a0, v0.t ; RV64-NEXT: vremu.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
%vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
%v = call <16 x i64> @llvm.vp.urem.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) %v = call <16 x i64> @llvm.vp.urem.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
define <16 x i64> @vremu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) { define <16 x i64> @vremu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vremu_vx_v16i64_unmasked: ; RV32-LABEL: vremu_vx_v16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vremu.vv v8, v8, v16 ; RV32-NEXT: vremu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vremu_vx_v16i64_unmasked: ; RV64-LABEL: vremu_vx_v16i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 10 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll

Show First 20 Lines • Show All 655 Lines • ▼ Show 20 Lines
define <2 x i64> @vrsub_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) { define <2 x i64> @vrsub_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vrsub_vx_v2i64: ; RV32-LABEL: vrsub_vx_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vsub.vv v8, v9, v8, v0.t ; RV32-NEXT: vsub.vv v8, v9, v8, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrsub_vx_v2i64: ; RV64-LABEL: vrsub_vx_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vrsub.vx v8, v8, a0, v0.t ; RV64-NEXT: vrsub.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
%v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %vb, <2 x i64> %va, <2 x i1> %m, i32 %evl) %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %vb, <2 x i64> %va, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v ret <2 x i64> %v
} }
define <2 x i64> @vrsub_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) { define <2 x i64> @vrsub_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vrsub_vx_v2i64_unmasked: ; RV32-LABEL: vrsub_vx_v2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vsub.vv v8, v9, v8 ; RV32-NEXT: vsub.vv v8, v9, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrsub_vx_v2i64_unmasked: ; RV64-LABEL: vrsub_vx_v2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 38 Lines
define <4 x i64> @vrsub_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) { define <4 x i64> @vrsub_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vrsub_vx_v4i64: ; RV32-LABEL: vrsub_vx_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vsub.vv v8, v10, v8, v0.t ; RV32-NEXT: vsub.vv v8, v10, v8, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrsub_vx_v4i64: ; RV64-LABEL: vrsub_vx_v4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vrsub.vx v8, v8, a0, v0.t ; RV64-NEXT: vrsub.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
%v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %vb, <4 x i64> %va, <4 x i1> %m, i32 %evl) %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %vb, <4 x i64> %va, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v ret <4 x i64> %v
} }
define <4 x i64> @vrsub_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) { define <4 x i64> @vrsub_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vrsub_vx_v4i64_unmasked: ; RV32-LABEL: vrsub_vx_v4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vsub.vv v8, v10, v8 ; RV32-NEXT: vsub.vv v8, v10, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrsub_vx_v4i64_unmasked: ; RV64-LABEL: vrsub_vx_v4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 38 Lines
define <8 x i64> @vrsub_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vrsub_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vrsub_vx_v8i64: ; RV32-LABEL: vrsub_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vsub.vv v8, v12, v8, v0.t ; RV32-NEXT: vsub.vv v8, v12, v8, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrsub_vx_v8i64: ; RV64-LABEL: vrsub_vx_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vrsub.vx v8, v8, a0, v0.t ; RV64-NEXT: vrsub.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
%v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %vb, <8 x i64> %va, <8 x i1> %m, i32 %evl) %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %vb, <8 x i64> %va, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
define <8 x i64> @vrsub_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) { define <8 x i64> @vrsub_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vrsub_vx_v8i64_unmasked: ; RV32-LABEL: vrsub_vx_v8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vsub.vv v8, v12, v8 ; RV32-NEXT: vsub.vv v8, v12, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrsub_vx_v8i64_unmasked: ; RV64-LABEL: vrsub_vx_v8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 38 Lines
define <16 x i64> @vrsub_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vrsub_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vrsub_vx_v16i64: ; RV32-LABEL: vrsub_vx_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vsub.vv v8, v16, v8, v0.t ; RV32-NEXT: vsub.vv v8, v16, v8, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrsub_vx_v16i64: ; RV64-LABEL: vrsub_vx_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vrsub.vx v8, v8, a0, v0.t ; RV64-NEXT: vrsub.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
%vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
%v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %vb, <16 x i64> %va, <16 x i1> %m, i32 %evl) %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %vb, <16 x i64> %va, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
define <16 x i64> @vrsub_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) { define <16 x i64> @vrsub_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vrsub_vx_v16i64_unmasked: ; RV32-LABEL: vrsub_vx_v16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vsub.vv v8, v16, v8 ; RV32-NEXT: vsub.vv v8, v16, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrsub_vx_v16i64_unmasked: ; RV64-LABEL: vrsub_vx_v16i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 36 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll

Show First 20 Lines • Show All 449 Lines • ▼ Show 20 Lines
define <2 x i64> @sadd_v2i64_vx(<2 x i64> %va, i64 %b) { define <2 x i64> @sadd_v2i64_vx(<2 x i64> %va, i64 %b) {
; RV32-LABEL: sadd_v2i64_vx: ; RV32-LABEL: sadd_v2i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsadd.vv v8, v8, v9 ; RV32-NEXT: vsadd.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: sadd_v2i64_vx: ; RV64-LABEL: sadd_v2i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
Show All 31 Lines
define <4 x i64> @sadd_v4i64_vx(<4 x i64> %va, i64 %b) { define <4 x i64> @sadd_v4i64_vx(<4 x i64> %va, i64 %b) {
; RV32-LABEL: sadd_v4i64_vx: ; RV32-LABEL: sadd_v4i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsadd.vv v8, v8, v10 ; RV32-NEXT: vsadd.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: sadd_v4i64_vx: ; RV64-LABEL: sadd_v4i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
Show All 31 Lines
define <8 x i64> @sadd_v8i64_vx(<8 x i64> %va, i64 %b) { define <8 x i64> @sadd_v8i64_vx(<8 x i64> %va, i64 %b) {
; RV32-LABEL: sadd_v8i64_vx: ; RV32-LABEL: sadd_v8i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsadd.vv v8, v8, v12 ; RV32-NEXT: vsadd.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: sadd_v8i64_vx: ; RV64-LABEL: sadd_v8i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
Show All 31 Lines
define <16 x i64> @sadd_v16i64_vx(<16 x i64> %va, i64 %b) { define <16 x i64> @sadd_v16i64_vx(<16 x i64> %va, i64 %b) {
; RV32-LABEL: sadd_v16i64_vx: ; RV32-LABEL: sadd_v16i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsadd.vv v8, v8, v16 ; RV32-NEXT: vsadd.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: sadd_v16i64_vx: ; RV64-LABEL: sadd_v16i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
Show All 19 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll

Show First 20 Lines • Show All 449 Lines • ▼ Show 20 Lines
define <2 x i64> @uadd_v2i64_vx(<2 x i64> %va, i64 %b) { define <2 x i64> @uadd_v2i64_vx(<2 x i64> %va, i64 %b) {
; RV32-LABEL: uadd_v2i64_vx: ; RV32-LABEL: uadd_v2i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsaddu.vv v8, v8, v9 ; RV32-NEXT: vsaddu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: uadd_v2i64_vx: ; RV64-LABEL: uadd_v2i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
Show All 31 Lines
define <4 x i64> @uadd_v4i64_vx(<4 x i64> %va, i64 %b) { define <4 x i64> @uadd_v4i64_vx(<4 x i64> %va, i64 %b) {
; RV32-LABEL: uadd_v4i64_vx: ; RV32-LABEL: uadd_v4i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsaddu.vv v8, v8, v10 ; RV32-NEXT: vsaddu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: uadd_v4i64_vx: ; RV64-LABEL: uadd_v4i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
Show All 31 Lines
define <8 x i64> @uadd_v8i64_vx(<8 x i64> %va, i64 %b) { define <8 x i64> @uadd_v8i64_vx(<8 x i64> %va, i64 %b) {
; RV32-LABEL: uadd_v8i64_vx: ; RV32-LABEL: uadd_v8i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsaddu.vv v8, v8, v12 ; RV32-NEXT: vsaddu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: uadd_v8i64_vx: ; RV64-LABEL: uadd_v8i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
Show All 31 Lines
define <16 x i64> @uadd_v16i64_vx(<16 x i64> %va, i64 %b) { define <16 x i64> @uadd_v16i64_vx(<16 x i64> %va, i64 %b) {
; RV32-LABEL: uadd_v16i64_vx: ; RV32-LABEL: uadd_v16i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsaddu.vv v8, v8, v16 ; RV32-NEXT: vsaddu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: uadd_v16i64_vx: ; RV64-LABEL: uadd_v16i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
Show All 19 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll

Show First 20 Lines • Show All 461 Lines • ▼ Show 20 Lines
define <2 x i64> @ssub_v2i64_vx(<2 x i64> %va, i64 %b) { define <2 x i64> @ssub_v2i64_vx(<2 x i64> %va, i64 %b) {
; RV32-LABEL: ssub_v2i64_vx: ; RV32-LABEL: ssub_v2i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vssub.vv v8, v8, v9 ; RV32-NEXT: vssub.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: ssub_v2i64_vx: ; RV64-LABEL: ssub_v2i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
Show All 32 Lines
define <4 x i64> @ssub_v4i64_vx(<4 x i64> %va, i64 %b) { define <4 x i64> @ssub_v4i64_vx(<4 x i64> %va, i64 %b) {
; RV32-LABEL: ssub_v4i64_vx: ; RV32-LABEL: ssub_v4i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vssub.vv v8, v8, v10 ; RV32-NEXT: vssub.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: ssub_v4i64_vx: ; RV64-LABEL: ssub_v4i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
Show All 32 Lines
define <8 x i64> @ssub_v8i64_vx(<8 x i64> %va, i64 %b) { define <8 x i64> @ssub_v8i64_vx(<8 x i64> %va, i64 %b) {
; RV32-LABEL: ssub_v8i64_vx: ; RV32-LABEL: ssub_v8i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vssub.vv v8, v8, v12 ; RV32-NEXT: vssub.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: ssub_v8i64_vx: ; RV64-LABEL: ssub_v8i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
Show All 32 Lines
define <16 x i64> @ssub_v16i64_vx(<16 x i64> %va, i64 %b) { define <16 x i64> @ssub_v16i64_vx(<16 x i64> %va, i64 %b) {
; RV32-LABEL: ssub_v16i64_vx: ; RV32-LABEL: ssub_v16i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vssub.vv v8, v8, v16 ; RV32-NEXT: vssub.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: ssub_v16i64_vx: ; RV64-LABEL: ssub_v16i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll

Show First 20 Lines • Show All 461 Lines • ▼ Show 20 Lines
define <2 x i64> @usub_v2i64_vx(<2 x i64> %va, i64 %b) { define <2 x i64> @usub_v2i64_vx(<2 x i64> %va, i64 %b) {
; RV32-LABEL: usub_v2i64_vx: ; RV32-LABEL: usub_v2i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vssubu.vv v8, v8, v9 ; RV32-NEXT: vssubu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: usub_v2i64_vx: ; RV64-LABEL: usub_v2i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
Show All 32 Lines
define <4 x i64> @usub_v4i64_vx(<4 x i64> %va, i64 %b) { define <4 x i64> @usub_v4i64_vx(<4 x i64> %va, i64 %b) {
; RV32-LABEL: usub_v4i64_vx: ; RV32-LABEL: usub_v4i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vssubu.vv v8, v8, v10 ; RV32-NEXT: vssubu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: usub_v4i64_vx: ; RV64-LABEL: usub_v4i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
Show All 32 Lines
define <8 x i64> @usub_v8i64_vx(<8 x i64> %va, i64 %b) { define <8 x i64> @usub_v8i64_vx(<8 x i64> %va, i64 %b) {
; RV32-LABEL: usub_v8i64_vx: ; RV32-LABEL: usub_v8i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vssubu.vv v8, v8, v12 ; RV32-NEXT: vssubu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: usub_v8i64_vx: ; RV64-LABEL: usub_v8i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
Show All 32 Lines
define <16 x i64> @usub_v16i64_vx(<16 x i64> %va, i64 %b) { define <16 x i64> @usub_v16i64_vx(<16 x i64> %va, i64 %b) {
; RV32-LABEL: usub_v16i64_vx: ; RV32-LABEL: usub_v16i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vssubu.vv v8, v8, v16 ; RV32-NEXT: vssubu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: usub_v16i64_vx: ; RV64-LABEL: usub_v16i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll

Show First 20 Lines • Show All 691 Lines • ▼ Show 20 Lines
define <2 x i64> @vsub_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) { define <2 x i64> @vsub_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vsub_vx_v2i64: ; RV32-LABEL: vsub_vx_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vsub.vv v8, v8, v9, v0.t ; RV32-NEXT: vsub.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vsub_vx_v2i64: ; RV64-LABEL: vsub_vx_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vsub.vx v8, v8, a0, v0.t ; RV64-NEXT: vsub.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
%v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v ret <2 x i64> %v
} }
define <2 x i64> @vsub_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) { define <2 x i64> @vsub_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vsub_vx_v2i64_unmasked: ; RV32-LABEL: vsub_vx_v2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vsub.vv v8, v8, v9 ; RV32-NEXT: vsub.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vsub_vx_v2i64_unmasked: ; RV64-LABEL: vsub_vx_v2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <4 x i64> @vsub_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) { define <4 x i64> @vsub_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vsub_vx_v4i64: ; RV32-LABEL: vsub_vx_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vsub.vv v8, v8, v10, v0.t ; RV32-NEXT: vsub.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vsub_vx_v4i64: ; RV64-LABEL: vsub_vx_v4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vsub.vx v8, v8, a0, v0.t ; RV64-NEXT: vsub.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
%v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v ret <4 x i64> %v
} }
define <4 x i64> @vsub_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) { define <4 x i64> @vsub_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vsub_vx_v4i64_unmasked: ; RV32-LABEL: vsub_vx_v4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vsub.vv v8, v8, v10 ; RV32-NEXT: vsub.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vsub_vx_v4i64_unmasked: ; RV64-LABEL: vsub_vx_v4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <8 x i64> @vsub_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vsub_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vsub_vx_v8i64: ; RV32-LABEL: vsub_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vsub.vv v8, v8, v12, v0.t ; RV32-NEXT: vsub.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vsub_vx_v8i64: ; RV64-LABEL: vsub_vx_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vsub.vx v8, v8, a0, v0.t ; RV64-NEXT: vsub.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
%v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
define <8 x i64> @vsub_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) { define <8 x i64> @vsub_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vsub_vx_v8i64_unmasked: ; RV32-LABEL: vsub_vx_v8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vsub.vv v8, v8, v12 ; RV32-NEXT: vsub.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vsub_vx_v8i64_unmasked: ; RV64-LABEL: vsub_vx_v8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <16 x i64> @vsub_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vsub_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vsub_vx_v16i64: ; RV32-LABEL: vsub_vx_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vsub.vv v8, v8, v16, v0.t ; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vsub_vx_v16i64: ; RV64-LABEL: vsub_vx_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vsub.vx v8, v8, a0, v0.t ; RV64-NEXT: vsub.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
%vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
%v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
define <16 x i64> @vsub_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) { define <16 x i64> @vsub_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vsub_vx_v16i64_unmasked: ; RV32-LABEL: vsub_vx_v16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vsub.vv v8, v8, v16 ; RV32-NEXT: vsub.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vsub_vx_v16i64_unmasked: ; RV64-LABEL: vsub_vx_v16i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 10 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll

Show First 20 Lines • Show All 1,379 Lines • ▼ Show 20 Lines
define <2 x i64> @vxor_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) { define <2 x i64> @vxor_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vxor_vx_v2i64: ; RV32-LABEL: vxor_vx_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vxor.vv v8, v8, v9, v0.t ; RV32-NEXT: vxor.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vxor_vx_v2i64: ; RV64-LABEL: vxor_vx_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vxor.vx v8, v8, a0, v0.t ; RV64-NEXT: vxor.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
%v = call <2 x i64> @llvm.vp.xor.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) %v = call <2 x i64> @llvm.vp.xor.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v ret <2 x i64> %v
} }
define <2 x i64> @vxor_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) { define <2 x i64> @vxor_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vxor_vx_v2i64_unmasked: ; RV32-LABEL: vxor_vx_v2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vxor.vv v8, v8, v9 ; RV32-NEXT: vxor.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vxor_vx_v2i64_unmasked: ; RV64-LABEL: vxor_vx_v2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
define <4 x i64> @vxor_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) { define <4 x i64> @vxor_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vxor_vx_v4i64: ; RV32-LABEL: vxor_vx_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vxor.vv v8, v8, v10, v0.t ; RV32-NEXT: vxor.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vxor_vx_v4i64: ; RV64-LABEL: vxor_vx_v4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vxor.vx v8, v8, a0, v0.t ; RV64-NEXT: vxor.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
%v = call <4 x i64> @llvm.vp.xor.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) %v = call <4 x i64> @llvm.vp.xor.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v ret <4 x i64> %v
} }
define <4 x i64> @vxor_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) { define <4 x i64> @vxor_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vxor_vx_v4i64_unmasked: ; RV32-LABEL: vxor_vx_v4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vxor.vv v8, v8, v10 ; RV32-NEXT: vxor.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vxor_vx_v4i64_unmasked: ; RV64-LABEL: vxor_vx_v4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
define <8 x i64> @vxor_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i64> @vxor_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vxor_vx_v8i64: ; RV32-LABEL: vxor_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vxor.vv v8, v8, v12, v0.t ; RV32-NEXT: vxor.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vxor_vx_v8i64: ; RV64-LABEL: vxor_vx_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vxor.vx v8, v8, a0, v0.t ; RV64-NEXT: vxor.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
%v = call <8 x i64> @llvm.vp.xor.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) %v = call <8 x i64> @llvm.vp.xor.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v ret <8 x i64> %v
} }
define <8 x i64> @vxor_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) { define <8 x i64> @vxor_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vxor_vx_v8i64_unmasked: ; RV32-LABEL: vxor_vx_v8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vxor.vv v8, v8, v12 ; RV32-NEXT: vxor.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vxor_vx_v8i64_unmasked: ; RV64-LABEL: vxor_vx_v8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
define <16 x i64> @vxor_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vxor_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vxor_vx_v16i64: ; RV32-LABEL: vxor_vx_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vxor.vv v8, v8, v16, v0.t ; RV32-NEXT: vxor.vv v8, v8, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vxor_vx_v16i64: ; RV64-LABEL: vxor_vx_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vxor.vx v8, v8, a0, v0.t ; RV64-NEXT: vxor.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
%vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
%v = call <16 x i64> @llvm.vp.xor.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) %v = call <16 x i64> @llvm.vp.xor.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
define <16 x i64> @vxor_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) { define <16 x i64> @vxor_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vxor_vx_v16i64_unmasked: ; RV32-LABEL: vxor_vx_v16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vxor.vv v8, v8, v16 ; RV32-NEXT: vxor.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vxor_vx_v16i64_unmasked: ; RV64-LABEL: vxor_vx_v16i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 62 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll

Show All 10 Linesdeclare void @llvm.riscv.vse.nxv1i64(
i64); i64);
define i64 @test(<vscale x 1 x i64> %0) nounwind { define i64 @test(<vscale x 1 x i64> %0) nounwind {
; CHECK-LABEL: name: test ; CHECK-LABEL: name: test
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK-NEXT: liveins: $v8 ; CHECK-NEXT: liveins: $v8
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8
; CHECK-NEXT: PseudoVSE64_V_M1 [[COPY]], %stack.0.a, 1, 6 /* e64 */ ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.a, 0
; CHECK-NEXT: PseudoVSE64_V_M1 [[COPY]], killed [[ADDI]], 1, 6 /* e64 */
; CHECK-NEXT: [[LD:%[0-9]+]]:gpr = LD %stack.0.a, 0 :: (dereferenceable load (s64) from %ir.a) ; CHECK-NEXT: [[LD:%[0-9]+]]:gpr = LD %stack.0.a, 0 :: (dereferenceable load (s64) from %ir.a)
; CHECK-NEXT: $x10 = COPY [[LD]] ; CHECK-NEXT: $x10 = COPY [[LD]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
entry: entry:
%a = alloca i64 %a = alloca i64
%b = bitcast i64* %a to <vscale x 1 x i64>* %b = bitcast i64* %a to <vscale x 1 x i64>*
call void @llvm.riscv.vse.nxv1i64( call void @llvm.riscv.vse.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64>* %b, <vscale x 1 x i64>* %b,
i64 1) i64 1)
%c = load i64, i64* %a %c = load i64, i64* %a
ret i64 %c ret i64 %c
} }

llvm/test/CodeGen/RISCV/rvv/localvar.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+v < %s \
; RUN: | FileCheck %s -check-prefix=RV64IV ; RUN: | FileCheck %s -check-prefix=RV64IV
define void @local_var_mf8() { define void @local_var_mf8() {
; RV64IV-LABEL: local_var_mf8: ; RV64IV-LABEL: local_var_mf8:
; RV64IV: # %bb.0: ; RV64IV: # %bb.0:
; RV64IV-NEXT: addi sp, sp, -16 ; RV64IV-NEXT: addi sp, sp, -16
; RV64IV-NEXT: .cfi_def_cfa_offset 16 ; RV64IV-NEXT: .cfi_def_cfa_offset 16
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: sub sp, sp, a0 ; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: addi a0, a0, 16 ; RV64IV-NEXT: addi a0, a0, 16
; RV64IV-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
; RV64IV-NEXT: vle8.v v8, (a0) ; RV64IV-NEXT: vle8.v v8, (a0)
; RV64IV-NEXT: addi a0, sp, 16 ; RV64IV-NEXT: addi a0, sp, 16
; RV64IV-NEXT: vle8.v v8, (a0) ; RV64IV-NEXT: vle8.v v8, (a0)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: add sp, sp, a0 ; RV64IV-NEXT: add sp, sp, a0
; RV64IV-NEXT: addi sp, sp, 16 ; RV64IV-NEXT: addi sp, sp, 16
; RV64IV-NEXT: ret ; RV64IV-NEXT: ret
▲ Show 20 Lines • Show All 123 Lines • ▼ Show 20 Lines; RV64IV-NEXT: ret
load volatile <vscale x 64 x i8>, <vscale x 64 x i8>* %local0 load volatile <vscale x 64 x i8>, <vscale x 64 x i8>* %local0
load volatile <vscale x 64 x i8>, <vscale x 64 x i8>* %local1 load volatile <vscale x 64 x i8>, <vscale x 64 x i8>* %local1
ret void ret void
} }
define void @local_var_m2_mix_local_scalar() { define void @local_var_m2_mix_local_scalar() {
; RV64IV-LABEL: local_var_m2_mix_local_scalar: ; RV64IV-LABEL: local_var_m2_mix_local_scalar:
; RV64IV: # %bb.0: ; RV64IV: # %bb.0:
; RV64IV-NEXT: addi sp, sp, -32 ; RV64IV-NEXT: addi sp, sp, -16
; RV64IV-NEXT: .cfi_def_cfa_offset 32 ; RV64IV-NEXT: .cfi_def_cfa_offset 16
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 2 ; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: sub sp, sp, a0 ; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: lw a0, 28(sp) ; RV64IV-NEXT: lw a0, 12(sp)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: addi a0, a0, 32 ; RV64IV-NEXT: addi a0, a0, 16
; RV64IV-NEXT: vl2r.v v8, (a0) ; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: addi a0, sp, 32 ; RV64IV-NEXT: addi a0, sp, 16
; RV64IV-NEXT: vl2r.v v8, (a0) ; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: lw a0, 24(sp) ; RV64IV-NEXT: lw a0, 8(sp)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 2 ; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: add sp, sp, a0 ; RV64IV-NEXT: add sp, sp, a0
; RV64IV-NEXT: addi sp, sp, 32 ; RV64IV-NEXT: addi sp, sp, 16
; RV64IV-NEXT: ret ; RV64IV-NEXT: ret
%local_scalar0 = alloca i32 %local_scalar0 = alloca i32
%local0 = alloca <vscale x 16 x i8> %local0 = alloca <vscale x 16 x i8>
%local1 = alloca <vscale x 16 x i8> %local1 = alloca <vscale x 16 x i8>
%local_scalar1 = alloca i32 %local_scalar1 = alloca i32
load volatile i32, i32* %local_scalar0 load volatile i32, i32* %local_scalar0
load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %local0 load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %local0
load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %local1 load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %local1
load volatile i32, i32* %local_scalar1 load volatile i32, i32* %local_scalar1
ret void ret void
} }
define void @local_var_m2_with_varsize_object(i64 %n) { define void @local_var_m2_with_varsize_object(i64 %n) {
; RV64IV-LABEL: local_var_m2_with_varsize_object: ; RV64IV-LABEL: local_var_m2_with_varsize_object:
; RV64IV: # %bb.0: ; RV64IV: # %bb.0:
; RV64IV-NEXT: addi sp, sp, -32 ; RV64IV-NEXT: addi sp, sp, -32
; RV64IV-NEXT: .cfi_def_cfa_offset 32 ; RV64IV-NEXT: .cfi_def_cfa_offset 32
; RV64IV-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64IV-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64IV-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64IV-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64IV-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64IV-NEXT: .cfi_offset ra, -8 ; RV64IV-NEXT: .cfi_offset ra, -8
; RV64IV-NEXT: .cfi_offset s0, -16 ; RV64IV-NEXT: .cfi_offset s0, -16
; RV64IV-NEXT: .cfi_offset s1, -24
; RV64IV-NEXT: addi s0, sp, 32 ; RV64IV-NEXT: addi s0, sp, 32
; RV64IV-NEXT: .cfi_def_cfa s0, 0 ; RV64IV-NEXT: .cfi_def_cfa s0, 0
; RV64IV-NEXT: csrr a1, vlenb ; RV64IV-NEXT: csrr a1, vlenb
; RV64IV-NEXT: slli a1, a1, 2 ; RV64IV-NEXT: slli a1, a1, 2
; RV64IV-NEXT: sub sp, sp, a1 ; RV64IV-NEXT: sub sp, sp, a1
; RV64IV-NEXT: addi a0, a0, 15 ; RV64IV-NEXT: addi a0, a0, 15
; RV64IV-NEXT: andi a0, a0, -16 ; RV64IV-NEXT: andi a0, a0, -16
; RV64IV-NEXT: sub a0, sp, a0 ; RV64IV-NEXT: sub a0, sp, a0
; RV64IV-NEXT: mv sp, a0 ; RV64IV-NEXT: mv sp, a0
; RV64IV-NEXT: csrr a1, vlenb ; RV64IV-NEXT: csrr a1, vlenb
; RV64IV-NEXT: slli a1, a1, 1 ; RV64IV-NEXT: slli a1, a1, 1
; RV64IV-NEXT: sub a1, s0, a1 ; RV64IV-NEXT: sub a1, s0, a1
; RV64IV-NEXT: addi a1, a1, -32 ; RV64IV-NEXT: addi a1, a1, -32
; RV64IV-NEXT: csrr a2, vlenb
; RV64IV-NEXT: slli a2, a2, 1
; RV64IV-NEXT: sub a2, s0, a2
; RV64IV-NEXT: addi s1, a2, -32
; RV64IV-NEXT: call notdead@plt ; RV64IV-NEXT: call notdead@plt
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: vl2r.v v8, (s1)
; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: sub a0, s0, a0
; RV64IV-NEXT: addi a0, a0, -32
; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 2 ; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: sub a0, s0, a0 ; RV64IV-NEXT: sub a0, s0, a0
; RV64IV-NEXT: addi a0, a0, -32 ; RV64IV-NEXT: addi a0, a0, -32
; RV64IV-NEXT: vl2r.v v8, (a0) ; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: addi sp, s0, -32 ; RV64IV-NEXT: addi sp, s0, -32
; RV64IV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64IV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64IV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64IV-NEXT: addi sp, sp, 32 ; RV64IV-NEXT: addi sp, sp, 32
; RV64IV-NEXT: ret ; RV64IV-NEXT: ret
%1 = alloca i8, i64 %n %1 = alloca i8, i64 %n
%2 = alloca <vscale x 16 x i8> %2 = alloca <vscale x 16 x i8>
%3 = alloca <vscale x 16 x i8> %3 = alloca <vscale x 16 x i8>
call void @notdead(i8* %1, <vscale x 16 x i8>* %2) call void @notdead(i8* %1, <vscale x 16 x i8>* %2)
load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %2 load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %2
load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %3 load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %3
ret void ret void
} }
define void @local_var_m2_with_bp(i64 %n) { define void @local_var_m2_with_bp(i64 %n) {
; RV64IV-LABEL: local_var_m2_with_bp: ; RV64IV-LABEL: local_var_m2_with_bp:
; RV64IV: # %bb.0: ; RV64IV: # %bb.0:
; RV64IV-NEXT: addi sp, sp, -272 ; RV64IV-NEXT: addi sp, sp, -256
; RV64IV-NEXT: .cfi_def_cfa_offset 272 ; RV64IV-NEXT: .cfi_def_cfa_offset 256
; RV64IV-NEXT: sd ra, 264(sp) # 8-byte Folded Spill ; RV64IV-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
; RV64IV-NEXT: sd s0, 256(sp) # 8-byte Folded Spill ; RV64IV-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
; RV64IV-NEXT: sd s1, 248(sp) # 8-byte Folded Spill ; RV64IV-NEXT: sd s1, 232(sp) # 8-byte Folded Spill
; RV64IV-NEXT: sd s2, 224(sp) # 8-byte Folded Spill
; RV64IV-NEXT: .cfi_offset ra, -8 ; RV64IV-NEXT: .cfi_offset ra, -8
; RV64IV-NEXT: .cfi_offset s0, -16 ; RV64IV-NEXT: .cfi_offset s0, -16
; RV64IV-NEXT: .cfi_offset s1, -24 ; RV64IV-NEXT: .cfi_offset s1, -24
; RV64IV-NEXT: addi s0, sp, 272 ; RV64IV-NEXT: .cfi_offset s2, -32
; RV64IV-NEXT: addi s0, sp, 256
; RV64IV-NEXT: .cfi_def_cfa s0, 0 ; RV64IV-NEXT: .cfi_def_cfa s0, 0
; RV64IV-NEXT: csrr a1, vlenb ; RV64IV-NEXT: csrr a1, vlenb
; RV64IV-NEXT: slli a1, a1, 2 ; RV64IV-NEXT: slli a1, a1, 2
; RV64IV-NEXT: sub sp, sp, a1 ; RV64IV-NEXT: sub sp, sp, a1
; RV64IV-NEXT: andi sp, sp, -128 ; RV64IV-NEXT: andi sp, sp, -128
; RV64IV-NEXT: mv s1, sp ; RV64IV-NEXT: mv s1, sp
; RV64IV-NEXT: addi a0, a0, 15 ; RV64IV-NEXT: addi a0, a0, 15
; RV64IV-NEXT: andi a0, a0, -16 ; RV64IV-NEXT: andi a0, a0, -16
; RV64IV-NEXT: sub a0, sp, a0 ; RV64IV-NEXT: sub a0, sp, a0
; RV64IV-NEXT: mv sp, a0 ; RV64IV-NEXT: mv sp, a0
; RV64IV-NEXT: addi a1, s1, 128 ; RV64IV-NEXT: addi a1, s1, 128
; RV64IV-NEXT: csrr a2, vlenb ; RV64IV-NEXT: csrr a2, vlenb
; RV64IV-NEXT: slli a2, a2, 1 ; RV64IV-NEXT: slli a2, a2, 1
; RV64IV-NEXT: add a2, s1, a2 ; RV64IV-NEXT: add a2, s1, a2
; RV64IV-NEXT: addi a2, a2, 240 ; RV64IV-NEXT: addi a2, a2, 224
; RV64IV-NEXT: csrr a3, vlenb
; RV64IV-NEXT: slli a3, a3, 1
; RV64IV-NEXT: add a3, s1, a3
; RV64IV-NEXT: addi s2, a3, 224
; RV64IV-NEXT: call notdead2@plt ; RV64IV-NEXT: call notdead2@plt
; RV64IV-NEXT: lw a0, 124(s1) ; RV64IV-NEXT: lw a0, 124(s1)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: vl2r.v v8, (s2)
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: addi a0, s1, 224
; RV64IV-NEXT: add a0, s1, a0
; RV64IV-NEXT: addi a0, a0, 240
; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: addi a0, s1, 240
; RV64IV-NEXT: vl2r.v v8, (a0) ; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: lw a0, 120(s1) ; RV64IV-NEXT: lw a0, 120(s1)
; RV64IV-NEXT: addi sp, s0, -272 ; RV64IV-NEXT: addi sp, s0, -256
; RV64IV-NEXT: ld ra, 264(sp) # 8-byte Folded Reload ; RV64IV-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld s0, 256(sp) # 8-byte Folded Reload ; RV64IV-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld s1, 248(sp) # 8-byte Folded Reload ; RV64IV-NEXT: ld s1, 232(sp) # 8-byte Folded Reload
; RV64IV-NEXT: addi sp, sp, 272 ; RV64IV-NEXT: ld s2, 224(sp) # 8-byte Folded Reload
; RV64IV-NEXT: addi sp, sp, 256
; RV64IV-NEXT: ret ; RV64IV-NEXT: ret
%1 = alloca i8, i64 %n %1 = alloca i8, i64 %n
%2 = alloca i32, align 128 %2 = alloca i32, align 128
%local_scalar0 = alloca i32 %local_scalar0 = alloca i32
%local0 = alloca <vscale x 16 x i8> %local0 = alloca <vscale x 16 x i8>
%local1 = alloca <vscale x 16 x i8> %local1 = alloca <vscale x 16 x i8>
%local_scalar1 = alloca i32 %local_scalar1 = alloca i32
call void @notdead2(i8* %1, i32* %2, <vscale x 16 x i8>* %local0) call void @notdead2(i8* %1, i32* %2, <vscale x 16 x i8>* %local0)
Show All 30 Lines

llvm/test/CodeGen/RISCV/rvv/masked-tama.ll

Show First 20 Lines • Show All 1,377 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; RV32-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64: ; RV32-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32-NEXT: vmseq.vv v0, v8, v9, v0.t ; RV32-NEXT: vmseq.vv v0, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64: ; RV64-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
Show All 19 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; RV32-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64: ; RV32-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32-NEXT: vmsle.vv v0, v9, v8, v0.t ; RV32-NEXT: vmsle.vv v0, v9, v8, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64: ; RV64-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
Show All 40 Lines

llvm/test/CodeGen/RISCV/rvv/memory-args.ll

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: addi a0, a0, 64 ; RV64IV-NEXT: addi a0, a0, 64
; RV64IV-NEXT: vl8r.v v16, (a0) ; RV64IV-NEXT: vl8r.v v16, (a0)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 3 ; RV64IV-NEXT: slli a0, a0, 3
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: addi a0, a0, 64 ; RV64IV-NEXT: addi a0, a0, 64
; RV64IV-NEXT: vl8r.v v24, (a0) ; RV64IV-NEXT: vl8r.v v24, (a0)
; RV64IV-NEXT: addi a0, sp, 64
; RV64IV-NEXT: addi a1, sp, 64 ; RV64IV-NEXT: addi a1, sp, 64
; RV64IV-NEXT: addi a0, sp, 64
; RV64IV-NEXT: vs8r.v v24, (a1) ; RV64IV-NEXT: vs8r.v v24, (a1)
; RV64IV-NEXT: call callee@plt ; RV64IV-NEXT: call callee@plt
; RV64IV-NEXT: addi sp, s0, -80 ; RV64IV-NEXT: addi sp, s0, -80
; RV64IV-NEXT: ld ra, 72(sp) # 8-byte Folded Reload ; RV64IV-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld s0, 64(sp) # 8-byte Folded Reload ; RV64IV-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; RV64IV-NEXT: addi sp, sp, 80 ; RV64IV-NEXT: addi sp, sp, 80
; RV64IV-NEXT: ret ; RV64IV-NEXT: ret
%local0 = alloca <vscale x 64 x i8> %local0 = alloca <vscale x 64 x i8>
Show All 10 Lines

llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll

Show All 28 Lines
; CHECK-NEXT: addi s0, sp, 80 ; CHECK-NEXT: addi s0, sp, 80
; CHECK-NEXT: .cfi_def_cfa s0, 0 ; CHECK-NEXT: .cfi_def_cfa s0, 0
; CHECK-NEXT: csrr t0, vlenb ; CHECK-NEXT: csrr t0, vlenb
; CHECK-NEXT: slli t0, t0, 4 ; CHECK-NEXT: slli t0, t0, 4
; CHECK-NEXT: sub sp, sp, t0 ; CHECK-NEXT: sub sp, sp, t0
; CHECK-NEXT: andi sp, sp, -64 ; CHECK-NEXT: andi sp, sp, -64
; CHECK-NEXT: mv s1, sp ; CHECK-NEXT: mv s1, sp
; CHECK-NEXT: addi t0, s1, 64 ; CHECK-NEXT: addi t0, s1, 64
; CHECK-NEXT: sd t0, 8(sp)
; CHECK-NEXT: csrr t0, vlenb
; CHECK-NEXT: slli t0, t0, 3
; CHECK-NEXT: add t0, s1, t0
; CHECK-NEXT: addi t0, t0, 64
; CHECK-NEXT: sd t0, 0(sp)
; CHECK-NEXT: addi t0, s1, 64
; CHECK-NEXT: vs8r.v v8, (t0)
; CHECK-NEXT: csrr t0, vlenb
; CHECK-NEXT: slli t0, t0, 3
; CHECK-NEXT: add t0, s1, t0
; CHECK-NEXT: addi t0, t0, 64
; CHECK-NEXT: vs8r.v v8, (t0) ; CHECK-NEXT: vs8r.v v8, (t0)
; CHECK-NEXT: csrr t1, vlenb
; CHECK-NEXT: slli t1, t1, 3
; CHECK-NEXT: add t1, s1, t1
; CHECK-NEXT: addi t1, t1, 64
; CHECK-NEXT: vs8r.v v8, (t1)
; CHECK-NEXT: sd t0, 8(sp)
; CHECK-NEXT: sd t1, 0(sp)
; CHECK-NEXT: vmv8r.v v16, v8 ; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: call bar@plt ; CHECK-NEXT: call bar@plt
; CHECK-NEXT: addi sp, s0, -80 ; CHECK-NEXT: addi sp, s0, -80
; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 80 ; CHECK-NEXT: addi sp, sp, 80
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ret = call <vscale x 16 x i32> @bar(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, <vscale x 16 x i32> %x, <vscale x 16 x i32> %x, <vscale x 16 x i32> %x, <vscale x 16 x i32> %x) %ret = call <vscale x 16 x i32> @bar(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, <vscale x 16 x i32> %x, <vscale x 16 x i32> %x, <vscale x 16 x i32> %x, <vscale x 16 x i32> %x)
ret <vscale x 16 x i32> %ret ret <vscale x 16 x i32> %ret
} }

llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
define dso_local void @lots_args(i32 signext %x0, i32 signext %x1, <vscale x 16 x i32> %v0, i32 signext %x2, i32 signext %x3, i32 signext %x4, i32 signext %x5, i32 signext %x6, i32 %x7, i32 %x8, i32 %x9) #0 { define dso_local void @lots_args(i32 signext %x0, i32 signext %x1, <vscale x 16 x i32> %v0, i32 signext %x2, i32 signext %x3, i32 signext %x4, i32 signext %x5, i32 signext %x6, i32 %x7, i32 %x8, i32 %x9) #0 {
; CHECK-LABEL: lots_args: ; CHECK-LABEL: lots_args:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -80 ; CHECK-NEXT: addi sp, sp, -64
; CHECK-NEXT: sd ra, 72(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 64(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
; CHECK-NEXT: addi s0, sp, 80 ; CHECK-NEXT: addi s0, sp, 64
; CHECK-NEXT: csrr t0, vlenb ; CHECK-NEXT: csrr t0, vlenb
; CHECK-NEXT: slli t0, t0, 3 ; CHECK-NEXT: slli t0, t0, 3
; CHECK-NEXT: sub sp, sp, t0 ; CHECK-NEXT: sub sp, sp, t0
; CHECK-NEXT: ld t0, 8(s0) ; CHECK-NEXT: ld t0, 8(s0)
; CHECK-NEXT: ld t1, 0(s0) ; CHECK-NEXT: ld t1, 0(s0)
; CHECK-NEXT: sw a0, -36(s0) ; CHECK-NEXT: sw a0, -28(s0)
; CHECK-NEXT: sw a1, -40(s0) ; CHECK-NEXT: sw a1, -32(s0)
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: sub a0, s0, a0 ; CHECK-NEXT: sub a0, s0, a0
; CHECK-NEXT: addi a0, a0, -80 ; CHECK-NEXT: addi a0, a0, -64
; CHECK-NEXT: vs8r.v v8, (a0) ; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: sw a2, -44(s0) ; CHECK-NEXT: sw a2, -36(s0)
; CHECK-NEXT: sw a3, -48(s0) ; CHECK-NEXT: sw a3, -40(s0)
; CHECK-NEXT: sw a4, -52(s0) ; CHECK-NEXT: sw a4, -44(s0)
; CHECK-NEXT: sw a5, -56(s0) ; CHECK-NEXT: sw a5, -48(s0)
; CHECK-NEXT: sw a6, -60(s0) ; CHECK-NEXT: sw a6, -52(s0)
; CHECK-NEXT: sw a7, -64(s0) ; CHECK-NEXT: sw a7, -56(s0)
; CHECK-NEXT: sw t1, -68(s0) ; CHECK-NEXT: sw t1, -60(s0)
; CHECK-NEXT: sw t0, -72(s0) ; CHECK-NEXT: sw t0, -64(s0)
; CHECK-NEXT: addi sp, s0, -80 ; CHECK-NEXT: addi sp, s0, -64
; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 64(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 80 ; CHECK-NEXT: addi sp, sp, 64
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%x0.addr = alloca i32, align 4 %x0.addr = alloca i32, align 4
%x1.addr = alloca i32, align 4 %x1.addr = alloca i32, align 4
%v0.addr = alloca <vscale x 16 x i32>, align 4 %v0.addr = alloca <vscale x 16 x i32>, align 4
%x2.addr = alloca i32, align 4 %x2.addr = alloca i32, align 4
%x3.addr = alloca i32, align 4 %x3.addr = alloca i32, align 4
%x4.addr = alloca i32, align 4 %x4.addr = alloca i32, align 4
Show All 17 Lines
} }
define dso_local signext i32 @main() #0 { define dso_local signext i32 @main() #0 {
; CHECK-LABEL: main: ; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -112 ; CHECK-NEXT: addi sp, sp, -112
; CHECK-NEXT: sd ra, 104(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 104(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 96(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 96(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 88(sp) # 8-byte Folded Spill
; CHECK-NEXT: addi s0, sp, 112 ; CHECK-NEXT: addi s0, sp, 112
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: sub sp, sp, a0 ; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: sw zero, -36(s0) ; CHECK-NEXT: sw zero, -36(s0)
; CHECK-NEXT: sd zero, -48(s0) ; CHECK-NEXT: sd zero, -48(s0)
; CHECK-NEXT: sd zero, -56(s0) ; CHECK-NEXT: sd zero, -56(s0)
; CHECK-NEXT: vsetivli a0, 4, e32, m8, ta, mu ; CHECK-NEXT: vsetivli a0, 4, e32, m8, ta, mu
; CHECK-NEXT: sd a0, -64(s0) ; CHECK-NEXT: sd a0, -64(s0)
; CHECK-NEXT: ld a0, -64(s0) ; CHECK-NEXT: ld a0, -64(s0)
; CHECK-NEXT: addi a1, s0, -56
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: addi a0, s0, -56 ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: sub a0, s0, a0 ; CHECK-NEXT: sub a0, s0, a0
; CHECK-NEXT: addi a0, a0, -112 ; CHECK-NEXT: addi s1, a0, -112
; CHECK-NEXT: vs8r.v v8, (a0) ; CHECK-NEXT: vs8r.v v8, (s1)
; CHECK-NEXT: li a0, 1 ; CHECK-NEXT: li a0, 1
; CHECK-NEXT: sw a0, -68(s0) ; CHECK-NEXT: sw a0, -68(s0)
; CHECK-NEXT: sw a0, -72(s0) ; CHECK-NEXT: sw a0, -72(s0)
; CHECK-NEXT: sw a0, -76(s0) ; CHECK-NEXT: sw a0, -76(s0)
; CHECK-NEXT: sw a0, -80(s0) ; CHECK-NEXT: sw a0, -80(s0)
; CHECK-NEXT: sw a0, -84(s0) ; CHECK-NEXT: sw a0, -84(s0)
; CHECK-NEXT: sw a0, -88(s0) ; CHECK-NEXT: sw a0, -88(s0)
; CHECK-NEXT: sw a0, -92(s0) ; CHECK-NEXT: sw a0, -92(s0)
; CHECK-NEXT: sw a0, -96(s0) ; CHECK-NEXT: sw a0, -96(s0)
; CHECK-NEXT: sw a0, -100(s0) ; CHECK-NEXT: sw a0, -100(s0)
; CHECK-NEXT: sw a0, -104(s0) ; CHECK-NEXT: sw a0, -104(s0)
; CHECK-NEXT: lw a0, -68(s0) ; CHECK-NEXT: lw a0, -68(s0)
; CHECK-NEXT: lw a1, -72(s0) ; CHECK-NEXT: lw a1, -72(s0)
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: vl8re32.v v8, (s1)
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub a2, s0, a2
; CHECK-NEXT: addi a2, a2, -112
; CHECK-NEXT: vl8re32.v v8, (a2)
; CHECK-NEXT: lw a2, -76(s0) ; CHECK-NEXT: lw a2, -76(s0)
; CHECK-NEXT: lw a3, -80(s0) ; CHECK-NEXT: lw a3, -80(s0)
; CHECK-NEXT: lw a4, -84(s0) ; CHECK-NEXT: lw a4, -84(s0)
; CHECK-NEXT: lw a5, -88(s0) ; CHECK-NEXT: lw a5, -88(s0)
; CHECK-NEXT: lw a6, -92(s0) ; CHECK-NEXT: lw a6, -92(s0)
; CHECK-NEXT: lw a7, -96(s0) ; CHECK-NEXT: lw a7, -96(s0)
; CHECK-NEXT: lw t0, -100(s0) ; CHECK-NEXT: lw t0, -100(s0)
; CHECK-NEXT: lw t1, -104(s0) ; CHECK-NEXT: lw t1, -104(s0)
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sd t1, 8(sp) ; CHECK-NEXT: sd t1, 8(sp)
; CHECK-NEXT: sd t0, 0(sp) ; CHECK-NEXT: sd t0, 0(sp)
; CHECK-NEXT: call lots_args ; CHECK-NEXT: call lots_args
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: lw a0, -68(s0) ; CHECK-NEXT: lw a0, -68(s0)
; CHECK-NEXT: lw a1, -72(s0) ; CHECK-NEXT: lw a1, -72(s0)
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: vl8re32.v v8, (s1)
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub a2, s0, a2
; CHECK-NEXT: addi a2, a2, -112
; CHECK-NEXT: vl8re32.v v8, (a2)
; CHECK-NEXT: lw a2, -76(s0) ; CHECK-NEXT: lw a2, -76(s0)
; CHECK-NEXT: lw a3, -80(s0) ; CHECK-NEXT: lw a3, -80(s0)
; CHECK-NEXT: lw a4, -84(s0) ; CHECK-NEXT: lw a4, -84(s0)
; CHECK-NEXT: lw a5, -88(s0) ; CHECK-NEXT: lw a5, -88(s0)
; CHECK-NEXT: lw a6, -92(s0) ; CHECK-NEXT: lw a6, -92(s0)
; CHECK-NEXT: lw a7, -96(s0) ; CHECK-NEXT: lw a7, -96(s0)
; CHECK-NEXT: lw t0, -100(s0) ; CHECK-NEXT: lw t0, -100(s0)
; CHECK-NEXT: lw t1, -104(s0) ; CHECK-NEXT: lw t1, -104(s0)
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sd t1, 8(sp) ; CHECK-NEXT: sd t1, 8(sp)
; CHECK-NEXT: sd t0, 0(sp) ; CHECK-NEXT: sd t0, 0(sp)
; CHECK-NEXT: call lots_args ; CHECK-NEXT: call lots_args
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: addi sp, s0, -112 ; CHECK-NEXT: addi sp, s0, -112
; CHECK-NEXT: ld ra, 104(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 104(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 96(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 96(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 88(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 112 ; CHECK-NEXT: addi sp, sp, 112
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%retval = alloca i32, align 4 %retval = alloca i32, align 4
%input = alloca [4 x i32], align 4 %input = alloca [4 x i32], align 4
%vl = alloca i64, align 8 %vl = alloca i64, align 8
%v0 = alloca <vscale x 16 x i32>, align 4 %v0 = alloca <vscale x 16 x i32>, align 4
%x0 = alloca i32, align 4 %x0 = alloca i32, align 4
▲ Show 20 Lines • Show All 63 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll

Show First 20 Lines • Show All 2,526 Lines • ▼ Show 20 Lines
define <vscale x 1 x i1> @icmp_eq_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @icmp_eq_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_eq_vx_nxv1i64: ; RV32-LABEL: icmp_eq_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vmseq.vv v0, v8, v9, v0.t ; RV32-NEXT: vmseq.vv v0, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_eq_vx_nxv1i64: ; RV64-LABEL: icmp_eq_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; RV64-NEXT: vmseq.vx v0, v8, a0, v0.t ; RV64-NEXT: vmseq.vx v0, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, metadata !"eq", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, metadata !"eq", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @icmp_eq_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @icmp_eq_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_eq_vx_swap_nxv1i64: ; RV32-LABEL: icmp_eq_vx_swap_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vmseq.vv v0, v9, v8, v0.t ; RV32-NEXT: vmseq.vv v0, v9, v8, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_eq_vx_swap_nxv1i64: ; RV64-LABEL: icmp_eq_vx_swap_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
define <vscale x 1 x i1> @icmp_ne_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @icmp_ne_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_ne_vx_nxv1i64: ; RV32-LABEL: icmp_ne_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vmsne.vv v0, v8, v9, v0.t ; RV32-NEXT: vmsne.vv v0, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ne_vx_nxv1i64: ; RV64-LABEL: icmp_ne_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; RV64-NEXT: vmsne.vx v0, v8, a0, v0.t ; RV64-NEXT: vmsne.vx v0, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, metadata !"ne", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, metadata !"ne", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @icmp_ne_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @icmp_ne_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_ne_vx_swap_nxv1i64: ; RV32-LABEL: icmp_ne_vx_swap_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vmsne.vv v0, v9, v8, v0.t ; RV32-NEXT: vmsne.vv v0, v9, v8, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ne_vx_swap_nxv1i64: ; RV64-LABEL: icmp_ne_vx_swap_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
define <vscale x 1 x i1> @icmp_ugt_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @icmp_ugt_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_ugt_vx_nxv1i64: ; RV32-LABEL: icmp_ugt_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vmsltu.vv v0, v9, v8, v0.t ; RV32-NEXT: vmsltu.vv v0, v9, v8, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ugt_vx_nxv1i64: ; RV64-LABEL: icmp_ugt_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; RV64-NEXT: vmsgtu.vx v0, v8, a0, v0.t ; RV64-NEXT: vmsgtu.vx v0, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, metadata !"ugt", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, metadata !"ugt", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @icmp_ugt_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @icmp_ugt_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_ugt_vx_swap_nxv1i64: ; RV32-LABEL: icmp_ugt_vx_swap_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vmsltu.vv v0, v8, v9, v0.t ; RV32-NEXT: vmsltu.vv v0, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ugt_vx_swap_nxv1i64: ; RV64-LABEL: icmp_ugt_vx_swap_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
define <vscale x 1 x i1> @icmp_uge_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @icmp_uge_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_uge_vx_nxv1i64: ; RV32-LABEL: icmp_uge_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vmsleu.vv v0, v9, v8, v0.t ; RV32-NEXT: vmsleu.vv v0, v9, v8, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_uge_vx_nxv1i64: ; RV64-LABEL: icmp_uge_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 10 Lines
define <vscale x 1 x i1> @icmp_uge_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @icmp_uge_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_uge_vx_swap_nxv1i64: ; RV32-LABEL: icmp_uge_vx_swap_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vmsleu.vv v0, v8, v9, v0.t ; RV32-NEXT: vmsleu.vv v0, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_uge_vx_swap_nxv1i64: ; RV64-LABEL: icmp_uge_vx_swap_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
define <vscale x 1 x i1> @icmp_ult_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @icmp_ult_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_ult_vx_nxv1i64: ; RV32-LABEL: icmp_ult_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vmsltu.vv v0, v8, v9, v0.t ; RV32-NEXT: vmsltu.vv v0, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ult_vx_nxv1i64: ; RV64-LABEL: icmp_ult_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; RV64-NEXT: vmsltu.vx v0, v8, a0, v0.t ; RV64-NEXT: vmsltu.vx v0, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, metadata !"ult", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, metadata !"ult", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @icmp_ult_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @icmp_ult_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_ult_vx_swap_nxv1i64: ; RV32-LABEL: icmp_ult_vx_swap_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vmsltu.vv v0, v9, v8, v0.t ; RV32-NEXT: vmsltu.vv v0, v9, v8, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ult_vx_swap_nxv1i64: ; RV64-LABEL: icmp_ult_vx_swap_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
define <vscale x 1 x i1> @icmp_sgt_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @icmp_sgt_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_sgt_vx_nxv1i64: ; RV32-LABEL: icmp_sgt_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vmslt.vv v0, v9, v8, v0.t ; RV32-NEXT: vmslt.vv v0, v9, v8, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sgt_vx_nxv1i64: ; RV64-LABEL: icmp_sgt_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; RV64-NEXT: vmsgt.vx v0, v8, a0, v0.t ; RV64-NEXT: vmsgt.vx v0, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, metadata !"sgt", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, metadata !"sgt", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @icmp_sgt_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @icmp_sgt_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_sgt_vx_swap_nxv1i64: ; RV32-LABEL: icmp_sgt_vx_swap_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vmslt.vv v0, v8, v9, v0.t ; RV32-NEXT: vmslt.vv v0, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sgt_vx_swap_nxv1i64: ; RV64-LABEL: icmp_sgt_vx_swap_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
define <vscale x 1 x i1> @icmp_sge_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @icmp_sge_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_sge_vx_nxv1i64: ; RV32-LABEL: icmp_sge_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vmsle.vv v0, v9, v8, v0.t ; RV32-NEXT: vmsle.vv v0, v9, v8, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sge_vx_nxv1i64: ; RV64-LABEL: icmp_sge_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 10 Lines
define <vscale x 1 x i1> @icmp_sge_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @icmp_sge_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_sge_vx_swap_nxv1i64: ; RV32-LABEL: icmp_sge_vx_swap_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vmsle.vv v0, v8, v9, v0.t ; RV32-NEXT: vmsle.vv v0, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sge_vx_swap_nxv1i64: ; RV64-LABEL: icmp_sge_vx_swap_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
define <vscale x 1 x i1> @icmp_slt_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @icmp_slt_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_slt_vx_nxv1i64: ; RV32-LABEL: icmp_slt_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vmslt.vv v0, v8, v9, v0.t ; RV32-NEXT: vmslt.vv v0, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_slt_vx_nxv1i64: ; RV64-LABEL: icmp_slt_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; RV64-NEXT: vmslt.vx v0, v8, a0, v0.t ; RV64-NEXT: vmslt.vx v0, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, metadata !"slt", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, metadata !"slt", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @icmp_slt_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @icmp_slt_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_slt_vx_swap_nxv1i64: ; RV32-LABEL: icmp_slt_vx_swap_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vmslt.vv v0, v9, v8, v0.t ; RV32-NEXT: vmslt.vv v0, v9, v8, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_slt_vx_swap_nxv1i64: ; RV64-LABEL: icmp_slt_vx_swap_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
define <vscale x 1 x i1> @icmp_sle_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @icmp_sle_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_sle_vx_nxv1i64: ; RV32-LABEL: icmp_sle_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vmsle.vv v0, v8, v9, v0.t ; RV32-NEXT: vmsle.vv v0, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sle_vx_nxv1i64: ; RV64-LABEL: icmp_sle_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; RV64-NEXT: vmsle.vx v0, v8, a0, v0.t ; RV64-NEXT: vmsle.vx v0, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, metadata !"sle", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.icmp.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, metadata !"sle", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @icmp_sle_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @icmp_sle_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_sle_vx_swap_nxv1i64: ; RV32-LABEL: icmp_sle_vx_swap_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV32-NEXT: vmsle.vv v0, v9, v8, v0.t ; RV32-NEXT: vmsle.vv v0, v9, v8, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sle_vx_swap_nxv1i64: ; RV64-LABEL: icmp_sle_vx_swap_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define <vscale x 8 x i1> @icmp_eq_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @icmp_eq_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_eq_vx_nxv8i64: ; RV32-LABEL: icmp_eq_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmseq.vv v16, v8, v24, v0.t ; RV32-NEXT: vmseq.vv v16, v8, v24, v0.t
; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_eq_vx_nxv8i64: ; RV64-LABEL: icmp_eq_vx_nxv8i64:
Show All 10 Lines
define <vscale x 8 x i1> @icmp_eq_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @icmp_eq_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_eq_vx_swap_nxv8i64: ; RV32-LABEL: icmp_eq_vx_swap_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmseq.vv v16, v24, v8, v0.t ; RV32-NEXT: vmseq.vv v16, v24, v8, v0.t
; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_eq_vx_swap_nxv8i64: ; RV64-LABEL: icmp_eq_vx_swap_nxv8i64:
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define <vscale x 8 x i1> @icmp_ne_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @icmp_ne_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_ne_vx_nxv8i64: ; RV32-LABEL: icmp_ne_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmsne.vv v16, v8, v24, v0.t ; RV32-NEXT: vmsne.vv v16, v8, v24, v0.t
; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ne_vx_nxv8i64: ; RV64-LABEL: icmp_ne_vx_nxv8i64:
Show All 10 Lines
define <vscale x 8 x i1> @icmp_ne_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @icmp_ne_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_ne_vx_swap_nxv8i64: ; RV32-LABEL: icmp_ne_vx_swap_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmsne.vv v16, v24, v8, v0.t ; RV32-NEXT: vmsne.vv v16, v24, v8, v0.t
; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ne_vx_swap_nxv8i64: ; RV64-LABEL: icmp_ne_vx_swap_nxv8i64:
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_ugt_vx_nxv8i64: ; RV32-LABEL: icmp_ugt_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmsltu.vv v16, v24, v8, v0.t ; RV32-NEXT: vmsltu.vv v16, v24, v8, v0.t
; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ugt_vx_nxv8i64: ; RV64-LABEL: icmp_ugt_vx_nxv8i64:
Show All 10 Lines
define <vscale x 8 x i1> @icmp_ugt_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @icmp_ugt_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_ugt_vx_swap_nxv8i64: ; RV32-LABEL: icmp_ugt_vx_swap_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmsltu.vv v16, v8, v24, v0.t ; RV32-NEXT: vmsltu.vv v16, v8, v24, v0.t
; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ugt_vx_swap_nxv8i64: ; RV64-LABEL: icmp_ugt_vx_swap_nxv8i64:
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define <vscale x 8 x i1> @icmp_uge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @icmp_uge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_uge_vx_nxv8i64: ; RV32-LABEL: icmp_uge_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmsleu.vv v16, v24, v8, v0.t ; RV32-NEXT: vmsleu.vv v16, v24, v8, v0.t
; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_uge_vx_nxv8i64: ; RV64-LABEL: icmp_uge_vx_nxv8i64:
Show All 12 Lines
define <vscale x 8 x i1> @icmp_uge_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @icmp_uge_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_uge_vx_swap_nxv8i64: ; RV32-LABEL: icmp_uge_vx_swap_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmsleu.vv v16, v8, v24, v0.t ; RV32-NEXT: vmsleu.vv v16, v8, v24, v0.t
; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_uge_vx_swap_nxv8i64: ; RV64-LABEL: icmp_uge_vx_swap_nxv8i64:
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define <vscale x 8 x i1> @icmp_ult_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @icmp_ult_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_ult_vx_nxv8i64: ; RV32-LABEL: icmp_ult_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmsltu.vv v16, v8, v24, v0.t ; RV32-NEXT: vmsltu.vv v16, v8, v24, v0.t
; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ult_vx_nxv8i64: ; RV64-LABEL: icmp_ult_vx_nxv8i64:
Show All 10 Lines
define <vscale x 8 x i1> @icmp_ult_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @icmp_ult_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_ult_vx_swap_nxv8i64: ; RV32-LABEL: icmp_ult_vx_swap_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmsltu.vv v16, v24, v8, v0.t ; RV32-NEXT: vmsltu.vv v16, v24, v8, v0.t
; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ult_vx_swap_nxv8i64: ; RV64-LABEL: icmp_ult_vx_swap_nxv8i64:
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_sgt_vx_nxv8i64: ; RV32-LABEL: icmp_sgt_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmslt.vv v16, v24, v8, v0.t ; RV32-NEXT: vmslt.vv v16, v24, v8, v0.t
; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sgt_vx_nxv8i64: ; RV64-LABEL: icmp_sgt_vx_nxv8i64:
Show All 10 Lines
define <vscale x 8 x i1> @icmp_sgt_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @icmp_sgt_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_sgt_vx_swap_nxv8i64: ; RV32-LABEL: icmp_sgt_vx_swap_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmslt.vv v16, v8, v24, v0.t ; RV32-NEXT: vmslt.vv v16, v8, v24, v0.t
; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sgt_vx_swap_nxv8i64: ; RV64-LABEL: icmp_sgt_vx_swap_nxv8i64:
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define <vscale x 8 x i1> @icmp_sge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @icmp_sge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_sge_vx_nxv8i64: ; RV32-LABEL: icmp_sge_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmsle.vv v16, v24, v8, v0.t ; RV32-NEXT: vmsle.vv v16, v24, v8, v0.t
; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sge_vx_nxv8i64: ; RV64-LABEL: icmp_sge_vx_nxv8i64:
Show All 12 Lines
define <vscale x 8 x i1> @icmp_sge_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @icmp_sge_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_sge_vx_swap_nxv8i64: ; RV32-LABEL: icmp_sge_vx_swap_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmsle.vv v16, v8, v24, v0.t ; RV32-NEXT: vmsle.vv v16, v8, v24, v0.t
; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sge_vx_swap_nxv8i64: ; RV64-LABEL: icmp_sge_vx_swap_nxv8i64:
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define <vscale x 8 x i1> @icmp_slt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @icmp_slt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_slt_vx_nxv8i64: ; RV32-LABEL: icmp_slt_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmslt.vv v16, v8, v24, v0.t ; RV32-NEXT: vmslt.vv v16, v8, v24, v0.t
; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_slt_vx_nxv8i64: ; RV64-LABEL: icmp_slt_vx_nxv8i64:
Show All 10 Lines
define <vscale x 8 x i1> @icmp_slt_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @icmp_slt_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_slt_vx_swap_nxv8i64: ; RV32-LABEL: icmp_slt_vx_swap_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmslt.vv v16, v24, v8, v0.t ; RV32-NEXT: vmslt.vv v16, v24, v8, v0.t
; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_slt_vx_swap_nxv8i64: ; RV64-LABEL: icmp_slt_vx_swap_nxv8i64:
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define <vscale x 8 x i1> @icmp_sle_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @icmp_sle_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_sle_vx_nxv8i64: ; RV32-LABEL: icmp_sle_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmsle.vv v16, v8, v24, v0.t ; RV32-NEXT: vmsle.vv v16, v8, v24, v0.t
; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sle_vx_nxv8i64: ; RV64-LABEL: icmp_sle_vx_nxv8i64:
Show All 10 Lines
define <vscale x 8 x i1> @icmp_sle_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @icmp_sle_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: icmp_sle_vx_swap_nxv8i64: ; RV32-LABEL: icmp_sle_vx_swap_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmsle.vv v16, v24, v8, v0.t ; RV32-NEXT: vmsle.vv v16, v24, v8, v0.t
; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sle_vx_swap_nxv8i64: ; RV64-LABEL: icmp_sle_vx_swap_nxv8i64:
Show All 38 Lines

llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll

Show First 20 Lines • Show All 2,237 Lines • ▼ Show 20 Lines
define <vscale x 8 x i1> @icmp_eq_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i1> @icmp_eq_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: icmp_eq_vx_nxv8i64: ; RV32-LABEL: icmp_eq_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmseq.vv v0, v8, v16 ; RV32-NEXT: vmseq.vv v0, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_eq_vx_nxv8i64: ; RV64-LABEL: icmp_eq_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vmseq.vx v0, v8, a0 ; RV64-NEXT: vmseq.vx v0, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp eq <vscale x 8 x i64> %va, %splat %vc = icmp eq <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_eq_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i1> @icmp_eq_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: icmp_eq_xv_nxv8i64: ; RV32-LABEL: icmp_eq_xv_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmseq.vv v0, v16, v8 ; RV32-NEXT: vmseq.vv v0, v16, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_eq_xv_nxv8i64: ; RV64-LABEL: icmp_eq_xv_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
define <vscale x 8 x i1> @icmp_ne_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i1> @icmp_ne_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: icmp_ne_vx_nxv8i64: ; RV32-LABEL: icmp_ne_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmsne.vv v0, v8, v16 ; RV32-NEXT: vmsne.vv v0, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ne_vx_nxv8i64: ; RV64-LABEL: icmp_ne_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vmsne.vx v0, v8, a0 ; RV64-NEXT: vmsne.vx v0, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp ne <vscale x 8 x i64> %va, %splat %vc = icmp ne <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ne_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i1> @icmp_ne_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: icmp_ne_xv_nxv8i64: ; RV32-LABEL: icmp_ne_xv_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmsne.vv v0, v16, v8 ; RV32-NEXT: vmsne.vv v0, v16, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ne_xv_nxv8i64: ; RV64-LABEL: icmp_ne_xv_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 29 Lines
define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: icmp_ugt_vx_nxv8i64: ; RV32-LABEL: icmp_ugt_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmsltu.vv v0, v16, v8 ; RV32-NEXT: vmsltu.vv v0, v16, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ugt_vx_nxv8i64: ; RV64-LABEL: icmp_ugt_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vmsgtu.vx v0, v8, a0 ; RV64-NEXT: vmsgtu.vx v0, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp ugt <vscale x 8 x i64> %va, %splat %vc = icmp ugt <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: icmp_ugt_xv_nxv8i64: ; RV32-LABEL: icmp_ugt_xv_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmsltu.vv v0, v8, v16 ; RV32-NEXT: vmsltu.vv v0, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ugt_xv_nxv8i64: ; RV64-LABEL: icmp_ugt_xv_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 29 Lines
define <vscale x 8 x i1> @icmp_uge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i1> @icmp_uge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: icmp_uge_vx_nxv8i64: ; RV32-LABEL: icmp_uge_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmsleu.vv v0, v16, v8 ; RV32-NEXT: vmsleu.vv v0, v16, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_uge_vx_nxv8i64: ; RV64-LABEL: icmp_uge_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vmv.v.x v16, a0 ; RV64-NEXT: vmv.v.x v16, a0
; RV64-NEXT: vmsleu.vv v0, v16, v8 ; RV64-NEXT: vmsleu.vv v0, v16, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i64> %va, %splat %vc = icmp uge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i1> @icmp_uge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: icmp_uge_xv_nxv8i64: ; RV32-LABEL: icmp_uge_xv_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmsleu.vv v0, v8, v16 ; RV32-NEXT: vmsleu.vv v0, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_uge_xv_nxv8i64: ; RV64-LABEL: icmp_uge_xv_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
define <vscale x 8 x i1> @icmp_ult_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i1> @icmp_ult_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: icmp_ult_vx_nxv8i64: ; RV32-LABEL: icmp_ult_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmsltu.vv v0, v8, v16 ; RV32-NEXT: vmsltu.vv v0, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ult_vx_nxv8i64: ; RV64-LABEL: icmp_ult_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vmsltu.vx v0, v8, a0 ; RV64-NEXT: vmsltu.vx v0, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i64> %va, %splat %vc = icmp ult <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i1> @icmp_ult_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: icmp_ult_xv_nxv8i64: ; RV32-LABEL: icmp_ult_xv_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmsltu.vv v0, v16, v8 ; RV32-NEXT: vmsltu.vv v0, v16, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ult_xv_nxv8i64: ; RV64-LABEL: icmp_ult_xv_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
define <vscale x 8 x i1> @icmp_ule_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i1> @icmp_ule_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: icmp_ule_vx_nxv8i64: ; RV32-LABEL: icmp_ule_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmsleu.vv v0, v8, v16 ; RV32-NEXT: vmsleu.vv v0, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ule_vx_nxv8i64: ; RV64-LABEL: icmp_ule_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vmsleu.vx v0, v8, a0 ; RV64-NEXT: vmsleu.vx v0, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp ule <vscale x 8 x i64> %va, %splat %vc = icmp ule <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ule_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i1> @icmp_ule_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: icmp_ule_xv_nxv8i64: ; RV32-LABEL: icmp_ule_xv_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmsleu.vv v0, v16, v8 ; RV32-NEXT: vmsleu.vv v0, v16, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_ule_xv_nxv8i64: ; RV64-LABEL: icmp_ule_xv_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 30 Lines
define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: icmp_sgt_vx_nxv8i64: ; RV32-LABEL: icmp_sgt_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmslt.vv v0, v16, v8 ; RV32-NEXT: vmslt.vv v0, v16, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sgt_vx_nxv8i64: ; RV64-LABEL: icmp_sgt_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vmsgt.vx v0, v8, a0 ; RV64-NEXT: vmsgt.vx v0, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp sgt <vscale x 8 x i64> %va, %splat %vc = icmp sgt <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: icmp_sgt_xv_nxv8i64: ; RV32-LABEL: icmp_sgt_xv_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmslt.vv v0, v8, v16 ; RV32-NEXT: vmslt.vv v0, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sgt_xv_nxv8i64: ; RV64-LABEL: icmp_sgt_xv_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 29 Lines
define <vscale x 8 x i1> @icmp_sge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i1> @icmp_sge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: icmp_sge_vx_nxv8i64: ; RV32-LABEL: icmp_sge_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmsle.vv v0, v16, v8 ; RV32-NEXT: vmsle.vv v0, v16, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sge_vx_nxv8i64: ; RV64-LABEL: icmp_sge_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vmv.v.x v16, a0 ; RV64-NEXT: vmv.v.x v16, a0
; RV64-NEXT: vmsle.vv v0, v16, v8 ; RV64-NEXT: vmsle.vv v0, v16, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i64> %va, %splat %vc = icmp sge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i1> @icmp_sge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: icmp_sge_xv_nxv8i64: ; RV32-LABEL: icmp_sge_xv_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmsle.vv v0, v8, v16 ; RV32-NEXT: vmsle.vv v0, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sge_xv_nxv8i64: ; RV64-LABEL: icmp_sge_xv_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
define <vscale x 8 x i1> @icmp_slt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i1> @icmp_slt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: icmp_slt_vx_nxv8i64: ; RV32-LABEL: icmp_slt_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmslt.vv v0, v8, v16 ; RV32-NEXT: vmslt.vv v0, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_slt_vx_nxv8i64: ; RV64-LABEL: icmp_slt_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vmslt.vx v0, v8, a0 ; RV64-NEXT: vmslt.vx v0, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i64> %va, %splat %vc = icmp slt <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i1> @icmp_slt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: icmp_slt_xv_nxv8i64: ; RV32-LABEL: icmp_slt_xv_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmslt.vv v0, v16, v8 ; RV32-NEXT: vmslt.vv v0, v16, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_slt_xv_nxv8i64: ; RV64-LABEL: icmp_slt_xv_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
define <vscale x 8 x i1> @icmp_sle_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i1> @icmp_sle_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: icmp_sle_vx_nxv8i64: ; RV32-LABEL: icmp_sle_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmsle.vv v0, v8, v16 ; RV32-NEXT: vmsle.vv v0, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sle_vx_nxv8i64: ; RV64-LABEL: icmp_sle_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vmsle.vx v0, v8, a0 ; RV64-NEXT: vmsle.vx v0, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = icmp sle <vscale x 8 x i64> %va, %splat %vc = icmp sle <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sle_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i1> @icmp_sle_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: icmp_sle_xv_nxv8i64: ; RV32-LABEL: icmp_sle_xv_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmsle.vv v0, v16, v8 ; RV32-NEXT: vmsle.vv v0, v16, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: icmp_sle_xv_nxv8i64: ; RV64-LABEL: icmp_sle_xv_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
▲ Show 20 Lines • Show All 56 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/stepvector.ll

Show First 20 Lines • Show All 495 Lines • ▼ Show 20 Lines
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: li a0, 7 ; RV32-NEXT: li a0, 7
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: lui a0, 797989 ; RV32-NEXT: lui a0, 797989
; RV32-NEXT: addi a0, a0, -683 ; RV32-NEXT: addi a0, a0, -683
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v8, (a0), zero ; RV32-NEXT: vlse64.v v8, (a0), zero
; RV32-NEXT: vid.v v16 ; RV32-NEXT: vid.v v16
; RV32-NEXT: vmul.vv v8, v16, v8 ; RV32-NEXT: vmul.vv v8, v16, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mul_bigimm_stepvector_nxv8i64: ; RV64-LABEL: mul_bigimm_stepvector_nxv8i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
Show All 33 Lines
define <vscale x 16 x i64> @stepvector_nxv16i64() { define <vscale x 16 x i64> @stepvector_nxv16i64() {
; RV32-LABEL: stepvector_nxv16i64: ; RV32-LABEL: stepvector_nxv16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vid.v v8 ; RV32-NEXT: vid.v v8
; RV32-NEXT: vadd.vv v16, v8, v16 ; RV32-NEXT: vadd.vv v16, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: stepvector_nxv16i64: ; RV64-LABEL: stepvector_nxv16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
; RV32-NEXT: srli a0, a0, 3 ; RV32-NEXT: srli a0, a0, 3
; RV32-NEXT: li a1, 62 ; RV32-NEXT: li a1, 62
; RV32-NEXT: mul a1, a0, a1 ; RV32-NEXT: mul a1, a0, a1
; RV32-NEXT: lui a2, 92455 ; RV32-NEXT: lui a2, 92455
; RV32-NEXT: addi a2, a2, -1368 ; RV32-NEXT: addi a2, a2, -1368
; RV32-NEXT: mulhu a0, a0, a2 ; RV32-NEXT: mulhu a0, a0, a2
; RV32-NEXT: add a0, a0, a1 ; RV32-NEXT: add a0, a0, a1
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v8, (a0), zero ; RV32-NEXT: vlse64.v v8, (a0), zero
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vid.v v24 ; RV32-NEXT: vid.v v24
; RV32-NEXT: vmul.vv v8, v24, v8 ; RV32-NEXT: vmul.vv v8, v24, v8
; RV32-NEXT: vadd.vv v16, v8, v16 ; RV32-NEXT: vadd.vv v16, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mul_bigimm_stepvector_nxv16i64: ; RV64-LABEL: mul_bigimm_stepvector_nxv16i64:
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll

Show First 20 Lines • Show All 287 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmacc.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, iXLen %3) nounwind { define <vscale x 1 x i64> @intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; RV32-LABEL: intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64: ; RV32-LABEL: intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmacc.vv v8, v9, v10 ; RV32-NEXT: vmacc.vv v8, v9, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64: ; RV64-LABEL: intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmadd.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vmadd_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, iXLen %3) nounwind { define <vscale x 1 x i64> @intrinsic_vmadd_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; RV32-LABEL: intrinsic_vmadd_vx_nxv1i64_i64_nxv1i64: ; RV32-LABEL: intrinsic_vmadd_vx_nxv1i64_i64_nxv1i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmadd.vv v8, v10, v9 ; RV32-NEXT: vmadd.vv v8, v10, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmadd_vx_nxv1i64_i64_nxv1i64: ; RV64-LABEL: intrinsic_vmadd_vx_nxv1i64_i64_nxv1i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vnmsac.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vnmsac_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, iXLen %3) nounwind { define <vscale x 1 x i64> @intrinsic_vnmsac_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; RV32-LABEL: intrinsic_vnmsac_vx_nxv1i64_i64_nxv1i64: ; RV32-LABEL: intrinsic_vnmsac_vx_nxv1i64_i64_nxv1i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vnmsac.vv v8, v9, v10 ; RV32-NEXT: vnmsac.vv v8, v9, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vnmsac_vx_nxv1i64_i64_nxv1i64: ; RV64-LABEL: intrinsic_vnmsac_vx_nxv1i64_i64_nxv1i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vnmsub.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vnmsub_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, iXLen %3) nounwind { define <vscale x 1 x i64> @intrinsic_vnmsub_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {
; RV32-LABEL: intrinsic_vnmsub_vx_nxv1i64_i64_nxv1i64: ; RV32-LABEL: intrinsic_vnmsub_vx_nxv1i64_i64_nxv1i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vnmsub.vv v8, v10, v9 ; RV32-NEXT: vnmsub.vv v8, v10, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vnmsub_vx_nxv1i64_i64_nxv1i64: ; RV64-LABEL: intrinsic_vnmsub_vx_nxv1i64_i64_nxv1i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
▲ Show 20 Lines • Show All 503 Lines • ▼ Show 20 Lines
declare <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(<vscale x 1 x i64>, i64, iXLen); declare <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(<vscale x 1 x i64>, i64, iXLen);
define <vscale x 1 x i64> @intrinsic_vmv.s.x_x_nxv1i64(i64 %0, iXLen %1) nounwind { define <vscale x 1 x i64> @intrinsic_vmv.s.x_x_nxv1i64(i64 %0, iXLen %1) nounwind {
; RV32-LABEL: intrinsic_vmv.s.x_x_nxv1i64: ; RV32-LABEL: intrinsic_vmv.s.x_x_nxv1i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v8, (a0), zero ; RV32-NEXT: vlse64.v v8, (a0), zero
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmv.s.x_x_nxv1i64: ; RV64-LABEL: intrinsic_vmv.s.x_x_nxv1i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vmv.s.x v8, a0 ; RV64-NEXT: vmv.s.x v8, a0
▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll

Show First 20 Lines • Show All 1,145 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vrsub.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind { define <vscale x 1 x i64> @intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind {
; RV32-LABEL: intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, mu
; RV32-NEXT: vsub.vv v8, v10, v9 ; RV32-NEXT: vsub.vv v8, v10, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
Show All 17 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vsadd.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vsadd_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind { define <vscale x 1 x i64> @intrinsic_vsadd_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind {
; RV32-LABEL: intrinsic_vsadd_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vsadd_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, mu
; RV32-NEXT: vsadd.vv v8, v9, v10 ; RV32-NEXT: vsadd.vv v8, v9, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vsadd_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vsadd_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind { define <vscale x 1 x i64> @intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind {
; RV32-LABEL: intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, mu
; RV32-NEXT: vsmul.vv v8, v9, v10 ; RV32-NEXT: vsmul.vv v8, v9, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
▲ Show 20 Lines • Show All 148 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vssub.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vssub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind { define <vscale x 1 x i64> @intrinsic_vssub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind {
; RV32-LABEL: intrinsic_vssub_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vssub_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, mu
; RV32-NEXT: vssub.vv v8, v9, v10 ; RV32-NEXT: vssub.vv v8, v9, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vssub_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vssub_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
Show All 17 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vssubu.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vssubu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind { define <vscale x 1 x i64> @intrinsic_vssubu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind {
; RV32-LABEL: intrinsic_vssubu_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vssubu_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, mu
; RV32-NEXT: vssubu.vv v8, v9, v10 ; RV32-NEXT: vssubu.vv v8, v9, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vssubu_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vssubu_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
▲ Show 20 Lines • Show All 971 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmerge.nxv8i64.i64(
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i64> @intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, tu, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, tu, mu
; RV32-NEXT: vmerge.vvm v8, v16, v24, v0 ; RV32-NEXT: vmerge.vvm v8, v16, v24, v0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
Show All 14 Lines
define <vscale x 8 x i64> @intrinsic_vmerge_vim_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind { define <vscale x 8 x i64> @intrinsic_vmerge_vim_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; RV32-LABEL: intrinsic_vmerge_vim_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vmerge_vim_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: li a1, 15 ; RV32-NEXT: li a1, 15
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: li a1, -1 ; RV32-NEXT: li a1, -1
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: addi a1, sp, 8
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vlse64.v v24, (a1), zero
; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsetvli zero, zero, e64, m8, tu, mu ; RV32-NEXT: vsetvli zero, zero, e64, m8, tu, mu
; RV32-NEXT: vmerge.vvm v8, v16, v24, v0 ; RV32-NEXT: vmerge.vvm v8, v16, v24, v0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmerge_vim_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vmerge_vim_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: li a1, -1 ; RV64-NEXT: li a1, -1
▲ Show 20 Lines • Show All 130 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vmv.v.x_x_nxv1i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 1 x i64> @intrinsic_vmv.v.x_x_nxv1i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vmv.v.x_x_nxv1i64: ; RV32-LABEL: intrinsic_vmv.v.x_x_nxv1i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
; RV32-NEXT: vlse64.v v8, (a0), zero ; RV32-NEXT: vlse64.v v8, (a0), zero
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmv.v.x_x_nxv1i64: ; RV64-LABEL: intrinsic_vmv.v.x_x_nxv1i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu
; RV64-NEXT: vmv.v.x v8, a0 ; RV64-NEXT: vmv.v.x v8, a0
Show All 29 Lines

llvm/test/CodeGen/RISCV/rvv/vaadd.ll

Show First 20 Lines • Show All 1,853 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vaadd.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 1 x i64> @intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vaadd.vv v8, v8, v9 ; RV32-NEXT: vaadd.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vaadd.mask.nxv1i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 1 x i64> @intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i64> @intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vaadd.vv v8, v9, v10, v0.t ; RV32-NEXT: vaadd.vv v8, v9, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vaadd.nxv2i64.i64(
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 2 x i64> @intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vaadd.vv v8, v8, v10 ; RV32-NEXT: vaadd.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vaadd.mask.nxv2i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 2 x i64> @intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i64> @intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vaadd.vv v8, v10, v12, v0.t ; RV32-NEXT: vaadd.vv v8, v10, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vaadd.nxv4i64.i64(
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 4 x i64> @intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vaadd.vv v8, v8, v12 ; RV32-NEXT: vaadd.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vaadd.mask.nxv4i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 4 x i64> @intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i64> @intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vaadd.vv v8, v12, v16, v0.t ; RV32-NEXT: vaadd.vv v8, v12, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vaadd.nxv8i64.i64(
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vaadd_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 8 x i64> @intrinsic_vaadd_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vaadd_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vaadd_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vaadd.vv v8, v8, v16 ; RV32-NEXT: vaadd.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vaadd_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vaadd_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vaadd.mask.nxv8i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 8 x i64> @intrinsic_vaadd_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i64> @intrinsic_vaadd_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vaadd_mask_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vaadd_mask_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vaadd.vv v8, v16, v24, v0.t ; RV32-NEXT: vaadd.vv v8, v16, v24, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vaadd_mask_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vaadd_mask_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
Show All 12 Lines

llvm/test/CodeGen/RISCV/rvv/vaaddu.ll

Show First 20 Lines • Show All 1,853 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vaaddu.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 1 x i64> @intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vaaddu.vv v8, v8, v9 ; RV32-NEXT: vaaddu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vaaddu.mask.nxv1i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 1 x i64> @intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i64> @intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vaaddu.vv v8, v9, v10, v0.t ; RV32-NEXT: vaaddu.vv v8, v9, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vaaddu.nxv2i64.i64(
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 2 x i64> @intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vaaddu.vv v8, v8, v10 ; RV32-NEXT: vaaddu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vaaddu.mask.nxv2i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 2 x i64> @intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i64> @intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vaaddu.vv v8, v10, v12, v0.t ; RV32-NEXT: vaaddu.vv v8, v10, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vaaddu.nxv4i64.i64(
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 4 x i64> @intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vaaddu.vv v8, v8, v12 ; RV32-NEXT: vaaddu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vaaddu.mask.nxv4i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 4 x i64> @intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i64> @intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vaaddu.vv v8, v12, v16, v0.t ; RV32-NEXT: vaaddu.vv v8, v12, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vaaddu.nxv8i64.i64(
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vaaddu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 8 x i64> @intrinsic_vaaddu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vaaddu_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vaaddu_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vaaddu.vv v8, v8, v16 ; RV32-NEXT: vaaddu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vaaddu_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vaaddu_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vaaddu.mask.nxv8i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 8 x i64> @intrinsic_vaaddu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i64> @intrinsic_vaaddu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vaaddu_mask_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vaaddu_mask_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vaaddu.vv v8, v16, v24, v0.t ; RV32-NEXT: vaaddu.vv v8, v16, v24, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vaaddu_mask_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vaaddu_mask_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
Show All 12 Lines

llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll

Show First 20 Lines • Show All 968 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vadc.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vadc_vxm_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vadc_vxm_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vadc_vxm_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vadc_vxm_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 ; CHECK-NEXT: vadc.vvm v8, v8, v9, v0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vadc.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vadc.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vadc.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vadc_vxm_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i64> @intrinsic_vadc_vxm_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vadc_vxm_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vadc_vxm_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vadc.vvm v8, v8, v10, v0 ; CHECK-NEXT: vadc.vvm v8, v8, v10, v0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vadc.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vadc.nxv2i64.i64(
<vscale x 2 x i64> undef, <vscale x 2 x i64> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vadc.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vadc_vxm_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i64> @intrinsic_vadc_vxm_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vadc_vxm_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vadc_vxm_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vadc.vvm v8, v8, v12, v0 ; CHECK-NEXT: vadc.vvm v8, v8, v12, v0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vadc.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vadc.nxv4i64.i64(
<vscale x 4 x i64> undef, <vscale x 4 x i64> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vadc.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vadc_vxm_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i64> @intrinsic_vadc_vxm_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vadc_vxm_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vadc_vxm_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vadc.vvm v8, v8, v16, v0 ; CHECK-NEXT: vadc.vvm v8, v8, v16, v0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vadc.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vadc.nxv8i64.i64(
<vscale x 8 x i64> undef, <vscale x 8 x i64> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
▲ Show 20 Lines • Show All 380 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll

Show First 20 Lines • Show All 666 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vadd_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) { define <vscale x 1 x i64> @vadd_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; RV32-LABEL: vadd_vx_nxv1i64: ; RV32-LABEL: vadd_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vadd.vv v8, v8, v9 ; RV32-NEXT: vadd.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_nxv1i64: ; RV64-LABEL: vadd_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
Show All 31 Lines
define <vscale x 2 x i64> @vadd_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) { define <vscale x 2 x i64> @vadd_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; RV32-LABEL: vadd_vx_nxv2i64: ; RV32-LABEL: vadd_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vadd.vv v8, v8, v10 ; RV32-NEXT: vadd.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_nxv2i64: ; RV64-LABEL: vadd_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
Show All 31 Lines
define <vscale x 4 x i64> @vadd_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) { define <vscale x 4 x i64> @vadd_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; RV32-LABEL: vadd_vx_nxv4i64: ; RV32-LABEL: vadd_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vadd.vv v8, v8, v12 ; RV32-NEXT: vadd.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_nxv4i64: ; RV64-LABEL: vadd_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
Show All 31 Lines
define <vscale x 8 x i64> @vadd_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i64> @vadd_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: vadd_vx_nxv8i64: ; RV32-LABEL: vadd_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vadd.vv v8, v8, v16 ; RV32-NEXT: vadd.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_nxv8i64: ; RV64-LABEL: vadd_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 31 Lines

llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll

Show First 20 Lines • Show All 1,704 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vadd_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i64> @vadd_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vadd_vx_nxv1i64: ; RV32-LABEL: vadd_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vadd.vv v8, v8, v9, v0.t ; RV32-NEXT: vadd.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_nxv1i64: ; RV64-LABEL: vadd_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vadd.vx v8, v8, a0, v0.t ; RV64-NEXT: vadd.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i64> @llvm.vp.add.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i64> @llvm.vp.add.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v ret <vscale x 1 x i64> %v
} }
define <vscale x 1 x i64> @vadd_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 1 x i64> @vadd_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vadd_vx_nxv1i64_unmasked: ; RV32-LABEL: vadd_vx_nxv1i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vadd.vv v8, v8, v9 ; RV32-NEXT: vadd.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_nxv1i64_unmasked: ; RV64-LABEL: vadd_vx_nxv1i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
define <vscale x 2 x i64> @vadd_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i64> @vadd_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vadd_vx_nxv2i64: ; RV32-LABEL: vadd_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vadd.vv v8, v8, v10, v0.t ; RV32-NEXT: vadd.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_nxv2i64: ; RV64-LABEL: vadd_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vadd.vx v8, v8, a0, v0.t ; RV64-NEXT: vadd.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i64> @llvm.vp.add.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl) %v = call <vscale x 2 x i64> @llvm.vp.add.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
define <vscale x 2 x i64> @vadd_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 2 x i64> @vadd_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vadd_vx_nxv2i64_unmasked: ; RV32-LABEL: vadd_vx_nxv2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vadd.vv v8, v8, v10 ; RV32-NEXT: vadd.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_nxv2i64_unmasked: ; RV64-LABEL: vadd_vx_nxv2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
define <vscale x 4 x i64> @vadd_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i64> @vadd_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vadd_vx_nxv4i64: ; RV32-LABEL: vadd_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vadd.vv v8, v8, v12, v0.t ; RV32-NEXT: vadd.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_nxv4i64: ; RV64-LABEL: vadd_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vadd.vx v8, v8, a0, v0.t ; RV64-NEXT: vadd.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i64> @llvm.vp.add.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl) %v = call <vscale x 4 x i64> @llvm.vp.add.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v ret <vscale x 4 x i64> %v
} }
define <vscale x 4 x i64> @vadd_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 4 x i64> @vadd_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vadd_vx_nxv4i64_unmasked: ; RV32-LABEL: vadd_vx_nxv4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vadd.vv v8, v8, v12 ; RV32-NEXT: vadd.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_nxv4i64_unmasked: ; RV64-LABEL: vadd_vx_nxv4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
define <vscale x 8 x i64> @vadd_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vadd_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vadd_vx_nxv8i64: ; RV32-LABEL: vadd_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t ; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_nxv8i64: ; RV64-LABEL: vadd_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vadd.vx v8, v8, a0, v0.t ; RV64-NEXT: vadd.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i64> @llvm.vp.add.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i64> @llvm.vp.add.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i64> @vadd_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 8 x i64> @vadd_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vadd_vx_nxv8i64_unmasked: ; RV32-LABEL: vadd_vx_nxv8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vadd.vv v8, v8, v16 ; RV32-NEXT: vadd.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_nxv8i64_unmasked: ; RV64-LABEL: vadd_vx_nxv8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 36 Lines

llvm/test/CodeGen/RISCV/rvv/vadd.ll

Show First 20 Lines • Show All 1,853 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vadd_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 1 x i64> @intrinsic_vadd_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vadd_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vadd_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vadd.vv v8, v8, v9 ; RV32-NEXT: vadd.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vadd_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vadd_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 1 x i64> @intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i64> @intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vadd.vv v8, v9, v10, v0.t ; RV32-NEXT: vadd.vv v8, v9, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64(
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_vadd_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 2 x i64> @intrinsic_vadd_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vadd_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vadd_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vadd.vv v8, v8, v10 ; RV32-NEXT: vadd.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vadd_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vadd_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 2 x i64> @intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i64> @intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vadd.vv v8, v10, v12, v0.t ; RV32-NEXT: vadd.vv v8, v10, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64(
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_vadd_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 4 x i64> @intrinsic_vadd_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vadd_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vadd_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vadd.vv v8, v8, v12 ; RV32-NEXT: vadd.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vadd_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vadd_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 4 x i64> @intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i64> @intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vadd.vv v8, v12, v16, v0.t ; RV32-NEXT: vadd.vv v8, v12, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64(
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vadd_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 8 x i64> @intrinsic_vadd_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vadd_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vadd_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vadd.vv v8, v8, v16 ; RV32-NEXT: vadd.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vadd_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vadd_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 8 x i64> @intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i64> @intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vadd.vv v8, v16, v24, v0.t ; RV32-NEXT: vadd.vv v8, v16, v24, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
▲ Show 20 Lines • Show All 738 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll

Show First 20 Lines • Show All 1,891 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vand.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vand_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vand_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vand_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vand_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: vand.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vand.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vand.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vand.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vand_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vand_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vand.vv v8, v9, v10, v0.t ; CHECK-NEXT: vand.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vand.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vand.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 11 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vand.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vand_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vand_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vand_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vand_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vand.vv v8, v8, v10 ; CHECK-NEXT: vand.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vand.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vand.nxv2i64.i64(
<vscale x 2 x i64> undef, <vscale x 2 x i64> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vand.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vand_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vand_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vand.vv v8, v10, v12, v0.t ; CHECK-NEXT: vand.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vand.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vand.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 11 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vand.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vand_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vand_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vand_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vand_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vand.vv v8, v8, v12 ; CHECK-NEXT: vand.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vand.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vand.nxv4i64.i64(
<vscale x 4 x i64> undef, <vscale x 4 x i64> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vand.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vand_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vand_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vand.vv v8, v12, v16, v0.t ; CHECK-NEXT: vand.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vand.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vand.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 11 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vand.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vand_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vand_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vand_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vand_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vand.vv v8, v8, v16 ; CHECK-NEXT: vand.vv v8, v8, v16
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vand.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vand.nxv8i64.i64(
<vscale x 8 x i64> undef, <vscale x 8 x i64> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
Show All 12 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vand.mask.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vand_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vand_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v24, (a0), zero ; CHECK-NEXT: vlse64.v v24, (a0), zero
; CHECK-NEXT: vand.vv v8, v16, v24, v0.t ; CHECK-NEXT: vand.vv v8, v16, v24, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vand.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vand.mask.nxv8i64.i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
▲ Show 20 Lines • Show All 732 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll

Show First 20 Lines • Show All 1,075 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vand_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) { define <vscale x 1 x i64> @vand_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; RV32-LABEL: vand_vx_nxv1i64: ; RV32-LABEL: vand_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vand.vv v8, v8, v9 ; RV32-NEXT: vand.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vand_vx_nxv1i64: ; RV64-LABEL: vand_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
define <vscale x 2 x i64> @vand_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) { define <vscale x 2 x i64> @vand_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; RV32-LABEL: vand_vx_nxv2i64: ; RV32-LABEL: vand_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vand_vx_nxv2i64: ; RV64-LABEL: vand_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
define <vscale x 4 x i64> @vand_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) { define <vscale x 4 x i64> @vand_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; RV32-LABEL: vand_vx_nxv4i64: ; RV32-LABEL: vand_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vand_vx_nxv4i64: ; RV64-LABEL: vand_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
define <vscale x 8 x i64> @vand_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i64> @vand_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: vand_vx_nxv8i64: ; RV32-LABEL: vand_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vand_vx_nxv8i64: ; RV64-LABEL: vand_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vand-vp.ll

Show First 20 Lines • Show All 1,499 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vand_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i64> @vand_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vand_vx_nxv1i64: ; RV32-LABEL: vand_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vand.vv v8, v8, v9, v0.t ; RV32-NEXT: vand.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vand_vx_nxv1i64: ; RV64-LABEL: vand_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i64> @llvm.vp.and.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i64> @llvm.vp.and.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v ret <vscale x 1 x i64> %v
} }
define <vscale x 1 x i64> @vand_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 1 x i64> @vand_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vand_vx_nxv1i64_unmasked: ; RV32-LABEL: vand_vx_nxv1i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vand.vv v8, v8, v9 ; RV32-NEXT: vand.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vand_vx_nxv1i64_unmasked: ; RV64-LABEL: vand_vx_nxv1i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
define <vscale x 2 x i64> @vand_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i64> @vand_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vand_vx_nxv2i64: ; RV32-LABEL: vand_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vand.vv v8, v8, v10, v0.t ; RV32-NEXT: vand.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vand_vx_nxv2i64: ; RV64-LABEL: vand_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i64> @llvm.vp.and.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl) %v = call <vscale x 2 x i64> @llvm.vp.and.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
define <vscale x 2 x i64> @vand_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 2 x i64> @vand_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vand_vx_nxv2i64_unmasked: ; RV32-LABEL: vand_vx_nxv2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vand_vx_nxv2i64_unmasked: ; RV64-LABEL: vand_vx_nxv2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
define <vscale x 4 x i64> @vand_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i64> @vand_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vand_vx_nxv4i64: ; RV32-LABEL: vand_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vand.vv v8, v8, v12, v0.t ; RV32-NEXT: vand.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vand_vx_nxv4i64: ; RV64-LABEL: vand_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i64> @llvm.vp.and.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl) %v = call <vscale x 4 x i64> @llvm.vp.and.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v ret <vscale x 4 x i64> %v
} }
define <vscale x 4 x i64> @vand_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 4 x i64> @vand_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vand_vx_nxv4i64_unmasked: ; RV32-LABEL: vand_vx_nxv4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vand_vx_nxv4i64_unmasked: ; RV64-LABEL: vand_vx_nxv4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
define <vscale x 8 x i64> @vand_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vand_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vand_vx_nxv8i64: ; RV32-LABEL: vand_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vand_vx_nxv8i64: ; RV64-LABEL: vand_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i64> @llvm.vp.and.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i64> @llvm.vp.and.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i64> @vand_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 8 x i64> @vand_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vand_vx_nxv8i64_unmasked: ; RV32-LABEL: vand_vx_nxv8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vand_vx_nxv8i64_unmasked: ; RV64-LABEL: vand_vx_nxv8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 36 Lines

llvm/test/CodeGen/RISCV/rvv/vasub.ll

Show First 20 Lines • Show All 1,853 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vasub.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vasub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 1 x i64> @intrinsic_vasub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vasub_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vasub_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vasub.vv v8, v8, v9 ; RV32-NEXT: vasub.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vasub_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vasub_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vasub.mask.nxv1i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 1 x i64> @intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i64> @intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vasub.vv v8, v9, v10, v0.t ; RV32-NEXT: vasub.vv v8, v9, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vasub.nxv2i64.i64(
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_vasub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 2 x i64> @intrinsic_vasub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vasub_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vasub_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vasub.vv v8, v8, v10 ; RV32-NEXT: vasub.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vasub_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vasub_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vasub.mask.nxv2i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 2 x i64> @intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i64> @intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vasub.vv v8, v10, v12, v0.t ; RV32-NEXT: vasub.vv v8, v10, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vasub.nxv4i64.i64(
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_vasub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 4 x i64> @intrinsic_vasub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vasub_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vasub_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vasub.vv v8, v8, v12 ; RV32-NEXT: vasub.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vasub_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vasub_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vasub.mask.nxv4i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 4 x i64> @intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i64> @intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vasub.vv v8, v12, v16, v0.t ; RV32-NEXT: vasub.vv v8, v12, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vasub.nxv8i64.i64(
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vasub_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 8 x i64> @intrinsic_vasub_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vasub_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vasub_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vasub.vv v8, v8, v16 ; RV32-NEXT: vasub.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vasub_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vasub_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vasub.mask.nxv8i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 8 x i64> @intrinsic_vasub_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i64> @intrinsic_vasub_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vasub_mask_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vasub_mask_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vasub.vv v8, v16, v24, v0.t ; RV32-NEXT: vasub.vv v8, v16, v24, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vasub_mask_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vasub_mask_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
Show All 12 Lines

llvm/test/CodeGen/RISCV/rvv/vasubu.ll

Show First 20 Lines • Show All 1,853 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vasubu.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 1 x i64> @intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vasubu.vv v8, v8, v9 ; RV32-NEXT: vasubu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vasubu.mask.nxv1i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 1 x i64> @intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i64> @intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vasubu.vv v8, v9, v10, v0.t ; RV32-NEXT: vasubu.vv v8, v9, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vasubu.nxv2i64.i64(
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 2 x i64> @intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vasubu.vv v8, v8, v10 ; RV32-NEXT: vasubu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vasubu.mask.nxv2i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 2 x i64> @intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i64> @intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vasubu.vv v8, v10, v12, v0.t ; RV32-NEXT: vasubu.vv v8, v10, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vasubu.nxv4i64.i64(
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 4 x i64> @intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vasubu.vv v8, v8, v12 ; RV32-NEXT: vasubu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vasubu.mask.nxv4i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 4 x i64> @intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i64> @intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vasubu.vv v8, v12, v16, v0.t ; RV32-NEXT: vasubu.vv v8, v12, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vasubu.nxv8i64.i64(
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 8 x i64> @intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vasubu.vv v8, v8, v16 ; RV32-NEXT: vasubu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vasubu.mask.nxv8i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 8 x i64> @intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i64> @intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vasubu.vv v8, v16, v24, v0.t ; RV32-NEXT: vasubu.vv v8, v16, v24, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
Show All 12 Lines

llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll

Show First 20 Lines • Show All 1,891 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vdiv.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vdiv_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vdiv_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vdiv_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vdiv_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vdiv.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vdiv.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vdiv.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vdiv_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vdiv_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t ; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vdiv.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vdiv.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 11 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vdiv.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vdiv_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vdiv_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vdiv_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vdiv_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vdiv.vv v8, v8, v10 ; CHECK-NEXT: vdiv.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vdiv.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vdiv.nxv2i64.i64(
<vscale x 2 x i64> undef, <vscale x 2 x i64> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vdiv.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vdiv_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vdiv_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vdiv.vv v8, v10, v12, v0.t ; CHECK-NEXT: vdiv.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vdiv.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vdiv.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 11 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vdiv.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vdiv_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vdiv_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vdiv_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vdiv_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: vdiv.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vdiv.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vdiv.nxv4i64.i64(
<vscale x 4 x i64> undef, <vscale x 4 x i64> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vdiv.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vdiv_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vdiv_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vdiv.vv v8, v12, v16, v0.t ; CHECK-NEXT: vdiv.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vdiv.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vdiv.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 11 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vdiv.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vdiv_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vdiv_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vdiv_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vdiv_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: vdiv.vv v8, v8, v16
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vdiv.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vdiv.nxv8i64.i64(
<vscale x 8 x i64> undef, <vscale x 8 x i64> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
Show All 12 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vdiv.mask.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vdiv_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vdiv_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v24, (a0), zero ; CHECK-NEXT: vlse64.v v24, (a0), zero
; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vdiv.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vdiv.mask.nxv8i64.i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll

Show First 20 Lines • Show All 872 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vdiv_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) { define <vscale x 1 x i64> @vdiv_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; RV32-LABEL: vdiv_vx_nxv1i64: ; RV32-LABEL: vdiv_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vdiv.vv v8, v8, v9 ; RV32-NEXT: vdiv.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdiv_vx_nxv1i64: ; RV64-LABEL: vdiv_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
Show All 11 Lines
; RV32-V-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: addi sp, sp, -16
; RV32-V-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16
; RV32-V-NEXT: lui a0, 748983 ; RV32-V-NEXT: lui a0, 748983
; RV32-V-NEXT: addi a0, a0, -586 ; RV32-V-NEXT: addi a0, a0, -586
; RV32-V-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: sw a0, 12(sp)
; RV32-V-NEXT: lui a0, 898779 ; RV32-V-NEXT: lui a0, 898779
; RV32-V-NEXT: addi a0, a0, 1755 ; RV32-V-NEXT: addi a0, a0, 1755
; RV32-V-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: sw a0, 8(sp)
; RV32-V-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-V-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: addi a0, sp, 8
; RV32-V-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-V-NEXT: vlse64.v v9, (a0), zero ; RV32-V-NEXT: vlse64.v v9, (a0), zero
; RV32-V-NEXT: vmulh.vv v8, v8, v9 ; RV32-V-NEXT: vmulh.vv v8, v8, v9
; RV32-V-NEXT: li a0, 63 ; RV32-V-NEXT: li a0, 63
; RV32-V-NEXT: vsrl.vx v9, v8, a0 ; RV32-V-NEXT: vsrl.vx v9, v8, a0
; RV32-V-NEXT: vsra.vi v8, v8, 1 ; RV32-V-NEXT: vsra.vi v8, v8, 1
; RV32-V-NEXT: vadd.vv v8, v8, v9 ; RV32-V-NEXT: vadd.vv v8, v8, v9
; RV32-V-NEXT: addi sp, sp, 16 ; RV32-V-NEXT: addi sp, sp, 16
; RV32-V-NEXT: ret ; RV32-V-NEXT: ret
Show All 34 Lines
define <vscale x 2 x i64> @vdiv_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) { define <vscale x 2 x i64> @vdiv_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; RV32-LABEL: vdiv_vx_nxv2i64: ; RV32-LABEL: vdiv_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vdiv.vv v8, v8, v10 ; RV32-NEXT: vdiv.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdiv_vx_nxv2i64: ; RV64-LABEL: vdiv_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
Show All 11 Lines
; RV32-V-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: addi sp, sp, -16
; RV32-V-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16
; RV32-V-NEXT: lui a0, 748983 ; RV32-V-NEXT: lui a0, 748983
; RV32-V-NEXT: addi a0, a0, -586 ; RV32-V-NEXT: addi a0, a0, -586
; RV32-V-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: sw a0, 12(sp)
; RV32-V-NEXT: lui a0, 898779 ; RV32-V-NEXT: lui a0, 898779
; RV32-V-NEXT: addi a0, a0, 1755 ; RV32-V-NEXT: addi a0, a0, 1755
; RV32-V-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: sw a0, 8(sp)
; RV32-V-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-V-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: addi a0, sp, 8
; RV32-V-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-V-NEXT: vlse64.v v10, (a0), zero ; RV32-V-NEXT: vlse64.v v10, (a0), zero
; RV32-V-NEXT: vmulh.vv v8, v8, v10 ; RV32-V-NEXT: vmulh.vv v8, v8, v10
; RV32-V-NEXT: li a0, 63 ; RV32-V-NEXT: li a0, 63
; RV32-V-NEXT: vsrl.vx v10, v8, a0 ; RV32-V-NEXT: vsrl.vx v10, v8, a0
; RV32-V-NEXT: vsra.vi v8, v8, 1 ; RV32-V-NEXT: vsra.vi v8, v8, 1
; RV32-V-NEXT: vadd.vv v8, v8, v10 ; RV32-V-NEXT: vadd.vv v8, v8, v10
; RV32-V-NEXT: addi sp, sp, 16 ; RV32-V-NEXT: addi sp, sp, 16
; RV32-V-NEXT: ret ; RV32-V-NEXT: ret
Show All 34 Lines
define <vscale x 4 x i64> @vdiv_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) { define <vscale x 4 x i64> @vdiv_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; RV32-LABEL: vdiv_vx_nxv4i64: ; RV32-LABEL: vdiv_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vdiv.vv v8, v8, v12 ; RV32-NEXT: vdiv.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdiv_vx_nxv4i64: ; RV64-LABEL: vdiv_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
Show All 11 Lines
; RV32-V-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: addi sp, sp, -16
; RV32-V-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16
; RV32-V-NEXT: lui a0, 748983 ; RV32-V-NEXT: lui a0, 748983
; RV32-V-NEXT: addi a0, a0, -586 ; RV32-V-NEXT: addi a0, a0, -586
; RV32-V-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: sw a0, 12(sp)
; RV32-V-NEXT: lui a0, 898779 ; RV32-V-NEXT: lui a0, 898779
; RV32-V-NEXT: addi a0, a0, 1755 ; RV32-V-NEXT: addi a0, a0, 1755
; RV32-V-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: sw a0, 8(sp)
; RV32-V-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-V-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: addi a0, sp, 8
; RV32-V-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-V-NEXT: vlse64.v v12, (a0), zero ; RV32-V-NEXT: vlse64.v v12, (a0), zero
; RV32-V-NEXT: vmulh.vv v8, v8, v12 ; RV32-V-NEXT: vmulh.vv v8, v8, v12
; RV32-V-NEXT: li a0, 63 ; RV32-V-NEXT: li a0, 63
; RV32-V-NEXT: vsrl.vx v12, v8, a0 ; RV32-V-NEXT: vsrl.vx v12, v8, a0
; RV32-V-NEXT: vsra.vi v8, v8, 1 ; RV32-V-NEXT: vsra.vi v8, v8, 1
; RV32-V-NEXT: vadd.vv v8, v8, v12 ; RV32-V-NEXT: vadd.vv v8, v8, v12
; RV32-V-NEXT: addi sp, sp, 16 ; RV32-V-NEXT: addi sp, sp, 16
; RV32-V-NEXT: ret ; RV32-V-NEXT: ret
Show All 34 Lines
define <vscale x 8 x i64> @vdiv_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i64> @vdiv_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: vdiv_vx_nxv8i64: ; RV32-LABEL: vdiv_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vdiv.vv v8, v8, v16 ; RV32-NEXT: vdiv.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdiv_vx_nxv8i64: ; RV64-LABEL: vdiv_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 11 Lines
; RV32-V-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: addi sp, sp, -16
; RV32-V-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16
; RV32-V-NEXT: lui a0, 748983 ; RV32-V-NEXT: lui a0, 748983
; RV32-V-NEXT: addi a0, a0, -586 ; RV32-V-NEXT: addi a0, a0, -586
; RV32-V-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: sw a0, 12(sp)
; RV32-V-NEXT: lui a0, 898779 ; RV32-V-NEXT: lui a0, 898779
; RV32-V-NEXT: addi a0, a0, 1755 ; RV32-V-NEXT: addi a0, a0, 1755
; RV32-V-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: sw a0, 8(sp)
; RV32-V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-V-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: addi a0, sp, 8
; RV32-V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-V-NEXT: vlse64.v v16, (a0), zero ; RV32-V-NEXT: vlse64.v v16, (a0), zero
; RV32-V-NEXT: vmulh.vv v8, v8, v16 ; RV32-V-NEXT: vmulh.vv v8, v8, v16
; RV32-V-NEXT: li a0, 63 ; RV32-V-NEXT: li a0, 63
; RV32-V-NEXT: vsrl.vx v16, v8, a0 ; RV32-V-NEXT: vsrl.vx v16, v8, a0
; RV32-V-NEXT: vsra.vi v8, v8, 1 ; RV32-V-NEXT: vsra.vi v8, v8, 1
; RV32-V-NEXT: vadd.vv v8, v8, v16 ; RV32-V-NEXT: vadd.vv v8, v8, v16
; RV32-V-NEXT: addi sp, sp, 16 ; RV32-V-NEXT: addi sp, sp, 16
; RV32-V-NEXT: ret ; RV32-V-NEXT: ret
Show All 24 Lines

llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll

Show First 20 Lines • Show All 961 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vdiv_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i64> @vdiv_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vdiv_vx_nxv1i64: ; RV32-LABEL: vdiv_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vdiv.vv v8, v8, v9, v0.t ; RV32-NEXT: vdiv.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdiv_vx_nxv1i64: ; RV64-LABEL: vdiv_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vdiv.vx v8, v8, a0, v0.t ; RV64-NEXT: vdiv.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i64> @llvm.vp.sdiv.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i64> @llvm.vp.sdiv.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v ret <vscale x 1 x i64> %v
} }
define <vscale x 1 x i64> @vdiv_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 1 x i64> @vdiv_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vdiv_vx_nxv1i64_unmasked: ; RV32-LABEL: vdiv_vx_nxv1i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vdiv.vv v8, v8, v9 ; RV32-NEXT: vdiv.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdiv_vx_nxv1i64_unmasked: ; RV64-LABEL: vdiv_vx_nxv1i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <vscale x 2 x i64> @vdiv_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i64> @vdiv_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vdiv_vx_nxv2i64: ; RV32-LABEL: vdiv_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vdiv.vv v8, v8, v10, v0.t ; RV32-NEXT: vdiv.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdiv_vx_nxv2i64: ; RV64-LABEL: vdiv_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vdiv.vx v8, v8, a0, v0.t ; RV64-NEXT: vdiv.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i64> @llvm.vp.sdiv.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl) %v = call <vscale x 2 x i64> @llvm.vp.sdiv.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
define <vscale x 2 x i64> @vdiv_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 2 x i64> @vdiv_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vdiv_vx_nxv2i64_unmasked: ; RV32-LABEL: vdiv_vx_nxv2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vdiv.vv v8, v8, v10 ; RV32-NEXT: vdiv.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdiv_vx_nxv2i64_unmasked: ; RV64-LABEL: vdiv_vx_nxv2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <vscale x 4 x i64> @vdiv_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i64> @vdiv_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vdiv_vx_nxv4i64: ; RV32-LABEL: vdiv_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vdiv.vv v8, v8, v12, v0.t ; RV32-NEXT: vdiv.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdiv_vx_nxv4i64: ; RV64-LABEL: vdiv_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vdiv.vx v8, v8, a0, v0.t ; RV64-NEXT: vdiv.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i64> @llvm.vp.sdiv.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl) %v = call <vscale x 4 x i64> @llvm.vp.sdiv.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v ret <vscale x 4 x i64> %v
} }
define <vscale x 4 x i64> @vdiv_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 4 x i64> @vdiv_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vdiv_vx_nxv4i64_unmasked: ; RV32-LABEL: vdiv_vx_nxv4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vdiv.vv v8, v8, v12 ; RV32-NEXT: vdiv.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdiv_vx_nxv4i64_unmasked: ; RV64-LABEL: vdiv_vx_nxv4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <vscale x 8 x i64> @vdiv_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vdiv_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vdiv_vx_nxv8i64: ; RV32-LABEL: vdiv_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vdiv.vv v8, v8, v16, v0.t ; RV32-NEXT: vdiv.vv v8, v8, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdiv_vx_nxv8i64: ; RV64-LABEL: vdiv_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vdiv.vx v8, v8, a0, v0.t ; RV64-NEXT: vdiv.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i64> @llvm.vp.sdiv.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i64> @llvm.vp.sdiv.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i64> @vdiv_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 8 x i64> @vdiv_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vdiv_vx_nxv8i64_unmasked: ; RV32-LABEL: vdiv_vx_nxv8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vdiv.vv v8, v8, v16 ; RV32-NEXT: vdiv.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdiv_vx_nxv8i64_unmasked: ; RV64-LABEL: vdiv_vx_nxv8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 10 Lines

llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll

Show First 20 Lines • Show All 1,891 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vdivu.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vdivu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vdivu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vdivu_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vdivu_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vdivu.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vdivu.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vdivu.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vdivu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vdivu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vdivu.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vdivu.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 11 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vdivu.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vdivu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vdivu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vdivu_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vdivu_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: vdivu.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vdivu.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vdivu.nxv2i64.i64(
<vscale x 2 x i64> undef, <vscale x 2 x i64> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vdivu.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vdivu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vdivu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vdivu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vdivu.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vdivu.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vdivu.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 11 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vdivu.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vdivu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vdivu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vdivu_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vdivu_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: vdivu.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vdivu.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vdivu.nxv4i64.i64(
<vscale x 4 x i64> undef, <vscale x 4 x i64> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vdivu.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vdivu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vdivu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vdivu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vdivu.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vdivu.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vdivu.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 11 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vdivu.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vdivu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vdivu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vdivu_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vdivu_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: vdivu.vv v8, v8, v16
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vdivu.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vdivu.nxv8i64.i64(
<vscale x 8 x i64> undef, <vscale x 8 x i64> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
Show All 12 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vdivu.mask.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vdivu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vdivu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v24, (a0), zero ; CHECK-NEXT: vlse64.v v24, (a0), zero
; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vdivu.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vdivu.mask.nxv8i64.i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll

Show First 20 Lines • Show All 797 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vdivu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) { define <vscale x 1 x i64> @vdivu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; RV32-LABEL: vdivu_vx_nxv1i64: ; RV32-LABEL: vdivu_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vdivu.vv v8, v8, v9 ; RV32-NEXT: vdivu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdivu_vx_nxv1i64: ; RV64-LABEL: vdivu_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
Show All 9 Lines
; RV32-V-LABEL: vdivu_vi_nxv1i64_0: ; RV32-V-LABEL: vdivu_vi_nxv1i64_0:
; RV32-V: # %bb.0: ; RV32-V: # %bb.0:
; RV32-V-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: addi sp, sp, -16
; RV32-V-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16
; RV32-V-NEXT: lui a0, 131072 ; RV32-V-NEXT: lui a0, 131072
; RV32-V-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: sw a0, 12(sp)
; RV32-V-NEXT: li a0, 1 ; RV32-V-NEXT: li a0, 1
; RV32-V-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: sw a0, 8(sp)
; RV32-V-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-V-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: addi a0, sp, 8
; RV32-V-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-V-NEXT: vlse64.v v9, (a0), zero ; RV32-V-NEXT: vlse64.v v9, (a0), zero
; RV32-V-NEXT: vmulhu.vv v8, v8, v9 ; RV32-V-NEXT: vmulhu.vv v8, v8, v9
; RV32-V-NEXT: li a0, 61 ; RV32-V-NEXT: li a0, 61
; RV32-V-NEXT: vsrl.vx v8, v8, a0 ; RV32-V-NEXT: vsrl.vx v8, v8, a0
; RV32-V-NEXT: addi sp, sp, 16 ; RV32-V-NEXT: addi sp, sp, 16
; RV32-V-NEXT: ret ; RV32-V-NEXT: ret
; ;
; ZVE64X-LABEL: vdivu_vi_nxv1i64_0: ; ZVE64X-LABEL: vdivu_vi_nxv1i64_0:
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
define <vscale x 2 x i64> @vdivu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) { define <vscale x 2 x i64> @vdivu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; RV32-LABEL: vdivu_vx_nxv2i64: ; RV32-LABEL: vdivu_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vdivu.vv v8, v8, v10 ; RV32-NEXT: vdivu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdivu_vx_nxv2i64: ; RV64-LABEL: vdivu_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
Show All 9 Lines
; RV32-V-LABEL: vdivu_vi_nxv2i64_0: ; RV32-V-LABEL: vdivu_vi_nxv2i64_0:
; RV32-V: # %bb.0: ; RV32-V: # %bb.0:
; RV32-V-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: addi sp, sp, -16
; RV32-V-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16
; RV32-V-NEXT: lui a0, 131072 ; RV32-V-NEXT: lui a0, 131072
; RV32-V-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: sw a0, 12(sp)
; RV32-V-NEXT: li a0, 1 ; RV32-V-NEXT: li a0, 1
; RV32-V-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: sw a0, 8(sp)
; RV32-V-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-V-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: addi a0, sp, 8
; RV32-V-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-V-NEXT: vlse64.v v10, (a0), zero ; RV32-V-NEXT: vlse64.v v10, (a0), zero
; RV32-V-NEXT: vmulhu.vv v8, v8, v10 ; RV32-V-NEXT: vmulhu.vv v8, v8, v10
; RV32-V-NEXT: li a0, 61 ; RV32-V-NEXT: li a0, 61
; RV32-V-NEXT: vsrl.vx v8, v8, a0 ; RV32-V-NEXT: vsrl.vx v8, v8, a0
; RV32-V-NEXT: addi sp, sp, 16 ; RV32-V-NEXT: addi sp, sp, 16
; RV32-V-NEXT: ret ; RV32-V-NEXT: ret
; ;
; ZVE64X-LABEL: vdivu_vi_nxv2i64_0: ; ZVE64X-LABEL: vdivu_vi_nxv2i64_0:
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
define <vscale x 4 x i64> @vdivu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) { define <vscale x 4 x i64> @vdivu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; RV32-LABEL: vdivu_vx_nxv4i64: ; RV32-LABEL: vdivu_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vdivu.vv v8, v8, v12 ; RV32-NEXT: vdivu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdivu_vx_nxv4i64: ; RV64-LABEL: vdivu_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
Show All 9 Lines
; RV32-V-LABEL: vdivu_vi_nxv4i64_0: ; RV32-V-LABEL: vdivu_vi_nxv4i64_0:
; RV32-V: # %bb.0: ; RV32-V: # %bb.0:
; RV32-V-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: addi sp, sp, -16
; RV32-V-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16
; RV32-V-NEXT: lui a0, 131072 ; RV32-V-NEXT: lui a0, 131072
; RV32-V-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: sw a0, 12(sp)
; RV32-V-NEXT: li a0, 1 ; RV32-V-NEXT: li a0, 1
; RV32-V-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: sw a0, 8(sp)
; RV32-V-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-V-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: addi a0, sp, 8
; RV32-V-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-V-NEXT: vlse64.v v12, (a0), zero ; RV32-V-NEXT: vlse64.v v12, (a0), zero
; RV32-V-NEXT: vmulhu.vv v8, v8, v12 ; RV32-V-NEXT: vmulhu.vv v8, v8, v12
; RV32-V-NEXT: li a0, 61 ; RV32-V-NEXT: li a0, 61
; RV32-V-NEXT: vsrl.vx v8, v8, a0 ; RV32-V-NEXT: vsrl.vx v8, v8, a0
; RV32-V-NEXT: addi sp, sp, 16 ; RV32-V-NEXT: addi sp, sp, 16
; RV32-V-NEXT: ret ; RV32-V-NEXT: ret
; ;
; ZVE64X-LABEL: vdivu_vi_nxv4i64_0: ; ZVE64X-LABEL: vdivu_vi_nxv4i64_0:
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
define <vscale x 8 x i64> @vdivu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i64> @vdivu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: vdivu_vx_nxv8i64: ; RV32-LABEL: vdivu_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vdivu.vv v8, v8, v16 ; RV32-NEXT: vdivu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdivu_vx_nxv8i64: ; RV64-LABEL: vdivu_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 9 Lines
; RV32-V-LABEL: vdivu_vi_nxv8i64_0: ; RV32-V-LABEL: vdivu_vi_nxv8i64_0:
; RV32-V: # %bb.0: ; RV32-V: # %bb.0:
; RV32-V-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: addi sp, sp, -16
; RV32-V-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16
; RV32-V-NEXT: lui a0, 131072 ; RV32-V-NEXT: lui a0, 131072
; RV32-V-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: sw a0, 12(sp)
; RV32-V-NEXT: li a0, 1 ; RV32-V-NEXT: li a0, 1
; RV32-V-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: sw a0, 8(sp)
; RV32-V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-V-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: addi a0, sp, 8
; RV32-V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-V-NEXT: vlse64.v v16, (a0), zero ; RV32-V-NEXT: vlse64.v v16, (a0), zero
; RV32-V-NEXT: vmulhu.vv v8, v8, v16 ; RV32-V-NEXT: vmulhu.vv v8, v8, v16
; RV32-V-NEXT: li a0, 61 ; RV32-V-NEXT: li a0, 61
; RV32-V-NEXT: vsrl.vx v8, v8, a0 ; RV32-V-NEXT: vsrl.vx v8, v8, a0
; RV32-V-NEXT: addi sp, sp, 16 ; RV32-V-NEXT: addi sp, sp, 16
; RV32-V-NEXT: ret ; RV32-V-NEXT: ret
; ;
; ZVE64X-LABEL: vdivu_vi_nxv8i64_0: ; ZVE64X-LABEL: vdivu_vi_nxv8i64_0:
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll

Show First 20 Lines • Show All 960 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vdivu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i64> @vdivu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vdivu_vx_nxv1i64: ; RV32-LABEL: vdivu_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vdivu.vv v8, v8, v9, v0.t ; RV32-NEXT: vdivu.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdivu_vx_nxv1i64: ; RV64-LABEL: vdivu_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vdivu.vx v8, v8, a0, v0.t ; RV64-NEXT: vdivu.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i64> @llvm.vp.udiv.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i64> @llvm.vp.udiv.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v ret <vscale x 1 x i64> %v
} }
define <vscale x 1 x i64> @vdivu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 1 x i64> @vdivu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vdivu_vx_nxv1i64_unmasked: ; RV32-LABEL: vdivu_vx_nxv1i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vdivu.vv v8, v8, v9 ; RV32-NEXT: vdivu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdivu_vx_nxv1i64_unmasked: ; RV64-LABEL: vdivu_vx_nxv1i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <vscale x 2 x i64> @vdivu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i64> @vdivu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vdivu_vx_nxv2i64: ; RV32-LABEL: vdivu_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vdivu.vv v8, v8, v10, v0.t ; RV32-NEXT: vdivu.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdivu_vx_nxv2i64: ; RV64-LABEL: vdivu_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vdivu.vx v8, v8, a0, v0.t ; RV64-NEXT: vdivu.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i64> @llvm.vp.udiv.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl) %v = call <vscale x 2 x i64> @llvm.vp.udiv.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
define <vscale x 2 x i64> @vdivu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 2 x i64> @vdivu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vdivu_vx_nxv2i64_unmasked: ; RV32-LABEL: vdivu_vx_nxv2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vdivu.vv v8, v8, v10 ; RV32-NEXT: vdivu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdivu_vx_nxv2i64_unmasked: ; RV64-LABEL: vdivu_vx_nxv2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <vscale x 4 x i64> @vdivu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i64> @vdivu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vdivu_vx_nxv4i64: ; RV32-LABEL: vdivu_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vdivu.vv v8, v8, v12, v0.t ; RV32-NEXT: vdivu.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdivu_vx_nxv4i64: ; RV64-LABEL: vdivu_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vdivu.vx v8, v8, a0, v0.t ; RV64-NEXT: vdivu.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i64> @llvm.vp.udiv.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl) %v = call <vscale x 4 x i64> @llvm.vp.udiv.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v ret <vscale x 4 x i64> %v
} }
define <vscale x 4 x i64> @vdivu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 4 x i64> @vdivu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vdivu_vx_nxv4i64_unmasked: ; RV32-LABEL: vdivu_vx_nxv4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vdivu.vv v8, v8, v12 ; RV32-NEXT: vdivu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdivu_vx_nxv4i64_unmasked: ; RV64-LABEL: vdivu_vx_nxv4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <vscale x 8 x i64> @vdivu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vdivu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vdivu_vx_nxv8i64: ; RV32-LABEL: vdivu_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vdivu.vv v8, v8, v16, v0.t ; RV32-NEXT: vdivu.vv v8, v8, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdivu_vx_nxv8i64: ; RV64-LABEL: vdivu_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vdivu.vx v8, v8, a0, v0.t ; RV64-NEXT: vdivu.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i64> @llvm.vp.udiv.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i64> @llvm.vp.udiv.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i64> @vdivu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 8 x i64> @vdivu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vdivu_vx_nxv8i64_unmasked: ; RV32-LABEL: vdivu_vx_nxv8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vdivu.vv v8, v8, v16 ; RV32-NEXT: vdivu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vdivu_vx_nxv8i64_unmasked: ; RV64-LABEL: vdivu_vx_nxv8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 10 Lines

llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll

Show First 20 Lines • Show All 1,593 Lines • ▼ Show 20 Lines
); );
define <vscale x 1 x i64> @intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu
; CHECK-NEXT: vmacc.vv v8, v10, v9 ; CHECK-NEXT: vmacc.vv v8, v10, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmacc.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmacc.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64(
i32, i32); i32, i32);
define <vscale x 1 x i64> @intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu
; CHECK-NEXT: vmacc.vv v8, v10, v9, v0.t ; CHECK-NEXT: vmacc.vv v8, v10, v9, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 14 Lines
); );
define <vscale x 2 x i64> @intrinsic_vmacc_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, i32 %3) nounwind { define <vscale x 2 x i64> @intrinsic_vmacc_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i64_i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i64_i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu
; CHECK-NEXT: vmacc.vv v8, v12, v10 ; CHECK-NEXT: vmacc.vv v8, v12, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmacc.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmacc.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64(
i32, i32); i32, i32);
define <vscale x 2 x i64> @intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu
; CHECK-NEXT: vmacc.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmacc.vv v8, v12, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 14 Lines
); );
define <vscale x 4 x i64> @intrinsic_vmacc_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, i32 %3) nounwind { define <vscale x 4 x i64> @intrinsic_vmacc_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i64_i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i64_i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
; CHECK-NEXT: vmacc.vv v8, v16, v12 ; CHECK-NEXT: vmacc.vv v8, v16, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmacc.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmacc.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64(
i32, i32); i32, i32);
define <vscale x 4 x i64> @intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
; CHECK-NEXT: vmacc.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmacc.vv v8, v16, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll

Show First 20 Lines • Show All 806 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmadc_vx_nxv1i1_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmadc_vx_nxv1i1_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmadc_vx_nxv1i1_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmadc_vx_nxv1i1_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vmadc.vv v0, v8, v9 ; CHECK-NEXT: vmadc.vv v0, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmadc_vx_nxv2i1_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmadc_vx_nxv2i1_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmadc_vx_nxv2i1_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmadc_vx_nxv2i1_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vmadc.vv v0, v8, v10 ; CHECK-NEXT: vmadc.vv v0, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmadc_vx_nxv4i1_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmadc_vx_nxv4i1_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmadc_vx_nxv4i1_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmadc_vx_nxv4i1_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmadc.vv v0, v8, v12 ; CHECK-NEXT: vmadc.vv v0, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i64.i64( declare <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i64.i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64, i64,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmadc_vx_nxv8i1_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmadc_vx_nxv8i1_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmadc_vx_nxv8i1_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vmadc_vx_nxv8i1_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmadc.vv v0, v8, v16 ; CHECK-NEXT: vmadc.vv v0, v8, v16
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i64.i64( %a = call <vscale x 8 x i1> @llvm.riscv.vmadc.nxv8i64.i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i64 %1, i64 %1,
▲ Show 20 Lines • Show All 334 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll

Show First 20 Lines • Show All 927 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vmadc.vvm v9, v8, v10, v0 ; CHECK-NEXT: vmadc.vvm v9, v8, v10, v0
; CHECK-NEXT: vmv.v.v v0, v9 ; CHECK-NEXT: vmv.v.v v0, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 11 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmadc.vvm v10, v8, v12, v0 ; CHECK-NEXT: vmadc.vvm v10, v8, v12, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 11 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmadc.vvm v12, v8, v16, v0 ; CHECK-NEXT: vmadc.vvm v12, v8, v16, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 11 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v24, (a0), zero ; CHECK-NEXT: vlse64.v v24, (a0), zero
; CHECK-NEXT: vmadc.vvm v16, v8, v24, v0 ; CHECK-NEXT: vmadc.vvm v16, v8, v24, v0
; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i64.i64( %a = call <vscale x 8 x i1> @llvm.riscv.vmadc.carry.in.nxv8i64.i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
▲ Show 20 Lines • Show All 380 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll

Show First 20 Lines • Show All 1,559 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmadd.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vmadd_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vmadd_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i64_i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i64_i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu
; CHECK-NEXT: vmadd.vv v8, v10, v9 ; CHECK-NEXT: vmadd.vv v8, v10, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmadd.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmadd.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64(
i32, i32); i32, i32);
define <vscale x 1 x i64> @intrinsic_vmadd_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vmadd_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i64_i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i64_i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu
; CHECK-NEXT: vmadd.vv v8, v10, v9, v0.t ; CHECK-NEXT: vmadd.vv v8, v10, v9, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 13 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vmadd.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vmadd_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, i32 %3) nounwind { define <vscale x 2 x i64> @intrinsic_vmadd_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i64_i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i64_i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu
; CHECK-NEXT: vmadd.vv v8, v12, v10 ; CHECK-NEXT: vmadd.vv v8, v12, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmadd.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmadd.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64(
i32, i32); i32, i32);
define <vscale x 2 x i64> @intrinsic_vmadd_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vmadd_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i64_i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i64_i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu
; CHECK-NEXT: vmadd.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmadd.vv v8, v12, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 13 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vmadd.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vmadd_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, i32 %3) nounwind { define <vscale x 4 x i64> @intrinsic_vmadd_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i64_i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i64_i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
; CHECK-NEXT: vmadd.vv v8, v16, v12 ; CHECK-NEXT: vmadd.vv v8, v16, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmadd.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmadd.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64(
i32, i32); i32, i32);
define <vscale x 4 x i64> @intrinsic_vmadd_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vmadd_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i64_i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i64_i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
; CHECK-NEXT: vmadd.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmadd.vv v8, v16, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll

Show First 20 Lines • Show All 454 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vmadd_vx_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i64 %c) { define <vscale x 1 x i64> @vmadd_vx_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i64 %c) {
; RV32-LABEL: vmadd_vx_nxv1i64: ; RV32-LABEL: vmadd_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmadd.vv v8, v10, v9 ; RV32-NEXT: vmadd.vv v8, v10, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmadd_vx_nxv1i64: ; RV64-LABEL: vmadd_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
Show All 19 Lines
define <vscale x 2 x i64> @vmadd_vx_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i64 %c) { define <vscale x 2 x i64> @vmadd_vx_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i64 %c) {
; RV32-LABEL: vmadd_vx_nxv2i64: ; RV32-LABEL: vmadd_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmacc.vv v8, v10, v12 ; RV32-NEXT: vmacc.vv v8, v10, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmadd_vx_nxv2i64: ; RV64-LABEL: vmadd_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
Show All 19 Lines
define <vscale x 4 x i64> @vmadd_vx_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, i64 %c) { define <vscale x 4 x i64> @vmadd_vx_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, i64 %c) {
; RV32-LABEL: vmadd_vx_nxv4i64: ; RV32-LABEL: vmadd_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmadd.vv v8, v16, v12 ; RV32-NEXT: vmadd.vv v8, v16, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmadd_vx_nxv4i64: ; RV64-LABEL: vmadd_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
Show All 20 Lines
define <vscale x 8 x i64> @vmadd_vx_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, i64 %c) { define <vscale x 8 x i64> @vmadd_vx_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, i64 %c) {
; RV32-LABEL: vmadd_vx_nxv8i64: ; RV32-LABEL: vmadd_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vmacc.vv v8, v16, v24 ; RV32-NEXT: vmacc.vv v8, v16, v24
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmadd_vx_nxv8i64: ; RV64-LABEL: vmadd_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vmacc.vx v8, a0, v16 ; RV64-NEXT: vmacc.vx v8, a0, v16
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %c, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 %c, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%x = mul <vscale x 8 x i64> %vb, %splat %x = mul <vscale x 8 x i64> %vb, %splat
%y = add <vscale x 8 x i64> %x, %va %y = add <vscale x 8 x i64> %x, %va
ret <vscale x 8 x i64> %y ret <vscale x 8 x i64> %y
} }

llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll

Show First 20 Lines • Show All 1,891 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmax.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vmax_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vmax_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmax_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmax_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmax.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmax.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmax.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vmax_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vmax_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmax.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmax.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 11 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vmax.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vmax_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vmax_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmax_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmax_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: vmax.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmax.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmax.nxv2i64.i64(
<vscale x 2 x i64> undef, <vscale x 2 x i64> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vmax.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vmax_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vmax_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmax.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmax.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmax.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmax.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 11 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vmax.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vmax_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vmax_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmax_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmax_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: vmax.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmax.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmax.nxv4i64.i64(
<vscale x 4 x i64> undef, <vscale x 4 x i64> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vmax.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vmax_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vmax_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmax.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmax.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmax.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmax.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 11 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmax.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vmax_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vmax_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmax_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vmax_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: vmax.vv v8, v8, v16
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmax.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmax.nxv8i64.i64(
<vscale x 8 x i64> undef, <vscale x 8 x i64> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
Show All 12 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmax.mask.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vmax_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vmax_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v24, (a0), zero ; CHECK-NEXT: vlse64.v v24, (a0), zero
; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmax.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmax.mask.nxv8i64.i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll

Show First 20 Lines • Show All 698 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vmax_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) { define <vscale x 1 x i64> @vmax_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; RV32-LABEL: vmax_vx_nxv1i64: ; RV32-LABEL: vmax_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vmax.vv v8, v8, v9 ; RV32-NEXT: vmax.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmax_vx_nxv1i64: ; RV64-LABEL: vmax_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
Show All 33 Lines
define <vscale x 2 x i64> @vmax_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) { define <vscale x 2 x i64> @vmax_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; RV32-LABEL: vmax_vx_nxv2i64: ; RV32-LABEL: vmax_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmax.vv v8, v8, v10 ; RV32-NEXT: vmax.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmax_vx_nxv2i64: ; RV64-LABEL: vmax_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
Show All 33 Lines
define <vscale x 4 x i64> @vmax_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) { define <vscale x 4 x i64> @vmax_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; RV32-LABEL: vmax_vx_nxv4i64: ; RV32-LABEL: vmax_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmax.vv v8, v8, v12 ; RV32-NEXT: vmax.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmax_vx_nxv4i64: ; RV64-LABEL: vmax_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
Show All 33 Lines
define <vscale x 8 x i64> @vmax_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i64> @vmax_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: vmax_vx_nxv8i64: ; RV32-LABEL: vmax_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmax.vv v8, v8, v16 ; RV32-NEXT: vmax.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmax_vx_nxv8i64: ; RV64-LABEL: vmax_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 23 Lines

llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll

Show First 20 Lines • Show All 1,891 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmaxu.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vmaxu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vmaxu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmaxu_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vmaxu.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmaxu.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmaxu.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmaxu.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vmaxu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vmaxu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmaxu.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmaxu.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 11 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vmaxu.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vmaxu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vmaxu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmaxu_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: vmaxu.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmaxu.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmaxu.nxv2i64.i64(
<vscale x 2 x i64> undef, <vscale x 2 x i64> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vmaxu.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vmaxu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vmaxu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmaxu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmaxu.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmaxu.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmaxu.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 11 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vmaxu.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vmaxu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vmaxu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmaxu_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmaxu.vv v8, v8, v12 ; CHECK-NEXT: vmaxu.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmaxu.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmaxu.nxv4i64.i64(
<vscale x 4 x i64> undef, <vscale x 4 x i64> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vmaxu.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vmaxu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vmaxu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmaxu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmaxu.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmaxu.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmaxu.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 11 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmaxu.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vmaxu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vmaxu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmaxu_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vmaxu_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmaxu.vv v8, v8, v16 ; CHECK-NEXT: vmaxu.vv v8, v8, v16
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmaxu.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmaxu.nxv8i64.i64(
<vscale x 8 x i64> undef, <vscale x 8 x i64> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
Show All 12 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmaxu.mask.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vmaxu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vmaxu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v24, (a0), zero ; CHECK-NEXT: vlse64.v v24, (a0), zero
; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmaxu.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmaxu.mask.nxv8i64.i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll

Show First 20 Lines • Show All 698 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vmax_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) { define <vscale x 1 x i64> @vmax_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; RV32-LABEL: vmax_vx_nxv1i64: ; RV32-LABEL: vmax_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vmaxu.vv v8, v8, v9 ; RV32-NEXT: vmaxu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmax_vx_nxv1i64: ; RV64-LABEL: vmax_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
Show All 33 Lines
define <vscale x 2 x i64> @vmax_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) { define <vscale x 2 x i64> @vmax_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; RV32-LABEL: vmax_vx_nxv2i64: ; RV32-LABEL: vmax_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmaxu.vv v8, v8, v10 ; RV32-NEXT: vmaxu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmax_vx_nxv2i64: ; RV64-LABEL: vmax_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
Show All 33 Lines
define <vscale x 4 x i64> @vmax_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) { define <vscale x 4 x i64> @vmax_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; RV32-LABEL: vmax_vx_nxv4i64: ; RV32-LABEL: vmax_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmaxu.vv v8, v8, v12 ; RV32-NEXT: vmaxu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmax_vx_nxv4i64: ; RV64-LABEL: vmax_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
Show All 33 Lines
define <vscale x 8 x i64> @vmax_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i64> @vmax_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: vmax_vx_nxv8i64: ; RV32-LABEL: vmax_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmaxu.vv v8, v8, v16 ; RV32-NEXT: vmaxu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmax_vx_nxv8i64: ; RV64-LABEL: vmax_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 23 Lines

llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll

Show First 20 Lines • Show All 1,891 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmin.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vmin_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vmin_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmin_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmin_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: vmin.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmin.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmin.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmin.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vmin_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vmin_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t ; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmin.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmin.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 11 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vmin.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vmin_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vmin_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmin_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmin_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vmin.vv v8, v8, v10 ; CHECK-NEXT: vmin.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmin.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmin.nxv2i64.i64(
<vscale x 2 x i64> undef, <vscale x 2 x i64> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vmin.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vmin_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vmin_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmin.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmin.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmin.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmin.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 11 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vmin.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vmin_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vmin_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmin_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmin_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmin.vv v8, v8, v12 ; CHECK-NEXT: vmin.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmin.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmin.nxv4i64.i64(
<vscale x 4 x i64> undef, <vscale x 4 x i64> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vmin.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vmin_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vmin_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmin.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmin.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmin.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmin.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 11 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmin.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vmin_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vmin_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmin_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vmin_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmin.vv v8, v8, v16 ; CHECK-NEXT: vmin.vv v8, v8, v16
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmin.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmin.nxv8i64.i64(
<vscale x 8 x i64> undef, <vscale x 8 x i64> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
Show All 12 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmin.mask.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vmin_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vmin_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v24, (a0), zero ; CHECK-NEXT: vlse64.v v24, (a0), zero
; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmin.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmin.mask.nxv8i64.i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll

Show First 20 Lines • Show All 698 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vmin_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) { define <vscale x 1 x i64> @vmin_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; RV32-LABEL: vmin_vx_nxv1i64: ; RV32-LABEL: vmin_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vmin.vv v8, v8, v9 ; RV32-NEXT: vmin.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmin_vx_nxv1i64: ; RV64-LABEL: vmin_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
Show All 33 Lines
define <vscale x 2 x i64> @vmin_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) { define <vscale x 2 x i64> @vmin_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; RV32-LABEL: vmin_vx_nxv2i64: ; RV32-LABEL: vmin_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmin.vv v8, v8, v10 ; RV32-NEXT: vmin.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmin_vx_nxv2i64: ; RV64-LABEL: vmin_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
Show All 33 Lines
define <vscale x 4 x i64> @vmin_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) { define <vscale x 4 x i64> @vmin_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; RV32-LABEL: vmin_vx_nxv4i64: ; RV32-LABEL: vmin_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmin.vv v8, v8, v12 ; RV32-NEXT: vmin.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmin_vx_nxv4i64: ; RV64-LABEL: vmin_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
Show All 33 Lines
define <vscale x 8 x i64> @vmin_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i64> @vmin_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: vmin_vx_nxv8i64: ; RV32-LABEL: vmin_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmin.vv v8, v8, v16 ; RV32-NEXT: vmin.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmin_vx_nxv8i64: ; RV64-LABEL: vmin_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 23 Lines

llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll

Show First 20 Lines • Show All 1,891 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vminu.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vminu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vminu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vminu_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vminu_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: vminu.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vminu.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vminu.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vminu.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vminu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vminu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vminu.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vminu.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 11 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vminu.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vminu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vminu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vminu_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vminu_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vminu.vv v8, v8, v10 ; CHECK-NEXT: vminu.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vminu.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vminu.nxv2i64.i64(
<vscale x 2 x i64> undef, <vscale x 2 x i64> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vminu.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vminu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vminu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vminu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vminu.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vminu.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vminu.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 11 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vminu.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vminu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vminu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vminu_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vminu_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vminu.vv v8, v8, v12 ; CHECK-NEXT: vminu.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vminu.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vminu.nxv4i64.i64(
<vscale x 4 x i64> undef, <vscale x 4 x i64> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vminu.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vminu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vminu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vminu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vminu.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vminu.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vminu.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 11 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vminu.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vminu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vminu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vminu_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vminu_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vminu.vv v8, v8, v16 ; CHECK-NEXT: vminu.vv v8, v8, v16
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vminu.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vminu.nxv8i64.i64(
<vscale x 8 x i64> undef, <vscale x 8 x i64> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
Show All 12 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vminu.mask.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vminu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vminu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v24, (a0), zero ; CHECK-NEXT: vlse64.v v24, (a0), zero
; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vminu.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vminu.mask.nxv8i64.i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll

Show First 20 Lines • Show All 698 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vmin_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) { define <vscale x 1 x i64> @vmin_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; RV32-LABEL: vmin_vx_nxv1i64: ; RV32-LABEL: vmin_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vminu.vv v8, v8, v9 ; RV32-NEXT: vminu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmin_vx_nxv1i64: ; RV64-LABEL: vmin_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
Show All 33 Lines
define <vscale x 2 x i64> @vmin_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) { define <vscale x 2 x i64> @vmin_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; RV32-LABEL: vmin_vx_nxv2i64: ; RV32-LABEL: vmin_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vminu.vv v8, v8, v10 ; RV32-NEXT: vminu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmin_vx_nxv2i64: ; RV64-LABEL: vmin_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
Show All 33 Lines
define <vscale x 4 x i64> @vmin_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) { define <vscale x 4 x i64> @vmin_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; RV32-LABEL: vmin_vx_nxv4i64: ; RV32-LABEL: vmin_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vminu.vv v8, v8, v12 ; RV32-NEXT: vminu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmin_vx_nxv4i64: ; RV64-LABEL: vmin_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
Show All 33 Lines
define <vscale x 8 x i64> @vmin_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i64> @vmin_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: vmin_vx_nxv8i64: ; RV32-LABEL: vmin_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vminu.vv v8, v8, v16 ; RV32-NEXT: vminu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmin_vx_nxv8i64: ; RV64-LABEL: vmin_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 23 Lines

llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll

Show First 20 Lines • Show All 806 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsbc_vx_nxv1i1_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsbc_vx_nxv1i1_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsbc_vx_nxv1i1_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsbc_vx_nxv1i1_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vmsbc.vv v0, v8, v9 ; CHECK-NEXT: vmsbc.vv v0, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsbc_vx_nxv2i1_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsbc_vx_nxv2i1_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsbc_vx_nxv2i1_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsbc_vx_nxv2i1_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vmsbc.vv v0, v8, v10 ; CHECK-NEXT: vmsbc.vv v0, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsbc.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsbc.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsbc_vx_nxv4i1_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsbc_vx_nxv4i1_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsbc_vx_nxv4i1_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsbc_vx_nxv4i1_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmsbc.vv v0, v8, v12 ; CHECK-NEXT: vmsbc.vv v0, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsbc.nxv8i64.i64( declare <vscale x 8 x i1> @llvm.riscv.vmsbc.nxv8i64.i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64, i64,
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsbc_vx_nxv8i1_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i1> @intrinsic_vmsbc_vx_nxv8i1_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsbc_vx_nxv8i1_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vmsbc_vx_nxv8i1_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmsbc.vv v0, v8, v16 ; CHECK-NEXT: vmsbc.vv v0, v8, v16
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.nxv8i64.i64( %a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.nxv8i64.i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i64 %1, i64 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll

Show First 20 Lines • Show All 927 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vmsbc.vvm v9, v8, v10, v0 ; CHECK-NEXT: vmsbc.vvm v9, v8, v10, v0
; CHECK-NEXT: vmv.v.v v0, v9 ; CHECK-NEXT: vmv.v.v v0, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 11 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmsbc.vvm v10, v8, v12, v0 ; CHECK-NEXT: vmsbc.vvm v10, v8, v12, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 11 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmsbc.vvm v12, v8, v16, v0 ; CHECK-NEXT: vmsbc.vvm v12, v8, v16, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 11 Linesdeclare <vscale x 8 x i1> @llvm.riscv.vmsbc.borrow.in.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v24, (a0), zero ; CHECK-NEXT: vlse64.v v24, (a0), zero
; CHECK-NEXT: vmsbc.vvm v16, v8, v24, v0 ; CHECK-NEXT: vmsbc.vvm v16, v8, v24, v0
; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.borrow.in.nxv8i64.i64( %a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.borrow.in.nxv8i64.i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i64 %1, i64 %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll

Show First 20 Lines • Show All 1,647 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmseq_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v0, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v11, (a0), zero ; CHECK-NEXT: vlse64.v v11, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vv v10, v8, v11, v0.t ; CHECK-NEXT: vmseq.vv v10, v8, v11, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 13 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmseq_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vmseq.vv v0, v8, v10 ; CHECK-NEXT: vmseq.vv v0, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vv v11, v8, v12, v0.t ; CHECK-NEXT: vmseq.vv v11, v8, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 13 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmseq_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmseq.vv v0, v8, v12 ; CHECK-NEXT: vmseq.vv v0, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vv v13, v8, v16, v0.t ; CHECK-NEXT: vmseq.vv v13, v8, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
▲ Show 20 Lines • Show All 639 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll

Show First 20 Lines • Show All 1,662 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v0, v9, v8
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v11, (a0), zero ; CHECK-NEXT: vlse64.v v11, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vv v10, v11, v8, v0.t ; CHECK-NEXT: vmsle.vv v10, v11, v8, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 13 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: vmsle.vv v0, v10, v8
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vv v11, v12, v8, v0.t ; CHECK-NEXT: vmsle.vv v11, v12, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 13 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: vmsle.vv v0, v12, v8
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vv v13, v16, v8, v0.t ; CHECK-NEXT: vmsle.vv v13, v16, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
▲ Show 20 Lines • Show All 909 Lines • ▼ Show 20 Lines
} }
define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vmsle.vv v0, v9, v8, v0.t ; CHECK-NEXT: vmsle.vv v0, v9, v8, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3) i32 %3)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmsle.vv v10, v12, v8, v0.t ; CHECK-NEXT: vmsle.vv v10, v12, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %3) i32 %3)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v12, v0 ; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vmsle.vv v12, v16, v8, v0.t ; CHECK-NEXT: vmsle.vv v12, v16, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3) i32 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll

Show First 20 Lines • Show All 1,662 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v0, v9, v8
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v11, (a0), zero ; CHECK-NEXT: vlse64.v v11, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vv v10, v11, v8, v0.t ; CHECK-NEXT: vmsleu.vv v10, v11, v8, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 13 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: vmsleu.vv v0, v10, v8
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vv v11, v12, v8, v0.t ; CHECK-NEXT: vmsleu.vv v11, v12, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 13 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: vmsleu.vv v0, v12, v8
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vv v13, v16, v8, v0.t ; CHECK-NEXT: vmsleu.vv v13, v16, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
▲ Show 20 Lines • Show All 921 Lines • ▼ Show 20 Lines
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vmsleu.vv v0, v9, v8, v0.t ; CHECK-NEXT: vmsleu.vv v0, v9, v8, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3) i32 %3)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmsleu.vv v10, v12, v8, v0.t ; CHECK-NEXT: vmsleu.vv v10, v12, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %3) i32 %3)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v12, v0 ; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vmsleu.vv v12, v16, v8, v0.t ; CHECK-NEXT: vmsleu.vv v12, v16, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3) i32 %3)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll

Show First 20 Lines • Show All 1,647 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgt_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v0, v9, v8
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v11, (a0), zero ; CHECK-NEXT: vlse64.v v11, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vv v10, v11, v8, v0.t ; CHECK-NEXT: vmslt.vv v10, v11, v8, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 13 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgt_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vmslt.vv v0, v10, v8 ; CHECK-NEXT: vmslt.vv v0, v10, v8
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vv v11, v12, v8, v0.t ; CHECK-NEXT: vmslt.vv v11, v12, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 13 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgt_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmslt.vv v0, v12, v8 ; CHECK-NEXT: vmslt.vv v0, v12, v8
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vv v13, v16, v8, v0.t ; CHECK-NEXT: vmslt.vv v13, v16, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
▲ Show 20 Lines • Show All 639 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll

Show First 20 Lines • Show All 1,647 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgtu_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v0, v9, v8
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v11, (a0), zero ; CHECK-NEXT: vlse64.v v11, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vv v10, v11, v8, v0.t ; CHECK-NEXT: vmsltu.vv v10, v11, v8, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 13 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgtu_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vmsltu.vv v0, v10, v8 ; CHECK-NEXT: vmsltu.vv v0, v10, v8
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vv v11, v12, v8, v0.t ; CHECK-NEXT: vmsltu.vv v11, v12, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 13 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgtu_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmsltu.vv v0, v12, v8 ; CHECK-NEXT: vmsltu.vv v0, v12, v8
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vv v13, v16, v8, v0.t ; CHECK-NEXT: vmsltu.vv v13, v16, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
▲ Show 20 Lines • Show All 639 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll

Show First 20 Lines • Show All 1,647 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsle_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v0, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v11, (a0), zero ; CHECK-NEXT: vlse64.v v11, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vv v10, v8, v11, v0.t ; CHECK-NEXT: vmsle.vv v10, v8, v11, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 13 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsle_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vmsle.vv v0, v8, v10 ; CHECK-NEXT: vmsle.vv v0, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vv v11, v8, v12, v0.t ; CHECK-NEXT: vmsle.vv v11, v8, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 13 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsle_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmsle.vv v0, v8, v12 ; CHECK-NEXT: vmsle.vv v0, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vv v13, v8, v16, v0.t ; CHECK-NEXT: vmsle.vv v13, v8, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
▲ Show 20 Lines • Show All 639 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll

Show First 20 Lines • Show All 1,647 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsleu_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v0, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v11, (a0), zero ; CHECK-NEXT: vlse64.v v11, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vv v10, v8, v11, v0.t ; CHECK-NEXT: vmsleu.vv v10, v8, v11, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 13 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsleu_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vmsleu.vv v0, v8, v10 ; CHECK-NEXT: vmsleu.vv v0, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vv v11, v8, v12, v0.t ; CHECK-NEXT: vmsleu.vv v11, v8, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 13 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsleu_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmsleu.vv v0, v8, v12 ; CHECK-NEXT: vmsleu.vv v0, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vv v13, v8, v16, v0.t ; CHECK-NEXT: vmsleu.vv v13, v8, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
▲ Show 20 Lines • Show All 639 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll

Show First 20 Lines • Show All 1,647 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmslt_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v0, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v11, (a0), zero ; CHECK-NEXT: vlse64.v v11, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vv v10, v8, v11, v0.t ; CHECK-NEXT: vmslt.vv v10, v8, v11, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 13 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmslt_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vmslt.vv v0, v8, v10 ; CHECK-NEXT: vmslt.vv v0, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vv v11, v8, v12, v0.t ; CHECK-NEXT: vmslt.vv v11, v8, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 13 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmslt_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmslt.vv v0, v8, v12 ; CHECK-NEXT: vmslt.vv v0, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vv v13, v8, v16, v0.t ; CHECK-NEXT: vmslt.vv v13, v8, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
▲ Show 20 Lines • Show All 639 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll

Show First 20 Lines • Show All 1,647 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsltu_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v0, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v11, (a0), zero ; CHECK-NEXT: vlse64.v v11, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vv v10, v8, v11, v0.t ; CHECK-NEXT: vmsltu.vv v10, v8, v11, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 13 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsltu_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vmsltu.vv v0, v8, v10 ; CHECK-NEXT: vmsltu.vv v0, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vv v11, v8, v12, v0.t ; CHECK-NEXT: vmsltu.vv v11, v8, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 13 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsltu_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmsltu.vv v0, v8, v12 ; CHECK-NEXT: vmsltu.vv v0, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vv v13, v8, v16, v0.t ; CHECK-NEXT: vmsltu.vv v13, v8, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
▲ Show 20 Lines • Show All 639 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll

Show First 20 Lines • Show All 1,647 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsne_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v0, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v11, (a0), zero ; CHECK-NEXT: vlse64.v v11, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vv v10, v8, v11, v0.t ; CHECK-NEXT: vmsne.vv v10, v8, v11, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 13 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsne_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vmsne.vv v0, v8, v10 ; CHECK-NEXT: vmsne.vv v0, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vv v11, v8, v12, v0.t ; CHECK-NEXT: vmsne.vv v11, v8, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 13 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsne_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmsne.vv v0, v8, v12 ; CHECK-NEXT: vmsne.vv v0, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
Show All 10 Linesdeclare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vv v13, v8, v16, v0.t ; CHECK-NEXT: vmsne.vv v13, v8, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
▲ Show 20 Lines • Show All 639 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll

Show First 20 Lines • Show All 643 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vmul_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) { define <vscale x 1 x i64> @vmul_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; RV32-LABEL: vmul_vx_nxv1i64: ; RV32-LABEL: vmul_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vmul.vv v8, v8, v9 ; RV32-NEXT: vmul.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmul_vx_nxv1i64: ; RV64-LABEL: vmul_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
define <vscale x 2 x i64> @vmul_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) { define <vscale x 2 x i64> @vmul_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; RV32-LABEL: vmul_vx_nxv2i64: ; RV32-LABEL: vmul_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmul.vv v8, v8, v10 ; RV32-NEXT: vmul.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmul_vx_nxv2i64: ; RV64-LABEL: vmul_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
define <vscale x 4 x i64> @vmul_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) { define <vscale x 4 x i64> @vmul_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; RV32-LABEL: vmul_vx_nxv4i64: ; RV32-LABEL: vmul_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmul.vv v8, v8, v12 ; RV32-NEXT: vmul.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmul_vx_nxv4i64: ; RV64-LABEL: vmul_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
define <vscale x 8 x i64> @vmul_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i64> @vmul_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: vmul_vx_nxv8i64: ; RV32-LABEL: vmul_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmul.vv v8, v8, v16 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmul_vx_nxv8i64: ; RV64-LABEL: vmul_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
▲ Show 20 Lines • Show All 44 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll

Show First 20 Lines • Show All 1,005 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vmul_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i64> @vmul_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vmul_vx_nxv1i64: ; RV32-LABEL: vmul_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vmul.vv v8, v8, v9, v0.t ; RV32-NEXT: vmul.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmul_vx_nxv1i64: ; RV64-LABEL: vmul_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i64> @llvm.vp.mul.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i64> @llvm.vp.mul.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v ret <vscale x 1 x i64> %v
} }
define <vscale x 1 x i64> @vmul_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 1 x i64> @vmul_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vmul_vx_nxv1i64_unmasked: ; RV32-LABEL: vmul_vx_nxv1i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vmul.vv v8, v8, v9 ; RV32-NEXT: vmul.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmul_vx_nxv1i64_unmasked: ; RV64-LABEL: vmul_vx_nxv1i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <vscale x 2 x i64> @vmul_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i64> @vmul_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vmul_vx_nxv2i64: ; RV32-LABEL: vmul_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vmul.vv v8, v8, v10, v0.t ; RV32-NEXT: vmul.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmul_vx_nxv2i64: ; RV64-LABEL: vmul_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i64> @llvm.vp.mul.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl) %v = call <vscale x 2 x i64> @llvm.vp.mul.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
define <vscale x 2 x i64> @vmul_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 2 x i64> @vmul_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vmul_vx_nxv2i64_unmasked: ; RV32-LABEL: vmul_vx_nxv2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vmul.vv v8, v8, v10 ; RV32-NEXT: vmul.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmul_vx_nxv2i64_unmasked: ; RV64-LABEL: vmul_vx_nxv2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <vscale x 4 x i64> @vmul_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i64> @vmul_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vmul_vx_nxv4i64: ; RV32-LABEL: vmul_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vmul.vv v8, v8, v12, v0.t ; RV32-NEXT: vmul.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmul_vx_nxv4i64: ; RV64-LABEL: vmul_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i64> @llvm.vp.mul.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl) %v = call <vscale x 4 x i64> @llvm.vp.mul.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v ret <vscale x 4 x i64> %v
} }
define <vscale x 4 x i64> @vmul_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 4 x i64> @vmul_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vmul_vx_nxv4i64_unmasked: ; RV32-LABEL: vmul_vx_nxv4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vmul.vv v8, v8, v12 ; RV32-NEXT: vmul.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmul_vx_nxv4i64_unmasked: ; RV64-LABEL: vmul_vx_nxv4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <vscale x 8 x i64> @vmul_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vmul_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vmul_vx_nxv8i64: ; RV32-LABEL: vmul_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vmul.vv v8, v8, v16, v0.t ; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmul_vx_nxv8i64: ; RV64-LABEL: vmul_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i64> @llvm.vp.mul.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i64> @llvm.vp.mul.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i64> @vmul_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 8 x i64> @vmul_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vmul_vx_nxv8i64_unmasked: ; RV32-LABEL: vmul_vx_nxv8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vmul.vv v8, v8, v16 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmul_vx_nxv8i64_unmasked: ; RV64-LABEL: vmul_vx_nxv8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 10 Lines

llvm/test/CodeGen/RISCV/rvv/vmul.ll

Show First 20 Lines • Show All 1,853 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmul.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vmul_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 1 x i64> @intrinsic_vmul_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vmul_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vmul_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vmul.vv v8, v8, v9 ; RV32-NEXT: vmul.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmul_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vmul_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmul.mask.nxv1i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 1 x i64> @intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i64> @intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmul.vv v8, v9, v10, v0.t ; RV32-NEXT: vmul.vv v8, v9, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vmul.nxv2i64.i64(
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_vmul_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 2 x i64> @intrinsic_vmul_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vmul_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vmul_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmul.vv v8, v8, v10 ; RV32-NEXT: vmul.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmul_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vmul_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vmul.mask.nxv2i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 2 x i64> @intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i64> @intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmul.vv v8, v10, v12, v0.t ; RV32-NEXT: vmul.vv v8, v10, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vmul.nxv4i64.i64(
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_vmul_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 4 x i64> @intrinsic_vmul_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vmul_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vmul_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmul.vv v8, v8, v12 ; RV32-NEXT: vmul.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmul_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vmul_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vmul.mask.nxv4i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 4 x i64> @intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i64> @intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmul.vv v8, v12, v16, v0.t ; RV32-NEXT: vmul.vv v8, v12, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmul.nxv8i64.i64(
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vmul_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 8 x i64> @intrinsic_vmul_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vmul_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vmul_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmul.vv v8, v8, v16 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmul_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vmul_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmul.mask.nxv8i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 8 x i64> @intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i64> @intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vmul.vv v8, v16, v24, v0.t ; RV32-NEXT: vmul.vv v8, v16, v24, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
Show All 12 Lines

llvm/test/CodeGen/RISCV/rvv/vmulh.ll

Show First 20 Lines • Show All 1,853 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vmulh_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 1 x i64> @intrinsic_vmulh_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vmulh_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vmulh_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vmulh.vv v8, v8, v9 ; RV32-NEXT: vmulh.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulh_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vmulh_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 1 x i64> @intrinsic_vmulh_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i64> @intrinsic_vmulh_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmulh_mask_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vmulh_mask_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmulh.vv v8, v9, v10, v0.t ; RV32-NEXT: vmulh.vv v8, v9, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulh_mask_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vmulh_mask_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64(
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_vmulh_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 2 x i64> @intrinsic_vmulh_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vmulh_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vmulh_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmulh.vv v8, v8, v10 ; RV32-NEXT: vmulh.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulh_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vmulh_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vmulh.mask.nxv2i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 2 x i64> @intrinsic_vmulh_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i64> @intrinsic_vmulh_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmulh_mask_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vmulh_mask_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmulh.vv v8, v10, v12, v0.t ; RV32-NEXT: vmulh.vv v8, v10, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulh_mask_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vmulh_mask_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64(
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_vmulh_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 4 x i64> @intrinsic_vmulh_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vmulh_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vmulh_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmulh.vv v8, v8, v12 ; RV32-NEXT: vmulh.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulh_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vmulh_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vmulh.mask.nxv4i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 4 x i64> @intrinsic_vmulh_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i64> @intrinsic_vmulh_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmulh_mask_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vmulh_mask_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmulh.vv v8, v12, v16, v0.t ; RV32-NEXT: vmulh.vv v8, v12, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulh_mask_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vmulh_mask_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64(
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vmulh_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 8 x i64> @intrinsic_vmulh_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vmulh_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vmulh_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmulh.vv v8, v8, v16 ; RV32-NEXT: vmulh.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulh_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vmulh_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmulh.mask.nxv8i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 8 x i64> @intrinsic_vmulh_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i64> @intrinsic_vmulh_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmulh_mask_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vmulh_mask_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vmulh.vv v8, v16, v24, v0.t ; RV32-NEXT: vmulh.vv v8, v16, v24, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulh_mask_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vmulh_mask_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
Show All 12 Lines

llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll

Show First 20 Lines • Show All 1,853 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vmulhsu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 1 x i64> @intrinsic_vmulhsu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vmulhsu_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vmulhsu_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vmulhsu.vv v8, v8, v9 ; RV32-NEXT: vmulhsu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulhsu_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vmulhsu_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 1 x i64> @intrinsic_vmulhsu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i64> @intrinsic_vmulhsu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmulhsu.vv v8, v9, v10, v0.t ; RV32-NEXT: vmulhsu.vv v8, v9, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64(
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_vmulhsu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 2 x i64> @intrinsic_vmulhsu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vmulhsu_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vmulhsu_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmulhsu.vv v8, v8, v10 ; RV32-NEXT: vmulhsu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulhsu_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vmulhsu_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vmulhsu.mask.nxv2i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 2 x i64> @intrinsic_vmulhsu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i64> @intrinsic_vmulhsu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmulhsu.vv v8, v10, v12, v0.t ; RV32-NEXT: vmulhsu.vv v8, v10, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64(
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_vmulhsu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 4 x i64> @intrinsic_vmulhsu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vmulhsu_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vmulhsu_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmulhsu.vv v8, v8, v12 ; RV32-NEXT: vmulhsu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulhsu_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vmulhsu_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vmulhsu.mask.nxv4i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 4 x i64> @intrinsic_vmulhsu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i64> @intrinsic_vmulhsu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmulhsu.vv v8, v12, v16, v0.t ; RV32-NEXT: vmulhsu.vv v8, v12, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64(
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vmulhsu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 8 x i64> @intrinsic_vmulhsu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vmulhsu_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vmulhsu_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmulhsu.vv v8, v8, v16 ; RV32-NEXT: vmulhsu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulhsu_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vmulhsu_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmulhsu.mask.nxv8i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 8 x i64> @intrinsic_vmulhsu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i64> @intrinsic_vmulhsu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vmulhsu.vv v8, v16, v24, v0.t ; RV32-NEXT: vmulhsu.vv v8, v16, v24, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
Show All 12 Lines

llvm/test/CodeGen/RISCV/rvv/vmulhu.ll

Show First 20 Lines • Show All 1,853 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vmulhu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 1 x i64> @intrinsic_vmulhu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vmulhu_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vmulhu_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vmulhu.vv v8, v8, v9 ; RV32-NEXT: vmulhu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulhu_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vmulhu_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 1 x i64> @intrinsic_vmulhu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i64> @intrinsic_vmulhu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmulhu_mask_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vmulhu_mask_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmulhu.vv v8, v9, v10, v0.t ; RV32-NEXT: vmulhu.vv v8, v9, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulhu_mask_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vmulhu_mask_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64(
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_vmulhu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 2 x i64> @intrinsic_vmulhu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vmulhu_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vmulhu_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmulhu.vv v8, v8, v10 ; RV32-NEXT: vmulhu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulhu_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vmulhu_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vmulhu.mask.nxv2i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 2 x i64> @intrinsic_vmulhu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i64> @intrinsic_vmulhu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmulhu_mask_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vmulhu_mask_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmulhu.vv v8, v10, v12, v0.t ; RV32-NEXT: vmulhu.vv v8, v10, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulhu_mask_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vmulhu_mask_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64(
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_vmulhu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 4 x i64> @intrinsic_vmulhu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vmulhu_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vmulhu_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmulhu.vv v8, v8, v12 ; RV32-NEXT: vmulhu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulhu_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vmulhu_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vmulhu.mask.nxv4i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 4 x i64> @intrinsic_vmulhu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i64> @intrinsic_vmulhu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmulhu_mask_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vmulhu_mask_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmulhu.vv v8, v12, v16, v0.t ; RV32-NEXT: vmulhu.vv v8, v12, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulhu_mask_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vmulhu_mask_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64(
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vmulhu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 8 x i64> @intrinsic_vmulhu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vmulhu_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vmulhu_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmulhu.vv v8, v8, v16 ; RV32-NEXT: vmulhu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulhu_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vmulhu_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmulhu.mask.nxv8i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 8 x i64> @intrinsic_vmulhu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i64> @intrinsic_vmulhu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmulhu_mask_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vmulhu_mask_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vmulhu.vv v8, v16, v24, v0.t ; RV32-NEXT: vmulhu.vv v8, v16, v24, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vmulhu_mask_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vmulhu_mask_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
Show All 12 Lines

llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll

Show First 20 Lines • Show All 366 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vmv.v.x_x_nxv1i64(i64 %0, i32 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vmv.v.x_x_nxv1i64(i64 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i64: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v8, (a0), zero ; CHECK-NEXT: vlse64.v v8, (a0), zero
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
i64 %0, i64 %0,
i32 %1) i32 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vmv.v.x_x_nxv2i64(i64 %0, i32 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vmv.v.x_x_nxv2i64(i64 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i64: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v8, (a0), zero ; CHECK-NEXT: vlse64.v v8, (a0), zero
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64(
<vscale x 2 x i64> undef, <vscale x 2 x i64> undef,
i64 %0, i64 %0,
i32 %1) i32 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vmv.v.x_x_nxv4i64(i64 %0, i32 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vmv.v.x_x_nxv4i64(i64 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i64: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v8, (a0), zero ; CHECK-NEXT: vlse64.v v8, (a0), zero
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64(
<vscale x 4 x i64> undef, <vscale x 4 x i64> undef,
i64 %0, i64 %0,
i32 %1) i32 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i64, i64,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vmv.v.x_x_nxv8i64(i64 %0, i32 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vmv.v.x_x_nxv8i64(i64 %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i64: ; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v8, (a0), zero ; CHECK-NEXT: vlse64.v v8, (a0), zero
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(
<vscale x 8 x i64> undef, <vscale x 8 x i64> undef,
i64 %0, i64 %0,
i32 %1) i32 %1)
▲ Show 20 Lines • Show All 393 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll

Show First 20 Lines • Show All 1,559 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vnmsac.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vnmsac_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vnmsac_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i64_i64_nxv1i64: ; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i64_i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v10, v9 ; CHECK-NEXT: vnmsac.vv v8, v10, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vnmsac.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vnmsac.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.i64(
i32, i32); i32, i32);
define <vscale x 1 x i64> @intrinsic_vnmsac_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vnmsac_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i64_i64_nxv1i64: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i64_i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v10, v9, v0.t ; CHECK-NEXT: vnmsac.vv v8, v10, v9, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 13 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vnmsac.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vnmsac_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, i32 %3) nounwind { define <vscale x 2 x i64> @intrinsic_vnmsac_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i64_i64_nxv2i64: ; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i64_i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v12, v10 ; CHECK-NEXT: vnmsac.vv v8, v12, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vnmsac.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vnmsac.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.i64(
i32, i32); i32, i32);
define <vscale x 2 x i64> @intrinsic_vnmsac_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vnmsac_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i64_i64_nxv2i64: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i64_i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v12, v10, v0.t ; CHECK-NEXT: vnmsac.vv v8, v12, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 13 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vnmsac.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vnmsac_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, i32 %3) nounwind { define <vscale x 4 x i64> @intrinsic_vnmsac_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i64_i64_nxv4i64: ; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i64_i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v16, v12 ; CHECK-NEXT: vnmsac.vv v8, v16, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vnmsac.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vnmsac.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.i64(
i32, i32); i32, i32);
define <vscale x 4 x i64> @intrinsic_vnmsac_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vnmsac_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i64_i64_nxv4i64: ; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i64_i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
; CHECK-NEXT: vnmsac.vv v8, v16, v12, v0.t ; CHECK-NEXT: vnmsac.vv v8, v16, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll

Show First 20 Lines • Show All 1,559 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vnmsub.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vnmsub_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vnmsub_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i64_i64_nxv1i64: ; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i64_i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v10, v9 ; CHECK-NEXT: vnmsub.vv v8, v10, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vnmsub.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vnmsub.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.i64(
i32, i32); i32, i32);
define <vscale x 1 x i64> @intrinsic_vnmsub_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vnmsub_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i64_i64_nxv1i64: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i64_i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m1, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v10, v9, v0.t ; CHECK-NEXT: vnmsub.vv v8, v10, v9, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 13 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vnmsub.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vnmsub_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, i32 %3) nounwind { define <vscale x 2 x i64> @intrinsic_vnmsub_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i64_i64_nxv2i64: ; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i64_i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v12, v10 ; CHECK-NEXT: vnmsub.vv v8, v12, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vnmsub.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vnmsub.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.i64(
i32, i32); i32, i32);
define <vscale x 2 x i64> @intrinsic_vnmsub_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vnmsub_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i64_i64_nxv2i64: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i64_i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v12, v10, v0.t ; CHECK-NEXT: vnmsub.vv v8, v12, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 13 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vnmsub.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vnmsub_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, i32 %3) nounwind { define <vscale x 4 x i64> @intrinsic_vnmsub_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i64_i64_nxv4i64: ; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i64_i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v16, v12 ; CHECK-NEXT: vnmsub.vv v8, v16, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vnmsub.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vnmsub.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.i64(
i32, i32); i32, i32);
define <vscale x 4 x i64> @intrinsic_vnmsub_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vnmsub_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i64_i64_nxv4i64: ; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i64_i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, mu
; CHECK-NEXT: vnmsub.vv v8, v16, v12, v0.t ; CHECK-NEXT: vnmsub.vv v8, v16, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i64 %1, i64 %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll

Show First 20 Lines • Show All 454 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vnmsub_vx_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i64 %c) { define <vscale x 1 x i64> @vnmsub_vx_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i64 %c) {
; RV32-LABEL: vnmsub_vx_nxv1i64: ; RV32-LABEL: vnmsub_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vnmsub.vv v8, v10, v9 ; RV32-NEXT: vnmsub.vv v8, v10, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vnmsub_vx_nxv1i64: ; RV64-LABEL: vnmsub_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
Show All 19 Lines
define <vscale x 2 x i64> @vnmsub_vx_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i64 %c) { define <vscale x 2 x i64> @vnmsub_vx_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i64 %c) {
; RV32-LABEL: vnmsub_vx_nxv2i64: ; RV32-LABEL: vnmsub_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vnmsac.vv v8, v10, v12 ; RV32-NEXT: vnmsac.vv v8, v10, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vnmsub_vx_nxv2i64: ; RV64-LABEL: vnmsub_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
Show All 19 Lines
define <vscale x 4 x i64> @vnmsub_vx_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, i64 %c) { define <vscale x 4 x i64> @vnmsub_vx_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, i64 %c) {
; RV32-LABEL: vnmsub_vx_nxv4i64: ; RV32-LABEL: vnmsub_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vnmsub.vv v8, v16, v12 ; RV32-NEXT: vnmsub.vv v8, v16, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vnmsub_vx_nxv4i64: ; RV64-LABEL: vnmsub_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
Show All 20 Lines
define <vscale x 8 x i64> @vnmsub_vx_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, i64 %c) { define <vscale x 8 x i64> @vnmsub_vx_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, i64 %c) {
; RV32-LABEL: vnmsub_vx_nxv8i64: ; RV32-LABEL: vnmsub_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vnmsac.vv v8, v16, v24 ; RV32-NEXT: vnmsac.vv v8, v16, v24
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vnmsub_vx_nxv8i64: ; RV64-LABEL: vnmsub_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vnmsac.vx v8, a0, v16 ; RV64-NEXT: vnmsac.vx v8, a0, v16
; RV64-NEXT: ret ; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %c, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 %c, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%x = mul <vscale x 8 x i64> %vb, %splat %x = mul <vscale x 8 x i64> %vb, %splat
%y = sub <vscale x 8 x i64> %va, %x %y = sub <vscale x 8 x i64> %va, %x
ret <vscale x 8 x i64> %y ret <vscale x 8 x i64> %y
} }

llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll

Show First 20 Lines • Show All 1,891 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vor.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vor_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vor_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vor_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vor_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vor.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vor.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vor.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vor_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vor_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vor.vv v8, v9, v10, v0.t ; CHECK-NEXT: vor.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vor.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vor.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 11 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vor.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vor_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vor_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vor_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vor_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: vor.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vor.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vor.nxv2i64.i64(
<vscale x 2 x i64> undef, <vscale x 2 x i64> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vor.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vor_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vor_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vor.vv v8, v10, v12, v0.t ; CHECK-NEXT: vor.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vor.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vor.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 11 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vor.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vor_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vor_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vor_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vor_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vor.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vor.nxv4i64.i64(
<vscale x 4 x i64> undef, <vscale x 4 x i64> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vor.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vor_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vor_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vor.vv v8, v12, v16, v0.t ; CHECK-NEXT: vor.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vor.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vor.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 11 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vor.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vor_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vor_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vor_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vor_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vor.vv v8, v8, v16 ; CHECK-NEXT: vor.vv v8, v8, v16
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vor.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vor.nxv8i64.i64(
<vscale x 8 x i64> undef, <vscale x 8 x i64> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
Show All 12 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vor.mask.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vor_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vor_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v24, (a0), zero ; CHECK-NEXT: vlse64.v v24, (a0), zero
; CHECK-NEXT: vor.vv v8, v16, v24, v0.t ; CHECK-NEXT: vor.vv v8, v16, v24, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vor.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vor.mask.nxv8i64.i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
▲ Show 20 Lines • Show All 732 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll

Show First 20 Lines • Show All 885 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) { define <vscale x 1 x i64> @vor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; RV32-LABEL: vor_vx_nxv1i64: ; RV32-LABEL: vor_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vor_vx_nxv1i64: ; RV64-LABEL: vor_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
define <vscale x 2 x i64> @vor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) { define <vscale x 2 x i64> @vor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; RV32-LABEL: vor_vx_nxv2i64: ; RV32-LABEL: vor_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vor_vx_nxv2i64: ; RV64-LABEL: vor_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
define <vscale x 4 x i64> @vor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) { define <vscale x 4 x i64> @vor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; RV32-LABEL: vor_vx_nxv4i64: ; RV32-LABEL: vor_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vor_vx_nxv4i64: ; RV64-LABEL: vor_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
define <vscale x 8 x i64> @vor_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i64> @vor_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: vor_vx_nxv8i64: ; RV32-LABEL: vor_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vor_vx_nxv8i64: ; RV64-LABEL: vor_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vor-vp.ll

Show First 20 Lines • Show All 1,513 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i64> @vor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vor_vx_nxv1i64: ; RV32-LABEL: vor_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vor.vv v8, v8, v9, v0.t ; RV32-NEXT: vor.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vor_vx_nxv1i64: ; RV64-LABEL: vor_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vor.vx v8, v8, a0, v0.t ; RV64-NEXT: vor.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i64> @llvm.vp.or.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i64> @llvm.vp.or.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v ret <vscale x 1 x i64> %v
} }
define <vscale x 1 x i64> @vor_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 1 x i64> @vor_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vor_vx_nxv1i64_unmasked: ; RV32-LABEL: vor_vx_nxv1i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vor_vx_nxv1i64_unmasked: ; RV64-LABEL: vor_vx_nxv1i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
define <vscale x 2 x i64> @vor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i64> @vor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vor_vx_nxv2i64: ; RV32-LABEL: vor_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vor.vv v8, v8, v10, v0.t ; RV32-NEXT: vor.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vor_vx_nxv2i64: ; RV64-LABEL: vor_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vor.vx v8, v8, a0, v0.t ; RV64-NEXT: vor.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i64> @llvm.vp.or.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl) %v = call <vscale x 2 x i64> @llvm.vp.or.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
define <vscale x 2 x i64> @vor_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 2 x i64> @vor_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vor_vx_nxv2i64_unmasked: ; RV32-LABEL: vor_vx_nxv2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vor_vx_nxv2i64_unmasked: ; RV64-LABEL: vor_vx_nxv2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
define <vscale x 4 x i64> @vor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i64> @vor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vor_vx_nxv4i64: ; RV32-LABEL: vor_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vor.vv v8, v8, v12, v0.t ; RV32-NEXT: vor.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vor_vx_nxv4i64: ; RV64-LABEL: vor_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vor.vx v8, v8, a0, v0.t ; RV64-NEXT: vor.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i64> @llvm.vp.or.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl) %v = call <vscale x 4 x i64> @llvm.vp.or.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v ret <vscale x 4 x i64> %v
} }
define <vscale x 4 x i64> @vor_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 4 x i64> @vor_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vor_vx_nxv4i64_unmasked: ; RV32-LABEL: vor_vx_nxv4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vor_vx_nxv4i64_unmasked: ; RV64-LABEL: vor_vx_nxv4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
define <vscale x 8 x i64> @vor_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vor_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vor_vx_nxv8i64: ; RV32-LABEL: vor_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vor.vv v8, v8, v16, v0.t ; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vor_vx_nxv8i64: ; RV64-LABEL: vor_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vor.vx v8, v8, a0, v0.t ; RV64-NEXT: vor.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i64> @llvm.vp.or.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i64> @llvm.vp.or.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i64> @vor_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 8 x i64> @vor_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vor_vx_nxv8i64_unmasked: ; RV32-LABEL: vor_vx_nxv8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vor_vx_nxv8i64_unmasked: ; RV64-LABEL: vor_vx_nxv8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 36 Lines

llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll

Show First 20 Lines • Show All 957 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vpmerge_vx_nxv1i64(i64 %a, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i64> @vpmerge_vx_nxv1i64(i64 %a, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpmerge_vx_nxv1i64: ; RV32-LABEL: vpmerge_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
; RV32-NEXT: vmerge.vvm v8, v8, v9, v0 ; RV32-NEXT: vmerge.vvm v8, v8, v9, v0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpmerge_vx_nxv1i64: ; RV64-LABEL: vpmerge_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 33 Lines
define <vscale x 2 x i64> @vpmerge_vx_nxv2i64(i64 %a, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i64> @vpmerge_vx_nxv2i64(i64 %a, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpmerge_vx_nxv2i64: ; RV32-LABEL: vpmerge_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
; RV32-NEXT: vmerge.vvm v8, v8, v10, v0 ; RV32-NEXT: vmerge.vvm v8, v8, v10, v0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpmerge_vx_nxv2i64: ; RV64-LABEL: vpmerge_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 33 Lines
define <vscale x 4 x i64> @vpmerge_vx_nxv4i64(i64 %a, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i64> @vpmerge_vx_nxv4i64(i64 %a, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpmerge_vx_nxv4i64: ; RV32-LABEL: vpmerge_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu
; RV32-NEXT: vmerge.vvm v8, v8, v12, v0 ; RV32-NEXT: vmerge.vvm v8, v8, v12, v0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpmerge_vx_nxv4i64: ; RV64-LABEL: vpmerge_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 33 Lines
define <vscale x 8 x i64> @vpmerge_vx_nxv8i64(i64 %a, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vpmerge_vx_nxv8i64(i64 %a, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpmerge_vx_nxv8i64: ; RV32-LABEL: vpmerge_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, tu, mu
; RV32-NEXT: vmerge.vvm v8, v8, v16, v0 ; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpmerge_vx_nxv8i64: ; RV64-LABEL: vpmerge_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 395 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll

Show First 20 Lines • Show All 1,365 Lines • ▼ Show 20 Lines
define i64 @vreduce_smax_nxv1i64(<vscale x 1 x i64> %v) { define i64 @vreduce_smax_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-LABEL: vreduce_smax_nxv1i64: ; CHECK-LABEL: vreduce_smax_nxv1i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: sw a0, 12(sp) ; CHECK-NEXT: sw a0, 12(sp)
; CHECK-NEXT: sw zero, 8(sp) ; CHECK-NEXT: sw zero, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vredmax.vs v8, v8, v9 ; CHECK-NEXT: vredmax.vs v8, v8, v9
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vsrl.vx v8, v8, a1 ; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: vmv.x.s a1, v8
Show All 29 Lines
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: li a0, -1 ; CHECK-NEXT: li a0, -1
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: sw a0, 12(sp) ; CHECK-NEXT: sw a0, 12(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vredmin.vs v8, v8, v9 ; CHECK-NEXT: vredmin.vs v8, v8, v9
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vsrl.vx v8, v8, a1 ; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: vmv.x.s a1, v8
▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
define i64 @vreduce_smax_nxv2i64(<vscale x 2 x i64> %v) { define i64 @vreduce_smax_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-LABEL: vreduce_smax_nxv2i64: ; CHECK-LABEL: vreduce_smax_nxv2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: sw a0, 12(sp) ; CHECK-NEXT: sw a0, 12(sp)
; CHECK-NEXT: sw zero, 8(sp) ; CHECK-NEXT: sw zero, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vredmax.vs v8, v8, v10 ; CHECK-NEXT: vredmax.vs v8, v8, v10
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vsrl.vx v8, v8, a1 ; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: vmv.x.s a1, v8
Show All 29 Lines
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: li a0, -1 ; CHECK-NEXT: li a0, -1
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: sw a0, 12(sp) ; CHECK-NEXT: sw a0, 12(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vredmin.vs v8, v8, v10 ; CHECK-NEXT: vredmin.vs v8, v8, v10
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vsrl.vx v8, v8, a1 ; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: vmv.x.s a1, v8
▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
define i64 @vreduce_smax_nxv4i64(<vscale x 4 x i64> %v) { define i64 @vreduce_smax_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-LABEL: vreduce_smax_nxv4i64: ; CHECK-LABEL: vreduce_smax_nxv4i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: sw a0, 12(sp) ; CHECK-NEXT: sw a0, 12(sp)
; CHECK-NEXT: sw zero, 8(sp) ; CHECK-NEXT: sw zero, 8(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vredmax.vs v8, v8, v12 ; CHECK-NEXT: vredmax.vs v8, v8, v12
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vsrl.vx v8, v8, a1 ; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: vmv.x.s a1, v8
Show All 29 Lines
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: li a0, -1 ; CHECK-NEXT: li a0, -1
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: sw a0, 12(sp) ; CHECK-NEXT: sw a0, 12(sp)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vredmin.vs v8, v8, v12 ; CHECK-NEXT: vredmin.vs v8, v8, v12
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vsrl.vx v8, v8, a1 ; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: vmv.x.s a1, v8
▲ Show 20 Lines • Show All 62 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll

Show First 20 Lines • Show All 1,322 Lines • ▼ Show 20 Lines
define signext i64 @vpreduce_add_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_add_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_add_nxv1i64: ; RV32-LABEL: vpreduce_add_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
; RV32-NEXT: vredsum.vs v9, v8, v9, v0.t ; RV32-NEXT: vredsum.vs v9, v8, v9, v0.t
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v9, a1 ; RV32-NEXT: vsrl.vx v8, v9, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 14 Lines
define signext i64 @vpwreduce_add_nxv1i32(i64 signext %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) { define signext i64 @vpwreduce_add_nxv1i32(i64 signext %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpwreduce_add_nxv1i32: ; RV32-LABEL: vpwreduce_add_nxv1i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e32, mf2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e32, mf2, tu, mu
; RV32-NEXT: vwredsum.vs v9, v8, v9, v0.t ; RV32-NEXT: vwredsum.vs v9, v8, v9, v0.t
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v9, a1 ; RV32-NEXT: vsrl.vx v8, v9, a1
Show All 17 Lines
define signext i64 @vpwreduce_uadd_nxv1i32(i64 signext %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) { define signext i64 @vpwreduce_uadd_nxv1i32(i64 signext %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpwreduce_uadd_nxv1i32: ; RV32-LABEL: vpwreduce_uadd_nxv1i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e32, mf2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e32, mf2, tu, mu
; RV32-NEXT: vwredsum.vs v9, v8, v9, v0.t ; RV32-NEXT: vwredsum.vs v9, v8, v9, v0.t
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v9, a1 ; RV32-NEXT: vsrl.vx v8, v9, a1
Show All 19 Lines
define signext i64 @vpreduce_umax_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_umax_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_umax_nxv1i64: ; RV32-LABEL: vpreduce_umax_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t ; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v9, a1 ; RV32-NEXT: vsrl.vx v8, v9, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_smax_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_smax_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_smax_nxv1i64: ; RV32-LABEL: vpreduce_smax_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
; RV32-NEXT: vredmax.vs v9, v8, v9, v0.t ; RV32-NEXT: vredmax.vs v9, v8, v9, v0.t
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v9, a1 ; RV32-NEXT: vsrl.vx v8, v9, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_umin_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_umin_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_umin_nxv1i64: ; RV32-LABEL: vpreduce_umin_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t ; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v9, a1 ; RV32-NEXT: vsrl.vx v8, v9, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_smin_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_smin_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_smin_nxv1i64: ; RV32-LABEL: vpreduce_smin_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
; RV32-NEXT: vredmin.vs v9, v8, v9, v0.t ; RV32-NEXT: vredmin.vs v9, v8, v9, v0.t
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v9, a1 ; RV32-NEXT: vsrl.vx v8, v9, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_and_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_and_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_and_nxv1i64: ; RV32-LABEL: vpreduce_and_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
; RV32-NEXT: vredand.vs v9, v8, v9, v0.t ; RV32-NEXT: vredand.vs v9, v8, v9, v0.t
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v9, a1 ; RV32-NEXT: vsrl.vx v8, v9, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_or_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_or_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_or_nxv1i64: ; RV32-LABEL: vpreduce_or_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
; RV32-NEXT: vredor.vs v9, v8, v9, v0.t ; RV32-NEXT: vredor.vs v9, v8, v9, v0.t
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v9, a1 ; RV32-NEXT: vsrl.vx v8, v9, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_xor_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_xor_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_xor_nxv1i64: ; RV32-LABEL: vpreduce_xor_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu
; RV32-NEXT: vredxor.vs v9, v8, v9, v0.t ; RV32-NEXT: vredxor.vs v9, v8, v9, v0.t
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v9, a1 ; RV32-NEXT: vsrl.vx v8, v9, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_add_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_add_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_add_nxv2i64: ; RV32-LABEL: vpreduce_add_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
; RV32-NEXT: vredsum.vs v10, v8, v10, v0.t ; RV32-NEXT: vredsum.vs v10, v8, v10, v0.t
; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v10, a1 ; RV32-NEXT: vsrl.vx v8, v10, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 14 Lines
define signext i64 @vwpreduce_add_nxv2i32(i64 signext %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) { define signext i64 @vwpreduce_add_nxv2i32(i64 signext %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vwpreduce_add_nxv2i32: ; RV32-LABEL: vwpreduce_add_nxv2i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e32, m1, tu, mu ; RV32-NEXT: vsetvli zero, a2, e32, m1, tu, mu
; RV32-NEXT: vwredsum.vs v9, v8, v9, v0.t ; RV32-NEXT: vwredsum.vs v9, v8, v9, v0.t
; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v9, a1 ; RV32-NEXT: vsrl.vx v8, v9, a1
Show All 17 Lines
define signext i64 @vwpreduce_uadd_nxv2i32(i64 signext %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) { define signext i64 @vwpreduce_uadd_nxv2i32(i64 signext %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vwpreduce_uadd_nxv2i32: ; RV32-LABEL: vwpreduce_uadd_nxv2i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e32, m1, tu, mu ; RV32-NEXT: vsetvli zero, a2, e32, m1, tu, mu
; RV32-NEXT: vwredsum.vs v9, v8, v9, v0.t ; RV32-NEXT: vwredsum.vs v9, v8, v9, v0.t
; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v9, a1 ; RV32-NEXT: vsrl.vx v8, v9, a1
Show All 19 Lines
define signext i64 @vpreduce_umax_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_umax_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_umax_nxv2i64: ; RV32-LABEL: vpreduce_umax_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
; RV32-NEXT: vredmaxu.vs v10, v8, v10, v0.t ; RV32-NEXT: vredmaxu.vs v10, v8, v10, v0.t
; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v10, a1 ; RV32-NEXT: vsrl.vx v8, v10, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_smax_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_smax_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_smax_nxv2i64: ; RV32-LABEL: vpreduce_smax_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
; RV32-NEXT: vredmax.vs v10, v8, v10, v0.t ; RV32-NEXT: vredmax.vs v10, v8, v10, v0.t
; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v10, a1 ; RV32-NEXT: vsrl.vx v8, v10, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_umin_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_umin_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_umin_nxv2i64: ; RV32-LABEL: vpreduce_umin_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
; RV32-NEXT: vredminu.vs v10, v8, v10, v0.t ; RV32-NEXT: vredminu.vs v10, v8, v10, v0.t
; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v10, a1 ; RV32-NEXT: vsrl.vx v8, v10, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_smin_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_smin_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_smin_nxv2i64: ; RV32-LABEL: vpreduce_smin_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
; RV32-NEXT: vredmin.vs v10, v8, v10, v0.t ; RV32-NEXT: vredmin.vs v10, v8, v10, v0.t
; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v10, a1 ; RV32-NEXT: vsrl.vx v8, v10, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_and_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_and_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_and_nxv2i64: ; RV32-LABEL: vpreduce_and_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
; RV32-NEXT: vredand.vs v10, v8, v10, v0.t ; RV32-NEXT: vredand.vs v10, v8, v10, v0.t
; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v10, a1 ; RV32-NEXT: vsrl.vx v8, v10, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_or_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_or_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_or_nxv2i64: ; RV32-LABEL: vpreduce_or_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
; RV32-NEXT: vredor.vs v10, v8, v10, v0.t ; RV32-NEXT: vredor.vs v10, v8, v10, v0.t
; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v10, a1 ; RV32-NEXT: vsrl.vx v8, v10, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_xor_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_xor_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_xor_nxv2i64: ; RV32-LABEL: vpreduce_xor_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu
; RV32-NEXT: vredxor.vs v10, v8, v10, v0.t ; RV32-NEXT: vredxor.vs v10, v8, v10, v0.t
; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v10, a1 ; RV32-NEXT: vsrl.vx v8, v10, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_add_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_add_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_add_nxv4i64: ; RV32-LABEL: vpreduce_add_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu
; RV32-NEXT: vredsum.vs v12, v8, v12, v0.t ; RV32-NEXT: vredsum.vs v12, v8, v12, v0.t
; RV32-NEXT: vmv.x.s a0, v12 ; RV32-NEXT: vmv.x.s a0, v12
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v12, a1 ; RV32-NEXT: vsrl.vx v8, v12, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 14 Lines
define signext i64 @vpwreduce_add_nxv4i32(i64 signext %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) { define signext i64 @vpwreduce_add_nxv4i32(i64 signext %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpwreduce_add_nxv4i32: ; RV32-LABEL: vpwreduce_add_nxv4i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e32, m2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e32, m2, tu, mu
; RV32-NEXT: vwredsum.vs v10, v8, v10, v0.t ; RV32-NEXT: vwredsum.vs v10, v8, v10, v0.t
; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v10, a1 ; RV32-NEXT: vsrl.vx v8, v10, a1
Show All 17 Lines
define signext i64 @vpwreduce_uadd_nxv4i32(i64 signext %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) { define signext i64 @vpwreduce_uadd_nxv4i32(i64 signext %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpwreduce_uadd_nxv4i32: ; RV32-LABEL: vpwreduce_uadd_nxv4i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e32, m2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e32, m2, tu, mu
; RV32-NEXT: vwredsumu.vs v10, v8, v10, v0.t ; RV32-NEXT: vwredsumu.vs v10, v8, v10, v0.t
; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; RV32-NEXT: vmv.x.s a0, v10 ; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v10, a1 ; RV32-NEXT: vsrl.vx v8, v10, a1
Show All 19 Lines
define signext i64 @vpreduce_umax_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_umax_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_umax_nxv4i64: ; RV32-LABEL: vpreduce_umax_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu
; RV32-NEXT: vredmaxu.vs v12, v8, v12, v0.t ; RV32-NEXT: vredmaxu.vs v12, v8, v12, v0.t
; RV32-NEXT: vmv.x.s a0, v12 ; RV32-NEXT: vmv.x.s a0, v12
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v12, a1 ; RV32-NEXT: vsrl.vx v8, v12, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_smax_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_smax_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_smax_nxv4i64: ; RV32-LABEL: vpreduce_smax_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu
; RV32-NEXT: vredmax.vs v12, v8, v12, v0.t ; RV32-NEXT: vredmax.vs v12, v8, v12, v0.t
; RV32-NEXT: vmv.x.s a0, v12 ; RV32-NEXT: vmv.x.s a0, v12
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v12, a1 ; RV32-NEXT: vsrl.vx v8, v12, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_umin_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_umin_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_umin_nxv4i64: ; RV32-LABEL: vpreduce_umin_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu
; RV32-NEXT: vredminu.vs v12, v8, v12, v0.t ; RV32-NEXT: vredminu.vs v12, v8, v12, v0.t
; RV32-NEXT: vmv.x.s a0, v12 ; RV32-NEXT: vmv.x.s a0, v12
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v12, a1 ; RV32-NEXT: vsrl.vx v8, v12, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_smin_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_smin_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_smin_nxv4i64: ; RV32-LABEL: vpreduce_smin_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu
; RV32-NEXT: vredmin.vs v12, v8, v12, v0.t ; RV32-NEXT: vredmin.vs v12, v8, v12, v0.t
; RV32-NEXT: vmv.x.s a0, v12 ; RV32-NEXT: vmv.x.s a0, v12
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v12, a1 ; RV32-NEXT: vsrl.vx v8, v12, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_and_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_and_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_and_nxv4i64: ; RV32-LABEL: vpreduce_and_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu
; RV32-NEXT: vredand.vs v12, v8, v12, v0.t ; RV32-NEXT: vredand.vs v12, v8, v12, v0.t
; RV32-NEXT: vmv.x.s a0, v12 ; RV32-NEXT: vmv.x.s a0, v12
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v12, a1 ; RV32-NEXT: vsrl.vx v8, v12, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_or_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_or_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_or_nxv4i64: ; RV32-LABEL: vpreduce_or_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu
; RV32-NEXT: vredor.vs v12, v8, v12, v0.t ; RV32-NEXT: vredor.vs v12, v8, v12, v0.t
; RV32-NEXT: vmv.x.s a0, v12 ; RV32-NEXT: vmv.x.s a0, v12
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v12, a1 ; RV32-NEXT: vsrl.vx v8, v12, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 16 Lines
define signext i64 @vpreduce_xor_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) { define signext i64 @vpreduce_xor_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_xor_nxv4i64: ; RV32-LABEL: vpreduce_xor_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu
; RV32-NEXT: vredxor.vs v12, v8, v12, v0.t ; RV32-NEXT: vredxor.vs v12, v8, v12, v0.t
; RV32-NEXT: vmv.x.s a0, v12 ; RV32-NEXT: vmv.x.s a0, v12
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vsrl.vx v8, v12, a1 ; RV32-NEXT: vsrl.vx v8, v12, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
Show All 14 Lines

llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll

Show First 20 Lines • Show All 1,891 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vrem.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vrem_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vrem_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vrem_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vrem_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: vrem.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vrem.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vrem.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vrem.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vrem_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vrem_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t ; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vrem.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vrem.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 11 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vrem.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vrem_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vrem_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vrem_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vrem_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vrem.vv v8, v8, v10 ; CHECK-NEXT: vrem.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vrem.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vrem.nxv2i64.i64(
<vscale x 2 x i64> undef, <vscale x 2 x i64> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vrem.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vrem_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vrem_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vrem.vv v8, v10, v12, v0.t ; CHECK-NEXT: vrem.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vrem.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vrem.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 11 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vrem.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vrem_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vrem_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vrem_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vrem_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vrem.vv v8, v8, v12 ; CHECK-NEXT: vrem.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vrem.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vrem.nxv4i64.i64(
<vscale x 4 x i64> undef, <vscale x 4 x i64> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vrem.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vrem_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vrem_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vrem.vv v8, v12, v16, v0.t ; CHECK-NEXT: vrem.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vrem.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vrem.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 11 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vrem.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vrem_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vrem_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vrem_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vrem_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vrem.vv v8, v8, v16 ; CHECK-NEXT: vrem.vv v8, v8, v16
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vrem.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vrem.nxv8i64.i64(
<vscale x 8 x i64> undef, <vscale x 8 x i64> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
Show All 12 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vrem.mask.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vrem_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vrem_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v24, (a0), zero ; CHECK-NEXT: vlse64.v v24, (a0), zero
; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vrem.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vrem.mask.nxv8i64.i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll

Show First 20 Lines • Show All 906 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vrem_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) { define <vscale x 1 x i64> @vrem_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; RV32-LABEL: vrem_vx_nxv1i64: ; RV32-LABEL: vrem_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vrem.vv v8, v8, v9 ; RV32-NEXT: vrem.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrem_vx_nxv1i64: ; RV64-LABEL: vrem_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
Show All 11 Lines
; RV32-V-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: addi sp, sp, -16
; RV32-V-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16
; RV32-V-NEXT: lui a0, 748983 ; RV32-V-NEXT: lui a0, 748983
; RV32-V-NEXT: addi a0, a0, -586 ; RV32-V-NEXT: addi a0, a0, -586
; RV32-V-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: sw a0, 12(sp)
; RV32-V-NEXT: lui a0, 898779 ; RV32-V-NEXT: lui a0, 898779
; RV32-V-NEXT: addi a0, a0, 1755 ; RV32-V-NEXT: addi a0, a0, 1755
; RV32-V-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: sw a0, 8(sp)
; RV32-V-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-V-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: addi a0, sp, 8
; RV32-V-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-V-NEXT: vlse64.v v9, (a0), zero ; RV32-V-NEXT: vlse64.v v9, (a0), zero
; RV32-V-NEXT: vmulh.vv v9, v8, v9 ; RV32-V-NEXT: vmulh.vv v9, v8, v9
; RV32-V-NEXT: li a0, 63 ; RV32-V-NEXT: li a0, 63
; RV32-V-NEXT: vsrl.vx v10, v9, a0 ; RV32-V-NEXT: vsrl.vx v10, v9, a0
; RV32-V-NEXT: vsra.vi v9, v9, 1 ; RV32-V-NEXT: vsra.vi v9, v9, 1
; RV32-V-NEXT: vadd.vv v9, v9, v10 ; RV32-V-NEXT: vadd.vv v9, v9, v10
; RV32-V-NEXT: li a0, -7 ; RV32-V-NEXT: li a0, -7
; RV32-V-NEXT: vnmsac.vx v8, a0, v9 ; RV32-V-NEXT: vnmsac.vx v8, a0, v9
Show All 38 Lines
define <vscale x 2 x i64> @vrem_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) { define <vscale x 2 x i64> @vrem_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; RV32-LABEL: vrem_vx_nxv2i64: ; RV32-LABEL: vrem_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vrem.vv v8, v8, v10 ; RV32-NEXT: vrem.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrem_vx_nxv2i64: ; RV64-LABEL: vrem_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
Show All 11 Lines
; RV32-V-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: addi sp, sp, -16
; RV32-V-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16
; RV32-V-NEXT: lui a0, 748983 ; RV32-V-NEXT: lui a0, 748983
; RV32-V-NEXT: addi a0, a0, -586 ; RV32-V-NEXT: addi a0, a0, -586
; RV32-V-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: sw a0, 12(sp)
; RV32-V-NEXT: lui a0, 898779 ; RV32-V-NEXT: lui a0, 898779
; RV32-V-NEXT: addi a0, a0, 1755 ; RV32-V-NEXT: addi a0, a0, 1755
; RV32-V-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: sw a0, 8(sp)
; RV32-V-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-V-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: addi a0, sp, 8
; RV32-V-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-V-NEXT: vlse64.v v10, (a0), zero ; RV32-V-NEXT: vlse64.v v10, (a0), zero
; RV32-V-NEXT: vmulh.vv v10, v8, v10 ; RV32-V-NEXT: vmulh.vv v10, v8, v10
; RV32-V-NEXT: li a0, 63 ; RV32-V-NEXT: li a0, 63
; RV32-V-NEXT: vsrl.vx v12, v10, a0 ; RV32-V-NEXT: vsrl.vx v12, v10, a0
; RV32-V-NEXT: vsra.vi v10, v10, 1 ; RV32-V-NEXT: vsra.vi v10, v10, 1
; RV32-V-NEXT: vadd.vv v10, v10, v12 ; RV32-V-NEXT: vadd.vv v10, v10, v12
; RV32-V-NEXT: li a0, -7 ; RV32-V-NEXT: li a0, -7
; RV32-V-NEXT: vnmsac.vx v8, a0, v10 ; RV32-V-NEXT: vnmsac.vx v8, a0, v10
Show All 38 Lines
define <vscale x 4 x i64> @vrem_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) { define <vscale x 4 x i64> @vrem_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; RV32-LABEL: vrem_vx_nxv4i64: ; RV32-LABEL: vrem_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vrem.vv v8, v8, v12 ; RV32-NEXT: vrem.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrem_vx_nxv4i64: ; RV64-LABEL: vrem_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
Show All 11 Lines
; RV32-V-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: addi sp, sp, -16
; RV32-V-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16
; RV32-V-NEXT: lui a0, 748983 ; RV32-V-NEXT: lui a0, 748983
; RV32-V-NEXT: addi a0, a0, -586 ; RV32-V-NEXT: addi a0, a0, -586
; RV32-V-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: sw a0, 12(sp)
; RV32-V-NEXT: lui a0, 898779 ; RV32-V-NEXT: lui a0, 898779
; RV32-V-NEXT: addi a0, a0, 1755 ; RV32-V-NEXT: addi a0, a0, 1755
; RV32-V-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: sw a0, 8(sp)
; RV32-V-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-V-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: addi a0, sp, 8
; RV32-V-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-V-NEXT: vlse64.v v12, (a0), zero ; RV32-V-NEXT: vlse64.v v12, (a0), zero
; RV32-V-NEXT: vmulh.vv v12, v8, v12 ; RV32-V-NEXT: vmulh.vv v12, v8, v12
; RV32-V-NEXT: li a0, 63 ; RV32-V-NEXT: li a0, 63
; RV32-V-NEXT: vsrl.vx v16, v12, a0 ; RV32-V-NEXT: vsrl.vx v16, v12, a0
; RV32-V-NEXT: vsra.vi v12, v12, 1 ; RV32-V-NEXT: vsra.vi v12, v12, 1
; RV32-V-NEXT: vadd.vv v12, v12, v16 ; RV32-V-NEXT: vadd.vv v12, v12, v16
; RV32-V-NEXT: li a0, -7 ; RV32-V-NEXT: li a0, -7
; RV32-V-NEXT: vnmsac.vx v8, a0, v12 ; RV32-V-NEXT: vnmsac.vx v8, a0, v12
Show All 38 Lines
define <vscale x 8 x i64> @vrem_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i64> @vrem_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: vrem_vx_nxv8i64: ; RV32-LABEL: vrem_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vrem.vv v8, v8, v16 ; RV32-NEXT: vrem.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrem_vx_nxv8i64: ; RV64-LABEL: vrem_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 11 Lines
; RV32-V-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: addi sp, sp, -16
; RV32-V-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16
; RV32-V-NEXT: lui a0, 748983 ; RV32-V-NEXT: lui a0, 748983
; RV32-V-NEXT: addi a0, a0, -586 ; RV32-V-NEXT: addi a0, a0, -586
; RV32-V-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: sw a0, 12(sp)
; RV32-V-NEXT: lui a0, 898779 ; RV32-V-NEXT: lui a0, 898779
; RV32-V-NEXT: addi a0, a0, 1755 ; RV32-V-NEXT: addi a0, a0, 1755
; RV32-V-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: sw a0, 8(sp)
; RV32-V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-V-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: addi a0, sp, 8
; RV32-V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-V-NEXT: vlse64.v v16, (a0), zero ; RV32-V-NEXT: vlse64.v v16, (a0), zero
; RV32-V-NEXT: vmulh.vv v16, v8, v16 ; RV32-V-NEXT: vmulh.vv v16, v8, v16
; RV32-V-NEXT: li a0, 63 ; RV32-V-NEXT: li a0, 63
; RV32-V-NEXT: vsrl.vx v24, v16, a0 ; RV32-V-NEXT: vsrl.vx v24, v16, a0
; RV32-V-NEXT: vsra.vi v16, v16, 1 ; RV32-V-NEXT: vsra.vi v16, v16, 1
; RV32-V-NEXT: vadd.vv v16, v16, v24 ; RV32-V-NEXT: vadd.vv v16, v16, v24
; RV32-V-NEXT: li a0, -7 ; RV32-V-NEXT: li a0, -7
; RV32-V-NEXT: vnmsac.vx v8, a0, v16 ; RV32-V-NEXT: vnmsac.vx v8, a0, v16
Show All 29 Lines

llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll

Show First 20 Lines • Show All 961 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vrem_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i64> @vrem_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vrem_vx_nxv1i64: ; RV32-LABEL: vrem_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vrem.vv v8, v8, v9, v0.t ; RV32-NEXT: vrem.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrem_vx_nxv1i64: ; RV64-LABEL: vrem_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vrem.vx v8, v8, a0, v0.t ; RV64-NEXT: vrem.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i64> @llvm.vp.srem.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i64> @llvm.vp.srem.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v ret <vscale x 1 x i64> %v
} }
define <vscale x 1 x i64> @vrem_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 1 x i64> @vrem_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vrem_vx_nxv1i64_unmasked: ; RV32-LABEL: vrem_vx_nxv1i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vrem.vv v8, v8, v9 ; RV32-NEXT: vrem.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrem_vx_nxv1i64_unmasked: ; RV64-LABEL: vrem_vx_nxv1i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <vscale x 2 x i64> @vrem_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i64> @vrem_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vrem_vx_nxv2i64: ; RV32-LABEL: vrem_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vrem.vv v8, v8, v10, v0.t ; RV32-NEXT: vrem.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrem_vx_nxv2i64: ; RV64-LABEL: vrem_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vrem.vx v8, v8, a0, v0.t ; RV64-NEXT: vrem.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i64> @llvm.vp.srem.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl) %v = call <vscale x 2 x i64> @llvm.vp.srem.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
define <vscale x 2 x i64> @vrem_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 2 x i64> @vrem_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vrem_vx_nxv2i64_unmasked: ; RV32-LABEL: vrem_vx_nxv2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vrem.vv v8, v8, v10 ; RV32-NEXT: vrem.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrem_vx_nxv2i64_unmasked: ; RV64-LABEL: vrem_vx_nxv2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <vscale x 4 x i64> @vrem_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i64> @vrem_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vrem_vx_nxv4i64: ; RV32-LABEL: vrem_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vrem.vv v8, v8, v12, v0.t ; RV32-NEXT: vrem.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrem_vx_nxv4i64: ; RV64-LABEL: vrem_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vrem.vx v8, v8, a0, v0.t ; RV64-NEXT: vrem.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i64> @llvm.vp.srem.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl) %v = call <vscale x 4 x i64> @llvm.vp.srem.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v ret <vscale x 4 x i64> %v
} }
define <vscale x 4 x i64> @vrem_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 4 x i64> @vrem_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vrem_vx_nxv4i64_unmasked: ; RV32-LABEL: vrem_vx_nxv4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vrem.vv v8, v8, v12 ; RV32-NEXT: vrem.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrem_vx_nxv4i64_unmasked: ; RV64-LABEL: vrem_vx_nxv4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <vscale x 8 x i64> @vrem_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vrem_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vrem_vx_nxv8i64: ; RV32-LABEL: vrem_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vrem.vv v8, v8, v16, v0.t ; RV32-NEXT: vrem.vv v8, v8, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrem_vx_nxv8i64: ; RV64-LABEL: vrem_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vrem.vx v8, v8, a0, v0.t ; RV64-NEXT: vrem.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i64> @llvm.vp.srem.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i64> @llvm.vp.srem.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i64> @vrem_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 8 x i64> @vrem_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vrem_vx_nxv8i64_unmasked: ; RV32-LABEL: vrem_vx_nxv8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vrem.vv v8, v8, v16 ; RV32-NEXT: vrem.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrem_vx_nxv8i64_unmasked: ; RV64-LABEL: vrem_vx_nxv8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 10 Lines

llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll

Show First 20 Lines • Show All 1,891 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vremu.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vremu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vremu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vremu_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vremu_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: vremu.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vremu.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vremu.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vremu.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vremu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vremu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vremu.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vremu.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 11 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vremu.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vremu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vremu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vremu_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vremu_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vremu.vv v8, v8, v10 ; CHECK-NEXT: vremu.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vremu.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vremu.nxv2i64.i64(
<vscale x 2 x i64> undef, <vscale x 2 x i64> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vremu.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vremu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vremu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vremu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vremu.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vremu.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vremu.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 11 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vremu.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vremu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vremu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vremu_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vremu_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vremu.vv v8, v8, v12 ; CHECK-NEXT: vremu.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vremu.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vremu.nxv4i64.i64(
<vscale x 4 x i64> undef, <vscale x 4 x i64> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vremu.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vremu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vremu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vremu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vremu.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vremu.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vremu.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 11 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vremu.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vremu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vremu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vremu_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vremu_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vremu.vv v8, v8, v16 ; CHECK-NEXT: vremu.vv v8, v8, v16
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vremu.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vremu.nxv8i64.i64(
<vscale x 8 x i64> undef, <vscale x 8 x i64> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
Show All 12 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vremu.mask.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vremu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vremu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v24, (a0), zero ; CHECK-NEXT: vlse64.v v24, (a0), zero
; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vremu.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vremu.mask.nxv8i64.i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll

Show First 20 Lines • Show All 831 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vremu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) { define <vscale x 1 x i64> @vremu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; RV32-LABEL: vremu_vx_nxv1i64: ; RV32-LABEL: vremu_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vremu.vv v8, v8, v9 ; RV32-NEXT: vremu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vremu_vx_nxv1i64: ; RV64-LABEL: vremu_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
Show All 9 Lines
; RV32-V-LABEL: vremu_vi_nxv1i64_0: ; RV32-V-LABEL: vremu_vi_nxv1i64_0:
; RV32-V: # %bb.0: ; RV32-V: # %bb.0:
; RV32-V-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: addi sp, sp, -16
; RV32-V-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16
; RV32-V-NEXT: lui a0, 131072 ; RV32-V-NEXT: lui a0, 131072
; RV32-V-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: sw a0, 12(sp)
; RV32-V-NEXT: li a0, 1 ; RV32-V-NEXT: li a0, 1
; RV32-V-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: sw a0, 8(sp)
; RV32-V-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-V-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: addi a0, sp, 8
; RV32-V-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-V-NEXT: vlse64.v v9, (a0), zero ; RV32-V-NEXT: vlse64.v v9, (a0), zero
; RV32-V-NEXT: vmulhu.vv v9, v8, v9 ; RV32-V-NEXT: vmulhu.vv v9, v8, v9
; RV32-V-NEXT: li a0, 61 ; RV32-V-NEXT: li a0, 61
; RV32-V-NEXT: vsrl.vx v9, v9, a0 ; RV32-V-NEXT: vsrl.vx v9, v9, a0
; RV32-V-NEXT: li a0, -7 ; RV32-V-NEXT: li a0, -7
; RV32-V-NEXT: vnmsac.vx v8, a0, v9 ; RV32-V-NEXT: vnmsac.vx v8, a0, v9
; RV32-V-NEXT: addi sp, sp, 16 ; RV32-V-NEXT: addi sp, sp, 16
; RV32-V-NEXT: ret ; RV32-V-NEXT: ret
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
define <vscale x 2 x i64> @vremu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) { define <vscale x 2 x i64> @vremu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; RV32-LABEL: vremu_vx_nxv2i64: ; RV32-LABEL: vremu_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vremu.vv v8, v8, v10 ; RV32-NEXT: vremu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vremu_vx_nxv2i64: ; RV64-LABEL: vremu_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
Show All 9 Lines
; RV32-V-LABEL: vremu_vi_nxv2i64_0: ; RV32-V-LABEL: vremu_vi_nxv2i64_0:
; RV32-V: # %bb.0: ; RV32-V: # %bb.0:
; RV32-V-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: addi sp, sp, -16
; RV32-V-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16
; RV32-V-NEXT: lui a0, 131072 ; RV32-V-NEXT: lui a0, 131072
; RV32-V-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: sw a0, 12(sp)
; RV32-V-NEXT: li a0, 1 ; RV32-V-NEXT: li a0, 1
; RV32-V-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: sw a0, 8(sp)
; RV32-V-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-V-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: addi a0, sp, 8
; RV32-V-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-V-NEXT: vlse64.v v10, (a0), zero ; RV32-V-NEXT: vlse64.v v10, (a0), zero
; RV32-V-NEXT: vmulhu.vv v10, v8, v10 ; RV32-V-NEXT: vmulhu.vv v10, v8, v10
; RV32-V-NEXT: li a0, 61 ; RV32-V-NEXT: li a0, 61
; RV32-V-NEXT: vsrl.vx v10, v10, a0 ; RV32-V-NEXT: vsrl.vx v10, v10, a0
; RV32-V-NEXT: li a0, -7 ; RV32-V-NEXT: li a0, -7
; RV32-V-NEXT: vnmsac.vx v8, a0, v10 ; RV32-V-NEXT: vnmsac.vx v8, a0, v10
; RV32-V-NEXT: addi sp, sp, 16 ; RV32-V-NEXT: addi sp, sp, 16
; RV32-V-NEXT: ret ; RV32-V-NEXT: ret
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
define <vscale x 4 x i64> @vremu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) { define <vscale x 4 x i64> @vremu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; RV32-LABEL: vremu_vx_nxv4i64: ; RV32-LABEL: vremu_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vremu.vv v8, v8, v12 ; RV32-NEXT: vremu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vremu_vx_nxv4i64: ; RV64-LABEL: vremu_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
Show All 9 Lines
; RV32-V-LABEL: vremu_vi_nxv4i64_0: ; RV32-V-LABEL: vremu_vi_nxv4i64_0:
; RV32-V: # %bb.0: ; RV32-V: # %bb.0:
; RV32-V-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: addi sp, sp, -16
; RV32-V-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16
; RV32-V-NEXT: lui a0, 131072 ; RV32-V-NEXT: lui a0, 131072
; RV32-V-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: sw a0, 12(sp)
; RV32-V-NEXT: li a0, 1 ; RV32-V-NEXT: li a0, 1
; RV32-V-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: sw a0, 8(sp)
; RV32-V-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-V-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: addi a0, sp, 8
; RV32-V-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-V-NEXT: vlse64.v v12, (a0), zero ; RV32-V-NEXT: vlse64.v v12, (a0), zero
; RV32-V-NEXT: vmulhu.vv v12, v8, v12 ; RV32-V-NEXT: vmulhu.vv v12, v8, v12
; RV32-V-NEXT: li a0, 61 ; RV32-V-NEXT: li a0, 61
; RV32-V-NEXT: vsrl.vx v12, v12, a0 ; RV32-V-NEXT: vsrl.vx v12, v12, a0
; RV32-V-NEXT: li a0, -7 ; RV32-V-NEXT: li a0, -7
; RV32-V-NEXT: vnmsac.vx v8, a0, v12 ; RV32-V-NEXT: vnmsac.vx v8, a0, v12
; RV32-V-NEXT: addi sp, sp, 16 ; RV32-V-NEXT: addi sp, sp, 16
; RV32-V-NEXT: ret ; RV32-V-NEXT: ret
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
define <vscale x 8 x i64> @vremu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i64> @vremu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: vremu_vx_nxv8i64: ; RV32-LABEL: vremu_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vremu.vv v8, v8, v16 ; RV32-NEXT: vremu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vremu_vx_nxv8i64: ; RV64-LABEL: vremu_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 9 Lines
; RV32-V-LABEL: vremu_vi_nxv8i64_0: ; RV32-V-LABEL: vremu_vi_nxv8i64_0:
; RV32-V: # %bb.0: ; RV32-V: # %bb.0:
; RV32-V-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: addi sp, sp, -16
; RV32-V-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16
; RV32-V-NEXT: lui a0, 131072 ; RV32-V-NEXT: lui a0, 131072
; RV32-V-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: sw a0, 12(sp)
; RV32-V-NEXT: li a0, 1 ; RV32-V-NEXT: li a0, 1
; RV32-V-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: sw a0, 8(sp)
; RV32-V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-V-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: addi a0, sp, 8
; RV32-V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-V-NEXT: vlse64.v v16, (a0), zero ; RV32-V-NEXT: vlse64.v v16, (a0), zero
; RV32-V-NEXT: vmulhu.vv v16, v8, v16 ; RV32-V-NEXT: vmulhu.vv v16, v8, v16
; RV32-V-NEXT: li a0, 61 ; RV32-V-NEXT: li a0, 61
; RV32-V-NEXT: vsrl.vx v16, v16, a0 ; RV32-V-NEXT: vsrl.vx v16, v16, a0
; RV32-V-NEXT: li a0, -7 ; RV32-V-NEXT: li a0, -7
; RV32-V-NEXT: vnmsac.vx v8, a0, v16 ; RV32-V-NEXT: vnmsac.vx v8, a0, v16
; RV32-V-NEXT: addi sp, sp, 16 ; RV32-V-NEXT: addi sp, sp, 16
; RV32-V-NEXT: ret ; RV32-V-NEXT: ret
▲ Show 20 Lines • Show All 56 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll

Show First 20 Lines • Show All 960 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vremu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i64> @vremu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vremu_vx_nxv1i64: ; RV32-LABEL: vremu_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vremu.vv v8, v8, v9, v0.t ; RV32-NEXT: vremu.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vremu_vx_nxv1i64: ; RV64-LABEL: vremu_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vremu.vx v8, v8, a0, v0.t ; RV64-NEXT: vremu.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i64> @llvm.vp.urem.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i64> @llvm.vp.urem.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v ret <vscale x 1 x i64> %v
} }
define <vscale x 1 x i64> @vremu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 1 x i64> @vremu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vremu_vx_nxv1i64_unmasked: ; RV32-LABEL: vremu_vx_nxv1i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vremu.vv v8, v8, v9 ; RV32-NEXT: vremu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vremu_vx_nxv1i64_unmasked: ; RV64-LABEL: vremu_vx_nxv1i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <vscale x 2 x i64> @vremu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i64> @vremu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vremu_vx_nxv2i64: ; RV32-LABEL: vremu_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vremu.vv v8, v8, v10, v0.t ; RV32-NEXT: vremu.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vremu_vx_nxv2i64: ; RV64-LABEL: vremu_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vremu.vx v8, v8, a0, v0.t ; RV64-NEXT: vremu.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i64> @llvm.vp.urem.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl) %v = call <vscale x 2 x i64> @llvm.vp.urem.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
define <vscale x 2 x i64> @vremu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 2 x i64> @vremu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vremu_vx_nxv2i64_unmasked: ; RV32-LABEL: vremu_vx_nxv2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vremu.vv v8, v8, v10 ; RV32-NEXT: vremu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vremu_vx_nxv2i64_unmasked: ; RV64-LABEL: vremu_vx_nxv2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <vscale x 4 x i64> @vremu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i64> @vremu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vremu_vx_nxv4i64: ; RV32-LABEL: vremu_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vremu.vv v8, v8, v12, v0.t ; RV32-NEXT: vremu.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vremu_vx_nxv4i64: ; RV64-LABEL: vremu_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vremu.vx v8, v8, a0, v0.t ; RV64-NEXT: vremu.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i64> @llvm.vp.urem.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl) %v = call <vscale x 4 x i64> @llvm.vp.urem.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v ret <vscale x 4 x i64> %v
} }
define <vscale x 4 x i64> @vremu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 4 x i64> @vremu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vremu_vx_nxv4i64_unmasked: ; RV32-LABEL: vremu_vx_nxv4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vremu.vv v8, v8, v12 ; RV32-NEXT: vremu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vremu_vx_nxv4i64_unmasked: ; RV64-LABEL: vremu_vx_nxv4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <vscale x 8 x i64> @vremu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vremu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vremu_vx_nxv8i64: ; RV32-LABEL: vremu_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vremu.vv v8, v8, v16, v0.t ; RV32-NEXT: vremu.vv v8, v8, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vremu_vx_nxv8i64: ; RV64-LABEL: vremu_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vremu.vx v8, v8, a0, v0.t ; RV64-NEXT: vremu.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i64> @llvm.vp.urem.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i64> @llvm.vp.urem.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i64> @vremu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 8 x i64> @vremu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vremu_vx_nxv8i64_unmasked: ; RV32-LABEL: vremu_vx_nxv8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vremu.vv v8, v8, v16 ; RV32-NEXT: vremu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vremu_vx_nxv8i64_unmasked: ; RV64-LABEL: vremu_vx_nxv8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 10 Lines

llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll

Show First 20 Lines • Show All 435 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vrsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) { define <vscale x 1 x i64> @vrsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; RV32-LABEL: vrsub_vx_nxv1i64: ; RV32-LABEL: vrsub_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsub.vv v8, v9, v8 ; RV32-NEXT: vsub.vv v8, v9, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrsub_vx_nxv1i64: ; RV64-LABEL: vrsub_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
Show All 19 Lines
define <vscale x 2 x i64> @vrsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) { define <vscale x 2 x i64> @vrsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; RV32-LABEL: vrsub_vx_nxv2i64: ; RV32-LABEL: vrsub_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsub.vv v8, v10, v8 ; RV32-NEXT: vsub.vv v8, v10, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrsub_vx_nxv2i64: ; RV64-LABEL: vrsub_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
Show All 19 Lines
define <vscale x 4 x i64> @vrsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) { define <vscale x 4 x i64> @vrsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; RV32-LABEL: vrsub_vx_nxv4i64: ; RV32-LABEL: vrsub_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsub.vv v8, v12, v8 ; RV32-NEXT: vsub.vv v8, v12, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrsub_vx_nxv4i64: ; RV64-LABEL: vrsub_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
Show All 19 Lines
define <vscale x 8 x i64> @vrsub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i64> @vrsub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: vrsub_vx_nxv8i64: ; RV32-LABEL: vrsub_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsub.vv v8, v16, v8 ; RV32-NEXT: vsub.vv v8, v16, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrsub_vx_nxv8i64: ; RV64-LABEL: vrsub_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll

Show First 20 Lines • Show All 979 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vrsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i64> @vrsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vrsub_vx_nxv1i64: ; RV32-LABEL: vrsub_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vsub.vv v8, v9, v8, v0.t ; RV32-NEXT: vsub.vv v8, v9, v8, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrsub_vx_nxv1i64: ; RV64-LABEL: vrsub_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vrsub.vx v8, v8, a0, v0.t ; RV64-NEXT: vrsub.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i64> @llvm.vp.sub.nxv1i64(<vscale x 1 x i64> %vb, <vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i64> @llvm.vp.sub.nxv1i64(<vscale x 1 x i64> %vb, <vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v ret <vscale x 1 x i64> %v
} }
define <vscale x 1 x i64> @vrsub_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 1 x i64> @vrsub_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vrsub_vx_nxv1i64_unmasked: ; RV32-LABEL: vrsub_vx_nxv1i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vsub.vv v8, v9, v8 ; RV32-NEXT: vsub.vv v8, v9, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrsub_vx_nxv1i64_unmasked: ; RV64-LABEL: vrsub_vx_nxv1i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 38 Lines
define <vscale x 2 x i64> @vrsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i64> @vrsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vrsub_vx_nxv2i64: ; RV32-LABEL: vrsub_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vsub.vv v8, v10, v8, v0.t ; RV32-NEXT: vsub.vv v8, v10, v8, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrsub_vx_nxv2i64: ; RV64-LABEL: vrsub_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vrsub.vx v8, v8, a0, v0.t ; RV64-NEXT: vrsub.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i64> @llvm.vp.sub.nxv2i64(<vscale x 2 x i64> %vb, <vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl) %v = call <vscale x 2 x i64> @llvm.vp.sub.nxv2i64(<vscale x 2 x i64> %vb, <vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
define <vscale x 2 x i64> @vrsub_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 2 x i64> @vrsub_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vrsub_vx_nxv2i64_unmasked: ; RV32-LABEL: vrsub_vx_nxv2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vsub.vv v8, v10, v8 ; RV32-NEXT: vsub.vv v8, v10, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrsub_vx_nxv2i64_unmasked: ; RV64-LABEL: vrsub_vx_nxv2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 38 Lines
define <vscale x 4 x i64> @vrsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i64> @vrsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vrsub_vx_nxv4i64: ; RV32-LABEL: vrsub_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vsub.vv v8, v12, v8, v0.t ; RV32-NEXT: vsub.vv v8, v12, v8, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrsub_vx_nxv4i64: ; RV64-LABEL: vrsub_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vrsub.vx v8, v8, a0, v0.t ; RV64-NEXT: vrsub.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i64> @llvm.vp.sub.nxv4i64(<vscale x 4 x i64> %vb, <vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 %evl) %v = call <vscale x 4 x i64> @llvm.vp.sub.nxv4i64(<vscale x 4 x i64> %vb, <vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v ret <vscale x 4 x i64> %v
} }
define <vscale x 4 x i64> @vrsub_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 4 x i64> @vrsub_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vrsub_vx_nxv4i64_unmasked: ; RV32-LABEL: vrsub_vx_nxv4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vsub.vv v8, v12, v8 ; RV32-NEXT: vsub.vv v8, v12, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrsub_vx_nxv4i64_unmasked: ; RV64-LABEL: vrsub_vx_nxv4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 38 Lines
define <vscale x 8 x i64> @vrsub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vrsub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vrsub_vx_nxv8i64: ; RV32-LABEL: vrsub_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vsub.vv v8, v16, v8, v0.t ; RV32-NEXT: vsub.vv v8, v16, v8, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrsub_vx_nxv8i64: ; RV64-LABEL: vrsub_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vrsub.vx v8, v8, a0, v0.t ; RV64-NEXT: vrsub.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i64> @llvm.vp.sub.nxv8i64(<vscale x 8 x i64> %vb, <vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i64> @llvm.vp.sub.nxv8i64(<vscale x 8 x i64> %vb, <vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i64> @vrsub_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 8 x i64> @vrsub_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vrsub_vx_nxv8i64_unmasked: ; RV32-LABEL: vrsub_vx_nxv8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vsub.vv v8, v16, v8 ; RV32-NEXT: vsub.vv v8, v16, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrsub_vx_nxv8i64_unmasked: ; RV64-LABEL: vrsub_vx_nxv8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 36 Lines

llvm/test/CodeGen/RISCV/rvv/vrsub.ll

Show First 20 Lines • Show All 837 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vrsub.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 1 x i64> @intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsub.vv v8, v9, v8 ; RV32-NEXT: vsub.vv v8, v9, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vrsub.mask.nxv1i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 1 x i64> @intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i64> @intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsub.vv v8, v10, v9, v0.t ; RV32-NEXT: vsub.vv v8, v10, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vrsub.nxv2i64.i64(
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 2 x i64> @intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsub.vv v8, v10, v8 ; RV32-NEXT: vsub.vv v8, v10, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vrsub.mask.nxv2i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 2 x i64> @intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i64> @intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsub.vv v8, v12, v10, v0.t ; RV32-NEXT: vsub.vv v8, v12, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vrsub.nxv4i64.i64(
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 4 x i64> @intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsub.vv v8, v12, v8 ; RV32-NEXT: vsub.vv v8, v12, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vrsub.mask.nxv4i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 4 x i64> @intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i64> @intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsub.vv v8, v16, v12, v0.t ; RV32-NEXT: vsub.vv v8, v16, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vrsub.nxv8i64.i64(
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 8 x i64> @intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsub.vv v8, v16, v8 ; RV32-NEXT: vsub.vv v8, v16, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vrsub.mask.nxv8i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 8 x i64> @intrinsic_vrsub_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i64> @intrinsic_vrsub_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vrsub_mask_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vrsub_mask_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsub.vv v8, v24, v16, v0.t ; RV32-NEXT: vsub.vv v8, v24, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vrsub_mask_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vrsub_mask_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
▲ Show 20 Lines • Show All 738 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll

Show First 20 Lines • Show All 1,891 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vsadd.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vsadd_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vsadd_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsadd_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vsadd_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: vsadd.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsadd.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vsadd.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vsadd.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vsadd_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vsadd_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsadd.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vsadd.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 11 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vsadd.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vsadd_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vsadd_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsadd_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vsadd_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsadd.vv v8, v8, v10 ; CHECK-NEXT: vsadd.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsadd.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vsadd.nxv2i64.i64(
<vscale x 2 x i64> undef, <vscale x 2 x i64> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vsadd.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vsadd_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vsadd_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: vsadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsadd.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vsadd.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 11 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vsadd.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vsadd_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vsadd_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsadd_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vsadd_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsadd.vv v8, v8, v12 ; CHECK-NEXT: vsadd.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsadd.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vsadd.nxv4i64.i64(
<vscale x 4 x i64> undef, <vscale x 4 x i64> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vsadd.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vsadd_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vsadd_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: vsadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsadd.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vsadd.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 11 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vsadd.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vsadd_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vsadd_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsadd_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vsadd_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsadd.vv v8, v8, v16 ; CHECK-NEXT: vsadd.vv v8, v8, v16
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsadd.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsadd.nxv8i64.i64(
<vscale x 8 x i64> undef, <vscale x 8 x i64> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
Show All 12 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vsadd.mask.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vsadd_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vsadd_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v24, (a0), zero ; CHECK-NEXT: vlse64.v v24, (a0), zero
; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsadd.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsadd.mask.nxv8i64.i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
▲ Show 20 Lines • Show All 732 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll

Show First 20 Lines • Show All 665 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @sadd_nxv1i64_vx(<vscale x 1 x i64> %va, i64 %b) { define <vscale x 1 x i64> @sadd_nxv1i64_vx(<vscale x 1 x i64> %va, i64 %b) {
; RV32-LABEL: sadd_nxv1i64_vx: ; RV32-LABEL: sadd_nxv1i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsadd.vv v8, v8, v9 ; RV32-NEXT: vsadd.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: sadd_nxv1i64_vx: ; RV64-LABEL: sadd_nxv1i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
Show All 31 Lines
define <vscale x 2 x i64> @sadd_nxv2i64_vx(<vscale x 2 x i64> %va, i64 %b) { define <vscale x 2 x i64> @sadd_nxv2i64_vx(<vscale x 2 x i64> %va, i64 %b) {
; RV32-LABEL: sadd_nxv2i64_vx: ; RV32-LABEL: sadd_nxv2i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsadd.vv v8, v8, v10 ; RV32-NEXT: vsadd.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: sadd_nxv2i64_vx: ; RV64-LABEL: sadd_nxv2i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
Show All 31 Lines
define <vscale x 4 x i64> @sadd_nxv4i64_vx(<vscale x 4 x i64> %va, i64 %b) { define <vscale x 4 x i64> @sadd_nxv4i64_vx(<vscale x 4 x i64> %va, i64 %b) {
; RV32-LABEL: sadd_nxv4i64_vx: ; RV32-LABEL: sadd_nxv4i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsadd.vv v8, v8, v12 ; RV32-NEXT: vsadd.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: sadd_nxv4i64_vx: ; RV64-LABEL: sadd_nxv4i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
Show All 31 Lines
define <vscale x 8 x i64> @sadd_nxv8i64_vx(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i64> @sadd_nxv8i64_vx(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: sadd_nxv8i64_vx: ; RV32-LABEL: sadd_nxv8i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsadd.vv v8, v8, v16 ; RV32-NEXT: vsadd.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: sadd_nxv8i64_vx: ; RV64-LABEL: sadd_nxv8i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 19 Lines

llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll

Show First 20 Lines • Show All 1,891 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vsaddu.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vsaddu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vsaddu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsaddu_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vsaddu_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vsaddu.vv v8, v8, v9 ; CHECK-NEXT: vsaddu.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsaddu.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vsaddu.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vsaddu.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vsaddu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vsaddu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsaddu.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vsaddu.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 11 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vsaddu.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vsaddu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vsaddu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsaddu_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vsaddu_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsaddu.vv v8, v8, v10 ; CHECK-NEXT: vsaddu.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsaddu.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vsaddu.nxv2i64.i64(
<vscale x 2 x i64> undef, <vscale x 2 x i64> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vsaddu.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vsaddu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vsaddu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsaddu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vsaddu.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsaddu.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vsaddu.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 11 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vsaddu.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vsaddu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vsaddu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsaddu_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vsaddu_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsaddu.vv v8, v8, v12 ; CHECK-NEXT: vsaddu.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsaddu.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vsaddu.nxv4i64.i64(
<vscale x 4 x i64> undef, <vscale x 4 x i64> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vsaddu.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vsaddu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vsaddu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsaddu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vsaddu.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsaddu.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vsaddu.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 11 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vsaddu.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vsaddu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vsaddu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsaddu_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vsaddu_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsaddu.vv v8, v8, v16 ; CHECK-NEXT: vsaddu.vv v8, v8, v16
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsaddu.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsaddu.nxv8i64.i64(
<vscale x 8 x i64> undef, <vscale x 8 x i64> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
Show All 12 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vsaddu.mask.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vsaddu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vsaddu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v24, (a0), zero ; CHECK-NEXT: vlse64.v v24, (a0), zero
; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsaddu.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsaddu.mask.nxv8i64.i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
▲ Show 20 Lines • Show All 732 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll

Show First 20 Lines • Show All 665 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @uadd_nxv1i64_vx(<vscale x 1 x i64> %va, i64 %b) { define <vscale x 1 x i64> @uadd_nxv1i64_vx(<vscale x 1 x i64> %va, i64 %b) {
; RV32-LABEL: uadd_nxv1i64_vx: ; RV32-LABEL: uadd_nxv1i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsaddu.vv v8, v8, v9 ; RV32-NEXT: vsaddu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: uadd_nxv1i64_vx: ; RV64-LABEL: uadd_nxv1i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
Show All 31 Lines
define <vscale x 2 x i64> @uadd_nxv2i64_vx(<vscale x 2 x i64> %va, i64 %b) { define <vscale x 2 x i64> @uadd_nxv2i64_vx(<vscale x 2 x i64> %va, i64 %b) {
; RV32-LABEL: uadd_nxv2i64_vx: ; RV32-LABEL: uadd_nxv2i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsaddu.vv v8, v8, v10 ; RV32-NEXT: vsaddu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: uadd_nxv2i64_vx: ; RV64-LABEL: uadd_nxv2i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
Show All 31 Lines
define <vscale x 4 x i64> @uadd_nxv4i64_vx(<vscale x 4 x i64> %va, i64 %b) { define <vscale x 4 x i64> @uadd_nxv4i64_vx(<vscale x 4 x i64> %va, i64 %b) {
; RV32-LABEL: uadd_nxv4i64_vx: ; RV32-LABEL: uadd_nxv4i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsaddu.vv v8, v8, v12 ; RV32-NEXT: vsaddu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: uadd_nxv4i64_vx: ; RV64-LABEL: uadd_nxv4i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
Show All 31 Lines
define <vscale x 8 x i64> @uadd_nxv8i64_vx(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i64> @uadd_nxv8i64_vx(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: uadd_nxv8i64_vx: ; RV32-LABEL: uadd_nxv8i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsaddu.vv v8, v8, v16 ; RV32-NEXT: vsaddu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: uadd_nxv8i64_vx: ; RV64-LABEL: uadd_nxv8i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 19 Lines

llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll

Show First 20 Lines • Show All 968 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vsbc.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vsbc_vxm_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vsbc_vxm_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsbc_vxm_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vsbc_vxm_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0 ; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsbc.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vsbc.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vsbc.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vsbc_vxm_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i64> @intrinsic_vsbc_vxm_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsbc_vxm_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vsbc_vxm_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsbc.vvm v8, v8, v10, v0 ; CHECK-NEXT: vsbc.vvm v8, v8, v10, v0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsbc.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vsbc.nxv2i64.i64(
<vscale x 2 x i64> undef, <vscale x 2 x i64> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vsbc.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vsbc_vxm_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i64> @intrinsic_vsbc_vxm_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsbc_vxm_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vsbc_vxm_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsbc.vvm v8, v8, v12, v0 ; CHECK-NEXT: vsbc.vvm v8, v8, v12, v0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsbc.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vsbc.nxv4i64.i64(
<vscale x 4 x i64> undef, <vscale x 4 x i64> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vsbc.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vsbc_vxm_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i64> @intrinsic_vsbc_vxm_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsbc_vxm_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vsbc_vxm_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsbc.vvm v8, v8, v16, v0 ; CHECK-NEXT: vsbc.vvm v8, v8, v16, v0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsbc.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsbc.nxv8i64.i64(
<vscale x 8 x i64> undef, <vscale x 8 x i64> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i64 %1, i64 %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll

Show First 20 Lines • Show All 658 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vmerge_xv_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %cond) { define <vscale x 1 x i64> @vmerge_xv_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %cond) {
; CHECK-LABEL: vmerge_xv_nxv1i64: ; CHECK-LABEL: vmerge_xv_nxv1i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i64> %splat, <vscale x 1 x i64> %va %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i64> %splat, <vscale x 1 x i64> %va
ret <vscale x 1 x i64> %vc ret <vscale x 1 x i64> %vc
Show All 23 Lines
define <vscale x 2 x i64> @vmerge_xv_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %cond) { define <vscale x 2 x i64> @vmerge_xv_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %cond) {
; CHECK-LABEL: vmerge_xv_nxv2i64: ; CHECK-LABEL: vmerge_xv_nxv2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
%vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i64> %splat, <vscale x 2 x i64> %va %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i64> %splat, <vscale x 2 x i64> %va
ret <vscale x 2 x i64> %vc ret <vscale x 2 x i64> %vc
Show All 23 Lines
define <vscale x 4 x i64> @vmerge_xv_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %cond) { define <vscale x 4 x i64> @vmerge_xv_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %cond) {
; CHECK-LABEL: vmerge_xv_nxv4i64: ; CHECK-LABEL: vmerge_xv_nxv4i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
%vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i64> %splat, <vscale x 4 x i64> %va %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i64> %splat, <vscale x 4 x i64> %va
ret <vscale x 4 x i64> %vc ret <vscale x 4 x i64> %vc
Show All 23 Lines
define <vscale x 8 x i64> @vmerge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %cond) { define <vscale x 8 x i64> @vmerge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %cond) {
; CHECK-LABEL: vmerge_xv_nxv8i64: ; CHECK-LABEL: vmerge_xv_nxv8i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i64> %splat, <vscale x 8 x i64> %va %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i64> %splat, <vscale x 8 x i64> %va
ret <vscale x 8 x i64> %vc ret <vscale x 8 x i64> %vc
Show All 32 Lines

llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll

Show First 20 Lines • Show All 1,891 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: vsmul.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vsmul_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vsmul_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 11 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vsmul_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vsmul_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsmul.vv v8, v8, v10 ; CHECK-NEXT: vsmul.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64(
<vscale x 2 x i64> undef, <vscale x 2 x i64> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vsmul.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vsmul_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vsmul_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t ; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsmul.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vsmul.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 11 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vsmul_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vsmul_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsmul.vv v8, v8, v12 ; CHECK-NEXT: vsmul.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64(
<vscale x 4 x i64> undef, <vscale x 4 x i64> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vsmul.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vsmul_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vsmul_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t ; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsmul.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vsmul.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 11 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vsmul_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vsmul_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsmul.vv v8, v8, v16 ; CHECK-NEXT: vsmul.vv v8, v8, v16
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64(
<vscale x 8 x i64> undef, <vscale x 8 x i64> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
Show All 12 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vsmul.mask.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vsmul_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vsmul_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v24, (a0), zero ; CHECK-NEXT: vlse64.v v24, (a0), zero
; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsmul.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsmul.mask.nxv8i64.i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; RV32V-LABEL: vsplat_nxv8i64_4: ; RV32V-LABEL: vsplat_nxv8i64_4:
; RV32V: # %bb.0: ; RV32V: # %bb.0:
; RV32V-NEXT: addi sp, sp, -16 ; RV32V-NEXT: addi sp, sp, -16
; RV32V-NEXT: .cfi_def_cfa_offset 16 ; RV32V-NEXT: .cfi_def_cfa_offset 16
; RV32V-NEXT: sw zero, 12(sp) ; RV32V-NEXT: sw zero, 12(sp)
; RV32V-NEXT: lui a0, 1028096 ; RV32V-NEXT: lui a0, 1028096
; RV32V-NEXT: addi a0, a0, -1281 ; RV32V-NEXT: addi a0, a0, -1281
; RV32V-NEXT: sw a0, 8(sp) ; RV32V-NEXT: sw a0, 8(sp)
; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32V-NEXT: addi a0, sp, 8 ; RV32V-NEXT: addi a0, sp, 8
; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32V-NEXT: vlse64.v v8, (a0), zero ; RV32V-NEXT: vlse64.v v8, (a0), zero
; RV32V-NEXT: addi sp, sp, 16 ; RV32V-NEXT: addi sp, sp, 16
; RV32V-NEXT: ret ; RV32V-NEXT: ret
; ;
; RV64V-LABEL: vsplat_nxv8i64_4: ; RV64V-LABEL: vsplat_nxv8i64_4:
; RV64V: # %bb.0: ; RV64V: # %bb.0:
; RV64V-NEXT: li a0, 251 ; RV64V-NEXT: li a0, 251
; RV64V-NEXT: slli a0, a0, 24 ; RV64V-NEXT: slli a0, a0, 24
; RV64V-NEXT: addi a0, a0, -1281 ; RV64V-NEXT: addi a0, a0, -1281
; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64V-NEXT: vmv.v.x v8, a0 ; RV64V-NEXT: vmv.v.x v8, a0
; RV64V-NEXT: ret ; RV64V-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 4211079935, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 4211079935, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
ret <vscale x 8 x i64> %splat ret <vscale x 8 x i64> %splat
} }
define <vscale x 8 x i64> @vsplat_nxv8i64_5(i64 %a) { define <vscale x 8 x i64> @vsplat_nxv8i64_5(i64 %a) {
; RV32V-LABEL: vsplat_nxv8i64_5: ; RV32V-LABEL: vsplat_nxv8i64_5:
; RV32V: # %bb.0: ; RV32V: # %bb.0:
; RV32V-NEXT: addi sp, sp, -16 ; RV32V-NEXT: addi sp, sp, -16
; RV32V-NEXT: .cfi_def_cfa_offset 16 ; RV32V-NEXT: .cfi_def_cfa_offset 16
; RV32V-NEXT: sw a1, 12(sp) ; RV32V-NEXT: sw a1, 12(sp)
; RV32V-NEXT: sw a0, 8(sp) ; RV32V-NEXT: sw a0, 8(sp)
; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32V-NEXT: addi a0, sp, 8 ; RV32V-NEXT: addi a0, sp, 8
; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32V-NEXT: vlse64.v v8, (a0), zero ; RV32V-NEXT: vlse64.v v8, (a0), zero
; RV32V-NEXT: addi sp, sp, 16 ; RV32V-NEXT: addi sp, sp, 16
; RV32V-NEXT: ret ; RV32V-NEXT: ret
; ;
; RV64V-LABEL: vsplat_nxv8i64_5: ; RV64V-LABEL: vsplat_nxv8i64_5:
; RV64V: # %bb.0: ; RV64V: # %bb.0:
; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64V-NEXT: vmv.v.x v8, a0 ; RV64V-NEXT: vmv.v.x v8, a0
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; RV32V-LABEL: vadd_vx_nxv8i64_10: ; RV32V-LABEL: vadd_vx_nxv8i64_10:
; RV32V: # %bb.0: ; RV32V: # %bb.0:
; RV32V-NEXT: addi sp, sp, -16 ; RV32V-NEXT: addi sp, sp, -16
; RV32V-NEXT: .cfi_def_cfa_offset 16 ; RV32V-NEXT: .cfi_def_cfa_offset 16
; RV32V-NEXT: sw zero, 12(sp) ; RV32V-NEXT: sw zero, 12(sp)
; RV32V-NEXT: lui a0, 1028096 ; RV32V-NEXT: lui a0, 1028096
; RV32V-NEXT: addi a0, a0, -1281 ; RV32V-NEXT: addi a0, a0, -1281
; RV32V-NEXT: sw a0, 8(sp) ; RV32V-NEXT: sw a0, 8(sp)
; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32V-NEXT: addi a0, sp, 8 ; RV32V-NEXT: addi a0, sp, 8
; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32V-NEXT: vlse64.v v16, (a0), zero ; RV32V-NEXT: vlse64.v v16, (a0), zero
; RV32V-NEXT: vadd.vv v8, v8, v16 ; RV32V-NEXT: vadd.vv v8, v8, v16
; RV32V-NEXT: addi sp, sp, 16 ; RV32V-NEXT: addi sp, sp, 16
; RV32V-NEXT: ret ; RV32V-NEXT: ret
; ;
; RV64V-LABEL: vadd_vx_nxv8i64_10: ; RV64V-LABEL: vadd_vx_nxv8i64_10:
; RV64V: # %bb.0: ; RV64V: # %bb.0:
; RV64V-NEXT: li a0, 251 ; RV64V-NEXT: li a0, 251
Show All 13 Lines
; RV32V: # %bb.0: ; RV32V: # %bb.0:
; RV32V-NEXT: addi sp, sp, -16 ; RV32V-NEXT: addi sp, sp, -16
; RV32V-NEXT: .cfi_def_cfa_offset 16 ; RV32V-NEXT: .cfi_def_cfa_offset 16
; RV32V-NEXT: li a0, 1 ; RV32V-NEXT: li a0, 1
; RV32V-NEXT: sw a0, 12(sp) ; RV32V-NEXT: sw a0, 12(sp)
; RV32V-NEXT: lui a0, 1028096 ; RV32V-NEXT: lui a0, 1028096
; RV32V-NEXT: addi a0, a0, -1281 ; RV32V-NEXT: addi a0, a0, -1281
; RV32V-NEXT: sw a0, 8(sp) ; RV32V-NEXT: sw a0, 8(sp)
; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32V-NEXT: addi a0, sp, 8 ; RV32V-NEXT: addi a0, sp, 8
; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32V-NEXT: vlse64.v v16, (a0), zero ; RV32V-NEXT: vlse64.v v16, (a0), zero
; RV32V-NEXT: vadd.vv v8, v8, v16 ; RV32V-NEXT: vadd.vv v8, v8, v16
; RV32V-NEXT: addi sp, sp, 16 ; RV32V-NEXT: addi sp, sp, 16
; RV32V-NEXT: ret ; RV32V-NEXT: ret
; ;
; RV64V-LABEL: vadd_vx_nxv8i64_11: ; RV64V-LABEL: vadd_vx_nxv8i64_11:
; RV64V: # %bb.0: ; RV64V: # %bb.0:
; RV64V-NEXT: li a0, 507 ; RV64V-NEXT: li a0, 507
Show All 10 Lines
define <vscale x 8 x i64> @vadd_vx_nxv8i64_12(<vscale x 8 x i64> %v, i64 %a) { define <vscale x 8 x i64> @vadd_vx_nxv8i64_12(<vscale x 8 x i64> %v, i64 %a) {
; RV32V-LABEL: vadd_vx_nxv8i64_12: ; RV32V-LABEL: vadd_vx_nxv8i64_12:
; RV32V: # %bb.0: ; RV32V: # %bb.0:
; RV32V-NEXT: addi sp, sp, -16 ; RV32V-NEXT: addi sp, sp, -16
; RV32V-NEXT: .cfi_def_cfa_offset 16 ; RV32V-NEXT: .cfi_def_cfa_offset 16
; RV32V-NEXT: sw a1, 12(sp) ; RV32V-NEXT: sw a1, 12(sp)
; RV32V-NEXT: sw a0, 8(sp) ; RV32V-NEXT: sw a0, 8(sp)
; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32V-NEXT: addi a0, sp, 8 ; RV32V-NEXT: addi a0, sp, 8
; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32V-NEXT: vlse64.v v16, (a0), zero ; RV32V-NEXT: vlse64.v v16, (a0), zero
; RV32V-NEXT: vadd.vv v8, v8, v16 ; RV32V-NEXT: vadd.vv v8, v8, v16
; RV32V-NEXT: addi sp, sp, 16 ; RV32V-NEXT: addi sp, sp, 16
; RV32V-NEXT: ret ; RV32V-NEXT: ret
; ;
; RV64V-LABEL: vadd_vx_nxv8i64_12: ; RV64V-LABEL: vadd_vx_nxv8i64_12:
; RV64V: # %bb.0: ; RV64V: # %bb.0:
; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 26 Lines
define <vscale x 8 x i64> @vsplat_nxv8i64_14(i32 %a) { define <vscale x 8 x i64> @vsplat_nxv8i64_14(i32 %a) {
; RV32V-LABEL: vsplat_nxv8i64_14: ; RV32V-LABEL: vsplat_nxv8i64_14:
; RV32V: # %bb.0: ; RV32V: # %bb.0:
; RV32V-NEXT: addi sp, sp, -16 ; RV32V-NEXT: addi sp, sp, -16
; RV32V-NEXT: .cfi_def_cfa_offset 16 ; RV32V-NEXT: .cfi_def_cfa_offset 16
; RV32V-NEXT: sw zero, 12(sp) ; RV32V-NEXT: sw zero, 12(sp)
; RV32V-NEXT: sw a0, 8(sp) ; RV32V-NEXT: sw a0, 8(sp)
; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32V-NEXT: addi a0, sp, 8 ; RV32V-NEXT: addi a0, sp, 8
; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32V-NEXT: vlse64.v v8, (a0), zero ; RV32V-NEXT: vlse64.v v8, (a0), zero
; RV32V-NEXT: addi sp, sp, 16 ; RV32V-NEXT: addi sp, sp, 16
; RV32V-NEXT: ret ; RV32V-NEXT: ret
; ;
; RV64V-LABEL: vsplat_nxv8i64_14: ; RV64V-LABEL: vsplat_nxv8i64_14:
; RV64V: # %bb.0: ; RV64V: # %bb.0:
; RV64V-NEXT: slli a0, a0, 32 ; RV64V-NEXT: slli a0, a0, 32
; RV64V-NEXT: srli a0, a0, 32 ; RV64V-NEXT: srli a0, a0, 32
; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64V-NEXT: vmv.v.x v8, a0 ; RV64V-NEXT: vmv.v.x v8, a0
; RV64V-NEXT: ret ; RV64V-NEXT: ret
%b = zext i32 %a to i64 %b = zext i32 %a to i64
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
ret <vscale x 8 x i64> %splat ret <vscale x 8 x i64> %splat
} }

llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll

Show First 20 Lines • Show All 1,891 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vssub.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vssub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vssub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssub_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vssub_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vssub.vv v8, v8, v9 ; CHECK-NEXT: vssub.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssub.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vssub.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vssub.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vssub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vssub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssub.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vssub.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 11 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vssub.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vssub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vssub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssub_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vssub_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vssub.vv v8, v8, v10 ; CHECK-NEXT: vssub.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssub.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vssub.nxv2i64.i64(
<vscale x 2 x i64> undef, <vscale x 2 x i64> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vssub.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vssub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vssub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vssub.vv v8, v10, v12, v0.t ; CHECK-NEXT: vssub.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssub.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vssub.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 11 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vssub.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vssub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vssub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssub_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vssub_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vssub.vv v8, v8, v12 ; CHECK-NEXT: vssub.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssub.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vssub.nxv4i64.i64(
<vscale x 4 x i64> undef, <vscale x 4 x i64> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vssub.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vssub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vssub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vssub.vv v8, v12, v16, v0.t ; CHECK-NEXT: vssub.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssub.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vssub.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 11 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vssub.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vssub_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vssub_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssub_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vssub_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vssub.vv v8, v8, v16 ; CHECK-NEXT: vssub.vv v8, v8, v16
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssub.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vssub.nxv8i64.i64(
<vscale x 8 x i64> undef, <vscale x 8 x i64> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
Show All 12 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vssub.mask.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vssub_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vssub_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v24, (a0), zero ; CHECK-NEXT: vlse64.v v24, (a0), zero
; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssub.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vssub.mask.nxv8i64.i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll

Show First 20 Lines • Show All 683 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @ssub_nxv1i64_vx(<vscale x 1 x i64> %va, i64 %b) { define <vscale x 1 x i64> @ssub_nxv1i64_vx(<vscale x 1 x i64> %va, i64 %b) {
; RV32-LABEL: ssub_nxv1i64_vx: ; RV32-LABEL: ssub_nxv1i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vssub.vv v8, v8, v9 ; RV32-NEXT: vssub.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: ssub_nxv1i64_vx: ; RV64-LABEL: ssub_nxv1i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
Show All 32 Lines
define <vscale x 2 x i64> @ssub_nxv2i64_vx(<vscale x 2 x i64> %va, i64 %b) { define <vscale x 2 x i64> @ssub_nxv2i64_vx(<vscale x 2 x i64> %va, i64 %b) {
; RV32-LABEL: ssub_nxv2i64_vx: ; RV32-LABEL: ssub_nxv2i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vssub.vv v8, v8, v10 ; RV32-NEXT: vssub.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: ssub_nxv2i64_vx: ; RV64-LABEL: ssub_nxv2i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
Show All 32 Lines
define <vscale x 4 x i64> @ssub_nxv4i64_vx(<vscale x 4 x i64> %va, i64 %b) { define <vscale x 4 x i64> @ssub_nxv4i64_vx(<vscale x 4 x i64> %va, i64 %b) {
; RV32-LABEL: ssub_nxv4i64_vx: ; RV32-LABEL: ssub_nxv4i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vssub.vv v8, v8, v12 ; RV32-NEXT: vssub.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: ssub_nxv4i64_vx: ; RV64-LABEL: ssub_nxv4i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
Show All 32 Lines
define <vscale x 8 x i64> @ssub_nxv8i64_vx(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i64> @ssub_nxv8i64_vx(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: ssub_nxv8i64_vx: ; RV32-LABEL: ssub_nxv8i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vssub.vv v8, v8, v16 ; RV32-NEXT: vssub.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: ssub_nxv8i64_vx: ; RV64-LABEL: ssub_nxv8i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll

Show First 20 Lines • Show All 1,891 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vssubu.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vssubu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vssubu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssubu_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vssubu_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vssubu.vv v8, v8, v9 ; CHECK-NEXT: vssubu.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssubu.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vssubu.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vssubu.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vssubu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vssubu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t ; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vssubu.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vssubu.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 11 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vssubu.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vssubu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vssubu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssubu_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vssubu_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vssubu.vv v8, v8, v10 ; CHECK-NEXT: vssubu.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssubu.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vssubu.nxv2i64.i64(
<vscale x 2 x i64> undef, <vscale x 2 x i64> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vssubu.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vssubu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vssubu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vssubu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vssubu.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vssubu.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vssubu.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 11 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vssubu.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vssubu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vssubu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssubu_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vssubu_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vssubu.vv v8, v8, v12 ; CHECK-NEXT: vssubu.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssubu.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vssubu.nxv4i64.i64(
<vscale x 4 x i64> undef, <vscale x 4 x i64> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vssubu.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vssubu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vssubu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vssubu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vssubu.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vssubu.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vssubu.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 11 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vssubu.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vssubu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vssubu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vssubu_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vssubu_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vssubu.vv v8, v8, v16 ; CHECK-NEXT: vssubu.vv v8, v8, v16
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssubu.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vssubu.nxv8i64.i64(
<vscale x 8 x i64> undef, <vscale x 8 x i64> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
Show All 12 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vssubu.mask.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vssubu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vssubu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v24, (a0), zero ; CHECK-NEXT: vlse64.v v24, (a0), zero
; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssubu.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vssubu.mask.nxv8i64.i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4, i32 1) i32 %4, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll

Show First 20 Lines • Show All 683 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @usub_nxv1i64_vx(<vscale x 1 x i64> %va, i64 %b) { define <vscale x 1 x i64> @usub_nxv1i64_vx(<vscale x 1 x i64> %va, i64 %b) {
; RV32-LABEL: usub_nxv1i64_vx: ; RV32-LABEL: usub_nxv1i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vssubu.vv v8, v8, v9 ; RV32-NEXT: vssubu.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: usub_nxv1i64_vx: ; RV64-LABEL: usub_nxv1i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
Show All 32 Lines
define <vscale x 2 x i64> @usub_nxv2i64_vx(<vscale x 2 x i64> %va, i64 %b) { define <vscale x 2 x i64> @usub_nxv2i64_vx(<vscale x 2 x i64> %va, i64 %b) {
; RV32-LABEL: usub_nxv2i64_vx: ; RV32-LABEL: usub_nxv2i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vssubu.vv v8, v8, v10 ; RV32-NEXT: vssubu.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: usub_nxv2i64_vx: ; RV64-LABEL: usub_nxv2i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
Show All 32 Lines
define <vscale x 4 x i64> @usub_nxv4i64_vx(<vscale x 4 x i64> %va, i64 %b) { define <vscale x 4 x i64> @usub_nxv4i64_vx(<vscale x 4 x i64> %va, i64 %b) {
; RV32-LABEL: usub_nxv4i64_vx: ; RV32-LABEL: usub_nxv4i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vssubu.vv v8, v8, v12 ; RV32-NEXT: vssubu.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: usub_nxv4i64_vx: ; RV64-LABEL: usub_nxv4i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
Show All 32 Lines
define <vscale x 8 x i64> @usub_nxv8i64_vx(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i64> @usub_nxv8i64_vx(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: usub_nxv8i64_vx: ; RV32-LABEL: usub_nxv8i64_vx:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vssubu.vv v8, v8, v16 ; RV32-NEXT: vssubu.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: usub_nxv8i64_vx: ; RV64-LABEL: usub_nxv8i64_vx:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll

Show First 20 Lines • Show All 658 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) { define <vscale x 1 x i64> @vsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; RV32-LABEL: vsub_vx_nxv1i64: ; RV32-LABEL: vsub_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsub.vv v8, v8, v9 ; RV32-NEXT: vsub.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vsub_vx_nxv1i64: ; RV64-LABEL: vsub_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
Show All 30 Lines
define <vscale x 2 x i64> @vsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) { define <vscale x 2 x i64> @vsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; RV32-LABEL: vsub_vx_nxv2i64: ; RV32-LABEL: vsub_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsub.vv v8, v8, v10 ; RV32-NEXT: vsub.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vsub_vx_nxv2i64: ; RV64-LABEL: vsub_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
Show All 30 Lines
define <vscale x 4 x i64> @vsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) { define <vscale x 4 x i64> @vsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; RV32-LABEL: vsub_vx_nxv4i64: ; RV32-LABEL: vsub_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsub.vv v8, v8, v12 ; RV32-NEXT: vsub.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vsub_vx_nxv4i64: ; RV64-LABEL: vsub_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
Show All 30 Lines
define <vscale x 8 x i64> @vsub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i64> @vsub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: vsub_vx_nxv8i64: ; RV32-LABEL: vsub_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsub.vv v8, v8, v16 ; RV32-NEXT: vsub.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vsub_vx_nxv8i64: ; RV64-LABEL: vsub_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
Show All 21 Lines

llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll

Show First 20 Lines • Show All 993 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i64> @vsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vsub_vx_nxv1i64: ; RV32-LABEL: vsub_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vsub.vv v8, v8, v9, v0.t ; RV32-NEXT: vsub.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vsub_vx_nxv1i64: ; RV64-LABEL: vsub_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vsub.vx v8, v8, a0, v0.t ; RV64-NEXT: vsub.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i64> @llvm.vp.sub.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i64> @llvm.vp.sub.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v ret <vscale x 1 x i64> %v
} }
define <vscale x 1 x i64> @vsub_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 1 x i64> @vsub_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vsub_vx_nxv1i64_unmasked: ; RV32-LABEL: vsub_vx_nxv1i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vsub.vv v8, v8, v9 ; RV32-NEXT: vsub.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vsub_vx_nxv1i64_unmasked: ; RV64-LABEL: vsub_vx_nxv1i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <vscale x 2 x i64> @vsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i64> @vsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vsub_vx_nxv2i64: ; RV32-LABEL: vsub_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vsub.vv v8, v8, v10, v0.t ; RV32-NEXT: vsub.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vsub_vx_nxv2i64: ; RV64-LABEL: vsub_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vsub.vx v8, v8, a0, v0.t ; RV64-NEXT: vsub.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i64> @llvm.vp.sub.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl) %v = call <vscale x 2 x i64> @llvm.vp.sub.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
define <vscale x 2 x i64> @vsub_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 2 x i64> @vsub_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vsub_vx_nxv2i64_unmasked: ; RV32-LABEL: vsub_vx_nxv2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vsub.vv v8, v8, v10 ; RV32-NEXT: vsub.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vsub_vx_nxv2i64_unmasked: ; RV64-LABEL: vsub_vx_nxv2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <vscale x 4 x i64> @vsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i64> @vsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vsub_vx_nxv4i64: ; RV32-LABEL: vsub_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vsub.vv v8, v8, v12, v0.t ; RV32-NEXT: vsub.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vsub_vx_nxv4i64: ; RV64-LABEL: vsub_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vsub.vx v8, v8, a0, v0.t ; RV64-NEXT: vsub.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i64> @llvm.vp.sub.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl) %v = call <vscale x 4 x i64> @llvm.vp.sub.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v ret <vscale x 4 x i64> %v
} }
define <vscale x 4 x i64> @vsub_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 4 x i64> @vsub_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vsub_vx_nxv4i64_unmasked: ; RV32-LABEL: vsub_vx_nxv4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vsub.vv v8, v8, v12 ; RV32-NEXT: vsub.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vsub_vx_nxv4i64_unmasked: ; RV64-LABEL: vsub_vx_nxv4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 34 Lines
define <vscale x 8 x i64> @vsub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vsub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vsub_vx_nxv8i64: ; RV32-LABEL: vsub_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vsub.vv v8, v8, v16, v0.t ; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vsub_vx_nxv8i64: ; RV64-LABEL: vsub_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vsub.vx v8, v8, a0, v0.t ; RV64-NEXT: vsub.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i64> @llvm.vp.sub.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i64> @llvm.vp.sub.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i64> @vsub_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 8 x i64> @vsub_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vsub_vx_nxv8i64_unmasked: ; RV32-LABEL: vsub_vx_nxv8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vsub.vv v8, v8, v16 ; RV32-NEXT: vsub.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vsub_vx_nxv8i64_unmasked: ; RV64-LABEL: vsub_vx_nxv8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 10 Lines

llvm/test/CodeGen/RISCV/rvv/vsub.ll

Show First 20 Lines • Show All 1,853 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.i64(
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vsub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 1 x i64> @intrinsic_vsub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vsub_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vsub_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsub.vv v8, v8, v9 ; RV32-NEXT: vsub.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vsub_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vsub_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vsub.mask.nxv1i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 1 x i64> @intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i64> @intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64: ; RV32-LABEL: intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsub.vv v8, v9, v10, v0.t ; RV32-NEXT: vsub.vv v8, v9, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64: ; RV64-LABEL: intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vsub.nxv2i64.i64(
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_vsub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 2 x i64> @intrinsic_vsub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vsub_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vsub_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsub.vv v8, v8, v10 ; RV32-NEXT: vsub.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vsub_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vsub_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vsub.mask.nxv2i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 2 x i64> @intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i64> @intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64: ; RV32-LABEL: intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsub.vv v8, v10, v12, v0.t ; RV32-NEXT: vsub.vv v8, v10, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64: ; RV64-LABEL: intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vsub.nxv4i64.i64(
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_vsub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 4 x i64> @intrinsic_vsub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vsub_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vsub_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsub.vv v8, v8, v12 ; RV32-NEXT: vsub.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vsub_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vsub_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vsub.mask.nxv4i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 4 x i64> @intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i64> @intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64: ; RV32-LABEL: intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsub.vv v8, v12, v16, v0.t ; RV32-NEXT: vsub.vv v8, v12, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64: ; RV64-LABEL: intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vsub.nxv8i64.i64(
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vsub_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind { define <vscale x 8 x i64> @intrinsic_vsub_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vsub_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vsub_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsub.vv v8, v8, v16 ; RV32-NEXT: vsub.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vsub_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vsub_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
Show All 17 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vsub.mask.nxv8i64.i64(
iXLen, iXLen); iXLen, iXLen);
define <vscale x 8 x i64> @intrinsic_vsub_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i64> @intrinsic_vsub_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vsub_mask_vx_nxv8i64_nxv8i64_i64: ; RV32-LABEL: intrinsic_vsub_mask_vx_nxv8i64_nxv8i64_i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vlse64.v v24, (a0), zero
; RV32-NEXT: vsub.vv v8, v16, v24, v0.t ; RV32-NEXT: vsub.vv v8, v16, v24, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: intrinsic_vsub_mask_vx_nxv8i64_nxv8i64_i64: ; RV64-LABEL: intrinsic_vsub_mask_vx_nxv8i64_nxv8i64_i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
▲ Show 20 Lines • Show All 738 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll

Show First 20 Lines • Show All 1,891 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vxor.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vxor_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vxor_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vxor_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vxor_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: vxor.vv v8, v8, v9
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vxor.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vxor.nxv1i64.i64(
<vscale x 1 x i64> undef, <vscale x 1 x i64> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
Show All 12 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vxor.mask.nxv1i64.i64(
i32); i32);
define <vscale x 1 x i64> @intrinsic_vxor_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vxor_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t ; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vxor.mask.nxv1i64.i64( %a = call <vscale x 1 x i64> @llvm.riscv.vxor.mask.nxv1i64.i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
Show All 11 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vxor.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vxor_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vxor_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vxor_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vxor_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vxor.vv v8, v8, v10 ; CHECK-NEXT: vxor.vv v8, v8, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vxor.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vxor.nxv2i64.i64(
<vscale x 2 x i64> undef, <vscale x 2 x i64> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
Show All 12 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vxor.mask.nxv2i64.i64(
i32); i32);
define <vscale x 2 x i64> @intrinsic_vxor_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i64> @intrinsic_vxor_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vxor.vv v8, v10, v12, v0.t ; CHECK-NEXT: vxor.vv v8, v10, v12, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vxor.mask.nxv2i64.i64( %a = call <vscale x 2 x i64> @llvm.riscv.vxor.mask.nxv2i64.i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
Show All 11 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vxor.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vxor_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vxor_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vxor_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vxor_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vxor.vv v8, v8, v12 ; CHECK-NEXT: vxor.vv v8, v8, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vxor.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vxor.nxv4i64.i64(
<vscale x 4 x i64> undef, <vscale x 4 x i64> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
Show All 12 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vxor.mask.nxv4i64.i64(
i32); i32);
define <vscale x 4 x i64> @intrinsic_vxor_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i64> @intrinsic_vxor_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vxor.vv v8, v12, v16, v0.t ; CHECK-NEXT: vxor.vv v8, v12, v16, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vxor.mask.nxv4i64.i64( %a = call <vscale x 4 x i64> @llvm.riscv.vxor.mask.nxv4i64.i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
Show All 11 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vxor.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vxor_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vxor_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vxor_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vxor_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vxor.vv v8, v8, v16 ; CHECK-NEXT: vxor.vv v8, v8, v16
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vxor.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vxor.nxv8i64.i64(
<vscale x 8 x i64> undef, <vscale x 8 x i64> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
Show All 12 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vxor.mask.nxv8i64.i64(
i32); i32);
define <vscale x 8 x i64> @intrinsic_vxor_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vxor_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vlse64.v v24, (a0), zero ; CHECK-NEXT: vlse64.v v24, (a0), zero
; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t ; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vxor.mask.nxv8i64.i64( %a = call <vscale x 8 x i64> @llvm.riscv.vxor.mask.nxv8i64.i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
▲ Show 20 Lines • Show All 732 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll

Show First 20 Lines • Show All 1,075 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vxor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) { define <vscale x 1 x i64> @vxor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; RV32-LABEL: vxor_vx_nxv1i64: ; RV32-LABEL: vxor_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vxor.vv v8, v8, v9 ; RV32-NEXT: vxor.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vxor_vx_nxv1i64: ; RV64-LABEL: vxor_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
define <vscale x 2 x i64> @vxor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) { define <vscale x 2 x i64> @vxor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; RV32-LABEL: vxor_vx_nxv2i64: ; RV32-LABEL: vxor_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vxor.vv v8, v8, v10 ; RV32-NEXT: vxor.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vxor_vx_nxv2i64: ; RV64-LABEL: vxor_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
define <vscale x 4 x i64> @vxor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) { define <vscale x 4 x i64> @vxor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; RV32-LABEL: vxor_vx_nxv4i64: ; RV32-LABEL: vxor_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vxor.vv v8, v8, v12 ; RV32-NEXT: vxor.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vxor_vx_nxv4i64: ; RV64-LABEL: vxor_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
define <vscale x 8 x i64> @vxor_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { define <vscale x 8 x i64> @vxor_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV32-LABEL: vxor_vx_nxv8i64: ; RV32-LABEL: vxor_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vxor.vv v8, v8, v16 ; RV32-NEXT: vxor.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vxor_vx_nxv8i64: ; RV64-LABEL: vxor_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll

Show First 20 Lines • Show All 1,993 Lines • ▼ Show 20 Lines
define <vscale x 1 x i64> @vxor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i64> @vxor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vxor_vx_nxv1i64: ; RV32-LABEL: vxor_vx_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vxor.vv v8, v8, v9, v0.t ; RV32-NEXT: vxor.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vxor_vx_nxv1i64: ; RV64-LABEL: vxor_vx_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vxor.vx v8, v8, a0, v0.t ; RV64-NEXT: vxor.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i64> @llvm.vp.xor.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i64> @llvm.vp.xor.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i64> %v ret <vscale x 1 x i64> %v
} }
define <vscale x 1 x i64> @vxor_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 1 x i64> @vxor_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vxor_vx_nxv1i64_unmasked: ; RV32-LABEL: vxor_vx_nxv1i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: vxor.vv v8, v8, v9 ; RV32-NEXT: vxor.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vxor_vx_nxv1i64_unmasked: ; RV64-LABEL: vxor_vx_nxv1i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
define <vscale x 2 x i64> @vxor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { define <vscale x 2 x i64> @vxor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vxor_vx_nxv2i64: ; RV32-LABEL: vxor_vx_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vxor.vv v8, v8, v10, v0.t ; RV32-NEXT: vxor.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vxor_vx_nxv2i64: ; RV64-LABEL: vxor_vx_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; RV64-NEXT: vxor.vx v8, v8, a0, v0.t ; RV64-NEXT: vxor.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x i64> @llvm.vp.xor.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl) %v = call <vscale x 2 x i64> @llvm.vp.xor.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x i64> %v ret <vscale x 2 x i64> %v
} }
define <vscale x 2 x i64> @vxor_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 2 x i64> @vxor_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vxor_vx_nxv2i64_unmasked: ; RV32-LABEL: vxor_vx_nxv2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; RV32-NEXT: vxor.vv v8, v8, v10 ; RV32-NEXT: vxor.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vxor_vx_nxv2i64_unmasked: ; RV64-LABEL: vxor_vx_nxv2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
define <vscale x 4 x i64> @vxor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { define <vscale x 4 x i64> @vxor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vxor_vx_nxv4i64: ; RV32-LABEL: vxor_vx_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vxor.vv v8, v8, v12, v0.t ; RV32-NEXT: vxor.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vxor_vx_nxv4i64: ; RV64-LABEL: vxor_vx_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; RV64-NEXT: vxor.vx v8, v8, a0, v0.t ; RV64-NEXT: vxor.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x i64> @llvm.vp.xor.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl) %v = call <vscale x 4 x i64> @llvm.vp.xor.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x i64> %v ret <vscale x 4 x i64> %v
} }
define <vscale x 4 x i64> @vxor_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 4 x i64> @vxor_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vxor_vx_nxv4i64_unmasked: ; RV32-LABEL: vxor_vx_nxv4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vxor.vv v8, v8, v12 ; RV32-NEXT: vxor.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vxor_vx_nxv4i64_unmasked: ; RV64-LABEL: vxor_vx_nxv4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
define <vscale x 8 x i64> @vxor_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i64> @vxor_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vxor_vx_nxv8i64: ; RV32-LABEL: vxor_vx_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vxor.vv v8, v8, v16, v0.t ; RV32-NEXT: vxor.vv v8, v8, v16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vxor_vx_nxv8i64: ; RV64-LABEL: vxor_vx_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; RV64-NEXT: vxor.vx v8, v8, a0, v0.t ; RV64-NEXT: vxor.vx v8, v8, a0, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i64> @llvm.vp.xor.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i64> @llvm.vp.xor.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %v ret <vscale x 8 x i64> %v
} }
define <vscale x 8 x i64> @vxor_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) { define <vscale x 8 x i64> @vxor_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {
; RV32-LABEL: vxor_vx_nxv8i64_unmasked: ; RV32-LABEL: vxor_vx_nxv8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; RV32-NEXT: vxor.vv v8, v8, v16 ; RV32-NEXT: vxor.vv v8, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vxor_vx_nxv8i64_unmasked: ; RV64-LABEL: vxor_vx_nxv8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 62 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

Show First 20 Lines • Show All 593 Lines • ▼ Show 20 Lines
; RV64M-NEXT: slli a2, a4, 31 ; RV64M-NEXT: slli a2, a4, 31
; RV64M-NEXT: srli a2, a2, 62 ; RV64M-NEXT: srli a2, a2, 62
; RV64M-NEXT: subw a1, a2, a1 ; RV64M-NEXT: subw a1, a2, a1
; RV64M-NEXT: sw a1, 8(a0) ; RV64M-NEXT: sw a1, 8(a0)
; RV64M-NEXT: ret ; RV64M-NEXT: ret
; ;
; RV32MV-LABEL: test_srem_vec: ; RV32MV-LABEL: test_srem_vec:
; RV32MV: # %bb.0: ; RV32MV: # %bb.0:
; RV32MV-NEXT: addi sp, sp, -96 ; RV32MV-NEXT: addi sp, sp, -64
; RV32MV-NEXT: sw ra, 92(sp) # 4-byte Folded Spill ; RV32MV-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32MV-NEXT: sw s0, 88(sp) # 4-byte Folded Spill ; RV32MV-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; RV32MV-NEXT: sw s2, 84(sp) # 4-byte Folded Spill ; RV32MV-NEXT: sw s2, 52(sp) # 4-byte Folded Spill
; RV32MV-NEXT: sw s3, 80(sp) # 4-byte Folded Spill ; RV32MV-NEXT: sw s3, 48(sp) # 4-byte Folded Spill
; RV32MV-NEXT: sw s4, 76(sp) # 4-byte Folded Spill ; RV32MV-NEXT: sw s4, 44(sp) # 4-byte Folded Spill
; RV32MV-NEXT: sw s5, 72(sp) # 4-byte Folded Spill ; RV32MV-NEXT: sw s5, 40(sp) # 4-byte Folded Spill
; RV32MV-NEXT: sw s6, 68(sp) # 4-byte Folded Spill ; RV32MV-NEXT: sw s6, 36(sp) # 4-byte Folded Spill
; RV32MV-NEXT: addi s0, sp, 96 ; RV32MV-NEXT: addi s0, sp, 64
; RV32MV-NEXT: andi sp, sp, -32 ; RV32MV-NEXT: andi sp, sp, -32
; RV32MV-NEXT: mv s2, a0 ; RV32MV-NEXT: mv s2, a0
; RV32MV-NEXT: lw a0, 8(a0) ; RV32MV-NEXT: lw a0, 8(a0)
; RV32MV-NEXT: lw a1, 4(s2) ; RV32MV-NEXT: lw a1, 4(s2)
; RV32MV-NEXT: slli a2, a0, 31 ; RV32MV-NEXT: slli a2, a0, 31
; RV32MV-NEXT: srli a3, a1, 1 ; RV32MV-NEXT: srli a3, a1, 1
; RV32MV-NEXT: or s3, a3, a2 ; RV32MV-NEXT: or s3, a3, a2
; RV32MV-NEXT: lb a2, 12(s2) ; RV32MV-NEXT: lb a2, 12(s2)
; RV32MV-NEXT: slli a3, a0, 30 ; RV32MV-NEXT: slli a3, a0, 30
; RV32MV-NEXT: srli a3, a3, 31 ; RV32MV-NEXT: srli a3, a3, 31
; RV32MV-NEXT: neg s4, a3 ; RV32MV-NEXT: neg s4, a3
; RV32MV-NEXT: slli a3, a2, 30 ; RV32MV-NEXT: slli a3, a2, 30
; RV32MV-NEXT: srli a0, a0, 2 ; RV32MV-NEXT: srli a0, a0, 2
; RV32MV-NEXT: or s5, a0, a3 ; RV32MV-NEXT: or s5, a0, a3
; RV32MV-NEXT: slli a0, a2, 29 ; RV32MV-NEXT: slli a0, a2, 29
; RV32MV-NEXT: srli a2, a0, 31 ; RV32MV-NEXT: srli a2, a0, 31
; RV32MV-NEXT: lw a0, 0(s2) ; RV32MV-NEXT: lw a0, 0(s2)
; RV32MV-NEXT: neg s6, a2 ; RV32MV-NEXT: neg s6, a2
; RV32MV-NEXT: andi a1, a1, 1 ; RV32MV-NEXT: andi a1, a1, 1
; RV32MV-NEXT: neg a1, a1 ; RV32MV-NEXT: neg a1, a1
; RV32MV-NEXT: li a2, 6 ; RV32MV-NEXT: li a2, 6
; RV32MV-NEXT: li a3, 0 ; RV32MV-NEXT: li a3, 0
; RV32MV-NEXT: call __moddi3@plt ; RV32MV-NEXT: call __moddi3@plt
; RV32MV-NEXT: sw a1, 36(sp) ; RV32MV-NEXT: sw a1, 4(sp)
; RV32MV-NEXT: sw a0, 32(sp) ; RV32MV-NEXT: sw a0, 0(sp)
; RV32MV-NEXT: li a2, -5 ; RV32MV-NEXT: li a2, -5
; RV32MV-NEXT: li a3, -1 ; RV32MV-NEXT: li a3, -1
; RV32MV-NEXT: mv a0, s5 ; RV32MV-NEXT: mv a0, s5
; RV32MV-NEXT: mv a1, s6 ; RV32MV-NEXT: mv a1, s6
; RV32MV-NEXT: call __moddi3@plt ; RV32MV-NEXT: call __moddi3@plt
; RV32MV-NEXT: sw a1, 52(sp) ; RV32MV-NEXT: sw a1, 20(sp)
; RV32MV-NEXT: sw a0, 48(sp) ; RV32MV-NEXT: sw a0, 16(sp)
; RV32MV-NEXT: li a2, 7 ; RV32MV-NEXT: li a2, 7
; RV32MV-NEXT: mv a0, s3 ; RV32MV-NEXT: mv a0, s3
; RV32MV-NEXT: mv a1, s4 ; RV32MV-NEXT: mv a1, s4
; RV32MV-NEXT: li a3, 0 ; RV32MV-NEXT: li a3, 0
; RV32MV-NEXT: call __moddi3@plt ; RV32MV-NEXT: call __moddi3@plt
; RV32MV-NEXT: sw a1, 44(sp) ; RV32MV-NEXT: sw a1, 12(sp)
; RV32MV-NEXT: sw a0, 40(sp) ; RV32MV-NEXT: sw a0, 8(sp)
; RV32MV-NEXT: li a0, 85 ; RV32MV-NEXT: li a0, 85
; RV32MV-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV32MV-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32MV-NEXT: vmv.s.x v0, a0 ; RV32MV-NEXT: vmv.s.x v0, a0
; RV32MV-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV32MV-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32MV-NEXT: vmv.v.i v8, 1 ; RV32MV-NEXT: vmv.v.i v8, 1
; RV32MV-NEXT: addi a0, sp, 32 ; RV32MV-NEXT: mv a0, sp
; RV32MV-NEXT: vle32.v v10, (a0) ; RV32MV-NEXT: vle32.v v10, (a0)
; RV32MV-NEXT: lui a0, %hi(.LCPI3_0) ; RV32MV-NEXT: lui a0, %hi(.LCPI3_0)
; RV32MV-NEXT: addi a0, a0, %lo(.LCPI3_0) ; RV32MV-NEXT: addi a0, a0, %lo(.LCPI3_0)
; RV32MV-NEXT: vle32.v v12, (a0) ; RV32MV-NEXT: vle32.v v12, (a0)
; RV32MV-NEXT: vmerge.vim v8, v8, -1, v0 ; RV32MV-NEXT: vmerge.vim v8, v8, -1, v0
; RV32MV-NEXT: vand.vv v8, v10, v8 ; RV32MV-NEXT: vand.vv v8, v10, v8
; RV32MV-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32MV-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32MV-NEXT: vmsne.vv v0, v8, v12 ; RV32MV-NEXT: vmsne.vv v0, v8, v12
Show All 21 Lines
; RV32MV-NEXT: vslidedown.vi v8, v8, 3 ; RV32MV-NEXT: vslidedown.vi v8, v8, 3
; RV32MV-NEXT: vmv.x.s a2, v8 ; RV32MV-NEXT: vmv.x.s a2, v8
; RV32MV-NEXT: andi a2, a2, 1 ; RV32MV-NEXT: andi a2, a2, 1
; RV32MV-NEXT: slli a2, a2, 1 ; RV32MV-NEXT: slli a2, a2, 1
; RV32MV-NEXT: or a1, a1, a2 ; RV32MV-NEXT: or a1, a1, a2
; RV32MV-NEXT: slli a0, a0, 2 ; RV32MV-NEXT: slli a0, a0, 2
; RV32MV-NEXT: or a0, a1, a0 ; RV32MV-NEXT: or a0, a1, a0
; RV32MV-NEXT: sw a0, 8(s2) ; RV32MV-NEXT: sw a0, 8(s2)
; RV32MV-NEXT: addi sp, s0, -96 ; RV32MV-NEXT: addi sp, s0, -64
; RV32MV-NEXT: lw ra, 92(sp) # 4-byte Folded Reload ; RV32MV-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32MV-NEXT: lw s0, 88(sp) # 4-byte Folded Reload ; RV32MV-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32MV-NEXT: lw s2, 84(sp) # 4-byte Folded Reload ; RV32MV-NEXT: lw s2, 52(sp) # 4-byte Folded Reload
; RV32MV-NEXT: lw s3, 80(sp) # 4-byte Folded Reload ; RV32MV-NEXT: lw s3, 48(sp) # 4-byte Folded Reload
; RV32MV-NEXT: lw s4, 76(sp) # 4-byte Folded Reload ; RV32MV-NEXT: lw s4, 44(sp) # 4-byte Folded Reload
; RV32MV-NEXT: lw s5, 72(sp) # 4-byte Folded Reload ; RV32MV-NEXT: lw s5, 40(sp) # 4-byte Folded Reload
; RV32MV-NEXT: lw s6, 68(sp) # 4-byte Folded Reload ; RV32MV-NEXT: lw s6, 36(sp) # 4-byte Folded Reload
; RV32MV-NEXT: addi sp, sp, 96 ; RV32MV-NEXT: addi sp, sp, 64
; RV32MV-NEXT: ret ; RV32MV-NEXT: ret
; ;
; RV64MV-LABEL: test_srem_vec: ; RV64MV-LABEL: test_srem_vec:
; RV64MV: # %bb.0: ; RV64MV: # %bb.0:
; RV64MV-NEXT: addi sp, sp, -96 ; RV64MV-NEXT: addi sp, sp, -64
; RV64MV-NEXT: sd ra, 88(sp) # 8-byte Folded Spill ; RV64MV-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
; RV64MV-NEXT: sd s0, 80(sp) # 8-byte Folded Spill ; RV64MV-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
; RV64MV-NEXT: addi s0, sp, 96 ; RV64MV-NEXT: addi s0, sp, 64
; RV64MV-NEXT: andi sp, sp, -32 ; RV64MV-NEXT: andi sp, sp, -32
; RV64MV-NEXT: lwu a1, 8(a0) ; RV64MV-NEXT: lwu a1, 8(a0)
; RV64MV-NEXT: ld a2, 0(a0) ; RV64MV-NEXT: ld a2, 0(a0)
; RV64MV-NEXT: slli a3, a1, 31 ; RV64MV-NEXT: slli a3, a1, 31
; RV64MV-NEXT: srli a4, a2, 33 ; RV64MV-NEXT: srli a4, a2, 33
; RV64MV-NEXT: lb a5, 12(a0) ; RV64MV-NEXT: lb a5, 12(a0)
; RV64MV-NEXT: or a3, a4, a3 ; RV64MV-NEXT: or a3, a4, a3
; RV64MV-NEXT: slli a3, a3, 31 ; RV64MV-NEXT: slli a3, a3, 31
Show All 9 Lines
; RV64MV-NEXT: srli a5, a4, 63 ; RV64MV-NEXT: srli a5, a4, 63
; RV64MV-NEXT: add a4, a4, a5 ; RV64MV-NEXT: add a4, a4, a5
; RV64MV-NEXT: li a5, 6 ; RV64MV-NEXT: li a5, 6
; RV64MV-NEXT: mul a4, a4, a5 ; RV64MV-NEXT: mul a4, a4, a5
; RV64MV-NEXT: lui a5, %hi(.LCPI3_1) ; RV64MV-NEXT: lui a5, %hi(.LCPI3_1)
; RV64MV-NEXT: ld a5, %lo(.LCPI3_1)(a5) ; RV64MV-NEXT: ld a5, %lo(.LCPI3_1)(a5)
; RV64MV-NEXT: srai a1, a1, 31 ; RV64MV-NEXT: srai a1, a1, 31
; RV64MV-NEXT: sub a2, a2, a4 ; RV64MV-NEXT: sub a2, a2, a4
; RV64MV-NEXT: sd a2, 32(sp) ; RV64MV-NEXT: sd a2, 0(sp)
; RV64MV-NEXT: mulh a2, a1, a5 ; RV64MV-NEXT: mulh a2, a1, a5
; RV64MV-NEXT: srli a4, a2, 63 ; RV64MV-NEXT: srli a4, a2, 63
; RV64MV-NEXT: srai a2, a2, 1 ; RV64MV-NEXT: srai a2, a2, 1
; RV64MV-NEXT: add a2, a2, a4 ; RV64MV-NEXT: add a2, a2, a4
; RV64MV-NEXT: slli a4, a2, 2 ; RV64MV-NEXT: slli a4, a2, 2
; RV64MV-NEXT: lui a5, %hi(.LCPI3_2) ; RV64MV-NEXT: lui a5, %hi(.LCPI3_2)
; RV64MV-NEXT: ld a5, %lo(.LCPI3_2)(a5) ; RV64MV-NEXT: ld a5, %lo(.LCPI3_2)(a5)
; RV64MV-NEXT: add a2, a4, a2 ; RV64MV-NEXT: add a2, a4, a2
; RV64MV-NEXT: add a1, a1, a2 ; RV64MV-NEXT: add a1, a1, a2
; RV64MV-NEXT: sd a1, 48(sp) ; RV64MV-NEXT: sd a1, 16(sp)
; RV64MV-NEXT: mulh a1, a3, a5 ; RV64MV-NEXT: mulh a1, a3, a5
; RV64MV-NEXT: srli a2, a1, 63 ; RV64MV-NEXT: srli a2, a1, 63
; RV64MV-NEXT: srai a1, a1, 1 ; RV64MV-NEXT: srai a1, a1, 1
; RV64MV-NEXT: add a1, a1, a2 ; RV64MV-NEXT: add a1, a1, a2
; RV64MV-NEXT: slli a2, a1, 3 ; RV64MV-NEXT: slli a2, a1, 3
; RV64MV-NEXT: sub a1, a1, a2 ; RV64MV-NEXT: sub a1, a1, a2
; RV64MV-NEXT: add a1, a3, a1 ; RV64MV-NEXT: add a1, a3, a1
; RV64MV-NEXT: sd a1, 40(sp) ; RV64MV-NEXT: sd a1, 8(sp)
; RV64MV-NEXT: mv a1, sp
; RV64MV-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64MV-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64MV-NEXT: addi a1, sp, 32
; RV64MV-NEXT: vle64.v v8, (a1) ; RV64MV-NEXT: vle64.v v8, (a1)
; RV64MV-NEXT: lui a1, %hi(.LCPI3_3) ; RV64MV-NEXT: lui a1, %hi(.LCPI3_3)
; RV64MV-NEXT: addi a1, a1, %lo(.LCPI3_3) ; RV64MV-NEXT: addi a1, a1, %lo(.LCPI3_3)
; RV64MV-NEXT: vle64.v v10, (a1) ; RV64MV-NEXT: vle64.v v10, (a1)
; RV64MV-NEXT: li a1, -1 ; RV64MV-NEXT: li a1, -1
; RV64MV-NEXT: srli a1, a1, 31 ; RV64MV-NEXT: srli a1, a1, 31
; RV64MV-NEXT: vand.vx v8, v8, a1 ; RV64MV-NEXT: vand.vx v8, v8, a1
; RV64MV-NEXT: vmsne.vv v0, v8, v10 ; RV64MV-NEXT: vmsne.vv v0, v8, v10
Show All 12 Lines
; RV64MV-NEXT: slli a4, a3, 33 ; RV64MV-NEXT: slli a4, a3, 33
; RV64MV-NEXT: or a1, a1, a4 ; RV64MV-NEXT: or a1, a1, a4
; RV64MV-NEXT: sd a1, 0(a0) ; RV64MV-NEXT: sd a1, 0(a0)
; RV64MV-NEXT: slli a1, a2, 2 ; RV64MV-NEXT: slli a1, a2, 2
; RV64MV-NEXT: slli a2, a3, 31 ; RV64MV-NEXT: slli a2, a3, 31
; RV64MV-NEXT: srli a2, a2, 62 ; RV64MV-NEXT: srli a2, a2, 62
; RV64MV-NEXT: or a1, a2, a1 ; RV64MV-NEXT: or a1, a2, a1
; RV64MV-NEXT: sw a1, 8(a0) ; RV64MV-NEXT: sw a1, 8(a0)
; RV64MV-NEXT: addi sp, s0, -96 ; RV64MV-NEXT: addi sp, s0, -64
; RV64MV-NEXT: ld ra, 88(sp) # 8-byte Folded Reload ; RV64MV-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; RV64MV-NEXT: ld s0, 80(sp) # 8-byte Folded Reload ; RV64MV-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; RV64MV-NEXT: addi sp, sp, 96 ; RV64MV-NEXT: addi sp, sp, 64
; RV64MV-NEXT: ret ; RV64MV-NEXT: ret
%ld = load <3 x i33>, <3 x i33>* %X %ld = load <3 x i33>, <3 x i33>* %X
%srem = srem <3 x i33> %ld, <i33 6, i33 7, i33 -5> %srem = srem <3 x i33> %ld, <i33 6, i33 7, i33 -5>
%cmp = icmp ne <3 x i33> %srem, <i33 0, i33 1, i33 2> %cmp = icmp ne <3 x i33> %srem, <i33 0, i33 1, i33 2>
%ext = sext <3 x i1> %cmp to <3 x i33> %ext = sext <3 x i1> %cmp to <3 x i33>
store <3 x i33> %ext, <3 x i33>* %X store <3 x i33> %ext, <3 x i33>* %X
ret void ret void
} }

llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

Show First 20 Lines • Show All 538 Lines • ▼ Show 20 Lines
; RV32MV-NEXT: srli a2, a2, 21 ; RV32MV-NEXT: srli a2, a2, 21
; RV32MV-NEXT: sh a2, 10(sp) ; RV32MV-NEXT: sh a2, 10(sp)
; RV32MV-NEXT: lb a2, 4(a0) ; RV32MV-NEXT: lb a2, 4(a0)
; RV32MV-NEXT: slli a2, a2, 10 ; RV32MV-NEXT: slli a2, a2, 10
; RV32MV-NEXT: srli a1, a1, 22 ; RV32MV-NEXT: srli a1, a1, 22
; RV32MV-NEXT: or a1, a1, a2 ; RV32MV-NEXT: or a1, a1, a2
; RV32MV-NEXT: andi a1, a1, 2047 ; RV32MV-NEXT: andi a1, a1, 2047
; RV32MV-NEXT: sh a1, 12(sp) ; RV32MV-NEXT: sh a1, 12(sp)
; RV32MV-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; RV32MV-NEXT: addi a1, sp, 8 ; RV32MV-NEXT: addi a1, sp, 8
; RV32MV-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; RV32MV-NEXT: vle16.v v8, (a1) ; RV32MV-NEXT: vle16.v v8, (a1)
; RV32MV-NEXT: vmv.v.i v9, 10 ; RV32MV-NEXT: vmv.v.i v9, 10
; RV32MV-NEXT: li a1, 9 ; RV32MV-NEXT: li a1, 9
; RV32MV-NEXT: vsetvli zero, zero, e16, mf2, tu, mu ; RV32MV-NEXT: vsetvli zero, zero, e16, mf2, tu, mu
; RV32MV-NEXT: vmv.s.x v9, a1 ; RV32MV-NEXT: vmv.s.x v9, a1
; RV32MV-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV32MV-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV32MV-NEXT: lui a1, %hi(.LCPI4_0) ; RV32MV-NEXT: lui a1, %hi(.LCPI4_0)
; RV32MV-NEXT: addi a1, a1, %lo(.LCPI4_0) ; RV32MV-NEXT: addi a1, a1, %lo(.LCPI4_0)
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; RV64MV-NEXT: or a1, a2, a1 ; RV64MV-NEXT: or a1, a2, a1
; RV64MV-NEXT: srli a2, a1, 22 ; RV64MV-NEXT: srli a2, a1, 22
; RV64MV-NEXT: sh a2, 12(sp) ; RV64MV-NEXT: sh a2, 12(sp)
; RV64MV-NEXT: andi a2, a1, 2047 ; RV64MV-NEXT: andi a2, a1, 2047
; RV64MV-NEXT: sh a2, 8(sp) ; RV64MV-NEXT: sh a2, 8(sp)
; RV64MV-NEXT: slli a1, a1, 42 ; RV64MV-NEXT: slli a1, a1, 42
; RV64MV-NEXT: srli a1, a1, 53 ; RV64MV-NEXT: srli a1, a1, 53
; RV64MV-NEXT: sh a1, 10(sp) ; RV64MV-NEXT: sh a1, 10(sp)
; RV64MV-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; RV64MV-NEXT: addi a1, sp, 8 ; RV64MV-NEXT: addi a1, sp, 8
; RV64MV-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; RV64MV-NEXT: vle16.v v8, (a1) ; RV64MV-NEXT: vle16.v v8, (a1)
; RV64MV-NEXT: vmv.v.i v9, 10 ; RV64MV-NEXT: vmv.v.i v9, 10
; RV64MV-NEXT: li a1, 9 ; RV64MV-NEXT: li a1, 9
; RV64MV-NEXT: vsetvli zero, zero, e16, mf2, tu, mu ; RV64MV-NEXT: vsetvli zero, zero, e16, mf2, tu, mu
; RV64MV-NEXT: vmv.s.x v9, a1 ; RV64MV-NEXT: vmv.s.x v9, a1
; RV64MV-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV64MV-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; RV64MV-NEXT: lui a1, %hi(.LCPI4_0) ; RV64MV-NEXT: lui a1, %hi(.LCPI4_0)
; RV64MV-NEXT: addi a1, a1, %lo(.LCPI4_0) ; RV64MV-NEXT: addi a1, a1, %lo(.LCPI4_0)
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines