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[AArch64][SME] Add SME addha/va intrinsics
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Authored by david-arm on Jun 15 2022, 7:43 AM.

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Summary

This patch adds new the following SME intrinsics:

@llvm.aarch64.sme.addva
@llvm.aarch64.sme.addha

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Event Timeline

david-arm created this revision.Jun 15 2022, 7:43 AM
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david-arm requested review of this revision.Jun 15 2022, 7:43 AM
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Matt added a subscriber: Matt.Jun 16 2022, 4:44 PM
llvm/lib/Target/AArch64/SMEInstrFormats.td
240–241

Need to enclose these instruction definitions in let Predicates = [HasSMEI64] {..}?

david-arm updated this revision to Diff 441669.Jul 1 2022, 5:35 AM
  • Added HasSMEI64 guards around 64-bit pseudos/patterns.
david-arm marked an inline comment as done.Jul 1 2022, 5:37 AM
david-arm added inline comments.
llvm/lib/Target/AArch64/SMEInstrFormats.td
240–241

Thanks @sagarkulkarni19, that's a great spot! The real instruction definitions are guarded correctly, but the patterns and pseudos are not. I think that the mopa/mops may have a similar problem, so I'm going to look into those too.

LGTM with nit addressed.

llvm/lib/Target/AArch64/SMEInstrFormats.td
255

nit: can you merge the definitions of the pseudos and the patterns together under a single HasSMEI64 condition?

sdesmalen accepted this revision.Jul 4 2022, 9:07 AM
This revision is now accepted and ready to land.Jul 4 2022, 9:07 AM
This revision was landed with ongoing or failed builds.Jul 5 2022, 1:48 AM
This revision was automatically updated to reflect the committed changes.
david-arm marked an inline comment as done.