[AArch64][SVE] Don't crash on pre-legalized types in extload combine.

[ab]

Summary

This was assuming the vector types were MVTs, but they don't have to be.

Note that the concrete output of the test isn't very useful, since it's dominated by nonsensical calling convention lowering for the weird types (ideas for a less gross test welcome!)

An alternative to consider is whether it makes sense to try this that early, but we get to this from the generic ext-load combines, so I guess it's fine on that side

[paulwalker-arm]

Thanks for the fix. I don't mind the test since as you say, the exact output is not relevant.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

5313

I kind of wondered if this should only require the vector element type to be simple but looking at MachineValueType.h the important vector types upto 2048bit are simple so I doubt it matters.

[paulwalker-arm]

@ab What's your plans for submitting this fix. I only ask because others have hit the same issue, as shown by https://github.com/llvm/llvm-project/issues/55866.

[ab]

Yep, committed c68b469e0788, thanks!

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

 }
 
 bool AArch64TargetLowering::mergeStoresAfterLegalization(EVT VT) const {
   return !Subtarget->useSVEForFixedLengthVectors();
 }
 
 bool AArch64TargetLowering::useSVEForFixedLengthVectorVT(
     EVT VT, bool OverrideNEON) const {
-  if (!VT.isFixedLengthVector())
+  if (!VT.isFixedLengthVector() || !VT.isSimple())
     return false;
 
   // Don't use SVE for vectors we cannot scalarize if required.
   switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
   // Fixed length predicates should be promoted to i8.
   // NOTE: This is consistent with how NEON (and thus 64/128bit vectors) work.
   case MVT::i1:
   default:

llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll

define <4 x i32> @load_zext_v4i16i32(<4 x i16>* %ap) #0 {
   ; CHECK: ldr d[[D0:[0-9]+]], [x0]
   ; CHECK-NEXT: ushll v[[D0]].4s, v[[D0]].4h, #0
   ; CHECK-NEXT: ret
   %a = load <4 x i16>, <4 x i16>* %ap
   %val = zext <4 x i16> %a to <4 x i32>
   ret <4 x i32> %val
 }
 
+; Don't try to use SVE for irregular types.
+define <2 x i256> @load_zext_v2i64i256(<2 x i64>* %ap) #0 {
+  ; CHECK-LABEL: load_zext_v2i64i256
+  ; CHECK-NOT: ptrue
+  %a = load <2 x i64>, <2 x i64>* %ap
+  %val = zext <2 x i64> %a to <2 x i256>
+  ret <2 x i256> %val
+}
+
 define <8 x i32> @load_zext_v8i16i32(<8 x i16>* %ap) #0 {
   ; CHECK-LABEL: load_zext_v8i16i32
   ; CHECK: ptrue [[P0:p[0-9]+]].s, vl8
   ; CHECK-NEXT: ld1h { [[Z0:z[0-9]+]].s }, [[P0]]/z, [x0]
   ; CHECK-NEXT: st1w { [[Z0]].s }, [[P0]], [x8]
   ; CHECK-NEXT: ret
   %a = load <8 x i16>, <8 x i16>* %ap
   %val = zext <8 x i16> %a to <8 x i32>