[AMDGPU] gfx11 LDSDIR instructions MC support

[Joe_Nash]

Summary

Contributors:
Carl Ritson <[e-mail]>

Patch 8/N for upstreaming of AMDGPU gfx11 architecture.

Depends on D125498

[rampitec]

LGTM with formatting fixed.

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

599

Formatting, code is misaligned.

[arsenm]

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

8858–8868

Missing parse error tests

[Joe_Nash]

deleted dead parser function and fixed formatting

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

8858–8868

Apparently this code is dead. Added error tests for the default parser and removed this.

[critson]

LGTM, thanks!

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

enum ImmTy {
     ImmTyNegHi,
     ImmTySwizzle,
     ImmTyGprIdxMode,
     ImmTyHigh,
     ImmTyBLGP,
     ImmTyCBSZ,
     ImmTyABID,
     ImmTyEndpgm,
+    ImmTyWaitVDST,
   };
 
   enum ImmKindTy {
     ImmKindTyNone,
     ImmKindTyLiteral,
     ImmKindTyConst,
   };
 
public:
   bool isDPPCtrl() const;
   bool isBLGP() const;
   bool isCBSZ() const;
   bool isABID() const;
   bool isGPRIdxMode() const;
   bool isS16Imm() const;
   bool isU16Imm() const;
   bool isEndpgm() const;
+  bool isWaitVDST() const;
 
   StringRef getExpressionAsToken() const {
     assert(isExpr());
     const MCSymbolRefExpr *S = cast<MCSymbolRefExpr>(Expr);
     return S->getSymbol().getName();
   }
 
   StringRef getToken() const {
static void printImmTy(raw_ostream& OS, ImmTy Type) {
     case ImmTyNegHi: OS << "NegHi"; break;
     case ImmTySwizzle: OS << "Swizzle"; break;
     case ImmTyGprIdxMode: OS << "GprIdxMode"; break;
     case ImmTyHigh: OS << "High"; break;
     case ImmTyBLGP: OS << "BLGP"; break;
     case ImmTyCBSZ: OS << "CBSZ"; break;
     case ImmTyABID: OS << "ABID"; break;
     case ImmTyEndpgm: OS << "Endpgm"; break;
+    case ImmTyWaitVDST: OS << "WaitVDST"; break;
     }
   }
 
   void print(raw_ostream &OS) const override {
     switch (Kind) {
     case Register:
       OS << "<register " << getReg() << " mods: " << Reg.Mods << '>';
       break;
void cvtSDWA(MCInst &Inst, const OperandVector &Operands,
                bool SkipSrcVcc = false);
 
   AMDGPUOperand::Ptr defaultBLGP() const;
   AMDGPUOperand::Ptr defaultCBSZ() const;
   AMDGPUOperand::Ptr defaultABID() const;
 
   OperandMatchResultTy parseEndpgmOp(OperandVector &Operands);
   AMDGPUOperand::Ptr defaultEndpgmImmOperands() const;
+
+  OperandMatchResultTy parseWaitVDST(OperandVector &Operands);
+  AMDGPUOperand::Ptr defaultWaitVDST() const;
 };
 
 struct OptionalOperand {
   const char *Name;
   AMDGPUOperand::ImmTy Type;
   bool IsBit;
   bool (*ConvertResult)(int64_t&);
 };
Optional<StringRef> AMDGPUAsmParser::validateLdsDirect(const MCInst &Inst) {
 
   for (auto SrcName : {OpName::src0, OpName::src1, OpName::src2}) {
     auto SrcIdx = getNamedOperandIdx(Opcode, SrcName);
     if (SrcIdx == -1)
       break;
     const auto &Src = Inst.getOperand(SrcIdx);
     if (Src.isReg() && Src.getReg() == LDS_DIRECT) {
 
-      if (isGFX90A())
+      if (isGFX90A() || isGFX11Plus())
         return StringRef("lds_direct is not supported on this GPU");
 
       if (IsRevOpcode(Opcode) || (Desc.TSFlags & SIInstrFlags::SDWA))
         return StringRef("lds_direct cannot be used with this instruction");
 
       if (SrcName != OpName::src0)
         return StringRef("lds_direct may be used as src0 only");
     }
static const OptionalOperand AMDGPUOptionalOperandTable[] = {
   {"compr", AMDGPUOperand::ImmTyExpCompr, true, nullptr },
   {"vm", AMDGPUOperand::ImmTyExpVM, true, nullptr},
   {"op_sel", AMDGPUOperand::ImmTyOpSel, false, nullptr},
   {"op_sel_hi", AMDGPUOperand::ImmTyOpSelHi, false, nullptr},
   {"neg_lo", AMDGPUOperand::ImmTyNegLo, false, nullptr},
   {"neg_hi", AMDGPUOperand::ImmTyNegHi, false, nullptr},
   {"blgp", AMDGPUOperand::ImmTyBLGP, false, nullptr},
   {"cbsz", AMDGPUOperand::ImmTyCBSZ, false, nullptr},
-  {"abid", AMDGPUOperand::ImmTyABID, false, nullptr}
+  {"abid", AMDGPUOperand::ImmTyABID, false, nullptr},
+  {"wait_vdst", AMDGPUOperand::ImmTyWaitVDST, false, nullptr}
 };
 
 void AMDGPUAsmParser::onBeginOfFile() {
   if (!getParser().getStreamer().getTargetStreamer() ||
       getSTI().getTargetTriple().getArch() == Triple::r600)
     return;
 
   if (!getTargetStreamer().getTargetID())
OperandMatchResultTy AMDGPUAsmParser::parseEndpgmOp(OperandVector &Operands) {
   }
 
   Operands.push_back(
       AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTyEndpgm));
   return MatchOperand_Success;
 }
 
 bool AMDGPUOperand::isEndpgm() const { return isImmTy(ImmTyEndpgm); }
+
+//===----------------------------------------------------------------------===//
+// LDSDIR
+//===----------------------------------------------------------------------===//
+
+AMDGPUOperand::Ptr AMDGPUAsmParser::defaultWaitVDST() const {
+  return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyWaitVDST);
+}
+
+bool AMDGPUOperand::isWaitVDST() const {
+  return isImmTy(ImmTyWaitVDST) && isUInt<4>(getImm());
+}

llvm/lib/Target/AMDGPU/LDSDIRInstructions.td

+//===-- LDSDIRInstructions.td - LDS Direct Instruction Definitions --------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// LDSDIR encoding
+//===----------------------------------------------------------------------===//
+
+class LDSDIRe<bits<2> op, bit is_direct> : Enc32 {
+  // encoding fields
+  bits<2> attrchan;
+  bits<6> attr;
+  bits<4> waitvdst;
+  bits<8> vdst;
+
+  // encoding
+  let Inst{31-24} = 0xce; // encoding
+  let Inst{23-22} = 0x0; // reserved
+  let Inst{21-20} = op;
+  let Inst{19-16} = waitvdst;
+  let Inst{15-10} = !if(is_direct, ?, attr);
+  let Inst{9-8} = !if(is_direct, ?, attrchan);
+  let Inst{7-0} = vdst;
+}
+
+//===----------------------------------------------------------------------===//
+// LDSDIR Classes
+//===----------------------------------------------------------------------===//
+
+class LDSDIR_getIns<bit direct> {
+  dag ret = !if(direct,
+    (ins wait_vdst:$waitvdst),
+    (ins Attr:$attr, AttrChan:$attrchan, wait_vdst:$waitvdst)
+  );
+}
+
+class LDSDIR_Common<string opName, string asm = "", bit direct> : InstSI<
+    (outs VGPR_32:$vdst),
+    LDSDIR_getIns<direct>.ret,
+    asm> {
+  let LDSDIR = 1;
+  let EXP_CNT = 1;
+
+  let hasSideEffects = 0;
+  let mayLoad = 1;
+  let mayStore = 0;
+
+  string Mnemonic = opName;
+  let UseNamedOperandTable = 1;
+
+  let Uses = [M0, EXEC];
+  let DisableWQM = 0;
+  let SchedRW = [WriteLDS];
+
+  bit is_direct;
+  let is_direct = direct;
+}
+
+class LDSDIR_Pseudo<string opName, bit direct> :
+  LDSDIR_Common<opName, "", direct>,
+  SIMCInstr<opName, SIEncodingFamily.NONE> {
+  let isPseudo = 1;
+  let isCodeGenOnly = 1;
+}
+
+class LDSDIR_getAsm<bit direct> {
+  string ret = !if(direct,
+    " $vdst$waitvdst",
+    " $vdst, $attr$attrchan$waitvdst"
+  );
+}
+
+class LDSDIR_Real<bits<2> op, LDSDIR_Pseudo lds, int subtarget> :
+  LDSDIR_Common<lds.Mnemonic,
+                lds.Mnemonic # LDSDIR_getAsm<lds.is_direct>.ret,
+                lds.is_direct>,
+  SIMCInstr <lds.Mnemonic, subtarget>,
+  LDSDIRe<op, lds.is_direct> {
+  let isPseudo = 0;
+  let isCodeGenOnly = 0;
+}
+
+//===----------------------------------------------------------------------===//
+// LDS Direct Instructions
+//===----------------------------------------------------------------------===//
+
+def LDS_DIRECT_LOAD : LDSDIR_Pseudo<"lds_direct_load", 1>;
+def LDS_PARAM_LOAD : LDSDIR_Pseudo<"lds_param_load", 0>;
+
+//===----------------------------------------------------------------------===//
+// GFX11+
+//===----------------------------------------------------------------------===//
+
+multiclass LDSDIR_Real_gfx11<bits<2> op, LDSDIR_Pseudo lds = !cast<LDSDIR_Pseudo>(NAME)> {
+  def _gfx11 : LDSDIR_Real<op, lds, SIEncodingFamily.GFX11> {
+    let AssemblerPredicate = isGFX11Plus;
+    let DecoderNamespace = "GFX11";
+  }
+}
+
+defm LDS_PARAM_LOAD : LDSDIR_Real_gfx11<0x0>;
+defm LDS_DIRECT_LOAD : LDSDIR_Real_gfx11<0x1>;

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h

private:
   void printBLGP(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                  raw_ostream &O);
   void printCBSZ(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                  raw_ostream &O);
   void printABID(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                  raw_ostream &O);
   void printDefaultVccOperand(unsigned OpNo, const MCSubtargetInfo &STI,
                               raw_ostream &O);
+  void printWaitVDST(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+                    raw_ostream &O);
 
   void printExpSrcN(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                     raw_ostream &O, unsigned N);
   void printExpSrc0(const MCInst *MI, unsigned OpNo,
                     const MCSubtargetInfo &STI, raw_ostream &O);
   void printExpSrc1(const MCInst *MI, unsigned OpNo,
                     const MCSubtargetInfo &STI, raw_ostream &O);
   void printExpSrc2(const MCInst *MI, unsigned OpNo,

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

void AMDGPUInstPrinter::printDefaultVccOperand(unsigned OpNo,
   if (OpNo > 0)
     O << ", ";
   printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
                   AMDGPU::VCC : AMDGPU::VCC_LO, O, MRI);
   if (OpNo == 0)
     O << ", ";
 }
 
+void AMDGPUInstPrinter::printWaitVDST(const MCInst *MI, unsigned OpNo,
+                                      const MCSubtargetInfo &STI,
+                                      raw_ostream &O) {
+  uint8_t Imm = MI->getOperand(OpNo).getImm();
+  if (Imm != 0) {
+    O << " wait_vdst:";
+    printU4ImmDecOperand(MI, OpNo, O);
+  }
+}
+
 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
                                      const MCSubtargetInfo &STI,
                                      raw_ostream &O) {
   // Print default vcc/vcc_lo operand of VOPC.
   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
   if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) &&
       (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
        Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))

llvm/lib/Target/AMDGPU/SIDefines.h

enum : uint64_t {
   EXP = 1 << 21,
   FLAT = 1 << 22,
   DS = 1 << 23,
 
   // Pseudo instruction formats.
   VGPRSpill = 1 << 24,
   SGPRSpill = 1 << 25,
 
+  // LDSDIR instruction format.
+  LDSDIR = 1 << 26,
+
   // High bits - other information.
   VM_CNT = UINT64_C(1) << 32,
   EXP_CNT = UINT64_C(1) << 33,
   LGKM_CNT = UINT64_C(1) << 34,
 
   WQM = UINT64_C(1) << 35,
   DisableWQM = UINT64_C(1) << 36,
   Gather4 = UINT64_C(1) << 37,

llvm/lib/Target/AMDGPU/SIInstrFormats.td

class InstSI <dag outs, dag ins, string asm = "",
   field bit EXP = 0;
   field bit FLAT = 0;
   field bit DS = 0;
 
   // Pseudo instruction formats.
   field bit VGPRSpill = 0;
   field bit SGPRSpill = 0;
 
+  // LDSDIR instruction format.
+  field bit LDSDIR = 0;
+
   // High bits - other information.
   field bit VM_CNT = 0;
   field bit EXP_CNT = 0;
   field bit LGKM_CNT = 0;
 
   // Whether WQM _must_ be enabled for this instruction.
   field bit WQM = 0;
 
class InstSI <dag outs, dag ins, string asm = "",
   let TSFlags{20} = MIMG;
   let TSFlags{21} = EXP;
   let TSFlags{22} = FLAT;
   let TSFlags{23} = DS;
 
   let TSFlags{24} = VGPRSpill;
   let TSFlags{25} = SGPRSpill;
 
+  let TSFlags{26} = LDSDIR;
+
   let TSFlags{32} = VM_CNT;
   let TSFlags{33} = EXP_CNT;
   let TSFlags{34} = LGKM_CNT;
 
   let TSFlags{35} = WQM;
   let TSFlags{36} = DisableWQM;
   let TSFlags{37} = Gather4;
 

llvm/lib/Target/AMDGPU/SIInstrInfo.h

public:
   static bool isDOT(const MachineInstr &MI) {
     return MI.getDesc().TSFlags & SIInstrFlags::IsDOT;
   }
 
   bool isDOT(uint16_t Opcode) const {
     return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
   }
 
+  static bool isLDSDIR(const MachineInstr &MI) {
+    return MI.getDesc().TSFlags & SIInstrFlags::LDSDIR;
+  }
+
+  bool isLDSDIR(uint16_t Opcode) const {
+    return get(Opcode).TSFlags & SIInstrFlags::LDSDIR;
+  }
+
   static bool isScalarUnit(const MachineInstr &MI) {
     return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
   }
 
   static bool usesVM_CNT(const MachineInstr &MI) {
     return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
   }
 

llvm/lib/Target/AMDGPU/SIInstrInfo.td

 def abid : NamedOperandU32<"ABID", NamedMatchClass<"ABID">>;
 
 def hwreg : NamedOperandU32<"Hwreg", NamedMatchClass<"Hwreg", 0>>;
 
 def exp_tgt : NamedOperandU32<"ExpTgt", NamedMatchClass<"ExpTgt", 0>> {
 
 }
 
+def wait_vdst : NamedOperandU8<"WaitVDST", NamedMatchClass<"WaitVDST">>;
+
 } // End OperandType = "OPERAND_IMMEDIATE"
 
 class KImmMatchClass<int size> : AsmOperandClass {
   let Name = "KImmFP"#size;
   let PredicateMethod = "isKImmFP"#size;
   let ParserMethod = "parseImm";
   let RenderMethod = "addKImmFP"#size#"Operands";
 }

llvm/lib/Target/AMDGPU/SIInstructions.td

class DivergentSextInreg<ValueType VT> : PatFrag<
   [{ return N->isDivergent(); }]>;
 
 include "SOPInstructions.td"
 include "VOPInstructions.td"
 include "SMInstructions.td"
 include "FLATInstructions.td"
 include "BUFInstructions.td"
 include "EXPInstructions.td"
+include "LDSDIRInstructions.td"
 
 //===----------------------------------------------------------------------===//
 // VINTRP Instructions
 //===----------------------------------------------------------------------===//
 
 // Used to inject printing of "_e32" suffix for VI (there are "_e64" variants for VI)
 def VINTRPDst : VINTRPDstOperand <VGPR_32>;
 

llvm/test/MC/AMDGPU/gfx11_err.s

 s_delay_alu instid0(VALU_DEP_9|)
 // GFX11: [[@LINE-1]]:{{[0-9]+}}: error: expected a right parenthesis
 
 s_delay_alu instid0(VALU_DEP_1) | (SALU_CYCLE_1)
 // GFX11: [[@LINE-1]]:{{[0-9]+}}: error: expected a field name
 
 s_delay_alu instid0(VALU_DEP_1) | SALU_CYCLE_1)
 // GFX11: [[@LINE-1]]:{{[0-9]+}}: error: expected a left parenthesis
+
+lds_direct_load v15 wait_vdst:16
+// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+lds_direct_load v15 wait_vdst
+// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

llvm/test/MC/AMDGPU/ldsdir.s

+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX11 %s
+
+lds_direct_load v1 wait_vdst:15
+// GFX11: lds_direct_load v1 wait_vdst:15  ; encoding: [0x01,0x00,0x1f,0xce]
+
+lds_direct_load v2 wait_vdst:14
+// GFX11: lds_direct_load v2 wait_vdst:14  ; encoding: [0x02,0x00,0x1e,0xce]
+
+lds_direct_load v3 wait_vdst:13
+// GFX11: lds_direct_load v3 wait_vdst:13  ; encoding: [0x03,0x00,0x1d,0xce]
+
+lds_direct_load v4 wait_vdst:12
+// GFX11: lds_direct_load v4 wait_vdst:12  ; encoding: [0x04,0x00,0x1c,0xce]
+
+lds_direct_load v5 wait_vdst:11
+// GFX11: lds_direct_load v5 wait_vdst:11  ; encoding: [0x05,0x00,0x1b,0xce]
+
+lds_direct_load v6 wait_vdst:10
+// GFX11: lds_direct_load v6 wait_vdst:10  ; encoding: [0x06,0x00,0x1a,0xce]
+
+lds_direct_load v7 wait_vdst:9
+// GFX11: lds_direct_load v7 wait_vdst:9   ; encoding: [0x07,0x00,0x19,0xce]
+
+lds_direct_load v8 wait_vdst:8
+// GFX11: lds_direct_load v8 wait_vdst:8   ; encoding: [0x08,0x00,0x18,0xce]
+
+lds_direct_load v9 wait_vdst:7
+// GFX11: lds_direct_load v9 wait_vdst:7   ; encoding: [0x09,0x00,0x17,0xce]
+
+lds_direct_load v10 wait_vdst:6
+// GFX11: lds_direct_load v10 wait_vdst:6  ; encoding: [0x0a,0x00,0x16,0xce]
+
+lds_direct_load v11 wait_vdst:5
+// GFX11: lds_direct_load v11 wait_vdst:5  ; encoding: [0x0b,0x00,0x15,0xce]
+
+lds_direct_load v12 wait_vdst:4
+// GFX11: lds_direct_load v12 wait_vdst:4  ; encoding: [0x0c,0x00,0x14,0xce]
+
+lds_direct_load v13 wait_vdst:3
+// GFX11: lds_direct_load v13 wait_vdst:3  ; encoding: [0x0d,0x00,0x13,0xce]
+
+lds_direct_load v14 wait_vdst:2
+// GFX11: lds_direct_load v14 wait_vdst:2  ; encoding: [0x0e,0x00,0x12,0xce]
+
+lds_direct_load v15 wait_vdst:1
+// GFX11: lds_direct_load v15 wait_vdst:1  ; encoding: [0x0f,0x00,0x11,0xce]
+
+lds_direct_load v16 wait_vdst:0
+// GFX11: lds_direct_load v16  ; encoding: [0x10,0x00,0x10,0xce]
+
+lds_direct_load v17
+// GFX11: lds_direct_load v17  ; encoding: [0x11,0x00,0x10,0xce]
+
+lds_param_load v1, attr0.x wait_vdst:15
+// GFX11: lds_param_load v1, attr0.x wait_vdst:15   ; encoding: [0x01,0x00,0x0f,0xce]
+
+lds_param_load v2, attr0.y wait_vdst:14
+// GFX11: lds_param_load v2, attr0.y wait_vdst:14   ; encoding: [0x02,0x01,0x0e,0xce]
+
+lds_param_load v3, attr0.z wait_vdst:13
+// GFX11: lds_param_load v3, attr0.z wait_vdst:13   ; encoding: [0x03,0x02,0x0d,0xce]
+
+lds_param_load v4, attr0.w wait_vdst:12
+// GFX11: lds_param_load v4, attr0.w wait_vdst:12   ; encoding: [0x04,0x03,0x0c,0xce]
+
+lds_param_load v5, attr0.x wait_vdst:11
+// GFX11: lds_param_load v5, attr0.x wait_vdst:11   ; encoding: [0x05,0x00,0x0b,0xce]
+
+lds_param_load v6, attr1.x wait_vdst:10
+// GFX11: lds_param_load v6, attr1.x wait_vdst:10   ; encoding: [0x06,0x04,0x0a,0xce]
+
+lds_param_load v7, attr2.y wait_vdst:9
+// GFX11: lds_param_load v7, attr2.y wait_vdst:9    ; encoding: [0x07,0x09,0x09,0xce]
+
+lds_param_load v8, attr3.z wait_vdst:8
+// GFX11: lds_param_load v8, attr3.z wait_vdst:8    ; encoding: [0x08,0x0e,0x08,0xce]
+
+lds_param_load v9, attr4.w wait_vdst:7
+// GFX11: lds_param_load v9, attr4.w wait_vdst:7    ; encoding: [0x09,0x13,0x07,0xce]
+
+lds_param_load v10, attr11.x wait_vdst:6
+// GFX11: lds_param_load v10, attr11.x wait_vdst:6  ; encoding: [0x0a,0x2c,0x06,0xce]
+
+lds_param_load v11, attr22.y wait_vdst:5
+// GFX11: lds_param_load v11, attr22.y wait_vdst:5  ; encoding: [0x0b,0x59,0x05,0xce]
+
+lds_param_load v12, attr33.z wait_vdst:4
+// GFX11: lds_param_load v12, attr33.z wait_vdst:4  ; encoding: [0x0c,0x86,0x04,0xce]
+
+lds_param_load v13, attr63.x wait_vdst:3
+// GFX11: lds_param_load v13, attr63.x wait_vdst:3  ; encoding: [0x0d,0xfc,0x03,0xce]
+
+lds_param_load v14, attr63.y wait_vdst:2
+// GFX11: lds_param_load v14, attr63.y wait_vdst:2  ; encoding: [0x0e,0xfd,0x02,0xce]
+
+lds_param_load v15, attr63.z wait_vdst:1
+// GFX11: lds_param_load v15, attr63.z wait_vdst:1  ; encoding: [0x0f,0xfe,0x01,0xce]
+
+lds_param_load v16, attr63.w wait_vdst:0
+// GFX11: lds_param_load v16, attr63.w  ; encoding: [0x10,0xff,0x00,0xce]
+
+lds_param_load v17, attr63.w
+// GFX11: lds_param_load v17, attr63.w  ; encoding: [0x11,0xff,0x00,0xce]

llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_all.txt

 # GFX11: s_xor_saveexec_b64 s[104:105], s[102:103] ; encoding: [0x66,0x25,0xe8,0xbe]
 0x66,0x25,0xe8,0xbe
 
 # GFX11: s_xor_saveexec_b64 s[104:105], s[2:3]   ; encoding: [0x02,0x25,0xe8,0xbe]
 0x02,0x25,0xe8,0xbe
 
 # GFX11: s_xor_saveexec_b64 vcc, s[2:3]          ; encoding: [0x02,0x25,0xea,0xbe]
 0x02,0x25,0xea,0xbe
+
+# GFX11: lds_direct_load v10 wait_vdst:6         ; encoding: [0x0a,0x00,0x16,0xce]
+0x0a,0x00,0x16,0xce
+
+# GFX11: lds_direct_load v11 wait_vdst:5         ; encoding: [0x0b,0x00,0x15,0xce]
+0x0b,0x00,0x15,0xce
+
+# GFX11: lds_direct_load v12 wait_vdst:4         ; encoding: [0x0c,0x00,0x14,0xce]
+0x0c,0x00,0x14,0xce
+
+# GFX11: lds_direct_load v13 wait_vdst:3         ; encoding: [0x0d,0x00,0x13,0xce]
+0x0d,0x00,0x13,0xce
+
+# GFX11: lds_direct_load v14 wait_vdst:2         ; encoding: [0x0e,0x00,0x12,0xce]
+0x0e,0x00,0x12,0xce
+
+# GFX11: lds_direct_load v15 wait_vdst:1         ; encoding: [0x0f,0x00,0x11,0xce]
+0x0f,0x00,0x11,0xce
+
+# GFX11: lds_direct_load v16                     ; encoding: [0x10,0x00,0x10,0xce]
+0x10,0x00,0x10,0xce
+
+# GFX11: lds_direct_load v17                     ; encoding: [0x11,0x00,0x10,0xce]
+0x11,0x00,0x10,0xce
+
+# GFX11: lds_direct_load v1 wait_vdst:15         ; encoding: [0x01,0x00,0x1f,0xce]
+0x01,0x00,0x1f,0xce
+
+# GFX11: lds_direct_load v2 wait_vdst:14         ; encoding: [0x02,0x00,0x1e,0xce]
+0x02,0x00,0x1e,0xce
+
+# GFX11: lds_direct_load v3 wait_vdst:13         ; encoding: [0x03,0x00,0x1d,0xce]
+0x03,0x00,0x1d,0xce
+
+# GFX11: lds_direct_load v4 wait_vdst:12         ; encoding: [0x04,0x00,0x1c,0xce]
+0x04,0x00,0x1c,0xce
+
+# GFX11: lds_direct_load v5 wait_vdst:11         ; encoding: [0x05,0x00,0x1b,0xce]
+0x05,0x00,0x1b,0xce
+
+# GFX11: lds_direct_load v6 wait_vdst:10         ; encoding: [0x06,0x00,0x1a,0xce]
+0x06,0x00,0x1a,0xce
+
+# GFX11: lds_direct_load v7 wait_vdst:9          ; encoding: [0x07,0x00,0x19,0xce]
+0x07,0x00,0x19,0xce
+
+# GFX11: lds_direct_load v8 wait_vdst:8          ; encoding: [0x08,0x00,0x18,0xce]
+0x08,0x00,0x18,0xce
+
+# GFX11: lds_direct_load v9 wait_vdst:7          ; encoding: [0x09,0x00,0x17,0xce]
+0x09,0x00,0x17,0xce
+
+# GFX11: lds_param_load v10, attr11.x wait_vdst:6 ; encoding: [0x0a,0x2c,0x06,0xce]
+0x0a,0x2c,0x06,0xce
+
+# GFX11: lds_param_load v11, attr22.y wait_vdst:5 ; encoding: [0x0b,0x59,0x05,0xce]
+0x0b,0x59,0x05,0xce
+
+# GFX11: lds_param_load v12, attr33.z wait_vdst:4 ; encoding: [0x0c,0x86,0x04,0xce]
+0x0c,0x86,0x04,0xce
+
+# GFX11: lds_param_load v13, attr63.x wait_vdst:3 ; encoding: [0x0d,0xfc,0x03,0xce]
+0x0d,0xfc,0x03,0xce
+
+# GFX11: lds_param_load v14, attr63.y wait_vdst:2 ; encoding: [0x0e,0xfd,0x02,0xce]
+0x0e,0xfd,0x02,0xce
+
+# GFX11: lds_param_load v15, attr63.z wait_vdst:1 ; encoding: [0x0f,0xfe,0x01,0xce]
+0x0f,0xfe,0x01,0xce
+
+# GFX11: lds_param_load v16, attr63.w            ; encoding: [0x10,0xff,0x00,0xce]
+0x10,0xff,0x00,0xce
+
+# GFX11: lds_param_load v17, attr63.w            ; encoding: [0x11,0xff,0x00,0xce]
+0x11,0xff,0x00,0xce
+
+# GFX11: lds_param_load v1, attr0.x wait_vdst:15 ; encoding: [0x01,0x00,0x0f,0xce]
+0x01,0x00,0x0f,0xce
+
+# GFX11: lds_param_load v2, attr0.y wait_vdst:14 ; encoding: [0x02,0x01,0x0e,0xce]
+0x02,0x01,0x0e,0xce
+
+# GFX11: lds_param_load v3, attr0.z wait_vdst:13 ; encoding: [0x03,0x02,0x0d,0xce]
+0x03,0x02,0x0d,0xce
+
+# GFX11: lds_param_load v4, attr0.w wait_vdst:12 ; encoding: [0x04,0x03,0x0c,0xce]
+0x04,0x03,0x0c,0xce
+
+# GFX11: lds_param_load v5, attr0.x wait_vdst:11 ; encoding: [0x05,0x00,0x0b,0xce]
+0x05,0x00,0x0b,0xce
+
+# GFX11: lds_param_load v6, attr1.x wait_vdst:10 ; encoding: [0x06,0x04,0x0a,0xce]
+0x06,0x04,0x0a,0xce
+
+# GFX11: lds_param_load v7, attr2.y wait_vdst:9  ; encoding: [0x07,0x09,0x09,0xce]
+0x07,0x09,0x09,0xce
+
+# GFX11: lds_param_load v8, attr3.z wait_vdst:8  ; encoding: [0x08,0x0e,0x08,0xce]
+0x08,0x0e,0x08,0xce
+
+# GFX11: lds_param_load v9, attr4.w wait_vdst:7  ; encoding: [0x09,0x13,0x07,0xce]
+0x09,0x13,0x07,0xce