[AMDGPU] gfx11 Decode wider instructions. NFC

[Joe_Nash]

Summary

Refactor to pass a templatized size parameter to the decoder to allow wider than
64bit decodes in a later patch.

Contributors:
Jay Foad <[e-mail]>

Depends on D125261

Patch 5/N for upstreaming of AMDGPU gfx11 architecture.

[dp]

Overall looks fine, but I do not understand the context in which DecoderUInt128 will be used.

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

425

Compiler should be able to deduce template type by QW type, why did you specify the type explicitly?

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h

42

Should be camel case.

53–54

Ditto.
Also it looks a bit illogical that the arguments are specified in the reversed order compared with insertBits. I assume this is required by autogenerated code?

[Joe_Nash]

removed DecoderUInt128 from patch. removed explicit template arguments.

[Joe_Nash]

In D125316#3503925, @dp wrote:

Overall looks fine, but I do not understand the context in which DecoderUInt128 will be used.

Its not needed here, I will move it to a more relevant patch.

[dp]

LGTM

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h

 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
 #define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
 
 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
 #include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCInst.h"
 #include "llvm/Support/DataExtractor.h"
 #include <memory>
 
 namespace llvm {
 
 class MCInst;
 class MCOperand;
 class MCSubtargetInfo;
 class Twine;
 
 //===----------------------------------------------------------------------===//
 // AMDGPUDisassembler
 //===----------------------------------------------------------------------===//
 
 class AMDGPUDisassembler : public MCDisassembler {
 private:
   std::unique_ptr<MCInstrInfo const> const MCII;
   const MCRegisterInfo &MRI;
   const unsigned TargetMaxInstBytes;
   mutable ArrayRef<uint8_t> Bytes;
   mutable uint32_t Literal;
   mutable bool HasLiteral;
 
 public:
   AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
                      MCInstrInfo const *MCII);
   ~AMDGPUDisassembler() override = default;
 
   DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
                               ArrayRef<uint8_t> Bytes, uint64_t Address,
                               raw_ostream &CS) const override;
 
   const char* getRegClassName(unsigned RegClassID) const;
 
   MCOperand createRegOperand(unsigned int RegId) const;
   MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
   MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
 
   MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
 
-  DecodeStatus tryDecodeInst(const uint8_t* Table, MCInst &MI, uint64_t Inst,
-                             uint64_t Address) const;
+  template <typename InsnType>
+  DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst,
+                             uint64_t Address) const {
+    assert(MI.getOpcode() == 0);
+    assert(MI.getNumOperands() == 0);
+    MCInst TmpInst;
+    HasLiteral = false;
+    const auto SavedBytes = Bytes;
+    if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
+      MI = TmpInst;
+      return MCDisassembler::Success;
+    }
+    Bytes = SavedBytes;
+    return MCDisassembler::Fail;
+  }
 
   Optional<DecodeStatus> onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size,
                                        ArrayRef<uint8_t> Bytes,
                                        uint64_t Address,
                                        raw_ostream &CStream) const override;
 
   DecodeStatus decodeKernelDescriptor(StringRef KdName, ArrayRef<uint8_t> Bytes,
                                       uint64_t KdAddress) const;

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

 
 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
   assert(Bytes.size() >= sizeof(T));
   const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
   Bytes = Bytes.slice(sizeof(T));
   return Res;
 }
 
-DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
-                                               MCInst &MI,
-                                               uint64_t Inst,
-                                               uint64_t Address) const {
-  assert(MI.getOpcode() == 0);
-  assert(MI.getNumOperands() == 0);
-  MCInst TmpInst;
-  HasLiteral = false;
-  const auto SavedBytes = Bytes;
-  if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
-    MI = TmpInst;
-    return MCDisassembler::Success;
-  }
-  Bytes = SavedBytes;
-  return MCDisassembler::Fail;
-}
-
 // The disassembler is greedy, so we need to check FI operand value to
 // not parse a dpp if the correct literal is not set. For dpp16 the
 // autogenerated decoder checks the dpp literal
 static bool isValidDPP8(const MCInst &MI) {
   using namespace llvm::AMDGPU::DPP;
   int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi);
   assert(FiIdx != -1);
   if ((unsigned)FiIdx >= MI.getNumOperands())
do {
     // but it is unknown yet, so try all we can
 
     // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
     // encodings
     if (Bytes.size() >= 8) {
       const uint64_t QW = eatBytes<uint64_t>(Bytes);
 
       if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) {
         Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address);
         if (Res) {
           if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8)
               == -1)
             break;
           if (convertDPP8Inst(MI) == MCDisassembler::Success)
             break;
           MI = MCInst(); // clear
         }