[ARM] Don't Enable AES Pass for Generic Cores

[lenary]

Summary

This brings clang/llvm into line with GCC. The Pass is still enabled for
the affected cores, but is now opt-in when using -march=.

I also took the opportunity to add release notes for this change.

[john.brawn]

LGTM.

clang/docs/ReleaseNotes.rst

 
 New Compiler Flags
 ------------------
 - Added the ``-fno-knr-functions`` flag to allow users to opt into the C2x
   behavior where a function with an empty parameter list is treated as though
   the parameter list were ``void``. There is no ``-fknr-functions`` or
   ``-fno-no-knr-functions`` flag; this feature cannot be disabled in language
   modes where it is required, such as C++ or C2x.
+- A new ARM pass to workaround Cortex-A57 Erratum 1742098 and Cortex-A72 Erratum
+  1655431 can be enabled using ``-mfix-cortex-a57-aes-1742098`` or
+  ``-mfix-cortex-a72-aes-1655431``. The pass is enabled when using either of
+  these cpus with ``-mcpu=`` and can be disabled using
+  ``-mno-fix-cortex-a57-aes-1742098`` or ``-mno-fix-cortex-a72-aes-1655431``.
 
 Deprecated Compiler Flags
 -------------------------
 
 Modified Compiler Flags
 -----------------------
 
 Removed Compiler Flags

llvm/docs/ReleaseNotes.rst

 * Added support for the Armv9-A, Armv9.1-A and Armv9.2-A architectures.
 * Added support for the Armv8.1-M PACBTI-M extension.
 * Added support for the Armv9-A, Armv9.1-A and Armv9.2-A architectures.
 * Added support for the Armv8.1-M PACBTI-M extension.
 * Removed the deprecation of ARMv8-A T32 Complex IT blocks. No deprecation
   warnings will be generated and -mrestrict-it is now always off by default.
   Previously it was on by default for Armv8 and off for all other architecture
   versions.
+* Added a pass to workaround Cortex-A57 Erratum 1742098 and Cortex-A72
+  Erratum 1655431. This is enabled by default when targeting either CPU.
 
 Changes to the AVR Backend
 --------------------------
 
 * ...
 
 Changes to the Hexagon Backend
 ------------------------------

llvm/lib/Target/ARM/ARM.td

 include "ARMScheduleA57.td"
 include "ARMScheduleM4.td"
 include "ARMScheduleM7.td"
 
 //===----------------------------------------------------------------------===//
 // ARM processors
 //
 // Dummy CPU, used to target architectures
-def : ProcessorModel<"generic",     CortexA8Model,      [FeatureFixCortexA57AES1742098]>;
+def : ProcessorModel<"generic",     CortexA8Model,      []>;
 
 // FIXME: Several processors below are not using their own scheduler
 // model, but one of similar/previous processor. These should be fixed.
 
 def : ProcNoItin<"arm8",                                [ARMv4]>;
 def : ProcNoItin<"arm810",                              [ARMv4]>;
 def : ProcNoItin<"strongarm",                           [ARMv4]>;
 def : ProcNoItin<"strongarm110",                        [ARMv4]>;