[RISCV] Use check-prefixes to reduce check lines

[frasercrmck]

llvm/test/CodeGen/RISCV/float-arith.ll

3

RV32IF is unused and that's an error. You should see this when running locally?

llvm/test/CodeGen/RISCV/float-fcmp-strict.ll

4

RV32IF is unused

llvm/test/CodeGen/RISCV/float-fcmp.ll

3

RV32IF unused

[sunshaoce]

Address @frasercrmck's comments. Thanks!

[sunshaoce]

Add more tests

[frasercrmck]

llvm/test/CodeGen/RISCV/float-isnan.ll

3

--check-prefixes=CHECK is redundant

7–8

These dead check prefixes can be removed

llvm/test/CodeGen/RISCV/float-select-fcmp.ll

3

Why's this CHECKIF and not CHECK?

7–8

Dead check prefixes here.

[sunshaoce]

Address @frasercrmck's comments.

[frasercrmck]

llvm/test/CodeGen/RISCV/double-arith-strict.ll

4

I think CHECK only fits if it's common to all RUN lines in the test. Here I'd prefer CHECKIFD, for instance, as it's a combined check for the IFD cases.

[sunshaoce]

Address @frasercrmck's comments.

[sunshaoce]

ping

[frasercrmck]

llvm/test/CodeGen/RISCV/double-fcmp-strict.ll

4

CHECKIFD here I think since we still have RV32I and RV64I separate

llvm/test/CodeGen/RISCV/double-fcmp.ll

3

CHECKIFD here too

llvm/test/CodeGen/RISCV/float-arith-strict.ll

4

CHECKIF - there's no D in this test.

llvm/test/CodeGen/RISCV/float-arith.ll

3

CHECKIF here because RV32I/RV64I are still used

llvm/test/CodeGen/RISCV/float-convert-strict.ll

4

CHECKIF - no D

llvm/test/CodeGen/RISCV/float-convert.ll

3

CHECKIF

llvm/test/CodeGen/RISCV/float-fcmp-strict.ll

4

CHECKIF

llvm/test/CodeGen/RISCV/float-fcmp.ll

3

CHECKIF

llvm/test/CodeGen/RISCV/float-imm.ll

7

I think this comment should be left where it is - it refers to the architecture, not the check prefix.

llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll

4

CHECKIF - no D

llvm/test/CodeGen/RISCV/float-mem.ll

3

CHECKIF

llvm/test/CodeGen/RISCV/float-round-conv-sat.ll

3

CHECKIF

llvm/test/CodeGen/RISCV/half-arith.ll

3

CHECKIFZFH so that CHECK doesn't look like it should cover RV32I and RV64I too

llvm/test/CodeGen/RISCV/half-convert-strict.ll

4

CHECKIZFH

llvm/test/CodeGen/RISCV/half-convert.ll

3

No F or D here - CHECKIZFH

llvm/test/CodeGen/RISCV/half-fcmp.ll

3

CHECKIZFH

llvm/test/CodeGen/RISCV/half-intrinsics.ll

4

CHECKIZFH

llvm/test/CodeGen/RISCV/half-mem.ll

3

CHECKIZFH or CHECK

llvm/test/CodeGen/RISCV/half-round-conv-sat.ll

3

CHECKIZFH or CHECK

llvm/test/CodeGen/RISCV/half-round-conv.ll

3

CHECKIZFH or CHECK

[sunshaoce]

Address comments.

[frasercrmck]

LGTM, thanks!

llvm/test/CodeGen/RISCV/double-arith-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=ilp32d \
-; RUN:   | FileCheck -check-prefix=RV32IFD %s
+; RUN:   | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=lp64d \
-; RUN:   | FileCheck -check-prefix=RV64IFD %s
+; RUN:   | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s
 
 define double @fadd_d(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fadd_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fadd.d fa0, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fadd_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fadd.d fa0, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fadd_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fadd.d fa0, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fadd_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __adddf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fadd_d:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __adddf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call double @llvm.experimental.constrained.fadd.f64(double %a, double %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret double %1
 }
 declare double @llvm.experimental.constrained.fadd.f64(double, double, metadata, metadata)
 
 define double @fsub_d(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fsub_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fsub.d fa0, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fsub_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fsub.d fa0, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fsub_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fsub.d fa0, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fsub_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __subdf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fsub_d:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __subdf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call double @llvm.experimental.constrained.fsub.f64(double %a, double %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret double %1
 }
 declare double @llvm.experimental.constrained.fsub.f64(double, double, metadata, metadata)
 
 define double @fmul_d(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fmul_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fmul.d fa0, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fmul_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fmul.d fa0, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fmul_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fmul.d fa0, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fmul_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __muldf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fmul_d:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __muldf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call double @llvm.experimental.constrained.fmul.f64(double %a, double %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret double %1
 }
 declare double @llvm.experimental.constrained.fmul.f64(double, double, metadata, metadata)
 
 define double @fdiv_d(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fdiv_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fdiv.d fa0, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fdiv_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fdiv.d fa0, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fdiv_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fdiv.d fa0, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fdiv_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __divdf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fdiv_d:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __divdf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call double @llvm.experimental.constrained.fdiv.f64(double %a, double %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret double %1
 }
 declare double @llvm.experimental.constrained.fdiv.f64(double, double, metadata, metadata)
 
 define double @fsqrt_d(double %a) nounwind strictfp {
-; RV32IFD-LABEL: fsqrt_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fsqrt.d fa0, fa0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fsqrt_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fsqrt.d fa0, fa0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fsqrt_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fsqrt.d fa0, fa0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fsqrt_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call sqrt@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call double @llvm.experimental.constrained.maxnum.f64(double %a, double %b, metadata !"fpexcept.strict") strictfp
   ret double %1
 }
 declare double @llvm.experimental.constrained.maxnum.f64(double, double, metadata) strictfp
 
 define double @fmadd_d(double %a, double %b, double %c) nounwind strictfp {
-; RV32IFD-LABEL: fmadd_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fmadd.d fa0, fa0, fa1, fa2
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fmadd_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fmadd.d fa0, fa0, fa1, fa2
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fmadd_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fmadd.d fa0, fa0, fa1, fa2
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fmadd_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fma@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

llvm/test/CodeGen/RISCV/double-arith.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32d | FileCheck -check-prefix=RV32IFD %s
+; RUN:   -target-abi=ilp32d | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64d | FileCheck -check-prefix=RV64IFD %s
+; RUN:   -target-abi=lp64d | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 ; These tests are each targeted at a particular RISC-V FPU instruction.
 ; Compares and conversions can be found in double-fcmp.ll and double-convert.ll
 ; respectively. Some other double-*.ll files in this folder exercise LLVM IR
 ; instructions that don't directly match a RISC-V instruction.
 
 define double @fadd_d(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fadd_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fadd.d fa0, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fadd_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fadd.d fa0, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fadd_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fadd.d fa0, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fadd_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __adddf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fadd_d:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __adddf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fadd double %a, %b
   ret double %1
 }
 
 define double @fsub_d(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fsub_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fsub.d fa0, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fsub_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fsub.d fa0, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fsub_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fsub.d fa0, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fsub_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __subdf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fsub_d:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __subdf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fsub double %a, %b
   ret double %1
 }
 
 define double @fmul_d(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fmul_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fmul.d fa0, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fmul_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fmul.d fa0, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fmul_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fmul.d fa0, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fmul_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __muldf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fmul_d:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __muldf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fmul double %a, %b
   ret double %1
 }
 
 define double @fdiv_d(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fdiv_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fdiv.d fa0, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fdiv_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fdiv.d fa0, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fdiv_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fdiv.d fa0, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fdiv_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __divdf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = fdiv double %a, %b
   ret double %1
 }
 
 declare double @llvm.sqrt.f64(double)
 
 define double @fsqrt_d(double %a) nounwind {
-; RV32IFD-LABEL: fsqrt_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fsqrt.d fa0, fa0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fsqrt_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fsqrt.d fa0, fa0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fsqrt_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fsqrt.d fa0, fa0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fsqrt_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call sqrt@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call double @llvm.sqrt.f64(double %a)
   ret double %1
 }
 
 declare double @llvm.copysign.f64(double, double)
 
 define double @fsgnj_d(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fsgnj_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fsgnj.d fa0, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fsgnj_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fsgnj.d fa0, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fsgnj_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fsgnj.d fa0, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fsgnj_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a2, 524288
 ; RV32I-NEXT:    and a2, a3, a2
 ; RV32I-NEXT:    slli a1, a1, 1
 ; RV32I-NEXT:    srli a1, a1, 1
 ; RV32I-NEXT:    or a1, a1, a2

 ; RV64I-NEXT:    ret
   %1 = call double @llvm.copysign.f64(double %a, double %b)
   ret double %1
 }
 
 ; This function performs extra work to ensure that
 ; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
 define i32 @fneg_d(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fneg_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fadd.d ft0, fa0, fa0
-; RV32IFD-NEXT:    fneg.d ft1, ft0
-; RV32IFD-NEXT:    feq.d a0, ft0, ft1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fneg_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fadd.d ft0, fa0, fa0
-; RV64IFD-NEXT:    fneg.d ft1, ft0
-; RV64IFD-NEXT:    feq.d a0, ft0, ft1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fneg_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fadd.d ft0, fa0, fa0
+; CHECKIFD-NEXT:    fneg.d ft1, ft0
+; CHECKIFD-NEXT:    feq.d a0, ft0, ft1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fneg_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv a2, a0
 ; RV32I-NEXT:    mv a3, a1
 ; RV32I-NEXT:    call __adddf3@plt
; RV64I-NEXT:    ret
   %4 = zext i1 %3 to i32
   ret i32 %4
 }
 
 define double @fsgnjn_d(double %a, double %b) nounwind {
 ; TODO: fsgnjn.s isn't selected on RV64 because DAGCombiner::visitBITCAST will
 ; convert (bitconvert (fneg x)) to a xor.
 ;
-; RV32IFD-LABEL: fsgnjn_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fsgnjn.d fa0, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fsgnjn_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fsgnjn.d fa0, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fsgnjn_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fsgnjn.d fa0, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fsgnjn_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    not a2, a3
 ; RV32I-NEXT:    lui a3, 524288
 ; RV32I-NEXT:    and a2, a2, a3
 ; RV32I-NEXT:    slli a1, a1, 1
 ; RV32I-NEXT:    srli a1, a1, 1
; RV64I-NEXT:    ret
   ret double %2
 }
 
 declare double @llvm.fabs.f64(double)
 
 ; This function performs extra work to ensure that
 ; DAGCombiner::visitBITCAST doesn't replace the fabs with an and.
 define double @fabs_d(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fabs_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fadd.d ft0, fa0, fa1
-; RV32IFD-NEXT:    fabs.d ft1, ft0
-; RV32IFD-NEXT:    fadd.d fa0, ft1, ft0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fabs_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fadd.d ft0, fa0, fa1
-; RV64IFD-NEXT:    fabs.d ft1, ft0
-; RV64IFD-NEXT:    fadd.d fa0, ft1, ft0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fabs_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fadd.d ft0, fa0, fa1
+; CHECKIFD-NEXT:    fabs.d ft1, ft0
+; CHECKIFD-NEXT:    fadd.d fa0, ft1, ft0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fabs_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __adddf3@plt
 ; RV32I-NEXT:    mv a3, a1
 ; RV32I-NEXT:    slli a1, a1, 1
; RV64I-NEXT:    ret
   %2 = call double @llvm.fabs.f64(double %1)
   %3 = fadd double %2, %1
   ret double %3
 }
 
 declare double @llvm.minnum.f64(double, double)
 
 define double @fmin_d(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fmin_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fmin.d fa0, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fmin_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fmin.d fa0, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fmin_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fmin.d fa0, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fmin_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fmin@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call double @llvm.minnum.f64(double %a, double %b)
   ret double %1
 }
 
 declare double @llvm.maxnum.f64(double, double)
 
 define double @fmax_d(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fmax_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fmax.d fa0, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fmax_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fmax.d fa0, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fmax_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fmax.d fa0, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fmax_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fmax@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call double @llvm.maxnum.f64(double %a, double %b)
   ret double %1
 }
 
 declare double @llvm.fma.f64(double, double, double)
 
 define double @fmadd_d(double %a, double %b, double %c) nounwind {
-; RV32IFD-LABEL: fmadd_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fmadd.d fa0, fa0, fa1, fa2
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fmadd_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fmadd.d fa0, fa0, fa1, fa2
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fmadd_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fmadd.d fa0, fa0, fa1, fa2
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fmadd_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fma@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %b_ = fadd double 0.0, %b
   %negb = fsub double -0.0, %b_
   %1 = call double @llvm.fma.f64(double %a, double %negb, double %c)
   ret double %1
 }
 
 define double @fmadd_d_contract(double %a, double %b, double %c) nounwind {
-; RV32IFD-LABEL: fmadd_d_contract:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fmadd.d fa0, fa0, fa1, fa2
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fmadd_d_contract:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fmadd.d fa0, fa0, fa1, fa2
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fmadd_d_contract:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fmadd.d fa0, fa0, fa1, fa2
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fmadd_d_contract:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a5

llvm/test/CodeGen/RISCV/double-convert-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=ilp32d \
-; RUN:   | FileCheck -check-prefix=RV32IFD %s
+; RUN:   | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=lp64d \
-; RUN:   | FileCheck -check-prefix=RV64IFD %s
+; RUN:   | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s
 
 ; NOTE: The rounding mode metadata does not effect which instruction is
 ; selected. Dynamic rounding mode is always used for operations that
 ; support rounding mode.
 
 define float @fcvt_s_d(double %a) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_s_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.s.d fa0, fa0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_s_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.s.d fa0, fa0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_s_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.s.d fa0, fa0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __truncdfsf2@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_d:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __truncdfsf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.fptrunc.f32.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
   ret float %1
 }
 declare float @llvm.experimental.constrained.fptrunc.f32.f64(double, metadata, metadata)
 
 define double @fcvt_d_s(float %a) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_d_s:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.d.s fa0, fa0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_d_s:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.d.s fa0, fa0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_d_s:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.d.s fa0, fa0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_d_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __extendsfdf2@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_d_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __extendsfdf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call double @llvm.experimental.constrained.fpext.f64.f32(float %a, metadata !"fpexcept.strict")
   ret double %1
 }
 declare double @llvm.experimental.constrained.fpext.f64.f32(float, metadata)
 
 define i32 @fcvt_w_d(double %a) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_w_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rtz
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_w_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rtz
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_w_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.w.d a0, fa0, rtz
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_w_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixdfsi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
; RV64I-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
 
 ; For RV64D, fcvt.lu.d is semantically equivalent to fcvt.wu.d in this case
 ; because fptosi will produce poison if the result doesn't fit into an i32.
 define i32 @fcvt_wu_d(double %a) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_wu_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_wu_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_wu_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rtz
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunsdfsi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
; RV64I-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata)
 
 ; Test where the fptoui has multiple uses, one of which causes a sext to be
 ; inserted on RV64.
 define i32 @fcvt_wu_d_multiple_use(double %x, i32* %y) nounwind {
-; RV32IFD-LABEL: fcvt_wu_d_multiple_use:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.wu.d a1, fa0, rtz
-; RV32IFD-NEXT:    li a0, 1
-; RV32IFD-NEXT:    beqz a1, .LBB4_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    mv a0, a1
-; RV32IFD-NEXT:  .LBB4_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_wu_d_multiple_use:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.wu.d a1, fa0, rtz
-; RV64IFD-NEXT:    li a0, 1
-; RV64IFD-NEXT:    beqz a1, .LBB4_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    mv a0, a1
-; RV64IFD-NEXT:  .LBB4_2:
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_wu_d_multiple_use:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.wu.d a1, fa0, rtz
+; CHECKIFD-NEXT:    li a0, 1
+; CHECKIFD-NEXT:    beqz a1, .LBB4_2
+; CHECKIFD-NEXT:  # %bb.1:
+; CHECKIFD-NEXT:    mv a0, a1
+; CHECKIFD-NEXT:  .LBB4_2:
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_d_multiple_use:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunsdfsi@plt
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    li a0, 1

 ; RV64I-NEXT:    ret
   %a = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %x, metadata !"fpexcept.strict") strictfp
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c
 }
 
 define double @fcvt_d_w(i32 %a) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_d_w:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.d.w fa0, a0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_d_w:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.d.w fa0, a0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_d_w:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.d.w fa0, a0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_d_w:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsidf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret double %1
 }
 declare double @llvm.experimental.constrained.sitofp.f64.i32(i32, metadata, metadata)
 
 define double @fcvt_d_w_load(i32* %p) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_d_w_load:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    lw a0, 0(a0)
-; RV32IFD-NEXT:    fcvt.d.w fa0, a0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_d_w_load:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    lw a0, 0(a0)
-; RV64IFD-NEXT:    fcvt.d.w fa0, a0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_d_w_load:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    lw a0, 0(a0)
+; CHECKIFD-NEXT:    fcvt.d.w fa0, a0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_d_w_load:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    lw a0, 0(a0)
 ; RV32I-NEXT:    call __floatsidf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %a = load i32, i32* %p
   %1 = call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret double %1
 }
 
 define double @fcvt_d_wu(i32 %a) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_d_wu:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.d.wu fa0, a0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_d_wu:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.d.wu fa0, a0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_d_wu:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.d.wu fa0, a0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_d_wu:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsidf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call double @llvm.experimental.constrained.uitofp.f64.i64(i64 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret double %1
 }
 declare double @llvm.experimental.constrained.uitofp.f64.i64(i64, metadata, metadata)
 
 define double @fcvt_d_w_i8(i8 signext %a) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_d_w_i8:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.d.w fa0, a0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_d_w_i8:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.d.w fa0, a0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_d_w_i8:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.d.w fa0, a0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_d_w_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsidf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_d_w_i8:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatsidf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call double @llvm.experimental.constrained.sitofp.f64.i8(i8 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret double %1
 }
 declare double @llvm.experimental.constrained.sitofp.f64.i8(i8, metadata, metadata)
 
 define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_d_wu_i8:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.d.wu fa0, a0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_d_wu_i8:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.d.wu fa0, a0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_d_wu_i8:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.d.wu fa0, a0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_d_wu_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsidf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_d_wu_i8:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatunsidf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call double @llvm.experimental.constrained.uitofp.f64.i8(i8 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret double %1
 }
 declare double @llvm.experimental.constrained.uitofp.f64.i8(i8, metadata, metadata)
 
 define double @fcvt_d_w_i16(i16 signext %a) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_d_w_i16:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.d.w fa0, a0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_d_w_i16:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.d.w fa0, a0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_d_w_i16:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.d.w fa0, a0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_d_w_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsidf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_d_w_i16:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatsidf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call double @llvm.experimental.constrained.sitofp.f64.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret double %1
 }
 declare double @llvm.experimental.constrained.sitofp.f64.i16(i16, metadata, metadata)
 
 define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind strictfp {
-; RV32IFD-LABEL: fcvt_d_wu_i16:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.d.wu fa0, a0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_d_wu_i16:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.d.wu fa0, a0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_d_wu_i16:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.d.wu fa0, a0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_d_wu_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsidf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

llvm/test/CodeGen/RISCV/double-convert.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32d | FileCheck -check-prefix=RV32IFD %s
+; RUN:   -target-abi=ilp32d | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64d | FileCheck -check-prefix=RV64IFD %s
+; RUN:   -target-abi=lp64d | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 define float @fcvt_s_d(double %a) nounwind {
-; RV32IFD-LABEL: fcvt_s_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.s.d fa0, fa0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_s_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.s.d fa0, fa0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_s_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.s.d fa0, fa0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __truncdfsf2@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_d:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __truncdfsf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fptrunc double %a to float
   ret float %1
 }
 
 define double @fcvt_d_s(float %a) nounwind {
-; RV32IFD-LABEL: fcvt_d_s:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.d.s fa0, fa0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_d_s:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.d.s fa0, fa0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_d_s:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.d.s fa0, fa0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_d_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __extendsfdf2@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_d_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __extendsfdf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fpext float %a to double
   ret double %1
 }
 
 define i32 @fcvt_w_d(double %a) nounwind {
-; RV32IFD-LABEL: fcvt_w_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rtz
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_w_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rtz
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_w_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.w.d a0, fa0, rtz
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_w_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixdfsi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_w_d:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __fixdfsi@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fptosi double %a to i32
   ret i32 %1
 }
 
 define i32 @fcvt_w_d_sat(double %a) nounwind {
-; RV32IFD-LABEL: fcvt_w_d_sat:
-; RV32IFD:       # %bb.0: # %start
-; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    beqz a0, .LBB3_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rtz
-; RV32IFD-NEXT:  .LBB3_2: # %start
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_w_d_sat:
-; RV64IFD:       # %bb.0: # %start
-; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    beqz a0, .LBB3_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rtz
-; RV64IFD-NEXT:  .LBB3_2: # %start
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_w_d_sat:
+; CHECKIFD:       # %bb.0: # %start
+; CHECKIFD-NEXT:    feq.d a0, fa0, fa0
+; CHECKIFD-NEXT:    beqz a0, .LBB3_2
+; CHECKIFD-NEXT:  # %bb.1:
+; CHECKIFD-NEXT:    fcvt.w.d a0, fa0, rtz
+; CHECKIFD-NEXT:  .LBB3_2: # %start
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_w_d_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
start:
   %0 = tail call i32 @llvm.fptosi.sat.i32.f64(double %a)
   ret i32 %0
 }
 declare i32 @llvm.fptosi.sat.i32.f64(double)
 
 ; For RV64D, fcvt.lu.d is semantically equivalent to fcvt.wu.d in this case
 ; because fptosi will produce poison if the result doesn't fit into an i32.
 define i32 @fcvt_wu_d(double %a) nounwind {
-; RV32IFD-LABEL: fcvt_wu_d:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_wu_d:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_wu_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rtz
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunsdfsi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = fptoui double %a to i32
   ret i32 %1
 }
 
 ; Test where the fptoui has multiple uses, one of which causes a sext to be
 ; inserted on RV64.
 define i32 @fcvt_wu_d_multiple_use(double %x, i32* %y) nounwind {
-; RV32IFD-LABEL: fcvt_wu_d_multiple_use:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.wu.d a1, fa0, rtz
-; RV32IFD-NEXT:    li a0, 1
-; RV32IFD-NEXT:    beqz a1, .LBB5_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    mv a0, a1
-; RV32IFD-NEXT:  .LBB5_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_wu_d_multiple_use:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.wu.d a1, fa0, rtz
-; RV64IFD-NEXT:    li a0, 1
-; RV64IFD-NEXT:    beqz a1, .LBB5_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    mv a0, a1
-; RV64IFD-NEXT:  .LBB5_2:
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_wu_d_multiple_use:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.wu.d a1, fa0, rtz
+; CHECKIFD-NEXT:    li a0, 1
+; CHECKIFD-NEXT:    beqz a1, .LBB5_2
+; CHECKIFD-NEXT:  # %bb.1:
+; CHECKIFD-NEXT:    mv a0, a1
+; CHECKIFD-NEXT:  .LBB5_2:
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_d_multiple_use:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunsdfsi@plt
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    li a0, 1

 ; RV64I-NEXT:    ret
   %a = fptoui double %x to i32
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c
 }
 
 define i32 @fcvt_wu_d_sat(double %a) nounwind {
-; RV32IFD-LABEL: fcvt_wu_d_sat:
-; RV32IFD:       # %bb.0: # %start
-; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    beqz a0, .LBB6_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
-; RV32IFD-NEXT:  .LBB6_2: # %start
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_wu_d_sat:
-; RV64IFD:       # %bb.0: # %start
-; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    beqz a0, .LBB6_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
-; RV64IFD-NEXT:  .LBB6_2: # %start
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_wu_d_sat:
+; CHECKIFD:       # %bb.0: # %start
+; CHECKIFD-NEXT:    feq.d a0, fa0, fa0
+; CHECKIFD-NEXT:    beqz a0, .LBB6_2
+; CHECKIFD-NEXT:  # %bb.1:
+; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rtz
+; CHECKIFD-NEXT:  .LBB6_2: # %start
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_d_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptoui.sat.i32.f64(double %a)
   ret i32 %0
 }
 declare i32 @llvm.fptoui.sat.i32.f64(double)
 
 define double @fcvt_d_w(i32 %a) nounwind {
-; RV32IFD-LABEL: fcvt_d_w:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.d.w fa0, a0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_d_w:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.d.w fa0, a0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_d_w:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.d.w fa0, a0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_d_w:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsidf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_d_w:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    call __floatsidf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = sitofp i32 %a to double
   ret double %1
 }
 
 define double @fcvt_d_w_load(i32* %p) nounwind {
-; RV32IFD-LABEL: fcvt_d_w_load:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    lw a0, 0(a0)
-; RV32IFD-NEXT:    fcvt.d.w fa0, a0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_d_w_load:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    lw a0, 0(a0)
-; RV64IFD-NEXT:    fcvt.d.w fa0, a0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_d_w_load:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    lw a0, 0(a0)
+; CHECKIFD-NEXT:    fcvt.d.w fa0, a0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_d_w_load:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    lw a0, 0(a0)
 ; RV32I-NEXT:    call __floatsidf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %a = load i32, i32* %p
   %1 = sitofp i32 %a to double
   ret double %1
 }
 
 define double @fcvt_d_wu(i32 %a) nounwind {
-; RV32IFD-LABEL: fcvt_d_wu:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.d.wu fa0, a0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_d_wu:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.d.wu fa0, a0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_d_wu:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.d.wu fa0, a0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_d_wu:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsidf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = bitcast i64 %a to double
   %2 = bitcast i64 %b to double
   %3 = fadd double %1, %2
   ret double %3
 }
 
 define double @fcvt_d_w_i8(i8 signext %a) nounwind {
-; RV32IFD-LABEL: fcvt_d_w_i8:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.d.w fa0, a0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_d_w_i8:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.d.w fa0, a0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_d_w_i8:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.d.w fa0, a0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_d_w_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsidf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_d_w_i8:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatsidf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = sitofp i8 %a to double
   ret double %1
 }
 
 define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind {
-; RV32IFD-LABEL: fcvt_d_wu_i8:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.d.wu fa0, a0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_d_wu_i8:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.d.wu fa0, a0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_d_wu_i8:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.d.wu fa0, a0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_d_wu_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsidf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_d_wu_i8:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatunsidf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = uitofp i8 %a to double
   ret double %1
 }
 
 define double @fcvt_d_w_i16(i16 signext %a) nounwind {
-; RV32IFD-LABEL: fcvt_d_w_i16:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.d.w fa0, a0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_d_w_i16:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.d.w fa0, a0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_d_w_i16:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.d.w fa0, a0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_d_w_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsidf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_d_w_i16:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatsidf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = sitofp i16 %a to double
   ret double %1
 }
 
 define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind {
-; RV32IFD-LABEL: fcvt_d_wu_i16:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.d.wu fa0, a0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcvt_d_wu_i16:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.d.wu fa0, a0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcvt_d_wu_i16:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.d.wu fa0, a0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_d_wu_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsidf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

llvm/test/CodeGen/RISCV/double-fcmp-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=ilp32d \
-; RUN:   | FileCheck -check-prefix=RV32IFD %s
+; RUN:   | FileCheck -check-prefix=CHECKIFD %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=lp64d \
-; RUN:   | FileCheck -check-prefix=RV64IFD %s
+; RUN:   | FileCheck -check-prefix=CHECKIFD %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s
 
 define i32 @fcmp_oeq(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_oeq:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_oeq:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmp_oeq:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    feq.d a0, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oeq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __eqdf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"oeq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 declare i1 @llvm.experimental.constrained.fcmp.f64(double, double, metadata, metadata)
 
 define i32 @fcmp_ogt(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_ogt:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    frflags a1
-; RV32IFD-NEXT:    flt.d a0, fa1, fa0
-; RV32IFD-NEXT:    fsflags a1
-; RV32IFD-NEXT:    feq.d zero, fa1, fa0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_ogt:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    frflags a1
-; RV64IFD-NEXT:    flt.d a0, fa1, fa0
-; RV64IFD-NEXT:    fsflags a1
-; RV64IFD-NEXT:    feq.d zero, fa1, fa0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmp_ogt:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    frflags a1
+; CHECKIFD-NEXT:    flt.d a0, fa1, fa0
+; CHECKIFD-NEXT:    fsflags a1
+; CHECKIFD-NEXT:    feq.d zero, fa1, fa0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oge(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_oge:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    frflags a1
-; RV32IFD-NEXT:    fle.d a0, fa1, fa0
-; RV32IFD-NEXT:    fsflags a1
-; RV32IFD-NEXT:    feq.d zero, fa1, fa0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_oge:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    frflags a1
-; RV64IFD-NEXT:    fle.d a0, fa1, fa0
-; RV64IFD-NEXT:    fsflags a1
-; RV64IFD-NEXT:    feq.d zero, fa1, fa0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmp_oge:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    frflags a1
+; CHECKIFD-NEXT:    fle.d a0, fa1, fa0
+; CHECKIFD-NEXT:    fsflags a1
+; CHECKIFD-NEXT:    feq.d zero, fa1, fa0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_olt(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_olt:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    frflags a1
-; RV32IFD-NEXT:    flt.d a0, fa0, fa1
-; RV32IFD-NEXT:    fsflags a1
-; RV32IFD-NEXT:    feq.d zero, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_olt:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    frflags a1
-; RV64IFD-NEXT:    flt.d a0, fa0, fa1
-; RV64IFD-NEXT:    fsflags a1
-; RV64IFD-NEXT:    feq.d zero, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmp_olt:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    frflags a1
+; CHECKIFD-NEXT:    flt.d a0, fa0, fa1
+; CHECKIFD-NEXT:    fsflags a1
+; CHECKIFD-NEXT:    feq.d zero, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_olt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltdf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ole(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_ole:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    frflags a1
-; RV32IFD-NEXT:    fle.d a0, fa0, fa1
-; RV32IFD-NEXT:    fsflags a1
-; RV32IFD-NEXT:    feq.d zero, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_ole:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    frflags a1
-; RV64IFD-NEXT:    fle.d a0, fa0, fa1
-; RV64IFD-NEXT:    fsflags a1
-; RV64IFD-NEXT:    feq.d zero, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmp_ole:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    frflags a1
+; CHECKIFD-NEXT:    fle.d a0, fa0, fa1
+; CHECKIFD-NEXT:    fsflags a1
+; CHECKIFD-NEXT:    feq.d zero, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ole:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ledf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 ; FIXME: We only need one frflags before the two flts and one fsflags after the
 ; two flts.
 define i32 @fcmp_one(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_one:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    frflags a0
-; RV32IFD-NEXT:    flt.d a1, fa0, fa1
-; RV32IFD-NEXT:    fsflags a0
-; RV32IFD-NEXT:    feq.d zero, fa0, fa1
-; RV32IFD-NEXT:    frflags a0
-; RV32IFD-NEXT:    flt.d a2, fa1, fa0
-; RV32IFD-NEXT:    fsflags a0
-; RV32IFD-NEXT:    or a0, a2, a1
-; RV32IFD-NEXT:    feq.d zero, fa1, fa0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_one:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    frflags a0
-; RV64IFD-NEXT:    flt.d a1, fa0, fa1
-; RV64IFD-NEXT:    fsflags a0
-; RV64IFD-NEXT:    feq.d zero, fa0, fa1
-; RV64IFD-NEXT:    frflags a0
-; RV64IFD-NEXT:    flt.d a2, fa1, fa0
-; RV64IFD-NEXT:    fsflags a0
-; RV64IFD-NEXT:    or a0, a2, a1
-; RV64IFD-NEXT:    feq.d zero, fa1, fa0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmp_one:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    frflags a0
+; CHECKIFD-NEXT:    flt.d a1, fa0, fa1
+; CHECKIFD-NEXT:    fsflags a0
+; CHECKIFD-NEXT:    feq.d zero, fa0, fa1
+; CHECKIFD-NEXT:    frflags a0
+; CHECKIFD-NEXT:    flt.d a2, fa1, fa0
+; CHECKIFD-NEXT:    fsflags a0
+; CHECKIFD-NEXT:    or a0, a2, a1
+; CHECKIFD-NEXT:    feq.d zero, fa1, fa0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"one", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ord(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_ord:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa1, fa1
-; RV32IFD-NEXT:    feq.d a1, fa0, fa0
-; RV32IFD-NEXT:    and a0, a1, a0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_ord:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa1, fa1
-; RV64IFD-NEXT:    feq.d a1, fa0, fa0
-; RV64IFD-NEXT:    and a0, a1, a0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmp_ord:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    feq.d a0, fa1, fa1
+; CHECKIFD-NEXT:    feq.d a1, fa0, fa0
+; CHECKIFD-NEXT:    and a0, a1, a0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ord:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unorddf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ord", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 ; FIXME: We only need one frflags before the two flts and one fsflags after the
 ; two flts.
 define i32 @fcmp_ueq(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_ueq:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    frflags a0
-; RV32IFD-NEXT:    flt.d a1, fa0, fa1
-; RV32IFD-NEXT:    fsflags a0
-; RV32IFD-NEXT:    feq.d zero, fa0, fa1
-; RV32IFD-NEXT:    frflags a0
-; RV32IFD-NEXT:    flt.d a2, fa1, fa0
-; RV32IFD-NEXT:    fsflags a0
-; RV32IFD-NEXT:    or a0, a2, a1
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    feq.d zero, fa1, fa0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_ueq:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    frflags a0
-; RV64IFD-NEXT:    flt.d a1, fa0, fa1
-; RV64IFD-NEXT:    fsflags a0
-; RV64IFD-NEXT:    feq.d zero, fa0, fa1
-; RV64IFD-NEXT:    frflags a0
-; RV64IFD-NEXT:    flt.d a2, fa1, fa0
-; RV64IFD-NEXT:    fsflags a0
-; RV64IFD-NEXT:    or a0, a2, a1
-; RV64IFD-NEXT:    xori a0, a0, 1
-; RV64IFD-NEXT:    feq.d zero, fa1, fa0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmp_ueq:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    frflags a0
+; CHECKIFD-NEXT:    flt.d a1, fa0, fa1
+; CHECKIFD-NEXT:    fsflags a0
+; CHECKIFD-NEXT:    feq.d zero, fa0, fa1
+; CHECKIFD-NEXT:    frflags a0
+; CHECKIFD-NEXT:    flt.d a2, fa1, fa0
+; CHECKIFD-NEXT:    fsflags a0
+; CHECKIFD-NEXT:    or a0, a2, a1
+; CHECKIFD-NEXT:    xori a0, a0, 1
+; CHECKIFD-NEXT:    feq.d zero, fa1, fa0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ueq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ugt(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_ugt:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    frflags a0
-; RV32IFD-NEXT:    fle.d a1, fa0, fa1
-; RV32IFD-NEXT:    fsflags a0
-; RV32IFD-NEXT:    xori a0, a1, 1
-; RV32IFD-NEXT:    feq.d zero, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_ugt:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    frflags a0
-; RV64IFD-NEXT:    fle.d a1, fa0, fa1
-; RV64IFD-NEXT:    fsflags a0
-; RV64IFD-NEXT:    xori a0, a1, 1
-; RV64IFD-NEXT:    feq.d zero, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmp_ugt:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    frflags a0
+; CHECKIFD-NEXT:    fle.d a1, fa0, fa1
+; CHECKIFD-NEXT:    fsflags a0
+; CHECKIFD-NEXT:    xori a0, a1, 1
+; CHECKIFD-NEXT:    feq.d zero, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ledf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uge(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_uge:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    frflags a0
-; RV32IFD-NEXT:    flt.d a1, fa0, fa1
-; RV32IFD-NEXT:    fsflags a0
-; RV32IFD-NEXT:    xori a0, a1, 1
-; RV32IFD-NEXT:    feq.d zero, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_uge:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    frflags a0
-; RV64IFD-NEXT:    flt.d a1, fa0, fa1
-; RV64IFD-NEXT:    fsflags a0
-; RV64IFD-NEXT:    xori a0, a1, 1
-; RV64IFD-NEXT:    feq.d zero, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmp_uge:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    frflags a0
+; CHECKIFD-NEXT:    flt.d a1, fa0, fa1
+; CHECKIFD-NEXT:    fsflags a0
+; CHECKIFD-NEXT:    xori a0, a1, 1
+; CHECKIFD-NEXT:    feq.d zero, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltdf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ult(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_ult:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    frflags a0
-; RV32IFD-NEXT:    fle.d a1, fa1, fa0
-; RV32IFD-NEXT:    fsflags a0
-; RV32IFD-NEXT:    xori a0, a1, 1
-; RV32IFD-NEXT:    feq.d zero, fa1, fa0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_ult:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    frflags a0
-; RV64IFD-NEXT:    fle.d a1, fa1, fa0
-; RV64IFD-NEXT:    fsflags a0
-; RV64IFD-NEXT:    xori a0, a1, 1
-; RV64IFD-NEXT:    feq.d zero, fa1, fa0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmp_ult:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    frflags a0
+; CHECKIFD-NEXT:    fle.d a1, fa1, fa0
+; CHECKIFD-NEXT:    fsflags a0
+; CHECKIFD-NEXT:    xori a0, a1, 1
+; CHECKIFD-NEXT:    feq.d zero, fa1, fa0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ult:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ult", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ule(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_ule:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    frflags a0
-; RV32IFD-NEXT:    flt.d a1, fa1, fa0
-; RV32IFD-NEXT:    fsflags a0
-; RV32IFD-NEXT:    xori a0, a1, 1
-; RV32IFD-NEXT:    feq.d zero, fa1, fa0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_ule:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    frflags a0
-; RV64IFD-NEXT:    flt.d a1, fa1, fa0
-; RV64IFD-NEXT:    fsflags a0
-; RV64IFD-NEXT:    xori a0, a1, 1
-; RV64IFD-NEXT:    feq.d zero, fa1, fa0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmp_ule:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    frflags a0
+; CHECKIFD-NEXT:    flt.d a1, fa1, fa0
+; CHECKIFD-NEXT:    fsflags a0
+; CHECKIFD-NEXT:    xori a0, a1, 1
+; CHECKIFD-NEXT:    feq.d zero, fa1, fa0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ule", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_une(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_une:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa0, fa1
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_une:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa0, fa1
-; RV64IFD-NEXT:    xori a0, a0, 1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmp_une:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    feq.d a0, fa0, fa1
+; CHECKIFD-NEXT:    xori a0, a0, 1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_une:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __nedf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"une", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uno(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmp_uno:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa1, fa1
-; RV32IFD-NEXT:    feq.d a1, fa0, fa0
-; RV32IFD-NEXT:    and a0, a1, a0
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_uno:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa1, fa1
-; RV64IFD-NEXT:    feq.d a1, fa0, fa0
-; RV64IFD-NEXT:    and a0, a1, a0
-; RV64IFD-NEXT:    xori a0, a0, 1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmp_uno:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    feq.d a0, fa1, fa1
+; CHECKIFD-NEXT:    feq.d a1, fa0, fa0
+; CHECKIFD-NEXT:    and a0, a1, a0
+; CHECKIFD-NEXT:    xori a0, a0, 1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uno:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unorddf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"uno", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_oeq(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_oeq:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fle.d a0, fa1, fa0
-; RV32IFD-NEXT:    fle.d a1, fa0, fa1
-; RV32IFD-NEXT:    and a0, a1, a0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmps_oeq:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fle.d a0, fa1, fa0
-; RV64IFD-NEXT:    fle.d a1, fa0, fa1
-; RV64IFD-NEXT:    and a0, a1, a0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmps_oeq:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fle.d a0, fa1, fa0
+; CHECKIFD-NEXT:    fle.d a1, fa0, fa1
+; CHECKIFD-NEXT:    and a0, a1, a0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_oeq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __eqdf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"oeq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 declare i1 @llvm.experimental.constrained.fcmps.f64(double, double, metadata, metadata)
 
 define i32 @fcmps_ogt(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_ogt:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    flt.d a0, fa1, fa0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmps_ogt:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    flt.d a0, fa1, fa0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmps_ogt:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    flt.d a0, fa1, fa0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_oge(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_oge:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fle.d a0, fa1, fa0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmps_oge:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fle.d a0, fa1, fa0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmps_oge:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fle.d a0, fa1, fa0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_olt(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_olt:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    flt.d a0, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmps_olt:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    flt.d a0, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmps_olt:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    flt.d a0, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_olt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltdf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ole(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_ole:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fle.d a0, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmps_ole:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fle.d a0, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmps_ole:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fle.d a0, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ole:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ledf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_one(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_one:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    flt.d a0, fa0, fa1
-; RV32IFD-NEXT:    flt.d a1, fa1, fa0
-; RV32IFD-NEXT:    or a0, a1, a0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmps_one:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    flt.d a0, fa0, fa1
-; RV64IFD-NEXT:    flt.d a1, fa1, fa0
-; RV64IFD-NEXT:    or a0, a1, a0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmps_one:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    flt.d a0, fa0, fa1
+; CHECKIFD-NEXT:    flt.d a1, fa1, fa0
+; CHECKIFD-NEXT:    or a0, a1, a0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"one", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ord(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_ord:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fle.d a0, fa1, fa1
-; RV32IFD-NEXT:    fle.d a1, fa0, fa0
-; RV32IFD-NEXT:    and a0, a1, a0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmps_ord:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fle.d a0, fa1, fa1
-; RV64IFD-NEXT:    fle.d a1, fa0, fa0
-; RV64IFD-NEXT:    and a0, a1, a0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmps_ord:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fle.d a0, fa1, fa1
+; CHECKIFD-NEXT:    fle.d a1, fa0, fa0
+; CHECKIFD-NEXT:    and a0, a1, a0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ord:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unorddf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"ord", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ueq(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_ueq:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    flt.d a0, fa0, fa1
-; RV32IFD-NEXT:    flt.d a1, fa1, fa0
-; RV32IFD-NEXT:    or a0, a1, a0
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmps_ueq:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    flt.d a0, fa0, fa1
-; RV64IFD-NEXT:    flt.d a1, fa1, fa0
-; RV64IFD-NEXT:    or a0, a1, a0
-; RV64IFD-NEXT:    xori a0, a0, 1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmps_ueq:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    flt.d a0, fa0, fa1
+; CHECKIFD-NEXT:    flt.d a1, fa1, fa0
+; CHECKIFD-NEXT:    or a0, a1, a0
+; CHECKIFD-NEXT:    xori a0, a0, 1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ueq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ugt(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_ugt:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fle.d a0, fa0, fa1
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmps_ugt:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fle.d a0, fa0, fa1
-; RV64IFD-NEXT:    xori a0, a0, 1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmps_ugt:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fle.d a0, fa0, fa1
+; CHECKIFD-NEXT:    xori a0, a0, 1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ledf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_uge(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_uge:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    flt.d a0, fa0, fa1
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmps_uge:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    flt.d a0, fa0, fa1
-; RV64IFD-NEXT:    xori a0, a0, 1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmps_uge:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    flt.d a0, fa0, fa1
+; CHECKIFD-NEXT:    xori a0, a0, 1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltdf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ult(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_ult:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fle.d a0, fa1, fa0
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmps_ult:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fle.d a0, fa1, fa0
-; RV64IFD-NEXT:    xori a0, a0, 1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmps_ult:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fle.d a0, fa1, fa0
+; CHECKIFD-NEXT:    xori a0, a0, 1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ult:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"ult", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ule(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_ule:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    flt.d a0, fa1, fa0
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmps_ule:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    flt.d a0, fa1, fa0
-; RV64IFD-NEXT:    xori a0, a0, 1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmps_ule:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    flt.d a0, fa1, fa0
+; CHECKIFD-NEXT:    xori a0, a0, 1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"ule", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_une(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_une:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fle.d a0, fa1, fa0
-; RV32IFD-NEXT:    fle.d a1, fa0, fa1
-; RV32IFD-NEXT:    and a0, a1, a0
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmps_une:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fle.d a0, fa1, fa0
-; RV64IFD-NEXT:    fle.d a1, fa0, fa1
-; RV64IFD-NEXT:    and a0, a1, a0
-; RV64IFD-NEXT:    xori a0, a0, 1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmps_une:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fle.d a0, fa1, fa0
+; CHECKIFD-NEXT:    fle.d a1, fa0, fa1
+; CHECKIFD-NEXT:    and a0, a1, a0
+; CHECKIFD-NEXT:    xori a0, a0, 1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_une:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __nedf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f64(double %a, double %b, metadata !"une", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_uno(double %a, double %b) nounwind strictfp {
-; RV32IFD-LABEL: fcmps_uno:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fle.d a0, fa1, fa1
-; RV32IFD-NEXT:    fle.d a1, fa0, fa0
-; RV32IFD-NEXT:    and a0, a1, a0
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmps_uno:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fle.d a0, fa1, fa1
-; RV64IFD-NEXT:    fle.d a1, fa0, fa0
-; RV64IFD-NEXT:    and a0, a1, a0
-; RV64IFD-NEXT:    xori a0, a0, 1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fcmps_uno:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fle.d a0, fa1, fa1
+; CHECKIFD-NEXT:    fle.d a1, fa0, fa0
+; CHECKIFD-NEXT:    and a0, a1, a0
+; CHECKIFD-NEXT:    xori a0, a0, 1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_uno:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unorddf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

llvm/test/CodeGen/RISCV/double-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32d | FileCheck -check-prefix=RV32IFD %s
+; RUN:   -target-abi=ilp32d | FileCheck -check-prefix=CHECKIFD %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64d | FileCheck -check-prefix=RV64IFD %s
+; RUN:   -target-abi=lp64d | FileCheck -check-prefix=CHECKIFD %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 define i32 @fcmp_false(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_false:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_false:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
+;CHECKIFD-LABEL: fcmp_false:
+;CHECKIFD:       # %bb.0:
+;CHECKIFD-NEXT:    li a0, 0
+;CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_false:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a0, 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_false:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 0
 ; RV64I-NEXT:    ret
   %1 = fcmp false double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oeq(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_oeq:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_oeq:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa0, fa1
-; RV64IFD-NEXT:    ret
+;CHECKIFD-LABEL: fcmp_oeq:
+;CHECKIFD:       # %bb.0:
+;CHECKIFD-NEXT:    feq.d a0, fa0, fa1
+;CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oeq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __eqdf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp oeq double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ogt(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_ogt:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    flt.d a0, fa1, fa0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_ogt:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    flt.d a0, fa1, fa0
-; RV64IFD-NEXT:    ret
+;CHECKIFD-LABEL: fcmp_ogt:
+;CHECKIFD:       # %bb.0:
+;CHECKIFD-NEXT:    flt.d a0, fa1, fa0
+;CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ogt double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oge(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_oge:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fle.d a0, fa1, fa0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_oge:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fle.d a0, fa1, fa0
-; RV64IFD-NEXT:    ret
+;CHECKIFD-LABEL: fcmp_oge:
+;CHECKIFD:       # %bb.0:
+;CHECKIFD-NEXT:    fle.d a0, fa1, fa0
+;CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp oge double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_olt(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_olt:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    flt.d a0, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_olt:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    flt.d a0, fa0, fa1
-; RV64IFD-NEXT:    ret
+;CHECKIFD-LABEL: fcmp_olt:
+;CHECKIFD:       # %bb.0:
+;CHECKIFD-NEXT:    flt.d a0, fa0, fa1
+;CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_olt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltdf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp olt double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ole(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_ole:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fle.d a0, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_ole:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fle.d a0, fa0, fa1
-; RV64IFD-NEXT:    ret
+;CHECKIFD-LABEL: fcmp_ole:
+;CHECKIFD:       # %bb.0:
+;CHECKIFD-NEXT:    fle.d a0, fa0, fa1
+;CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ole:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ledf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ole double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_one(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_one:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    flt.d a0, fa0, fa1
-; RV32IFD-NEXT:    flt.d a1, fa1, fa0
-; RV32IFD-NEXT:    or a0, a1, a0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_one:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    flt.d a0, fa0, fa1
-; RV64IFD-NEXT:    flt.d a1, fa1, fa0
-; RV64IFD-NEXT:    or a0, a1, a0
-; RV64IFD-NEXT:    ret
+;CHECKIFD-LABEL: fcmp_one:
+;CHECKIFD:       # %bb.0:
+;CHECKIFD-NEXT:    flt.d a0, fa0, fa1
+;CHECKIFD-NEXT:    flt.d a1, fa1, fa0
+;CHECKIFD-NEXT:    or a0, a1, a0
+;CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = fcmp one double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ord(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_ord:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa1, fa1
-; RV32IFD-NEXT:    feq.d a1, fa0, fa0
-; RV32IFD-NEXT:    and a0, a1, a0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_ord:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa1, fa1
-; RV64IFD-NEXT:    feq.d a1, fa0, fa0
-; RV64IFD-NEXT:    and a0, a1, a0
-; RV64IFD-NEXT:    ret
+;CHECKIFD-LABEL: fcmp_ord:
+;CHECKIFD:       # %bb.0:
+;CHECKIFD-NEXT:    feq.d a0, fa1, fa1
+;CHECKIFD-NEXT:    feq.d a1, fa0, fa0
+;CHECKIFD-NEXT:    and a0, a1, a0
+;CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ord:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unorddf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ord double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ueq(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_ueq:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    flt.d a0, fa0, fa1
-; RV32IFD-NEXT:    flt.d a1, fa1, fa0
-; RV32IFD-NEXT:    or a0, a1, a0
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_ueq:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    flt.d a0, fa0, fa1
-; RV64IFD-NEXT:    flt.d a1, fa1, fa0
-; RV64IFD-NEXT:    or a0, a1, a0
-; RV64IFD-NEXT:    xori a0, a0, 1
-; RV64IFD-NEXT:    ret
+;CHECKIFD-LABEL: fcmp_ueq:
+;CHECKIFD:       # %bb.0:
+;CHECKIFD-NEXT:    flt.d a0, fa0, fa1
+;CHECKIFD-NEXT:    flt.d a1, fa1, fa0
+;CHECKIFD-NEXT:    or a0, a1, a0
+;CHECKIFD-NEXT:    xori a0, a0, 1
+;CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ueq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = fcmp ueq double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ugt(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_ugt:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fle.d a0, fa0, fa1
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_ugt:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fle.d a0, fa0, fa1
-; RV64IFD-NEXT:    xori a0, a0, 1
-; RV64IFD-NEXT:    ret
+;CHECKIFD-LABEL: fcmp_ugt:
+;CHECKIFD:       # %bb.0:
+;CHECKIFD-NEXT:    fle.d a0, fa0, fa1
+;CHECKIFD-NEXT:    xori a0, a0, 1
+;CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ledf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ugt double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uge(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_uge:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    flt.d a0, fa0, fa1
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_uge:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    flt.d a0, fa0, fa1
-; RV64IFD-NEXT:    xori a0, a0, 1
-; RV64IFD-NEXT:    ret
+;CHECKIFD-LABEL: fcmp_uge:
+;CHECKIFD:       # %bb.0:
+;CHECKIFD-NEXT:    flt.d a0, fa0, fa1
+;CHECKIFD-NEXT:    xori a0, a0, 1
+;CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltdf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp uge double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ult(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_ult:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fle.d a0, fa1, fa0
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_ult:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fle.d a0, fa1, fa0
-; RV64IFD-NEXT:    xori a0, a0, 1
-; RV64IFD-NEXT:    ret
+;CHECKIFD-LABEL: fcmp_ult:
+;CHECKIFD:       # %bb.0:
+;CHECKIFD-NEXT:    fle.d a0, fa1, fa0
+;CHECKIFD-NEXT:    xori a0, a0, 1
+;CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ult:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ult double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ule(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_ule:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    flt.d a0, fa1, fa0
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_ule:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    flt.d a0, fa1, fa0
-; RV64IFD-NEXT:    xori a0, a0, 1
-; RV64IFD-NEXT:    ret
+;CHECKIFD-LABEL: fcmp_ule:
+;CHECKIFD:       # %bb.0:
+;CHECKIFD-NEXT:    flt.d a0, fa1, fa0
+;CHECKIFD-NEXT:    xori a0, a0, 1
+;CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ule double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_une(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_une:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa0, fa1
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_une:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa0, fa1
-; RV64IFD-NEXT:    xori a0, a0, 1
-; RV64IFD-NEXT:    ret
+;CHECKIFD-LABEL: fcmp_une:
+;CHECKIFD:       # %bb.0:
+;CHECKIFD-NEXT:    feq.d a0, fa0, fa1
+;CHECKIFD-NEXT:    xori a0, a0, 1
+;CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_une:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __nedf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp une double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uno(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_uno:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa1, fa1
-; RV32IFD-NEXT:    feq.d a1, fa0, fa0
-; RV32IFD-NEXT:    and a0, a1, a0
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_uno:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa1, fa1
-; RV64IFD-NEXT:    feq.d a1, fa0, fa0
-; RV64IFD-NEXT:    and a0, a1, a0
-; RV64IFD-NEXT:    xori a0, a0, 1
-; RV64IFD-NEXT:    ret
+;CHECKIFD-LABEL: fcmp_uno:
+;CHECKIFD:       # %bb.0:
+;CHECKIFD-NEXT:    feq.d a0, fa1, fa1
+;CHECKIFD-NEXT:    feq.d a1, fa0, fa0
+;CHECKIFD-NEXT:    and a0, a1, a0
+;CHECKIFD-NEXT:    xori a0, a0, 1
+;CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uno:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unorddf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp uno double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_true(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fcmp_true:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    li a0, 1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fcmp_true:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    li a0, 1
-; RV64IFD-NEXT:    ret
+;CHECKIFD-LABEL: fcmp_true:
+;CHECKIFD:       # %bb.0:
+;CHECKIFD-NEXT:    li a0, 1
+;CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_true:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_true:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 1
 ; RV64I-NEXT:    ret
   %1 = fcmp true double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/double-imm.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32d | FileCheck -check-prefix=RV32IFD %s
+; RUN:   -target-abi=ilp32d | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64d | FileCheck -check-prefix=RV64IFD %s
+; RUN:   -target-abi=lp64d | FileCheck %s
 
 define double @double_imm() nounwind {
-; RV32IFD-LABEL: double_imm:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    lui a0, %hi(.LCPI0_0)
-; RV32IFD-NEXT:    fld fa0, %lo(.LCPI0_0)(a0)
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: double_imm:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    lui a0, %hi(.LCPI0_0)
-; RV64IFD-NEXT:    fld fa0, %lo(.LCPI0_0)(a0)
-; RV64IFD-NEXT:    ret
+; CHECK-LABEL: double_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI0_0)
+; CHECK-NEXT:    fld fa0, %lo(.LCPI0_0)(a0)
+; CHECK-NEXT:    ret
   ret double 3.1415926535897931159979634685441851615905761718750
 }
 
 define double @double_imm_op(double %a) nounwind {
-; RV32IFD-LABEL: double_imm_op:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV32IFD-NEXT:    fld ft0, %lo(.LCPI1_0)(a0)
-; RV32IFD-NEXT:    fadd.d fa0, fa0, ft0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: double_imm_op:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV64IFD-NEXT:    fld ft0, %lo(.LCPI1_0)(a0)
-; RV64IFD-NEXT:    fadd.d fa0, fa0, ft0
-; RV64IFD-NEXT:    ret
+; CHECK-LABEL: double_imm_op:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI1_0)
+; CHECK-NEXT:    fld ft0, %lo(.LCPI1_0)(a0)
+; CHECK-NEXT:    fadd.d fa0, fa0, ft0
+; CHECK-NEXT:    ret
   %1 = fadd double %a, 1.0
   ret double %1
 }

llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
 ; RUN:   -verify-machineinstrs -disable-strictnode-mutation -target-abi=ilp32d \
-; RUN:   | FileCheck -check-prefix=RV32IFD %s
+; RUN:   | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
 ; RUN:   -verify-machineinstrs -disable-strictnode-mutation -target-abi=lp64d \
-; RUN:   | FileCheck -check-prefix=RV64IFD %s
+; RUN:   | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
 ; RUN:   -verify-machineinstrs -disable-strictnode-mutation \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
 ; RUN:   -verify-machineinstrs -disable-strictnode-mutation \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 declare double @llvm.experimental.constrained.sqrt.f64(double, metadata, metadata)
 
 define double @sqrt_f64(double %a) nounwind strictfp {
-; RV32IFD-LABEL: sqrt_f64:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fsqrt.d fa0, fa0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: sqrt_f64:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fsqrt.d fa0, fa0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: sqrt_f64:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fsqrt.d fa0, fa0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: sqrt_f64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call sqrt@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call double @llvm.experimental.constrained.log2.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret double %1
 }
 
 declare double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata)
 
 define double @fma_f64(double %a, double %b, double %c) nounwind strictfp {
-; RV32IFD-LABEL: fma_f64:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fmadd.d fa0, fa0, fa1, fa2
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fma_f64:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fmadd.d fa0, fa0, fa1, fa2
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fma_f64:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fmadd.d fa0, fa0, fa1, fa2
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fma_f64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fma@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call double @llvm.experimental.constrained.fma.f64(double %a, double %b, double %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret double %1
 }
 
 declare double @llvm.experimental.constrained.fmuladd.f64(double, double, double, metadata, metadata)
 
 define double @fmuladd_f64(double %a, double %b, double %c) nounwind strictfp {
-; RV32IFD-LABEL: fmuladd_f64:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fmadd.d fa0, fa0, fa1, fa2
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fmuladd_f64:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fmadd.d fa0, fa0, fa1, fa2
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fmuladd_f64:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fmadd.d fa0, fa0, fa1, fa2
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fmuladd_f64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a5

llvm/test/CodeGen/RISCV/double-intrinsics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
 ; RUN:   -verify-machineinstrs -target-abi=ilp32d \
-; RUN:   | FileCheck -check-prefix=RV32IFD %s
+; RUN:   | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
 ; RUN:   -verify-machineinstrs -target-abi=lp64d \
-; RUN:   | FileCheck -check-prefix=RV64IFD %s
+; RUN:   | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
 ; RUN:   -verify-machineinstrs | FileCheck -check-prefix=RV32I %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
 ; RUN:   -verify-machineinstrs | FileCheck -check-prefix=RV64I %s
 
 declare double @llvm.sqrt.f64(double)
 
 define double @sqrt_f64(double %a) nounwind {
-; RV32IFD-LABEL: sqrt_f64:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fsqrt.d fa0, fa0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: sqrt_f64:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fsqrt.d fa0, fa0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: sqrt_f64:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fsqrt.d fa0, fa0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: sqrt_f64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call sqrt@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call double @llvm.log2.f64(double %a)
   ret double %1
 }
 
 declare double @llvm.fma.f64(double, double, double)
 
 define double @fma_f64(double %a, double %b, double %c) nounwind {
-; RV32IFD-LABEL: fma_f64:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fmadd.d fa0, fa0, fa1, fa2
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fma_f64:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fmadd.d fa0, fa0, fa1, fa2
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fma_f64:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fmadd.d fa0, fa0, fa1, fa2
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fma_f64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fma@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call double @llvm.fma.f64(double %a, double %b, double %c)
   ret double %1
 }
 
 declare double @llvm.fmuladd.f64(double, double, double)
 
 define double @fmuladd_f64(double %a, double %b, double %c) nounwind {
-; RV32IFD-LABEL: fmuladd_f64:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fmadd.d fa0, fa0, fa1, fa2
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fmuladd_f64:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fmadd.d fa0, fa0, fa1, fa2
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fmuladd_f64:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fmadd.d fa0, fa0, fa1, fa2
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fmuladd_f64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a5

 ; RV64I-NEXT:    ret
   %1 = call double @llvm.fmuladd.f64(double %a, double %b, double %c)
   ret double %1
 }
 
 declare double @llvm.fabs.f64(double)
 
 define double @fabs_f64(double %a) nounwind {
-; RV32IFD-LABEL: fabs_f64:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fabs.d fa0, fa0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fabs_f64:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fabs.d fa0, fa0
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fabs_f64:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fabs.d fa0, fa0
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fabs_f64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a1, a1, 1
 ; RV32I-NEXT:    srli a1, a1, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fabs_f64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a0, a0, 1
 ; RV64I-NEXT:    srli a0, a0, 1
 ; RV64I-NEXT:    ret
   %1 = call double @llvm.fabs.f64(double %a)
   ret double %1
 }
 
 declare double @llvm.minnum.f64(double, double)
 
 define double @minnum_f64(double %a, double %b) nounwind {
-; RV32IFD-LABEL: minnum_f64:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fmin.d fa0, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: minnum_f64:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fmin.d fa0, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: minnum_f64:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fmin.d fa0, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: minnum_f64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fmin@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call double @llvm.minnum.f64(double %a, double %b)
   ret double %1
 }
 
 declare double @llvm.maxnum.f64(double, double)
 
 define double @maxnum_f64(double %a, double %b) nounwind {
-; RV32IFD-LABEL: maxnum_f64:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fmax.d fa0, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: maxnum_f64:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fmax.d fa0, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: maxnum_f64:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fmax.d fa0, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: maxnum_f64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fmax@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; define double @fmaximum_f64(double %a, double %b) nounwind {
 ;   %1 = call double @llvm.maximum.f64(double %a, double %b)
 ;   ret double %1
 ; }
 
 declare double @llvm.copysign.f64(double, double)
 
 define double @copysign_f64(double %a, double %b) nounwind {
-; RV32IFD-LABEL: copysign_f64:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fsgnj.d fa0, fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: copysign_f64:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fsgnj.d fa0, fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: copysign_f64:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fsgnj.d fa0, fa0, fa1
+; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: copysign_f64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a2, 524288
 ; RV32I-NEXT:    and a2, a3, a2
 ; RV32I-NEXT:    slli a1, a1, 1
 ; RV32I-NEXT:    srli a1, a1, 1
 ; RV32I-NEXT:    or a1, a1, a2

llvm/test/CodeGen/RISCV/double-isnan.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs \
-; RUN:   < %s | FileCheck -check-prefix=RV32IFD %s
+; RUN:   < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs \
-; RUN:   < %s | FileCheck -check-prefix=RV64IFD %s
+; RUN:   < %s | FileCheck %s
 
 define zeroext i1 @double_is_nan(double %a) nounwind {
-; RV32IFD-LABEL: double_is_nan:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    xori a0, a0, 1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: double_is_nan:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    xori a0, a0, 1
-; RV64IFD-NEXT:    ret
+; CHECK-LABEL: double_is_nan:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.d a0, fa0, fa0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
   %1 = fcmp uno double %a, 0.000000e+00
   ret i1 %1
 }
 
 define zeroext i1 @double_not_nan(double %a) nounwind {
-; RV32IFD-LABEL: double_not_nan:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: double_not_nan:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    ret
+; CHECK-LABEL: double_not_nan:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.d a0, fa0, fa0
+; CHECK-NEXT:    ret
   %1 = fcmp ord double %a, 0.000000e+00
   ret i1 %1
 }

llvm/test/CodeGen/RISCV/double-mem.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32d | FileCheck -check-prefix=RV32IFD %s
+; RUN:   -target-abi=ilp32d | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64d | FileCheck -check-prefix=RV64IFD %s
+; RUN:   -target-abi=lp64d | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
 
 define dso_local double @fld(double *%a) nounwind {
-; RV32IFD-LABEL: fld:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fld ft0, 0(a0)
-; RV32IFD-NEXT:    fld ft1, 24(a0)
-; RV32IFD-NEXT:    fadd.d fa0, ft0, ft1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fld:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fld ft0, 0(a0)
-; RV64IFD-NEXT:    fld ft1, 24(a0)
-; RV64IFD-NEXT:    fadd.d fa0, ft0, ft1
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fld:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fld ft0, 0(a0)
+; CHECKIFD-NEXT:    fld ft1, 24(a0)
+; CHECKIFD-NEXT:    fadd.d fa0, ft0, ft1
+; CHECKIFD-NEXT:    ret
   %1 = load double, double* %a
   %2 = getelementptr double, double* %a, i32 3
   %3 = load double, double* %2
 ; Use both loaded values in an FP op to ensure an fld is used, even for the
 ; soft float ABI
   %4 = fadd double %1, %3
   ret double %4
 }
 
 define dso_local void @fsd(double *%a, double %b, double %c) nounwind {
-; RV32IFD-LABEL: fsd:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fadd.d ft0, fa0, fa1
-; RV32IFD-NEXT:    fsd ft0, 0(a0)
-; RV32IFD-NEXT:    fsd ft0, 64(a0)
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fsd:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fadd.d ft0, fa0, fa1
-; RV64IFD-NEXT:    fsd ft0, 0(a0)
-; RV64IFD-NEXT:    fsd ft0, 64(a0)
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fsd:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fadd.d ft0, fa0, fa1
+; CHECKIFD-NEXT:    fsd ft0, 0(a0)
+; CHECKIFD-NEXT:    fsd ft0, 64(a0)
+; CHECKIFD-NEXT:    ret
 ; Use %b and %c in an FP op to ensure floating point registers are used, even
 ; for the soft float ABI
   %1 = fadd double %b, %c
   store double %1, double* %a
   %2 = getelementptr double, double* %a, i32 8
   store double %1, double* %2
   ret void
 }
 
 ; Check load and store to a global
 @G = dso_local global double 0.0
 
 define dso_local double @fld_fsd_global(double %a, double %b) nounwind {
-; RV32IFD-LABEL: fld_fsd_global:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fadd.d fa0, fa0, fa1
-; RV32IFD-NEXT:    lui a0, %hi(G)
-; RV32IFD-NEXT:    fld ft0, %lo(G)(a0)
-; RV32IFD-NEXT:    addi a1, a0, %lo(G)
-; RV32IFD-NEXT:    fsd fa0, %lo(G)(a0)
-; RV32IFD-NEXT:    fld ft0, 72(a1)
-; RV32IFD-NEXT:    fsd fa0, 72(a1)
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fld_fsd_global:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fadd.d fa0, fa0, fa1
-; RV64IFD-NEXT:    lui a0, %hi(G)
-; RV64IFD-NEXT:    fld ft0, %lo(G)(a0)
-; RV64IFD-NEXT:    addi a1, a0, %lo(G)
-; RV64IFD-NEXT:    fsd fa0, %lo(G)(a0)
-; RV64IFD-NEXT:    fld ft0, 72(a1)
-; RV64IFD-NEXT:    fsd fa0, 72(a1)
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fld_fsd_global:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fadd.d fa0, fa0, fa1
+; CHECKIFD-NEXT:    lui a0, %hi(G)
+; CHECKIFD-NEXT:    fld ft0, %lo(G)(a0)
+; CHECKIFD-NEXT:    addi a1, a0, %lo(G)
+; CHECKIFD-NEXT:    fsd fa0, %lo(G)(a0)
+; CHECKIFD-NEXT:    fld ft0, 72(a1)
+; CHECKIFD-NEXT:    fsd fa0, 72(a1)
+; CHECKIFD-NEXT:    ret
 ; Use %a and %b in an FP op to ensure floating point registers are used, even
 ; for the soft float ABI
   %1 = fadd double %a, %b
   %2 = load volatile double, double* @G
   store double %1, double* @G
   %3 = getelementptr double, double* @G, i32 9
   %4 = load volatile double, double* %3
   store double %1, double* %3
; RV64IFD-NEXT:    ret
   store double %1, double* %2
   %3 = bitcast double* %2 to i8*
   call void @notdead(i8* %3)
   ret void
 }
 
 ; Test selection of store<ST4[%a], trunc to f32>, ..
 define dso_local void @fsd_trunc(float* %a, double %b) nounwind noinline optnone {
-; RV32IFD-LABEL: fsd_trunc:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.s.d ft0, fa0
-; RV32IFD-NEXT:    fsw ft0, 0(a0)
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: fsd_trunc:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.s.d ft0, fa0
-; RV64IFD-NEXT:    fsw ft0, 0(a0)
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: fsd_trunc:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.s.d ft0, fa0
+; CHECKIFD-NEXT:    fsw ft0, 0(a0)
+; CHECKIFD-NEXT:    ret
   %1 = fptrunc double %b to float
   store float %1, float* %a, align 4
   ret void
 }

llvm/test/CodeGen/RISCV/double-round-conv-sat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32d | FileCheck -check-prefix=RV32IFD %s
+; RUN:   -target-abi=ilp32d | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64d | FileCheck -check-prefix=RV64IFD %s
+; RUN:   -target-abi=lp64d | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
 
 define signext i32 @test_floor_si32(double %x) {
-; RV32IFD-LABEL: test_floor_si32:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    beqz a0, .LBB0_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rdn
-; RV32IFD-NEXT:  .LBB0_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: test_floor_si32:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    beqz a0, .LBB0_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rdn
-; RV64IFD-NEXT:  .LBB0_2:
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: test_floor_si32:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    feq.d a0, fa0, fa0
+; CHECKIFD-NEXT:    beqz a0, .LBB0_2
+; CHECKIFD-NEXT:  # %bb.1:
+; CHECKIFD-NEXT:    fcvt.w.d a0, fa0, rdn
+; CHECKIFD-NEXT:  .LBB0_2:
+; CHECKIFD-NEXT:    ret
   %a = call double @llvm.floor.f64(double %x)
   %b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
   ret i32 %b
 }
 
 define i64 @test_floor_si64(double %x) nounwind {
 ; RV32IFD-LABEL: test_floor_si64:
 ; RV32IFD:       # %bb.0:

 ; RV64IFD-NEXT:  .LBB1_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.floor.f64(double %x)
   %b = call i64 @llvm.fptosi.sat.i64.f64(double %a)
   ret i64 %b
 }
 
 define signext i32 @test_floor_ui32(double %x) {
-; RV32IFD-LABEL: test_floor_ui32:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    beqz a0, .LBB2_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rdn
-; RV32IFD-NEXT:  .LBB2_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: test_floor_ui32:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    beqz a0, .LBB2_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rdn
-; RV64IFD-NEXT:  .LBB2_2:
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: test_floor_ui32:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    feq.d a0, fa0, fa0
+; CHECKIFD-NEXT:    beqz a0, .LBB2_2
+; CHECKIFD-NEXT:  # %bb.1:
+; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rdn
+; CHECKIFD-NEXT:  .LBB2_2:
+; CHECKIFD-NEXT:    ret
   %a = call double @llvm.floor.f64(double %x)
   %b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
   ret i32 %b
 }
 
 define i64 @test_floor_ui64(double %x) nounwind {
 ; RV32IFD-LABEL: test_floor_ui64:
 ; RV32IFD:       # %bb.0:

 ; RV64IFD-NEXT:  .LBB3_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.floor.f64(double %x)
   %b = call i64 @llvm.fptoui.sat.i64.f64(double %a)
   ret i64 %b
 }
 
 define signext i32 @test_ceil_si32(double %x) {
-; RV32IFD-LABEL: test_ceil_si32:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    beqz a0, .LBB4_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rup
-; RV32IFD-NEXT:  .LBB4_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: test_ceil_si32:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    beqz a0, .LBB4_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rup
-; RV64IFD-NEXT:  .LBB4_2:
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: test_ceil_si32:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    feq.d a0, fa0, fa0
+; CHECKIFD-NEXT:    beqz a0, .LBB4_2
+; CHECKIFD-NEXT:  # %bb.1:
+; CHECKIFD-NEXT:    fcvt.w.d a0, fa0, rup
+; CHECKIFD-NEXT:  .LBB4_2:
+; CHECKIFD-NEXT:    ret
   %a = call double @llvm.ceil.f64(double %x)
   %b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
   ret i32 %b
 }
 
 define i64 @test_ceil_si64(double %x) nounwind {
 ; RV32IFD-LABEL: test_ceil_si64:
 ; RV32IFD:       # %bb.0:

 ; RV64IFD-NEXT:  .LBB5_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.ceil.f64(double %x)
   %b = call i64 @llvm.fptosi.sat.i64.f64(double %a)
   ret i64 %b
 }
 
 define signext i32 @test_ceil_ui32(double %x) {
-; RV32IFD-LABEL: test_ceil_ui32:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    beqz a0, .LBB6_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rup
-; RV32IFD-NEXT:  .LBB6_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: test_ceil_ui32:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    beqz a0, .LBB6_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rup
-; RV64IFD-NEXT:  .LBB6_2:
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: test_ceil_ui32:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    feq.d a0, fa0, fa0
+; CHECKIFD-NEXT:    beqz a0, .LBB6_2
+; CHECKIFD-NEXT:  # %bb.1:
+; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rup
+; CHECKIFD-NEXT:  .LBB6_2:
+; CHECKIFD-NEXT:    ret
   %a = call double @llvm.ceil.f64(double %x)
   %b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
   ret i32 %b
 }
 
 define i64 @test_ceil_ui64(double %x) nounwind {
 ; RV32IFD-LABEL: test_ceil_ui64:
 ; RV32IFD:       # %bb.0:

 ; RV64IFD-NEXT:  .LBB7_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.ceil.f64(double %x)
   %b = call i64 @llvm.fptoui.sat.i64.f64(double %a)
   ret i64 %b
 }
 
 define signext i32 @test_trunc_si32(double %x) {
-; RV32IFD-LABEL: test_trunc_si32:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    beqz a0, .LBB8_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rtz
-; RV32IFD-NEXT:  .LBB8_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: test_trunc_si32:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    beqz a0, .LBB8_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rtz
-; RV64IFD-NEXT:  .LBB8_2:
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: test_trunc_si32:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    feq.d a0, fa0, fa0
+; CHECKIFD-NEXT:    beqz a0, .LBB8_2
+; CHECKIFD-NEXT:  # %bb.1:
+; CHECKIFD-NEXT:    fcvt.w.d a0, fa0, rtz
+; CHECKIFD-NEXT:  .LBB8_2:
+; CHECKIFD-NEXT:    ret
   %a = call double @llvm.trunc.f64(double %x)
   %b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
   ret i32 %b
 }
 
 define i64 @test_trunc_si64(double %x) nounwind {
 ; RV32IFD-LABEL: test_trunc_si64:
 ; RV32IFD:       # %bb.0:

 ; RV64IFD-NEXT:  .LBB9_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.trunc.f64(double %x)
   %b = call i64 @llvm.fptosi.sat.i64.f64(double %a)
   ret i64 %b
 }
 
 define signext i32 @test_trunc_ui32(double %x) {
-; RV32IFD-LABEL: test_trunc_ui32:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    beqz a0, .LBB10_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
-; RV32IFD-NEXT:  .LBB10_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: test_trunc_ui32:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    beqz a0, .LBB10_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
-; RV64IFD-NEXT:  .LBB10_2:
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: test_trunc_ui32:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    feq.d a0, fa0, fa0
+; CHECKIFD-NEXT:    beqz a0, .LBB10_2
+; CHECKIFD-NEXT:  # %bb.1:
+; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rtz
+; CHECKIFD-NEXT:  .LBB10_2:
+; CHECKIFD-NEXT:    ret
   %a = call double @llvm.trunc.f64(double %x)
   %b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
   ret i32 %b
 }
 
 define i64 @test_trunc_ui64(double %x) nounwind {
 ; RV32IFD-LABEL: test_trunc_ui64:
 ; RV32IFD:       # %bb.0:

 ; RV64IFD-NEXT:  .LBB11_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.trunc.f64(double %x)
   %b = call i64 @llvm.fptoui.sat.i64.f64(double %a)
   ret i64 %b
 }
 
 define signext i32 @test_round_si32(double %x) {
-; RV32IFD-LABEL: test_round_si32:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    beqz a0, .LBB12_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rmm
-; RV32IFD-NEXT:  .LBB12_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: test_round_si32:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    beqz a0, .LBB12_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rmm
-; RV64IFD-NEXT:  .LBB12_2:
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: test_round_si32:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    feq.d a0, fa0, fa0
+; CHECKIFD-NEXT:    beqz a0, .LBB12_2
+; CHECKIFD-NEXT:  # %bb.1:
+; CHECKIFD-NEXT:    fcvt.w.d a0, fa0, rmm
+; CHECKIFD-NEXT:  .LBB12_2:
+; CHECKIFD-NEXT:    ret
   %a = call double @llvm.round.f64(double %x)
   %b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
   ret i32 %b
 }
 
 define i64 @test_round_si64(double %x) nounwind {
 ; RV32IFD-LABEL: test_round_si64:
 ; RV32IFD:       # %bb.0:

 ; RV64IFD-NEXT:  .LBB13_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.round.f64(double %x)
   %b = call i64 @llvm.fptosi.sat.i64.f64(double %a)
   ret i64 %b
 }
 
 define signext i32 @test_round_ui32(double %x) {
-; RV32IFD-LABEL: test_round_ui32:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    beqz a0, .LBB14_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rmm
-; RV32IFD-NEXT:  .LBB14_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: test_round_ui32:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    beqz a0, .LBB14_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rmm
-; RV64IFD-NEXT:  .LBB14_2:
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: test_round_ui32:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    feq.d a0, fa0, fa0
+; CHECKIFD-NEXT:    beqz a0, .LBB14_2
+; CHECKIFD-NEXT:  # %bb.1:
+; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rmm
+; CHECKIFD-NEXT:  .LBB14_2:
+; CHECKIFD-NEXT:    ret
   %a = call double @llvm.round.f64(double %x)
   %b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
   ret i32 %b
 }
 
 define i64 @test_round_ui64(double %x) nounwind {
 ; RV32IFD-LABEL: test_round_ui64:
 ; RV32IFD:       # %bb.0:

 ; RV64IFD-NEXT:  .LBB15_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.round.f64(double %x)
   %b = call i64 @llvm.fptoui.sat.i64.f64(double %a)
   ret i64 %b
 }
 
 define signext i32 @test_roundeven_si32(double %x) {
-; RV32IFD-LABEL: test_roundeven_si32:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    beqz a0, .LBB16_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rne
-; RV32IFD-NEXT:  .LBB16_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: test_roundeven_si32:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    beqz a0, .LBB16_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rne
-; RV64IFD-NEXT:  .LBB16_2:
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: test_roundeven_si32:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    feq.d a0, fa0, fa0
+; CHECKIFD-NEXT:    beqz a0, .LBB16_2
+; CHECKIFD-NEXT:  # %bb.1:
+; CHECKIFD-NEXT:    fcvt.w.d a0, fa0, rne
+; CHECKIFD-NEXT:  .LBB16_2:
+; CHECKIFD-NEXT:    ret
   %a = call double @llvm.roundeven.f64(double %x)
   %b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
   ret i32 %b
 }
 
 define i64 @test_roundeven_si64(double %x) nounwind {
 ; RV32IFD-LABEL: test_roundeven_si64:
 ; RV32IFD:       # %bb.0:

 ; RV64IFD-NEXT:  .LBB17_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.roundeven.f64(double %x)
   %b = call i64 @llvm.fptosi.sat.i64.f64(double %a)
   ret i64 %b
 }
 
 define signext i32 @test_roundeven_ui32(double %x) {
-; RV32IFD-LABEL: test_roundeven_ui32:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    beqz a0, .LBB18_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rne
-; RV32IFD-NEXT:  .LBB18_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: test_roundeven_ui32:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    beqz a0, .LBB18_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rne
-; RV64IFD-NEXT:  .LBB18_2:
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: test_roundeven_ui32:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    feq.d a0, fa0, fa0
+; CHECKIFD-NEXT:    beqz a0, .LBB18_2
+; CHECKIFD-NEXT:  # %bb.1:
+; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rne
+; CHECKIFD-NEXT:  .LBB18_2:
+; CHECKIFD-NEXT:    ret
   %a = call double @llvm.roundeven.f64(double %x)
   %b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
   ret i32 %b
 }
 
 define i64 @test_roundeven_ui64(double %x) nounwind {
 ; RV32IFD-LABEL: test_roundeven_ui64:
 ; RV32IFD:       # %bb.0:

llvm/test/CodeGen/RISCV/double-round-conv.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32d | FileCheck -check-prefix=RV32IFD %s
+; RUN:   -target-abi=ilp32d | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64d | FileCheck -check-prefix=RV64IFD %s
+; RUN:   -target-abi=lp64d | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
 
 define signext i8 @test_floor_si8(double %x) {
 ; RV32IFD-LABEL: test_floor_si8:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rdn
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: test_floor_si8:

 ; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rdn
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.floor.f64(double %x)
   %b = fptosi double %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_floor_si32(double %x) {
-; RV32IFD-LABEL: test_floor_si32:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rdn
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: test_floor_si32:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rdn
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: test_floor_si32:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.w.d a0, fa0, rdn
+; CHECKIFD-NEXT:    ret
   %a = call double @llvm.floor.f64(double %x)
   %b = fptosi double %a to i32
   ret i32 %b
 }
 
 define i64 @test_floor_si64(double %x) {
 ; RV32IFD-LABEL: test_floor_si64:
 ; RV32IFD:       # %bb.0:

 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rdn
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.floor.f64(double %x)
   %b = fptoui double %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_floor_ui32(double %x) {
-; RV32IFD-LABEL: test_floor_ui32:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rdn
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: test_floor_ui32:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rdn
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: test_floor_ui32:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rdn
+; CHECKIFD-NEXT:    ret
   %a = call double @llvm.floor.f64(double %x)
   %b = fptoui double %a to i32
   ret i32 %b
 }
 
 define i64 @test_floor_ui64(double %x) {
 ; RV32IFD-LABEL: test_floor_ui64:
 ; RV32IFD:       # %bb.0:

 ; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rup
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.ceil.f64(double %x)
   %b = fptosi double %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_ceil_si32(double %x) {
-; RV32IFD-LABEL: test_ceil_si32:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rup
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: test_ceil_si32:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rup
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: test_ceil_si32:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.w.d a0, fa0, rup
+; CHECKIFD-NEXT:    ret
   %a = call double @llvm.ceil.f64(double %x)
   %b = fptosi double %a to i32
   ret i32 %b
 }
 
 define i64 @test_ceil_si64(double %x) {
 ; RV32IFD-LABEL: test_ceil_si64:
 ; RV32IFD:       # %bb.0:

 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rup
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.ceil.f64(double %x)
   %b = fptoui double %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_ceil_ui32(double %x) {
-; RV32IFD-LABEL: test_ceil_ui32:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rup
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: test_ceil_ui32:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rup
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: test_ceil_ui32:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rup
+; CHECKIFD-NEXT:    ret
   %a = call double @llvm.ceil.f64(double %x)
   %b = fptoui double %a to i32
   ret i32 %b
 }
 
 define i64 @test_ceil_ui64(double %x) {
 ; RV32IFD-LABEL: test_ceil_ui64:
 ; RV32IFD:       # %bb.0:

 ; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rtz
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.trunc.f64(double %x)
   %b = fptosi double %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_trunc_si32(double %x) {
-; RV32IFD-LABEL: test_trunc_si32:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rtz
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: test_trunc_si32:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rtz
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: test_trunc_si32:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.w.d a0, fa0, rtz
+; CHECKIFD-NEXT:    ret
   %a = call double @llvm.trunc.f64(double %x)
   %b = fptosi double %a to i32
   ret i32 %b
 }
 
 define i64 @test_trunc_si64(double %x) {
 ; RV32IFD-LABEL: test_trunc_si64:
 ; RV32IFD:       # %bb.0:

 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rtz
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.trunc.f64(double %x)
   %b = fptoui double %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_trunc_ui32(double %x) {
-; RV32IFD-LABEL: test_trunc_ui32:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: test_trunc_ui32:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: test_trunc_ui32:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rtz
+; CHECKIFD-NEXT:    ret
   %a = call double @llvm.trunc.f64(double %x)
   %b = fptoui double %a to i32
   ret i32 %b
 }
 
 define i64 @test_trunc_ui64(double %x) {
 ; RV32IFD-LABEL: test_trunc_ui64:
 ; RV32IFD:       # %bb.0:

 ; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rmm
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.round.f64(double %x)
   %b = fptosi double %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_round_si32(double %x) {
-; RV32IFD-LABEL: test_round_si32:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rmm
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: test_round_si32:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rmm
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: test_round_si32:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.w.d a0, fa0, rmm
+; CHECKIFD-NEXT:    ret
   %a = call double @llvm.round.f64(double %x)
   %b = fptosi double %a to i32
   ret i32 %b
 }
 
 define i64 @test_round_si64(double %x) {
 ; RV32IFD-LABEL: test_round_si64:
 ; RV32IFD:       # %bb.0:

 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rmm
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.round.f64(double %x)
   %b = fptoui double %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_round_ui32(double %x) {
-; RV32IFD-LABEL: test_round_ui32:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rmm
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: test_round_ui32:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rmm
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: test_round_ui32:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rmm
+; CHECKIFD-NEXT:    ret
   %a = call double @llvm.round.f64(double %x)
   %b = fptoui double %a to i32
   ret i32 %b
 }
 
 define i64 @test_round_ui64(double %x) {
 ; RV32IFD-LABEL: test_round_ui64:
 ; RV32IFD:       # %bb.0:

 ; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rne
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.roundeven.f64(double %x)
   %b = fptosi double %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_roundeven_si32(double %x) {
-; RV32IFD-LABEL: test_roundeven_si32:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rne
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: test_roundeven_si32:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rne
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: test_roundeven_si32:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.w.d a0, fa0, rne
+; CHECKIFD-NEXT:    ret
   %a = call double @llvm.roundeven.f64(double %x)
   %b = fptosi double %a to i32
   ret i32 %b
 }
 
 define i64 @test_roundeven_si64(double %x) {
 ; RV32IFD-LABEL: test_roundeven_si64:
 ; RV32IFD:       # %bb.0:

 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rne
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.roundeven.f64(double %x)
   %b = fptoui double %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_roundeven_ui32(double %x) {
-; RV32IFD-LABEL: test_roundeven_ui32:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rne
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: test_roundeven_ui32:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rne
-; RV64IFD-NEXT:    ret
+; CHECKIFD-LABEL: test_roundeven_ui32:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rne
+; CHECKIFD-NEXT:    ret
   %a = call double @llvm.roundeven.f64(double %x)
   %b = fptoui double %a to i32
   ret i32 %b
 }
 
 define i64 @test_roundeven_ui64(double %x) {
 ; RV32IFD-LABEL: test_roundeven_ui64:
 ; RV32IFD:       # %bb.0:

llvm/test/CodeGen/RISCV/double-select-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32d | FileCheck -check-prefix=RV32IFD %s
+; RUN:   -target-abi=ilp32d | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64d | FileCheck -check-prefix=RV64IFD %s
+; RUN:   -target-abi=lp64d | FileCheck %s
 
 define double @select_fcmp_false(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_false:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fmv.d fa0, fa1
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: select_fcmp_false:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fmv.d fa0, fa1
-; RV64IFD-NEXT:    ret
+; CHECK-LABEL: select_fcmp_false:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.d fa0, fa1
+; CHECK-NEXT:    ret
   %1 = fcmp false double %a, %b
   %2 = select i1 %1, double %a, double %b
   ret double %2
 }
 
 define double @select_fcmp_oeq(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_oeq:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa0, fa1
-; RV32IFD-NEXT:    bnez a0, .LBB1_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fmv.d fa0, fa1
-; RV32IFD-NEXT:  .LBB1_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: select_fcmp_oeq:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa0, fa1
-; RV64IFD-NEXT:    bnez a0, .LBB1_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fmv.d fa0, fa1
-; RV64IFD-NEXT:  .LBB1_2:
-; RV64IFD-NEXT:    ret
+; CHECK-LABEL: select_fcmp_oeq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.d a0, fa0, fa1
+; CHECK-NEXT:    bnez a0, .LBB1_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.d fa0, fa1
+; CHECK-NEXT:  .LBB1_2:
+; CHECK-NEXT:    ret
   %1 = fcmp oeq double %a, %b
   %2 = select i1 %1, double %a, double %b
   ret double %2
 }
 
 define double @select_fcmp_ogt(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_ogt:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    flt.d a0, fa1, fa0
-; RV32IFD-NEXT:    bnez a0, .LBB2_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fmv.d fa0, fa1
-; RV32IFD-NEXT:  .LBB2_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: select_fcmp_ogt:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    flt.d a0, fa1, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB2_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fmv.d fa0, fa1
-; RV64IFD-NEXT:  .LBB2_2:
-; RV64IFD-NEXT:    ret
+; CHECK-LABEL: select_fcmp_ogt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.d a0, fa1, fa0
+; CHECK-NEXT:    bnez a0, .LBB2_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.d fa0, fa1
+; CHECK-NEXT:  .LBB2_2:
+; CHECK-NEXT:    ret
   %1 = fcmp ogt double %a, %b
   %2 = select i1 %1, double %a, double %b
   ret double %2
 }
 
 define double @select_fcmp_oge(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_oge:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fle.d a0, fa1, fa0
-; RV32IFD-NEXT:    bnez a0, .LBB3_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fmv.d fa0, fa1
-; RV32IFD-NEXT:  .LBB3_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: select_fcmp_oge:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fle.d a0, fa1, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB3_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fmv.d fa0, fa1
-; RV64IFD-NEXT:  .LBB3_2:
-; RV64IFD-NEXT:    ret
+; CHECK-LABEL: select_fcmp_oge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.d a0, fa1, fa0
+; CHECK-NEXT:    bnez a0, .LBB3_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.d fa0, fa1
+; CHECK-NEXT:  .LBB3_2:
+; CHECK-NEXT:    ret
   %1 = fcmp oge double %a, %b
   %2 = select i1 %1, double %a, double %b
   ret double %2
 }
 
 define double @select_fcmp_olt(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_olt:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    flt.d a0, fa0, fa1
-; RV32IFD-NEXT:    bnez a0, .LBB4_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fmv.d fa0, fa1
-; RV32IFD-NEXT:  .LBB4_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: select_fcmp_olt:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    flt.d a0, fa0, fa1
-; RV64IFD-NEXT:    bnez a0, .LBB4_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fmv.d fa0, fa1
-; RV64IFD-NEXT:  .LBB4_2:
-; RV64IFD-NEXT:    ret
+; CHECK-LABEL: select_fcmp_olt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.d a0, fa0, fa1
+; CHECK-NEXT:    bnez a0, .LBB4_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.d fa0, fa1
+; CHECK-NEXT:  .LBB4_2:
+; CHECK-NEXT:    ret
   %1 = fcmp olt double %a, %b
   %2 = select i1 %1, double %a, double %b
   ret double %2
 }
 
 define double @select_fcmp_ole(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_ole:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fle.d a0, fa0, fa1
-; RV32IFD-NEXT:    bnez a0, .LBB5_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fmv.d fa0, fa1
-; RV32IFD-NEXT:  .LBB5_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: select_fcmp_ole:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fle.d a0, fa0, fa1
-; RV64IFD-NEXT:    bnez a0, .LBB5_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fmv.d fa0, fa1
-; RV64IFD-NEXT:  .LBB5_2:
-; RV64IFD-NEXT:    ret
+; CHECK-LABEL: select_fcmp_ole:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.d a0, fa0, fa1
+; CHECK-NEXT:    bnez a0, .LBB5_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.d fa0, fa1
+; CHECK-NEXT:  .LBB5_2:
+; CHECK-NEXT:    ret
   %1 = fcmp ole double %a, %b
   %2 = select i1 %1, double %a, double %b
   ret double %2
 }
 
 define double @select_fcmp_one(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_one:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    flt.d a0, fa0, fa1
-; RV32IFD-NEXT:    flt.d a1, fa1, fa0
-; RV32IFD-NEXT:    or a0, a1, a0
-; RV32IFD-NEXT:    bnez a0, .LBB6_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fmv.d fa0, fa1
-; RV32IFD-NEXT:  .LBB6_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: select_fcmp_one:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    flt.d a0, fa0, fa1
-; RV64IFD-NEXT:    flt.d a1, fa1, fa0
-; RV64IFD-NEXT:    or a0, a1, a0
-; RV64IFD-NEXT:    bnez a0, .LBB6_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fmv.d fa0, fa1
-; RV64IFD-NEXT:  .LBB6_2:
-; RV64IFD-NEXT:    ret
+; CHECK-LABEL: select_fcmp_one:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.d a0, fa0, fa1
+; CHECK-NEXT:    flt.d a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    bnez a0, .LBB6_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.d fa0, fa1
+; CHECK-NEXT:  .LBB6_2:
+; CHECK-NEXT:    ret
   %1 = fcmp one double %a, %b
   %2 = select i1 %1, double %a, double %b
   ret double %2
 }
 
 define double @select_fcmp_ord(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_ord:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa1, fa1
-; RV32IFD-NEXT:    feq.d a1, fa0, fa0
-; RV32IFD-NEXT:    and a0, a1, a0
-; RV32IFD-NEXT:    bnez a0, .LBB7_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fmv.d fa0, fa1
-; RV32IFD-NEXT:  .LBB7_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: select_fcmp_ord:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa1, fa1
-; RV64IFD-NEXT:    feq.d a1, fa0, fa0
-; RV64IFD-NEXT:    and a0, a1, a0
-; RV64IFD-NEXT:    bnez a0, .LBB7_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fmv.d fa0, fa1
-; RV64IFD-NEXT:  .LBB7_2:
-; RV64IFD-NEXT:    ret
+; CHECK-LABEL: select_fcmp_ord:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.d a0, fa1, fa1
+; CHECK-NEXT:    feq.d a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    bnez a0, .LBB7_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.d fa0, fa1
+; CHECK-NEXT:  .LBB7_2:
+; CHECK-NEXT:    ret
   %1 = fcmp ord double %a, %b
   %2 = select i1 %1, double %a, double %b
   ret double %2
 }
 
 define double @select_fcmp_ueq(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_ueq:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    flt.d a0, fa0, fa1
-; RV32IFD-NEXT:    flt.d a1, fa1, fa0
-; RV32IFD-NEXT:    or a0, a1, a0
-; RV32IFD-NEXT:    beqz a0, .LBB8_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fmv.d fa0, fa1
-; RV32IFD-NEXT:  .LBB8_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: select_fcmp_ueq:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    flt.d a0, fa0, fa1
-; RV64IFD-NEXT:    flt.d a1, fa1, fa0
-; RV64IFD-NEXT:    or a0, a1, a0
-; RV64IFD-NEXT:    beqz a0, .LBB8_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fmv.d fa0, fa1
-; RV64IFD-NEXT:  .LBB8_2:
-; RV64IFD-NEXT:    ret
+; CHECK-LABEL: select_fcmp_ueq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.d a0, fa0, fa1
+; CHECK-NEXT:    flt.d a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    beqz a0, .LBB8_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.d fa0, fa1
+; CHECK-NEXT:  .LBB8_2:
+; CHECK-NEXT:    ret
   %1 = fcmp ueq double %a, %b
   %2 = select i1 %1, double %a, double %b
   ret double %2
 }
 
 define double @select_fcmp_ugt(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_ugt:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fle.d a0, fa0, fa1
-; RV32IFD-NEXT:    beqz a0, .LBB9_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fmv.d fa0, fa1
-; RV32IFD-NEXT:  .LBB9_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: select_fcmp_ugt:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fle.d a0, fa0, fa1
-; RV64IFD-NEXT:    beqz a0, .LBB9_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fmv.d fa0, fa1
-; RV64IFD-NEXT:  .LBB9_2:
-; RV64IFD-NEXT:    ret
+; CHECK-LABEL: select_fcmp_ugt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.d a0, fa0, fa1
+; CHECK-NEXT:    beqz a0, .LBB9_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.d fa0, fa1
+; CHECK-NEXT:  .LBB9_2:
+; CHECK-NEXT:    ret
   %1 = fcmp ugt double %a, %b
   %2 = select i1 %1, double %a, double %b
   ret double %2
 }
 
 define double @select_fcmp_uge(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_uge:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    flt.d a0, fa0, fa1
-; RV32IFD-NEXT:    beqz a0, .LBB10_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fmv.d fa0, fa1
-; RV32IFD-NEXT:  .LBB10_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: select_fcmp_uge:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    flt.d a0, fa0, fa1
-; RV64IFD-NEXT:    beqz a0, .LBB10_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fmv.d fa0, fa1
-; RV64IFD-NEXT:  .LBB10_2:
-; RV64IFD-NEXT:    ret
+; CHECK-LABEL: select_fcmp_uge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.d a0, fa0, fa1
+; CHECK-NEXT:    beqz a0, .LBB10_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.d fa0, fa1
+; CHECK-NEXT:  .LBB10_2:
+; CHECK-NEXT:    ret
   %1 = fcmp uge double %a, %b
   %2 = select i1 %1, double %a, double %b
   ret double %2
 }
 
 define double @select_fcmp_ult(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_ult:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fle.d a0, fa1, fa0
-; RV32IFD-NEXT:    beqz a0, .LBB11_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fmv.d fa0, fa1
-; RV32IFD-NEXT:  .LBB11_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: select_fcmp_ult:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fle.d a0, fa1, fa0
-; RV64IFD-NEXT:    beqz a0, .LBB11_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fmv.d fa0, fa1
-; RV64IFD-NEXT:  .LBB11_2:
-; RV64IFD-NEXT:    ret
+; CHECK-LABEL: select_fcmp_ult:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.d a0, fa1, fa0
+; CHECK-NEXT:    beqz a0, .LBB11_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.d fa0, fa1
+; CHECK-NEXT:  .LBB11_2:
+; CHECK-NEXT:    ret
   %1 = fcmp ult double %a, %b
   %2 = select i1 %1, double %a, double %b
   ret double %2
 }
 
 define double @select_fcmp_ule(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_ule:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    flt.d a0, fa1, fa0
-; RV32IFD-NEXT:    beqz a0, .LBB12_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fmv.d fa0, fa1
-; RV32IFD-NEXT:  .LBB12_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: select_fcmp_ule:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    flt.d a0, fa1, fa0
-; RV64IFD-NEXT:    beqz a0, .LBB12_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fmv.d fa0, fa1
-; RV64IFD-NEXT:  .LBB12_2:
-; RV64IFD-NEXT:    ret
+; CHECK-LABEL: select_fcmp_ule:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.d a0, fa1, fa0
+; CHECK-NEXT:    beqz a0, .LBB12_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.d fa0, fa1
+; CHECK-NEXT:  .LBB12_2:
+; CHECK-NEXT:    ret
   %1 = fcmp ule double %a, %b
   %2 = select i1 %1, double %a, double %b
   ret double %2
 }
 
 define double @select_fcmp_une(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_une:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa0, fa1
-; RV32IFD-NEXT:    beqz a0, .LBB13_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fmv.d fa0, fa1
-; RV32IFD-NEXT:  .LBB13_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: select_fcmp_une:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa0, fa1
-; RV64IFD-NEXT:    beqz a0, .LBB13_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fmv.d fa0, fa1
-; RV64IFD-NEXT:  .LBB13_2:
-; RV64IFD-NEXT:    ret
+; CHECK-LABEL: select_fcmp_une:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.d a0, fa0, fa1
+; CHECK-NEXT:    beqz a0, .LBB13_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.d fa0, fa1
+; CHECK-NEXT:  .LBB13_2:
+; CHECK-NEXT:    ret
   %1 = fcmp une double %a, %b
   %2 = select i1 %1, double %a, double %b
   ret double %2
 }
 
 define double @select_fcmp_uno(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_uno:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a0, fa1, fa1
-; RV32IFD-NEXT:    feq.d a1, fa0, fa0
-; RV32IFD-NEXT:    and a0, a1, a0
-; RV32IFD-NEXT:    beqz a0, .LBB14_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    fmv.d fa0, fa1
-; RV32IFD-NEXT:  .LBB14_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: select_fcmp_uno:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a0, fa1, fa1
-; RV64IFD-NEXT:    feq.d a1, fa0, fa0
-; RV64IFD-NEXT:    and a0, a1, a0
-; RV64IFD-NEXT:    beqz a0, .LBB14_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    fmv.d fa0, fa1
-; RV64IFD-NEXT:  .LBB14_2:
-; RV64IFD-NEXT:    ret
+; CHECK-LABEL: select_fcmp_uno:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.d a0, fa1, fa1
+; CHECK-NEXT:    feq.d a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    beqz a0, .LBB14_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.d fa0, fa1
+; CHECK-NEXT:  .LBB14_2:
+; CHECK-NEXT:    ret
   %1 = fcmp uno double %a, %b
   %2 = select i1 %1, double %a, double %b
   ret double %2
 }
 
 define double @select_fcmp_true(double %a, double %b) nounwind {
-; RV32IFD-LABEL: select_fcmp_true:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: select_fcmp_true:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    ret
+; CHECK-LABEL: select_fcmp_true:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ret
   %1 = fcmp true double %a, %b
   %2 = select i1 %1, double %a, double %b
   ret double %2
 }
 
 ; Ensure that ISel succeeds for a select+fcmp that has an i32 result type.
 define i32 @i32_select_fcmp_oeq(double %a, double %b, i32 %c, i32 %d) nounwind {
-; RV32IFD-LABEL: i32_select_fcmp_oeq:
-; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    feq.d a2, fa0, fa1
-; RV32IFD-NEXT:    bnez a2, .LBB16_2
-; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    mv a0, a1
-; RV32IFD-NEXT:  .LBB16_2:
-; RV32IFD-NEXT:    ret
-;
-; RV64IFD-LABEL: i32_select_fcmp_oeq:
-; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    feq.d a2, fa0, fa1
-; RV64IFD-NEXT:    bnez a2, .LBB16_2
-; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    mv a0, a1
-; RV64IFD-NEXT:  .LBB16_2:
-; RV64IFD-NEXT:    ret
+; CHECK-LABEL: i32_select_fcmp_oeq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.d a2, fa0, fa1
+; CHECK-NEXT:    bnez a2, .LBB16_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    mv a0, a1
+; CHECK-NEXT:  .LBB16_2:
+; CHECK-NEXT:    ret
   %1 = fcmp oeq double %a, %b
   %2 = select i1 %1, i32 %c, i32 %d
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/float-arith-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=ilp32f \
-; RUN:   | FileCheck -check-prefix=RV32IF %s
+; RUN:   | FileCheck -check-prefixes=CHECKIF,RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=lp64f \
-; RUN:   | FileCheck -check-prefix=RV64IF %s
+; RUN:   | FileCheck -check-prefixes=CHECKIF,RV64IF %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s
 
 define float @fadd_s(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fadd_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fadd_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fadd_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fadd.s fa0, fa0, fa1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __addsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fadd_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __addsf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.fadd.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata)
 
 define float @fsub_s(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fsub_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fsub.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fsub_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fsub.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fsub_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fsub.s fa0, fa0, fa1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __subsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fsub_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __subsf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.fsub.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.fsub.f32(float, float, metadata, metadata)
 
 define float @fmul_s(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fmul_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmul.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmul_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmul.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fmul_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmul.s fa0, fa0, fa1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fmul_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __mulsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fmul_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __mulsf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.fmul.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.fmul.f32(float, float, metadata, metadata)
 
 define float @fdiv_s(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fdiv_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fdiv.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fdiv_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fdiv.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fdiv_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fdiv.s fa0, fa0, fa1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fdiv_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __divsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fdiv_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __divsf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.fdiv.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.fdiv.f32(float, float, metadata, metadata)
 
 define float @fsqrt_s(float %a) nounwind strictfp {
-; RV32IF-LABEL: fsqrt_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fsqrt.s fa0, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fsqrt_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fsqrt.s fa0, fa0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fsqrt_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fsqrt.s fa0, fa0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fsqrt_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call sqrtf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.maxnum.f32(float %a, float %b, metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.maxnum.f32(float, float, metadata) strictfp
 
 define float @fmadd_s(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fmadd_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmadd_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fmadd_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fmadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fmaf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fmadd_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call fmaf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %b, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) strictfp
 
 define float @fmsub_s(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fmsub_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmsub_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fmsub_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmv.w.x ft0, zero
+; CHECKIF-NEXT:    fadd.s ft0, fa2, ft0
+; CHECKIF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fmsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1

 ; RV64I-NEXT:    ret
   %c_ = fadd float 0.0, %c ; avoid negation using xor
   %negc = fneg float %c_
   %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %b, float %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 
 define float @fnmadd_s(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fnmadd_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fnmadd.s fa0, ft1, fa1, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmadd_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fnmadd.s fa0, ft1, fa1, ft0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fnmadd_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmv.w.x ft0, zero
+; CHECKIF-NEXT:    fadd.s ft1, fa0, ft0
+; CHECKIF-NEXT:    fadd.s ft0, fa2, ft0
+; CHECKIF-NEXT:    fnmadd.s fa0, ft1, fa1, ft0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %c_ = fadd float 0.0, %c
   %nega = fneg float %a_
   %negc = fneg float %c_
   %1 = call float @llvm.experimental.constrained.fma.f32(float %nega, float %b, float %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 
 define float @fnmadd_s_2(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fnmadd_s_2:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft1, fa1, ft0
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fnmadd.s fa0, ft1, fa0, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmadd_s_2:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft1, fa1, ft0
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fnmadd.s fa0, ft1, fa0, ft0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fnmadd_s_2:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmv.w.x ft0, zero
+; CHECKIF-NEXT:    fadd.s ft1, fa1, ft0
+; CHECKIF-NEXT:    fadd.s ft0, fa2, ft0
+; CHECKIF-NEXT:    fnmadd.s fa0, ft1, fa0, ft0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmadd_s_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %c_ = fadd float 0.0, %c
   %negb = fneg float %b_
   %negc = fneg float %c_
   %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %negb, float %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 
 define float @fnmsub_s(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fnmsub_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft0, fa0, ft0
-; RV32IF-NEXT:    fnmsub.s fa0, ft0, fa1, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmsub_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft0, fa0, ft0
-; RV64IF-NEXT:    fnmsub.s fa0, ft0, fa1, fa2
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fnmsub_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmv.w.x ft0, zero
+; CHECKIF-NEXT:    fadd.s ft0, fa0, ft0
+; CHECKIF-NEXT:    fnmsub.s fa0, ft0, fa1, fa2
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a2

 ; RV64I-NEXT:    ret
   %a_ = fadd float 0.0, %a
   %nega = fneg float %a_
   %1 = call float @llvm.experimental.constrained.fma.f32(float %nega, float %b, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 
 define float @fnmsub_s_2(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fnmsub_s_2:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft0, fa1, ft0
-; RV32IF-NEXT:    fnmsub.s fa0, ft0, fa0, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmsub_s_2:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft0, fa1, ft0
-; RV64IF-NEXT:    fnmsub.s fa0, ft0, fa0, fa2
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fnmsub_s_2:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmv.w.x ft0, zero
+; CHECKIF-NEXT:    fadd.s ft0, fa1, ft0
+; CHECKIF-NEXT:    fnmsub.s fa0, ft0, fa0, fa2
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmsub_s_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a2

llvm/test/CodeGen/RISCV/float-arith.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=CHECKIF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefix=CHECKIF %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 ; These tests are each targeted at a particular RISC-V FPU instruction.
 ; Compares and conversions can be found in float-fcmp.ll and float-convert.ll
 ; respectively. Some other float-*.ll files in this folder exercise LLVM IR
 ; instructions that don't directly match a RISC-V instruction.
 
 define float @fadd_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fadd_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fadd_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fadd_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fadd.s fa0, fa0, fa1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __addsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fadd_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __addsf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fadd float %a, %b
   ret float %1
 }
 
 define float @fsub_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fsub_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fsub.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fsub_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fsub.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fsub_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fsub.s fa0, fa0, fa1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __subsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fsub_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __subsf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fsub float %a, %b
   ret float %1
 }
 
 define float @fmul_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fmul_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmul.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmul_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmul.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fmul_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmul.s fa0, fa0, fa1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fmul_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __mulsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fmul_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __mulsf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fmul float %a, %b
   ret float %1
 }
 
 define float @fdiv_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fdiv_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fdiv.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fdiv_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fdiv.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fdiv_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fdiv.s fa0, fa0, fa1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fdiv_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __divsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = fdiv float %a, %b
   ret float %1
 }
 
 declare float @llvm.sqrt.f32(float)
 
 define float @fsqrt_s(float %a) nounwind {
-; RV32IF-LABEL: fsqrt_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fsqrt.s fa0, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fsqrt_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fsqrt.s fa0, fa0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fsqrt_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fsqrt.s fa0, fa0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fsqrt_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call sqrtf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call float @llvm.sqrt.f32(float %a)
   ret float %1
 }
 
 declare float @llvm.copysign.f32(float, float)
 
 define float @fsgnj_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fsgnj_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fsgnj.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fsgnj_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fsgnj.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fsgnj_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fsgnj.s fa0, fa0, fa1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fsgnj_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a2, 524288
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    slli a0, a0, 1
 ; RV32I-NEXT:    srli a0, a0, 1
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fsgnj_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a2, 524288
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    slli a0, a0, 33
 ; RV64I-NEXT:    srli a0, a0, 33
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.copysign.f32(float %a, float %b)
   ret float %1
 }
 
-; This function performs extra work to ensure that
-; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
 define i32 @fneg_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fneg_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s ft0, fa0, fa0
-; RV32IF-NEXT:    fneg.s ft1, ft0
-; RV32IF-NEXT:    feq.s a0, ft0, ft1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fneg_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s ft0, fa0, fa0
-; RV64IF-NEXT:    fneg.s ft1, ft0
-; RV64IF-NEXT:    feq.s a0, ft0, ft1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fneg_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fadd.s ft0, fa0, fa0
+; CHECKIF-NEXT:    fneg.s ft1, ft0
+; CHECKIF-NEXT:    feq.s a0, ft0, ft1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fneg_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    call __addsf3@plt
 ; RV32I-NEXT:    lui a1, 524288

 ; RV64I-NEXT:    ret
   %1 = fadd float %a, %a
   %2 = fneg float %1
   %3 = fcmp oeq float %1, %2
   %4 = zext i1 %3 to i32
   ret i32 %4
 }
 
-; This function performs extra work to ensure that
-; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
 define float @fsgnjn_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fsgnjn_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV32IF-NEXT:    fsgnjn.s fa0, fa0, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fsgnjn_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV64IF-NEXT:    fsgnjn.s fa0, fa0, ft0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fsgnjn_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fadd.s ft0, fa0, fa1
+; CHECKIF-NEXT:    fsgnjn.s fa0, fa0, ft0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fsgnjn_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    call __addsf3@plt
; RV64I-NEXT:    ret
   %1 = fadd float %a, %b
   %2 = fneg float %1
   %3 = call float @llvm.copysign.f32(float %a, float %2)
   ret float %3
 }
 
 declare float @llvm.fabs.f32(float)
 
-; This function performs extra work to ensure that
-; DAGCombiner::visitBITCAST doesn't replace the fabs with an and.
 define float @fabs_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fabs_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV32IF-NEXT:    fabs.s ft1, ft0
-; RV32IF-NEXT:    fadd.s fa0, ft1, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fabs_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV64IF-NEXT:    fabs.s ft1, ft0
-; RV64IF-NEXT:    fadd.s fa0, ft1, ft0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fabs_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fadd.s ft0, fa0, fa1
+; CHECKIF-NEXT:    fabs.s ft1, ft0
+; CHECKIF-NEXT:    fadd.s fa0, ft1, ft0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fabs_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __addsf3@plt
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    slli a0, a0, 1
; RV64I-NEXT:    ret
   %2 = call float @llvm.fabs.f32(float %1)
   %3 = fadd float %2, %1
   ret float %3
 }
 
 declare float @llvm.minnum.f32(float, float)
 
 define float @fmin_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fmin_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmin.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmin_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmin.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fmin_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmin.s fa0, fa0, fa1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fmin_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fminf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call float @llvm.minnum.f32(float %a, float %b)
   ret float %1
 }
 
 declare float @llvm.maxnum.f32(float, float)
 
 define float @fmax_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fmax_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmax.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmax_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmax.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fmax_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmax.s fa0, fa0, fa1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fmax_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fmaxf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call float @llvm.maxnum.f32(float %a, float %b)
   ret float %1
 }
 
 declare float @llvm.fma.f32(float, float, float)
 
 define float @fmadd_s(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fmadd_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmadd_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fmadd_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fmadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fmaf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fmadd_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call fmaf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.fma.f32(float %a, float %b, float %c)
   ret float %1
 }
 
 define float @fmsub_s(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fmsub_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmsub_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fmsub_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmv.w.x ft0, zero
+; CHECKIF-NEXT:    fadd.s ft0, fa2, ft0
+; CHECKIF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fmsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1

 ; RV64I-NEXT:    ret
   %c_ = fadd float 0.0, %c ; avoid negation using xor
   %negc = fsub float -0.0, %c_
   %1 = call float @llvm.fma.f32(float %a, float %b, float %negc)
   ret float %1
 }
 
 define float @fnmadd_s(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmadd_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fnmadd.s fa0, ft1, fa1, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmadd_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fnmadd.s fa0, ft1, fa1, ft0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fnmadd_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmv.w.x ft0, zero
+; CHECKIF-NEXT:    fadd.s ft1, fa0, ft0
+; CHECKIF-NEXT:    fadd.s ft0, fa2, ft0
+; CHECKIF-NEXT:    fnmadd.s fa0, ft1, fa1, ft0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %c_ = fadd float 0.0, %c
   %nega = fsub float -0.0, %a_
   %negc = fsub float -0.0, %c_
   %1 = call float @llvm.fma.f32(float %nega, float %b, float %negc)
   ret float %1
 }
 
 define float @fnmadd_s_2(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmadd_s_2:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft1, fa1, ft0
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fnmadd.s fa0, ft1, fa0, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmadd_s_2:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft1, fa1, ft0
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fnmadd.s fa0, ft1, fa0, ft0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fnmadd_s_2:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmv.w.x ft0, zero
+; CHECKIF-NEXT:    fadd.s ft1, fa1, ft0
+; CHECKIF-NEXT:    fadd.s ft0, fa2, ft0
+; CHECKIF-NEXT:    fnmadd.s fa0, ft1, fa0, ft0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmadd_s_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %c_ = fadd float 0.0, %c
   %negb = fsub float -0.0, %b_
   %negc = fsub float -0.0, %c_
   %1 = call float @llvm.fma.f32(float %a, float %negb, float %negc)
   ret float %1
 }
 
 define float @fnmsub_s(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmsub_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft0, fa0, ft0
-; RV32IF-NEXT:    fnmsub.s fa0, ft0, fa1, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmsub_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft0, fa0, ft0
-; RV64IF-NEXT:    fnmsub.s fa0, ft0, fa1, fa2
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fnmsub_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmv.w.x ft0, zero
+; CHECKIF-NEXT:    fadd.s ft0, fa0, ft0
+; CHECKIF-NEXT:    fnmsub.s fa0, ft0, fa1, fa2
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a2

 ; RV64I-NEXT:    ret
   %a_ = fadd float 0.0, %a
   %nega = fsub float -0.0, %a_
   %1 = call float @llvm.fma.f32(float %nega, float %b, float %c)
   ret float %1
 }
 
 define float @fnmsub_s_2(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmsub_s_2:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft0, fa1, ft0
-; RV32IF-NEXT:    fnmsub.s fa0, ft0, fa0, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmsub_s_2:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft0, fa1, ft0
-; RV64IF-NEXT:    fnmsub.s fa0, ft0, fa0, fa2
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fnmsub_s_2:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmv.w.x ft0, zero
+; CHECKIF-NEXT:    fadd.s ft0, fa1, ft0
+; CHECKIF-NEXT:    fnmsub.s fa0, ft0, fa0, fa2
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmsub_s_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a2

 ; RV64I-NEXT:    ret
   %b_ = fadd float 0.0, %b
   %negb = fsub float -0.0, %b_
   %1 = call float @llvm.fma.f32(float %a, float %negb, float %c)
   ret float %1
 }
 
 define float @fmadd_s_contract(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fmadd_s_contract:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmadd_s_contract:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fmadd_s_contract:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fmadd_s_contract:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    call __mulsf3@plt

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fmul contract float %a, %b
   %2 = fadd contract float %1, %c
   ret float %2
 }
 
 define float @fmsub_s_contract(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fmsub_s_contract:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmsub_s_contract:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fmsub_s_contract:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmv.w.x ft0, zero
+; CHECKIF-NEXT:    fadd.s ft0, fa2, ft0
+; CHECKIF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fmsub_s_contract:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ret
   %c_ = fadd float 0.0, %c ; avoid negation using xor
   %1 = fmul contract float %a, %b
   %2 = fsub contract float %1, %c_
   ret float %2
 }
 
 define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmadd_s_contract:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV32IF-NEXT:    fadd.s ft2, fa1, ft0
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fnmadd.s fa0, ft1, ft2, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmadd_s_contract:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV64IF-NEXT:    fadd.s ft2, fa1, ft0
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fnmadd.s fa0, ft1, ft2, ft0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fnmadd_s_contract:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmv.w.x ft0, zero
+; CHECKIF-NEXT:    fadd.s ft1, fa0, ft0
+; CHECKIF-NEXT:    fadd.s ft2, fa1, ft0
+; CHECKIF-NEXT:    fadd.s ft0, fa2, ft0
+; CHECKIF-NEXT:    fnmadd.s fa0, ft1, ft2, ft0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmadd_s_contract:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %c_ = fadd float 0.0, %c ; avoid negation using xor
   %1 = fmul contract float %a_, %b_
   %2 = fneg float %1
   %3 = fsub contract float %2, %c_
   ret float %3
 }
 
 define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmsub_s_contract:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV32IF-NEXT:    fadd.s ft0, fa1, ft0
-; RV32IF-NEXT:    fnmsub.s fa0, ft1, ft0, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmsub_s_contract:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV64IF-NEXT:    fadd.s ft0, fa1, ft0
-; RV64IF-NEXT:    fnmsub.s fa0, ft1, ft0, fa2
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fnmsub_s_contract:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmv.w.x ft0, zero
+; CHECKIF-NEXT:    fadd.s ft1, fa0, ft0
+; CHECKIF-NEXT:    fadd.s ft0, fa1, ft0
+; CHECKIF-NEXT:    fnmsub.s fa0, ft1, ft0, fa2
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmsub_s_contract:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

llvm/test/CodeGen/RISCV/float-convert-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=ilp32f \
-; RUN:   | FileCheck -check-prefix=RV32IF %s
+; RUN:   | FileCheck -check-prefixes=CHECKIF,RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=lp64f \
-; RUN:   | FileCheck -check-prefix=RV64IF %s
+; RUN:   | FileCheck -check-prefixes=CHECKIF,RV64IF %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s
 
 ; NOTE: The rounding mode metadata does not effect which instruction is
 ; selected. Dynamic rounding mode is always used for operations that
 ; support rounding mode.
 
 define i32 @fcvt_w_s(float %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_w_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_w_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_w_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fcvt.w.s a0, fa0, rtz
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_w_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixsfsi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_w_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __fixsfsi@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata)
 
 define i32 @fcvt_wu_s(float %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_wu_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_wu_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_wu_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rtz
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunssfsi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
; RV64I-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata)
 
 ; Test where the fptoui has multiple uses, one of which causes a sext to be
 ; inserted on RV64.
 define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) nounwind {
-; RV32IF-LABEL: fcvt_wu_s_multiple_use:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.wu.s a1, fa0, rtz
-; RV32IF-NEXT:    li a0, 1
-; RV32IF-NEXT:    beqz a1, .LBB2_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    mv a0, a1
-; RV32IF-NEXT:  .LBB2_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_wu_s_multiple_use:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.wu.s a1, fa0, rtz
-; RV64IF-NEXT:    li a0, 1
-; RV64IF-NEXT:    beqz a1, .LBB2_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    mv a0, a1
-; RV64IF-NEXT:  .LBB2_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_wu_s_multiple_use:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fcvt.wu.s a1, fa0, rtz
+; CHECKIF-NEXT:    li a0, 1
+; CHECKIF-NEXT:    beqz a1, .LBB2_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    mv a0, a1
+; CHECKIF-NEXT:  .LBB2_2:
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s_multiple_use:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunssfsi@plt
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    li a0, 1

 ; RV64I-NEXT:    ret
   %a = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %x, metadata !"fpexcept.strict") strictfp
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c
 }
 
 define float @fcvt_s_w(i32 %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_w:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_s_w:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fcvt.s.w fa0, a0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.sitofp.f32.i32(i32, metadata, metadata)
 
 define float @fcvt_s_w_load(i32* %p) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_w_load:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    lw a0, 0(a0)
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w_load:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    lw a0, 0(a0)
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_s_w_load:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    lw a0, 0(a0)
+; CHECKIF-NEXT:    fcvt.s.w fa0, a0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w_load:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    lw a0, 0(a0)
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %a = load i32, i32* %p
   %1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 
 define float @fcvt_s_wu(i32 %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_wu:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.wu fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_wu:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.wu fa0, a0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_s_wu:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fcvt.s.wu fa0, a0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_wu:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.uitofp.f32.i64(i64 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.uitofp.f32.i64(i64, metadata, metadata)
 
 define float @fcvt_s_w_i8(i8 signext %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_w_i8:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w_i8:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_s_w_i8:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fcvt.s.w fa0, a0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_w_i8:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatsisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.sitofp.f32.i8(i8 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.sitofp.f32.i8(i8, metadata, metadata)
 
 define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_wu_i8:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.wu fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_wu_i8:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.wu fa0, a0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_s_wu_i8:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fcvt.s.wu fa0, a0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_wu_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_wu_i8:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatunsisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.uitofp.f32.i8(i8 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
   ret float %1
 }
 declare float @llvm.experimental.constrained.uitofp.f32.i8(i8, metadata, metadata)
 
 define float @fcvt_s_w_i16(i16 signext %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_w_i16:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w_i16:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_s_w_i16:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fcvt.s.w fa0, a0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_w_i16:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatsisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.sitofp.f32.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.sitofp.f32.i16(i16, metadata, metadata)
 
 define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_wu_i16:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.wu fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_wu_i16:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.wu fa0, a0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_s_wu_i16:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fcvt.s.wu fa0, a0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_wu_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

llvm/test/CodeGen/RISCV/float-convert.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIF,RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECKIF,RV64IF %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 define i32 @fcvt_w_s(float %a) nounwind {
-; RV32IF-LABEL: fcvt_w_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_w_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_w_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fcvt.w.s a0, fa0, rtz
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_w_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixsfsi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_w_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __fixsfsi@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fptosi float %a to i32
   ret i32 %1
 }
 
 define i32 @fcvt_w_s_sat(float %a) nounwind {
-; RV32IF-LABEL: fcvt_w_s_sat:
-; RV32IF:       # %bb.0: # %start
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB1_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV32IF-NEXT:  .LBB1_2: # %start
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_w_s_sat:
-; RV64IF:       # %bb.0: # %start
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB1_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV64IF-NEXT:  .LBB1_2: # %start
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_w_s_sat:
+; CHECKIF:       # %bb.0: # %start
+; CHECKIF-NEXT:    feq.s a0, fa0, fa0
+; CHECKIF-NEXT:    beqz a0, .LBB1_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fcvt.w.s a0, fa0, rtz
+; CHECKIF-NEXT:  .LBB1_2: # %start
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_w_s_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %0
 }
 declare i32 @llvm.fptosi.sat.i32.f32(float)
 
 define i32 @fcvt_wu_s(float %a) nounwind {
-; RV32IF-LABEL: fcvt_wu_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_wu_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_wu_s:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rtz
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunssfsi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = fptoui float %a to i32
   ret i32 %1
 }
 
 ; Test where the fptoui has multiple uses, one of which causes a sext to be
 ; inserted on RV64.
 define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) nounwind {
-; RV32IF-LABEL: fcvt_wu_s_multiple_use:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.wu.s a1, fa0, rtz
-; RV32IF-NEXT:    li a0, 1
-; RV32IF-NEXT:    beqz a1, .LBB3_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    mv a0, a1
-; RV32IF-NEXT:  .LBB3_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_wu_s_multiple_use:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.wu.s a1, fa0, rtz
-; RV64IF-NEXT:    li a0, 1
-; RV64IF-NEXT:    beqz a1, .LBB3_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    mv a0, a1
-; RV64IF-NEXT:  .LBB3_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_wu_s_multiple_use:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fcvt.wu.s a1, fa0, rtz
+; CHECKIF-NEXT:    li a0, 1
+; CHECKIF-NEXT:    beqz a1, .LBB3_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    mv a0, a1
+; CHECKIF-NEXT:  .LBB3_2:
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s_multiple_use:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunssfsi@plt
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    li a0, 1

 ; RV64I-NEXT:    ret
   %a = fptoui float %x to i32
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c
 }
 
 define i32 @fcvt_wu_s_sat(float %a) nounwind {
-; RV32IF-LABEL: fcvt_wu_s_sat:
-; RV32IF:       # %bb.0: # %start
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB4_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV32IF-NEXT:  .LBB4_2: # %start
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_wu_s_sat:
-; RV64IF:       # %bb.0: # %start
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB4_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV64IF-NEXT:  .LBB4_2: # %start
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_wu_s_sat:
+; CHECKIF:       # %bb.0: # %start
+; CHECKIF-NEXT:    feq.s a0, fa0, fa0
+; CHECKIF-NEXT:    beqz a0, .LBB4_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rtz
+; CHECKIF-NEXT:  .LBB4_2: # %start
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %0
 }
 declare i32 @llvm.fptoui.sat.i32.f32(float)
 
 define i32 @fmv_x_w(float %a, float %b) nounwind {
-; RV32IF-LABEL: fmv_x_w:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV32IF-NEXT:    fmv.x.w a0, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmv_x_w:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV64IF-NEXT:    fmv.x.w a0, ft0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fmv_x_w:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fadd.s ft0, fa0, fa1
+; CHECKIF-NEXT:    fmv.x.w a0, ft0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fmv_x_w:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __addsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
 ; Ensure fmv.x.w is generated even for a soft float calling convention
   %1 = fadd float %a, %b
   %2 = bitcast float %1 to i32
   ret i32 %2
 }
 
 define float @fcvt_s_w(i32 %a) nounwind {
-; RV32IF-LABEL: fcvt_s_w:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_s_w:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fcvt.s.w fa0, a0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_w:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    call __floatsisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = sitofp i32 %a to float
   ret float %1
 }
 
 define float @fcvt_s_w_load(i32* %p) nounwind {
-; RV32IF-LABEL: fcvt_s_w_load:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    lw a0, 0(a0)
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w_load:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    lw a0, 0(a0)
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_s_w_load:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    lw a0, 0(a0)
+; CHECKIF-NEXT:    fcvt.s.w fa0, a0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w_load:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    lw a0, 0(a0)
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %a = load i32, i32* %p
   %1 = sitofp i32 %a to float
   ret float %1
 }
 
 define float @fcvt_s_wu(i32 %a) nounwind {
-; RV32IF-LABEL: fcvt_s_wu:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.wu fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_wu:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.wu fa0, a0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_s_wu:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fcvt.s.wu fa0, a0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_wu:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %a = load i32, i32* %p
   %1 = uitofp i32 %a to float
   ret float %1
 }
 
 define float @fmv_w_x(i32 %a, i32 %b) nounwind {
-; RV32IF-LABEL: fmv_w_x:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, a0
-; RV32IF-NEXT:    fmv.w.x ft1, a1
-; RV32IF-NEXT:    fadd.s fa0, ft0, ft1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmv_w_x:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, a0
-; RV64IF-NEXT:    fmv.w.x ft1, a1
-; RV64IF-NEXT:    fadd.s fa0, ft0, ft1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fmv_w_x:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmv.w.x ft0, a0
+; CHECKIF-NEXT:    fmv.w.x ft1, a1
+; CHECKIF-NEXT:    fadd.s fa0, ft0, ft1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fmv_w_x:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __addsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = uitofp i64 %a to float
   ret float %1
 }
 
 define float @fcvt_s_w_i8(i8 signext %a) nounwind {
-; RV32IF-LABEL: fcvt_s_w_i8:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w_i8:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_s_w_i8:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fcvt.s.w fa0, a0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_w_i8:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatsisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = sitofp i8 %a to float
   ret float %1
 }
 
 define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind {
-; RV32IF-LABEL: fcvt_s_wu_i8:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.wu fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_wu_i8:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.wu fa0, a0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_s_wu_i8:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fcvt.s.wu fa0, a0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_wu_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_wu_i8:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatunsisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = uitofp i8 %a to float
   ret float %1
 }
 
 define float @fcvt_s_w_i16(i16 signext %a) nounwind {
-; RV32IF-LABEL: fcvt_s_w_i16:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w_i16:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_s_w_i16:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fcvt.s.w fa0, a0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_w_i16:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatsisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = sitofp i16 %a to float
   ret float %1
 }
 
 define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind {
-; RV32IF-LABEL: fcvt_s_wu_i16:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.wu fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_wu_i16:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.wu fa0, a0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcvt_s_wu_i16:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fcvt.s.wu fa0, a0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_wu_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

llvm/test/CodeGen/RISCV/float-fcmp-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=ilp32f \
-; RUN:   | FileCheck -check-prefix=RV32IF %s
+; RUN:   | FileCheck -check-prefix=CHECKIF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=lp64f \
-; RUN:   | FileCheck -check-prefix=RV64IF %s
+; RUN:   | FileCheck -check-prefix=CHECKIF %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s
 
 define i32 @fcmp_oeq(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_oeq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_oeq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_oeq:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa0, fa1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oeq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __eqsf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"oeq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 declare i1 @llvm.experimental.constrained.fcmp.f32(float, float, metadata, metadata)
 
 define i32 @fcmp_ogt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ogt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a1
-; RV32IF-NEXT:    flt.s a0, fa1, fa0
-; RV32IF-NEXT:    fsflags a1
-; RV32IF-NEXT:    feq.s zero, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ogt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a1
-; RV64IF-NEXT:    flt.s a0, fa1, fa0
-; RV64IF-NEXT:    fsflags a1
-; RV64IF-NEXT:    feq.s zero, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_ogt:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    frflags a1
+; CHECKIF-NEXT:    flt.s a0, fa1, fa0
+; CHECKIF-NEXT:    fsflags a1
+; CHECKIF-NEXT:    feq.s zero, fa1, fa0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oge(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_oge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a1
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    fsflags a1
-; RV32IF-NEXT:    feq.s zero, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_oge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a1
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    fsflags a1
-; RV64IF-NEXT:    feq.s zero, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_oge:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    frflags a1
+; CHECKIF-NEXT:    fle.s a0, fa1, fa0
+; CHECKIF-NEXT:    fsflags a1
+; CHECKIF-NEXT:    feq.s zero, fa1, fa0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_olt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_olt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a1
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    fsflags a1
-; RV32IF-NEXT:    feq.s zero, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_olt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a1
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    fsflags a1
-; RV64IF-NEXT:    feq.s zero, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_olt:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    frflags a1
+; CHECKIF-NEXT:    flt.s a0, fa0, fa1
+; CHECKIF-NEXT:    fsflags a1
+; CHECKIF-NEXT:    feq.s zero, fa0, fa1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_olt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ole(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ole:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a1
-; RV32IF-NEXT:    fle.s a0, fa0, fa1
-; RV32IF-NEXT:    fsflags a1
-; RV32IF-NEXT:    feq.s zero, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ole:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a1
-; RV64IF-NEXT:    fle.s a0, fa0, fa1
-; RV64IF-NEXT:    fsflags a1
-; RV64IF-NEXT:    feq.s zero, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_ole:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    frflags a1
+; CHECKIF-NEXT:    fle.s a0, fa0, fa1
+; CHECKIF-NEXT:    fsflags a1
+; CHECKIF-NEXT:    feq.s zero, fa0, fa1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ole:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 ; FIXME: We only need one frflags before the two flts and one fsflags after the
 ; two flts.
 define i32 @fcmp_one(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_one:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    flt.s a1, fa0, fa1
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    feq.s zero, fa0, fa1
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    flt.s a2, fa1, fa0
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    or a0, a2, a1
-; RV32IF-NEXT:    feq.s zero, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_one:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    flt.s a1, fa0, fa1
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    feq.s zero, fa0, fa1
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    flt.s a2, fa1, fa0
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    or a0, a2, a1
-; RV64IF-NEXT:    feq.s zero, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_one:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    frflags a0
+; CHECKIF-NEXT:    flt.s a1, fa0, fa1
+; CHECKIF-NEXT:    fsflags a0
+; CHECKIF-NEXT:    feq.s zero, fa0, fa1
+; CHECKIF-NEXT:    frflags a0
+; CHECKIF-NEXT:    flt.s a2, fa1, fa0
+; CHECKIF-NEXT:    fsflags a0
+; CHECKIF-NEXT:    or a0, a2, a1
+; CHECKIF-NEXT:    feq.s zero, fa1, fa0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"one", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ord(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ord:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa1, fa1
-; RV32IF-NEXT:    feq.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ord:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa1, fa1
-; RV64IF-NEXT:    feq.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_ord:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa1, fa1
+; CHECKIF-NEXT:    feq.s a1, fa0, fa0
+; CHECKIF-NEXT:    and a0, a1, a0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ord:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ord", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 ; FIXME: We only need one frflags before the two flts and one fsflags after the
 ; two flts.
 define i32 @fcmp_ueq(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ueq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    flt.s a1, fa0, fa1
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    feq.s zero, fa0, fa1
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    flt.s a2, fa1, fa0
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    or a0, a2, a1
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    feq.s zero, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ueq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    flt.s a1, fa0, fa1
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    feq.s zero, fa0, fa1
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    flt.s a2, fa1, fa0
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    or a0, a2, a1
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    feq.s zero, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_ueq:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    frflags a0
+; CHECKIF-NEXT:    flt.s a1, fa0, fa1
+; CHECKIF-NEXT:    fsflags a0
+; CHECKIF-NEXT:    feq.s zero, fa0, fa1
+; CHECKIF-NEXT:    frflags a0
+; CHECKIF-NEXT:    flt.s a2, fa1, fa0
+; CHECKIF-NEXT:    fsflags a0
+; CHECKIF-NEXT:    or a0, a2, a1
+; CHECKIF-NEXT:    xori a0, a0, 1
+; CHECKIF-NEXT:    feq.s zero, fa1, fa0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ueq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ugt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ugt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    fle.s a1, fa0, fa1
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    xori a0, a1, 1
-; RV32IF-NEXT:    feq.s zero, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ugt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    fle.s a1, fa0, fa1
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    xori a0, a1, 1
-; RV64IF-NEXT:    feq.s zero, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_ugt:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    frflags a0
+; CHECKIF-NEXT:    fle.s a1, fa0, fa1
+; CHECKIF-NEXT:    fsflags a0
+; CHECKIF-NEXT:    xori a0, a1, 1
+; CHECKIF-NEXT:    feq.s zero, fa0, fa1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uge(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_uge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    flt.s a1, fa0, fa1
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    xori a0, a1, 1
-; RV32IF-NEXT:    feq.s zero, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_uge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    flt.s a1, fa0, fa1
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    xori a0, a1, 1
-; RV64IF-NEXT:    feq.s zero, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_uge:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    frflags a0
+; CHECKIF-NEXT:    flt.s a1, fa0, fa1
+; CHECKIF-NEXT:    fsflags a0
+; CHECKIF-NEXT:    xori a0, a1, 1
+; CHECKIF-NEXT:    feq.s zero, fa0, fa1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ult(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ult:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    fle.s a1, fa1, fa0
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    xori a0, a1, 1
-; RV32IF-NEXT:    feq.s zero, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ult:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    fle.s a1, fa1, fa0
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    xori a0, a1, 1
-; RV64IF-NEXT:    feq.s zero, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_ult:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    frflags a0
+; CHECKIF-NEXT:    fle.s a1, fa1, fa0
+; CHECKIF-NEXT:    fsflags a0
+; CHECKIF-NEXT:    xori a0, a1, 1
+; CHECKIF-NEXT:    feq.s zero, fa1, fa0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ult:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ult", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ule(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ule:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    flt.s a1, fa1, fa0
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    xori a0, a1, 1
-; RV32IF-NEXT:    feq.s zero, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ule:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    flt.s a1, fa1, fa0
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    xori a0, a1, 1
-; RV64IF-NEXT:    feq.s zero, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_ule:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    frflags a0
+; CHECKIF-NEXT:    flt.s a1, fa1, fa0
+; CHECKIF-NEXT:    fsflags a0
+; CHECKIF-NEXT:    xori a0, a1, 1
+; CHECKIF-NEXT:    feq.s zero, fa1, fa0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ule", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_une(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_une:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa1
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_une:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa1
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_une:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa0, fa1
+; CHECKIF-NEXT:    xori a0, a0, 1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_une:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __nesf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"une", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uno(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_uno:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa1, fa1
-; RV32IF-NEXT:    feq.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_uno:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa1, fa1
-; RV64IF-NEXT:    feq.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_uno:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa1, fa1
+; CHECKIF-NEXT:    feq.s a1, fa0, fa0
+; CHECKIF-NEXT:    and a0, a1, a0
+; CHECKIF-NEXT:    xori a0, a0, 1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uno:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"uno", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_oeq(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_oeq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    fle.s a1, fa0, fa1
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_oeq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    fle.s a1, fa0, fa1
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmps_oeq:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fle.s a0, fa1, fa0
+; CHECKIF-NEXT:    fle.s a1, fa0, fa1
+; CHECKIF-NEXT:    and a0, a1, a0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_oeq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __eqsf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"oeq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 declare i1 @llvm.experimental.constrained.fcmps.f32(float, float, metadata, metadata)
 
 define i32 @fcmps_ogt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ogt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_ogt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmps_ogt:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa1, fa0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_oge(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_oge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_oge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmps_oge:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fle.s a0, fa1, fa0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_olt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_olt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_olt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmps_olt:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa0, fa1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_olt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ole(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ole:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_ole:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmps_ole:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fle.s a0, fa0, fa1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ole:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_one(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_one:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    flt.s a1, fa1, fa0
-; RV32IF-NEXT:    or a0, a1, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_one:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    flt.s a1, fa1, fa0
-; RV64IF-NEXT:    or a0, a1, a0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmps_one:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa0, fa1
+; CHECKIF-NEXT:    flt.s a1, fa1, fa0
+; CHECKIF-NEXT:    or a0, a1, a0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"one", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ord(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ord:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa1
-; RV32IF-NEXT:    fle.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_ord:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa1
-; RV64IF-NEXT:    fle.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmps_ord:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fle.s a0, fa1, fa1
+; CHECKIF-NEXT:    fle.s a1, fa0, fa0
+; CHECKIF-NEXT:    and a0, a1, a0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ord:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ord", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ueq(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ueq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    flt.s a1, fa1, fa0
-; RV32IF-NEXT:    or a0, a1, a0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_ueq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    flt.s a1, fa1, fa0
-; RV64IF-NEXT:    or a0, a1, a0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmps_ueq:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa0, fa1
+; CHECKIF-NEXT:    flt.s a1, fa1, fa0
+; CHECKIF-NEXT:    or a0, a1, a0
+; CHECKIF-NEXT:    xori a0, a0, 1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ueq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ugt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ugt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa0, fa1
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_ugt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa0, fa1
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmps_ugt:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fle.s a0, fa0, fa1
+; CHECKIF-NEXT:    xori a0, a0, 1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_uge(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_uge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_uge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmps_uge:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa0, fa1
+; CHECKIF-NEXT:    xori a0, a0, 1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ult(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ult:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_ult:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmps_ult:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fle.s a0, fa1, fa0
+; CHECKIF-NEXT:    xori a0, a0, 1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ult:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ult", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ule(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ule:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa1, fa0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_ule:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa1, fa0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmps_ule:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa1, fa0
+; CHECKIF-NEXT:    xori a0, a0, 1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ule", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_une(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_une:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    fle.s a1, fa0, fa1
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_une:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    fle.s a1, fa0, fa1
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmps_une:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fle.s a0, fa1, fa0
+; CHECKIF-NEXT:    fle.s a1, fa0, fa1
+; CHECKIF-NEXT:    and a0, a1, a0
+; CHECKIF-NEXT:    xori a0, a0, 1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_une:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __nesf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"une", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_uno(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_uno:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa1
-; RV32IF-NEXT:    fle.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_uno:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa1
-; RV64IF-NEXT:    fle.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmps_uno:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fle.s a0, fa1, fa1
+; CHECKIF-NEXT:    fle.s a1, fa0, fa0
+; CHECKIF-NEXT:    and a0, a1, a0
+; CHECKIF-NEXT:    xori a0, a0, 1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_uno:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

llvm/test/CodeGen/RISCV/float-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=CHECKIF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefix=CHECKIF %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 define i32 @fcmp_false(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_false:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_false:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_false:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    li a0, 0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_false:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a0, 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_false:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 0
 ; RV64I-NEXT:    ret
   %1 = fcmp false float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oeq(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_oeq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_oeq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_oeq:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa0, fa1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oeq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __eqsf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp oeq float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ogt(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ogt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ogt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_ogt:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa1, fa0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ogt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oge(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_oge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_oge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_oge:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fle.s a0, fa1, fa0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp oge float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_olt(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_olt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_olt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_olt:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa0, fa1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_olt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp olt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ole(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ole:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ole:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_ole:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fle.s a0, fa0, fa1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ole:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ole float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_one(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_one:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    flt.s a1, fa1, fa0
-; RV32IF-NEXT:    or a0, a1, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_one:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    flt.s a1, fa1, fa0
-; RV64IF-NEXT:    or a0, a1, a0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_one:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa0, fa1
+; CHECKIF-NEXT:    flt.s a1, fa1, fa0
+; CHECKIF-NEXT:    or a0, a1, a0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = fcmp one float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ord(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ord:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa1, fa1
-; RV32IF-NEXT:    feq.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ord:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa1, fa1
-; RV64IF-NEXT:    feq.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_ord:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa1, fa1
+; CHECKIF-NEXT:    feq.s a1, fa0, fa0
+; CHECKIF-NEXT:    and a0, a1, a0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ord:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ord float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ueq(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ueq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    flt.s a1, fa1, fa0
-; RV32IF-NEXT:    or a0, a1, a0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ueq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    flt.s a1, fa1, fa0
-; RV64IF-NEXT:    or a0, a1, a0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_ueq:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa0, fa1
+; CHECKIF-NEXT:    flt.s a1, fa1, fa0
+; CHECKIF-NEXT:    or a0, a1, a0
+; CHECKIF-NEXT:    xori a0, a0, 1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ueq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = fcmp ueq float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ugt(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ugt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa0, fa1
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ugt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa0, fa1
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_ugt:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fle.s a0, fa0, fa1
+; CHECKIF-NEXT:    xori a0, a0, 1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ugt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uge(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_uge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_uge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_uge:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa0, fa1
+; CHECKIF-NEXT:    xori a0, a0, 1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp uge float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ult(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ult:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ult:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_ult:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fle.s a0, fa1, fa0
+; CHECKIF-NEXT:    xori a0, a0, 1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ult:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ult float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ule(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ule:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa1, fa0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ule:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa1, fa0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_ule:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa1, fa0
+; CHECKIF-NEXT:    xori a0, a0, 1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ule float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_une(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_une:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa1
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_une:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa1
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_une:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa0, fa1
+; CHECKIF-NEXT:    xori a0, a0, 1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_une:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __nesf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp une float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uno(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_uno:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa1, fa1
-; RV32IF-NEXT:    feq.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_uno:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa1, fa1
-; RV64IF-NEXT:    feq.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_uno:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa1, fa1
+; CHECKIF-NEXT:    feq.s a1, fa0, fa0
+; CHECKIF-NEXT:    and a0, a1, a0
+; CHECKIF-NEXT:    xori a0, a0, 1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uno:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp uno float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_true(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_true:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    li a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_true:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    li a0, 1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fcmp_true:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    li a0, 1
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_true:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_true:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 1
 ; RV64I-NEXT:    ret
   %1 = fcmp true float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/float-imm.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck %s
 
 ; TODO: constant pool shouldn't be necessary for RV64IF.
 define float @float_imm() nounwind {
-; RV32IF-LABEL: float_imm:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    lui a0, %hi(.LCPI0_0)
-; RV32IF-NEXT:    flw fa0, %lo(.LCPI0_0)(a0)
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: float_imm:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    lui a0, %hi(.LCPI0_0)
-; RV64IF-NEXT:    flw fa0, %lo(.LCPI0_0)(a0)
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: float_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI0_0)
+; CHECK-NEXT:    flw fa0, %lo(.LCPI0_0)(a0)
+; CHECK-NEXT:    ret
   ret float 3.14159274101257324218750
 }
 
 define float @float_imm_op(float %a) nounwind {
-; RV32IF-LABEL: float_imm_op:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV32IF-NEXT:    flw ft0, %lo(.LCPI1_0)(a0)
-; RV32IF-NEXT:    fadd.s fa0, fa0, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: float_imm_op:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV64IF-NEXT:    flw ft0, %lo(.LCPI1_0)(a0)
-; RV64IF-NEXT:    fadd.s fa0, fa0, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: float_imm_op:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI1_0)
+; CHECK-NEXT:    flw ft0, %lo(.LCPI1_0)(a0)
+; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    ret
   %1 = fadd float %a, 1.0
   ret float %1
 }

llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f \
 ; RUN:   -verify-machineinstrs -disable-strictnode-mutation -target-abi=ilp32f \
-; RUN:   | FileCheck -check-prefix=RV32IF %s
+; RUN:   | FileCheck -check-prefixes=CHECKIF,RV32IF %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f \
 ; RUN:   -verify-machineinstrs -disable-strictnode-mutation -target-abi=lp64f \
-; RUN:   | FileCheck -check-prefix=RV64IF %s
+; RUN:   | FileCheck -check-prefixes=CHECKIF,RV64IF %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
 ; RUN:   -verify-machineinstrs -disable-strictnode-mutation \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
 ; RUN:   -verify-machineinstrs -disable-strictnode-mutation \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 declare float @llvm.experimental.constrained.sqrt.f32(float, metadata, metadata)
 
 define float @sqrt_f32(float %a) nounwind strictfp {
-; RV32IF-LABEL: sqrt_f32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fsqrt.s fa0, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: sqrt_f32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fsqrt.s fa0, fa0
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: sqrt_f32:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fsqrt.s fa0, fa0
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: sqrt_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call sqrtf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.log2.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 
 declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata)
 
 define float @fma_f32(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fma_f32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fma_f32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fma_f32:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fma_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fmaf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %b, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 
 declare float @llvm.experimental.constrained.fmuladd.f32(float, float, float, metadata, metadata)
 
 define float @fmuladd_f32(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fmuladd_f32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmuladd_f32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fmuladd_f32:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
+; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fmuladd_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    call __mulsf3@plt

llvm/test/CodeGen/RISCV/float-isnan.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs \
-; RUN:   < %s | FileCheck -check-prefix=RV32IF %s
+; RUN:   < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs \
-; RUN:   < %s | FileCheck -check-prefix=RV64IF %s
+; RUN:   < %s | FileCheck %s
 
 define zeroext i1 @float_is_nan(float %a) nounwind {
-; RV32IF-LABEL: float_is_nan:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: float_is_nan:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: float_is_nan:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
   %1 = fcmp uno float %a, 0.000000e+00
   ret i1 %1
 }
 
 define zeroext i1 @float_not_nan(float %a) nounwind {
-; RV32IF-LABEL: float_not_nan:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: float_not_nan:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: float_not_nan:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    ret
   %1 = fcmp ord float %a, 0.000000e+00
   ret i1 %1
 }

llvm/test/CodeGen/RISCV/float-mem.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIF,RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECKIF,RV64IF %s
 
 define dso_local float @flw(float *%a) nounwind {
-; RV32IF-LABEL: flw:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flw ft0, 0(a0)
-; RV32IF-NEXT:    flw ft1, 12(a0)
-; RV32IF-NEXT:    fadd.s fa0, ft0, ft1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: flw:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flw ft0, 0(a0)
-; RV64IF-NEXT:    flw ft1, 12(a0)
-; RV64IF-NEXT:    fadd.s fa0, ft0, ft1
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: flw:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flw ft0, 0(a0)
+; CHECKIF-NEXT:    flw ft1, 12(a0)
+; CHECKIF-NEXT:    fadd.s fa0, ft0, ft1
+; CHECKIF-NEXT:    ret
   %1 = load float, float* %a
   %2 = getelementptr float, float* %a, i32 3
   %3 = load float, float* %2
 ; Use both loaded values in an FP op to ensure an flw is used, even for the
 ; soft float ABI
   %4 = fadd float %1, %3
   ret float %4
 }
 
 define dso_local void @fsw(float *%a, float %b, float %c) nounwind {
 ; Use %b and %c in an FP op to ensure floating point registers are used, even
 ; for the soft float ABI
-; RV32IF-LABEL: fsw:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV32IF-NEXT:    fsw ft0, 0(a0)
-; RV32IF-NEXT:    fsw ft0, 32(a0)
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fsw:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV64IF-NEXT:    fsw ft0, 0(a0)
-; RV64IF-NEXT:    fsw ft0, 32(a0)
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: fsw:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fadd.s ft0, fa0, fa1
+; CHECKIF-NEXT:    fsw ft0, 0(a0)
+; CHECKIF-NEXT:    fsw ft0, 32(a0)
+; CHECKIF-NEXT:    ret
   %1 = fadd float %b, %c
   store float %1, float* %a
   %2 = getelementptr float, float* %a, i32 8
   store float %1, float* %2
   ret void
 }
 
 ; Check load and store to a global
 @G = dso_local global float 0.0
 
 define dso_local float @flw_fsw_global(float %a, float %b) nounwind {
 ; Use %a and %b in an FP op to ensure floating point registers are used, even
 ; for the soft float ABI
-; RV32IF-LABEL: flw_fsw_global:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s fa0, fa0, fa1
-; RV32IF-NEXT:    lui a0, %hi(G)
-; RV32IF-NEXT:    flw ft0, %lo(G)(a0)
-; RV32IF-NEXT:    addi a1, a0, %lo(G)
-; RV32IF-NEXT:    fsw fa0, %lo(G)(a0)
-; RV32IF-NEXT:    flw ft0, 36(a1)
-; RV32IF-NEXT:    fsw fa0, 36(a1)
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: flw_fsw_global:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s fa0, fa0, fa1
-; RV64IF-NEXT:    lui a0, %hi(G)
-; RV64IF-NEXT:    flw ft0, %lo(G)(a0)
-; RV64IF-NEXT:    addi a1, a0, %lo(G)
-; RV64IF-NEXT:    fsw fa0, %lo(G)(a0)
-; RV64IF-NEXT:    flw ft0, 36(a1)
-; RV64IF-NEXT:    fsw fa0, 36(a1)
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: flw_fsw_global:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fadd.s fa0, fa0, fa1
+; CHECKIF-NEXT:    lui a0, %hi(G)
+; CHECKIF-NEXT:    flw ft0, %lo(G)(a0)
+; CHECKIF-NEXT:    addi a1, a0, %lo(G)
+; CHECKIF-NEXT:    fsw fa0, %lo(G)(a0)
+; CHECKIF-NEXT:    flw ft0, 36(a1)
+; CHECKIF-NEXT:    fsw fa0, 36(a1)
+; CHECKIF-NEXT:    ret
   %1 = fadd float %a, %b
   %2 = load volatile float, float* @G
   store float %1, float* @G
   %3 = getelementptr float, float* @G, i32 9
   %4 = load volatile float, float* %3
   store float %1, float* %3
   ret float %1
 }

llvm/test/CodeGen/RISCV/float-round-conv-sat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIF,RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECKIF,RV64IF %s
 
 define signext i32 @test_floor_si32(float %x) {
-; RV32IF-LABEL: test_floor_si32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB0_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rdn
-; RV32IF-NEXT:  .LBB0_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_floor_si32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB0_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rdn
-; RV64IF-NEXT:  .LBB0_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: test_floor_si32:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa0, fa0
+; CHECKIF-NEXT:    beqz a0, .LBB0_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fcvt.w.s a0, fa0, rdn
+; CHECKIF-NEXT:  .LBB0_2:
+; CHECKIF-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_floor_si64(float %x) nounwind {
 ; RV32IF-LABEL: test_floor_si64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:  .LBB1_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_floor_ui32(float %x) {
-; RV32IF-LABEL: test_floor_ui32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB2_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rdn
-; RV32IF-NEXT:  .LBB2_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_floor_ui32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB2_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rdn
-; RV64IF-NEXT:  .LBB2_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: test_floor_ui32:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa0, fa0
+; CHECKIF-NEXT:    beqz a0, .LBB2_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rdn
+; CHECKIF-NEXT:  .LBB2_2:
+; CHECKIF-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_floor_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_floor_ui64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:  .LBB3_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_ceil_si32(float %x) {
-; RV32IF-LABEL: test_ceil_si32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB4_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rup
-; RV32IF-NEXT:  .LBB4_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_ceil_si32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB4_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rup
-; RV64IF-NEXT:  .LBB4_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: test_ceil_si32:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa0, fa0
+; CHECKIF-NEXT:    beqz a0, .LBB4_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fcvt.w.s a0, fa0, rup
+; CHECKIF-NEXT:  .LBB4_2:
+; CHECKIF-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_ceil_si64(float %x) nounwind {
 ; RV32IF-LABEL: test_ceil_si64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:  .LBB5_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_ceil_ui32(float %x) {
-; RV32IF-LABEL: test_ceil_ui32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB6_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rup
-; RV32IF-NEXT:  .LBB6_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_ceil_ui32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB6_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rup
-; RV64IF-NEXT:  .LBB6_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: test_ceil_ui32:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa0, fa0
+; CHECKIF-NEXT:    beqz a0, .LBB6_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rup
+; CHECKIF-NEXT:  .LBB6_2:
+; CHECKIF-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_ceil_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_ceil_ui64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:  .LBB7_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_trunc_si32(float %x) {
-; RV32IF-LABEL: test_trunc_si32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB8_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV32IF-NEXT:  .LBB8_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_trunc_si32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB8_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV64IF-NEXT:  .LBB8_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: test_trunc_si32:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa0, fa0
+; CHECKIF-NEXT:    beqz a0, .LBB8_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fcvt.w.s a0, fa0, rtz
+; CHECKIF-NEXT:  .LBB8_2:
+; CHECKIF-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_trunc_si64(float %x) nounwind {
 ; RV32IF-LABEL: test_trunc_si64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:  .LBB9_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_trunc_ui32(float %x) {
-; RV32IF-LABEL: test_trunc_ui32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB10_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV32IF-NEXT:  .LBB10_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_trunc_ui32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB10_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV64IF-NEXT:  .LBB10_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: test_trunc_ui32:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa0, fa0
+; CHECKIF-NEXT:    beqz a0, .LBB10_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rtz
+; CHECKIF-NEXT:  .LBB10_2:
+; CHECKIF-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_trunc_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_trunc_ui64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:  .LBB11_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_round_si32(float %x) {
-; RV32IF-LABEL: test_round_si32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB12_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rmm
-; RV32IF-NEXT:  .LBB12_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_round_si32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB12_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rmm
-; RV64IF-NEXT:  .LBB12_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: test_round_si32:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa0, fa0
+; CHECKIF-NEXT:    beqz a0, .LBB12_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fcvt.w.s a0, fa0, rmm
+; CHECKIF-NEXT:  .LBB12_2:
+; CHECKIF-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_round_si64(float %x) nounwind {
 ; RV32IF-LABEL: test_round_si64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:  .LBB13_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_round_ui32(float %x) {
-; RV32IF-LABEL: test_round_ui32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB14_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rmm
-; RV32IF-NEXT:  .LBB14_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_round_ui32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB14_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rmm
-; RV64IF-NEXT:  .LBB14_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: test_round_ui32:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa0, fa0
+; CHECKIF-NEXT:    beqz a0, .LBB14_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rmm
+; CHECKIF-NEXT:  .LBB14_2:
+; CHECKIF-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_round_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_round_ui64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:  .LBB15_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_roundeven_si32(float %x) {
-; RV32IF-LABEL: test_roundeven_si32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB16_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rne
-; RV32IF-NEXT:  .LBB16_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_roundeven_si32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB16_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rne
-; RV64IF-NEXT:  .LBB16_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: test_roundeven_si32:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa0, fa0
+; CHECKIF-NEXT:    beqz a0, .LBB16_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fcvt.w.s a0, fa0, rne
+; CHECKIF-NEXT:  .LBB16_2:
+; CHECKIF-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_roundeven_si64(float %x) nounwind {
 ; RV32IF-LABEL: test_roundeven_si64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:  .LBB17_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_roundeven_ui32(float %x) {
-; RV32IF-LABEL: test_roundeven_ui32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB18_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rne
-; RV32IF-NEXT:  .LBB18_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_roundeven_ui32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB18_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rne
-; RV64IF-NEXT:  .LBB18_2:
-; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: test_roundeven_ui32:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa0, fa0
+; CHECKIF-NEXT:    beqz a0, .LBB18_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rne
+; CHECKIF-NEXT:  .LBB18_2:
+; CHECKIF-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_roundeven_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_roundeven_ui64:
 ; RV32IF:       # %bb.0:

llvm/test/CodeGen/RISCV/float-select-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck %s
 
 define float @select_fcmp_false(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_false:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_false:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: select_fcmp_false:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.s fa0, fa1
+; CHECK-NEXT:    ret
   %1 = fcmp false float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_oeq(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_oeq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa1
-; RV32IF-NEXT:    bnez a0, .LBB1_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB1_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_oeq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa1
-; RV64IF-NEXT:    bnez a0, .LBB1_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB1_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: select_fcmp_oeq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa1
+; CHECK-NEXT:    bnez a0, .LBB1_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.s fa0, fa1
+; CHECK-NEXT:  .LBB1_2:
+; CHECK-NEXT:    ret
   %1 = fcmp oeq float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ogt(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_ogt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa1, fa0
-; RV32IF-NEXT:    bnez a0, .LBB2_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB2_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_ogt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa1, fa0
-; RV64IF-NEXT:    bnez a0, .LBB2_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB2_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: select_fcmp_ogt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa1, fa0
+; CHECK-NEXT:    bnez a0, .LBB2_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.s fa0, fa1
+; CHECK-NEXT:  .LBB2_2:
+; CHECK-NEXT:    ret
   %1 = fcmp ogt float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_oge(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_oge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    bnez a0, .LBB3_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB3_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_oge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    bnez a0, .LBB3_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB3_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: select_fcmp_oge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa1, fa0
+; CHECK-NEXT:    bnez a0, .LBB3_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.s fa0, fa1
+; CHECK-NEXT:  .LBB3_2:
+; CHECK-NEXT:    ret
   %1 = fcmp oge float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_olt(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_olt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    bnez a0, .LBB4_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB4_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_olt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    bnez a0, .LBB4_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB4_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: select_fcmp_olt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    bnez a0, .LBB4_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.s fa0, fa1
+; CHECK-NEXT:  .LBB4_2:
+; CHECK-NEXT:    ret
   %1 = fcmp olt float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ole(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_ole:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa0, fa1
-; RV32IF-NEXT:    bnez a0, .LBB5_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB5_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_ole:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa0, fa1
-; RV64IF-NEXT:    bnez a0, .LBB5_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB5_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: select_fcmp_ole:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa0, fa1
+; CHECK-NEXT:    bnez a0, .LBB5_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.s fa0, fa1
+; CHECK-NEXT:  .LBB5_2:
+; CHECK-NEXT:    ret
   %1 = fcmp ole float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_one(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_one:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    flt.s a1, fa1, fa0
-; RV32IF-NEXT:    or a0, a1, a0
-; RV32IF-NEXT:    bnez a0, .LBB6_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB6_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_one:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    flt.s a1, fa1, fa0
-; RV64IF-NEXT:    or a0, a1, a0
-; RV64IF-NEXT:    bnez a0, .LBB6_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB6_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: select_fcmp_one:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    flt.s a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    bnez a0, .LBB6_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.s fa0, fa1
+; CHECK-NEXT:  .LBB6_2:
+; CHECK-NEXT:    ret
   %1 = fcmp one float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ord(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_ord:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa1, fa1
-; RV32IF-NEXT:    feq.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    bnez a0, .LBB7_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB7_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_ord:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa1, fa1
-; RV64IF-NEXT:    feq.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    bnez a0, .LBB7_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB7_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: select_fcmp_ord:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa1, fa1
+; CHECK-NEXT:    feq.s a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    bnez a0, .LBB7_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.s fa0, fa1
+; CHECK-NEXT:  .LBB7_2:
+; CHECK-NEXT:    ret
   %1 = fcmp ord float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ueq(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_ueq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    flt.s a1, fa1, fa0
-; RV32IF-NEXT:    or a0, a1, a0
-; RV32IF-NEXT:    beqz a0, .LBB8_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB8_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_ueq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    flt.s a1, fa1, fa0
-; RV64IF-NEXT:    or a0, a1, a0
-; RV64IF-NEXT:    beqz a0, .LBB8_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB8_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: select_fcmp_ueq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    flt.s a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    beqz a0, .LBB8_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.s fa0, fa1
+; CHECK-NEXT:  .LBB8_2:
+; CHECK-NEXT:    ret
   %1 = fcmp ueq float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ugt(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_ugt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa0, fa1
-; RV32IF-NEXT:    beqz a0, .LBB9_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB9_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_ugt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa0, fa1
-; RV64IF-NEXT:    beqz a0, .LBB9_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB9_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: select_fcmp_ugt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa0, fa1
+; CHECK-NEXT:    beqz a0, .LBB9_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.s fa0, fa1
+; CHECK-NEXT:  .LBB9_2:
+; CHECK-NEXT:    ret
   %1 = fcmp ugt float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_uge(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_uge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    beqz a0, .LBB10_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB10_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_uge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    beqz a0, .LBB10_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB10_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: select_fcmp_uge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    beqz a0, .LBB10_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.s fa0, fa1
+; CHECK-NEXT:  .LBB10_2:
+; CHECK-NEXT:    ret
   %1 = fcmp uge float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ult(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_ult:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    beqz a0, .LBB11_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB11_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_ult:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    beqz a0, .LBB11_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB11_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: select_fcmp_ult:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa1, fa0
+; CHECK-NEXT:    beqz a0, .LBB11_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.s fa0, fa1
+; CHECK-NEXT:  .LBB11_2:
+; CHECK-NEXT:    ret
   %1 = fcmp ult float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ule(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_ule:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa1, fa0
-; RV32IF-NEXT:    beqz a0, .LBB12_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB12_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_ule:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa1, fa0
-; RV64IF-NEXT:    beqz a0, .LBB12_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB12_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: select_fcmp_ule:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa1, fa0
+; CHECK-NEXT:    beqz a0, .LBB12_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.s fa0, fa1
+; CHECK-NEXT:  .LBB12_2:
+; CHECK-NEXT:    ret
   %1 = fcmp ule float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_une(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_une:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa1
-; RV32IF-NEXT:    beqz a0, .LBB13_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB13_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_une:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa1
-; RV64IF-NEXT:    beqz a0, .LBB13_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB13_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: select_fcmp_une:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa1
+; CHECK-NEXT:    beqz a0, .LBB13_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.s fa0, fa1
+; CHECK-NEXT:  .LBB13_2:
+; CHECK-NEXT:    ret
   %1 = fcmp une float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_uno(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_uno:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa1, fa1
-; RV32IF-NEXT:    feq.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    beqz a0, .LBB14_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fmv.s fa0, fa1
-; RV32IF-NEXT:  .LBB14_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_uno:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa1, fa1
-; RV64IF-NEXT:    feq.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    beqz a0, .LBB14_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fmv.s fa0, fa1
-; RV64IF-NEXT:  .LBB14_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: select_fcmp_uno:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa1, fa1
+; CHECK-NEXT:    feq.s a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    beqz a0, .LBB14_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.s fa0, fa1
+; CHECK-NEXT:  .LBB14_2:
+; CHECK-NEXT:    ret
   %1 = fcmp uno float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_true(float %a, float %b) nounwind {
-; RV32IF-LABEL: select_fcmp_true:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: select_fcmp_true:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: select_fcmp_true:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ret
   %1 = fcmp true float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 ; Ensure that ISel succeeds for a select+fcmp that has an i32 result type.
 define i32 @i32_select_fcmp_oeq(float %a, float %b, i32 %c, i32 %d) nounwind {
-; RV32IF-LABEL: i32_select_fcmp_oeq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a2, fa0, fa1
-; RV32IF-NEXT:    bnez a2, .LBB16_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    mv a0, a1
-; RV32IF-NEXT:  .LBB16_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: i32_select_fcmp_oeq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a2, fa0, fa1
-; RV64IF-NEXT:    bnez a2, .LBB16_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    mv a0, a1
-; RV64IF-NEXT:  .LBB16_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: i32_select_fcmp_oeq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a2, fa0, fa1
+; CHECK-NEXT:    bnez a2, .LBB16_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    mv a0, a1
+; CHECK-NEXT:  .LBB16_2:
+; CHECK-NEXT:    ret
   %1 = fcmp oeq float %a, %b
   %2 = select i1 %1, i32 %c, i32 %d
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/half-arith-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
-; RUN:   -disable-strictnode-mutation -target-abi ilp32f < %s \
-; RUN:    | FileCheck -check-prefix=RV32IZFH %s
+; RUN:   -disable-strictnode-mutation -target-abi ilp32f < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
-; RUN:   -disable-strictnode-mutation -target-abi lp64f < %s \
-; RUN:   | FileCheck -check-prefix=RV64IZFH %s
+; RUN:   -disable-strictnode-mutation -target-abi lp64f < %s | FileCheck %s
 
 ; FIXME: We can't test without Zfh because soft promote legalization isn't
 ; implemented in SelectionDAG for STRICT nodes.
 
 define half @fadd_h(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fadd_h:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fadd.h fa0, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fadd_h:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fadd.h fa0, fa0, fa1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fadd_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fadd.h fa0, fa0, fa1
+; CHECK-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.fadd.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.fadd.f16(half, half, metadata, metadata)
 
 define half @fsub_h(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fsub_h:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fsub.h fa0, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fsub_h:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fsub.h fa0, fa0, fa1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fsub_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fsub.h fa0, fa0, fa1
+; CHECK-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.fsub.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.fsub.f16(half, half, metadata, metadata)
 
 define half @fmul_h(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fmul_h:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmul.h fa0, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fmul_h:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmul.h fa0, fa0, fa1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fmul_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmul.h fa0, fa0, fa1
+; CHECK-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.fmul.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.fmul.f16(half, half, metadata, metadata)
 
 define half @fdiv_h(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fdiv_h:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fdiv.h fa0, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fdiv_h:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fdiv.h fa0, fa0, fa1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fdiv_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fdiv.h fa0, fa0, fa1
+; CHECK-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.fdiv.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.fdiv.f16(half, half, metadata, metadata)
 
 define half @fsqrt_h(half %a) nounwind strictfp {
-; RV32IZFH-LABEL: fsqrt_h:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fsqrt.h fa0, fa0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fsqrt_h:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fsqrt.h fa0, fa0
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fsqrt_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fsqrt.h fa0, fa0
+; CHECK-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.sqrt.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata)
 
 ; FIXME: fminnum/fmaxnum need libcalls to handle SNaN, but we don't have f16
 ; libcalls and don't support promotion yet.
 ;define half @fmin_h(half %a, half %b) nounwind strictfp {
 ;  %1 = call half @llvm.experimental.constrained.minnum.f16(half %a, half %b, metadata !"fpexcept.strict") strictfp
 ;  ret half %1
 ;}
 ;declare half @llvm.experimental.constrained.minnum.f16(half, half, metadata) strictfp
 ;
 ;define half @fmax_h(half %a, half %b) nounwind strictfp {
 ;  %1 = call half @llvm.experimental.constrained.maxnum.f16(half %a, half %b, metadata !"fpexcept.strict") strictfp
 ;  ret half %1
 ;}
 ;declare half @llvm.experimental.constrained.maxnum.f16(half, half, metadata) strictfp
 
 define half @fmadd_h(half %a, half %b, half %c) nounwind strictfp {
-; RV32IZFH-LABEL: fmadd_h:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmadd.h fa0, fa0, fa1, fa2
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fmadd_h:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmadd.h fa0, fa0, fa1, fa2
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fmadd_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmadd.h fa0, fa0, fa1, fa2
+; CHECK-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %b, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.fma.f16(half, half, half, metadata, metadata) strictfp
 
 define half @fmsub_h(half %a, half %b, half %c) nounwind strictfp {
-; RV32IZFH-LABEL: fmsub_h:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT:    fmsub.h fa0, fa0, fa1, ft0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fmsub_h:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT:    fmsub.h fa0, fa0, fa1, ft0
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fmsub_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.h.x ft0, zero
+; CHECK-NEXT:    fadd.h ft0, fa2, ft0
+; CHECK-NEXT:    fmsub.h fa0, fa0, fa1, ft0
+; CHECK-NEXT:    ret
   %c_ = fadd half 0.0, %c ; avoid negation using xor
   %negc = fneg half %c_
   %1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %b, half %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fnmadd_h(half %a, half %b, half %c) nounwind strictfp {
-; RV32IZFH-LABEL: fnmadd_h:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft1, fa0, ft0
-; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT:    fnmadd.h fa0, ft1, fa1, ft0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fnmadd_h:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft1, fa0, ft0
-; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT:    fnmadd.h fa0, ft1, fa1, ft0
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fnmadd_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.h.x ft0, zero
+; CHECK-NEXT:    fadd.h ft1, fa0, ft0
+; CHECK-NEXT:    fadd.h ft0, fa2, ft0
+; CHECK-NEXT:    fnmadd.h fa0, ft1, fa1, ft0
+; CHECK-NEXT:    ret
   %a_ = fadd half 0.0, %a
   %c_ = fadd half 0.0, %c
   %nega = fneg half %a_
   %negc = fneg half %c_
   %1 = call half @llvm.experimental.constrained.fma.f16(half %nega, half %b, half %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fnmadd_h_2(half %a, half %b, half %c) nounwind strictfp {
-; RV32IZFH-LABEL: fnmadd_h_2:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft1, fa1, ft0
-; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT:    fnmadd.h fa0, ft1, fa0, ft0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fnmadd_h_2:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft1, fa1, ft0
-; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT:    fnmadd.h fa0, ft1, fa0, ft0
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fnmadd_h_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.h.x ft0, zero
+; CHECK-NEXT:    fadd.h ft1, fa1, ft0
+; CHECK-NEXT:    fadd.h ft0, fa2, ft0
+; CHECK-NEXT:    fnmadd.h fa0, ft1, fa0, ft0
+; CHECK-NEXT:    ret
   %b_ = fadd half 0.0, %b
   %c_ = fadd half 0.0, %c
   %negb = fneg half %b_
   %negc = fneg half %c_
   %1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %negb, half %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fnmsub_h(half %a, half %b, half %c) nounwind strictfp {
-; RV32IZFH-LABEL: fnmsub_h:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft0, fa0, ft0
-; RV32IZFH-NEXT:    fnmsub.h fa0, ft0, fa1, fa2
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fnmsub_h:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft0, fa0, ft0
-; RV64IZFH-NEXT:    fnmsub.h fa0, ft0, fa1, fa2
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fnmsub_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.h.x ft0, zero
+; CHECK-NEXT:    fadd.h ft0, fa0, ft0
+; CHECK-NEXT:    fnmsub.h fa0, ft0, fa1, fa2
+; CHECK-NEXT:    ret
   %a_ = fadd half 0.0, %a
   %nega = fneg half %a_
   %1 = call half @llvm.experimental.constrained.fma.f16(half %nega, half %b, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fnmsub_h_2(half %a, half %b, half %c) nounwind strictfp {
-; RV32IZFH-LABEL: fnmsub_h_2:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft0, fa1, ft0
-; RV32IZFH-NEXT:    fnmsub.h fa0, ft0, fa0, fa2
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fnmsub_h_2:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft0, fa1, ft0
-; RV64IZFH-NEXT:    fnmsub.h fa0, ft0, fa0, fa2
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fnmsub_h_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.h.x ft0, zero
+; CHECK-NEXT:    fadd.h ft0, fa1, ft0
+; CHECK-NEXT:    fnmsub.h fa0, ft0, fa0, fa2
+; CHECK-NEXT:    ret
   %b_ = fadd half 0.0, %b
   %negb = fneg half %b_
   %1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %negb, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }

llvm/test/CodeGen/RISCV/half-arith.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
-; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
+; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=CHECKIZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
-; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=CHECKIZFH %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 ; These tests are each targeted at a particular RISC-V FPU instruction.
 ; Compares and conversions can be found in half-fcmp.ll and half-convert.ll
 ; respectively. Some other half-*.ll files in this folder exercise LLVM IR
 ; instructions that don't directly match a RISC-V instruction.
 
 define half @fadd_s(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fadd_s:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fadd.h fa0, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fadd_s:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fadd.h fa0, fa0, fa1
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fadd_s:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fadd.h fa0, fa0, fa1
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = fadd half %a, %b
   ret half %1
 }
 
 define half @fsub_s(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fsub_s:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fsub.h fa0, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fsub_s:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fsub.h fa0, fa0, fa1
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fsub_s:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fsub.h fa0, fa0, fa1
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = fsub half %a, %b
   ret half %1
 }
 
 define half @fmul_s(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fmul_s:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmul.h fa0, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fmul_s:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmul.h fa0, fa0, fa1
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fmul_s:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fmul.h fa0, fa0, fa1
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fmul_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = fmul half %a, %b
   ret half %1
 }
 
 define half @fdiv_s(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fdiv_s:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fdiv.h fa0, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fdiv_s:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fdiv.h fa0, fa0, fa1
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fdiv_s:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fdiv.h fa0, fa0, fa1
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fdiv_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ret
   %1 = fdiv half %a, %b
   ret half %1
 }
 
 declare half @llvm.sqrt.f16(half)
 
 define half @fsqrt_s(half %a) nounwind {
-; RV32IZFH-LABEL: fsqrt_s:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fsqrt.h fa0, fa0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fsqrt_s:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fsqrt.h fa0, fa0
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fsqrt_s:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fsqrt.h fa0, fa0
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fsqrt_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt

 ; RV64I-NEXT:    ret
   %1 = call half @llvm.sqrt.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.copysign.f16(half, half)
 
 define half @fsgnj_s(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fsgnj_s:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fsgnj.h fa0, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fsgnj_s:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fsgnj.h fa0, fa0, fa1
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fsgnj_s:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fsgnj.h fa0, fa0, fa1
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fsgnj_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a2, 1048568
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    slli a0, a0, 17
 ; RV32I-NEXT:    srli a0, a0, 17
 ; RV32I-NEXT:    or a0, a0, a1

 ; RV64I-NEXT:    ret
   %1 = call half @llvm.copysign.f16(half %a, half %b)
   ret half %1
 }
 
 ; This function performs extra work to ensure that
 ; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
 define i32 @fneg_s(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fneg_s:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fadd.h ft0, fa0, fa0
-; RV32IZFH-NEXT:    fneg.h ft1, ft0
-; RV32IZFH-NEXT:    feq.h a0, ft0, ft1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fneg_s:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fadd.h ft0, fa0, fa0
-; RV64IZFH-NEXT:    fneg.h ft1, ft0
-; RV64IZFH-NEXT:    feq.h a0, ft0, ft1
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fneg_s:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fadd.h ft0, fa0, fa0
+;CHECKIZFH-NEXT:    fneg.h ft1, ft0
+;CHECKIZFH-NEXT:    feq.h a0, ft0, ft1
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fneg_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    lui a1, 16
; RV64I-NEXT:    ret
   %3 = fcmp oeq half %1, %2
   %4 = zext i1 %3 to i32
   ret i32 %4
 }
 
 ; This function performs extra work to ensure that
 ; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
 define half @fsgnjn_s(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fsgnjn_s:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fadd.h ft0, fa0, fa1
-; RV32IZFH-NEXT:    fsgnjn.h fa0, fa0, ft0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fsgnjn_s:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fadd.h ft0, fa0, fa1
-; RV64IZFH-NEXT:    fsgnjn.h fa0, fa0, ft0
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fsgnjn_s:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fadd.h ft0, fa0, fa1
+;CHECKIZFH-NEXT:    fsgnjn.h fa0, fa0, ft0
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fsgnjn_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   ret half %3
 }
 
 declare half @llvm.fabs.f16(half)
 
 ; This function performs extra work to ensure that
 ; DAGCombiner::visitBITCAST doesn't replace the fabs with an and.
 define half @fabs_s(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fabs_s:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fadd.h ft0, fa0, fa1
-; RV32IZFH-NEXT:    fabs.h ft1, ft0
-; RV32IZFH-NEXT:    fadd.h fa0, ft1, ft0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fabs_s:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fadd.h ft0, fa0, fa1
-; RV64IZFH-NEXT:    fabs.h ft1, ft0
-; RV64IZFH-NEXT:    fadd.h fa0, ft1, ft0
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fabs_s:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fadd.h ft0, fa0, fa1
+;CHECKIZFH-NEXT:    fabs.h ft1, ft0
+;CHECKIZFH-NEXT:    fadd.h fa0, ft1, ft0
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fabs_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %2 = call half @llvm.fabs.f16(half %1)
   %3 = fadd half %2, %1
   ret half %3
 }
 
 declare half @llvm.minnum.f16(half, half)
 
 define half @fmin_s(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fmin_s:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmin.h fa0, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fmin_s:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmin.h fa0, fa0, fa1
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fmin_s:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fmin.h fa0, fa0, fa1
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fmin_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ret
   %1 = call half @llvm.minnum.f16(half %a, half %b)
   ret half %1
 }
 
 declare half @llvm.maxnum.f16(half, half)
 
 define half @fmax_s(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fmax_s:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmax.h fa0, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fmax_s:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmax.h fa0, fa0, fa1
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fmax_s:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fmax.h fa0, fa0, fa1
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fmax_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ret
   %1 = call half @llvm.maxnum.f16(half %a, half %b)
   ret half %1
 }
 
 declare half @llvm.fma.f16(half, half, half)
 
 define half @fmadd_s(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fmadd_s:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmadd.h fa0, fa0, fa1, fa2
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fmadd_s:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmadd.h fa0, fa0, fa1, fa2
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fmadd_s:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fmadd.h fa0, fa0, fa1, fa2
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fmadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
   %1 = call half @llvm.fma.f16(half %a, half %b, half %c)
   ret half %1
 }
 
 define half @fmsub_s(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fmsub_s:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT:    fmsub.h fa0, fa0, fa1, ft0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fmsub_s:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT:    fmsub.h fa0, fa0, fa1, ft0
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fmsub_s:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fmv.h.x ft0, zero
+;CHECKIZFH-NEXT:    fadd.h ft0, fa2, ft0
+;CHECKIZFH-NEXT:    fmsub.h fa0, fa0, fa1, ft0
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fmsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ret
   %c_ = fadd half 0.0, %c ; avoid negation using xor
   %negc = fsub half -0.0, %c_
   %1 = call half @llvm.fma.f16(half %a, half %b, half %negc)
   ret half %1
 }
 
 define half @fnmadd_s(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fnmadd_s:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft1, fa0, ft0
-; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT:    fnmadd.h fa0, ft1, fa1, ft0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fnmadd_s:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft1, fa0, ft0
-; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT:    fnmadd.h fa0, ft1, fa1, ft0
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fnmadd_s:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fmv.h.x ft0, zero
+;CHECKIZFH-NEXT:    fadd.h ft1, fa0, ft0
+;CHECKIZFH-NEXT:    fadd.h ft0, fa2, ft0
+;CHECKIZFH-NEXT:    fnmadd.h fa0, ft1, fa1, ft0
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %c_ = fadd half 0.0, %c
   %nega = fsub half -0.0, %a_
   %negc = fsub half -0.0, %c_
   %1 = call half @llvm.fma.f16(half %nega, half %b, half %negc)
   ret half %1
 }
 
 define half @fnmadd_s_2(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fnmadd_s_2:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft1, fa1, ft0
-; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT:    fnmadd.h fa0, ft1, fa0, ft0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fnmadd_s_2:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft1, fa1, ft0
-; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT:    fnmadd.h fa0, ft1, fa0, ft0
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fnmadd_s_2:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fmv.h.x ft0, zero
+;CHECKIZFH-NEXT:    fadd.h ft1, fa1, ft0
+;CHECKIZFH-NEXT:    fadd.h ft0, fa2, ft0
+;CHECKIZFH-NEXT:    fnmadd.h fa0, ft1, fa0, ft0
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmadd_s_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %c_ = fadd half 0.0, %c
   %negb = fsub half -0.0, %b_
   %negc = fsub half -0.0, %c_
   %1 = call half @llvm.fma.f16(half %a, half %negb, half %negc)
   ret half %1
 }
 
 define half @fnmsub_s(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fnmsub_s:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft0, fa0, ft0
-; RV32IZFH-NEXT:    fnmsub.h fa0, ft0, fa1, fa2
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fnmsub_s:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft0, fa0, ft0
-; RV64IZFH-NEXT:    fnmsub.h fa0, ft0, fa1, fa2
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fnmsub_s:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fmv.h.x ft0, zero
+;CHECKIZFH-NEXT:    fadd.h ft0, fa0, ft0
+;CHECKIZFH-NEXT:    fnmsub.h fa0, ft0, fa1, fa2
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ret
   %a_ = fadd half 0.0, %a
   %nega = fsub half -0.0, %a_
   %1 = call half @llvm.fma.f16(half %nega, half %b, half %c)
   ret half %1
 }
 
 define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fnmsub_s_2:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft0, fa1, ft0
-; RV32IZFH-NEXT:    fnmsub.h fa0, ft0, fa0, fa2
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fnmsub_s_2:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft0, fa1, ft0
-; RV64IZFH-NEXT:    fnmsub.h fa0, ft0, fa0, fa2
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fnmsub_s_2:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fmv.h.x ft0, zero
+;CHECKIZFH-NEXT:    fadd.h ft0, fa1, ft0
+;CHECKIZFH-NEXT:    fnmsub.h fa0, ft0, fa0, fa2
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmsub_s_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ret
   %b_ = fadd half 0.0, %b
   %negb = fsub half -0.0, %b_
   %1 = call half @llvm.fma.f16(half %a, half %negb, half %c)
   ret half %1
 }
 
 define half @fmadd_s_contract(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fmadd_s_contract:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmadd.h fa0, fa0, fa1, fa2
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fmadd_s_contract:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmadd.h fa0, fa0, fa1, fa2
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fmadd_s_contract:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fmadd.h fa0, fa0, fa1, fa2
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fmadd_s_contract:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
   %1 = fmul contract half %a, %b
   %2 = fadd contract half %1, %c
   ret half %2
 }
 
 define half @fmsub_s_contract(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fmsub_s_contract:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT:    fmsub.h fa0, fa0, fa1, ft0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fmsub_s_contract:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT:    fmsub.h fa0, fa0, fa1, ft0
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fmsub_s_contract:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fmv.h.x ft0, zero
+;CHECKIZFH-NEXT:    fadd.h ft0, fa2, ft0
+;CHECKIZFH-NEXT:    fmsub.h fa0, fa0, fa1, ft0
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fmsub_s_contract:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ret
   %c_ = fadd half 0.0, %c ; avoid negation using xor
   %1 = fmul contract half %a, %b
   %2 = fsub contract half %1, %c_
   ret half %2
 }
 
 define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fnmadd_s_contract:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft1, fa0, ft0
-; RV32IZFH-NEXT:    fadd.h ft2, fa1, ft0
-; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0
-; RV32IZFH-NEXT:    fnmadd.h fa0, ft1, ft2, ft0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fnmadd_s_contract:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft1, fa0, ft0
-; RV64IZFH-NEXT:    fadd.h ft2, fa1, ft0
-; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0
-; RV64IZFH-NEXT:    fnmadd.h fa0, ft1, ft2, ft0
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fnmadd_s_contract:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fmv.h.x ft0, zero
+;CHECKIZFH-NEXT:    fadd.h ft1, fa0, ft0
+;CHECKIZFH-NEXT:    fadd.h ft2, fa1, ft0
+;CHECKIZFH-NEXT:    fadd.h ft0, fa2, ft0
+;CHECKIZFH-NEXT:    fnmadd.h fa0, ft1, ft2, ft0
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmadd_s_contract:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %c_ = fadd half 0.0, %c ; avoid negation using xor
   %1 = fmul contract half %a_, %b_
   %2 = fneg half %1
   %3 = fsub contract half %2, %c_
   ret half %3
 }
 
 define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fnmsub_s_contract:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft1, fa0, ft0
-; RV32IZFH-NEXT:    fadd.h ft0, fa1, ft0
-; RV32IZFH-NEXT:    fnmsub.h fa0, ft1, ft0, fa2
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fnmsub_s_contract:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft1, fa0, ft0
-; RV64IZFH-NEXT:    fadd.h ft0, fa1, ft0
-; RV64IZFH-NEXT:    fnmsub.h fa0, ft1, ft0, fa2
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fnmsub_s_contract:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fmv.h.x ft0, zero
+;CHECKIZFH-NEXT:    fadd.h ft1, fa0, ft0
+;CHECKIZFH-NEXT:    fadd.h ft0, fa1, ft0
+;CHECKIZFH-NEXT:    fnmsub.h fa0, ft1, ft0, fa2
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmsub_s_contract:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill

llvm/test/CodeGen/RISCV/half-convert-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f -disable-strictnode-mutation < %s \
-; RUN:   | FileCheck -check-prefix=RV32IZFH %s
+; RUN:   | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f -disable-strictnode-mutation < %s \
-; RUN:   | FileCheck -check-prefix=RV64IZFH %s
+; RUN:   | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32d -disable-strictnode-mutation < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IDZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64d -disable-strictnode-mutation < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IDZFH %s
 
 ; NOTE: The rounding mode metadata does not effect which instruction is

 ; RV64IDZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
   %1 = call i16 @llvm.experimental.constrained.fptoui.i16.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i16 %1
 }
 declare i16 @llvm.experimental.constrained.fptoui.i16.f16(half, metadata)
 
 define i32 @fcvt_w_h(half %a) nounwind strictfp {
-; RV32IZFH-LABEL: fcvt_w_h:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_w_h:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_w_h:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rtz
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_w_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_w_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 declare i32 @llvm.experimental.constrained.fptosi.i32.f16(half, metadata)
 
 define i32 @fcvt_wu_h(half %a) nounwind strictfp {
-; RV32IZFH-LABEL: fcvt_wu_h:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_wu_h:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_wu_h:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_wu_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_wu_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 declare i32 @llvm.experimental.constrained.fptoui.i32.f16(half, metadata)
 
 ; Test where the fptoui has multiple uses, one of which causes a sext to be
 ; inserted on RV64.
 ; FIXME: We should not have an fcvt.wu.h and an fcvt.lu.h.
 define i32 @fcvt_wu_h_multiple_use(half %x, i32* %y) {
-; RV32IZFH-LABEL: fcvt_wu_h_multiple_use:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
-; RV32IZFH-NEXT:    li a0, 1
-; RV32IZFH-NEXT:    beqz a1, .LBB4_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    mv a0, a1
-; RV32IZFH-NEXT:  .LBB4_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_wu_h_multiple_use:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
-; RV64IZFH-NEXT:    li a0, 1
-; RV64IZFH-NEXT:    beqz a1, .LBB4_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    mv a0, a1
-; RV64IZFH-NEXT:  .LBB4_2:
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_wu_h_multiple_use:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
+; CHECKIZFH-NEXT:    li a0, 1
+; CHECKIZFH-NEXT:    beqz a1, .LBB4_2
+; CHECKIZFH-NEXT:  # %bb.1:
+; CHECKIZFH-NEXT:    mv a0, a1
+; CHECKIZFH-NEXT:  .LBB4_2:
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_wu_h_multiple_use:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
 ; RV32IDZFH-NEXT:    li a0, 1
 ; RV32IDZFH-NEXT:    beqz a1, .LBB4_2
 ; RV32IDZFH-NEXT:  # %bb.1:
 ; RV32IDZFH-NEXT:    mv a0, a1

 ; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IDZFH-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.sitofp.f16.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.sitofp.f16.i16(i16, metadata, metadata)
 
 define half @fcvt_h_si_signext(i16 signext %a) nounwind strictfp {
-; RV32IZFH-LABEL: fcvt_h_si_signext:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.h.w fa0, a0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_h_si_signext:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.h.w fa0, a0
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_h_si_signext:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.h.w fa0, a0
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_si_signext:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_si_signext:
 ; RV64IDZFH:       # %bb.0:

 ; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IDZFH-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.uitofp.f16.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.uitofp.f16.i16(i16, metadata, metadata)
 
 define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind strictfp {
-; RV32IZFH-LABEL: fcvt_h_ui_zeroext:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.h.wu fa0, a0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_h_ui_zeroext:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.h.wu fa0, a0
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_h_ui_zeroext:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.h.wu fa0, a0
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_ui_zeroext:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_ui_zeroext:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IDZFH-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.uitofp.f16.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fcvt_h_w(i32 %a) nounwind strictfp {
-; RV32IZFH-LABEL: fcvt_h_w:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.h.w fa0, a0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_h_w:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.h.w fa0, a0
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_h_w:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.h.w fa0, a0
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_w:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_w:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IDZFH-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.sitofp.f16.i32(i32, metadata, metadata)
 
 define half @fcvt_h_w_load(i32* %p) nounwind strictfp {
-; RV32IZFH-LABEL: fcvt_h_w_load:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    lw a0, 0(a0)
-; RV32IZFH-NEXT:    fcvt.h.w fa0, a0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_h_w_load:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    lw a0, 0(a0)
-; RV64IZFH-NEXT:    fcvt.h.w fa0, a0
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_h_w_load:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    lw a0, 0(a0)
+; CHECKIZFH-NEXT:    fcvt.h.w fa0, a0
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_w_load:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    lw a0, 0(a0)
 ; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_w_load:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    lw a0, 0(a0)
 ; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IDZFH-NEXT:    ret
   %a = load i32, i32* %p
   %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fcvt_h_wu(i32 %a) nounwind strictfp {
-; RV32IZFH-LABEL: fcvt_h_wu:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.h.wu fa0, a0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_h_wu:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.h.wu fa0, a0
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_h_wu:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.h.wu fa0, a0
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_wu:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_wu:
 ; RV64IDZFH:       # %bb.0:

 ; RV64IDZFH-NEXT:    fcvt.h.lu fa0, a0
 ; RV64IDZFH-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.uitofp.f16.i64(i64 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.uitofp.f16.i64(i64, metadata, metadata)
 
 define half @fcvt_h_s(float %a) nounwind strictfp {
-; RV32IZFH-LABEL: fcvt_h_s:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.h.s fa0, fa0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_h_s:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_h_s:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.h.s fa0, fa0
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_s:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_s:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IDZFH-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.fptrunc.f16.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
   ret half %1
 }
 declare half @llvm.experimental.constrained.fptrunc.f16.f32(float, metadata, metadata)
 
 define float @fcvt_s_h(half %a) nounwind strictfp {
-; RV32IZFH-LABEL: fcvt_s_h:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_s_h:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_s_h:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.s.h fa0, fa0
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_s_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_s_h:
 ; RV64IDZFH:       # %bb.0:

llvm/test/CodeGen/RISCV/half-convert.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
-; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
+; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
-; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN:   -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32d < %s | FileCheck -check-prefix=RV32IDZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64d < %s | FileCheck -check-prefix=RV64IDZFH %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV64I %s

 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i16 @llvm.fptoui.sat.i16.f16(half %a)
   ret i16 %0
 }
 declare i16 @llvm.fptoui.sat.i16.f16(half)
 
 define i32 @fcvt_w_h(half %a) nounwind {
-; RV32IZFH-LABEL: fcvt_w_h:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_w_h:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_w_h:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rtz
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_w_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_w_h:
 ; RV64IDZFH:       # %bb.0:

 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fptosi half %a to i32
   ret i32 %1
 }
 
 define i32 @fcvt_w_h_sat(half %a) nounwind {
-; RV32IZFH-LABEL: fcvt_w_h_sat:
-; RV32IZFH:       # %bb.0: # %start
-; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    beqz a0, .LBB5_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
-; RV32IZFH-NEXT:  .LBB5_2: # %start
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_w_h_sat:
-; RV64IZFH:       # %bb.0: # %start
-; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    beqz a0, .LBB5_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
-; RV64IZFH-NEXT:  .LBB5_2: # %start
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_w_h_sat:
+; CHECKIZFH:       # %bb.0: # %start
+; CHECKIZFH-NEXT:    feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT:    beqz a0, .LBB5_2
+; CHECKIZFH-NEXT:  # %bb.1:
+; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rtz
+; CHECKIZFH-NEXT:  .LBB5_2: # %start
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_w_h_sat:
 ; RV32IDZFH:       # %bb.0: # %start
 ; RV32IDZFH-NEXT:    feq.h a0, fa0, fa0
 ; RV32IDZFH-NEXT:    beqz a0, .LBB5_2
 ; RV32IDZFH-NEXT:  # %bb.1:
 ; RV32IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:  .LBB5_2: # %start

 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %0
 }
 declare i32 @llvm.fptosi.sat.i32.f16(half)
 
 define i32 @fcvt_wu_h(half %a) nounwind {
-; RV32IZFH-LABEL: fcvt_wu_h:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_wu_h:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_wu_h:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_wu_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_wu_h:
 ; RV64IDZFH:       # %bb.0:

 ; RV64I-NEXT:    ret
   %1 = fptoui half %a to i32
   ret i32 %1
 }
 
 ; Test where the fptoui has multiple uses, one of which causes a sext to be
 ; inserted on RV64.
 define i32 @fcvt_wu_h_multiple_use(half %x, i32* %y) nounwind {
-; RV32IZFH-LABEL: fcvt_wu_h_multiple_use:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
-; RV32IZFH-NEXT:    li a0, 1
-; RV32IZFH-NEXT:    beqz a1, .LBB7_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    mv a0, a1
-; RV32IZFH-NEXT:  .LBB7_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_wu_h_multiple_use:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
-; RV64IZFH-NEXT:    li a0, 1
-; RV64IZFH-NEXT:    beqz a1, .LBB7_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    mv a0, a1
-; RV64IZFH-NEXT:  .LBB7_2:
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_wu_h_multiple_use:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
+; CHECKIZFH-NEXT:    li a0, 1
+; CHECKIZFH-NEXT:    beqz a1, .LBB7_2
+; CHECKIZFH-NEXT:  # %bb.1:
+; CHECKIZFH-NEXT:    mv a0, a1
+; CHECKIZFH-NEXT:  .LBB7_2:
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_wu_h_multiple_use:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
 ; RV32IDZFH-NEXT:    li a0, 1
 ; RV32IDZFH-NEXT:    beqz a1, .LBB7_2
 ; RV32IDZFH-NEXT:  # %bb.1:
 ; RV32IDZFH-NEXT:    mv a0, a1

 ; RV64I-NEXT:    ret
   %a = fptoui half %x to i32
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c
 }
 
 define i32 @fcvt_wu_h_sat(half %a) nounwind {
-; RV32IZFH-LABEL: fcvt_wu_h_sat:
-; RV32IZFH:       # %bb.0: # %start
-; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    beqz a0, .LBB8_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
-; RV32IZFH-NEXT:  .LBB8_2: # %start
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_wu_h_sat:
-; RV64IZFH:       # %bb.0: # %start
-; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    beqz a0, .LBB8_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
-; RV64IZFH-NEXT:  .LBB8_2: # %start
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_wu_h_sat:
+; CHECKIZFH:       # %bb.0: # %start
+; CHECKIZFH-NEXT:    feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT:    beqz a0, .LBB8_2
+; CHECKIZFH-NEXT:  # %bb.1:
+; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
+; CHECKIZFH-NEXT:  .LBB8_2: # %start
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_wu_h_sat:
 ; RV32IDZFH:       # %bb.0: # %start
 ; RV32IDZFH-NEXT:    feq.h a0, fa0, fa0
 ; RV32IDZFH-NEXT:    beqz a0, .LBB8_2
 ; RV32IDZFH-NEXT:  # %bb.1:
 ; RV32IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:  .LBB8_2: # %start

 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = sitofp i16 %a to half
   ret half %1
 }
 
 define half @fcvt_h_si_signext(i16 signext %a) nounwind {
-; RV32IZFH-LABEL: fcvt_h_si_signext:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.h.w fa0, a0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_h_si_signext:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.h.w fa0, a0
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_h_si_signext:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.h.w fa0, a0
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_si_signext:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_si_signext:
 ; RV64IDZFH:       # %bb.0:

 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = uitofp i16 %a to half
   ret half %1
 }
 
 define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind {
-; RV32IZFH-LABEL: fcvt_h_ui_zeroext:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.h.wu fa0, a0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_h_ui_zeroext:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.h.wu fa0, a0
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_h_ui_zeroext:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.h.wu fa0, a0
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_ui_zeroext:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_ui_zeroext:
 ; RV64IDZFH:       # %bb.0:

 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = uitofp i16 %a to half
   ret half %1
 }
 
 define half @fcvt_h_w(i32 %a) nounwind {
-; RV32IZFH-LABEL: fcvt_h_w:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.h.w fa0, a0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_h_w:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.h.w fa0, a0
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_h_w:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.h.w fa0, a0
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_w:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_w:
 ; RV64IDZFH:       # %bb.0:

 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = sitofp i32 %a to half
   ret half %1
 }
 
 define half @fcvt_h_w_load(i32* %p) nounwind {
-; RV32IZFH-LABEL: fcvt_h_w_load:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    lw a0, 0(a0)
-; RV32IZFH-NEXT:    fcvt.h.w fa0, a0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_h_w_load:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    lw a0, 0(a0)
-; RV64IZFH-NEXT:    fcvt.h.w fa0, a0
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_h_w_load:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    lw a0, 0(a0)
+; CHECKIZFH-NEXT:    fcvt.h.w fa0, a0
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_w_load:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    lw a0, 0(a0)
 ; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_w_load:

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %a = load i32, i32* %p
   %1 = sitofp i32 %a to half
   ret half %1
 }
 
 define half @fcvt_h_wu(i32 %a) nounwind {
-; RV32IZFH-LABEL: fcvt_h_wu:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.h.wu fa0, a0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_h_wu:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.h.wu fa0, a0
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_h_wu:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.h.wu fa0, a0
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_wu:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_wu:
 ; RV64IDZFH:       # %bb.0:

 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = uitofp i64 %a to half
   ret half %1
 }
 
 define half @fcvt_h_s(float %a) nounwind {
-; RV32IZFH-LABEL: fcvt_h_s:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.h.s fa0, fa0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_h_s:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_h_s:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.h.s fa0, fa0
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_s:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_s:
 ; RV64IDZFH:       # %bb.0:

 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fptrunc float %a to half
   ret half %1
 }
 
 define float @fcvt_s_h(half %a) nounwind {
-; RV32IZFH-LABEL: fcvt_s_h:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcvt_s_h:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fcvt_s_h:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.s.h fa0, fa0
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_s_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_s_h:
 ; RV64IDZFH:       # %bb.0:

 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fpext half %a to double
   ret double %1
 }
 
 define half @bitcast_h_i16(i16 %a) nounwind {
-; RV32IZFH-LABEL: bitcast_h_i16:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmv.h.x fa0, a0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: bitcast_h_i16:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmv.h.x fa0, a0
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: bitcast_h_i16:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fmv.h.x fa0, a0
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: bitcast_h_i16:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fmv.h.x fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: bitcast_h_i16:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fmv.h.x fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: bitcast_h_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: bitcast_h_i16:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    ret
   %1 = bitcast i16 %a to half
   ret half %1
 }
 
 define i16 @bitcast_i16_h(half %a) nounwind {
-; RV32IZFH-LABEL: bitcast_i16_h:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmv.x.h a0, fa0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: bitcast_i16_h:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmv.x.h a0, fa0
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: bitcast_i16_h:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fmv.x.h a0, fa0
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: bitcast_i16_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fmv.x.h a0, fa0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: bitcast_i16_h:
 ; RV64IDZFH:       # %bb.0:

llvm/test/CodeGen/RISCV/half-fcmp-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
-; RUN:   -target-abi ilp32f -disable-strictnode-mutation < %s \
-; RUN:   | FileCheck -check-prefix=RV32IZFH %s
+; RUN:   -target-abi ilp32f -disable-strictnode-mutation < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
-; RUN:   -target-abi lp64f -disable-strictnode-mutation < %s \
-; RUN:   | FileCheck -check-prefix=RV64IZFH %s
+; RUN:   -target-abi lp64f -disable-strictnode-mutation < %s | FileCheck %s
 
 define i32 @fcmp_oeq(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_oeq:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_oeq:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa0, fa1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmp_oeq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.h a0, fa0, fa1
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"oeq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 declare i1 @llvm.experimental.constrained.fcmp.f16(half, half, metadata, metadata)
 
 define i32 @fcmp_ogt(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_ogt:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    frflags a1
-; RV32IZFH-NEXT:    flt.h a0, fa1, fa0
-; RV32IZFH-NEXT:    fsflags a1
-; RV32IZFH-NEXT:    feq.h zero, fa1, fa0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_ogt:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    frflags a1
-; RV64IZFH-NEXT:    flt.h a0, fa1, fa0
-; RV64IZFH-NEXT:    fsflags a1
-; RV64IZFH-NEXT:    feq.h zero, fa1, fa0
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmp_ogt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a1
+; CHECK-NEXT:    flt.h a0, fa1, fa0
+; CHECK-NEXT:    fsflags a1
+; CHECK-NEXT:    feq.h zero, fa1, fa0
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oge(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_oge:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    frflags a1
-; RV32IZFH-NEXT:    fle.h a0, fa1, fa0
-; RV32IZFH-NEXT:    fsflags a1
-; RV32IZFH-NEXT:    feq.h zero, fa1, fa0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_oge:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    frflags a1
-; RV64IZFH-NEXT:    fle.h a0, fa1, fa0
-; RV64IZFH-NEXT:    fsflags a1
-; RV64IZFH-NEXT:    feq.h zero, fa1, fa0
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmp_oge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a1
+; CHECK-NEXT:    fle.h a0, fa1, fa0
+; CHECK-NEXT:    fsflags a1
+; CHECK-NEXT:    feq.h zero, fa1, fa0
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_olt(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_olt:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    frflags a1
-; RV32IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV32IZFH-NEXT:    fsflags a1
-; RV32IZFH-NEXT:    feq.h zero, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_olt:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    frflags a1
-; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV64IZFH-NEXT:    fsflags a1
-; RV64IZFH-NEXT:    feq.h zero, fa0, fa1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmp_olt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a1
+; CHECK-NEXT:    flt.h a0, fa0, fa1
+; CHECK-NEXT:    fsflags a1
+; CHECK-NEXT:    feq.h zero, fa0, fa1
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ole(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_ole:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    frflags a1
-; RV32IZFH-NEXT:    fle.h a0, fa0, fa1
-; RV32IZFH-NEXT:    fsflags a1
-; RV32IZFH-NEXT:    feq.h zero, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_ole:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    frflags a1
-; RV64IZFH-NEXT:    fle.h a0, fa0, fa1
-; RV64IZFH-NEXT:    fsflags a1
-; RV64IZFH-NEXT:    feq.h zero, fa0, fa1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmp_ole:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a1
+; CHECK-NEXT:    fle.h a0, fa0, fa1
+; CHECK-NEXT:    fsflags a1
+; CHECK-NEXT:    feq.h zero, fa0, fa1
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 ; FIXME: We only need one frflags before the two flts and one fsflags after the
 ; two flts.
 define i32 @fcmp_one(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_one:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    frflags a0
-; RV32IZFH-NEXT:    flt.h a1, fa0, fa1
-; RV32IZFH-NEXT:    fsflags a0
-; RV32IZFH-NEXT:    feq.h zero, fa0, fa1
-; RV32IZFH-NEXT:    frflags a0
-; RV32IZFH-NEXT:    flt.h a2, fa1, fa0
-; RV32IZFH-NEXT:    fsflags a0
-; RV32IZFH-NEXT:    or a0, a2, a1
-; RV32IZFH-NEXT:    feq.h zero, fa1, fa0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_one:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    frflags a0
-; RV64IZFH-NEXT:    flt.h a1, fa0, fa1
-; RV64IZFH-NEXT:    fsflags a0
-; RV64IZFH-NEXT:    feq.h zero, fa0, fa1
-; RV64IZFH-NEXT:    frflags a0
-; RV64IZFH-NEXT:    flt.h a2, fa1, fa0
-; RV64IZFH-NEXT:    fsflags a0
-; RV64IZFH-NEXT:    or a0, a2, a1
-; RV64IZFH-NEXT:    feq.h zero, fa1, fa0
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmp_one:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    flt.h a1, fa0, fa1
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    feq.h zero, fa0, fa1
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    flt.h a2, fa1, fa0
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    or a0, a2, a1
+; CHECK-NEXT:    feq.h zero, fa1, fa0
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"one", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ord(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_ord:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa1, fa1
-; RV32IZFH-NEXT:    feq.h a1, fa0, fa0
-; RV32IZFH-NEXT:    and a0, a1, a0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_ord:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa1, fa1
-; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
-; RV64IZFH-NEXT:    and a0, a1, a0
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmp_ord:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.h a0, fa1, fa1
+; CHECK-NEXT:    feq.h a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ord", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 ; FIXME: We only need one frflags before the two flts and one fsflags after the
 ; two flts.
 define i32 @fcmp_ueq(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_ueq:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    frflags a0
-; RV32IZFH-NEXT:    flt.h a1, fa0, fa1
-; RV32IZFH-NEXT:    fsflags a0
-; RV32IZFH-NEXT:    feq.h zero, fa0, fa1
-; RV32IZFH-NEXT:    frflags a0
-; RV32IZFH-NEXT:    flt.h a2, fa1, fa0
-; RV32IZFH-NEXT:    fsflags a0
-; RV32IZFH-NEXT:    or a0, a2, a1
-; RV32IZFH-NEXT:    xori a0, a0, 1
-; RV32IZFH-NEXT:    feq.h zero, fa1, fa0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_ueq:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    frflags a0
-; RV64IZFH-NEXT:    flt.h a1, fa0, fa1
-; RV64IZFH-NEXT:    fsflags a0
-; RV64IZFH-NEXT:    feq.h zero, fa0, fa1
-; RV64IZFH-NEXT:    frflags a0
-; RV64IZFH-NEXT:    flt.h a2, fa1, fa0
-; RV64IZFH-NEXT:    fsflags a0
-; RV64IZFH-NEXT:    or a0, a2, a1
-; RV64IZFH-NEXT:    xori a0, a0, 1
-; RV64IZFH-NEXT:    feq.h zero, fa1, fa0
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmp_ueq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    flt.h a1, fa0, fa1
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    feq.h zero, fa0, fa1
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    flt.h a2, fa1, fa0
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    or a0, a2, a1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    feq.h zero, fa1, fa0
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ugt(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_ugt:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    frflags a0
-; RV32IZFH-NEXT:    fle.h a1, fa0, fa1
-; RV32IZFH-NEXT:    fsflags a0
-; RV32IZFH-NEXT:    xori a0, a1, 1
-; RV32IZFH-NEXT:    feq.h zero, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_ugt:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    frflags a0
-; RV64IZFH-NEXT:    fle.h a1, fa0, fa1
-; RV64IZFH-NEXT:    fsflags a0
-; RV64IZFH-NEXT:    xori a0, a1, 1
-; RV64IZFH-NEXT:    feq.h zero, fa0, fa1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmp_ugt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    fle.h a1, fa0, fa1
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    xori a0, a1, 1
+; CHECK-NEXT:    feq.h zero, fa0, fa1
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uge(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_uge:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    frflags a0
-; RV32IZFH-NEXT:    flt.h a1, fa0, fa1
-; RV32IZFH-NEXT:    fsflags a0
-; RV32IZFH-NEXT:    xori a0, a1, 1
-; RV32IZFH-NEXT:    feq.h zero, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_uge:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    frflags a0
-; RV64IZFH-NEXT:    flt.h a1, fa0, fa1
-; RV64IZFH-NEXT:    fsflags a0
-; RV64IZFH-NEXT:    xori a0, a1, 1
-; RV64IZFH-NEXT:    feq.h zero, fa0, fa1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmp_uge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    flt.h a1, fa0, fa1
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    xori a0, a1, 1
+; CHECK-NEXT:    feq.h zero, fa0, fa1
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ult(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_ult:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    frflags a0
-; RV32IZFH-NEXT:    fle.h a1, fa1, fa0
-; RV32IZFH-NEXT:    fsflags a0
-; RV32IZFH-NEXT:    xori a0, a1, 1
-; RV32IZFH-NEXT:    feq.h zero, fa1, fa0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_ult:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    frflags a0
-; RV64IZFH-NEXT:    fle.h a1, fa1, fa0
-; RV64IZFH-NEXT:    fsflags a0
-; RV64IZFH-NEXT:    xori a0, a1, 1
-; RV64IZFH-NEXT:    feq.h zero, fa1, fa0
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmp_ult:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    fle.h a1, fa1, fa0
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    xori a0, a1, 1
+; CHECK-NEXT:    feq.h zero, fa1, fa0
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ult", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ule(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_ule:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    frflags a0
-; RV32IZFH-NEXT:    flt.h a1, fa1, fa0
-; RV32IZFH-NEXT:    fsflags a0
-; RV32IZFH-NEXT:    xori a0, a1, 1
-; RV32IZFH-NEXT:    feq.h zero, fa1, fa0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_ule:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    frflags a0
-; RV64IZFH-NEXT:    flt.h a1, fa1, fa0
-; RV64IZFH-NEXT:    fsflags a0
-; RV64IZFH-NEXT:    xori a0, a1, 1
-; RV64IZFH-NEXT:    feq.h zero, fa1, fa0
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmp_ule:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    flt.h a1, fa1, fa0
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    xori a0, a1, 1
+; CHECK-NEXT:    feq.h zero, fa1, fa0
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ule", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_une(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_une:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa0, fa1
-; RV32IZFH-NEXT:    xori a0, a0, 1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_une:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa0, fa1
-; RV64IZFH-NEXT:    xori a0, a0, 1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmp_une:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.h a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"une", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uno(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmp_uno:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa1, fa1
-; RV32IZFH-NEXT:    feq.h a1, fa0, fa0
-; RV32IZFH-NEXT:    and a0, a1, a0
-; RV32IZFH-NEXT:    xori a0, a0, 1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_uno:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa1, fa1
-; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
-; RV64IZFH-NEXT:    and a0, a1, a0
-; RV64IZFH-NEXT:    xori a0, a0, 1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmp_uno:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.h a0, fa1, fa1
+; CHECK-NEXT:    feq.h a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"uno", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_oeq(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_oeq:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fle.h a0, fa1, fa0
-; RV32IZFH-NEXT:    fle.h a1, fa0, fa1
-; RV32IZFH-NEXT:    and a0, a1, a0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmps_oeq:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fle.h a0, fa1, fa0
-; RV64IZFH-NEXT:    fle.h a1, fa0, fa1
-; RV64IZFH-NEXT:    and a0, a1, a0
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmps_oeq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.h a0, fa1, fa0
+; CHECK-NEXT:    fle.h a1, fa0, fa1
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"oeq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 declare i1 @llvm.experimental.constrained.fcmps.f16(half, half, metadata, metadata)
 
 define i32 @fcmps_ogt(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_ogt:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    flt.h a0, fa1, fa0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmps_ogt:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    flt.h a0, fa1, fa0
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmps_ogt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.h a0, fa1, fa0
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_oge(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_oge:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fle.h a0, fa1, fa0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmps_oge:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fle.h a0, fa1, fa0
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmps_oge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.h a0, fa1, fa0
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_olt(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_olt:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmps_olt:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmps_olt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.h a0, fa0, fa1
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ole(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_ole:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fle.h a0, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmps_ole:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fle.h a0, fa0, fa1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmps_ole:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.h a0, fa0, fa1
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_one(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_one:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV32IZFH-NEXT:    flt.h a1, fa1, fa0
-; RV32IZFH-NEXT:    or a0, a1, a0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmps_one:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV64IZFH-NEXT:    flt.h a1, fa1, fa0
-; RV64IZFH-NEXT:    or a0, a1, a0
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmps_one:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.h a0, fa0, fa1
+; CHECK-NEXT:    flt.h a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"one", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ord(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_ord:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fle.h a0, fa1, fa1
-; RV32IZFH-NEXT:    fle.h a1, fa0, fa0
-; RV32IZFH-NEXT:    and a0, a1, a0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmps_ord:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fle.h a0, fa1, fa1
-; RV64IZFH-NEXT:    fle.h a1, fa0, fa0
-; RV64IZFH-NEXT:    and a0, a1, a0
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmps_ord:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.h a0, fa1, fa1
+; CHECK-NEXT:    fle.h a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ord", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ueq(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_ueq:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV32IZFH-NEXT:    flt.h a1, fa1, fa0
-; RV32IZFH-NEXT:    or a0, a1, a0
-; RV32IZFH-NEXT:    xori a0, a0, 1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmps_ueq:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV64IZFH-NEXT:    flt.h a1, fa1, fa0
-; RV64IZFH-NEXT:    or a0, a1, a0
-; RV64IZFH-NEXT:    xori a0, a0, 1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmps_ueq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.h a0, fa0, fa1
+; CHECK-NEXT:    flt.h a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ugt(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_ugt:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fle.h a0, fa0, fa1
-; RV32IZFH-NEXT:    xori a0, a0, 1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmps_ugt:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fle.h a0, fa0, fa1
-; RV64IZFH-NEXT:    xori a0, a0, 1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmps_ugt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.h a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_uge(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_uge:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV32IZFH-NEXT:    xori a0, a0, 1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmps_uge:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV64IZFH-NEXT:    xori a0, a0, 1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmps_uge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.h a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ult(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_ult:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fle.h a0, fa1, fa0
-; RV32IZFH-NEXT:    xori a0, a0, 1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmps_ult:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fle.h a0, fa1, fa0
-; RV64IZFH-NEXT:    xori a0, a0, 1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmps_ult:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.h a0, fa1, fa0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ult", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ule(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_ule:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    flt.h a0, fa1, fa0
-; RV32IZFH-NEXT:    xori a0, a0, 1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmps_ule:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    flt.h a0, fa1, fa0
-; RV64IZFH-NEXT:    xori a0, a0, 1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmps_ule:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.h a0, fa1, fa0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ule", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_une(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_une:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fle.h a0, fa1, fa0
-; RV32IZFH-NEXT:    fle.h a1, fa0, fa1
-; RV32IZFH-NEXT:    and a0, a1, a0
-; RV32IZFH-NEXT:    xori a0, a0, 1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmps_une:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fle.h a0, fa1, fa0
-; RV64IZFH-NEXT:    fle.h a1, fa0, fa1
-; RV64IZFH-NEXT:    and a0, a1, a0
-; RV64IZFH-NEXT:    xori a0, a0, 1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmps_une:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.h a0, fa1, fa0
+; CHECK-NEXT:    fle.h a1, fa0, fa1
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"une", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_uno(half %a, half %b) nounwind strictfp {
-; RV32IZFH-LABEL: fcmps_uno:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fle.h a0, fa1, fa1
-; RV32IZFH-NEXT:    fle.h a1, fa0, fa0
-; RV32IZFH-NEXT:    and a0, a1, a0
-; RV32IZFH-NEXT:    xori a0, a0, 1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmps_uno:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fle.h a0, fa1, fa1
-; RV64IZFH-NEXT:    fle.h a1, fa0, fa0
-; RV64IZFH-NEXT:    and a0, a1, a0
-; RV64IZFH-NEXT:    xori a0, a0, 1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: fcmps_uno:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.h a0, fa1, fa1
+; CHECK-NEXT:    fle.h a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"uno", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/half-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
-; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
+; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=CHECKIZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
-; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=CHECKIZFH %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV64I %s
 
 define i32 @fcmp_false(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_false:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_false:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fcmp_false:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    li a0, 0
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_false:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a0, 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_false:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 0
 ; RV64I-NEXT:    ret
   %1 = fcmp false half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oeq(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_oeq:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_oeq:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa0, fa1
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fcmp_oeq:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    feq.h a0, fa0, fa1
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oeq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a1
 ; RV32I-NEXT:    fmv.h.x ft1, a0
 ; RV32I-NEXT:    feq.h a0, ft1, ft0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_oeq:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a1
 ; RV64I-NEXT:    fmv.h.x ft1, a0
 ; RV64I-NEXT:    feq.h a0, ft1, ft0
 ; RV64I-NEXT:    ret
   %1 = fcmp oeq half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ogt(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_ogt:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    flt.h a0, fa1, fa0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_ogt:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    flt.h a0, fa1, fa0
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fcmp_ogt:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    flt.h a0, fa1, fa0
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a0
 ; RV32I-NEXT:    fmv.h.x ft1, a1
 ; RV32I-NEXT:    flt.h a0, ft1, ft0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ogt:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a0
 ; RV64I-NEXT:    fmv.h.x ft1, a1
 ; RV64I-NEXT:    flt.h a0, ft1, ft0
 ; RV64I-NEXT:    ret
   %1 = fcmp ogt half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oge(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_oge:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fle.h a0, fa1, fa0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_oge:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fle.h a0, fa1, fa0
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fcmp_oge:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fle.h a0, fa1, fa0
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a0
 ; RV32I-NEXT:    fmv.h.x ft1, a1
 ; RV32I-NEXT:    fle.h a0, ft1, ft0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_oge:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a0
 ; RV64I-NEXT:    fmv.h.x ft1, a1
 ; RV64I-NEXT:    fle.h a0, ft1, ft0
 ; RV64I-NEXT:    ret
   %1 = fcmp oge half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_olt(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_olt:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_olt:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fcmp_olt:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    flt.h a0, fa0, fa1
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_olt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a1
 ; RV32I-NEXT:    fmv.h.x ft1, a0
 ; RV32I-NEXT:    flt.h a0, ft1, ft0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_olt:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a1
 ; RV64I-NEXT:    fmv.h.x ft1, a0
 ; RV64I-NEXT:    flt.h a0, ft1, ft0
 ; RV64I-NEXT:    ret
   %1 = fcmp olt half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ole(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_ole:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fle.h a0, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_ole:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fle.h a0, fa0, fa1
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fcmp_ole:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fle.h a0, fa0, fa1
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ole:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a1
 ; RV32I-NEXT:    fmv.h.x ft1, a0
 ; RV32I-NEXT:    fle.h a0, ft1, ft0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ole:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a1
 ; RV64I-NEXT:    fmv.h.x ft1, a0
 ; RV64I-NEXT:    fle.h a0, ft1, ft0
 ; RV64I-NEXT:    ret
   %1 = fcmp ole half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_one(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_one:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV32IZFH-NEXT:    flt.h a1, fa1, fa0
-; RV32IZFH-NEXT:    or a0, a1, a0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_one:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV64IZFH-NEXT:    flt.h a1, fa1, fa0
-; RV64IZFH-NEXT:    or a0, a1, a0
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fcmp_one:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    flt.h a0, fa0, fa1
+;CHECKIZFH-NEXT:    flt.h a1, fa1, fa0
+;CHECKIZFH-NEXT:    or a0, a1, a0
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a1
 ; RV32I-NEXT:    fmv.h.x ft1, a0
 ; RV32I-NEXT:    flt.h a0, ft1, ft0
 ; RV32I-NEXT:    flt.h a1, ft0, ft1
 ; RV32I-NEXT:    or a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_one:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a1
 ; RV64I-NEXT:    fmv.h.x ft1, a0
 ; RV64I-NEXT:    flt.h a0, ft1, ft0
 ; RV64I-NEXT:    flt.h a1, ft0, ft1
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
   %1 = fcmp one half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ord(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_ord:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa1, fa1
-; RV32IZFH-NEXT:    feq.h a1, fa0, fa0
-; RV32IZFH-NEXT:    and a0, a1, a0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_ord:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa1, fa1
-; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
-; RV64IZFH-NEXT:    and a0, a1, a0
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fcmp_ord:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    feq.h a0, fa1, fa1
+;CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
+;CHECKIZFH-NEXT:    and a0, a1, a0
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ord:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a0
 ; RV32I-NEXT:    fmv.h.x ft1, a1
 ; RV32I-NEXT:    feq.h a0, ft1, ft1
 ; RV32I-NEXT:    feq.h a1, ft0, ft0
 ; RV32I-NEXT:    and a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ord:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a0
 ; RV64I-NEXT:    fmv.h.x ft1, a1
 ; RV64I-NEXT:    feq.h a0, ft1, ft1
 ; RV64I-NEXT:    feq.h a1, ft0, ft0
 ; RV64I-NEXT:    and a0, a1, a0
 ; RV64I-NEXT:    ret
   %1 = fcmp ord half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ueq(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_ueq:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV32IZFH-NEXT:    flt.h a1, fa1, fa0
-; RV32IZFH-NEXT:    or a0, a1, a0
-; RV32IZFH-NEXT:    xori a0, a0, 1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_ueq:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV64IZFH-NEXT:    flt.h a1, fa1, fa0
-; RV64IZFH-NEXT:    or a0, a1, a0
-; RV64IZFH-NEXT:    xori a0, a0, 1
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fcmp_ueq:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    flt.h a0, fa0, fa1
+;CHECKIZFH-NEXT:    flt.h a1, fa1, fa0
+;CHECKIZFH-NEXT:    or a0, a1, a0
+;CHECKIZFH-NEXT:    xori a0, a0, 1
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ueq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a1
 ; RV32I-NEXT:    fmv.h.x ft1, a0
 ; RV32I-NEXT:    flt.h a0, ft1, ft0
 ; RV32I-NEXT:    flt.h a1, ft0, ft1
 ; RV32I-NEXT:    or a0, a1, a0

 ; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ret
   %1 = fcmp ueq half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ugt(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_ugt:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fle.h a0, fa0, fa1
-; RV32IZFH-NEXT:    xori a0, a0, 1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_ugt:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fle.h a0, fa0, fa1
-; RV64IZFH-NEXT:    xori a0, a0, 1
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fcmp_ugt:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fle.h a0, fa0, fa1
+;CHECKIZFH-NEXT:    xori a0, a0, 1
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a1
 ; RV32I-NEXT:    fmv.h.x ft1, a0
 ; RV32I-NEXT:    fle.h a0, ft1, ft0
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ugt:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a1
 ; RV64I-NEXT:    fmv.h.x ft1, a0
 ; RV64I-NEXT:    fle.h a0, ft1, ft0
 ; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ret
   %1 = fcmp ugt half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uge(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_uge:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV32IZFH-NEXT:    xori a0, a0, 1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_uge:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV64IZFH-NEXT:    xori a0, a0, 1
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fcmp_uge:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    flt.h a0, fa0, fa1
+;CHECKIZFH-NEXT:    xori a0, a0, 1
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a1
 ; RV32I-NEXT:    fmv.h.x ft1, a0
 ; RV32I-NEXT:    flt.h a0, ft1, ft0
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_uge:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a1
 ; RV64I-NEXT:    fmv.h.x ft1, a0
 ; RV64I-NEXT:    flt.h a0, ft1, ft0
 ; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ret
   %1 = fcmp uge half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ult(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_ult:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fle.h a0, fa1, fa0
-; RV32IZFH-NEXT:    xori a0, a0, 1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_ult:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fle.h a0, fa1, fa0
-; RV64IZFH-NEXT:    xori a0, a0, 1
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fcmp_ult:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    fle.h a0, fa1, fa0
+;CHECKIZFH-NEXT:    xori a0, a0, 1
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ult:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a0
 ; RV32I-NEXT:    fmv.h.x ft1, a1
 ; RV32I-NEXT:    fle.h a0, ft1, ft0
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ult:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a0
 ; RV64I-NEXT:    fmv.h.x ft1, a1
 ; RV64I-NEXT:    fle.h a0, ft1, ft0
 ; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ret
   %1 = fcmp ult half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ule(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_ule:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    flt.h a0, fa1, fa0
-; RV32IZFH-NEXT:    xori a0, a0, 1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_ule:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    flt.h a0, fa1, fa0
-; RV64IZFH-NEXT:    xori a0, a0, 1
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fcmp_ule:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    flt.h a0, fa1, fa0
+;CHECKIZFH-NEXT:    xori a0, a0, 1
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a0
 ; RV32I-NEXT:    fmv.h.x ft1, a1
 ; RV32I-NEXT:    flt.h a0, ft1, ft0
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ule:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a0
 ; RV64I-NEXT:    fmv.h.x ft1, a1
 ; RV64I-NEXT:    flt.h a0, ft1, ft0
 ; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ret
   %1 = fcmp ule half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_une(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_une:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa0, fa1
-; RV32IZFH-NEXT:    xori a0, a0, 1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_une:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa0, fa1
-; RV64IZFH-NEXT:    xori a0, a0, 1
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fcmp_une:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    feq.h a0, fa0, fa1
+;CHECKIZFH-NEXT:    xori a0, a0, 1
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_une:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a1
 ; RV32I-NEXT:    fmv.h.x ft1, a0
 ; RV32I-NEXT:    feq.h a0, ft1, ft0
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_une:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fmv.h.x ft0, a1
 ; RV64I-NEXT:    fmv.h.x ft1, a0
 ; RV64I-NEXT:    feq.h a0, ft1, ft0
 ; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ret
   %1 = fcmp une half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uno(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_uno:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa1, fa1
-; RV32IZFH-NEXT:    feq.h a1, fa0, fa0
-; RV32IZFH-NEXT:    and a0, a1, a0
-; RV32IZFH-NEXT:    xori a0, a0, 1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_uno:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa1, fa1
-; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
-; RV64IZFH-NEXT:    and a0, a1, a0
-; RV64IZFH-NEXT:    xori a0, a0, 1
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fcmp_uno:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    feq.h a0, fa1, fa1
+;CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
+;CHECKIZFH-NEXT:    and a0, a1, a0
+;CHECKIZFH-NEXT:    xori a0, a0, 1
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uno:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x ft0, a0
 ; RV32I-NEXT:    fmv.h.x ft1, a1
 ; RV32I-NEXT:    feq.h a0, ft1, ft1
 ; RV32I-NEXT:    feq.h a1, ft0, ft0
 ; RV32I-NEXT:    and a0, a1, a0

 ; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    ret
   %1 = fcmp uno half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_true(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: fcmp_true:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    li a0, 1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fcmp_true:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    li a0, 1
-; RV64IZFH-NEXT:    ret
+;CHECKIZFH-LABEL: fcmp_true:
+;CHECKIZFH:       # %bb.0:
+;CHECKIZFH-NEXT:    li a0, 1
+;CHECKIZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_true:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_true:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 1
 ; RV64I-NEXT:    ret
   %1 = fcmp true half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/half-imm.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
-; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
+; RUN:   -target-abi ilp32f < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
-; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN:   -target-abi lp64f < %s | FileCheck %s
 
 ; TODO: constant pool shouldn't be necessary for RV32IZfh and RV64IZfh
 define half @half_imm() nounwind {
-; RV32IZFH-LABEL: half_imm:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    lui a0, %hi(.LCPI0_0)
-; RV32IZFH-NEXT:    flh fa0, %lo(.LCPI0_0)(a0)
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: half_imm:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    lui a0, %hi(.LCPI0_0)
-; RV64IZFH-NEXT:    flh fa0, %lo(.LCPI0_0)(a0)
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: half_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI0_0)
+; CHECK-NEXT:    flh fa0, %lo(.LCPI0_0)(a0)
+; CHECK-NEXT:    ret
   ret half 3.0
 }
 
 define half @half_imm_op(half %a) nounwind {
-; RV32IZFH-LABEL: half_imm_op:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV32IZFH-NEXT:    flh ft0, %lo(.LCPI1_0)(a0)
-; RV32IZFH-NEXT:    fadd.h fa0, fa0, ft0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: half_imm_op:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV64IZFH-NEXT:    flh ft0, %lo(.LCPI1_0)(a0)
-; RV64IZFH-NEXT:    fadd.h fa0, fa0, ft0
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: half_imm_op:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI1_0)
+; CHECK-NEXT:    flh ft0, %lo(.LCPI1_0)(a0)
+; CHECK-NEXT:    fadd.h fa0, fa0, ft0
+; CHECK-NEXT:    ret
   %1 = fadd half %a, 1.0
   ret half %1
 }

llvm/test/CodeGen/RISCV/half-intrinsics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfh \
 ; RUN:   -verify-machineinstrs -target-abi ilp32f | \
-; RUN:   FileCheck -check-prefix=RV32IZFH %s
+; RUN:   FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfh \
 ; RUN:   -verify-machineinstrs -target-abi lp64f | \
-; RUN:   FileCheck -check-prefix=RV64IZFH %s
+; RUN:   FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
 ; RUN:   -mattr=+zfh -verify-machineinstrs -target-abi ilp32d | \
 ; RUN:   FileCheck -check-prefix=RV32IDZFH %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
 ; RUN:   -mattr=+zfh -verify-machineinstrs -target-abi lp64d | \
 ; RUN:   FileCheck -check-prefix=RV64IDZFH %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
 ; RUN:   -verify-machineinstrs | \
 ; RUN:   FileCheck -check-prefix=RV32I %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
 ; RUN:   -verify-machineinstrs | \
 ; RUN:   FileCheck -check-prefix=RV64I %s
 
 declare half @llvm.sqrt.f16(half)
 
 define half @sqrt_f16(half %a) nounwind {
-; RV32IZFH-LABEL: sqrt_f16:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fsqrt.h fa0, fa0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: sqrt_f16:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fsqrt.h fa0, fa0
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: sqrt_f16:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fsqrt.h fa0, fa0
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: sqrt_f16:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fsqrt.h fa0, fa0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: sqrt_f16:
 ; RV64IDZFH:       # %bb.0:

 ; RV64I-NEXT:    ret
   %1 = call half @llvm.log2.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.fma.f16(half, half, half)
 
 define half @fma_f16(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fma_f16:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmadd.h fa0, fa0, fa1, fa2
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fma_f16:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmadd.h fa0, fa0, fa1, fa2
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fma_f16:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fmadd.h fa0, fa0, fa1, fa2
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fma_f16:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fmadd.h fa0, fa0, fa1, fa2
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fma_f16:
 ; RV64IDZFH:       # %bb.0:

 ; RV64I-NEXT:    ret
   %1 = call half @llvm.fma.f16(half %a, half %b, half %c)
   ret half %1
 }
 
 declare half @llvm.fmuladd.f16(half, half, half)
 
 define half @fmuladd_f16(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fmuladd_f16:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmadd.h fa0, fa0, fa1, fa2
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fmuladd_f16:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmadd.h fa0, fa0, fa1, fa2
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fmuladd_f16:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fmadd.h fa0, fa0, fa1, fa2
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fmuladd_f16:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fmadd.h fa0, fa0, fa1, fa2
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fmuladd_f16:
 ; RV64IDZFH:       # %bb.0:

 ; RV64I-NEXT:    ret
   %1 = call half @llvm.fmuladd.f16(half %a, half %b, half %c)
   ret half %1
 }
 
 declare half @llvm.fabs.f16(half)
 
 define half @fabs_f16(half %a) nounwind {
-; RV32IZFH-LABEL: fabs_f16:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fabs.h fa0, fa0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fabs_f16:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fabs.h fa0, fa0
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fabs_f16:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fabs.h fa0, fa0
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fabs_f16:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fabs.h fa0, fa0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fabs_f16:
 ; RV64IDZFH:       # %bb.0:

 ; RV64I-NEXT:    ret
   %1 = call half @llvm.fabs.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.minnum.f16(half, half)
 
 define half @minnum_f16(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: minnum_f16:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmin.h fa0, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: minnum_f16:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmin.h fa0, fa0, fa1
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: minnum_f16:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fmin.h fa0, fa0, fa1
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: minnum_f16:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fmin.h fa0, fa0, fa1
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: minnum_f16:
 ; RV64IDZFH:       # %bb.0:

 ; RV64I-NEXT:    ret
   %1 = call half @llvm.minnum.f16(half %a, half %b)
   ret half %1
 }
 
 declare half @llvm.maxnum.f16(half, half)
 
 define half @maxnum_f16(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: maxnum_f16:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmax.h fa0, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: maxnum_f16:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmax.h fa0, fa0, fa1
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: maxnum_f16:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fmax.h fa0, fa0, fa1
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: maxnum_f16:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fmax.h fa0, fa0, fa1
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: maxnum_f16:
 ; RV64IDZFH:       # %bb.0:

 ; define half @fmaximum_f16(half %a, half %b) nounwind {
 ;   %1 = call half @llvm.maximum.f16(half %a, half %b)
 ;   ret half %1
 ; }
 
 declare half @llvm.copysign.f16(half, half)
 
 define half @copysign_f16(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: copysign_f16:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fsgnj.h fa0, fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: copysign_f16:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fsgnj.h fa0, fa0, fa1
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: copysign_f16:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fsgnj.h fa0, fa0, fa1
+; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: copysign_f16:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fsgnj.h fa0, fa0, fa1
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: copysign_f16:
 ; RV64IDZFH:       # %bb.0:

llvm/test/CodeGen/RISCV/half-isnan.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
-; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
+; RUN:   -target-abi ilp32f < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
-; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN:   -target-abi lp64f < %s | FileCheck %s
 
 define zeroext i1 @half_is_nan(half %a) nounwind {
-; RV32IZFH-LABEL: half_is_nan:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    xori a0, a0, 1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: half_is_nan:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    xori a0, a0, 1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: half_is_nan:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.h a0, fa0, fa0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
   %1 = fcmp uno half %a, 0.000000e+00
   ret i1 %1
 }
 
 define zeroext i1 @half_not_nan(half %a) nounwind {
-; RV32IZFH-LABEL: half_not_nan:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: half_not_nan:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: half_not_nan:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.h a0, fa0, fa0
+; CHECK-NEXT:    ret
   %1 = fcmp ord half %a, 0.000000e+00
   ret i1 %1
 }

llvm/test/CodeGen/RISCV/half-mem.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
-; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
+; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
-; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN:   -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
 
 define half @flh(half *%a) nounwind {
-; RV32IZFH-LABEL: flh:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    flh ft0, 0(a0)
-; RV32IZFH-NEXT:    flh ft1, 6(a0)
-; RV32IZFH-NEXT:    fadd.h fa0, ft0, ft1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: flh:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    flh ft0, 0(a0)
-; RV64IZFH-NEXT:    flh ft1, 6(a0)
-; RV64IZFH-NEXT:    fadd.h fa0, ft0, ft1
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: flh:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    flh ft0, 0(a0)
+; CHECKIZFH-NEXT:    flh ft1, 6(a0)
+; CHECKIZFH-NEXT:    fadd.h fa0, ft0, ft1
+; CHECKIZFH-NEXT:    ret
   %1 = load half, half* %a
   %2 = getelementptr half, half* %a, i32 3
   %3 = load half, half* %2
 ; Use both loaded values in an FP op to ensure an flh is used, even for the
 ; soft half ABI
   %4 = fadd half %1, %3
   ret half %4
 }
 
 define dso_local void @fsh(half *%a, half %b, half %c) nounwind {
 ; Use %b and %c in an FP op to ensure half precision floating point registers
 ; are used, even for the soft half ABI
-; RV32IZFH-LABEL: fsh:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fadd.h ft0, fa0, fa1
-; RV32IZFH-NEXT:    fsh ft0, 0(a0)
-; RV32IZFH-NEXT:    fsh ft0, 16(a0)
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: fsh:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fadd.h ft0, fa0, fa1
-; RV64IZFH-NEXT:    fsh ft0, 0(a0)
-; RV64IZFH-NEXT:    fsh ft0, 16(a0)
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: fsh:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fadd.h ft0, fa0, fa1
+; CHECKIZFH-NEXT:    fsh ft0, 0(a0)
+; CHECKIZFH-NEXT:    fsh ft0, 16(a0)
+; CHECKIZFH-NEXT:    ret
   %1 = fadd half %b, %c
   store half %1, half* %a
   %2 = getelementptr half, half* %a, i32 8
   store half %1, half* %2
   ret void
 }
 
 ; Check load and store to a global
 @G = dso_local global half 0.0
 
 define half @flh_fsh_global(half %a, half %b) nounwind {
 ; Use %a and %b in an FP op to ensure half precision floating point registers
 ; are used, even for the soft half ABI
-; RV32IZFH-LABEL: flh_fsh_global:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fadd.h fa0, fa0, fa1
-; RV32IZFH-NEXT:    lui a0, %hi(G)
-; RV32IZFH-NEXT:    flh ft0, %lo(G)(a0)
-; RV32IZFH-NEXT:    addi a1, a0, %lo(G)
-; RV32IZFH-NEXT:    fsh fa0, %lo(G)(a0)
-; RV32IZFH-NEXT:    flh ft0, 18(a1)
-; RV32IZFH-NEXT:    fsh fa0, 18(a1)
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: flh_fsh_global:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fadd.h fa0, fa0, fa1
-; RV64IZFH-NEXT:    lui a0, %hi(G)
-; RV64IZFH-NEXT:    flh ft0, %lo(G)(a0)
-; RV64IZFH-NEXT:    addi a1, a0, %lo(G)
-; RV64IZFH-NEXT:    fsh fa0, %lo(G)(a0)
-; RV64IZFH-NEXT:    flh ft0, 18(a1)
-; RV64IZFH-NEXT:    fsh fa0, 18(a1)
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: flh_fsh_global:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fadd.h fa0, fa0, fa1
+; CHECKIZFH-NEXT:    lui a0, %hi(G)
+; CHECKIZFH-NEXT:    flh ft0, %lo(G)(a0)
+; CHECKIZFH-NEXT:    addi a1, a0, %lo(G)
+; CHECKIZFH-NEXT:    fsh fa0, %lo(G)(a0)
+; CHECKIZFH-NEXT:    flh ft0, 18(a1)
+; CHECKIZFH-NEXT:    fsh fa0, 18(a1)
+; CHECKIZFH-NEXT:    ret
   %1 = fadd half %a, %b
   %2 = load volatile half, half* @G
   store half %1, half* @G
   %3 = getelementptr half, half* @G, i32 9
   %4 = load volatile half, half* %3
   store half %1, half* %3
   ret half %1
 }

llvm/test/CodeGen/RISCV/half-round-conv-sat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IZFH %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IZFH %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
 
 define signext i32 @test_floor_si32(half %x) {
-; RV32IZFH-LABEL: test_floor_si32:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    beqz a0, .LBB0_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rdn
-; RV32IZFH-NEXT:  .LBB0_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: test_floor_si32:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    beqz a0, .LBB0_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rdn
-; RV64IZFH-NEXT:  .LBB0_2:
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: test_floor_si32:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT:    beqz a0, .LBB0_2
+; CHECKIZFH-NEXT:  # %bb.1:
+; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rdn
+; CHECKIZFH-NEXT:  .LBB0_2:
+; CHECKIZFH-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_floor_si64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_floor_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-NEXT:  .LBB1_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_floor_ui32(half %x) {
-; RV32IZFH-LABEL: test_floor_ui32:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    beqz a0, .LBB2_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rdn
-; RV32IZFH-NEXT:  .LBB2_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: test_floor_ui32:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    beqz a0, .LBB2_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rdn
-; RV64IZFH-NEXT:  .LBB2_2:
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: test_floor_ui32:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT:    beqz a0, .LBB2_2
+; CHECKIZFH-NEXT:  # %bb.1:
+; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rdn
+; CHECKIZFH-NEXT:  .LBB2_2:
+; CHECKIZFH-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_floor_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_floor_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-NEXT:  .LBB3_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_ceil_si32(half %x) {
-; RV32IZFH-LABEL: test_ceil_si32:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    beqz a0, .LBB4_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rup
-; RV32IZFH-NEXT:  .LBB4_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: test_ceil_si32:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    beqz a0, .LBB4_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rup
-; RV64IZFH-NEXT:  .LBB4_2:
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: test_ceil_si32:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT:    beqz a0, .LBB4_2
+; CHECKIZFH-NEXT:  # %bb.1:
+; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rup
+; CHECKIZFH-NEXT:  .LBB4_2:
+; CHECKIZFH-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_ceil_si64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_ceil_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-NEXT:  .LBB5_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_ceil_ui32(half %x) {
-; RV32IZFH-LABEL: test_ceil_ui32:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    beqz a0, .LBB6_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rup
-; RV32IZFH-NEXT:  .LBB6_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: test_ceil_ui32:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    beqz a0, .LBB6_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rup
-; RV64IZFH-NEXT:  .LBB6_2:
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: test_ceil_ui32:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT:    beqz a0, .LBB6_2
+; CHECKIZFH-NEXT:  # %bb.1:
+; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rup
+; CHECKIZFH-NEXT:  .LBB6_2:
+; CHECKIZFH-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_ceil_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_ceil_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-NEXT:  .LBB7_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_trunc_si32(half %x) {
-; RV32IZFH-LABEL: test_trunc_si32:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    beqz a0, .LBB8_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
-; RV32IZFH-NEXT:  .LBB8_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: test_trunc_si32:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    beqz a0, .LBB8_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
-; RV64IZFH-NEXT:  .LBB8_2:
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: test_trunc_si32:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT:    beqz a0, .LBB8_2
+; CHECKIZFH-NEXT:  # %bb.1:
+; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rtz
+; CHECKIZFH-NEXT:  .LBB8_2:
+; CHECKIZFH-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_trunc_si64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_trunc_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-NEXT:  .LBB9_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_trunc_ui32(half %x) {
-; RV32IZFH-LABEL: test_trunc_ui32:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    beqz a0, .LBB10_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
-; RV32IZFH-NEXT:  .LBB10_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: test_trunc_ui32:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    beqz a0, .LBB10_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
-; RV64IZFH-NEXT:  .LBB10_2:
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: test_trunc_ui32:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT:    beqz a0, .LBB10_2
+; CHECKIZFH-NEXT:  # %bb.1:
+; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
+; CHECKIZFH-NEXT:  .LBB10_2:
+; CHECKIZFH-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_trunc_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_trunc_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-NEXT:  .LBB11_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_round_si32(half %x) {
-; RV32IZFH-LABEL: test_round_si32:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    beqz a0, .LBB12_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rmm
-; RV32IZFH-NEXT:  .LBB12_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: test_round_si32:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    beqz a0, .LBB12_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rmm
-; RV64IZFH-NEXT:  .LBB12_2:
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: test_round_si32:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT:    beqz a0, .LBB12_2
+; CHECKIZFH-NEXT:  # %bb.1:
+; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rmm
+; CHECKIZFH-NEXT:  .LBB12_2:
+; CHECKIZFH-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_round_si64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_round_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-NEXT:  .LBB13_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_round_ui32(half %x) {
-; RV32IZFH-LABEL: test_round_ui32:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    beqz a0, .LBB14_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rmm
-; RV32IZFH-NEXT:  .LBB14_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: test_round_ui32:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    beqz a0, .LBB14_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rmm
-; RV64IZFH-NEXT:  .LBB14_2:
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: test_round_ui32:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT:    beqz a0, .LBB14_2
+; CHECKIZFH-NEXT:  # %bb.1:
+; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rmm
+; CHECKIZFH-NEXT:  .LBB14_2:
+; CHECKIZFH-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_round_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_round_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-NEXT:  .LBB15_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_roundeven_si32(half %x) {
-; RV32IZFH-LABEL: test_roundeven_si32:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    beqz a0, .LBB16_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rne
-; RV32IZFH-NEXT:  .LBB16_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: test_roundeven_si32:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    beqz a0, .LBB16_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rne
-; RV64IZFH-NEXT:  .LBB16_2:
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: test_roundeven_si32:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT:    beqz a0, .LBB16_2
+; CHECKIZFH-NEXT:  # %bb.1:
+; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rne
+; CHECKIZFH-NEXT:  .LBB16_2:
+; CHECKIZFH-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_roundeven_si64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_roundeven_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-NEXT:  .LBB17_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_roundeven_ui32(half %x) {
-; RV32IZFH-LABEL: test_roundeven_ui32:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    beqz a0, .LBB18_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rne
-; RV32IZFH-NEXT:  .LBB18_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: test_roundeven_ui32:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    beqz a0, .LBB18_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rne
-; RV64IZFH-NEXT:  .LBB18_2:
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: test_roundeven_ui32:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    feq.h a0, fa0, fa0
+; CHECKIZFH-NEXT:    beqz a0, .LBB18_2
+; CHECKIZFH-NEXT:  # %bb.1:
+; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rne
+; CHECKIZFH-NEXT:  .LBB18_2:
+; CHECKIZFH-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_roundeven_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_roundeven_ui64:
 ; RV32IZFH:       # %bb.0:

llvm/test/CodeGen/RISCV/half-round-conv.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IZFH %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IZFH %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
 
 define signext i8 @test_floor_si8(half %x) {
 ; RV32IZFH-LABEL: test_floor_si8:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rdn
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_floor_si8:

 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rdn
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = fptosi half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_floor_si32(half %x) {
-; RV32IZFH-LABEL: test_floor_si32:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rdn
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: test_floor_si32:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rdn
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: test_floor_si32:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rdn
+; CHECKIZFH-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = fptosi half %a to i32
   ret i32 %b
 }
 
 define i64 @test_floor_si64(half %x) {
 ; RV32IZFH-LABEL: test_floor_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rdn
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = fptoui half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_floor_ui32(half %x) {
-; RV32IZFH-LABEL: test_floor_ui32:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rdn
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: test_floor_ui32:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rdn
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: test_floor_ui32:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rdn
+; CHECKIZFH-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = fptoui half %a to i32
   ret i32 %b
 }
 
 define i64 @test_floor_ui64(half %x) {
 ; RV32IZFH-LABEL: test_floor_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rup
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = fptosi half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_ceil_si32(half %x) {
-; RV32IZFH-LABEL: test_ceil_si32:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rup
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: test_ceil_si32:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rup
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: test_ceil_si32:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rup
+; CHECKIZFH-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = fptosi half %a to i32
   ret i32 %b
 }
 
 define i64 @test_ceil_si64(half %x) {
 ; RV32IZFH-LABEL: test_ceil_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rup
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = fptoui half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_ceil_ui32(half %x) {
-; RV32IZFH-LABEL: test_ceil_ui32:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rup
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: test_ceil_ui32:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rup
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: test_ceil_ui32:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rup
+; CHECKIZFH-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = fptoui half %a to i32
   ret i32 %b
 }
 
 define i64 @test_ceil_ui64(half %x) {
 ; RV32IZFH-LABEL: test_ceil_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = fptosi half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_trunc_si32(half %x) {
-; RV32IZFH-LABEL: test_trunc_si32:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: test_trunc_si32:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: test_trunc_si32:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rtz
+; CHECKIZFH-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = fptosi half %a to i32
   ret i32 %b
 }
 
 define i64 @test_trunc_si64(half %x) {
 ; RV32IZFH-LABEL: test_trunc_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = fptoui half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_trunc_ui32(half %x) {
-; RV32IZFH-LABEL: test_trunc_ui32:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: test_trunc_ui32:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: test_trunc_ui32:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
+; CHECKIZFH-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = fptoui half %a to i32
   ret i32 %b
 }
 
 define i64 @test_trunc_ui64(half %x) {
 ; RV32IZFH-LABEL: test_trunc_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = fptosi half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_round_si32(half %x) {
-; RV32IZFH-LABEL: test_round_si32:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rmm
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: test_round_si32:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rmm
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: test_round_si32:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rmm
+; CHECKIZFH-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = fptosi half %a to i32
   ret i32 %b
 }
 
 define i64 @test_round_si64(half %x) {
 ; RV32IZFH-LABEL: test_round_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = fptoui half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_round_ui32(half %x) {
-; RV32IZFH-LABEL: test_round_ui32:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rmm
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: test_round_ui32:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rmm
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: test_round_ui32:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rmm
+; CHECKIZFH-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = fptoui half %a to i32
   ret i32 %b
 }
 
 define i64 @test_round_ui64(half %x) {
 ; RV32IZFH-LABEL: test_round_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rne
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = fptosi half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_roundeven_si32(half %x) {
-; RV32IZFH-LABEL: test_roundeven_si32:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rne
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: test_roundeven_si32:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rne
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: test_roundeven_si32:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rne
+; CHECKIZFH-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = fptosi half %a to i32
   ret i32 %b
 }
 
 define i64 @test_roundeven_si64(half %x) {
 ; RV32IZFH-LABEL: test_roundeven_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rne
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = fptoui half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_roundeven_ui32(half %x) {
-; RV32IZFH-LABEL: test_roundeven_ui32:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rne
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: test_roundeven_ui32:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rne
-; RV64IZFH-NEXT:    ret
+; CHECKIZFH-LABEL: test_roundeven_ui32:
+; CHECKIZFH:       # %bb.0:
+; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rne
+; CHECKIZFH-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = fptoui half %a to i32
   ret i32 %b
 }
 
 define i64 @test_roundeven_ui64(half %x) {
 ; RV32IZFH-LABEL: test_roundeven_ui64:
 ; RV32IZFH:       # %bb.0:

llvm/test/CodeGen/RISCV/half-select-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
-; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
+; RUN:   -target-abi ilp32f < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
-; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN:   -target-abi lp64f < %s | FileCheck %s
 
 define half @select_fcmp_false(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_false:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmv.h fa0, fa1
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: select_fcmp_false:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmv.h fa0, fa1
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: select_fcmp_false:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.h fa0, fa1
+; CHECK-NEXT:    ret
   %1 = fcmp false half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_oeq(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_oeq:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa0, fa1
-; RV32IZFH-NEXT:    bnez a0, .LBB1_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fmv.h fa0, fa1
-; RV32IZFH-NEXT:  .LBB1_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: select_fcmp_oeq:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa0, fa1
-; RV64IZFH-NEXT:    bnez a0, .LBB1_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fmv.h fa0, fa1
-; RV64IZFH-NEXT:  .LBB1_2:
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: select_fcmp_oeq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.h a0, fa0, fa1
+; CHECK-NEXT:    bnez a0, .LBB1_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.h fa0, fa1
+; CHECK-NEXT:  .LBB1_2:
+; CHECK-NEXT:    ret
   %1 = fcmp oeq half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ogt(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_ogt:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    flt.h a0, fa1, fa0
-; RV32IZFH-NEXT:    bnez a0, .LBB2_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fmv.h fa0, fa1
-; RV32IZFH-NEXT:  .LBB2_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: select_fcmp_ogt:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    flt.h a0, fa1, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB2_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fmv.h fa0, fa1
-; RV64IZFH-NEXT:  .LBB2_2:
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: select_fcmp_ogt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.h a0, fa1, fa0
+; CHECK-NEXT:    bnez a0, .LBB2_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.h fa0, fa1
+; CHECK-NEXT:  .LBB2_2:
+; CHECK-NEXT:    ret
   %1 = fcmp ogt half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_oge(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_oge:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fle.h a0, fa1, fa0
-; RV32IZFH-NEXT:    bnez a0, .LBB3_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fmv.h fa0, fa1
-; RV32IZFH-NEXT:  .LBB3_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: select_fcmp_oge:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fle.h a0, fa1, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB3_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fmv.h fa0, fa1
-; RV64IZFH-NEXT:  .LBB3_2:
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: select_fcmp_oge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.h a0, fa1, fa0
+; CHECK-NEXT:    bnez a0, .LBB3_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.h fa0, fa1
+; CHECK-NEXT:  .LBB3_2:
+; CHECK-NEXT:    ret
   %1 = fcmp oge half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_olt(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_olt:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV32IZFH-NEXT:    bnez a0, .LBB4_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fmv.h fa0, fa1
-; RV32IZFH-NEXT:  .LBB4_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: select_fcmp_olt:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV64IZFH-NEXT:    bnez a0, .LBB4_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fmv.h fa0, fa1
-; RV64IZFH-NEXT:  .LBB4_2:
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: select_fcmp_olt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.h a0, fa0, fa1
+; CHECK-NEXT:    bnez a0, .LBB4_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.h fa0, fa1
+; CHECK-NEXT:  .LBB4_2:
+; CHECK-NEXT:    ret
   %1 = fcmp olt half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ole(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_ole:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fle.h a0, fa0, fa1
-; RV32IZFH-NEXT:    bnez a0, .LBB5_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fmv.h fa0, fa1
-; RV32IZFH-NEXT:  .LBB5_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: select_fcmp_ole:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fle.h a0, fa0, fa1
-; RV64IZFH-NEXT:    bnez a0, .LBB5_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fmv.h fa0, fa1
-; RV64IZFH-NEXT:  .LBB5_2:
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: select_fcmp_ole:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.h a0, fa0, fa1
+; CHECK-NEXT:    bnez a0, .LBB5_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.h fa0, fa1
+; CHECK-NEXT:  .LBB5_2:
+; CHECK-NEXT:    ret
   %1 = fcmp ole half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_one(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_one:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV32IZFH-NEXT:    flt.h a1, fa1, fa0
-; RV32IZFH-NEXT:    or a0, a1, a0
-; RV32IZFH-NEXT:    bnez a0, .LBB6_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fmv.h fa0, fa1
-; RV32IZFH-NEXT:  .LBB6_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: select_fcmp_one:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV64IZFH-NEXT:    flt.h a1, fa1, fa0
-; RV64IZFH-NEXT:    or a0, a1, a0
-; RV64IZFH-NEXT:    bnez a0, .LBB6_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fmv.h fa0, fa1
-; RV64IZFH-NEXT:  .LBB6_2:
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: select_fcmp_one:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.h a0, fa0, fa1
+; CHECK-NEXT:    flt.h a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    bnez a0, .LBB6_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.h fa0, fa1
+; CHECK-NEXT:  .LBB6_2:
+; CHECK-NEXT:    ret
   %1 = fcmp one half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ord(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_ord:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa1, fa1
-; RV32IZFH-NEXT:    feq.h a1, fa0, fa0
-; RV32IZFH-NEXT:    and a0, a1, a0
-; RV32IZFH-NEXT:    bnez a0, .LBB7_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fmv.h fa0, fa1
-; RV32IZFH-NEXT:  .LBB7_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: select_fcmp_ord:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa1, fa1
-; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
-; RV64IZFH-NEXT:    and a0, a1, a0
-; RV64IZFH-NEXT:    bnez a0, .LBB7_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fmv.h fa0, fa1
-; RV64IZFH-NEXT:  .LBB7_2:
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: select_fcmp_ord:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.h a0, fa1, fa1
+; CHECK-NEXT:    feq.h a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    bnez a0, .LBB7_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.h fa0, fa1
+; CHECK-NEXT:  .LBB7_2:
+; CHECK-NEXT:    ret
   %1 = fcmp ord half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ueq(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_ueq:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV32IZFH-NEXT:    flt.h a1, fa1, fa0
-; RV32IZFH-NEXT:    or a0, a1, a0
-; RV32IZFH-NEXT:    beqz a0, .LBB8_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fmv.h fa0, fa1
-; RV32IZFH-NEXT:  .LBB8_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: select_fcmp_ueq:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV64IZFH-NEXT:    flt.h a1, fa1, fa0
-; RV64IZFH-NEXT:    or a0, a1, a0
-; RV64IZFH-NEXT:    beqz a0, .LBB8_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fmv.h fa0, fa1
-; RV64IZFH-NEXT:  .LBB8_2:
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: select_fcmp_ueq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.h a0, fa0, fa1
+; CHECK-NEXT:    flt.h a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    beqz a0, .LBB8_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.h fa0, fa1
+; CHECK-NEXT:  .LBB8_2:
+; CHECK-NEXT:    ret
   %1 = fcmp ueq half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ugt(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_ugt:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fle.h a0, fa0, fa1
-; RV32IZFH-NEXT:    beqz a0, .LBB9_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fmv.h fa0, fa1
-; RV32IZFH-NEXT:  .LBB9_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: select_fcmp_ugt:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fle.h a0, fa0, fa1
-; RV64IZFH-NEXT:    beqz a0, .LBB9_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fmv.h fa0, fa1
-; RV64IZFH-NEXT:  .LBB9_2:
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: select_fcmp_ugt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.h a0, fa0, fa1
+; CHECK-NEXT:    beqz a0, .LBB9_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.h fa0, fa1
+; CHECK-NEXT:  .LBB9_2:
+; CHECK-NEXT:    ret
   %1 = fcmp ugt half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_uge(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_uge:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV32IZFH-NEXT:    beqz a0, .LBB10_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fmv.h fa0, fa1
-; RV32IZFH-NEXT:  .LBB10_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: select_fcmp_uge:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV64IZFH-NEXT:    beqz a0, .LBB10_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fmv.h fa0, fa1
-; RV64IZFH-NEXT:  .LBB10_2:
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: select_fcmp_uge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.h a0, fa0, fa1
+; CHECK-NEXT:    beqz a0, .LBB10_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.h fa0, fa1
+; CHECK-NEXT:  .LBB10_2:
+; CHECK-NEXT:    ret
   %1 = fcmp uge half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ult(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_ult:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fle.h a0, fa1, fa0
-; RV32IZFH-NEXT:    beqz a0, .LBB11_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fmv.h fa0, fa1
-; RV32IZFH-NEXT:  .LBB11_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: select_fcmp_ult:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fle.h a0, fa1, fa0
-; RV64IZFH-NEXT:    beqz a0, .LBB11_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fmv.h fa0, fa1
-; RV64IZFH-NEXT:  .LBB11_2:
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: select_fcmp_ult:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.h a0, fa1, fa0
+; CHECK-NEXT:    beqz a0, .LBB11_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.h fa0, fa1
+; CHECK-NEXT:  .LBB11_2:
+; CHECK-NEXT:    ret
   %1 = fcmp ult half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ule(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_ule:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    flt.h a0, fa1, fa0
-; RV32IZFH-NEXT:    beqz a0, .LBB12_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fmv.h fa0, fa1
-; RV32IZFH-NEXT:  .LBB12_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: select_fcmp_ule:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    flt.h a0, fa1, fa0
-; RV64IZFH-NEXT:    beqz a0, .LBB12_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fmv.h fa0, fa1
-; RV64IZFH-NEXT:  .LBB12_2:
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: select_fcmp_ule:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.h a0, fa1, fa0
+; CHECK-NEXT:    beqz a0, .LBB12_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.h fa0, fa1
+; CHECK-NEXT:  .LBB12_2:
+; CHECK-NEXT:    ret
   %1 = fcmp ule half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_une(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_une:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa0, fa1
-; RV32IZFH-NEXT:    beqz a0, .LBB13_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fmv.h fa0, fa1
-; RV32IZFH-NEXT:  .LBB13_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: select_fcmp_une:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa0, fa1
-; RV64IZFH-NEXT:    beqz a0, .LBB13_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fmv.h fa0, fa1
-; RV64IZFH-NEXT:  .LBB13_2:
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: select_fcmp_une:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.h a0, fa0, fa1
+; CHECK-NEXT:    beqz a0, .LBB13_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.h fa0, fa1
+; CHECK-NEXT:  .LBB13_2:
+; CHECK-NEXT:    ret
   %1 = fcmp une half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_uno(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_uno:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a0, fa1, fa1
-; RV32IZFH-NEXT:    feq.h a1, fa0, fa0
-; RV32IZFH-NEXT:    and a0, a1, a0
-; RV32IZFH-NEXT:    beqz a0, .LBB14_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    fmv.h fa0, fa1
-; RV32IZFH-NEXT:  .LBB14_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: select_fcmp_uno:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a0, fa1, fa1
-; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
-; RV64IZFH-NEXT:    and a0, a1, a0
-; RV64IZFH-NEXT:    beqz a0, .LBB14_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    fmv.h fa0, fa1
-; RV64IZFH-NEXT:  .LBB14_2:
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: select_fcmp_uno:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.h a0, fa1, fa1
+; CHECK-NEXT:    feq.h a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    beqz a0, .LBB14_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fmv.h fa0, fa1
+; CHECK-NEXT:  .LBB14_2:
+; CHECK-NEXT:    ret
   %1 = fcmp uno half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_true(half %a, half %b) nounwind {
-; RV32IZFH-LABEL: select_fcmp_true:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: select_fcmp_true:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: select_fcmp_true:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ret
   %1 = fcmp true half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 ; Ensure that ISel succeeds for a select+fcmp that has an i32 result type.
 define i32 @i32_select_fcmp_oeq(half %a, half %b, i32 %c, i32 %d) nounwind {
-; RV32IZFH-LABEL: i32_select_fcmp_oeq:
-; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    feq.h a2, fa0, fa1
-; RV32IZFH-NEXT:    bnez a2, .LBB16_2
-; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    mv a0, a1
-; RV32IZFH-NEXT:  .LBB16_2:
-; RV32IZFH-NEXT:    ret
-;
-; RV64IZFH-LABEL: i32_select_fcmp_oeq:
-; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    feq.h a2, fa0, fa1
-; RV64IZFH-NEXT:    bnez a2, .LBB16_2
-; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    mv a0, a1
-; RV64IZFH-NEXT:  .LBB16_2:
-; RV64IZFH-NEXT:    ret
+; CHECK-LABEL: i32_select_fcmp_oeq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.h a2, fa0, fa1
+; CHECK-NEXT:    bnez a2, .LBB16_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    mv a0, a1
+; CHECK-NEXT:  .LBB16_2:
+; CHECK-NEXT:    ret
   %1 = fcmp oeq half %a, %b
   %2 = select i1 %1, i32 %c, i32 %d
   ret i32 %2
 }