[RISCV] Use check-prefixes to reduce check lines

[frasercrmck]

llvm/test/CodeGen/RISCV/float-arith.ll

3

RV32IF is unused and that's an error. You should see this when running locally?

llvm/test/CodeGen/RISCV/float-fcmp-strict.ll

4

RV32IF is unused

llvm/test/CodeGen/RISCV/float-fcmp.ll

3

RV32IF unused

[sunshaoce]

Address @frasercrmck's comments. Thanks!

[sunshaoce]

Add more tests

[frasercrmck]

llvm/test/CodeGen/RISCV/float-isnan.ll

3

--check-prefixes=CHECK is redundant

8

These dead check prefixes can be removed

llvm/test/CodeGen/RISCV/float-select-fcmp.ll

3

Why's this CHECKIF and not CHECK?

8

Dead check prefixes here.

[sunshaoce]

Address @frasercrmck's comments.

[frasercrmck]

llvm/test/CodeGen/RISCV/double-arith-strict.ll

4 ↗

(On Diff #430237)

I think CHECK only fits if it's common to all RUN lines in the test. Here I'd prefer CHECKIFD, for instance, as it's a combined check for the IFD cases.

[sunshaoce]

Address @frasercrmck's comments.

[sunshaoce]

ping

[frasercrmck]

llvm/test/CodeGen/RISCV/double-fcmp-strict.ll

3 ↗

(On Diff #430596)

CHECKIFD here I think since we still have RV32I and RV64I separate

llvm/test/CodeGen/RISCV/double-fcmp.ll

3 ↗

(On Diff #430596)

CHECKIFD here too

llvm/test/CodeGen/RISCV/float-arith-strict.ll

4

CHECKIF - there's no D in this test.

llvm/test/CodeGen/RISCV/float-arith.ll

3

CHECKIF here because RV32I/RV64I are still used

llvm/test/CodeGen/RISCV/float-convert-strict.ll

4

CHECKIF - no D

llvm/test/CodeGen/RISCV/float-convert.ll

3

CHECKIF

llvm/test/CodeGen/RISCV/float-fcmp-strict.ll

4

CHECKIF

llvm/test/CodeGen/RISCV/float-fcmp.ll

3

CHECKIF

llvm/test/CodeGen/RISCV/float-imm.ll

7

I think this comment should be left where it is - it refers to the architecture, not the check prefix.

llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll

4

CHECKIF - no D

llvm/test/CodeGen/RISCV/float-mem.ll

3

CHECKIF

llvm/test/CodeGen/RISCV/float-round-conv-sat.ll

3

CHECKIF

llvm/test/CodeGen/RISCV/half-arith.ll

3 ↗

(On Diff #430596)

CHECKIFZFH so that CHECK doesn't look like it should cover RV32I and RV64I too

llvm/test/CodeGen/RISCV/half-convert-strict.ll

4 ↗

(On Diff #430596)

CHECKIZFH

llvm/test/CodeGen/RISCV/half-convert.ll

3 ↗

(On Diff #430596)

No F or D here - CHECKIZFH

llvm/test/CodeGen/RISCV/half-fcmp.ll

3 ↗

(On Diff #430596)

CHECKIZFH

llvm/test/CodeGen/RISCV/half-intrinsics.ll

4 ↗

(On Diff #430596)

CHECKIZFH

llvm/test/CodeGen/RISCV/half-mem.ll

3 ↗

(On Diff #430596)

CHECKIZFH or CHECK

llvm/test/CodeGen/RISCV/half-round-conv-sat.ll

3 ↗

(On Diff #430596)

CHECKIZFH or CHECK

llvm/test/CodeGen/RISCV/half-round-conv.ll

3 ↗

(On Diff #430596)

CHECKIZFH or CHECK

[sunshaoce]

Address comments.

[frasercrmck]

LGTM, thanks!

llvm/test/CodeGen/RISCV/float-arith-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=ilp32f \
-; RUN:   | FileCheck -check-prefix=RV32IF %s
+; RUN:   | FileCheck -check-prefixes=CHECK,RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=lp64f \
-; RUN:   | FileCheck -check-prefix=RV64IF %s
+; RUN:   | FileCheck -check-prefixes=CHECK,RV64IF %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s
 
 define float @fadd_s(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fadd_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fadd_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fadd_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fadd.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __addsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fadd_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __addsf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.fadd.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata)
 
 define float @fsub_s(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fsub_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fsub.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fsub_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fsub.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fsub_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fsub.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __subsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fsub_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __subsf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.fsub.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.fsub.f32(float, float, metadata, metadata)
 
 define float @fmul_s(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fmul_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmul.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmul_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmul.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmul_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmul.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fmul_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __mulsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fmul_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __mulsf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.fmul.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.fmul.f32(float, float, metadata, metadata)
 
 define float @fdiv_s(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fdiv_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fdiv.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fdiv_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fdiv.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fdiv_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fdiv.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fdiv_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __divsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fdiv_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __divsf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.fdiv.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.fdiv.f32(float, float, metadata, metadata)
 
 define float @fsqrt_s(float %a) nounwind strictfp {
-; RV32IF-LABEL: fsqrt_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fsqrt.s fa0, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fsqrt_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fsqrt.s fa0, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fsqrt_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fsqrt.s fa0, fa0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fsqrt_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call sqrtf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.maxnum.f32(float %a, float %b, metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.maxnum.f32(float, float, metadata) strictfp
 
 define float @fmadd_s(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fmadd_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmadd_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmadd_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmadd.s fa0, fa0, fa1, fa2
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fmadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fmaf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fmadd_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call fmaf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %b, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) strictfp
 
 define float @fmsub_s(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fmsub_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmsub_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmsub_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft0, fa2, ft0
+; CHECK-NEXT:    fmsub.s fa0, fa0, fa1, ft0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fmsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1

 ; RV64I-NEXT:    ret
   %c_ = fadd float 0.0, %c ; avoid negation using xor
   %negc = fneg float %c_
   %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %b, float %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 
 define float @fnmadd_s(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fnmadd_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fnmadd.s fa0, ft1, fa1, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmadd_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fnmadd.s fa0, ft1, fa1, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fnmadd_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft1, fa0, ft0
+; CHECK-NEXT:    fadd.s ft0, fa2, ft0
+; CHECK-NEXT:    fnmadd.s fa0, ft1, fa1, ft0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %c_ = fadd float 0.0, %c
   %nega = fneg float %a_
   %negc = fneg float %c_
   %1 = call float @llvm.experimental.constrained.fma.f32(float %nega, float %b, float %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 
 define float @fnmadd_s_2(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fnmadd_s_2:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft1, fa1, ft0
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fnmadd.s fa0, ft1, fa0, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmadd_s_2:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft1, fa1, ft0
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fnmadd.s fa0, ft1, fa0, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fnmadd_s_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft1, fa1, ft0
+; CHECK-NEXT:    fadd.s ft0, fa2, ft0
+; CHECK-NEXT:    fnmadd.s fa0, ft1, fa0, ft0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmadd_s_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %c_ = fadd float 0.0, %c
   %negb = fneg float %b_
   %negc = fneg float %c_
   %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %negb, float %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 
 define float @fnmsub_s(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fnmsub_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft0, fa0, ft0
-; RV32IF-NEXT:    fnmsub.s fa0, ft0, fa1, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmsub_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft0, fa0, ft0
-; RV64IF-NEXT:    fnmsub.s fa0, ft0, fa1, fa2
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fnmsub_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft0, fa0, ft0
+; CHECK-NEXT:    fnmsub.s fa0, ft0, fa1, fa2
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a2

 ; RV64I-NEXT:    ret
   %a_ = fadd float 0.0, %a
   %nega = fneg float %a_
   %1 = call float @llvm.experimental.constrained.fma.f32(float %nega, float %b, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 
 define float @fnmsub_s_2(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fnmsub_s_2:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft0, fa1, ft0
-; RV32IF-NEXT:    fnmsub.s fa0, ft0, fa0, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmsub_s_2:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft0, fa1, ft0
-; RV64IF-NEXT:    fnmsub.s fa0, ft0, fa0, fa2
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fnmsub_s_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft0, fa1, ft0
+; CHECK-NEXT:    fnmsub.s fa0, ft0, fa0, fa2
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmsub_s_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a2

llvm/test/CodeGen/RISCV/float-arith.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECK %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECK %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 ; These tests are each targeted at a particular RISC-V FPU instruction.
 ; Compares and conversions can be found in float-fcmp.ll and float-convert.ll
 ; respectively. Some other float-*.ll files in this folder exercise LLVM IR
 ; instructions that don't directly match a RISC-V instruction.
 
 define float @fadd_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fadd_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fadd_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fadd_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fadd.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __addsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fadd_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __addsf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fadd float %a, %b
   ret float %1
 }
 
 define float @fsub_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fsub_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fsub.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fsub_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fsub.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fsub_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fsub.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __subsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fsub_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __subsf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fsub float %a, %b
   ret float %1
 }
 
 define float @fmul_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fmul_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmul.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmul_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmul.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmul_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmul.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fmul_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __mulsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fmul_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __mulsf3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fmul float %a, %b
   ret float %1
 }
 
 define float @fdiv_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fdiv_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fdiv.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fdiv_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fdiv.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fdiv_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fdiv.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fdiv_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __divsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = fdiv float %a, %b
   ret float %1
 }
 
 declare float @llvm.sqrt.f32(float)
 
 define float @fsqrt_s(float %a) nounwind {
-; RV32IF-LABEL: fsqrt_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fsqrt.s fa0, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fsqrt_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fsqrt.s fa0, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fsqrt_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fsqrt.s fa0, fa0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fsqrt_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call sqrtf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call float @llvm.sqrt.f32(float %a)
   ret float %1
 }
 
 declare float @llvm.copysign.f32(float, float)
 
 define float @fsgnj_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fsgnj_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fsgnj.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fsgnj_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fsgnj.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fsgnj_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fsgnj.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fsgnj_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a2, 524288
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    slli a0, a0, 1
 ; RV32I-NEXT:    srli a0, a0, 1
 ; RV32I-NEXT:    or a0, a0, a1

 ; RV64I-NEXT:    ret
   %1 = call float @llvm.copysign.f32(float %a, float %b)
   ret float %1
 }
 
 ; This function performs extra work to ensure that
 ; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
 define i32 @fneg_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fneg_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s ft0, fa0, fa0
-; RV32IF-NEXT:    fneg.s ft1, ft0
-; RV32IF-NEXT:    feq.s a0, ft0, ft1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fneg_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s ft0, fa0, fa0
-; RV64IF-NEXT:    fneg.s ft1, ft0
-; RV64IF-NEXT:    feq.s a0, ft0, ft1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fneg_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fadd.s ft0, fa0, fa0
+; CHECK-NEXT:    fneg.s ft1, ft0
+; CHECK-NEXT:    feq.s a0, ft0, ft1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fneg_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    call __addsf3@plt
 ; RV32I-NEXT:    lui a1, 524288
; RV64I-NEXT:    ret
   %3 = fcmp oeq float %1, %2
   %4 = zext i1 %3 to i32
   ret i32 %4
 }
 
 ; This function performs extra work to ensure that
 ; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
 define float @fsgnjn_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fsgnjn_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV32IF-NEXT:    fsgnjn.s fa0, fa0, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fsgnjn_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV64IF-NEXT:    fsgnjn.s fa0, fa0, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fsgnjn_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fadd.s ft0, fa0, fa1
+; CHECK-NEXT:    fsgnjn.s fa0, fa0, ft0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fsgnjn_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    call __addsf3@plt
; RV64I-NEXT:    ret
   ret float %3
 }
 
 declare float @llvm.fabs.f32(float)
 
 ; This function performs extra work to ensure that
 ; DAGCombiner::visitBITCAST doesn't replace the fabs with an and.
 define float @fabs_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fabs_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV32IF-NEXT:    fabs.s ft1, ft0
-; RV32IF-NEXT:    fadd.s fa0, ft1, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fabs_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV64IF-NEXT:    fabs.s ft1, ft0
-; RV64IF-NEXT:    fadd.s fa0, ft1, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fabs_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fadd.s ft0, fa0, fa1
+; CHECK-NEXT:    fabs.s ft1, ft0
+; CHECK-NEXT:    fadd.s fa0, ft1, ft0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fabs_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __addsf3@plt
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    slli a0, a0, 1
; RV64I-NEXT:    ret
   %2 = call float @llvm.fabs.f32(float %1)
   %3 = fadd float %2, %1
   ret float %3
 }
 
 declare float @llvm.minnum.f32(float, float)
 
 define float @fmin_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fmin_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmin.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmin_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmin.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmin_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmin.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fmin_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fminf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call float @llvm.minnum.f32(float %a, float %b)
   ret float %1
 }
 
 declare float @llvm.maxnum.f32(float, float)
 
 define float @fmax_s(float %a, float %b) nounwind {
-; RV32IF-LABEL: fmax_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmax.s fa0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmax_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmax.s fa0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmax_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmax.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fmax_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fmaxf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call float @llvm.maxnum.f32(float %a, float %b)
   ret float %1
 }
 
 declare float @llvm.fma.f32(float, float, float)
 
 define float @fmadd_s(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fmadd_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmadd_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmadd_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmadd.s fa0, fa0, fa1, fa2
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fmadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fmaf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fmadd_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call fmaf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.fma.f32(float %a, float %b, float %c)
   ret float %1
 }
 
 define float @fmsub_s(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fmsub_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmsub_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmsub_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft0, fa2, ft0
+; CHECK-NEXT:    fmsub.s fa0, fa0, fa1, ft0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fmsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1

 ; RV64I-NEXT:    ret
   %c_ = fadd float 0.0, %c ; avoid negation using xor
   %negc = fsub float -0.0, %c_
   %1 = call float @llvm.fma.f32(float %a, float %b, float %negc)
   ret float %1
 }
 
 define float @fnmadd_s(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmadd_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fnmadd.s fa0, ft1, fa1, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmadd_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fnmadd.s fa0, ft1, fa1, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fnmadd_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft1, fa0, ft0
+; CHECK-NEXT:    fadd.s ft0, fa2, ft0
+; CHECK-NEXT:    fnmadd.s fa0, ft1, fa1, ft0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %c_ = fadd float 0.0, %c
   %nega = fsub float -0.0, %a_
   %negc = fsub float -0.0, %c_
   %1 = call float @llvm.fma.f32(float %nega, float %b, float %negc)
   ret float %1
 }
 
 define float @fnmadd_s_2(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmadd_s_2:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft1, fa1, ft0
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fnmadd.s fa0, ft1, fa0, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmadd_s_2:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft1, fa1, ft0
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fnmadd.s fa0, ft1, fa0, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fnmadd_s_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft1, fa1, ft0
+; CHECK-NEXT:    fadd.s ft0, fa2, ft0
+; CHECK-NEXT:    fnmadd.s fa0, ft1, fa0, ft0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmadd_s_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %c_ = fadd float 0.0, %c
   %negb = fsub float -0.0, %b_
   %negc = fsub float -0.0, %c_
   %1 = call float @llvm.fma.f32(float %a, float %negb, float %negc)
   ret float %1
 }
 
 define float @fnmsub_s(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmsub_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft0, fa0, ft0
-; RV32IF-NEXT:    fnmsub.s fa0, ft0, fa1, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmsub_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft0, fa0, ft0
-; RV64IF-NEXT:    fnmsub.s fa0, ft0, fa1, fa2
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fnmsub_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft0, fa0, ft0
+; CHECK-NEXT:    fnmsub.s fa0, ft0, fa1, fa2
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a2

 ; RV64I-NEXT:    ret
   %a_ = fadd float 0.0, %a
   %nega = fsub float -0.0, %a_
   %1 = call float @llvm.fma.f32(float %nega, float %b, float %c)
   ret float %1
 }
 
 define float @fnmsub_s_2(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmsub_s_2:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft0, fa1, ft0
-; RV32IF-NEXT:    fnmsub.s fa0, ft0, fa0, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmsub_s_2:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft0, fa1, ft0
-; RV64IF-NEXT:    fnmsub.s fa0, ft0, fa0, fa2
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fnmsub_s_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft0, fa1, ft0
+; CHECK-NEXT:    fnmsub.s fa0, ft0, fa0, fa2
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmsub_s_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a2

 ; RV64I-NEXT:    ret
   %b_ = fadd float 0.0, %b
   %negb = fsub float -0.0, %b_
   %1 = call float @llvm.fma.f32(float %a, float %negb, float %c)
   ret float %1
 }
 
 define float @fmadd_s_contract(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fmadd_s_contract:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmadd_s_contract:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmadd_s_contract:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmadd.s fa0, fa0, fa1, fa2
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fmadd_s_contract:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    call __mulsf3@plt

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fmul contract float %a, %b
   %2 = fadd contract float %1, %c
   ret float %2
 }
 
 define float @fmsub_s_contract(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fmsub_s_contract:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmsub_s_contract:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fmsub.s fa0, fa0, fa1, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmsub_s_contract:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft0, fa2, ft0
+; CHECK-NEXT:    fmsub.s fa0, fa0, fa1, ft0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fmsub_s_contract:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ret
   %c_ = fadd float 0.0, %c ; avoid negation using xor
   %1 = fmul contract float %a, %b
   %2 = fsub contract float %1, %c_
   ret float %2
 }
 
 define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmadd_s_contract:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV32IF-NEXT:    fadd.s ft2, fa1, ft0
-; RV32IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV32IF-NEXT:    fnmadd.s fa0, ft1, ft2, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmadd_s_contract:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV64IF-NEXT:    fadd.s ft2, fa1, ft0
-; RV64IF-NEXT:    fadd.s ft0, fa2, ft0
-; RV64IF-NEXT:    fnmadd.s fa0, ft1, ft2, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fnmadd_s_contract:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft1, fa0, ft0
+; CHECK-NEXT:    fadd.s ft2, fa1, ft0
+; CHECK-NEXT:    fadd.s ft0, fa2, ft0
+; CHECK-NEXT:    fnmadd.s fa0, ft1, ft2, ft0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmadd_s_contract:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %c_ = fadd float 0.0, %c ; avoid negation using xor
   %1 = fmul contract float %a_, %b_
   %2 = fneg float %1
   %3 = fsub contract float %2, %c_
   ret float %3
 }
 
 define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind {
-; RV32IF-LABEL: fnmsub_s_contract:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, zero
-; RV32IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV32IF-NEXT:    fadd.s ft0, fa1, ft0
-; RV32IF-NEXT:    fnmsub.s fa0, ft1, ft0, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fnmsub_s_contract:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, zero
-; RV64IF-NEXT:    fadd.s ft1, fa0, ft0
-; RV64IF-NEXT:    fadd.s ft0, fa1, ft0
-; RV64IF-NEXT:    fnmsub.s fa0, ft1, ft0, fa2
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fnmsub_s_contract:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, zero
+; CHECK-NEXT:    fadd.s ft1, fa0, ft0
+; CHECK-NEXT:    fadd.s ft0, fa1, ft0
+; CHECK-NEXT:    fnmsub.s fa0, ft1, ft0, fa2
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fnmsub_s_contract:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

llvm/test/CodeGen/RISCV/float-convert-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=ilp32f \
-; RUN:   | FileCheck -check-prefix=RV32IF %s
+; RUN:   | FileCheck -check-prefixes=CHECK,RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=lp64f \
-; RUN:   | FileCheck -check-prefix=RV64IF %s
+; RUN:   | FileCheck -check-prefixes=CHECK,RV64IF %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s
 
 ; NOTE: The rounding mode metadata does not effect which instruction is
 ; selected. Dynamic rounding mode is always used for operations that
 ; support rounding mode.
 
 define i32 @fcvt_w_s(float %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_w_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_w_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_w_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.w.s a0, fa0, rtz
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_w_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixsfsi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_w_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __fixsfsi@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata)
 
 define i32 @fcvt_wu_s(float %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_wu_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_wu_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_wu_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.wu.s a0, fa0, rtz
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunssfsi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
; RV64I-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata)
 
 ; Test where the fptoui has multiple uses, one of which causes a sext to be
 ; inserted on RV64.
 define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) nounwind {
-; RV32IF-LABEL: fcvt_wu_s_multiple_use:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.wu.s a1, fa0, rtz
-; RV32IF-NEXT:    li a0, 1
-; RV32IF-NEXT:    beqz a1, .LBB2_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    mv a0, a1
-; RV32IF-NEXT:  .LBB2_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_wu_s_multiple_use:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.wu.s a1, fa0, rtz
-; RV64IF-NEXT:    li a0, 1
-; RV64IF-NEXT:    beqz a1, .LBB2_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    mv a0, a1
-; RV64IF-NEXT:  .LBB2_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_wu_s_multiple_use:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.wu.s a1, fa0, rtz
+; CHECK-NEXT:    li a0, 1
+; CHECK-NEXT:    beqz a1, .LBB2_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    mv a0, a1
+; CHECK-NEXT:  .LBB2_2:
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s_multiple_use:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunssfsi@plt
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    li a0, 1

 ; RV64I-NEXT:    ret
   %a = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %x, metadata !"fpexcept.strict") strictfp
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c
 }
 
 define float @fcvt_s_w(i32 %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_w:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_w:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.w fa0, a0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.sitofp.f32.i32(i32, metadata, metadata)
 
 define float @fcvt_s_w_load(i32* %p) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_w_load:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    lw a0, 0(a0)
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w_load:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    lw a0, 0(a0)
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_w_load:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lw a0, 0(a0)
+; CHECK-NEXT:    fcvt.s.w fa0, a0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w_load:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    lw a0, 0(a0)
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %a = load i32, i32* %p
   %1 = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 
 define float @fcvt_s_wu(i32 %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_wu:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.wu fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_wu:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.wu fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_wu:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.wu fa0, a0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_wu:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.uitofp.f32.i64(i64 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.uitofp.f32.i64(i64, metadata, metadata)
 
 define float @fcvt_s_w_i8(i8 signext %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_w_i8:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w_i8:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_w_i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.w fa0, a0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_w_i8:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatsisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.sitofp.f32.i8(i8 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.sitofp.f32.i8(i8, metadata, metadata)
 
 define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_wu_i8:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.wu fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_wu_i8:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.wu fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_wu_i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.wu fa0, a0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_wu_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_wu_i8:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatunsisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.uitofp.f32.i8(i8 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
   ret float %1
 }
 declare float @llvm.experimental.constrained.uitofp.f32.i8(i8, metadata, metadata)
 
 define float @fcvt_s_w_i16(i16 signext %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_w_i16:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w_i16:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_w_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.w fa0, a0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_w_i16:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatsisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.sitofp.f32.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 declare float @llvm.experimental.constrained.sitofp.f32.i16(i16, metadata, metadata)
 
 define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind strictfp {
-; RV32IF-LABEL: fcvt_s_wu_i16:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.wu fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_wu_i16:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.wu fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_wu_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.wu fa0, a0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_wu_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

llvm/test/CodeGen/RISCV/float-convert.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECK,RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECK,RV64IF %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 define i32 @fcvt_w_s(float %a) nounwind {
-; RV32IF-LABEL: fcvt_w_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_w_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_w_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.w.s a0, fa0, rtz
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_w_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixsfsi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_w_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __fixsfsi@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fptosi float %a to i32
   ret i32 %1
 }
 
 define i32 @fcvt_w_s_sat(float %a) nounwind {
-; RV32IF-LABEL: fcvt_w_s_sat:
-; RV32IF:       # %bb.0: # %start
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB1_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV32IF-NEXT:  .LBB1_2: # %start
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_w_s_sat:
-; RV64IF:       # %bb.0: # %start
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB1_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV64IF-NEXT:  .LBB1_2: # %start
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_w_s_sat:
+; CHECK:       # %bb.0: # %start
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB1_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.w.s a0, fa0, rtz
+; CHECK-NEXT:  .LBB1_2: # %start
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_w_s_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %0
 }
 declare i32 @llvm.fptosi.sat.i32.f32(float)
 
 define i32 @fcvt_wu_s(float %a) nounwind {
-; RV32IF-LABEL: fcvt_wu_s:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_wu_s:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_wu_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.wu.s a0, fa0, rtz
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunssfsi@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = fptoui float %a to i32
   ret i32 %1
 }
 
 ; Test where the fptoui has multiple uses, one of which causes a sext to be
 ; inserted on RV64.
 define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) nounwind {
-; RV32IF-LABEL: fcvt_wu_s_multiple_use:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.wu.s a1, fa0, rtz
-; RV32IF-NEXT:    li a0, 1
-; RV32IF-NEXT:    beqz a1, .LBB3_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    mv a0, a1
-; RV32IF-NEXT:  .LBB3_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_wu_s_multiple_use:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.wu.s a1, fa0, rtz
-; RV64IF-NEXT:    li a0, 1
-; RV64IF-NEXT:    beqz a1, .LBB3_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    mv a0, a1
-; RV64IF-NEXT:  .LBB3_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_wu_s_multiple_use:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.wu.s a1, fa0, rtz
+; CHECK-NEXT:    li a0, 1
+; CHECK-NEXT:    beqz a1, .LBB3_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    mv a0, a1
+; CHECK-NEXT:  .LBB3_2:
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s_multiple_use:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunssfsi@plt
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    li a0, 1

 ; RV64I-NEXT:    ret
   %a = fptoui float %x to i32
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c
 }
 
 define i32 @fcvt_wu_s_sat(float %a) nounwind {
-; RV32IF-LABEL: fcvt_wu_s_sat:
-; RV32IF:       # %bb.0: # %start
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB4_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV32IF-NEXT:  .LBB4_2: # %start
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_wu_s_sat:
-; RV64IF:       # %bb.0: # %start
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB4_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV64IF-NEXT:  .LBB4_2: # %start
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_wu_s_sat:
+; CHECK:       # %bb.0: # %start
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB4_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.wu.s a0, fa0, rtz
+; CHECK-NEXT:  .LBB4_2: # %start
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %0
 }
 declare i32 @llvm.fptoui.sat.i32.f32(float)
 
 define i32 @fmv_x_w(float %a, float %b) nounwind {
-; RV32IF-LABEL: fmv_x_w:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV32IF-NEXT:    fmv.x.w a0, ft0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmv_x_w:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV64IF-NEXT:    fmv.x.w a0, ft0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmv_x_w:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fadd.s ft0, fa0, fa1
+; CHECK-NEXT:    fmv.x.w a0, ft0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fmv_x_w:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __addsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
 ; Ensure fmv.x.w is generated even for a soft float calling convention
   %1 = fadd float %a, %b
   %2 = bitcast float %1 to i32
   ret i32 %2
 }
 
 define float @fcvt_s_w(i32 %a) nounwind {
-; RV32IF-LABEL: fcvt_s_w:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_w:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.w fa0, a0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_w:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    call __floatsisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = sitofp i32 %a to float
   ret float %1
 }
 
 define float @fcvt_s_w_load(i32* %p) nounwind {
-; RV32IF-LABEL: fcvt_s_w_load:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    lw a0, 0(a0)
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w_load:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    lw a0, 0(a0)
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_w_load:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lw a0, 0(a0)
+; CHECK-NEXT:    fcvt.s.w fa0, a0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w_load:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    lw a0, 0(a0)
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %a = load i32, i32* %p
   %1 = sitofp i32 %a to float
   ret float %1
 }
 
 define float @fcvt_s_wu(i32 %a) nounwind {
-; RV32IF-LABEL: fcvt_s_wu:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.wu fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_wu:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.wu fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_wu:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.wu fa0, a0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_wu:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %a = load i32, i32* %p
   %1 = uitofp i32 %a to float
   ret float %1
 }
 
 define float @fmv_w_x(i32 %a, i32 %b) nounwind {
-; RV32IF-LABEL: fmv_w_x:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmv.w.x ft0, a0
-; RV32IF-NEXT:    fmv.w.x ft1, a1
-; RV32IF-NEXT:    fadd.s fa0, ft0, ft1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmv_w_x:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmv.w.x ft0, a0
-; RV64IF-NEXT:    fmv.w.x ft1, a1
-; RV64IF-NEXT:    fadd.s fa0, ft0, ft1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmv_w_x:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    fmv.w.x ft1, a1
+; CHECK-NEXT:    fadd.s fa0, ft0, ft1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fmv_w_x:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __addsf3@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = uitofp i64 %a to float
   ret float %1
 }
 
 define float @fcvt_s_w_i8(i8 signext %a) nounwind {
-; RV32IF-LABEL: fcvt_s_w_i8:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w_i8:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_w_i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.w fa0, a0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_w_i8:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatsisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = sitofp i8 %a to float
   ret float %1
 }
 
 define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind {
-; RV32IF-LABEL: fcvt_s_wu_i8:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.wu fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_wu_i8:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.wu fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_wu_i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.wu fa0, a0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_wu_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_wu_i8:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatunsisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = uitofp i8 %a to float
   ret float %1
 }
 
 define float @fcvt_s_w_i16(i16 signext %a) nounwind {
-; RV32IF-LABEL: fcvt_s_w_i16:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.w fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_w_i16:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.w fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_w_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.w fa0, a0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_w_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_s_w_i16:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __floatsisf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = sitofp i16 %a to float
   ret float %1
 }
 
 define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind {
-; RV32IF-LABEL: fcvt_s_wu_i16:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.s.wu fa0, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcvt_s_wu_i16:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.s.wu fa0, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcvt_s_wu_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fcvt.s.wu fa0, a0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_s_wu_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

llvm/test/CodeGen/RISCV/float-fcmp-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=ilp32f \
-; RUN:   | FileCheck -check-prefix=RV32IF %s
+; RUN:   | FileCheck -check-prefixes=CHECK %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation -target-abi=lp64f \
-; RUN:   | FileCheck -check-prefix=RV64IF %s
+; RUN:   | FileCheck -check-prefixes=CHECK %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV64I %s
 
 define i32 @fcmp_oeq(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_oeq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_oeq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_oeq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oeq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __eqsf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"oeq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 declare i1 @llvm.experimental.constrained.fcmp.f32(float, float, metadata, metadata)
 
 define i32 @fcmp_ogt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ogt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a1
-; RV32IF-NEXT:    flt.s a0, fa1, fa0
-; RV32IF-NEXT:    fsflags a1
-; RV32IF-NEXT:    feq.s zero, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ogt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a1
-; RV64IF-NEXT:    flt.s a0, fa1, fa0
-; RV64IF-NEXT:    fsflags a1
-; RV64IF-NEXT:    feq.s zero, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ogt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a1
+; CHECK-NEXT:    flt.s a0, fa1, fa0
+; CHECK-NEXT:    fsflags a1
+; CHECK-NEXT:    feq.s zero, fa1, fa0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oge(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_oge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a1
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    fsflags a1
-; RV32IF-NEXT:    feq.s zero, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_oge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a1
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    fsflags a1
-; RV64IF-NEXT:    feq.s zero, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_oge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a1
+; CHECK-NEXT:    fle.s a0, fa1, fa0
+; CHECK-NEXT:    fsflags a1
+; CHECK-NEXT:    feq.s zero, fa1, fa0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_olt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_olt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a1
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    fsflags a1
-; RV32IF-NEXT:    feq.s zero, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_olt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a1
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    fsflags a1
-; RV64IF-NEXT:    feq.s zero, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_olt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a1
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    fsflags a1
+; CHECK-NEXT:    feq.s zero, fa0, fa1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_olt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ole(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ole:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a1
-; RV32IF-NEXT:    fle.s a0, fa0, fa1
-; RV32IF-NEXT:    fsflags a1
-; RV32IF-NEXT:    feq.s zero, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ole:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a1
-; RV64IF-NEXT:    fle.s a0, fa0, fa1
-; RV64IF-NEXT:    fsflags a1
-; RV64IF-NEXT:    feq.s zero, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ole:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a1
+; CHECK-NEXT:    fle.s a0, fa0, fa1
+; CHECK-NEXT:    fsflags a1
+; CHECK-NEXT:    feq.s zero, fa0, fa1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ole:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 ; FIXME: We only need one frflags before the two flts and one fsflags after the
 ; two flts.
 define i32 @fcmp_one(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_one:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    flt.s a1, fa0, fa1
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    feq.s zero, fa0, fa1
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    flt.s a2, fa1, fa0
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    or a0, a2, a1
-; RV32IF-NEXT:    feq.s zero, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_one:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    flt.s a1, fa0, fa1
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    feq.s zero, fa0, fa1
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    flt.s a2, fa1, fa0
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    or a0, a2, a1
-; RV64IF-NEXT:    feq.s zero, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_one:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    flt.s a1, fa0, fa1
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    feq.s zero, fa0, fa1
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    flt.s a2, fa1, fa0
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    or a0, a2, a1
+; CHECK-NEXT:    feq.s zero, fa1, fa0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"one", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ord(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ord:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa1, fa1
-; RV32IF-NEXT:    feq.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ord:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa1, fa1
-; RV64IF-NEXT:    feq.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ord:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa1, fa1
+; CHECK-NEXT:    feq.s a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ord:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ord", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 ; FIXME: We only need one frflags before the two flts and one fsflags after the
 ; two flts.
 define i32 @fcmp_ueq(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ueq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    flt.s a1, fa0, fa1
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    feq.s zero, fa0, fa1
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    flt.s a2, fa1, fa0
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    or a0, a2, a1
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    feq.s zero, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ueq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    flt.s a1, fa0, fa1
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    feq.s zero, fa0, fa1
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    flt.s a2, fa1, fa0
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    or a0, a2, a1
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    feq.s zero, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ueq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    flt.s a1, fa0, fa1
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    feq.s zero, fa0, fa1
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    flt.s a2, fa1, fa0
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    or a0, a2, a1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    feq.s zero, fa1, fa0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ueq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ugt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ugt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    fle.s a1, fa0, fa1
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    xori a0, a1, 1
-; RV32IF-NEXT:    feq.s zero, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ugt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    fle.s a1, fa0, fa1
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    xori a0, a1, 1
-; RV64IF-NEXT:    feq.s zero, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ugt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    fle.s a1, fa0, fa1
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    xori a0, a1, 1
+; CHECK-NEXT:    feq.s zero, fa0, fa1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uge(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_uge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    flt.s a1, fa0, fa1
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    xori a0, a1, 1
-; RV32IF-NEXT:    feq.s zero, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_uge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    flt.s a1, fa0, fa1
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    xori a0, a1, 1
-; RV64IF-NEXT:    feq.s zero, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_uge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    flt.s a1, fa0, fa1
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    xori a0, a1, 1
+; CHECK-NEXT:    feq.s zero, fa0, fa1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ult(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ult:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    fle.s a1, fa1, fa0
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    xori a0, a1, 1
-; RV32IF-NEXT:    feq.s zero, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ult:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    fle.s a1, fa1, fa0
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    xori a0, a1, 1
-; RV64IF-NEXT:    feq.s zero, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ult:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    fle.s a1, fa1, fa0
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    xori a0, a1, 1
+; CHECK-NEXT:    feq.s zero, fa1, fa0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ult:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ult", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ule(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_ule:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    frflags a0
-; RV32IF-NEXT:    flt.s a1, fa1, fa0
-; RV32IF-NEXT:    fsflags a0
-; RV32IF-NEXT:    xori a0, a1, 1
-; RV32IF-NEXT:    feq.s zero, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ule:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    frflags a0
-; RV64IF-NEXT:    flt.s a1, fa1, fa0
-; RV64IF-NEXT:    fsflags a0
-; RV64IF-NEXT:    xori a0, a1, 1
-; RV64IF-NEXT:    feq.s zero, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ule:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    frflags a0
+; CHECK-NEXT:    flt.s a1, fa1, fa0
+; CHECK-NEXT:    fsflags a0
+; CHECK-NEXT:    xori a0, a1, 1
+; CHECK-NEXT:    feq.s zero, fa1, fa0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ule", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_une(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_une:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa1
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_une:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa1
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_une:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_une:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __nesf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"une", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uno(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmp_uno:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa1, fa1
-; RV32IF-NEXT:    feq.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_uno:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa1, fa1
-; RV64IF-NEXT:    feq.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_uno:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa1, fa1
+; CHECK-NEXT:    feq.s a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uno:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"uno", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_oeq(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_oeq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    fle.s a1, fa0, fa1
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_oeq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    fle.s a1, fa0, fa1
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_oeq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa1, fa0
+; CHECK-NEXT:    fle.s a1, fa0, fa1
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_oeq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __eqsf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"oeq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 declare i1 @llvm.experimental.constrained.fcmps.f32(float, float, metadata, metadata)
 
 define i32 @fcmps_ogt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ogt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_ogt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_ogt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa1, fa0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_oge(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_oge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_oge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_oge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa1, fa0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_olt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_olt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_olt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_olt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_olt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ole(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ole:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_ole:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_ole:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa0, fa1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ole:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_one(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_one:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    flt.s a1, fa1, fa0
-; RV32IF-NEXT:    or a0, a1, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_one:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    flt.s a1, fa1, fa0
-; RV64IF-NEXT:    or a0, a1, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_one:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    flt.s a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"one", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ord(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ord:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa1
-; RV32IF-NEXT:    fle.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_ord:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa1
-; RV64IF-NEXT:    fle.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_ord:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa1, fa1
+; CHECK-NEXT:    fle.s a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ord:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ord", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ueq(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ueq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    flt.s a1, fa1, fa0
-; RV32IF-NEXT:    or a0, a1, a0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_ueq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    flt.s a1, fa1, fa0
-; RV64IF-NEXT:    or a0, a1, a0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_ueq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    flt.s a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ueq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ugt(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ugt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa0, fa1
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_ugt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa0, fa1
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_ugt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_uge(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_uge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_uge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_uge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ult(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ult:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_ult:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_ult:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa1, fa0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ult:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ult", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ule(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_ule:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa1, fa0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_ule:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa1, fa0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_ule:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa1, fa0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"ule", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_une(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_une:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    fle.s a1, fa0, fa1
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_une:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    fle.s a1, fa0, fa1
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_une:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa1, fa0
+; CHECK-NEXT:    fle.s a1, fa0, fa1
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_une:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __nesf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f32(float %a, float %b, metadata !"une", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_uno(float %a, float %b) nounwind strictfp {
-; RV32IF-LABEL: fcmps_uno:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa1
-; RV32IF-NEXT:    fle.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmps_uno:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa1
-; RV64IF-NEXT:    fle.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmps_uno:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa1, fa1
+; CHECK-NEXT:    fle.s a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmps_uno:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

llvm/test/CodeGen/RISCV/float-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECK %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECK %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 define i32 @fcmp_false(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_false:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_false:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_false:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_false:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a0, 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_false:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 0
 ; RV64I-NEXT:    ret
   %1 = fcmp false float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oeq(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_oeq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_oeq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_oeq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oeq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __eqsf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp oeq float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ogt(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ogt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ogt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ogt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa1, fa0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ogt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oge(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_oge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_oge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_oge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa1, fa0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp oge float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_olt(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_olt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_olt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_olt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_olt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp olt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ole(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ole:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa0, fa1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ole:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa0, fa1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ole:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa0, fa1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ole:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ole float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_one(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_one:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    flt.s a1, fa1, fa0
-; RV32IF-NEXT:    or a0, a1, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_one:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    flt.s a1, fa1, fa0
-; RV64IF-NEXT:    or a0, a1, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_one:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    flt.s a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = fcmp one float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ord(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ord:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa1, fa1
-; RV32IF-NEXT:    feq.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ord:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa1, fa1
-; RV64IF-NEXT:    feq.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ord:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa1, fa1
+; CHECK-NEXT:    feq.s a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ord:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ord float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ueq(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ueq:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    flt.s a1, fa1, fa0
-; RV32IF-NEXT:    or a0, a1, a0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ueq:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    flt.s a1, fa1, fa0
-; RV64IF-NEXT:    or a0, a1, a0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ueq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    flt.s a1, fa1, fa0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ueq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill

 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
   %1 = fcmp ueq float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ugt(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ugt:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa0, fa1
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ugt:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa0, fa1
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ugt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ugt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uge(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_uge:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_uge:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_uge:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp uge float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ult(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ult:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ult:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ult:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa1, fa0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ult:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ult float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ule(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_ule:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa1, fa0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_ule:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa1, fa0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_ule:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flt.s a0, fa1, fa0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp ule float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_une(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_une:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa1
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_une:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa1
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_une:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_une:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __nesf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp une float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uno(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_uno:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa1, fa1
-; RV32IF-NEXT:    feq.s a1, fa0, fa0
-; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:    xori a0, a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_uno:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa1, fa1
-; RV64IF-NEXT:    feq.s a1, fa0, fa0
-; RV64IF-NEXT:    and a0, a1, a0
-; RV64IF-NEXT:    xori a0, a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_uno:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa1, fa1
+; CHECK-NEXT:    feq.s a1, fa0, fa0
+; CHECK-NEXT:    and a0, a1, a0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uno:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = fcmp uno float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_true(float %a, float %b) nounwind {
-; RV32IF-LABEL: fcmp_true:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    li a0, 1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fcmp_true:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    li a0, 1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fcmp_true:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 1
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_true:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_true:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 1
 ; RV64I-NEXT:    ret
   %1 = fcmp true float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/float-imm.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECK %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECK %s
 
 ; TODO: constant pool shouldn't be necessary for RV64IF.
 define float @float_imm() nounwind {
 ; RV32IF-LABEL: float_imm:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    lui a0, %hi(.LCPI0_0)
 ; RV32IF-NEXT:    flw fa0, %lo(.LCPI0_0)(a0)
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: float_imm:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    lui a0, %hi(.LCPI0_0)
 ; RV64IF-NEXT:    flw fa0, %lo(.LCPI0_0)(a0)
 ; RV64IF-NEXT:    ret
+; CHECK-LABEL: float_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI0_0)
+; CHECK-NEXT:    flw fa0, %lo(.LCPI0_0)(a0)
+; CHECK-NEXT:    ret
   ret float 3.14159274101257324218750
 }
 
 define float @float_imm_op(float %a) nounwind {
 ; RV32IF-LABEL: float_imm_op:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    lui a0, %hi(.LCPI1_0)
 ; RV32IF-NEXT:    flw ft0, %lo(.LCPI1_0)(a0)
 ; RV32IF-NEXT:    fadd.s fa0, fa0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: float_imm_op:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    lui a0, %hi(.LCPI1_0)
 ; RV64IF-NEXT:    flw ft0, %lo(.LCPI1_0)(a0)
 ; RV64IF-NEXT:    fadd.s fa0, fa0, ft0
 ; RV64IF-NEXT:    ret
+; CHECK-LABEL: float_imm_op:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI1_0)
+; CHECK-NEXT:    flw ft0, %lo(.LCPI1_0)(a0)
+; CHECK-NEXT:    fadd.s fa0, fa0, ft0
+; CHECK-NEXT:    ret
   %1 = fadd float %a, 1.0
   ret float %1
 }

llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f \
 ; RUN:   -verify-machineinstrs -disable-strictnode-mutation -target-abi=ilp32f \
-; RUN:   | FileCheck -check-prefix=RV32IF %s
+; RUN:   | FileCheck -check-prefixes=CHECK,RV32IF %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f \
 ; RUN:   -verify-machineinstrs -disable-strictnode-mutation -target-abi=lp64f \
-; RUN:   | FileCheck -check-prefix=RV64IF %s
+; RUN:   | FileCheck -check-prefixes=CHECK,RV64IF %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
 ; RUN:   -verify-machineinstrs -disable-strictnode-mutation \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
 ; RUN:   -verify-machineinstrs -disable-strictnode-mutation \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
 declare float @llvm.experimental.constrained.sqrt.f32(float, metadata, metadata)
 
 define float @sqrt_f32(float %a) nounwind strictfp {
-; RV32IF-LABEL: sqrt_f32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fsqrt.s fa0, fa0
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: sqrt_f32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fsqrt.s fa0, fa0
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: sqrt_f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fsqrt.s fa0, fa0
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: sqrt_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call sqrtf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.log2.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 
 declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata)
 
 define float @fma_f32(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fma_f32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fma_f32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fma_f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmadd.s fa0, fa0, fa1, fa2
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fma_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call fmaf@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; RV64I-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.fma.f32(float %a, float %b, float %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret float %1
 }
 
 declare float @llvm.experimental.constrained.fmuladd.f32(float, float, float, metadata, metadata)
 
 define float @fmuladd_f32(float %a, float %b, float %c) nounwind strictfp {
-; RV32IF-LABEL: fmuladd_f32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fmuladd_f32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fmuladd_f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmadd.s fa0, fa0, fa1, fa2
+; CHECK-NEXT:    ret
 ;
 ; RV32I-LABEL: fmuladd_f32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a2
 ; RV32I-NEXT:    call __mulsf3@plt

llvm/test/CodeGen/RISCV/float-isnan.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs \
-; RUN:   < %s | FileCheck -check-prefix=RV32IF %s
+; RUN:   < %s | FileCheck -check-prefixes=CHECK %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs \
-; RUN:   < %s | FileCheck -check-prefix=RV64IF %s
+; RUN:   < %s | FileCheck -check-prefixes=CHECK %s
 
 define zeroext i1 @float_is_nan(float %a) nounwind {
 ; RV32IF-LABEL: float_is_nan:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    feq.s a0, fa0, fa0
 ; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: float_is_nan:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    xori a0, a0, 1
 ; RV64IF-NEXT:    ret
+; CHECK-LABEL: float_is_nan:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    ret
   %1 = fcmp uno float %a, 0.000000e+00
   ret i1 %1
 }
 
 define zeroext i1 @float_not_nan(float %a) nounwind {
 ; RV32IF-LABEL: float_not_nan:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    feq.s a0, fa0, fa0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: float_not_nan:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
 ; RV64IF-NEXT:    ret
+; CHECK-LABEL: float_not_nan:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    ret
   %1 = fcmp ord float %a, 0.000000e+00
   ret i1 %1
 }

llvm/test/CodeGen/RISCV/float-mem.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECK,RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECK,RV64IF %s
 
 define dso_local float @flw(float *%a) nounwind {
-; RV32IF-LABEL: flw:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flw ft0, 0(a0)
-; RV32IF-NEXT:    flw ft1, 12(a0)
-; RV32IF-NEXT:    fadd.s fa0, ft0, ft1
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: flw:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flw ft0, 0(a0)
-; RV64IF-NEXT:    flw ft1, 12(a0)
-; RV64IF-NEXT:    fadd.s fa0, ft0, ft1
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: flw:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flw ft0, 0(a0)
+; CHECK-NEXT:    flw ft1, 12(a0)
+; CHECK-NEXT:    fadd.s fa0, ft0, ft1
+; CHECK-NEXT:    ret
   %1 = load float, float* %a
   %2 = getelementptr float, float* %a, i32 3
   %3 = load float, float* %2
 ; Use both loaded values in an FP op to ensure an flw is used, even for the
 ; soft float ABI
   %4 = fadd float %1, %3
   ret float %4
 }
 
 define dso_local void @fsw(float *%a, float %b, float %c) nounwind {
 ; Use %b and %c in an FP op to ensure floating point registers are used, even
 ; for the soft float ABI
-; RV32IF-LABEL: fsw:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV32IF-NEXT:    fsw ft0, 0(a0)
-; RV32IF-NEXT:    fsw ft0, 32(a0)
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: fsw:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s ft0, fa0, fa1
-; RV64IF-NEXT:    fsw ft0, 0(a0)
-; RV64IF-NEXT:    fsw ft0, 32(a0)
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: fsw:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fadd.s ft0, fa0, fa1
+; CHECK-NEXT:    fsw ft0, 0(a0)
+; CHECK-NEXT:    fsw ft0, 32(a0)
+; CHECK-NEXT:    ret
   %1 = fadd float %b, %c
   store float %1, float* %a
   %2 = getelementptr float, float* %a, i32 8
   store float %1, float* %2
   ret void
 }
 
 ; Check load and store to a global
 @G = dso_local global float 0.0
 
 define dso_local float @flw_fsw_global(float %a, float %b) nounwind {
 ; Use %a and %b in an FP op to ensure floating point registers are used, even
 ; for the soft float ABI
-; RV32IF-LABEL: flw_fsw_global:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fadd.s fa0, fa0, fa1
-; RV32IF-NEXT:    lui a0, %hi(G)
-; RV32IF-NEXT:    flw ft0, %lo(G)(a0)
-; RV32IF-NEXT:    fsw fa0, %lo(G)(a0)
-; RV32IF-NEXT:    addi a0, a0, %lo(G)
-; RV32IF-NEXT:    flw ft0, 36(a0)
-; RV32IF-NEXT:    fsw fa0, 36(a0)
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: flw_fsw_global:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fadd.s fa0, fa0, fa1
-; RV64IF-NEXT:    lui a0, %hi(G)
-; RV64IF-NEXT:    flw ft0, %lo(G)(a0)
-; RV64IF-NEXT:    fsw fa0, %lo(G)(a0)
-; RV64IF-NEXT:    addi a0, a0, %lo(G)
-; RV64IF-NEXT:    flw ft0, 36(a0)
-; RV64IF-NEXT:    fsw fa0, 36(a0)
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: flw_fsw_global:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fadd.s fa0, fa0, fa1
+; CHECK-NEXT:    lui a0, %hi(G)
+; CHECK-NEXT:    flw ft0, %lo(G)(a0)
+; CHECK-NEXT:    fsw fa0, %lo(G)(a0)
+; CHECK-NEXT:    addi a0, a0, %lo(G)
+; CHECK-NEXT:    flw ft0, 36(a0)
+; CHECK-NEXT:    fsw fa0, 36(a0)
+; CHECK-NEXT:    ret
   %1 = fadd float %a, %b
   %2 = load volatile float, float* @G
   store float %1, float* @G
   %3 = getelementptr float, float* @G, i32 9
   %4 = load volatile float, float* %3
   store float %1, float* %3
   ret float %1
 }

llvm/test/CodeGen/RISCV/float-round-conv-sat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECK,RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECK,RV64IF %s
 
 define signext i32 @test_floor_si32(float %x) {
-; RV32IF-LABEL: test_floor_si32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB0_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rdn
-; RV32IF-NEXT:  .LBB0_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_floor_si32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB0_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rdn
-; RV64IF-NEXT:  .LBB0_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: test_floor_si32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB0_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.w.s a0, fa0, rdn
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_floor_si64(float %x) nounwind {
 ; RV32IF-LABEL: test_floor_si64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:  .LBB1_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_floor_ui32(float %x) {
-; RV32IF-LABEL: test_floor_ui32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB2_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rdn
-; RV32IF-NEXT:  .LBB2_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_floor_ui32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB2_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rdn
-; RV64IF-NEXT:  .LBB2_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: test_floor_ui32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB2_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.wu.s a0, fa0, rdn
+; CHECK-NEXT:  .LBB2_2:
+; CHECK-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_floor_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_floor_ui64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:  .LBB3_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_ceil_si32(float %x) {
-; RV32IF-LABEL: test_ceil_si32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB4_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rup
-; RV32IF-NEXT:  .LBB4_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_ceil_si32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB4_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rup
-; RV64IF-NEXT:  .LBB4_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: test_ceil_si32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB4_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.w.s a0, fa0, rup
+; CHECK-NEXT:  .LBB4_2:
+; CHECK-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_ceil_si64(float %x) nounwind {
 ; RV32IF-LABEL: test_ceil_si64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:  .LBB5_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_ceil_ui32(float %x) {
-; RV32IF-LABEL: test_ceil_ui32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB6_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rup
-; RV32IF-NEXT:  .LBB6_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_ceil_ui32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB6_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rup
-; RV64IF-NEXT:  .LBB6_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: test_ceil_ui32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB6_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.wu.s a0, fa0, rup
+; CHECK-NEXT:  .LBB6_2:
+; CHECK-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_ceil_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_ceil_ui64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:  .LBB7_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_trunc_si32(float %x) {
-; RV32IF-LABEL: test_trunc_si32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB8_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV32IF-NEXT:  .LBB8_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_trunc_si32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB8_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV64IF-NEXT:  .LBB8_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: test_trunc_si32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB8_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.w.s a0, fa0, rtz
+; CHECK-NEXT:  .LBB8_2:
+; CHECK-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_trunc_si64(float %x) nounwind {
 ; RV32IF-LABEL: test_trunc_si64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:  .LBB9_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_trunc_ui32(float %x) {
-; RV32IF-LABEL: test_trunc_ui32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB10_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV32IF-NEXT:  .LBB10_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_trunc_ui32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB10_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; RV64IF-NEXT:  .LBB10_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: test_trunc_ui32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB10_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.wu.s a0, fa0, rtz
+; CHECK-NEXT:  .LBB10_2:
+; CHECK-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_trunc_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_trunc_ui64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:  .LBB11_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_round_si32(float %x) {
-; RV32IF-LABEL: test_round_si32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB12_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rmm
-; RV32IF-NEXT:  .LBB12_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_round_si32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB12_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rmm
-; RV64IF-NEXT:  .LBB12_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: test_round_si32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB12_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.w.s a0, fa0, rmm
+; CHECK-NEXT:  .LBB12_2:
+; CHECK-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_round_si64(float %x) nounwind {
 ; RV32IF-LABEL: test_round_si64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:  .LBB13_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_round_ui32(float %x) {
-; RV32IF-LABEL: test_round_ui32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB14_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rmm
-; RV32IF-NEXT:  .LBB14_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_round_ui32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB14_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rmm
-; RV64IF-NEXT:  .LBB14_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: test_round_ui32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB14_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.wu.s a0, fa0, rmm
+; CHECK-NEXT:  .LBB14_2:
+; CHECK-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_round_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_round_ui64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:  .LBB15_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_roundeven_si32(float %x) {
-; RV32IF-LABEL: test_roundeven_si32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB16_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.w.s a0, fa0, rne
-; RV32IF-NEXT:  .LBB16_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_roundeven_si32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB16_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.w.s a0, fa0, rne
-; RV64IF-NEXT:  .LBB16_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: test_roundeven_si32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB16_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.w.s a0, fa0, rne
+; CHECK-NEXT:  .LBB16_2:
+; CHECK-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_roundeven_si64(float %x) nounwind {
 ; RV32IF-LABEL: test_roundeven_si64:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:  .LBB17_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_roundeven_ui32(float %x) {
-; RV32IF-LABEL: test_roundeven_ui32:
-; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    beqz a0, .LBB18_2
-; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rne
-; RV32IF-NEXT:  .LBB18_2:
-; RV32IF-NEXT:    ret
-;
-; RV64IF-LABEL: test_roundeven_ui32:
-; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    beqz a0, .LBB18_2
-; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rne
-; RV64IF-NEXT:  .LBB18_2:
-; RV64IF-NEXT:    ret
+; CHECK-LABEL: test_roundeven_ui32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    feq.s a0, fa0, fa0
+; CHECK-NEXT:    beqz a0, .LBB18_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    fcvt.wu.s a0, fa0, rne
+; CHECK-NEXT:  .LBB18_2:
+; CHECK-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_roundeven_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_roundeven_ui64:
 ; RV32IF:       # %bb.0:

llvm/test/CodeGen/RISCV/float-select-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
+; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
-; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
+; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECKIF %s
 
 define float @select_fcmp_false(float %a, float %b) nounwind {
 ; RV32IF-LABEL: select_fcmp_false:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.s fa0, fa1
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: select_fcmp_false:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.s fa0, fa1
 ; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_false:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:    ret
   %1 = fcmp false float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_oeq(float %a, float %b) nounwind {
 ; RV32IF-LABEL: select_fcmp_oeq:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    feq.s a0, fa0, fa1
 ; RV32IF-NEXT:    bnez a0, .LBB1_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fmv.s fa0, fa1
 ; RV32IF-NEXT:  .LBB1_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: select_fcmp_oeq:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa1
 ; RV64IF-NEXT:    bnez a0, .LBB1_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fmv.s fa0, fa1
 ; RV64IF-NEXT:  .LBB1_2:
 ; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_oeq:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa0, fa1
+; CHECKIF-NEXT:    bnez a0, .LBB1_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB1_2:
+; CHECKIF-NEXT:    ret
   %1 = fcmp oeq float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ogt(float %a, float %b) nounwind {
 ; RV32IF-LABEL: select_fcmp_ogt:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    flt.s a0, fa1, fa0
 ; RV32IF-NEXT:    bnez a0, .LBB2_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fmv.s fa0, fa1
 ; RV32IF-NEXT:  .LBB2_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: select_fcmp_ogt:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    flt.s a0, fa1, fa0
 ; RV64IF-NEXT:    bnez a0, .LBB2_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fmv.s fa0, fa1
 ; RV64IF-NEXT:  .LBB2_2:
 ; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_ogt:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa1, fa0
+; CHECKIF-NEXT:    bnez a0, .LBB2_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB2_2:
+; CHECKIF-NEXT:    ret
   %1 = fcmp ogt float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_oge(float %a, float %b) nounwind {
 ; RV32IF-LABEL: select_fcmp_oge:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fle.s a0, fa1, fa0
 ; RV32IF-NEXT:    bnez a0, .LBB3_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fmv.s fa0, fa1
 ; RV32IF-NEXT:  .LBB3_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: select_fcmp_oge:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fle.s a0, fa1, fa0
 ; RV64IF-NEXT:    bnez a0, .LBB3_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fmv.s fa0, fa1
 ; RV64IF-NEXT:  .LBB3_2:
 ; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_oge:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fle.s a0, fa1, fa0
+; CHECKIF-NEXT:    bnez a0, .LBB3_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB3_2:
+; CHECKIF-NEXT:    ret
   %1 = fcmp oge float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_olt(float %a, float %b) nounwind {
 ; RV32IF-LABEL: select_fcmp_olt:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    flt.s a0, fa0, fa1
 ; RV32IF-NEXT:    bnez a0, .LBB4_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fmv.s fa0, fa1
 ; RV32IF-NEXT:  .LBB4_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: select_fcmp_olt:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    flt.s a0, fa0, fa1
 ; RV64IF-NEXT:    bnez a0, .LBB4_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fmv.s fa0, fa1
 ; RV64IF-NEXT:  .LBB4_2:
 ; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_olt:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa0, fa1
+; CHECKIF-NEXT:    bnez a0, .LBB4_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB4_2:
+; CHECKIF-NEXT:    ret
   %1 = fcmp olt float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ole(float %a, float %b) nounwind {
 ; RV32IF-LABEL: select_fcmp_ole:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fle.s a0, fa0, fa1
 ; RV32IF-NEXT:    bnez a0, .LBB5_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fmv.s fa0, fa1
 ; RV32IF-NEXT:  .LBB5_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: select_fcmp_ole:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fle.s a0, fa0, fa1
 ; RV64IF-NEXT:    bnez a0, .LBB5_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fmv.s fa0, fa1
 ; RV64IF-NEXT:  .LBB5_2:
 ; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_ole:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fle.s a0, fa0, fa1
+; CHECKIF-NEXT:    bnez a0, .LBB5_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB5_2:
+; CHECKIF-NEXT:    ret
   %1 = fcmp ole float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_one(float %a, float %b) nounwind {
 ; RV32IF-LABEL: select_fcmp_one:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:    flt.s a0, fa0, fa1
 ; RV64IF-NEXT:    flt.s a1, fa1, fa0
 ; RV64IF-NEXT:    or a0, a1, a0
 ; RV64IF-NEXT:    bnez a0, .LBB6_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fmv.s fa0, fa1
 ; RV64IF-NEXT:  .LBB6_2:
 ; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_one:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa0, fa1
+; CHECKIF-NEXT:    flt.s a1, fa1, fa0
+; CHECKIF-NEXT:    or a0, a1, a0
+; CHECKIF-NEXT:    bnez a0, .LBB6_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB6_2:
+; CHECKIF-NEXT:    ret
   %1 = fcmp one float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ord(float %a, float %b) nounwind {
 ; RV32IF-LABEL: select_fcmp_ord:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:    feq.s a0, fa1, fa1
 ; RV64IF-NEXT:    feq.s a1, fa0, fa0
 ; RV64IF-NEXT:    and a0, a1, a0
 ; RV64IF-NEXT:    bnez a0, .LBB7_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fmv.s fa0, fa1
 ; RV64IF-NEXT:  .LBB7_2:
 ; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_ord:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa1, fa1
+; CHECKIF-NEXT:    feq.s a1, fa0, fa0
+; CHECKIF-NEXT:    and a0, a1, a0
+; CHECKIF-NEXT:    bnez a0, .LBB7_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB7_2:
+; CHECKIF-NEXT:    ret
   %1 = fcmp ord float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ueq(float %a, float %b) nounwind {
 ; RV32IF-LABEL: select_fcmp_ueq:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:    flt.s a0, fa0, fa1
 ; RV64IF-NEXT:    flt.s a1, fa1, fa0
 ; RV64IF-NEXT:    or a0, a1, a0
 ; RV64IF-NEXT:    beqz a0, .LBB8_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fmv.s fa0, fa1
 ; RV64IF-NEXT:  .LBB8_2:
 ; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_ueq:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa0, fa1
+; CHECKIF-NEXT:    flt.s a1, fa1, fa0
+; CHECKIF-NEXT:    or a0, a1, a0
+; CHECKIF-NEXT:    beqz a0, .LBB8_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB8_2:
+; CHECKIF-NEXT:    ret
   %1 = fcmp ueq float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ugt(float %a, float %b) nounwind {
 ; RV32IF-LABEL: select_fcmp_ugt:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fle.s a0, fa0, fa1
 ; RV32IF-NEXT:    beqz a0, .LBB9_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fmv.s fa0, fa1
 ; RV32IF-NEXT:  .LBB9_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: select_fcmp_ugt:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fle.s a0, fa0, fa1
 ; RV64IF-NEXT:    beqz a0, .LBB9_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fmv.s fa0, fa1
 ; RV64IF-NEXT:  .LBB9_2:
 ; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_ugt:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fle.s a0, fa0, fa1
+; CHECKIF-NEXT:    beqz a0, .LBB9_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB9_2:
+; CHECKIF-NEXT:    ret
   %1 = fcmp ugt float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_uge(float %a, float %b) nounwind {
 ; RV32IF-LABEL: select_fcmp_uge:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    flt.s a0, fa0, fa1
 ; RV32IF-NEXT:    beqz a0, .LBB10_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fmv.s fa0, fa1
 ; RV32IF-NEXT:  .LBB10_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: select_fcmp_uge:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    flt.s a0, fa0, fa1
 ; RV64IF-NEXT:    beqz a0, .LBB10_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fmv.s fa0, fa1
 ; RV64IF-NEXT:  .LBB10_2:
 ; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_uge:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa0, fa1
+; CHECKIF-NEXT:    beqz a0, .LBB10_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB10_2:
+; CHECKIF-NEXT:    ret
   %1 = fcmp uge float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ult(float %a, float %b) nounwind {
 ; RV32IF-LABEL: select_fcmp_ult:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fle.s a0, fa1, fa0
 ; RV32IF-NEXT:    beqz a0, .LBB11_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fmv.s fa0, fa1
 ; RV32IF-NEXT:  .LBB11_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: select_fcmp_ult:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fle.s a0, fa1, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB11_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fmv.s fa0, fa1
 ; RV64IF-NEXT:  .LBB11_2:
 ; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_ult:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    fle.s a0, fa1, fa0
+; CHECKIF-NEXT:    beqz a0, .LBB11_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB11_2:
+; CHECKIF-NEXT:    ret
   %1 = fcmp ult float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ule(float %a, float %b) nounwind {
 ; RV32IF-LABEL: select_fcmp_ule:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    flt.s a0, fa1, fa0
 ; RV32IF-NEXT:    beqz a0, .LBB12_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fmv.s fa0, fa1
 ; RV32IF-NEXT:  .LBB12_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: select_fcmp_ule:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    flt.s a0, fa1, fa0
 ; RV64IF-NEXT:    beqz a0, .LBB12_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fmv.s fa0, fa1
 ; RV64IF-NEXT:  .LBB12_2:
 ; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_ule:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    flt.s a0, fa1, fa0
+; CHECKIF-NEXT:    beqz a0, .LBB12_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB12_2:
+; CHECKIF-NEXT:    ret
   %1 = fcmp ule float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_une(float %a, float %b) nounwind {
 ; RV32IF-LABEL: select_fcmp_une:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    feq.s a0, fa0, fa1
 ; RV32IF-NEXT:    beqz a0, .LBB13_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fmv.s fa0, fa1
 ; RV32IF-NEXT:  .LBB13_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: select_fcmp_une:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa1
 ; RV64IF-NEXT:    beqz a0, .LBB13_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fmv.s fa0, fa1
 ; RV64IF-NEXT:  .LBB13_2:
 ; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_une:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa0, fa1
+; CHECKIF-NEXT:    beqz a0, .LBB13_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB13_2:
+; CHECKIF-NEXT:    ret
   %1 = fcmp une float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_uno(float %a, float %b) nounwind {
 ; RV32IF-LABEL: select_fcmp_uno:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:    feq.s a0, fa1, fa1
 ; RV64IF-NEXT:    feq.s a1, fa0, fa0
 ; RV64IF-NEXT:    and a0, a1, a0
 ; RV64IF-NEXT:    beqz a0, .LBB14_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fmv.s fa0, fa1
 ; RV64IF-NEXT:  .LBB14_2:
 ; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_uno:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a0, fa1, fa1
+; CHECKIF-NEXT:    feq.s a1, fa0, fa0
+; CHECKIF-NEXT:    and a0, a1, a0
+; CHECKIF-NEXT:    beqz a0, .LBB14_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    fmv.s fa0, fa1
+; CHECKIF-NEXT:  .LBB14_2:
+; CHECKIF-NEXT:    ret
   %1 = fcmp uno float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_true(float %a, float %b) nounwind {
 ; RV32IF-LABEL: select_fcmp_true:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: select_fcmp_true:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: select_fcmp_true:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    ret
   %1 = fcmp true float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 ; Ensure that ISel succeeds for a select+fcmp that has an i32 result type.
 define i32 @i32_select_fcmp_oeq(float %a, float %b, i32 %c, i32 %d) nounwind {
 ; RV32IF-LABEL: i32_select_fcmp_oeq:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    feq.s a2, fa0, fa1
 ; RV32IF-NEXT:    bnez a2, .LBB16_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    mv a0, a1
 ; RV32IF-NEXT:  .LBB16_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: i32_select_fcmp_oeq:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a2, fa0, fa1
 ; RV64IF-NEXT:    bnez a2, .LBB16_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    mv a0, a1
 ; RV64IF-NEXT:  .LBB16_2:
 ; RV64IF-NEXT:    ret
+; CHECKIF-LABEL: i32_select_fcmp_oeq:
+; CHECKIF:       # %bb.0:
+; CHECKIF-NEXT:    feq.s a2, fa0, fa1
+; CHECKIF-NEXT:    bnez a2, .LBB16_2
+; CHECKIF-NEXT:  # %bb.1:
+; CHECKIF-NEXT:    mv a0, a1
+; CHECKIF-NEXT:  .LBB16_2:
+; CHECKIF-NEXT:    ret
   %1 = fcmp oeq float %a, %b
   %2 = select i1 %1, i32 %c, i32 %d
   ret i32 %2
 }