[DAGCombiner] Fold (max/min X, X) -> X.

[craig.topper]

Summary

This also shows we're missing zero_extend/sign_extend undef -> 0 fold in DAGCombiner.

[RKSimon]

Don't we need this in DAGCombine as well to handle cases where the same arg appears after another fold?

[craig.topper]

In D124951#3491982, @RKSimon wrote:

Don't we need this in DAGCombine as well to handle cases where the same arg appears after another fold?

Yes. I could also just move this to DAGCombine only and not affect pr55271.

[craig.topper]

Move to DAGCombine

[craig.topper]

Remove pr55271 test.

[craig.topper]

llvm/test/CodeGen/RISCV/min-max.ll

534

We wouldn't hit the bug if we folded sext/zext undef in DAGCombiner. Instead we type legalize and hit the sext_inreg getNode bug.

[RKSimon]

LGTM

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::visitIMINMAX(SDNode *N) {
   EVT VT = N0.getValueType();
   unsigned Opcode = N->getOpcode();
   SDLoc DL(N);
 
   // fold operation with constant operands.
   if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1}))
     return C;
 
+  // If the operands are the same, this is a no-op.
+  if (N0 == N1)
+    return N0;
+
   // canonicalize constant to RHS
   if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
       !DAG.isConstantIntBuildVectorOrConstantInt(N1))
     return DAG.getNode(Opcode, DL, VT, N1, N0);
 
   // fold vector ops
   if (VT.isVector())
     if (SDValue FoldedVOp = SimplifyVBinOp(N, DL))

llvm/test/CodeGen/RISCV/min-max.ll

 ; RV64ZBB-LABEL: umin_i64:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    minu a0, a0, a1
 ; RV64ZBB-NEXT:    ret
   %c = call i64 @llvm.umin.i64(i64 %a, i64 %b)
   ret i64 %c
 }
 
-; Tests with the same operand used twice.
-; FIXME: These should fold away.
+; Tests with the same operand used twice. These should fold away.
 
 define signext i32 @smin_same_op_i32(i32 signext %a) {
 ; NOZBB-LABEL: smin_same_op_i32:
 ; NOZBB:       # %bb.0:
 ; NOZBB-NEXT:    ret
 ;
 ; ZBB-LABEL: smin_same_op_i32:
 ; ZBB:       # %bb.0:
-; ZBB-NEXT:    min a0, a0, a0
 ; ZBB-NEXT:    ret
   %c = call i32 @llvm.smin.i32(i32 %a, i32 %a)
   ret i32 %c
 }
 
 define signext i32 @smax_same_op_i32(i32 signext %a) {
 ; NOZBB-LABEL: smax_same_op_i32:
 ; NOZBB:       # %bb.0:
 ; NOZBB-NEXT:    ret
 ;
 ; ZBB-LABEL: smax_same_op_i32:
 ; ZBB:       # %bb.0:
-; ZBB-NEXT:    max a0, a0, a0
 ; ZBB-NEXT:    ret
   %c = call i32 @llvm.smax.i32(i32 %a, i32 %a)
   ret i32 %c
 }
 
 define signext i32 @umin_same_op_i32(i32 signext %a) {
 ; NOZBB-LABEL: umin_same_op_i32:
 ; NOZBB:       # %bb.0:
 ; NOZBB-NEXT:    ret
 ;
 ; ZBB-LABEL: umin_same_op_i32:
 ; ZBB:       # %bb.0:
-; ZBB-NEXT:    minu a0, a0, a0
 ; ZBB-NEXT:    ret
   %c = call i32 @llvm.umin.i32(i32 %a, i32 %a)
   ret i32 %c
 }
 
 define signext i32 @umax_same_op_i32(i32 signext %a) {
 ; NOZBB-LABEL: umax_same_op_i32:
 ; NOZBB:       # %bb.0:
 ; NOZBB-NEXT:    ret
 ;
 ; ZBB-LABEL: umax_same_op_i32:
 ; ZBB:       # %bb.0:
-; ZBB-NEXT:    maxu a0, a0, a0
 ; ZBB-NEXT:    ret
   %c = call i32 @llvm.umax.i32(i32 %a, i32 %a)
   ret i32 %c
 }
 
-; Tests with undef operands.
-; FIXME: These should fold to undef for RV32 or 0 for RV64.
-; FIXME: The RV64ZBB cases are hitting pr55178.
+; Tests with undef operands. These should fold to undef for RV32 or 0 for RV64.
+; FIXME: The RV64 cases are hitting pr55178.
 
 define signext i32 @smin_undef_i32() {
-; RV32I-LABEL: smin_undef_i32:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: smin_undef_i32:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a0, 0
-; RV64I-NEXT:    ret
-;
-; RV32ZBB-LABEL: smin_undef_i32:
-; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    min a0, a0, a0
-; RV32ZBB-NEXT:    ret
+; NOZBB-LABEL: smin_undef_i32:
+; NOZBB:       # %bb.0:
+; NOZBB-NEXT:    ret
 ;
-; RV64ZBB-LABEL: smin_undef_i32:
-; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    min a0, a0, a0
-; RV64ZBB-NEXT:    sext.w a0, a0
-; RV64ZBB-NEXT:    ret
+; ZBB-LABEL: smin_undef_i32:
+; ZBB:       # %bb.0:
+; ZBB-NEXT:    ret
   %c = call i32 @llvm.smin.i32(i32 undef, i32 undef)
   ret i32 %c
 }
 
 define signext i32 @smax_undef_i32() {
-; RV32I-LABEL: smax_undef_i32:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: smax_undef_i32:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a0, 0
-; RV64I-NEXT:    ret
-;
-; RV32ZBB-LABEL: smax_undef_i32:
-; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    max a0, a0, a0
-; RV32ZBB-NEXT:    ret
+; NOZBB-LABEL: smax_undef_i32:
+; NOZBB:       # %bb.0:
+; NOZBB-NEXT:    ret
 ;
-; RV64ZBB-LABEL: smax_undef_i32:
-; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    max a0, a0, a0
-; RV64ZBB-NEXT:    sext.w a0, a0
-; RV64ZBB-NEXT:    ret
+; ZBB-LABEL: smax_undef_i32:
+; ZBB:       # %bb.0:
+; ZBB-NEXT:    ret
   %c = call i32 @llvm.smax.i32(i32 undef, i32 undef)
   ret i32 %c
 }
 
 define signext i32 @umin_undef_i32() {
-; RV32I-LABEL: umin_undef_i32:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: umin_undef_i32:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a0, 0
-; RV64I-NEXT:    ret
-;
-; RV32ZBB-LABEL: umin_undef_i32:
-; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    minu a0, a0, a0
-; RV32ZBB-NEXT:    ret
+; NOZBB-LABEL: umin_undef_i32:
+; NOZBB:       # %bb.0:
+; NOZBB-NEXT:    ret
 ;
-; RV64ZBB-LABEL: umin_undef_i32:
-; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    minu a0, a0, a0
-; RV64ZBB-NEXT:    sext.w a0, a0
-; RV64ZBB-NEXT:    ret
+; ZBB-LABEL: umin_undef_i32:
+; ZBB:       # %bb.0:
+; ZBB-NEXT:    ret
   %c = call i32 @llvm.umin.i32(i32 undef, i32 undef)
   ret i32 %c
 }
 
 define signext i32 @umax_undef_i32() {
-; RV32I-LABEL: umax_undef_i32:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: umax_undef_i32:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a0, 0
-; RV64I-NEXT:    ret
-;
-; RV32ZBB-LABEL: umax_undef_i32:
-; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    maxu a0, a0, a0
-; RV32ZBB-NEXT:    ret
+; NOZBB-LABEL: umax_undef_i32:
+; NOZBB:       # %bb.0:
+; NOZBB-NEXT:    ret
 ;
-; RV64ZBB-LABEL: umax_undef_i32:
-; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    maxu a0, a0, a0
-; RV64ZBB-NEXT:    sext.w a0, a0
-; RV64ZBB-NEXT:    ret
+; ZBB-LABEL: umax_undef_i32:
+; ZBB:       # %bb.0:
+; ZBB-NEXT:    ret
   %c = call i32 @llvm.umax.i32(i32 undef, i32 undef)
   ret i32 %c
 }