llvm-reduce: Add cloning of target MachineFunctionInfo

[arsenm]

Summary

MIR support is totally unusable for AMDGPU without this, since the set
of reserved registers is set from fields here.

Add a clone method to MachineFunctionInfo. This is a subtle variant of
the copy constructor that is required if there are any MIR constructs
that use pointers. Specifically, at minimum fields that reference
MachineBasicBlocks or the MachineFunction need to be adjusted to the
values in the new function.

[markus]

Having to touch all these target specific files seems a bit unfortunate but maybe that is the way it has to be.

[MatzeB]

I wonder if we wouldn't be better off by just adding an implementation into the baseclass that does return nullptr; and then abort the llvm-reduce process? That way implementing a proper clone() function becomes a problem for the individual target maintainers when they want to use llvm-reduce and we should get more complete/correct implementations.

That said I don't care too deeply either way. So LGTM leaving the return nullptr change to your discretion.

[arsenm]

In D123953#3476385, @MatzeB wrote:

I wonder if we wouldn't be better off by just adding an implementation into the baseclass that does return nullptr; and then abort the llvm-reduce process? That way implementing a proper clone() function becomes a problem for the individual target maintainers when they want to use llvm-reduce and we should get more complete/correct implementations.

That is what this does, it just turned out to be not very difficult to implement for every target once frame index values are stable

[arsenm]

cc5a1b3dd9039d50f6b9caa679d60398f0cec65f

llvm/include/llvm/CodeGen/MachineFunction.h

struct MachineFunctionInfo {
   /// Factory function: default behavior is to call new using the
   /// supplied allocator.
   ///
   /// This function can be overridden in a derive class.
   template<typename Ty>
   static Ty *create(BumpPtrAllocator &Allocator, MachineFunction &MF) {
     return new (Allocator.Allocate<Ty>()) Ty(MF);
   }
+
+  template <typename Ty>
+  static Ty *create(BumpPtrAllocator &Allocator, const Ty &MFI) {
+    return new (Allocator.Allocate<Ty>()) Ty(MFI);
+  }
+
+  /// Make a functionally equivalent copy of this MachineFunctionInfo in \p MF.
+  /// This requires remapping MachineBasicBlock references from the original
+  /// parent to values in the new function. Targets may assume that virtual
+  /// register and frame index values are preserved in the new function.
+  virtual MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const {
+    return nullptr;
+  }
 };
 
 /// Properties which a MachineFunction may have at a given point in time.
 /// Each of these has checking code in the MachineVerifier, and passes can
 /// require that a property be set.
 class MachineFunctionProperties {
   // Possible TODO: Allow targets to extend this (perhaps by allowing the
   // constructor to specify the size of the bit vector)
Ty *getInfo() {
     return static_cast<Ty*>(MFInfo);
   }
 
   template<typename Ty>
   const Ty *getInfo() const {
      return const_cast<MachineFunction*>(this)->getInfo<Ty>();
   }
 
+  template <typename Ty> Ty *cloneInfo(const Ty &Old) {
+    assert(!MFInfo);
+    MFInfo = Ty::template create<Ty>(Allocator, Old);
+    return static_cast<Ty *>(MFInfo);
+  }
+
+  MachineFunctionInfo *cloneInfoFrom(
+      const MachineFunction &OrigMF,
+      const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB) {
+    assert(!MFInfo && "new function already has MachineFunctionInfo");
+    if (!OrigMF.MFInfo)
+      return nullptr;
+    return OrigMF.MFInfo->clone(Allocator, *this, Src2DstMBB);
+  }
+
   /// Returns the denormal handling type for the default rounding mode of the
   /// function.
   DenormalMode getDenormalMode(const fltSemantics &FPType) const;
 
   /// getBlockNumbered - MachineBasicBlocks are automatically numbered when they
   /// are inserted into the machine function.  The block number for a machine
   /// basic block can be found by using the MBB::getNumber method, this method
   /// provides the inverse mapping.

llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h

 } // end namespace yaml
 
 class MachineInstr;
 
 /// AArch64FunctionInfo - This class is derived from MachineFunctionInfo and
 /// contains private AArch64-specific information for each MachineFunction.
 class AArch64FunctionInfo final : public MachineFunctionInfo {
   /// Backreference to the machine function.
-  MachineFunction &MF;
+  MachineFunction *MF;
 
   /// Number of bytes of arguments this function has on the stack. If the callee
   /// is expected to restore the argument stack this should be a multiple of 16,
   /// all usable during a tail call.
   ///
   /// The alternative would forbid tail call optimisation in some cases: if we
   /// want to transfer control from a function with 8-bytes of stack-argument
   /// space to a function with 16-bytes then misalignment of this value would
class AArch64FunctionInfo final : public MachineFunctionInfo {
   mutable Optional<bool> NeedsDwarfUnwindInfo;
 
   /// True if the function need asynchronous unwind information.
   mutable Optional<bool> NeedsAsyncDwarfUnwindInfo;
 
 public:
   explicit AArch64FunctionInfo(MachineFunction &MF);
 
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
+
   void initializeBaseYamlFields(const yaml::AArch64FunctionInfo &YamlMFI);
 
   unsigned getBytesInStackArgArea() const { return BytesInStackArgArea; }
   void setBytesInStackArgArea(unsigned bytes) { BytesInStackArgArea = bytes; }
 
   unsigned getArgumentStackToRestore() const { return ArgumentStackToRestore; }
   void setArgumentStackToRestore(unsigned bytes) {
     ArgumentStackToRestore = bytes;

llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp

static bool ShouldSignWithBKey(const Function &F) {
   }
 
   const StringRef Key =
       F.getFnAttribute("sign-return-address-key").getValueAsString();
   assert(Key.equals_insensitive("a_key") || Key.equals_insensitive("b_key"));
   return Key.equals_insensitive("b_key");
 }
 
-AArch64FunctionInfo::AArch64FunctionInfo(MachineFunction &MF) : MF(MF) {
+AArch64FunctionInfo::AArch64FunctionInfo(MachineFunction &MF_) : MF(&MF_) {
   // If we already know that the function doesn't have a redzone, set
   // HasRedZone here.
-  if (MF.getFunction().hasFnAttribute(Attribute::NoRedZone))
+  if (MF->getFunction().hasFnAttribute(Attribute::NoRedZone))
     HasRedZone = false;
 
-  const Function &F = MF.getFunction();
+  const Function &F = MF->getFunction();
   std::tie(SignReturnAddress, SignReturnAddressAll) = GetSignReturnAddress(F);
   SignWithBKey = ShouldSignWithBKey(F);
 
   if (!F.hasFnAttribute("branch-target-enforcement")) {
     if (const auto *BTE = mdconst::extract_or_null<ConstantInt>(
             F.getParent()->getModuleFlag("branch-target-enforcement")))
       BranchTargetEnforcement = BTE->getZExtValue();
     return;
   }
 
   const StringRef BTIEnable =
       F.getFnAttribute("branch-target-enforcement").getValueAsString();
   assert(BTIEnable.equals_insensitive("true") ||
          BTIEnable.equals_insensitive("false"));
   BranchTargetEnforcement = BTIEnable.equals_insensitive("true");
 }
 
+MachineFunctionInfo *AArch64FunctionInfo::clone(
+    BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+    const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+    const {
+  AArch64FunctionInfo *InfoClone = DestMF.cloneInfo<AArch64FunctionInfo>(*this);
+  InfoClone->MF = &DestMF;
+  return InfoClone;
+}
+
 bool AArch64FunctionInfo::shouldSignReturnAddress(bool SpillsLR) const {
   if (!SignReturnAddress)
     return false;
   if (SignReturnAddressAll)
     return true;
   return SpillsLR;
 }
 
 bool AArch64FunctionInfo::shouldSignReturnAddress() const {
   return shouldSignReturnAddress(llvm::any_of(
-      MF.getFrameInfo().getCalleeSavedInfo(),
+      MF->getFrameInfo().getCalleeSavedInfo(),
       [](const auto &Info) { return Info.getReg() == AArch64::LR; }));
 }
 
 bool AArch64FunctionInfo::needsDwarfUnwindInfo() const {
   if (!NeedsDwarfUnwindInfo)
-    NeedsDwarfUnwindInfo = MF.needsFrameMoves() &&
-                           !MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
+    NeedsDwarfUnwindInfo = MF->needsFrameMoves() &&
+                           !MF->getTarget().getMCAsmInfo()->usesWindowsCFI();
 
   return *NeedsDwarfUnwindInfo;
 }
 
 bool AArch64FunctionInfo::needsAsyncDwarfUnwindInfo() const {
   if (!NeedsAsyncDwarfUnwindInfo) {
-    const Function &F = MF.getFunction();
+    const Function &F = MF->getFunction();
     //  The check got "minsize" is because epilogue unwind info is not emitted
     //  (yet) for homogeneous epilogues, outlined functions, and functions
     //  outlined from.
     NeedsAsyncDwarfUnwindInfo = needsDwarfUnwindInfo() &&
                                 F.getUWTableKind() == UWTableKind::Async &&
                                 !F.hasMinSize();
   }
   return *NeedsAsyncDwarfUnwindInfo;
 }

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h

public: // FIXME
   /// base pointer.
   Register SGPRForBPSaveRestoreCopy;
   Optional<int> BasePointerSaveIndex;
 
   bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg);
 
 public:
   SIMachineFunctionInfo(const MachineFunction &MF);
+  SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI) = default;
+
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
 
   bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI,
                                 const MachineFunction &MF,
                                 PerFunctionMIParsingState &PFS,
                                 SMDiagnostic &Error, SMRange &SourceRange);
 
   void reserveWWMRegister(Register Reg) {
     WWMReservedRegs.insert(Reg);

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
 
   // On GFX908, in order to guarantee copying between AGPRs, we need a scratch
   // VGPR available at all times.
   if (ST.hasMAIInsts() && !ST.hasGFX90AInsts()) {
     VGPRForAGPRCopy = AMDGPU::VGPR_32RegClass.getRegister(32);
   }
 }
 
+MachineFunctionInfo *SIMachineFunctionInfo::clone(
+    BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+    const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+    const {
+  return DestMF.cloneInfo<SIMachineFunctionInfo>(*this);
+}
+
 void SIMachineFunctionInfo::limitOccupancy(const MachineFunction &MF) {
   limitOccupancy(getMaxWavesPerEU());
   const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
   limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
                  MF.getFunction()));
 }
 
 Register SIMachineFunctionInfo::addPrivateSegmentBuffer(

llvm/lib/Target/ARC/ARCMachineFunctionInfo.h

 public:
   ARCFunctionInfo()
       : ReturnStackOffsetSet(false), VarArgsFrameIndex(0),
         ReturnStackOffset(-1U), MaxCallStackReq(0) {}
 
   explicit ARCFunctionInfo(MachineFunction &MF)
       : ReturnStackOffsetSet(false), VarArgsFrameIndex(0),
         ReturnStackOffset(-1U), MaxCallStackReq(0) {}
-
   ~ARCFunctionInfo() {}
 
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
+
   void setVarArgsFrameIndex(int off) { VarArgsFrameIndex = off; }
   int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
 
   void setReturnStackOffset(unsigned value) {
     assert(!ReturnStackOffsetSet && "Return stack offset set twice");
     ReturnStackOffset = value;
     ReturnStackOffsetSet = true;
   }

llvm/lib/Target/ARC/ARCMachineFunctionInfo.cpp

 //===- ARCMachineFunctionInfo.cpp - ARC machine func info -------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "ARCMachineFunctionInfo.h"
 
 using namespace llvm;
 
 void ARCFunctionInfo::anchor() {}
+
+MachineFunctionInfo *
+ARCFunctionInfo::clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+                       const DenseMap<MachineBasicBlock *, MachineBasicBlock *>
+                           &Src2DstMBB) const {
+  return DestMF.cloneInfo<ARCFunctionInfo>(*this);
+}

llvm/lib/Target/ARM/ARMMachineFunctionInfo.h

class ARMFunctionInfo : public MachineFunctionInfo {
   /// destinations.
   bool BranchTargetEnforcement = false;
 
 public:
   ARMFunctionInfo() = default;
 
   explicit ARMFunctionInfo(MachineFunction &MF);
 
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
+
   bool isThumbFunction() const { return isThumb; }
   bool isThumb1OnlyFunction() const { return isThumb && !hasThumb2; }
   bool isThumb2Function() const { return isThumb && hasThumb2; }
 
   bool isCmseNSEntryFunction() const { return IsCmseNSEntry; }
   bool isCmseNSCallFunction() const { return IsCmseNSCall; }
 
   unsigned getStoredByValParamsPadding() const { return StByValParamsPadding; }

llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp

: isThumb(MF.getSubtarget<ARMSubtarget>().isThumb()),
       IsCmseNSCall(MF.getFunction().hasFnAttribute("cmse_nonsecure_call")),
       BranchTargetEnforcement(GetBranchTargetEnforcement(MF)) {
 
   const auto &Subtarget = MF.getSubtarget<ARMSubtarget>();
   if (Subtarget.isMClass() && Subtarget.hasV7Ops())
     std::tie(SignReturnAddress, SignReturnAddressAll) =
         GetSignReturnAddress(MF.getFunction());
 }
+
+MachineFunctionInfo *
+ARMFunctionInfo::clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+                       const DenseMap<MachineBasicBlock *, MachineBasicBlock *>
+                           &Src2DstMBB) const {
+  return DestMF.cloneInfo<ARMFunctionInfo>(*this);
+}

llvm/lib/Target/AVR/AVRMachineFunctionInfo.h

explicit AVRMachineFunctionInfo(MachineFunction &MF)
     unsigned CallConv = MF.getFunction().getCallingConv();
 
     this->IsInterruptHandler = CallConv == CallingConv::AVR_INTR ||
                                MF.getFunction().hasFnAttribute("interrupt");
     this->IsSignalHandler = CallConv == CallingConv::AVR_SIGNAL ||
                             MF.getFunction().hasFnAttribute("signal");
   }
 
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override {
+    return DestMF.cloneInfo<AVRMachineFunctionInfo>(*this);
+  }
+
   bool getHasSpills() const { return HasSpills; }
   void setHasSpills(bool B) { HasSpills = B; }
 
   bool getHasAllocas() const { return HasAllocas; }
   void setHasAllocas(bool B) { HasAllocas = B; }
 
   bool getHasStackArgs() const { return HasStackArgs; }
   void setHasStackArgs(bool B) { HasStackArgs = B; }

llvm/lib/Target/CSKY/CSKYMachineFunctionInfo.h

class CSKYMachineFunctionInfo : public MachineFunctionInfo {
 
   bool LRSpilled = false;
 
   unsigned PICLabelUId = 0;
 
 public:
   CSKYMachineFunctionInfo(MachineFunction &) {}
 
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override {
+    return DestMF.cloneInfo<CSKYMachineFunctionInfo>(*this);
+  }
+
   Register getGlobalBaseReg() const { return GlobalBaseReg; }
   void setGlobalBaseReg(Register Reg) { GlobalBaseReg = Reg; }
 
   void setSpillsCR() { SpillsCR = true; }
   bool isCRSpilled() const { return SpillsCR; }
 
   void setVarArgsFrameIndex(int v) { VarArgsFrameIndex = v; }
   int getVarArgsFrameIndex() { return VarArgsFrameIndex; }

llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h

class HexagonMachineFunctionInfo : public MachineFunctionInfo {
   bool HasEHReturn = false;
   std::map<const MachineInstr*, unsigned> PacketInfo;
   virtual void anchor();
 
 public:
   HexagonMachineFunctionInfo() = default;
 
   HexagonMachineFunctionInfo(MachineFunction &MF) {}
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
 
   unsigned getSRetReturnReg() const { return SRetReturnReg; }
   void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
 
   void setVarArgsFrameIndex(int v) { VarArgsFrameIndex = v; }
   int getVarArgsFrameIndex() { return VarArgsFrameIndex; }
 
   void setRegSavedAreaStartFrameIndex(int v) { RegSavedAreaStartFrameIndex = v;}

llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp

 //= HexagonMachineFunctionInfo.cpp - Hexagon machine function info *- C++ -*-=//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "HexagonMachineFunctionInfo.h"
 
 using namespace llvm;
 
 // pin vtable to this file
 void HexagonMachineFunctionInfo::anchor() {}
 
+MachineFunctionInfo *HexagonMachineFunctionInfo::clone(
+    BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+    const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+    const {
+  return DestMF.cloneInfo<HexagonMachineFunctionInfo>(*this);
+}

llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.h

class LanaiMachineFunctionInfo : public MachineFunctionInfo {
   Register GlobalBaseReg;
 
   // VarArgsFrameIndex - FrameIndex for start of varargs area.
   int VarArgsFrameIndex;
 
 public:
   explicit LanaiMachineFunctionInfo(MachineFunction &MF)
       : VarArgsFrameIndex(0) {}
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
 
   Register getSRetReturnReg() const { return SRetReturnReg; }
   void setSRetReturnReg(Register Reg) { SRetReturnReg = Reg; }
 
   int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
   void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
 };
 
 } // namespace llvm
 
 #endif // LLVM_LIB_TARGET_LANAI_LANAIMACHINEFUNCTIONINFO_H

llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.cpp

 //===-- LanaiMachineFuctionInfo.cpp - Lanai machine function info ---===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "LanaiMachineFunctionInfo.h"
 
 using namespace llvm;
 
 void LanaiMachineFunctionInfo::anchor() {}
+
+MachineFunctionInfo *LanaiMachineFunctionInfo::clone(
+    BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+    const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+    const {
+  return DestMF.cloneInfo<LanaiMachineFunctionInfo>(*this);
+}

llvm/lib/Target/LoongArch/LoongArchMachineFunctionInfo.h

private:
   int VarArgsSaveSize = 0;
 
   /// Size of stack frame to save callee saved registers
   unsigned CalleeSavedStackSize = 0;
 
 public:
   LoongArchMachineFunctionInfo(const MachineFunction &MF) {}
 
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override {
+    return DestMF.cloneInfo<LoongArchMachineFunctionInfo>(*this);
+  }
+
   int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
   void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
 
   unsigned getVarArgsSaveSize() const { return VarArgsSaveSize; }
   void setVarArgsSaveSize(int Size) { VarArgsSaveSize = Size; }
 
   unsigned getCalleeSavedStackSize() const { return CalleeSavedStackSize; }
   void setCalleeSavedStackSize(unsigned Size) { CalleeSavedStackSize = Size; }
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHMACHINEFUNCTIONINFO_H

llvm/lib/Target/M68k/M68kMachineFunction.h

 
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/Support/MachineValueType.h"
 
 namespace llvm {
 
 class M68kMachineFunctionInfo : public MachineFunctionInfo {
-  MachineFunction &MF;
-
   /// Non-zero if the function has base pointer and makes call to
   /// llvm.eh.sjlj.setjmp. When non-zero, the value is a displacement from the
   /// frame pointer to a slot where the base pointer is stashed.
   signed char RestoreBasePointerOffset = 0;
 
   /// Size of the callee-saved register portion of the stack frame in bytes.
   unsigned CalleeSavedFrameSize = 0;
 
class M68kMachineFunctionInfo : public MachineFunctionInfo {
   /// musttail call.
   SmallVector<ForwardedRegister, 1> ForwardedMustTailRegParms;
 
   /// The number of bytes on stack consumed by the arguments being passed on
   /// the stack.
   unsigned ArgumentStackSize = 0;
 
 public:
-  explicit M68kMachineFunctionInfo(MachineFunction &MF) : MF(MF) {}
+  explicit M68kMachineFunctionInfo() = default;
+
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
 
   bool getRestoreBasePointer() const { return RestoreBasePointerOffset != 0; }
   void setRestoreBasePointer(const MachineFunction *MF);
   int getRestoreBasePointerOffset() const { return RestoreBasePointerOffset; }
 
   unsigned getCalleeSavedFrameSize() const { return CalleeSavedFrameSize; }
   void setCalleeSavedFrameSize(unsigned bytes) { CalleeSavedFrameSize = bytes; }
 

llvm/lib/Target/M68k/M68kMachineFunction.cpp

 
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/IR/Function.h"
 
 using namespace llvm;
 
 void M68kMachineFunctionInfo::anchor() {}
+
+MachineFunctionInfo *M68kMachineFunctionInfo::clone(
+    BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+    const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+    const {
+  return DestMF.cloneInfo<M68kMachineFunctionInfo>(*this);
+}

llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h

class MSP430MachineFunctionInfo : public MachineFunctionInfo {
   Register SRetReturnReg;
 
 public:
   MSP430MachineFunctionInfo() = default;
 
   explicit MSP430MachineFunctionInfo(MachineFunction &MF)
     : CalleeSavedFrameSize(0), ReturnAddrIndex(0), SRetReturnReg(0) {}
 
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
+
   unsigned getCalleeSavedFrameSize() const { return CalleeSavedFrameSize; }
   void setCalleeSavedFrameSize(unsigned bytes) { CalleeSavedFrameSize = bytes; }
 
   Register getSRetReturnReg() const { return SRetReturnReg; }
   void setSRetReturnReg(Register Reg) { SRetReturnReg = Reg; }
 
   int getRAIndex() const { return ReturnAddrIndex; }
   void setRAIndex(int Index) { ReturnAddrIndex = Index; }
 
   int getVarArgsFrameIndex() const { return VarArgsFrameIndex;}
   void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
 };
 
 } // End llvm namespace
 
 #endif

llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.cpp

 //===-- MSP430MachineFunctionInfo.cpp - MSP430 machine function info ------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "MSP430MachineFunctionInfo.h"
 
 using namespace llvm;
 
 void MSP430MachineFunctionInfo::anchor() { }
+
+MachineFunctionInfo *MSP430MachineFunctionInfo::clone(
+    BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+    const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+    const {
+  return DestMF.cloneInfo<MSP430MachineFunctionInfo>(*this);
+}

llvm/lib/Target/Mips/MipsMachineFunction.h

 namespace llvm {
 
 /// MipsFunctionInfo - This class is derived from MachineFunction private
 /// Mips target-specific information for each MachineFunction.
 class MipsFunctionInfo : public MachineFunctionInfo {
 public:
   MipsFunctionInfo(MachineFunction &MF) {}
 
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
+
   ~MipsFunctionInfo() override;
 
   unsigned getSRetReturnReg() const { return SRetReturnReg; }
   void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
 
   bool globalBaseRegSet() const;
   Register getGlobalBaseReg(MachineFunction &MF);
   Register getGlobalBaseRegForGlobalISel(MachineFunction &MF);

llvm/lib/Target/Mips/MipsMachineFunction.cpp

 #include "llvm/Support/CommandLine.h"
 
 using namespace llvm;
 
 static cl::opt<bool>
 FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
                  cl::desc("Always use $gp as the global base register."));
 
+MachineFunctionInfo *
+MipsFunctionInfo::clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+                        const DenseMap<MachineBasicBlock *, MachineBasicBlock *>
+                            &Src2DstMBB) const {
+  return DestMF.cloneInfo<MipsFunctionInfo>(*this);
+}
+
 MipsFunctionInfo::~MipsFunctionInfo() = default;
 
 bool MipsFunctionInfo::globalBaseRegSet() const {
   return GlobalBaseReg;
 }
 
 static const TargetRegisterClass &getGlobalBaseRegClass(MachineFunction &MF) {
   auto &STI = static_cast<const MipsSubtarget &>(MF.getSubtarget());

llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h

 private:
   /// Stores a mapping from index to symbol name for removing image handles
   /// on Fermi.
   SmallVector<std::string, 8> ImageHandleList;
 
 public:
   NVPTXMachineFunctionInfo(MachineFunction &MF) {}
 
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override {
+    return DestMF.cloneInfo<NVPTXMachineFunctionInfo>(*this);
+  }
+
   /// Returns the index for the symbol \p Symbol. If the symbol was previously,
   /// added, the same index is returned. Otherwise, the symbol is added and the
   /// new index is returned.
   unsigned getImageHandleSymbolIndex(const char *Symbol) {
     // Is the symbol already present?
     for (unsigned i = 0, e = ImageHandleList.size(); i != e; ++i)
       if (ImageHandleList[i] == std::string(Symbol))
         return i;

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h

private:
 
   /// We keep track attributes for each live-in virtual registers
   /// to use SExt/ZExt flags in later optimization.
   std::vector<std::pair<Register, ISD::ArgFlagsTy>> LiveInAttrs;
 
 public:
   explicit PPCFunctionInfo(const MachineFunction &MF);
 
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
+
   int getFramePointerSaveIndex() const { return FramePointerSaveIndex; }
   void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = Idx; }
 
   int getReturnAddrSaveIndex() const { return ReturnAddrSaveIndex; }
   void setReturnAddrSaveIndex(int idx) { ReturnAddrSaveIndex = idx; }
 
   int getBasePointerSaveIndex() const { return BasePointerSaveIndex; }
   void setBasePointerSaveIndex(int Idx) { BasePointerSaveIndex = Idx; }

llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

static cl::opt<bool> PPCDisableNonVolatileCR(
     "ppc-disable-non-volatile-cr",
     cl::desc("Disable the use of non-volatile CR register fields"),
     cl::init(false), cl::Hidden);
 
 void PPCFunctionInfo::anchor() {}
 PPCFunctionInfo::PPCFunctionInfo(const MachineFunction &MF)
     : DisableNonVolatileCR(PPCDisableNonVolatileCR) {}
 
+MachineFunctionInfo *
+PPCFunctionInfo::clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+                       const DenseMap<MachineBasicBlock *, MachineBasicBlock *>
+                           &Src2DstMBB) const {
+  return DestMF.cloneInfo<PPCFunctionInfo>(*this);
+}
+
 MCSymbol *PPCFunctionInfo::getPICOffsetSymbol(MachineFunction &MF) const {
   const DataLayout &DL = MF.getDataLayout();
   return MF.getContext().getOrCreateSymbol(Twine(DL.getPrivateGlobalPrefix()) +
                                            Twine(MF.getFunctionNumber()) +
                                            "$poff");
 }
 
 MCSymbol *PPCFunctionInfo::getGlobalEPSymbol(MachineFunction &MF) const {

llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h

private:
   /// Padding required to keep RVV stack aligned within the main stack.
   uint64_t RVVPadding = 0;
   /// Size of stack frame to save callee saved registers
   unsigned CalleeSavedStackSize = 0;
 
 public:
   RISCVMachineFunctionInfo(const MachineFunction &MF) {}
 
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
+
   int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
   void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
 
   unsigned getVarArgsSaveSize() const { return VarArgsSaveSize; }
   void setVarArgsSaveSize(int Size) { VarArgsSaveSize = Size; }
 
   int getMoveF64FrameIndex(MachineFunction &MF) {
     if (MoveF64FrameIndex == -1)

llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp

 
 using namespace llvm;
 
 yaml::RISCVMachineFunctionInfo::RISCVMachineFunctionInfo(
     const llvm::RISCVMachineFunctionInfo &MFI)
     : VarArgsFrameIndex(MFI.getVarArgsFrameIndex()),
       VarArgsSaveSize(MFI.getVarArgsSaveSize()) {}
 
+MachineFunctionInfo *RISCVMachineFunctionInfo::clone(
+    BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+    const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+    const {
+  return DestMF.cloneInfo<RISCVMachineFunctionInfo>(*this);
+}
+
 void yaml::RISCVMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
   MappingTraits<RISCVMachineFunctionInfo>::mapping(YamlIO, *this);
 }
 
 void RISCVMachineFunctionInfo::initializeBaseYamlFields(
     const yaml::RISCVMachineFunctionInfo &YamlMFI) {
   VarArgsFrameIndex = YamlMFI.VarArgsFrameIndex;
   VarArgsSaveSize = YamlMFI.VarArgsSaveSize;
 }

llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h

namespace llvm {
   public:
     SparcMachineFunctionInfo()
       : GlobalBaseReg(0), VarArgsFrameOffset(0), SRetReturnReg(0),
         IsLeafProc(false) {}
     explicit SparcMachineFunctionInfo(MachineFunction &MF)
       : GlobalBaseReg(0), VarArgsFrameOffset(0), SRetReturnReg(0),
         IsLeafProc(false) {}
 
+    MachineFunctionInfo *
+    clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+          const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+        const override;
+
     Register getGlobalBaseReg() const { return GlobalBaseReg; }
     void setGlobalBaseReg(Register Reg) { GlobalBaseReg = Reg; }
 
     int getVarArgsFrameOffset() const { return VarArgsFrameOffset; }
     void setVarArgsFrameOffset(int Offset) { VarArgsFrameOffset = Offset; }
 
     Register getSRetReturnReg() const { return SRetReturnReg; }
     void setSRetReturnReg(Register Reg) { SRetReturnReg = Reg; }
 
     void setLeafProc(bool rhs) { IsLeafProc = rhs; }
     bool isLeafProc() const { return IsLeafProc; }
   };
 }
 
 #endif

llvm/lib/Target/Sparc/SparcMachineFunctionInfo.cpp

 //===-- SparcMachineFunctionInfo.cpp - Sparc Machine Function Info --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "SparcMachineFunctionInfo.h"
 
 using namespace llvm;
 
 void SparcMachineFunctionInfo::anchor() { }
+
+MachineFunctionInfo *SparcMachineFunctionInfo::clone(
+    BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+    const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+    const {
+  return DestMF.cloneInfo<SparcMachineFunctionInfo>(*this);
+}

llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h

class SystemZMachineFunctionInfo : public MachineFunctionInfo {
   int FramePointerSaveIndex;
   unsigned NumLocalDynamics;
 
 public:
   explicit SystemZMachineFunctionInfo(MachineFunction &MF)
     : VarArgsFirstGPR(0), VarArgsFirstFPR(0), VarArgsFrameIndex(0),
       RegSaveFrameIndex(0), FramePointerSaveIndex(0), NumLocalDynamics(0) {}
 
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
+
   // Get and set the first and last call-saved GPR that should be saved by
   // this function and the SP offset for the STMG.  These are 0 if no GPRs
   // need to be saved or restored.
   SystemZ::GPRRegs getSpillGPRRegs() const { return SpillGPRRegs; }
   void setSpillGPRRegs(Register Low, Register High, unsigned Offs) {
     SpillGPRRegs.LowGPR = Low;
     SpillGPRRegs.HighGPR = High;
     SpillGPRRegs.GPROffset = Offs;

llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.cpp

 //=== SystemZMachineFunctionInfo.cpp - SystemZ machine function info ------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "SystemZMachineFunctionInfo.h"
 
 using namespace llvm;
 
 
 // pin vtable to this file
 void SystemZMachineFunctionInfo::anchor() {}
 
+MachineFunctionInfo *SystemZMachineFunctionInfo::clone(
+    BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+    const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+    const {
+  return DestMF.cloneInfo<SystemZMachineFunctionInfo>(*this);
+}

llvm/lib/Target/VE/VEMachineFunctionInfo.h

private:
   /// IsLeafProc - True if the function is a leaf procedure.
   bool IsLeafProc;
 
 public:
   VEMachineFunctionInfo() : VarArgsFrameOffset(0), IsLeafProc(false) {}
   explicit VEMachineFunctionInfo(MachineFunction &MF)
       : VarArgsFrameOffset(0), IsLeafProc(false) {}
 
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
+
   Register getGlobalBaseReg() const { return GlobalBaseReg; }
   void setGlobalBaseReg(Register Reg) { GlobalBaseReg = Reg; }
 
   int getVarArgsFrameOffset() const { return VarArgsFrameOffset; }
   void setVarArgsFrameOffset(int Offset) { VarArgsFrameOffset = Offset; }
 
   void setLeafProc(bool rhs) { IsLeafProc = rhs; }
   bool isLeafProc() const { return IsLeafProc; }
 };
 } // namespace llvm
 
 #endif

llvm/lib/Target/VE/VEMachineFunctionInfo.cpp

 //===-- VEMachineFunctionInfo.cpp - VE Machine Function Info --------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "VEMachineFunctionInfo.h"
 
 using namespace llvm;
 
 void VEMachineFunctionInfo::anchor() {}
+
+MachineFunctionInfo *VEMachineFunctionInfo::clone(
+    BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+    const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+    const {
+  return DestMF.cloneInfo<VEMachineFunctionInfo>(*this);
+}

llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h

 
 namespace yaml {
 struct WebAssemblyFunctionInfo;
 }
 
 /// This class is derived from MachineFunctionInfo and contains private
 /// WebAssembly-specific information for each MachineFunction.
 class WebAssemblyFunctionInfo final : public MachineFunctionInfo {
-  const MachineFunction &MF;
+  const MachineFunction *MF;
 
   std::vector<MVT> Params;
   std::vector<MVT> Results;
   std::vector<MVT> Locals;
 
   /// A mapping from CodeGen vreg index to WebAssembly register number.
   std::vector<unsigned> WARegs;
 
class WebAssemblyFunctionInfo final : public MachineFunctionInfo {
 
   // Function properties.
   bool CFGStackified = false;
 
   // Catchpad unwind destination info for wasm EH.
   WasmEHFuncInfo *WasmEHInfo = nullptr;
 
 public:
-  explicit WebAssemblyFunctionInfo(MachineFunction &MF)
-      : MF(MF), WasmEHInfo(MF.getWasmEHFuncInfo()) {}
+  explicit WebAssemblyFunctionInfo(MachineFunction &MF_)
+      : MF(&MF_), WasmEHInfo(MF_.getWasmEHFuncInfo()) {}
   ~WebAssemblyFunctionInfo() override;
 
-  const MachineFunction &getMachineFunction() const { return MF; }
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
+
+  const MachineFunction &getMachineFunction() const { return *MF; }
 
   void initializeBaseYamlFields(const yaml::WebAssemblyFunctionInfo &YamlMFI);
 
   void addParam(MVT VT) { Params.push_back(VT); }
   const std::vector<MVT> &getParams() const { return Params; }
 
   void addResult(MVT VT) { Results.push_back(VT); }
   const std::vector<MVT> &getResults() const { return Results; }

llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp

 #include "WebAssemblySubtarget.h"
 #include "llvm/CodeGen/Analysis.h"
 #include "llvm/CodeGen/WasmEHFuncInfo.h"
 #include "llvm/Target/TargetMachine.h"
 using namespace llvm;
 
 WebAssemblyFunctionInfo::~WebAssemblyFunctionInfo() = default; // anchor.
 
+MachineFunctionInfo *WebAssemblyFunctionInfo::clone(
+    BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+    const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+    const {
+  WebAssemblyFunctionInfo *Clone =
+      DestMF.cloneInfo<WebAssemblyFunctionInfo>(*this);
+  Clone->MF = &DestMF;
+  return Clone;
+}
+
 void WebAssemblyFunctionInfo::initWARegs(MachineRegisterInfo &MRI) {
   assert(WARegs.empty());
   unsigned Reg = UnusedReg;
   WARegs.resize(MRI.getNumVirtRegs(), Reg);
 }
 
 void llvm::computeLegalValueVTs(const WebAssemblyTargetLowering &TLI,
                                 LLVMContext &Ctx, const DataLayout &DL,
void WebAssemblyFunctionInfo::initializeBaseYamlFields(
     const yaml::WebAssemblyFunctionInfo &YamlMFI) {
   CFGStackified = YamlMFI.CFGStackified;
   for (auto VT : YamlMFI.Params)
     addParam(WebAssembly::parseMVT(VT.Value));
   for (auto VT : YamlMFI.Results)
     addResult(WebAssembly::parseMVT(VT.Value));
   if (WasmEHInfo) {
     for (auto KV : YamlMFI.SrcToUnwindDest)
-      WasmEHInfo->setUnwindDest(MF.getBlockNumbered(KV.first),
-                                MF.getBlockNumbered(KV.second));
+      WasmEHInfo->setUnwindDest(MF->getBlockNumbered(KV.first),
+                                MF->getBlockNumbered(KV.second));
   }
 }

llvm/lib/Target/X86/X86MachineFunctionInfo.h

private:
   /// ForwardedMustTailRegParms - A list of virtual and physical registers
   /// that must be forwarded to every musttail call.
   SmallVector<ForwardedRegister, 1> ForwardedMustTailRegParms;
 
 public:
   X86MachineFunctionInfo() = default;
 
   explicit X86MachineFunctionInfo(MachineFunction &MF) {}
+  explicit X86MachineFunctionInfo(const X86MachineFunctionInfo &) = default;
+
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
 
   bool getForceFramePointer() const { return ForceFramePointer;}
   void setForceFramePointer(bool forceFP) { ForceFramePointer = forceFP; }
 
   bool getHasPushSequences() const { return HasPushSequences; }
   void setHasPushSequences(bool HasPush) { HasPushSequences = HasPush; }
 
   bool getRestoreBasePointer() const { return RestoreBasePointerOffset!=0; }

llvm/lib/Target/X86/X86MachineFunctionInfo.cpp

 //===-- X86MachineFunctionInfo.cpp - X86 machine function info ------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "X86MachineFunctionInfo.h"
 #include "X86RegisterInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 
 using namespace llvm;
 
+MachineFunctionInfo *X86MachineFunctionInfo::clone(
+    BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+    const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+    const {
+  return DestMF.cloneInfo<X86MachineFunctionInfo>(*this);
+}
+
 void X86MachineFunctionInfo::anchor() { }
 
 void X86MachineFunctionInfo::setRestoreBasePointer(const MachineFunction *MF) {
   if (!RestoreBasePointerOffset) {
     const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
       MF->getSubtarget().getRegisterInfo());
     unsigned SlotSize = RegInfo->getSlotSize();
     for (const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs();
          unsigned Reg = *CSR; ++CSR) {
       if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
         RestoreBasePointerOffset -= SlotSize;
     }
   }
 }
 

llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h

class XCoreFunctionInfo : public MachineFunctionInfo {
 
   virtual void anchor();
 
 public:
   XCoreFunctionInfo() = default;
 
   explicit XCoreFunctionInfo(MachineFunction &MF) {}
 
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override;
+
   ~XCoreFunctionInfo() override = default;
 
   void setVarArgsFrameIndex(int off) { VarArgsFrameIndex = off; }
   int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
 
   int createLRSpillSlot(MachineFunction &MF);
   bool hasLRSpillSlot() { return LRSpillSlotSet; }
   int getLRSpillSlot() const {

llvm/lib/Target/XCore/XCoreMachineFunctionInfo.cpp

 #include "XCoreInstrInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/Function.h"
 
 using namespace llvm;
 
 void XCoreFunctionInfo::anchor() { }
 
+MachineFunctionInfo *XCoreFunctionInfo::clone(
+    BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+    const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+    const {
+  return DestMF.cloneInfo<XCoreFunctionInfo>(*this);
+}
+
 bool XCoreFunctionInfo::isLargeFrame(const MachineFunction &MF) const {
   if (CachedEStackSize == -1) {
     CachedEStackSize = MF.getFrameInfo().estimateStackSize(MF);
   }
   // isLargeFrame() is used when deciding if spill slots should be added to
   // allow eliminateFrameIndex() to scavenge registers.
   // This is only required when there is no FP and offsets are greater than
   // ~256KB (~64Kwords). Thus only for code run on the emulator!

llvm/test/tools/llvm-reduce/mir/preserve-machine-function-info-amdgpu.mir

+# REQUIRES: amdgpu-registered-target
+# RUN: llvm-reduce -simplify-mir -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: FileCheck --check-prefix=RESULT %s < %t
+
+# CHECK-INTERESTINGNESS-COUNT-6: S_NOP
+
+# RESULT: name: func
+
+--- |
+  define void @func() {
+    ret void
+  }
+
+...
+
+# RESULT: machineFunctionInfo:
+# RESULT-NEXT: explicitKernArgSize: 108
+# RESULT-NEXT: maxKernArgAlign: 32
+# RESULT-NEXT: ldsSize:         256
+# RESULT-NEXT: gdsSize:         128
+# RESULT-NEXT: dynLDSAlign:     16
+# RESULT-NEXT: isEntryFunction: true
+# RESULT-NEXT: noSignedZerosFPMath: true
+# RESULT-NEXT: memoryBound:     true
+# RESULT-NEXT: waveLimiter:     true
+# RESULT-NEXT: hasSpilledSGPRs: true
+# RESULT-NEXT: hasSpilledVGPRs: true
+# RESULT-NEXT: scratchRSrcReg:  '$sgpr48_sgpr49_sgpr50_sgpr51'
+# RESULT-NEXT: frameOffsetReg:  '$sgpr44'
+# RESULT-NEXT: stackPtrOffsetReg: '$sgpr45'
+# RESULT-NEXT: bytesInStackArgArea: 112
+# RESULT-NEXT: returnsVoid:     false
+# RESULT-NEXT: argumentInfo:
+# RESULT-NEXT: privateSegmentBuffer: { reg: '$sgpr60_sgpr61_sgpr62_sgpr63' }
+# RESULT-NEXT: dispatchPtr:     { reg: '$sgpr6_sgpr7' }
+# RESULT-NEXT: queuePtr:        { reg: '$sgpr4_sgpr5' }
+# RESULT-NEXT: dispatchID:      { reg: '$sgpr12_sgpr13' }
+# RESULT-NEXT: workGroupIDX:    { reg: '$sgpr20' }
+# RESULT-NEXT: workGroupIDY:    { reg: '$sgpr19' }
+# RESULT-NEXT: workGroupIDZ:    { reg: '$sgpr18' }
+# RESULT-NEXT: implicitArgPtr:  { reg: '$sgpr10_sgpr11' }
+# RESULT-NEXT: workItemIDX:     { reg: '$vgpr34', mask: 1023 }
+# RESULT-NEXT: workItemIDY:     { reg: '$vgpr34', mask: 1047552 }
+# RESULT-NEXT: workItemIDZ:     { reg: '$vgpr34', mask: 1072693248 }
+# RESULT-NEXT: mode:
+# RESULT-NEXT: ieee:            false
+# RESULT-NEXT: dx10-clamp:      false
+# RESULT-NEXT: fp32-input-denormals: false
+# RESULT-NEXT: fp32-output-denormals: false
+# RESULT-NEXT: fp64-fp16-input-denormals: false
+# RESULT-NEXT: fp64-fp16-output-denormals: false
+# RESULT-NEXT: highBitsOf32BitAddress: 4276993775
+# RESULT-NEXT: occupancy:       8
+# RESULT-NEXT: wwmReservedRegs:
+# RESULT-NEXT: - '$vgpr2'
+# RESULT-NEXT: - '$vgpr3'
+# RESULT-NEXT: vgprForAGPRCopy: '$vgpr33'
+
+# RESULT: S_NOP 0, implicit $sgpr48_sgpr49_sgpr50_sgpr51
+# RESULT: S_NOP 0, implicit $vgpr33
+# RESULT: S_NOP 0, implicit $sgpr44
+# RESULT: S_NOP 0, implicit $sgpr45
+# RESULT: S_NOP 0, implicit $vgpr2
+# RESULT: S_NOP 0, implicit $vgpr3
+
+---
+name: func
+tracksRegLiveness: true
+machineFunctionInfo:
+  explicitKernArgSize: 108
+  maxKernArgAlign: 32
+  ldsSize:         256
+  gdsSize:         128
+  dynLDSAlign:     16
+  isEntryFunction: true
+  noSignedZerosFPMath: true
+  memoryBound:     true
+  waveLimiter:     true
+  hasSpilledSGPRs: true
+  hasSpilledVGPRs: true
+  scratchRSrcReg:  '$sgpr48_sgpr49_sgpr50_sgpr51'
+  frameOffsetReg:  '$sgpr44'
+  stackPtrOffsetReg: '$sgpr45'
+  bytesInStackArgArea: 112
+  returnsVoid:     false
+  argumentInfo:
+    privateSegmentBuffer: { reg: '$sgpr60_sgpr61_sgpr62_sgpr63' }
+    dispatchPtr:     { reg: '$sgpr6_sgpr7' }
+    queuePtr:        { reg: '$sgpr4_sgpr5' }
+    dispatchID:      { reg: '$sgpr12_sgpr13' }
+    workGroupIDX:    { reg: '$sgpr20' }
+    workGroupIDY:    { reg: '$sgpr19' }
+    workGroupIDZ:    { reg: '$sgpr18' }
+    implicitArgPtr:  { reg: '$sgpr10_sgpr11' }
+    workItemIDX:     { reg: '$vgpr34', mask: 1023 }
+    workItemIDY:     { reg: '$vgpr34', mask: 1047552 }
+    workItemIDZ:     { reg: '$vgpr34', mask: 1072693248 }
+  mode:
+    ieee:            false
+    dx10-clamp:      false
+    fp32-input-denormals: false
+    fp32-output-denormals: false
+    fp64-fp16-input-denormals: false
+    fp64-fp16-output-denormals: false
+  highBitsOf32BitAddress: 0xfeedbeef
+  occupancy:       8
+  wwmReservedRegs:
+    - '$vgpr2'
+    - '$vgpr3'
+  vgprForAGPRCopy: '$vgpr33'
+body:             |
+  bb.0:
+    S_WAITCNT 0
+    %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+
+    ; Test some register uses that are undef unless the reserved
+    ; registers are respected.
+    S_NOP 0, implicit $sgpr48_sgpr49_sgpr50_sgpr51
+    S_NOP 0, implicit $vgpr33
+    S_NOP 0, implicit $sgpr44
+    S_NOP 0, implicit $sgpr45
+    S_NOP 0, implicit $vgpr2
+    S_NOP 0, implicit $vgpr3
+    S_ENDPGM 0, implicit %0
+...

llvm/test/tools/llvm-reduce/mir/preserve-machine-function-info-riscv.mir

+# REQUIRES: riscv-registered-target
+# RUN: llvm-reduce -simplify-mir -mtriple=riscv64-- --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: FileCheck --check-prefix=RESULT %s < %t
+
+# CHECK-INTERESTINGNESS: ADDW
+
+# RESULT: name: func
+# RESULT: stack:
+# RESULT-NEXT: - { id: 0, offset: 16, size: 16, alignment: 8 }
+
+# RESULT: machineFunctionInfo:
+# RESULT-NEXT: varArgsFrameIndex: 4
+# RESULT-NEXT: varArgsSaveSize: 12
+
+# RESULT: $x10 = ADDW %stack.0, renamable $x10
+--- |
+  define i32 @func(i32 %arg) {
+    ret i32 undef
+  }
+
+...
+
+# Note the frame index value changes during printing/parsing, not the
+# clone.
+---
+name: func
+tracksRegLiveness: true
+machineFunctionInfo:
+  varArgsFrameIndex: 4
+  varArgsSaveSize: 12
+stack:
+  - { id: 4, offset: 16, size: 16, alignment: 8 }
+
+body:             |
+  bb.0:
+    liveins: $x10
+
+    renamable $x10 = ADDW %stack.4, renamable $x10
+    renamable $x10 = ADDIW killed renamable $x10, -4
+    PseudoRET implicit $x10
+
+...

llvm/tools/llvm-reduce/ReducerWorkItem.cpp

static std::unique_ptr<MachineFunction> cloneMF(MachineFunction *SrcMF) {
   MachineFrameInfo &DstMFI = DstMF->getFrameInfo();
 
   // Copy stack objects and other info
   cloneFrameInfo(DstMFI, SrcMFI, Src2DstMBB);
 
   // Remap the debug info frame index references.
   DstMF->VariableDbgInfos = SrcMF->VariableDbgInfos;
 
-  // FIXME: Need to clone MachineFunctionInfo, which may also depend on frame
-  // index and block mapping.
   // Clone virtual registers
   for (unsigned I = 0, E = SrcMRI->getNumVirtRegs(); I != E; ++I) {
     Register Reg = Register::index2VirtReg(I);
     Register NewReg = DstMRI->createIncompleteVirtualRegister(
       SrcMRI->getVRegName(Reg));
     assert(NewReg == Reg && "expected to preserve virtreg number");
 
     DstMRI->setRegClassOrRegBank(NewReg, SrcMRI->getRegClassOrRegBank(Reg));
if (!SrcMF->getLandingPads().empty() ||
       SrcMF->hasAnyWasmLandingPadIndex() ||
       SrcMF->hasAnyCallSiteLandingPad() ||
       SrcMF->hasAnyCallSiteLabel() ||
       !SrcMF->getCallSitesInfo().empty())
     report_fatal_error("cloning not implemented for machine function property");
 
   DstMF->setDebugInstrNumberingCount(SrcMF->DebugInstrNumberingCount);
 
+  if (!DstMF->cloneInfoFrom(*SrcMF, Src2DstMBB))
+    report_fatal_error("target does not implement MachineFunctionInfo cloning");
+
+  DstMRI->freezeReservedRegs(*DstMF);
+
   DstMF->verify(nullptr, "", /*AbortOnError=*/true);
   return DstMF;
 }
 
 std::unique_ptr<ReducerWorkItem> parseReducerWorkItem(StringRef Filename,
                                                       LLVMContext &Ctxt,
                                                       MachineModuleInfo *MMI) {
   auto MMM = std::make_unique<ReducerWorkItem>();