[Verifier] Add verifier for min-legal-vector-width

[efriedma]

I think this is missing a check: for call instructions, you need to check the min-legal-vector-width of both the call itself, and the function containing the call.

I'm still not really convinced this is the best approach, but maybe it's good enough.

llvm/lib/IR/Verifier.cpp

void Verifier::verifyFunctionAttrs(FunctionType *FT, AttributeList Attrs,
   AttributeSet RetAttrs = Attrs.getRetAttrs();
   for (Attribute RetAttr : RetAttrs)
     Assert(RetAttr.isStringAttribute() ||
            Attribute::canUseAsRetAttr(RetAttr.getKindAsEnum()),
            "Attribute '" + RetAttr.getAsString() +
                "' does not apply to function return values",
            V);
 
+  unsigned MaxParameterWidth = 0;
+  auto GetMaxParameterWidth = [&MaxParameterWidth](Type *Ty) {
+    if (Ty->isVectorTy()) {
+      if (auto *VT = dyn_cast<FixedVectorType>(Ty)) {
+        unsigned Size = VT->getPrimitiveSizeInBits().getFixedSize();
+        if (Size > MaxParameterWidth)
+          MaxParameterWidth = Size;
+      }
+    }
+  };
+  GetMaxParameterWidth(FT->getReturnType());
+
   verifyParameterAttrs(RetAttrs, FT->getReturnType(), V);
 
   // Verify parameter attributes.
   for (unsigned i = 0, e = FT->getNumParams(); i != e; ++i) {
     Type *Ty = FT->getParamType(i);
     AttributeSet ArgAttrs = Attrs.getParamAttrs(i);
 
     if (!IsIntrinsic) {
       Assert(!ArgAttrs.hasAttribute(Attribute::ImmArg),
              "immarg attribute only applies to intrinsics",V);
       if (!IsInlineAsm)
         Assert(!ArgAttrs.hasAttribute(Attribute::ElementType),
                "Attribute 'elementtype' can only be applied to intrinsics"
                " and inline asm.", V);
     }
 
     verifyParameterAttrs(ArgAttrs, Ty, V);
+    GetMaxParameterWidth(Ty);
 
     if (ArgAttrs.hasAttribute(Attribute::Nest)) {
       Assert(!SawNest, "More than one parameter has attribute nest!", V);
       SawNest = true;
     }
 
     if (ArgAttrs.hasAttribute(Attribute::Returned)) {
       Assert(!SawReturned, "More than one parameter has attribute returned!",
void Verifier::verifyFunctionAttrs(FunctionType *FT, AttributeList Attrs,
   }
 
   if (Attrs.hasFnAttr("frame-pointer")) {
     StringRef FP = Attrs.getFnAttr("frame-pointer").getValueAsString();
     if (FP != "all" && FP != "non-leaf" && FP != "none")
       CheckFailed("invalid value for 'frame-pointer' attribute: " + FP, V);
   }
 
+  if (Attrs.hasFnAttr("min-legal-vector-width")) {
+    StringRef Val =
+        Attrs.getFnAttr("min-legal-vector-width").getValueAsString();
+    unsigned Width;
+    if (Val.getAsInteger(0, Width) || Width < MaxParameterWidth)
+      CheckFailed(
+          "invalid value for 'min-legal-vector-width' attribute: " + Val, V);
+  }
+
   checkUnsignedBaseTenFuncAttr(Attrs, "patchable-function-prefix", V);
   checkUnsignedBaseTenFuncAttr(Attrs, "patchable-function-entry", V);
   checkUnsignedBaseTenFuncAttr(Attrs, "warn-stack-size", V);
 }
 
 void Verifier::verifyFunctionMetadata(
     ArrayRef<std::pair<unsigned, MDNode *>> MDs) {
   for (const auto &Pair : MDs) {

llvm/test/CodeGen/X86/avx512fp16-mov.ll

 for.body.preheader:                               ; preds = %entry
   store i8 0, i8* %c, align 1
   br label %for.end
 
 for.end:                                          ; preds = %for.body.preheader, %entry
   ret void
 }
 
-define <16 x i32> @pr52561(<16 x i32> %a, <16 x i32> %b) "min-legal-vector-width"="256" "prefer-vector-width"="256" nounwind {
+@res = external global <16 x i32>, align 64
+
+define void @pr52561(<8 x i32> %a1, <8 x i32> %a2, <8 x i32> %b1, <8 x i32> %b2) "min-legal-vector-width"="256" "prefer-vector-width"="256" nounwind {
 ; X64-LABEL: pr52561:
 ; X64:       # %bb.0:
 ; X64-NEXT:    vpbroadcastd {{.*#+}} ymm4 = [112,112,112,112,112,112,112,112]
+; X64-NEXT:    vpaddd %ymm4, %ymm3, %ymm3
+; X64-NEXT:    vpaddd %ymm3, %ymm1, %ymm1
 ; X64-NEXT:    vpaddd %ymm4, %ymm2, %ymm2
 ; X64-NEXT:    vpaddd %ymm2, %ymm0, %ymm0
-; X64-NEXT:    vpaddd %ymm4, %ymm3, %ymm2
-; X64-NEXT:    vpaddd %ymm2, %ymm1, %ymm1
-; X64-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
 ; X64-NEXT:    vpxor %xmm2, %xmm2, %xmm2
 ; X64-NEXT:    vmovsh %xmm0, %xmm2, %xmm0
+; X64-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; X64-NEXT:    movq res@GOTPCREL(%rip), %rax
+; X64-NEXT:    vmovdqa %ymm1, 32(%rax)
+; X64-NEXT:    vmovaps %ymm0, (%rax)
+; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: pr52561:
 ; X86:       # %bb.0:
 ; X86-NEXT:    pushl %ebp
 ; X86-NEXT:    movl %esp, %ebp
 ; X86-NEXT:    andl $-32, %esp
 ; X86-NEXT:    subl $32, %esp
 ; X86-NEXT:    vpaddd 8(%ebp), %ymm1, %ymm1
 ; X86-NEXT:    vpbroadcastd {{.*#+}} ymm3 = [112,112,112,112,112,112,112,112]
+; X86-NEXT:    vpaddd %ymm3, %ymm1, %ymm1
 ; X86-NEXT:    vpaddd %ymm3, %ymm2, %ymm2
 ; X86-NEXT:    vpaddd %ymm2, %ymm0, %ymm0
-; X86-NEXT:    vpaddd %ymm3, %ymm1, %ymm1
-; X86-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1
 ; X86-NEXT:    vpxor %xmm2, %xmm2, %xmm2
 ; X86-NEXT:    vmovsh %xmm0, %xmm2, %xmm0
+; X86-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1
+; X86-NEXT:    vmovdqa %ymm1, res+32
+; X86-NEXT:    vmovaps %ymm0, res
 ; X86-NEXT:    movl %ebp, %esp
 ; X86-NEXT:    popl %ebp
+; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
+  %a = shufflevector <8 x i32> %a1, <8 x i32> %a2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  %b = shufflevector <8 x i32> %b1, <8 x i32> %b2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %1 = add <16 x i32> %a, <i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112>
   %2 = add <16 x i32> %1, %b
   %3 = and <16 x i32> %2, <i32 65535, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 65535>
-  ret <16 x i32> %3
+  store <16 x i32> %3, <16 x i32> *@res, align 64
+  ret void
 }

llvm/test/CodeGen/X86/min-legal-vector-width.ll

 ; CHECK-NEXT:    vpblendmd (%rdi), %xmm1, %xmm0 {%k1}
 ; CHECK-NEXT:    retq
   %mask = icmp eq <4 x i32> %trigger, zeroinitializer
   %res = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %addr, i32 4, <4 x i1> %mask, <4 x i32> %dst)
   ret <4 x i32> %res
 }
 declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32, <4 x i1>, <4 x i32>)
 
-define <16 x i32> @trunc_v16i64_v16i32(<16 x i64>* %x) nounwind "min-legal-vector-width"="256" {
+@res = external global <16 x i32>, align 64
+
+define void @trunc_v16i64_v16i32(<16 x i64>* %x) nounwind "min-legal-vector-width"="256" {
 ; CHECK-LABEL: trunc_v16i64_v16i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vmovdqa (%rdi), %ymm0
 ; CHECK-NEXT:    vmovdqa 32(%rdi), %ymm1
 ; CHECK-NEXT:    vmovdqa 64(%rdi), %ymm2
 ; CHECK-NEXT:    vmovdqa 96(%rdi), %ymm3
-; CHECK-NEXT:    vpmovqd %ymm0, %xmm0
-; CHECK-NEXT:    vpmovqd %ymm1, %xmm1
-; CHECK-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
-; CHECK-NEXT:    vpmovqd %ymm2, %xmm1
-; CHECK-NEXT:    vpmovqd %ymm3, %xmm2
-; CHECK-NEXT:    vinserti128 $1, %xmm2, %ymm1, %ymm1
+; CHECK-NEXT:    movq res@GOTPCREL(%rip), %rax
+; CHECK-NEXT:    vpmovqd %ymm3, 48(%rax)
+; CHECK-NEXT:    vpmovqd %ymm2, 32(%rax)
+; CHECK-NEXT:    vpmovqd %ymm1, 16(%rax)
+; CHECK-NEXT:    vpmovqd %ymm0, (%rax)
+; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
   %a = load <16 x i64>, <16 x i64>* %x
   %b = trunc <16 x i64> %a to <16 x i32>
-  ret <16 x i32> %b
+  store <16 x i32> %b, <16 x i32> *@res, align 64
+  ret void
 }
 
 define <16 x i8> @trunc_v16i64_v16i8(<16 x i64>* %x) nounwind "min-legal-vector-width"="256" {
 ; CHECK-LABEL: trunc_v16i64_v16i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vmovdqa (%rdi), %ymm0
 ; CHECK-NEXT:    vmovdqa 32(%rdi), %ymm1
 ; CHECK-NEXT:    vmovdqa 64(%rdi), %ymm2

llvm/test/Transforms/PhaseOrdering/X86/horiz-math-inseltpoison.ll

;
   %vecext10 = extractelement <4 x float> %b, i32 2
   %vecext11 = extractelement <4 x float> %b, i32 3
   %add12 = fadd float %vecext10, %vecext11
   %vecinit13 = insertelement <4 x float> %vecinit9, float %add12, i32 3
   %shuffle = shufflevector <4 x float> %vecinit13, <4 x float> %a, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   ret <4 x float> %shuffle
 }
 
-define <8 x float> @hadd_reverse_v8f32(<8 x float> %a, <8 x float> %b) #0 {
+define <8 x float> @hadd_reverse_v8f32(<8 x float> %a, <8 x float> %b) #1 {
 ; CHECK-LABEL: @hadd_reverse_v8f32(
 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <8 x i32> <i32 7, i32 5, i32 15, i32 13, i32 3, i32 1, i32 11, i32 9>
 ; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x float> [[A]], <8 x float> [[B]], <8 x i32> <i32 6, i32 4, i32 14, i32 12, i32 2, i32 0, i32 10, i32 8>
 ; CHECK-NEXT:    [[TMP3:%.*]] = fadd <8 x float> [[TMP1]], [[TMP2]]
 ; CHECK-NEXT:    ret <8 x float> [[TMP3]]
 ;
   %shuffle = shufflevector <8 x float> %a, <8 x float> %a, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
   %shuffle1 = shufflevector <8 x float> %b, <8 x float> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
;
   %vecinit26 = insertelement <8 x float> %vecinit22, float %add25, i32 6
   %vecext27 = extractelement <8 x float> %shuffle1, i32 6
   %vecext28 = extractelement <8 x float> %shuffle1, i32 7
   %add29 = fadd float %vecext27, %vecext28
   %vecinit30 = insertelement <8 x float> %vecinit26, float %add29, i32 7
   ret <8 x float> %vecinit30
 }
 
-define <8 x float> @reverse_hadd_v8f32(<8 x float> %a, <8 x float> %b) #0 {
+define <8 x float> @reverse_hadd_v8f32(<8 x float> %a, <8 x float> %b) #1 {
 ; CHECK-LABEL: @reverse_hadd_v8f32(
 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
 ; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x float> [[A]], <8 x float> [[B]], <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
 ; CHECK-NEXT:    [[TMP3:%.*]] = fadd <8 x float> [[TMP1]], [[TMP2]]
 ; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <8 x float> [[TMP3]], <8 x float> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
 ; CHECK-NEXT:    ret <8 x float> [[SHUFFLE]]
 ;
   %vecext = extractelement <8 x float> %a, i32 0
;
   %vecext27 = extractelement <8 x float> %b, i32 7
   %add28 = fadd float %vecext26, %vecext27
   %vecinit29 = insertelement <8 x float> %vecinit25, float %add28, i32 7
   %shuffle = shufflevector <8 x float> %vecinit29, <8 x float> %a, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
   ret <8 x float> %shuffle
 }
 
 attributes #0 = { "min-legal-vector-width"="128" "target-cpu"="btver2" "target-features"="+avx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+sse4a,+ssse3" }
+attributes #1 = { "min-legal-vector-width"="256" "target-cpu"="btver2" "target-features"="+avx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+sse4a,+ssse3" }

llvm/test/Transforms/PhaseOrdering/X86/horiz-math.ll

;
   %vecext10 = extractelement <4 x float> %b, i32 2
   %vecext11 = extractelement <4 x float> %b, i32 3
   %add12 = fadd float %vecext10, %vecext11
   %vecinit13 = insertelement <4 x float> %vecinit9, float %add12, i32 3
   %shuffle = shufflevector <4 x float> %vecinit13, <4 x float> %a, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   ret <4 x float> %shuffle
 }
 
-define <8 x float> @hadd_reverse_v8f32(<8 x float> %a, <8 x float> %b) #0 {
+define <8 x float> @hadd_reverse_v8f32(<8 x float> %a, <8 x float> %b) #1 {
 ; CHECK-LABEL: @hadd_reverse_v8f32(
 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <8 x i32> <i32 7, i32 5, i32 15, i32 13, i32 3, i32 1, i32 11, i32 9>
 ; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x float> [[A]], <8 x float> [[B]], <8 x i32> <i32 6, i32 4, i32 14, i32 12, i32 2, i32 0, i32 10, i32 8>
 ; CHECK-NEXT:    [[TMP3:%.*]] = fadd <8 x float> [[TMP1]], [[TMP2]]
 ; CHECK-NEXT:    ret <8 x float> [[TMP3]]
 ;
   %shuffle = shufflevector <8 x float> %a, <8 x float> %a, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
   %shuffle1 = shufflevector <8 x float> %b, <8 x float> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
;
   %vecinit26 = insertelement <8 x float> %vecinit22, float %add25, i32 6
   %vecext27 = extractelement <8 x float> %shuffle1, i32 6
   %vecext28 = extractelement <8 x float> %shuffle1, i32 7
   %add29 = fadd float %vecext27, %vecext28
   %vecinit30 = insertelement <8 x float> %vecinit26, float %add29, i32 7
   ret <8 x float> %vecinit30
 }
 
-define <8 x float> @reverse_hadd_v8f32(<8 x float> %a, <8 x float> %b) #0 {
+define <8 x float> @reverse_hadd_v8f32(<8 x float> %a, <8 x float> %b) #1 {
 ; CHECK-LABEL: @reverse_hadd_v8f32(
 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
 ; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x float> [[A]], <8 x float> [[B]], <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
 ; CHECK-NEXT:    [[TMP3:%.*]] = fadd <8 x float> [[TMP1]], [[TMP2]]
 ; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <8 x float> [[TMP3]], <8 x float> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
 ; CHECK-NEXT:    ret <8 x float> [[SHUFFLE]]
 ;
   %vecext = extractelement <8 x float> %a, i32 0
;
   %vecext27 = extractelement <8 x float> %b, i32 7
   %add28 = fadd float %vecext26, %vecext27
   %vecinit29 = insertelement <8 x float> %vecinit25, float %add28, i32 7
   %shuffle = shufflevector <8 x float> %vecinit29, <8 x float> %a, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
   ret <8 x float> %shuffle
 }
 
 attributes #0 = { "min-legal-vector-width"="128" "target-cpu"="btver2" "target-features"="+avx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+sse4a,+ssse3" }
+attributes #1 = { "min-legal-vector-width"="256" "target-cpu"="btver2" "target-features"="+avx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+sse4a,+ssse3" }

llvm/test/Transforms/SampleProfile/merge-function-attributes.ll

 ; REQUIRES: x86_64-linux
 ; RUN: opt < %s -passes=sample-profile -sample-profile-file=%S/Inputs/merge-function-attributes.afdo -S | FileCheck %s
 
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-grtev4-linux-gnu"
 
+@res = external global <8 x double>, align 64
+
 ; Verify that yyy is inlined into xxx with the function attibutes properly merged.
-; CHECK:      define <8 x double> @xxx(){{.*}} #[[ATTRNO:[0-9]+]]
+; CHECK:      define void @xxx(){{.*}} #[[ATTRNO:[0-9]+]]
 ; CHECK-NEXT: call <8 x double> @llvm.x86.avx512.mask.rndscale.pd.512
-define <8 x double> @xxx() #0 !dbg !5 {
+define void @xxx() #0 !dbg !5 {
   %x = call <8 x double> @yyy(), !dbg !7
-  ret <8 x double> %x
+  store <8 x double> %x, <8 x double> *@res, align 64
+  ret void
 }
 
 define available_externally <8 x double> @yyy() #1 !dbg !8 {
   %y = call <8 x double> @llvm.x86.avx512.mask.rndscale.pd.512(<8 x double> zeroinitializer, i32 9, <8 x double> zeroinitializer, i8 -1, i32 4)
   ret <8 x double> %y
 }
 
 ; Function Attrs: nounwind readnone