[SDAG] try to canonicalize logical shift after bswap

[spatel]

Summary

When shifting by a byte-multiple:
bswap (shl X, C) --> lshr (bswap X), C
bswap (lshr X, C) --> shl (bswap X), C

This is the backend version of D122010 and an alternative suggested in D120648. There's an extra check to make sure the shift amount is valid that was not in the rough draft.

I'm not sure if there is a larger motivating case for RISCV (bug report?), but the ARM diffs show a benefit from having a late version of the transform (because we do not combine the loads in IR).

[RKSimon]

As bswap nodes tend to be generated in the DAG via load combines I agree we need this fold here as well as instcombine

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

9756

Add comment describing the fold

[spatel]

Added code comment to describe the transform.

[RKSimon]

LGTM - cheers

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (ShAmt && ShAmt->getAPIntValue().ult(BW) &&
         Res = DAG.getNode(ISD::SHL, DL, VT, Res,
                           DAG.getConstant(NewShAmt, DL, getShiftAmountTy(VT)));
       Res = DAG.getZExtOrTrunc(Res, DL, HalfVT);
       Res = DAG.getNode(ISD::BSWAP, DL, HalfVT, Res);
       return DAG.getZExtOrTrunc(Res, DL, VT);
     }
   }
 
+  // Try to canonicalize bswap-of-logical-shift-by-8-bit-multiple as
+  // inverse-shift-of-bswap:
+  // bswap (X u<< C) --> (bswap X) u>> C
+  // bswap (X u>> C) --> (bswap X) u<< C
+  if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
+      N0.hasOneUse()) {
+    auto *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
+    if (ShAmt && ShAmt->getAPIntValue().ult(BW) &&
+        ShAmt->getZExtValue() % 8 == 0) {
+      SDValue NewSwap = DAG.getNode(ISD::BSWAP, DL, VT, N0.getOperand(0));
+      unsigned InverseShift = N0.getOpcode() == ISD::SHL ? ISD::SRL : ISD::SHL;
+      return DAG.getNode(InverseShift, DL, VT, NewSwap, N0.getOperand(1));
+    }
+  }
+
   return SDValue();
 }
 
 SDValue DAGCombiner::visitBITREVERSE(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   EVT VT = N->getValueType(0);
 
   // fold (bitreverse c1) -> c2

llvm/test/CodeGen/AArch64/arm64-rev.ll

 
 ; Reduced regression from D120192
 define void @test_bswap32_narrow(i32* %p0, i16* %p1) nounwind {
 ; CHECK-LABEL: test_bswap32_narrow:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    ldrh w8, [x0, #2]
 ; CHECK-NEXT:    mov x19, x1
-; CHECK-NEXT:    lsl w8, w8, #16
-; CHECK-NEXT:    rev w0, w8
+; CHECK-NEXT:    rev16 w0, w8
 ; CHECK-NEXT:    bl gid_tbl_len
 ; CHECK-NEXT:    strh wzr, [x19]
 ; CHECK-NEXT:    ldp x30, x19, [sp], #16 // 16-byte Folded Reload
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_bswap32_narrow:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    stp x30, x19, [sp, #-16]! // 16-byte Folded Spill

llvm/test/CodeGen/AArch64/load-combine-big-endian.ll

; CHECK-NEXT:    ret
   ret i32 %tmp48
 }
 ; i8* p; // p is 2 byte aligned
 ; (i32) p[0] | ((i32) p[1] << 8)
 define i32 @zext_load_i32_by_i8(i32* %arg) {
 ; CHECK-LABEL: zext_load_i32_by_i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldrh w8, [x0]
-; CHECK-NEXT:    lsl w8, w8, #16
-; CHECK-NEXT:    rev w0, w8
+; CHECK-NEXT:    rev16 w0, w8
 ; CHECK-NEXT:    ret
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
   %tmp2 = load i8, i8* %tmp1, align 2
   %tmp3 = zext i8 %tmp2 to i32
   %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 1
   %tmp5 = load i8, i8* %tmp4, align 1
   %tmp6 = zext i8 %tmp5 to i32

llvm/test/CodeGen/AArch64/load-combine.ll

; CHECK-NEXT:    ret
   ret i32 %tmp8
 }
 ; i8* p; // p is 2 byte aligned
 ; (i32) p[1] | ((i32) p[0] << 8)
 define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
 ; CHECK-LABEL: zext_load_i32_by_i8_bswap:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldrh w8, [x0]
-; CHECK-NEXT:    lsl w8, w8, #16
-; CHECK-NEXT:    rev w0, w8
+; CHECK-NEXT:    rev16 w0, w8
 ; CHECK-NEXT:    ret
 
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1
   %tmp2 = load i8, i8* %tmp1, align 1
   %tmp3 = zext i8 %tmp2 to i32
   %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 0
   %tmp5 = load i8, i8* %tmp4, align 2

llvm/test/CodeGen/ARM/load-combine-big-endian.ll

 ; CHECK-NEXT:    ldrb r1, [r0]
 ; CHECK-NEXT:    ldrb r0, [r0, #1]
 ; CHECK-NEXT:    orr r0, r1, r0, lsl #8
 ; CHECK-NEXT:    mov pc, lr
 ;
 ; CHECK-ARMv6-LABEL: zext_load_i32_by_i8:
 ; CHECK-ARMv6:       @ %bb.0:
 ; CHECK-ARMv6-NEXT:    ldrh r0, [r0]
-; CHECK-ARMv6-NEXT:    lsl r0, r0, #16
-; CHECK-ARMv6-NEXT:    rev r0, r0
+; CHECK-ARMv6-NEXT:    rev16 r0, r0
 ; CHECK-ARMv6-NEXT:    bx lr
 ;
 ; CHECK-THUMBv6-LABEL: zext_load_i32_by_i8:
 ; CHECK-THUMBv6:       @ %bb.0:
 ; CHECK-THUMBv6-NEXT:    ldrh r0, [r0]
-; CHECK-THUMBv6-NEXT:    lsls r0, r0, #16
-; CHECK-THUMBv6-NEXT:    rev r0, r0
+; CHECK-THUMBv6-NEXT:    rev16 r0, r0
 ; CHECK-THUMBv6-NEXT:    bx lr
 ;
 ; CHECK-THUMBv7-LABEL: zext_load_i32_by_i8:
 ; CHECK-THUMBv7:       @ %bb.0:
 ; CHECK-THUMBv7-NEXT:    ldrh r0, [r0]
-; CHECK-THUMBv7-NEXT:    lsls r0, r0, #16
-; CHECK-THUMBv7-NEXT:    rev r0, r0
+; CHECK-THUMBv7-NEXT:    rev16 r0, r0
 ; CHECK-THUMBv7-NEXT:    bx lr
 
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
   %tmp2 = load i8, i8* %tmp1, align 2
   %tmp3 = zext i8 %tmp2 to i32
   %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 1
   %tmp5 = load i8, i8* %tmp4, align 1

llvm/test/CodeGen/ARM/load-combine.ll

 ; CHECK-NEXT:    ldrb r1, [r0]
 ; CHECK-NEXT:    ldrb r0, [r0, #1]
 ; CHECK-NEXT:    orr r0, r0, r1, lsl #8
 ; CHECK-NEXT:    mov pc, lr
 ;
 ; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_bswap:
 ; CHECK-ARMv6:       @ %bb.0:
 ; CHECK-ARMv6-NEXT:    ldrh r0, [r0]
-; CHECK-ARMv6-NEXT:    lsl r0, r0, #16
-; CHECK-ARMv6-NEXT:    rev r0, r0
+; CHECK-ARMv6-NEXT:    rev16 r0, r0
 ; CHECK-ARMv6-NEXT:    bx lr
 ;
 ; CHECK-THUMBv6-LABEL: zext_load_i32_by_i8_bswap:
 ; CHECK-THUMBv6:       @ %bb.0:
 ; CHECK-THUMBv6-NEXT:    ldrh r0, [r0]
-; CHECK-THUMBv6-NEXT:    lsls r0, r0, #16
-; CHECK-THUMBv6-NEXT:    rev r0, r0
+; CHECK-THUMBv6-NEXT:    rev16 r0, r0
 ; CHECK-THUMBv6-NEXT:    bx lr
 ;
 ; CHECK-THUMBv7-LABEL: zext_load_i32_by_i8_bswap:
 ; CHECK-THUMBv7:       @ %bb.0:
 ; CHECK-THUMBv7-NEXT:    ldrh r0, [r0]
-; CHECK-THUMBv7-NEXT:    lsls r0, r0, #16
-; CHECK-THUMBv7-NEXT:    rev r0, r0
+; CHECK-THUMBv7-NEXT:    rev16 r0, r0
 ; CHECK-THUMBv7-NEXT:    bx lr
 
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1
   %tmp2 = load i8, i8* %tmp1, align 1
   %tmp3 = zext i8 %tmp2 to i32
   %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 0
   %tmp5 = load i8, i8* %tmp4, align 2

llvm/test/CodeGen/RISCV/bswap-shift.ll

; RV64ZB-NEXT:    ret
     %2 = lshr i16 %1, 7
     %3 = call i16 @llvm.bswap.i16(i16 %2)
     ret i16 %3
 }
 
 define i16 @test_bswap_srli_8_bswap_i16(i16 %a) nounwind {
 ; RV32ZB-LABEL: test_bswap_srli_8_bswap_i16:
 ; RV32ZB:       # %bb.0:
-; RV32ZB-NEXT:    andi a0, a0, 255
-; RV32ZB-NEXT:    rev8 a0, a0
-; RV32ZB-NEXT:    srli a0, a0, 16
+; RV32ZB-NEXT:    slli a0, a0, 8
 ; RV32ZB-NEXT:    ret
 ;
 ; RV64ZB-LABEL: test_bswap_srli_8_bswap_i16:
 ; RV64ZB:       # %bb.0:
-; RV64ZB-NEXT:    andi a0, a0, 255
-; RV64ZB-NEXT:    rev8 a0, a0
-; RV64ZB-NEXT:    srli a0, a0, 48
+; RV64ZB-NEXT:    slli a0, a0, 8
 ; RV64ZB-NEXT:    ret
     %1 = call i16 @llvm.bswap.i16(i16 %a)
     %2 = lshr i16 %1, 8
     %3 = call i16 @llvm.bswap.i16(i16 %2)
     ret i16 %3
 }
 
 define i32 @test_bswap_srli_8_bswap_i32(i32 %a) nounwind {
 ; RV32ZB-LABEL: test_bswap_srli_8_bswap_i32:
 ; RV32ZB:       # %bb.0:
-; RV32ZB-NEXT:    rev8 a0, a0
-; RV32ZB-NEXT:    srli a0, a0, 8
-; RV32ZB-NEXT:    rev8 a0, a0
+; RV32ZB-NEXT:    slli a0, a0, 8
 ; RV32ZB-NEXT:    ret
 ;
 ; RV64ZB-LABEL: test_bswap_srli_8_bswap_i32:
 ; RV64ZB:       # %bb.0:
-; RV64ZB-NEXT:    rev8 a0, a0
-; RV64ZB-NEXT:    srli a0, a0, 40
-; RV64ZB-NEXT:    rev8 a0, a0
-; RV64ZB-NEXT:    srli a0, a0, 32
+; RV64ZB-NEXT:    slliw a0, a0, 8
 ; RV64ZB-NEXT:    ret
     %1 = call i32 @llvm.bswap.i32(i32 %a)
     %2 = lshr i32 %1, 8
     %3 = call i32 @llvm.bswap.i32(i32 %2)
     ret i32 %3
 }
 
 define i32 @test_bswap_srli_16_bswap_i32(i32 %a) nounwind {
 ; RV32ZB-LABEL: test_bswap_srli_16_bswap_i32:
 ; RV32ZB:       # %bb.0:
-; RV32ZB-NEXT:    rev8 a0, a0
-; RV32ZB-NEXT:    srli a0, a0, 16
-; RV32ZB-NEXT:    rev8 a0, a0
+; RV32ZB-NEXT:    slli a0, a0, 16
 ; RV32ZB-NEXT:    ret
 ;
 ; RV64ZB-LABEL: test_bswap_srli_16_bswap_i32:
 ; RV64ZB:       # %bb.0:
-; RV64ZB-NEXT:    rev8 a0, a0
-; RV64ZB-NEXT:    srli a0, a0, 48
-; RV64ZB-NEXT:    rev8 a0, a0
-; RV64ZB-NEXT:    srli a0, a0, 32
+; RV64ZB-NEXT:    slliw a0, a0, 16
 ; RV64ZB-NEXT:    ret
     %1 = call i32 @llvm.bswap.i32(i32 %a)
     %2 = lshr i32 %1, 16
     %3 = call i32 @llvm.bswap.i32(i32 %2)
     ret i32 %3
 }
 
 define i32 @test_bswap_srli_24_bswap_i32(i32 %a) nounwind {
 ; RV32ZB-LABEL: test_bswap_srli_24_bswap_i32:
 ; RV32ZB:       # %bb.0:
-; RV32ZB-NEXT:    andi a0, a0, 255
-; RV32ZB-NEXT:    rev8 a0, a0
+; RV32ZB-NEXT:    slli a0, a0, 24
 ; RV32ZB-NEXT:    ret
 ;
 ; RV64ZB-LABEL: test_bswap_srli_24_bswap_i32:
 ; RV64ZB:       # %bb.0:
-; RV64ZB-NEXT:    andi a0, a0, 255
-; RV64ZB-NEXT:    rev8 a0, a0
-; RV64ZB-NEXT:    srli a0, a0, 32
+; RV64ZB-NEXT:    slliw a0, a0, 24
 ; RV64ZB-NEXT:    ret
     %1 = call i32 @llvm.bswap.i32(i32 %a)
     %2 = lshr i32 %1, 24
     %3 = call i32 @llvm.bswap.i32(i32 %2)
     ret i32 %3
 }
 
 define i64 @test_bswap_srli_48_bswap_i64(i64 %a) nounwind {
 ; RV32ZB-LABEL: test_bswap_srli_48_bswap_i64:
 ; RV32ZB:       # %bb.0:
-; RV32ZB-NEXT:    rev8 a0, a0
-; RV32ZB-NEXT:    srli a0, a0, 16
-; RV32ZB-NEXT:    rev8 a1, a0
+; RV32ZB-NEXT:    slli a1, a0, 16
 ; RV32ZB-NEXT:    li a0, 0
 ; RV32ZB-NEXT:    ret
 ;
 ; RV64ZB-LABEL: test_bswap_srli_48_bswap_i64:
 ; RV64ZB:       # %bb.0:
-; RV64ZB-NEXT:    rev8 a0, a0
-; RV64ZB-NEXT:    srli a0, a0, 48
-; RV64ZB-NEXT:    rev8 a0, a0
+; RV64ZB-NEXT:    slli a0, a0, 48
 ; RV64ZB-NEXT:    ret
     %1 = call i64 @llvm.bswap.i64(i64 %a)
     %2 = lshr i64 %1, 48
     %3 = call i64 @llvm.bswap.i64(i64 %2)
     ret i64 %3
 }
 
 define i16 @test_bswap_shli_7_bswap_i16(i16 %a) nounwind {
; RV64ZB-NEXT:    ret
     %2 = shl i16 %1, 7
     %3 = call i16 @llvm.bswap.i16(i16 %2)
     ret i16 %3
 }
 
 define i16 @test_bswap_shli_8_bswap_i16(i16 %a) nounwind {
 ; RV32ZB-LABEL: test_bswap_shli_8_bswap_i16:
 ; RV32ZB:       # %bb.0:
-; RV32ZB-NEXT:    andi a0, a0, -256
-; RV32ZB-NEXT:    rev8 a0, a0
-; RV32ZB-NEXT:    srli a0, a0, 16
+; RV32ZB-NEXT:    slli a0, a0, 16
+; RV32ZB-NEXT:    srli a0, a0, 24
 ; RV32ZB-NEXT:    ret
 ;
 ; RV64ZB-LABEL: test_bswap_shli_8_bswap_i16:
 ; RV64ZB:       # %bb.0:
-; RV64ZB-NEXT:    andi a0, a0, -256
-; RV64ZB-NEXT:    rev8 a0, a0
-; RV64ZB-NEXT:    srli a0, a0, 48
+; RV64ZB-NEXT:    slli a0, a0, 48
+; RV64ZB-NEXT:    srli a0, a0, 56
 ; RV64ZB-NEXT:    ret
     %1 = call i16 @llvm.bswap.i16(i16 %a)
     %2 = shl i16 %1, 8
     %3 = call i16 @llvm.bswap.i16(i16 %2)
     ret i16 %3
 }
 
 define i32 @test_bswap_shli_8_bswap_i32(i32 %a) nounwind {
 ; RV32ZB-LABEL: test_bswap_shli_8_bswap_i32:
 ; RV32ZB:       # %bb.0:
-; RV32ZB-NEXT:    rev8 a0, a0
-; RV32ZB-NEXT:    slli a0, a0, 8
-; RV32ZB-NEXT:    rev8 a0, a0
+; RV32ZB-NEXT:    srli a0, a0, 8
 ; RV32ZB-NEXT:    ret
 ;
 ; RV64ZB-LABEL: test_bswap_shli_8_bswap_i32:
 ; RV64ZB:       # %bb.0:
-; RV64ZB-NEXT:    rev8 a0, a0
-; RV64ZB-NEXT:    srli a0, a0, 24
-; RV64ZB-NEXT:    andi a0, a0, -256
-; RV64ZB-NEXT:    rev8 a0, a0
-; RV64ZB-NEXT:    srli a0, a0, 32
+; RV64ZB-NEXT:    srliw a0, a0, 8
 ; RV64ZB-NEXT:    ret
     %1 = call i32 @llvm.bswap.i32(i32 %a)
     %2 = shl i32 %1, 8
     %3 = call i32 @llvm.bswap.i32(i32 %2)
     ret i32 %3
 }
 
 define i32 @test_bswap_shli_16_bswap_i32(i32 %a) nounwind {
 ; RV32ZB-LABEL: test_bswap_shli_16_bswap_i32:
 ; RV32ZB:       # %bb.0:
-; RV32ZB-NEXT:    rev8 a0, a0
-; RV32ZB-NEXT:    slli a0, a0, 16
-; RV32ZB-NEXT:    rev8 a0, a0
+; RV32ZB-NEXT:    srli a0, a0, 16
 ; RV32ZB-NEXT:    ret
 ;
 ; RV64ZB-LABEL: test_bswap_shli_16_bswap_i32:
 ; RV64ZB:       # %bb.0:
-; RV64ZB-NEXT:    rev8 a0, a0
-; RV64ZB-NEXT:    srli a0, a0, 32
-; RV64ZB-NEXT:    slli a0, a0, 16
-; RV64ZB-NEXT:    rev8 a0, a0
-; RV64ZB-NEXT:    srli a0, a0, 32
+; RV64ZB-NEXT:    srliw a0, a0, 16
 ; RV64ZB-NEXT:    ret
     %1 = call i32 @llvm.bswap.i32(i32 %a)
     %2 = shl i32 %1, 16
     %3 = call i32 @llvm.bswap.i32(i32 %2)
     ret i32 %3
 }
 
 define i32 @test_bswap_shli_24_bswap_i32(i32 %a) nounwind {
 ; RV32ZB-LABEL: test_bswap_shli_24_bswap_i32:
 ; RV32ZB:       # %bb.0:
-; RV32ZB-NEXT:    lui a1, 1044480
-; RV32ZB-NEXT:    and a0, a0, a1
-; RV32ZB-NEXT:    rev8 a0, a0
+; RV32ZB-NEXT:    srli a0, a0, 24
 ; RV32ZB-NEXT:    ret
 ;
 ; RV64ZB-LABEL: test_bswap_shli_24_bswap_i32:
 ; RV64ZB:       # %bb.0:
-; RV64ZB-NEXT:    lui a1, 1044480
-; RV64ZB-NEXT:    and a0, a0, a1
-; RV64ZB-NEXT:    rev8 a0, a0
-; RV64ZB-NEXT:    srli a0, a0, 32
+; RV64ZB-NEXT:    srliw a0, a0, 24
 ; RV64ZB-NEXT:    ret
     %1 = call i32 @llvm.bswap.i32(i32 %a)
     %2 = shl i32 %1, 24
     %3 = call i32 @llvm.bswap.i32(i32 %2)
     ret i32 %3
 }
 
 define i64 @test_bswap_shli_48_bswap_i64(i64 %a) nounwind {
 ; RV32ZB-LABEL: test_bswap_shli_48_bswap_i64:
 ; RV32ZB:       # %bb.0:
-; RV32ZB-NEXT:    rev8 a0, a1
-; RV32ZB-NEXT:    slli a0, a0, 16
-; RV32ZB-NEXT:    rev8 a0, a0
+; RV32ZB-NEXT:    srli a0, a1, 16
 ; RV32ZB-NEXT:    li a1, 0
 ; RV32ZB-NEXT:    ret
 ;
 ; RV64ZB-LABEL: test_bswap_shli_48_bswap_i64:
 ; RV64ZB:       # %bb.0:
-; RV64ZB-NEXT:    rev8 a0, a0
-; RV64ZB-NEXT:    slli a0, a0, 48
-; RV64ZB-NEXT:    rev8 a0, a0
+; RV64ZB-NEXT:    srli a0, a0, 48
 ; RV64ZB-NEXT:    ret
     %1 = call i64 @llvm.bswap.i64(i64 %a)
     %2 = shl i64 %1, 48
     %3 = call i64 @llvm.bswap.i64(i64 %2)
     ret i64 %3
 }

llvm/test/CodeGen/X86/combine-bswap.ll

 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    retq
   %b = call i32 @llvm.bswap.i32(i32 %a0)
   %c = call i32 @llvm.bswap.i32(i32 %b)
   ret i32 %c
 }
 
-; TODO: fold (bswap(srl (bswap c), x)) -> (shl c, x)
 define i16 @test_bswap_srli_8_bswap_i16(i16 %a) nounwind {
 ; X86-LABEL: test_bswap_srli_8_bswap_i16:
 ; X86:       # %bb.0:
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    rolw $8, %ax
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    shll $8, %eax
 ; X86-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_bswap_srli_8_bswap_i16:
 ; X64:       # %bb.0:
-; X64-NEXT:    movzbl %dil, %eax
-; X64-NEXT:    rolw $8, %ax
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    shll $8, %eax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
     %1 = call i16 @llvm.bswap.i16(i16 %a)
     %2 = lshr i16 %1, 8
     %3 = call i16 @llvm.bswap.i16(i16 %2)
     ret i16 %3
 }
 
 define i32 @test_bswap_srli_8_bswap_i32(i32 %a) nounwind {
 ; X86-LABEL: test_bswap_srli_8_bswap_i32:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    bswapl %eax
-; X86-NEXT:    shrl $8, %eax
-; X86-NEXT:    bswapl %eax
+; X86-NEXT:    shll $8, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_bswap_srli_8_bswap_i32:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    bswapl %eax
-; X64-NEXT:    shrl $8, %eax
-; X64-NEXT:    bswapl %eax
+; X64-NEXT:    shll $8, %eax
 ; X64-NEXT:    retq
     %1 = call i32 @llvm.bswap.i32(i32 %a)
     %2 = lshr i32 %1, 8
     %3 = call i32 @llvm.bswap.i32(i32 %2)
     ret i32 %3
 }
 
 define i64 @test_bswap_srli_16_bswap_i64(i64 %a) nounwind {
 ; X86-LABEL: test_bswap_srli_16_bswap_i64:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT:    bswapl %edx
-; X86-NEXT:    bswapl %eax
-; X86-NEXT:    shrdl $16, %eax, %edx
-; X86-NEXT:    shrl $16, %eax
-; X86-NEXT:    bswapl %edx
-; X86-NEXT:    bswapl %eax
+; X86-NEXT:    shll $16, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_bswap_srli_16_bswap_i64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
-; X64-NEXT:    bswapq %rax
-; X64-NEXT:    shrq $16, %rax
-; X64-NEXT:    bswapq %rax
+; X64-NEXT:    shlq $16, %rax
 ; X64-NEXT:    retq
     %1 = call i64 @llvm.bswap.i64(i64 %a)
     %2 = lshr i64 %1, 16
     %3 = call i64 @llvm.bswap.i64(i64 %2)
     ret i64 %3
 }
 
-; TODO: fold (bswap(shl (bswap c), x)) -> (srl c, x)
 define i16 @test_bswap_shli_8_bswap_i16(i16 %a) nounwind {
 ; X86-LABEL: test_bswap_shli_8_bswap_i16:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    shll $8, %eax
-; X86-NEXT:    rolw $8, %ax
 ; X86-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_bswap_shli_8_bswap_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    andl $65280, %eax # imm = 0xFF00
-; X64-NEXT:    rolw $8, %ax
+; X64-NEXT:    movzbl %ah, %eax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
     %1 = call i16 @llvm.bswap.i16(i16 %a)
     %2 = shl i16 %1, 8
     %3 = call i16 @llvm.bswap.i16(i16 %2)
     ret i16 %3
 }
 
 define i32 @test_bswap_shli_8_bswap_i32(i32 %a) nounwind {
 ; X86-LABEL: test_bswap_shli_8_bswap_i32:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    bswapl %eax
-; X86-NEXT:    shll $8, %eax
-; X86-NEXT:    bswapl %eax
+; X86-NEXT:    shrl $8, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_bswap_shli_8_bswap_i32:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    bswapl %eax
-; X64-NEXT:    shll $8, %eax
-; X64-NEXT:    bswapl %eax
+; X64-NEXT:    shrl $8, %eax
 ; X64-NEXT:    retq
     %1 = call i32 @llvm.bswap.i32(i32 %a)
     %2 = shl i32 %1, 8
     %3 = call i32 @llvm.bswap.i32(i32 %2)
     ret i32 %3
 }
 
 define i64 @test_bswap_shli_16_bswap_i64(i64 %a) nounwind {
 ; X86-LABEL: test_bswap_shli_16_bswap_i64:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT:    bswapl %ecx
-; X86-NEXT:    bswapl %eax
-; X86-NEXT:    shldl $16, %ecx, %eax
-; X86-NEXT:    bswapl %eax
-; X86-NEXT:    rolw $8, %cx
-; X86-NEXT:    movzwl %cx, %edx
+; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_bswap_shli_16_bswap_i64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
-; X64-NEXT:    bswapq %rax
-; X64-NEXT:    shlq $16, %rax
-; X64-NEXT:    bswapq %rax
+; X64-NEXT:    shrq $16, %rax
 ; X64-NEXT:    retq
     %1 = call i64 @llvm.bswap.i64(i64 %a)
     %2 = shl i64 %1, 16
     %3 = call i64 @llvm.bswap.i64(i64 %2)
     ret i64 %3
 }
 
 define i32 @test_demandedbits_bswap(i32 %a0) nounwind {